1 /*
2 * Copyright 2021-2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
17 * Note: The clock could not be set when it is being used as system clock.
18 * In default out of reset, the CPU is clocked from FIRC,
19 * so before setting FIRC, change to use another avaliable clock source.
20 *
21 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
22 *
23 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
24 * Wait until the system clock source is changed to target source.
25 *
26 */
27
28 /* clang-format off */
29 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
30 !!GlobalInfo
31 product: Clocks v11.0
32 processor: KW45B41Z83xxxA
33 package_id: KW45B41Z83AFTA
34 mcu_data: ksdk2_0
35 processor_version: 14.0.0
36 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
37 /* clang-format on */
38
39 #include "fsl_ccm32k.h"
40 #include "fsl_spc.h"
41 #include "clock_config.h"
42
43 /*******************************************************************************
44 * Definitions
45 ******************************************************************************/
46
47 /*******************************************************************************
48 * Variables
49 ******************************************************************************/
50
51 /*******************************************************************************
52 * Code
53 ******************************************************************************/
54 /*FUNCTION**********************************************************************
55 *
56 * Function Name : CLOCK_CONFIG_SetScgOutSel
57 * Description : Set the SCG clock out select (CLKOUTSEL).
58 * Param setting : The selected clock source.
59 *
60 *END**************************************************************************/
CLOCK_CONFIG_SetScgOutSel(clock_clkout_src_t setting)61 static void CLOCK_CONFIG_SetScgOutSel(clock_clkout_src_t setting)
62 {
63 SCG0->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
64 }
65
66 /*FUNCTION**********************************************************************
67 *
68 * Function Name : CLOCK_CONFIG_FircSafeConfig
69 * Description : This function is used to safely configure FIRC clock.
70 * In default out of reset, the CPU is clocked from FIRC.
71 * Before setting FIRC, change to use SIRC as system clock,
72 * then configure FIRC.
73 * Param fircConfig : FIRC configuration.
74 *
75 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)76 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
77 {
78 scg_sys_clk_config_t curConfig;
79 scg_sys_clk_config_t sysClkSafeConfigSource = {
80 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow clock divider */
81 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core clock divider */
82 .src = (uint32_t)kSCG_SysClkSrcSirc, /* System clock source */
83 };
84 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
85 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
86 /* Wait for clock source switch finished */
87 do
88 {
89 CLOCK_GetCurSysClkConfig(&curConfig);
90 } while (curConfig.src != sysClkSafeConfigSource.src);
91
92 /* Init Firc */
93 (void)CLOCK_InitFirc(fircConfig);
94 }
95
96 /*******************************************************************************
97 ************************ BOARD_InitBootClocks function ************************
98 ******************************************************************************/
BOARD_InitBootClocks(void)99 void BOARD_InitBootClocks(void)
100 {
101 BOARD_BootClockRUN();
102 }
103
104 /*******************************************************************************
105 ********************** Configuration BOARD_BootClockRUN ***********************
106 ******************************************************************************/
107 /* clang-format off */
108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
109 !!Configuration
110 name: BOARD_BootClockRUN
111 called_from_default_init: true
112 outputs:
113 - {id: BUS_CLK.outFreq, value: 96 MHz}
114 - {id: CPU_CLK.outFreq, value: 96 MHz}
115 - {id: FIRC_CLK.outFreq, value: 96 MHz}
116 - {id: FRO16K_CLK.outFreq, value: 16 kHz}
117 - {id: RADIO_FRO192M_CLK.outFreq, value: 32 MHz}
118 - {id: RADIO_FRO192M_FRODIV_CLK.outFreq, value: 16 MHz}
119 - {id: ROSC_CLK.outFreq, value: 32.768 kHz}
120 - {id: SCG.FIRC_EXT_REF_TRIM_CLK.outFreq, value: 1 MHz}
121 - {id: SCGCLKOUT_CLK.outFreq, value: 24 MHz}
122 - {id: SIRC_CLK.outFreq, value: 6 MHz}
123 - {id: SLOW_CLK.outFreq, value: 24 MHz}
124 - {id: SOSC_CLK.outFreq, value: 32 MHz}
125 - {id: System_clock.outFreq, value: 96 MHz}
126 settings:
127 - {id: VDDCore, value: voltage_1v1}
128 - {id: CCM32K.CCM32K_32K_SEL.sel, value: CCM32K.OSC_32K}
129 - {id: CCM32K_FRO32K_CTRL_FRO_EN_CFG, value: Disabled}
130 - {id: CCM32K_OSC32K_CTRL_CAP_SEL_EN_CFG, value: Enabled}
131 - {id: CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL_CFG, value: 8PF}
132 - {id: CCM32K_OSC32K_CTRL_OSC_EN_CFG, value: Enabled}
133 - {id: CCM32K_OSC32K_CTRL_XTAL_CAP_SEL_CFG, value: 8PF}
134 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
135 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
136 - {id: SCG.FIRC_TRIMDIV.scale, value: '32', locked: true}
137 - {id: SCG_FIRCCSR_TRIM_CFG, value: Autotrimming}
138 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
139 sources:
140 - {id: CCM32K.OSC_32K.outFreq, value: 32.768 kHz, enabled: true}
141 - {id: RADIO.RADIO_FRO192M.outFreq, value: 32 MHz}
142 - {id: SCG.FIRC.outFreq, value: 96 MHz}
143 - {id: SCG.SOSC.outFreq, value: 32 MHz, enabled: true}
144 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
145 /* clang-format on */
146
147 /*******************************************************************************
148 * Variables for BOARD_BootClockRUN configuration
149 ******************************************************************************/
150 static const scg_firc_trim_config_t FircTrimConfig_BOARD_BootClockRUN =
151 {
152 .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */
153 .trimSrc = kSCG_FircTrimSrcSysOsc, /* Trim source is System OSC */
154 .trimDiv = 31U, /* Divided by 32 */
155 .trimCoar = 0U, /* Trim value, see Reference Manual for more information */
156 .trimFine = 0U, /* Trim value, see Reference Manual for more information */
157 };
158 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
159 {
160 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
161 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
162 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
163 .src = (uint32_t)kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
164 };
165 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
166 {
167 .freq = 32000000U, /* System Oscillator frequency: 32000000Hz */
168 .monitorMode = kSCG_SysOscMonitorDisable, /* System OSC Clock Monitor is disabled */
169 .enableMode = kSCG_SoscEnable, /* System OSC Enable */
170 };
171 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
172 {
173 .enableMode = kSCG_SircDisableInSleep, /* Slow IRC is disabled in sleep modes */
174 };
175 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
176 {
177 .enableMode = kSCG_FircEnable, /* Fast IRC is enabled */
178 .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */
179 .trimConfig = &FircTrimConfig_BOARD_BootClockRUN,
180 };
181 static const ccm32k_osc_config_t g_ccm32kOscConfig_BOARD_BootClockRUN =
182 {
183 .coarseAdjustment = kCCM32K_OscCoarseAdjustmentRange0,/* ESR_Range0 */
184 .enableInternalCapBank = true, /* Internal capacitance bank is enabled */
185 .xtalCap = kCCM32K_OscXtal8pFCap, /* 8 pF */
186 .extalCap = kCCM32K_OscExtal8pFCap, /* 8 pF */
187 };
188 /*******************************************************************************
189 * Code for BOARD_BootClockRUN configuration
190 ******************************************************************************/
BOARD_BootClockRUN(void)191 void BOARD_BootClockRUN(void)
192 {
193 uint32_t coreFreq;
194 scg_sys_clk_config_t curConfig;
195 spc_active_mode_core_ldo_option_t ldoOption;
196
197 /* Unlock FIRC, SIRC, ROSC and SOSC control status registers */
198 CLOCK_UnlockFircControlStatusReg();
199 CLOCK_UnlockSircControlStatusReg();
200 CLOCK_UnlockRoscControlStatusReg();
201 CLOCK_UnlockSysOscControlStatusReg();
202
203 /* Get the CPU Core frequency */
204 coreFreq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
205
206 if (coreFreq <= BOARD_BOOTCLOCKRUN_CORE_CLOCK) {
207 /* Set the LDO_CORE VDD regulator level */
208 ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
209 ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
210 (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
211 /* Configure Flash to support different voltage level and frequency */
212 FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
213 /* Specifies the operating voltage for the SRAM's read/write timing margin */
214 SPC_SetSRAMOperateVoltage(SPC0, kSPC_SRAM_OperatVoltage1P1V);
215 }
216
217 /* Config 32k Crystal Oscillator */
218 CCM32K_Set32kOscConfig(CCM32K, kCCM32K_Enable32kHzCrystalOsc, &g_ccm32kOscConfig_BOARD_BootClockRUN);
219 /* Monitor is disabled */
220 CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorDisable);
221 /* Wait for the 32kHz crystal oscillator to be stable */
222 while ((CCM32K_GetStatusFlag(CCM32K) & CCM32K_STATUS_OSC32K_RDY_MASK) == 0UL)
223 {
224 }
225 /* OSC32K clock output is selected as clock source */
226 CCM32K_SelectClockSource(CCM32K, kCCM32K_ClockSourceSelectOsc32k);
227 /* Disable the FRO32K clock */
228 CCM32K_Enable32kFro(CCM32K, false);
229 /* Wait for RTC Oscillator to be Valid */
230 while (!CLOCK_IsRoscValid())
231 {
232 }
233
234 CLOCK_SetXtal32Freq(BOARD_BOOTCLOCKRUN_ROSC_CLOCK);
235
236 /* Init FIRC */
237 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
238 /* Set SCG to FIRC mode */
239 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
240 /* Wait for clock source switch finished */
241 do
242 {
243 CLOCK_GetCurSysClkConfig(&curConfig);
244 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
245 /* Initializes SOSC according to board configuration */
246 (void)CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
247 /* Set the XTAL0 frequency based on board settings */
248 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
249 /* Init SIRC */
250 (void)CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
251 /* Set SystemCoreClock variable */
252 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
253
254 if (coreFreq > BOARD_BOOTCLOCKRUN_CORE_CLOCK) {
255 /* Configure Flash to support different voltage level and frequency */
256 FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
257 /* Specifies the operating voltage for the SRAM's read/write timing margin */
258 SPC_SetSRAMOperateVoltage(SPC0, kSPC_SRAM_OperatVoltage1P1V);
259 /* Set the LDO_CORE VDD regulator level */
260 ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
261 ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
262 (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
263 }
264
265 /* Set SCG CLKOUT selection. */
266 CLOCK_CONFIG_SetScgOutSel(kClockClkoutSelScgSlow);
267 }
268
