1 /*
2 * Copyright 2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 /***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11 /*
12 * How to setup clock using clock driver functions:
13 *
14 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
15 * Note: The clock could not be set when it is being used as system clock.
16 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
17 * so before setting FIRC, change to use another avaliable clock source.
18 *
19 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
20 *
21 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
22 * Wait until the system clock source is changed to target source.
23 *
24 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
25 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
26 * Supported run mode and clock restrictions could be found in Reference Manual.
27 */
28
29 /* clang-format off */
30 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
31 !!GlobalInfo
32 product: Clocks v12.0
33 processor: MKE17Z512xxx9
34 package_id: MKE17Z512VLL9
35 mcu_data: ksdk2_0
36 processor_version: 0.0.0
37 board: FRDM-KE17Z512
38 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
39 /* clang-format on */
40
41 #include "fsl_smc.h"
42 #include "clock_config.h"
43
44 /*******************************************************************************
45 * Definitions
46 ******************************************************************************/
47
48 /*******************************************************************************
49 * Variables
50 ******************************************************************************/
51
52 /*******************************************************************************
53 * Code
54 ******************************************************************************/
55 /*FUNCTION**********************************************************************
56 *
57 * Function Name : CLOCK_CONFIG_FircSafeConfig
58 * Description : This function is used to safely configure FIRC clock.
59 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
60 * Before setting FIRC, change to use SIRC as system clock,
61 * then configure FIRC. After FIRC is set, change back to use FIRC
62 * in case SIRC need to be configured.
63 * Param fircConfig : FIRC configuration.
64 *
65 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)66 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
67 {
68 scg_sys_clk_config_t curConfig;
69 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
70 .div2 = kSCG_AsyncClkDivBy2,
71 .range = kSCG_SircRangeHigh};
72 scg_sys_clk_config_t sysClkSafeConfigSource = {
73 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
74 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
75 .src = kSCG_SysClkSrcSirc /* System clock source */
76 };
77 /* Init Sirc. */
78 CLOCK_InitSirc(&scgSircConfig);
79 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
80 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
81 /* Wait for clock source switch finished. */
82 do
83 {
84 CLOCK_GetCurSysClkConfig(&curConfig);
85 } while (curConfig.src != sysClkSafeConfigSource.src);
86
87 /* Init Firc. */
88 CLOCK_InitFirc(fircConfig);
89 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
90 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
91 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
92 /* Wait for clock source switch finished. */
93 do
94 {
95 CLOCK_GetCurSysClkConfig(&curConfig);
96 } while (curConfig.src != sysClkSafeConfigSource.src);
97 }
98
99 /*******************************************************************************
100 ************************ BOARD_InitBootClocks function ************************
101 ******************************************************************************/
BOARD_InitBootClocks(void)102 void BOARD_InitBootClocks(void)
103 {
104 BOARD_BootClockRUN();
105 }
106
107 /*******************************************************************************
108 ********************** Configuration BOARD_BootClockRUN ***********************
109 ******************************************************************************/
110 /* clang-format off */
111 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
112 !!Configuration
113 name: BOARD_BootClockRUN
114 called_from_default_init: true
115 outputs:
116 - {id: Bus_clock.outFreq, value: 24 MHz}
117 - {id: Core_clock.outFreq, value: 72 MHz}
118 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
119 - {id: FLLDIV2_CLK.outFreq, value: 36 MHz}
120 - {id: Flash_clock.outFreq, value: 24 MHz}
121 - {id: LPO1KCLK.outFreq, value: 1 kHz}
122 - {id: LPO_clock.outFreq, value: 128 kHz}
123 - {id: PCC.PCC_ADC0_CLK.outFreq, value: 8 MHz}
124 - {id: PCC.PCC_LPI2C0_CLK.outFreq, value: 8 MHz}
125 - {id: PCC.PCC_LPUART0_CLK.outFreq, value: 8 MHz}
126 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
127 - {id: SIRC_CLK.outFreq, value: 8 MHz}
128 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
129 - {id: SOSC_CLK.outFreq, value: 8 MHz}
130 - {id: System_clock.outFreq, value: 72 MHz}
131 settings:
132 - {id: SCGMode, value: LPFLL}
133 - {id: PCC.PCC_ADC0_SEL.sel, value: SCG.SOSCDIV2_CLK}
134 - {id: PCC.PCC_LPI2C0_SEL.sel, value: SCG.SOSCDIV2_CLK}
135 - {id: PCC.PCC_LPUART0_SEL.sel, value: SCG.SOSCDIV2_CLK}
136 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
137 - {id: SCG.DIVSLOW.scale, value: '3', locked: true}
138 - {id: SCG.FIRCDIV2.scale, value: '1'}
139 - {id: SCG.LPFLLDIV2.scale, value: '2'}
140 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
141 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
142 - {id: SCG.SIRCDIV2.scale, value: '2'}
143 - {id: SCG.SOSCDIV2.scale, value: '1'}
144 - {id: SCG.TRIMDIV.scale, value: '4'}
145 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
146 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
147 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
148 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
149 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
150 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
151 sources:
152 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
153 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
154 /* clang-format on */
155
156 /*******************************************************************************
157 * Variables for BOARD_BootClockRUN configuration
158 ******************************************************************************/
159 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
160 {
161 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
162 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
163 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
164 };
165 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
166 {
167 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
168 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
169 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
171 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
172 };
173 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
174 {
175 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
177 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
178 };
179 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
180 {
181 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
183 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
184 .trimConfig = NULL, /* Fast IRC Trim disabled */
185 };
186 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
187 {
188 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
190 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
191 .trimConfig = NULL,
192 };
193 /*******************************************************************************
194 * Code for BOARD_BootClockRUN configuration
195 ******************************************************************************/
BOARD_BootClockRUN(void)196 void BOARD_BootClockRUN(void)
197 {
198 scg_sys_clk_config_t curConfig;
199
200 /* Init SOSC according to board configuration. */
201 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
202 /* Set the XTAL0 frequency based on board settings. */
203 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
204 /* Init FIRC. */
205 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
206 /* Init SIRC. */
207 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
208 /* Init LPFLL. */
209 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
210 /* Set SCG to LPFLL mode. */
211 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
212 /* Wait for clock source switch finished. */
213 do
214 {
215 CLOCK_GetCurSysClkConfig(&curConfig);
216 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
217 /* Set SystemCoreClock variable. */
218 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
219 /* Set PCC ADC0 selection */
220 CLOCK_SetIpSrc(kCLOCK_Adc0, kCLOCK_IpSrcSysOscAsync);
221 /* Set PCC LPI2C0 selection */
222 CLOCK_SetIpSrc(kCLOCK_Lpi2c0, kCLOCK_IpSrcSysOscAsync);
223 /* Set PCC LPUART0 selection */
224 CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcSysOscAsync);
225 }
226
227 /*******************************************************************************
228 ********************* Configuration BOARD_BootClockVLPR ***********************
229 ******************************************************************************/
230 /* clang-format off */
231 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
232 !!Configuration
233 name: BOARD_BootClockVLPR
234 outputs:
235 - {id: Bus_clock.outFreq, value: 1 MHz}
236 - {id: Core_clock.outFreq, value: 4 MHz}
237 - {id: Flash_clock.outFreq, value: 1 MHz}
238 - {id: LPO1KCLK.outFreq, value: 1 kHz}
239 - {id: LPO_clock.outFreq, value: 128 kHz}
240 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
241 - {id: SOSC_CLK.outFreq, value: 8 MHz}
242 - {id: System_clock.outFreq, value: 4 MHz}
243 settings:
244 - {id: SCGMode, value: SOSC}
245 - {id: powerMode, value: VLPR}
246 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
247 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
248 - {id: SCG.FIRCDIV2.scale, value: '1'}
249 - {id: SCG.LPFLLDIV2.scale, value: '2'}
250 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
251 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
252 - {id: SCG.SIRCDIV2.scale, value: '2'}
253 - {id: SCG.SOSCDIV2.scale, value: '1'}
254 - {id: SCG.TRIMDIV.scale, value: '4'}
255 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
256 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
257 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
258 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
259 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
260 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
261 sources:
262 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
263 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
264 /* clang-format on */
265
266 /*******************************************************************************
267 * Variables for BOARD_BootClockVLPR configuration
268 ******************************************************************************/
269 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
270 {
271 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
272 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
273 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
274 };
275 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
276 {
277 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
278 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
279 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
280 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
281 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
282 };
283 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
284 {
285 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
286 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
287 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
288 };
289 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
290 {
291 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
292 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
293 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
294 .trimConfig = NULL, /* Fast IRC Trim disabled */
295 };
296 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
297 {
298 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
299 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
300 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
301 .trimConfig = NULL,
302 };
303 /*******************************************************************************
304 * Code for BOARD_BootClockVLPR configuration
305 ******************************************************************************/
BOARD_BootClockVLPR(void)306 void BOARD_BootClockVLPR(void)
307 {
308 /* Init SOSC according to board configuration. */
309 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
310 /* Set the XTAL0 frequency based on board settings. */
311 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
312 /* Set SCG to SOSC mode. */
313 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
314 /* Allow SMC all power modes. */
315 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
316 /* Set VLPR power mode. */
317 SMC_SetPowerModeVlpr(SMC);
318 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
319 {
320 }
321 /* Set SystemCoreClock variable. */
322 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
323 }
324
325 /*******************************************************************************
326 ********************* Configuration BOARD_BootClockHSRUN **********************
327 ******************************************************************************/
328 /* clang-format off */
329 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
330 !!Configuration
331 name: BOARD_BootClockHSRUN
332 outputs:
333 - {id: Bus_clock.outFreq, value: 24 MHz}
334 - {id: Core_clock.outFreq, value: 96 MHz}
335 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
336 - {id: FLLDIV2_CLK.outFreq, value: 48 MHz}
337 - {id: Flash_clock.outFreq, value: 24 MHz}
338 - {id: LPO1KCLK.outFreq, value: 1 kHz}
339 - {id: LPO_clock.outFreq, value: 128 kHz}
340 - {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
341 - {id: SIRC_CLK.outFreq, value: 8 MHz}
342 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
343 - {id: SOSC_CLK.outFreq, value: 8 MHz}
344 - {id: System_clock.outFreq, value: 96 MHz}
345 settings:
346 - {id: SCGMode, value: LPFLL}
347 - {id: powerMode, value: HSRUN}
348 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
349 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
350 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
351 - {id: SCG.LPFLLDIV2.scale, value: '2', locked: true}
352 - {id: SCG.LPFLL_mul.scale, value: '48', locked: true}
353 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
354 - {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
355 - {id: SCG.SOSCDIV2.scale, value: '1', locked: true}
356 - {id: SCG.TRIMDIV.scale, value: '24'}
357 - {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
358 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
359 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
360 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
361 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
362 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
363 sources:
364 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
365 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
366 /* clang-format on */
367
368 /*******************************************************************************
369 * Variables for BOARD_BootClockHSRUN configuration
370 ******************************************************************************/
371 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
372 {
373 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
374 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
375 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
376 };
377 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
378 {
379 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
380 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
381 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
382 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
383 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
384 };
385 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
386 {
387 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
388 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
389 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
390 };
391 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
392 {
393 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
394 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
395 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
396 .trimConfig = NULL, /* Fast IRC Trim disabled */
397 };
398 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
399 {
400 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
401 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
402 .range = kSCG_LpFllRange96M, /* LPFLL is trimmed to 96MHz */
403 .trimConfig = NULL,
404 };
405 /*******************************************************************************
406 * Code for BOARD_BootClockHSRUN configuration
407 ******************************************************************************/
BOARD_BootClockHSRUN(void)408 void BOARD_BootClockHSRUN(void)
409 {
410 scg_sys_clk_config_t curConfig;
411
412 /* Init SOSC according to board configuration. */
413 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
414 /* Set the XTAL0 frequency based on board settings. */
415 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
416 /* Init FIRC. */
417 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
418 /* Set HSRUN power mode. */
419 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
420 SMC_SetPowerModeHsrun(SMC);
421 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
422 {
423 }
424
425 /* Init SIRC. */
426 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
427 /* Init LPFLL. */
428 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
429 /* Set SCG to LPFLL mode. */
430 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
431 /* Wait for clock source switch finished. */
432 do
433 {
434 CLOCK_GetCurSysClkConfig(&curConfig);
435 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
436 /* Set SystemCoreClock variable. */
437 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
438 }
439
