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Searched refs:divCore (Results 1 – 25 of 67) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c114 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
131 .divCore = kSCG_SysClkDivBy5, /* Core clock divider. */
149 .divCore = kSCG_SysClkDivBy6, /* Core clock divider. */
165 .divCore = kSCG_SysClkDivBy3, /* Core clock divider. */
181 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c92 .divCore = 0, /* Core clock divider. */
148 .divCore = 1, /* Core clock divider. */
153 .divCore = 1, /* Core clock divider. */
158 .divCore = 2, /* Core clock divider. */
361 tmp_sys_clk_cfg.divCore = *core_clk_divider - 1; in BOARD_CalculateCoreClkDivider()
410 g_sysClkConfigFroSource.divCore = core_clk_divider - 1; in BOARD_SwitchToFROClk()
904 g_sysClkConfigRun.divCore = core_clk_divider - 1; in BOARD_SwitchDriveMode()
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z512/
Dclock_config.c74 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
272 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
374 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c79 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
143 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
243 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
351 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c78 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
161 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
273 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
393 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c98 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
182 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
313 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
429 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke16z/
Dclock_config.c77 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
270 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke15z/
Dclock_config.c78 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
161 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
266 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z/
Dclock_config.c75 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
157 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
258 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
/hal_nxp-latest/mcux/mcux-sdk/boards/k32w148evk/
Dclock_config.c81 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zevk/
Dclock_config.c81 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zloc/
Dclock_config.c81 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxw71/
Dclock_config.c81 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core clock divider */ in CLOCK_CONFIG_FircSafeConfig()
162 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c288 freq /= (sysClkConfig.divCore + 1U); /* Divided by the DIVCORE firstly. */ in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c287 freq /= (sysClkConfig.divCore + 1U); /* Divided by the DIVCORE firstly. */ in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c287 freq /= (sysClkConfig.divCore + 1U); /* Divided by the DIVCORE firstly. */ in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h311 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h307 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h299 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h322 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h331 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.h357 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.h323 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h339 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.h364 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member

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