| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_clock.c | 1856 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1857 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1862 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1869 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1870 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_POWER_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1872 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1875 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1879 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbHs0PhyPllClock()
1880 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1881 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_BYPASS_MASK) != 0U) in CLOCK_EnableUsbHs0PhyPllClock()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_clock.c | 1856 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1857 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1862 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1869 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1870 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_POWER_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1872 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1875 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1879 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbHs0PhyPllClock()
1880 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1881 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_BYPASS_MASK) != 0U) in CLOCK_EnableUsbHs0PhyPllClock()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_clock.c | 1856 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1857 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1862 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1869 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1870 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_POWER_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1872 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1); in CLOCK_EnableUsbHs0PhyPllClock()
1875 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0U) in CLOCK_EnableUsbHs0PhyPllClock()
1879 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbHs0PhyPllClock()
1880 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1881 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_BYPASS_MASK) != 0U) in CLOCK_EnableUsbHs0PhyPllClock()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/drivers/ |
| D | fsl_clock.c | 675 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL… in CLOCK_EnableUsbhs0Clock()
687 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY … in CLOCK_DisableUsbhs0Clock()
743 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */ in CLOCK_EnableUsbhs0PhyPllClock()
744 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
745 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */ in CLOCK_EnableUsbhs0PhyPllClock()
746 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
747 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */ in CLOCK_EnableUsbhs0PhyPllClock()
748 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */ in CLOCK_EnableUsbhs0PhyPllClock()
751 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL) in CLOCK_EnableUsbhs0PhyPllClock()
764 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/drivers/ |
| D | fsl_clock.c | 675 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL… in CLOCK_EnableUsbhs0Clock()
687 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY … in CLOCK_DisableUsbhs0Clock()
743 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */ in CLOCK_EnableUsbhs0PhyPllClock()
744 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
745 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */ in CLOCK_EnableUsbhs0PhyPllClock()
746 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
747 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */ in CLOCK_EnableUsbhs0PhyPllClock()
748 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */ in CLOCK_EnableUsbhs0PhyPllClock()
751 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL) in CLOCK_EnableUsbhs0PhyPllClock()
764 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/drivers/ |
| D | fsl_clock.c | 663 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL… in CLOCK_EnableUsbhs0Clock()
670 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY … in CLOCK_DisableUsbhs0Clock()
724 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */ in CLOCK_EnableUsbhs0PhyPllClock()
725 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
726 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */ in CLOCK_EnableUsbhs0PhyPllClock()
727 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
728 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */ in CLOCK_EnableUsbhs0PhyPllClock()
729 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */ in CLOCK_EnableUsbhs0PhyPllClock()
732 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL) in CLOCK_EnableUsbhs0PhyPllClock()
741 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/drivers/ |
| D | fsl_clock.c | 663 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL… in CLOCK_EnableUsbhs0Clock()
670 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY … in CLOCK_DisableUsbhs0Clock()
724 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */ in CLOCK_EnableUsbhs0PhyPllClock()
725 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
726 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */ in CLOCK_EnableUsbhs0PhyPllClock()
727 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
728 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */ in CLOCK_EnableUsbhs0PhyPllClock()
729 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */ in CLOCK_EnableUsbhs0PhyPllClock()
732 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL) in CLOCK_EnableUsbhs0PhyPllClock()
741 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/drivers/ |
| D | fsl_clock.c | 674 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL… in CLOCK_EnableUsbhs0Clock()
686 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY … in CLOCK_DisableUsbhs0Clock()
742 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */ in CLOCK_EnableUsbhs0PhyPllClock()
743 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
744 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */ in CLOCK_EnableUsbhs0PhyPllClock()
745 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
746 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */ in CLOCK_EnableUsbhs0PhyPllClock()
747 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */ in CLOCK_EnableUsbhs0PhyPllClock()
750 while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL) in CLOCK_EnableUsbhs0PhyPllClock()
763 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/ |
| D | system_MK65F18.c | 191 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) { in SystemCoreClockUpdate()
194 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4); in SystemCoreClockUpdate()
195 … if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) { in SystemCoreClockUpdate()
197 … } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) { in SystemCoreClockUpdate()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/ |
| D | system_MK26F18.c | 178 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) { in SystemCoreClockUpdate()
181 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4); in SystemCoreClockUpdate()
182 … if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) { in SystemCoreClockUpdate()
184 … } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) { in SystemCoreClockUpdate()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/ |
| D | system_MK66F18.c | 191 if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) { in SystemCoreClockUpdate()
194 Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4); in SystemCoreClockUpdate()
195 … if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) { in SystemCoreClockUpdate()
197 … } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) { in SystemCoreClockUpdate()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_clock.c | 1476 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1534 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbHs0PhyPllClock()
1535 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbHs0PhyPllClock()
1536 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1537 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbHs0PhyPllClock()
1539 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1541 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbHs0PhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_clock.c | 1477 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1538 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbHs0PhyPllClock()
1539 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbHs0PhyPllClock()
1540 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1541 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbHs0PhyPllClock()
1543 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbHs0PhyPllClock()
1545 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbHs0PhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/ |
| D | fsl_clock.c | 2574 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2575 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2576 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
2637 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
2639 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2640 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
2642 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2643 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
2645 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
2658 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/ |
| D | fsl_clock.c | 2574 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2575 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2576 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
2637 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
2639 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2640 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
2642 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
2643 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
2645 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
2658 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5514/drivers/ |
| D | fsl_clock.c | 2128 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2173 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
2174 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2175 USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 in CLOCK_EnableUsbhs0PhyPllClock()
2176 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2177 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2179 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2180 USBPHY->PWD_SET = 0x0; in CLOCK_EnableUsbhs0PhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/drivers/ |
| D | fsl_clock.c | 2128 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2173 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
2174 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2175 USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 in CLOCK_EnableUsbhs0PhyPllClock()
2176 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2177 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2179 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2180 USBPHY->PWD_SET = 0x0; in CLOCK_EnableUsbhs0PhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/drivers/ |
| D | fsl_clock.c | 2128 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2173 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
2174 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2175 USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 in CLOCK_EnableUsbhs0PhyPllClock()
2176 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2177 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2179 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2180 USBPHY->PWD_SET = 0x0; in CLOCK_EnableUsbhs0PhyPllClock()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC5516/drivers/ |
| D | fsl_clock.c | 2128 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2173 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
2174 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2175 USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 in CLOCK_EnableUsbhs0PhyPllClock()
2176 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2177 USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2179 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
2180 USBPHY->PWD_SET = 0x0; in CLOCK_EnableUsbhs0PhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/ |
| D | fsl_clock.c | 3016 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3017 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3018 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3079 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
3081 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3082 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3084 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3085 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
3087 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
3100 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/ |
| D | fsl_clock.c | 3016 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3017 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3018 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3079 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
3081 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3082 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3084 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3085 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
3087 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
3100 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/ |
| D | fsl_clock.c | 3016 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3017 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3018 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3079 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
3081 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3082 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3084 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3085 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
3087 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
3100 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/ |
| D | fsl_clock.c | 3016 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3017 USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3018 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3079 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhsPhyPllClock()
3081 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3082 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhsPhyPllClock()
3084 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhsPhyPllClock()
3085 USBPHY->PWD = 0x0U; in CLOCK_EnableUsbhsPhyPllClock()
3087 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhsPhyPllClock()
3100 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhsPhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/ |
| D | fsl_clock.c | 515 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
516 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
518 USBPHY->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
519 USBPHY->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
531 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/ |
| D | fsl_clock.c | 515 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
516 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
518 USBPHY->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
519 USBPHY->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
531 USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
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