1856         USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;  in CLOCK_EnableUsbHs0PhyPllClock()
1857         USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;  in CLOCK_EnableUsbHs0PhyPllClock()
1862         USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK;  in CLOCK_EnableUsbHs0PhyPllClock()
1869         USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1);  in CLOCK_EnableUsbHs0PhyPllClock()
1870         while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_POWER_MASK) == 0U)  in CLOCK_EnableUsbHs0PhyPllClock()
1872             USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_POWER(1);  in CLOCK_EnableUsbHs0PhyPllClock()
1875         while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0U)  in CLOCK_EnableUsbHs0PhyPllClock()
1879         USBPHY->PLL_SIC     = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv;  in CLOCK_EnableUsbHs0PhyPllClock()
1880         USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;  in CLOCK_EnableUsbHs0PhyPllClock()
1881         while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_BYPASS_MASK) != 0U)  in CLOCK_EnableUsbHs0PhyPllClock()
1883             USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;  in CLOCK_EnableUsbHs0PhyPllClock()
1886         USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_ENABLE(1);  in CLOCK_EnableUsbHs0PhyPllClock()
1887         USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1);  in CLOCK_EnableUsbHs0PhyPllClock()
1888 …while ((USBPHY->PLL_SIC & (USBPHY_PLL_SIC_PLL_ENABLE(1) | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1))) …  in CLOCK_EnableUsbHs0PhyPllClock()
1891 …        USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_PLL_ENABLE(1) | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(1);  in CLOCK_EnableUsbHs0PhyPllClock()
1894         USBPHY->PWD = 0x0;  in CLOCK_EnableUsbHs0PhyPllClock()
1906     USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */  in CLOCK_DisableUsbHs0PhyPllClock()
1907     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */  in CLOCK_DisableUsbHs0PhyPllClock()