675 …USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PL…  in CLOCK_EnableUsbhs0Clock()
687 …USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY …  in CLOCK_DisableUsbhs0Clock()
743     USBPHY->TRIM_OVERRIDE_EN = 0x01U;                 /* Override the trim. */  in CLOCK_EnableUsbhs0PhyPllClock()
744     USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */  in CLOCK_EnableUsbhs0PhyPllClock()
745     USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */  in CLOCK_EnableUsbhs0PhyPllClock()
746     USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv;  in CLOCK_EnableUsbhs0PhyPllClock()
747     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */  in CLOCK_EnableUsbhs0PhyPllClock()
748     USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;          /* Clear to 0U to run clocks */  in CLOCK_EnableUsbhs0PhyPllClock()
751     while ((USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK) == 0UL)  in CLOCK_EnableUsbhs0PhyPllClock()
764     USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */  in CLOCK_DisableUsbhs0PhyPllClock()
765     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */  in CLOCK_DisableUsbhs0PhyPllClock()
788 …USBPHY->ANACTRL = (USBPHY->ANACTRL & ~(USBPHY_ANACTRL_PFD_FRAC_MASK | USBPHY_ANACTRL_PFD_CLK_SEL_M…  in CLOCK_EnableUsbhs0PfdClock()
791     USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;  in CLOCK_EnableUsbhs0PfdClock()
792     while ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK) == 0U)  in CLOCK_EnableUsbhs0PfdClock()
821     USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLKGATE_MASK;  in CLOCK_DisableUsbhs0PfdClock()