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Searched refs:TMR3_BASE (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h12144 #define TMR3_BASE (0x4005A000u) macro
12146 #define TMR3 ((TMR_Type *)TMR3_BASE)
12148 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h16849 #define TMR3_BASE (0x4005A000u) macro
16851 #define TMR3 ((TMR_Type *)TMR3_BASE)
16853 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h16845 #define TMR3_BASE (0x4005A000u) macro
16847 #define TMR3 ((TMR_Type *)TMR3_BASE)
16849 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h18261 #define TMR3_BASE (0x4005A000u) macro
18263 #define TMR3 ((TMR_Type *)TMR3_BASE)
18265 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h18393 #define TMR3_BASE (0x4005A000u) macro
18395 #define TMR3 ((TMR_Type *)TMR3_BASE)
18399 TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE \
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h40405 #define TMR3_BASE (0x401E4000u) macro
40407 #define TMR3 ((TMR_Type *)TMR3_BASE)
40413 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h38888 #define TMR3_BASE (0x401E4000u) macro
38890 #define TMR3 ((TMR_Type *)TMR3_BASE)
38896 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h43815 #define TMR3_BASE (0x401E4000u) macro
43817 #define TMR3 ((TMR_Type *)TMR3_BASE)
43823 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h43154 #define TMR3_BASE (0x401E4000u) macro
43156 #define TMR3 ((TMR_Type *)TMR3_BASE)
43162 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h41289 #define TMR3_BASE (0x401E4000u) macro
41291 #define TMR3 ((TMR_Type *)TMR3_BASE)
41297 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h82912 #define TMR3_BASE (0x526B0000u) macro
82916 #define TMR3 ((TMR_Type *)TMR3_BASE)
82928 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
82945 #define TMR3_BASE (0x426B0000u) macro
82947 #define TMR3 ((TMR_Type *)TMR3_BASE)
82953 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h79063 #define TMR3_BASE (0x526B0000u) macro
79067 #define TMR3 ((TMR_Type *)TMR3_BASE)
79079 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
79096 #define TMR3_BASE (0x426B0000u) macro
79098 #define TMR3 ((TMR_Type *)TMR3_BASE)
79104 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h45483 #define TMR3_BASE (0x401E4000u) macro
45485 #define TMR3 ((TMR_Type *)TMR3_BASE)
45491 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h45419 #define TMR3_BASE (0x401E4000u) macro
45421 #define TMR3 ((TMR_Type *)TMR3_BASE)
45427 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h83122 #define TMR3_BASE (0x526B0000u) macro
83126 #define TMR3 ((TMR_Type *)TMR3_BASE)
83170 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
83187 #define TMR3_BASE (0x426B0000u) macro
83189 #define TMR3 ((TMR_Type *)TMR3_BASE)
83211 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h86970 #define TMR3_BASE (0x526B0000u) macro
86974 #define TMR3 ((TMR_Type *)TMR3_BASE)
87018 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
87035 #define TMR3_BASE (0x426B0000u) macro
87037 #define TMR3 ((TMR_Type *)TMR3_BASE)
87059 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h73642 #define TMR3_BASE (0x40164000u) macro
73644 #define TMR3 ((TMR_Type *)TMR3_BASE)
73650 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1165_cm7.h72740 #define TMR3_BASE (0x40164000u) macro
72742 #define TMR3 ((TMR_Type *)TMR3_BASE)
72748 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h73242 #define TMR3_BASE (0x40164000u) macro
73244 #define TMR3 ((TMR_Type *)TMR3_BASE)
73250 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h74144 #define TMR3_BASE (0x40164000u) macro
74146 #define TMR3 ((TMR_Type *)TMR3_BASE)
74152 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1175_cm7.h73242 #define TMR3_BASE (0x40164000u) macro
73244 #define TMR3 ((TMR_Type *)TMR3_BASE)
73250 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h78702 #define TMR3_BASE (0x40164000u) macro
78704 #define TMR3 ((TMR_Type *)TMR3_BASE)
78710 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1173_cm4.h79604 #define TMR3_BASE (0x40164000u) macro
79606 #define TMR3 ((TMR_Type *)TMR3_BASE)
79612 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h78203 #define TMR3_BASE (0x40164000u) macro
78205 #define TMR3 ((TMR_Type *)TMR3_BASE)
78211 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1166_cm4.h79105 #define TMR3_BASE (0x40164000u) macro
79107 #define TMR3 ((TMR_Type *)TMR3_BASE)
79113 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }

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