1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1182CVP2B
4 **                          MIMXRT1182XVP2B
5 **
6 **     Compilers:           GNU C Compiler
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **                          Keil ARM C/C++ Compiler
9 **                          MCUXpresso Compiler
10 **
11 **     Reference manual:    IMXRT1180RM, Rev 5, 01/2024
12 **     Version:             rev. 2.0, 2024-01-18
13 **     Build:               b240417
14 **
15 **     Abstract:
16 **         CMSIS Peripheral Access Layer for MIMXRT1182
17 **
18 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
19 **     Copyright 2016-2024 NXP
20 **     SPDX-License-Identifier: BSD-3-Clause
21 **
22 **     http:                 www.nxp.com
23 **     mail:                 support@nxp.com
24 **
25 **     Revisions:
26 **     - rev. 1.0 (2021-03-09)
27 **         Initial version.
28 **     - rev. 2.0 (2024-01-18)
29 **         Header RFP.
30 **
31 ** ###################################################################
32 */
33 
34 /*!
35  * @file MIMXRT1182.h
36  * @version 2.0
37  * @date 2024-01-18
38  * @brief CMSIS Peripheral Access Layer for MIMXRT1182
39  *
40  * CMSIS Peripheral Access Layer for MIMXRT1182
41  */
42 
43 #if !defined(MIMXRT1182_H_)
44 #define MIMXRT1182_H_                            /**< Symbol preventing repeated inclusion */
45 
46 /** Memory map major version (memory maps with equal major version number are
47  * compatible) */
48 #define MCU_MEM_MAP_VERSION 0x0200U
49 /** Memory map minor version */
50 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
51 
52 /* ----------------------------------------------------------------------------
53    --
54    ---------------------------------------------------------------------------- */
55 
56 /* XBAR related definitions */
57 typedef enum
58 {
59     kXBAR_DSC1 = 1,
60     kXBAR_DSC2 = 2,
61     kXBAR_DSC3 = 3
62 } xbar_instance_t;
63 #define XBAR_INFO \
64     { \
65         { \
66             (volatile uint16_t *)XBAR1_BASE, 0x0U, 111U, 0xDEU, 4U \
67         }, \
68         { \
69             (volatile uint16_t *)XBAR2_BASE, 0x0U, 16U, 0x20U, 1U \
70         }, \
71         { \
72             (volatile uint16_t *)XBAR3_BASE, 0x0U, 16U, 0x20U, 1U \
73         } \
74     }
75 
76 
77 
78 /* ----------------------------------------------------------------------------
79    -- Interrupt vector numbers
80    ---------------------------------------------------------------------------- */
81 
82 /*!
83  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
84  * @{
85  */
86 
87 /** Interrupt Number Definitions */
88 #define NUMBER_OF_INT_VECTORS 255                /**< Number of interrupts in the Vector table */
89 
90 typedef enum IRQn {
91   /* Auxiliary constants */
92   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
93 
94   /* Core interrupts */
95   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
96   HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
97   MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
98   BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
99   UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
100   SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
101   SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
102   DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
103   PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
104   SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */
105 
106   /* Device specific interrupts */
107   TMR1_IRQn                    = 0,                /**< TMR1 interrupt */
108   DAP_IRQn                     = 1,                /**< DAP interrupt */
109   M7_CTI_TRIGGER_OUTPUT_IRQn   = 2,                /**< CTI trigger outputs from CM7 */
110   M33_CTI_TRIGGER_OUTPUT_IRQn  = 3,                /**< CTI trigger outputs from CM33 */
111   Reserved20_IRQn              = 4,                /**< Reserved interrupt */
112   Reserved21_IRQn              = 5,                /**< Reserved interrupt */
113   Reserved22_IRQn              = 6,                /**< Reserved interrupt */
114   Reserved23_IRQn              = 7,                /**< Reserved interrupt */
115   CAN1_IRQn                    = 8,                /**< CAN1 interrupt */
116   CAN1_ERROR_IRQn              = 9,                /**< CAN1 error interrupt */
117   GPIO1_0_IRQn                 = 10,               /**< GPIO1 interrupt 0 */
118   GPIO1_1_IRQn                 = 11,               /**< GPIO1 interrupt 1 */
119   I3C1_IRQn                    = 12,               /**< I3C1 interrupt */
120   LPI2C1_IRQn                  = 13,               /**< LPI2C1 interrupt */
121   LPI2C2_IRQn                  = 14,               /**< LPI2C2 interrupt */
122   LPIT1_IRQn                   = 15,               /**< LPIT1 interrupt */
123   LPSPI1_IRQn                  = 16,               /**< LPSPI1 interrupt */
124   LPSPI2_IRQn                  = 17,               /**< LPSPI2 interrupt */
125   LPTMR1_IRQn                  = 18,               /**< LPTMR1 interrupt */
126   LPUART1_IRQn                 = 19,               /**< LPUART1 interrupt */
127   LPUART2_IRQn                 = 20,               /**< LPUART2 interrupt */
128   MU1_IRQn                     = 21,               /**< MU1 interrupt */
129   MU2_IRQn                     = 22,               /**< MU2 interrupt */
130   PWM1_FAULT_IRQn              = 23,               /**< PWM1 fault or reload error interrupt */
131   PWM1_0_IRQn                  = 24,               /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
132   PWM1_1_IRQn                  = 25,               /**< PWM1 capture 1, compare 1, or reload 1 interrupt */
133   PWM1_2_IRQn                  = 26,               /**< PWM1 capture 2, compare 2, or reload 2 interrupt */
134   PWM1_3_IRQn                  = 27,               /**< PWM1 capture 3, compare 3, or reload 3 interrupt */
135   EDGELOCK_TRUST_MUA_RX_FULL_IRQn = 28,            /**< Edgelock Trust MUA RX full interrupt */
136   EDGELOCK_TRUST_MUA_TX_EMPTY_IRQn = 29,           /**< Edgelock Trust MUA TX empty interrupt */
137   EDGELOCK_APPS_CORE_MUA_RX_FULL_IRQn = 30,        /**< Edgelock Apps Core MUA RX full interrupt */
138   EDGELOCK_APPS_CORE_MUA_TX_EMPTY_IRQn = 31,       /**< Edgelock Apps Core MUA TX empty interrupt */
139   EDGELOCK_REALTIME_CORE_MUA_RX_FULL_IRQn = 32,    /**< Edgelock Realtime Core MUA RX full interrupt */
140   EDGELOCK_REALTIME_CORE_MUA_TX_EMPTY_IRQn = 33,   /**< Edgelock Realtime Core MUA TX empty interrupt */
141   EDGELOCK_SECURE_IRQn         = 34,               /**< Edgelock secure interrupt */
142   EDGELOCK_NONSECURE_IRQn      = 35,               /**< Edgelock non-secure interrupt */
143   TPM1_IRQn                    = 36,               /**< TPM1 interrupt */
144   TPM2_IRQn                    = 37,               /**< TPM2 interrupt */
145   RTWDOG1_IRQn                 = 38,               /**< RTWDOG1 interrupt */
146   RTWDOG2_IRQn                 = 39,               /**< RTWDOG2 interrupt */
147   TRDC_MGR_AON_IRQn            = 40,               /**< AONMIX TRDC transfer error interrupt */
148   PDM_HWVAD_EVENT_IRQn         = 41,               /**< HWVAD event interrupt */
149   PDM_HWVAD_ERROR_IRQn         = 42,               /**< HWVAD error interrupt */
150   PDM_EVENT_IRQn               = 43,               /**< PDM event interrupt */
151   PDM_ERROR_IRQn               = 44,               /**< PDM error interrupt */
152   SAI1_IRQn                    = 45,               /**< SAI interrupt */
153   CM33_PS_IRQn                 = 46,               /**< M33 PS Tag/Data Parity Error */
154   CM33_TCM_ECC_IRQn            = 47,               /**< M33 TCM ECC interrupt */
155   CM33_TCM_ERROR_IRQn          = 48,               /**< M33 TCM Error interrupt */
156   CM7_TCM_ECC_IRQn             = 49,               /**< M7 TCM ECC interrupt */
157   CM7_TCM_ERROR_IRQn           = 50,               /**< M7 TCM Error interrupt */
158   CAN2_IRQn                    = 51,               /**< CAN2 interrupt */
159   CAN2_ERROR_IRQn              = 52,               /**< CAN2 error interrupt */
160   FLEXIO1_IRQn                 = 53,               /**< FLEXIO1 interrupt */
161   FLEXIO2_IRQn                 = 54,               /**< FLEXIO2 interrupt */
162   FLEXSPI1_IRQn                = 55,               /**< FLEXSPI1 interrupt */
163   FLEXSPI2_IRQn                = 56,               /**< FLEXSPI2 interrupt */
164   GPIO2_0_IRQn                 = 57,               /**< GPIO2 interrupt 0 */
165   GPIO2_1_IRQn                 = 58,               /**< GPIO2 interrupt 1 */
166   GPIO3_0_IRQn                 = 59,               /**< GPIO3 interrupt 0 */
167   GPIO3_1_IRQn                 = 60,               /**< GPIO3 interrupt 1 */
168   I3C2_IRQn                    = 61,               /**< I3C2 interrupt */
169   LPI2C3_IRQn                  = 62,               /**< LPI2C3 interrupt */
170   Reserved79_IRQn              = 63,               /**< Reserved interrupt */
171   LPIT2_IRQn                   = 64,               /**< LPIT2 interrupt */
172   LPSPI3_IRQn                  = 65,               /**< LPSPI3 interrupt */
173   LPSPI4_IRQn                  = 66,               /**< LPSPI4 interrupt */
174   Reserved83_IRQn              = 67,               /**< Reserved interrupt */
175   LPUART3_IRQn                 = 68,               /**< LPUART3 interrupt */
176   LPUART4_IRQn                 = 69,               /**< LPUART4 interrupt */
177   LPUART5_IRQn                 = 70,               /**< LPUART5 interrupt */
178   LPUART6_IRQn                 = 71,               /**< LPUART6 interrupt */
179   Reserved88_IRQn              = 72,               /**< Reserved interrupt 88 */
180   BBNSM_IRQn                   = 73,               /**< BBNSM iterrupt */
181   SYS_CTR1_IRQn                = 74,               /**< System Counter compare interrupt 0 and 1 */
182   TPM3_IRQn                    = 75,               /**< TPM3 interrupt */
183   Reserved92_IRQn              = 76,               /**< Reserved interrupt */
184   Reserved93_IRQn              = 77,               /**< Reserved interrupt */
185   Reserved94_IRQn              = 78,               /**< Reserved interrupt */
186   RTWDOG3_IRQn                 = 79,               /**< RTWDOG3 interrupt */
187   RTWDOG4_IRQn                 = 80,               /**< RTWDOG4 interrupt */
188   RTWDOG5_IRQn                 = 81,               /**< RTWDOG5 interrupt */
189   TRDC_MGR_WKUP_IRQn           = 82,               /**< WAKEUPMIX TRDC transfer error interrupt */
190   TMPSNS_INT_IRQn              = 83,               /**< Temperature alarm interrupt */
191   BBSM_IRQn                    = 84,               /**< BBSM wakeup alarm interrupt */
192   LDO_AON_ANA_IRQn             = 85,               /**< Brown out interrupt */
193   USDHC1_IRQn                  = 86,               /**< USDHC1 */
194   Reserved103_IRQn             = 87,               /**< Reserved interrupt */
195   TRDC_MGR_MEGA_IRQn           = 88,               /**< MEGAMIX TRDC transfer error interrupt */
196   SFA_IRQn                     = 89,               /**< Signal Frequency Analyzer interrupt */
197   LDO_AON_DIG_IRQn             = 90,               /**< Brown out interrupt */
198   MECC1_IRQn                   = 91,               /**< MECC1 interrupt */
199   MECC2_IRQn                   = 92,               /**< MECC2 interrupt */
200   ADC1_IRQn                    = 93,               /**< ADC1 interrupt */
201   DMA_ERROR_IRQn               = 94,               /**< AON Domain eDMA error interrupt */
202   DMA3_CH0_IRQn                = 95,               /**< AON Domain eDMA channel 0 interrupt */
203   DMA3_CH1_IRQn                = 96,               /**< AON Domain eDMA channel 1 interrupt */
204   DMA3_CH2_IRQn                = 97,               /**< AON Domain eDMA channel 2 interrupt */
205   DMA3_CH3_IRQn                = 98,               /**< AON Domain eDMA channel 3 interrupt */
206   DMA3_CH4_IRQn                = 99,               /**< AON Domain eDMA channel 4 interrupt */
207   DMA3_CH5_IRQn                = 100,              /**< AON Domain eDMA channel 5 interrupt */
208   DMA3_CH6_IRQn                = 101,              /**< AON Domain eDMA channel 6 interrupt */
209   DMA3_CH7_IRQn                = 102,              /**< AON Domain eDMA channel 7 interrupt */
210   DMA3_CH8_IRQn                = 103,              /**< AON Domain eDMA channel 8 interrupt */
211   DMA3_CH9_IRQn                = 104,              /**< AON Domain eDMA channel 9 interrupt */
212   DMA3_CH10_IRQn               = 105,              /**< AON Domain eDMA channel 10 interrupt */
213   DMA3_CH11_IRQn               = 106,              /**< AON Domain eDMA channel 11 interrupt */
214   DMA3_CH12_IRQn               = 107,              /**< AON Domain eDMA channel 12 interrupt */
215   DMA3_CH13_IRQn               = 108,              /**< AON Domain eDMA channel 13 interrupt */
216   DMA3_CH14_IRQn               = 109,              /**< AON Domain eDMA channel 14 interrupt */
217   DMA3_CH15_IRQn               = 110,              /**< AON Domain eDMA channel 15 interrupt */
218   DMA3_CH16_IRQn               = 111,              /**< AON Domain eDMA channel 16 interrupt */
219   DMA3_CH17_IRQn               = 112,              /**< AON Domain eDMA channel 17 interrupt */
220   DMA3_CH18_IRQn               = 113,              /**< AON Domain eDMA channel 18 interrupt */
221   DMA3_CH19_IRQn               = 114,              /**< AON Domain eDMA channel 19 interrupt */
222   DMA3_CH20_IRQn               = 115,              /**< AON Domain eDMA channel 20 interrupt */
223   DMA3_CH21_IRQn               = 116,              /**< AON Domain eDMA channel 21 interrupt */
224   DMA3_CH22_IRQn               = 117,              /**< AON Domain eDMA channel 22 interrupt */
225   DMA3_CH23_IRQn               = 118,              /**< AON Domain eDMA channel 23 interrupt */
226   DMA3_CH24_IRQn               = 119,              /**< AON Domain eDMA channel 24 interrupt */
227   DMA3_CH25_IRQn               = 120,              /**< AON Domain eDMA channel 25 interrupt */
228   DMA3_CH26_IRQn               = 121,              /**< AON Domain eDMA channel 26 interrupt */
229   DMA3_CH27_IRQn               = 122,              /**< AON Domain eDMA channel 27 interrupt */
230   DMA3_CH28_IRQn               = 123,              /**< AON Domain eDMA channel 28 interrupt */
231   DMA3_CH29_IRQn               = 124,              /**< AON Domain eDMA channel 29 interrupt */
232   DMA3_CH30_IRQn               = 125,              /**< AON Domain eDMA channel 30 interrupt */
233   DMA3_CH31_IRQn               = 126,              /**< AON Domain eDMA channel 31 interrupt */
234   DMA4_ERROR_IRQn              = 127,              /**< WAKEUP Domain eDMA error interrupt */
235   DMA4_CH0_CH1_CH32_CH33_IRQn  = 128,              /**< WAKEUP Domain eDMA channel 0/1/32/33 interrupt */
236   DMA4_CH2_CH3_CH34_CH35_IRQn  = 129,              /**< WAKEUP Domain eDMA channel 2/3/34/35 interrupt */
237   DMA4_CH4_CH5_CH36_CH37_IRQn  = 130,              /**< WAKEUP Domain eDMA channel 4/5/36/37 interrupt */
238   DMA4_CH6_CH7_CH38_CH39_IRQn  = 131,              /**< WAKEUP Domain eDMA channel 6/7/38/39 interrupt */
239   DMA4_CH8_CH9_CH40_CH41_IRQn  = 132,              /**< WAKEUP Domain eDMA channel 8/9/40/41 interrupt */
240   DMA4_CH10_CH11_CH42_CH43_IRQn = 133,             /**< WAKEUP Domain eDMA channel 10/11/42/43 interrupt */
241   DMA4_CH12_CH13_CH44_CH45_IRQn = 134,             /**< WAKEUP Domain eDMA channel 12/13/44/45 interrupt */
242   DMA4_CH14_CH15_CH46_CH47_IRQn = 135,             /**< WAKEUP Domain eDMA channel 14/15/46/47 interrupt */
243   DMA4_CH16_CH17_CH48_CH49_IRQn = 136,             /**< WAKEUP Domain eDMA channel 16/17/48/49 interrupt */
244   DMA4_CH18_CH19_CH50_CH51_IRQn = 137,             /**< WAKEUP Domain eDMA channel 18/19/50/51 interrupt */
245   DMA4_CH20_CH21_CH52_CH53_IRQn = 138,             /**< WAKEUP Domain eDMA channel 20/21/52/53 interrupt */
246   DMA4_CH22_CH23_CH54_CH55_IRQn = 139,             /**< WAKEUP Domain eDMA channel 22/23/54/55 interrupt */
247   DMA4_CH24_CH25_CH56_CH57_IRQn = 140,             /**< WAKEUP Domain eDMA channel 24/25/56/57 interrupt */
248   DMA4_CH26_CH27_CH58_CH59_IRQn = 141,             /**< WAKEUP Domain eDMA channel 26/27/58/59 interrupt */
249   DMA4_CH28_CH29_CH60_CH61_IRQn = 142,             /**< WAKEUP Domain eDMA channel 28/29/60/61 interrupt */
250   DMA4_CH30_CH31_CH62_CH63_IRQn = 143,             /**< WAKEUP Domain eDMA channel 30/31/62/63 interrupt */
251   XBAR1_CH0_CH1_IRQn           = 144,              /**< XBAR1 channel 0/1 interrupt */
252   XBAR1_CH2_CH3_IRQn           = 145,              /**< XBAR1 channel 2/3 interrupt */
253   Reserved162_IRQn             = 146,              /**< Reserved interrupt */
254   EWM_IRQn                     = 147,              /**< EWM reset out interrupt */
255   Reserved164_IRQn             = 148,              /**< Reserved interrupt */
256   LPIT3_IRQn                   = 149,              /**< LPIT3 interrupt */
257   Reserved166_IRQn             = 150,              /**< Reserved interrupt */
258   TMR4_IRQn                    = 151,              /**< TMR4 interrupt */
259   Reserved168_IRQn             = 152,              /**< Reserved interrupt */
260   Reserved169_IRQn             = 153,              /**< Reserved interrupt */
261   SAI4_IRQn                    = 154,              /**< SAI4 interrupt */
262   SPDIF_IRQn                   = 155,              /**< SPDIF interrupt */
263   Reserved172_IRQn             = 156,              /**< Reserved interrupt */
264   Reserved173_IRQn             = 157,              /**< Reserved interrupt */
265   Reserved174_IRQn             = 158,              /**< Reserved interrupt */
266   Reserved175_IRQn             = 159,              /**< Reserved interrupt */
267   INTG_BOOTROM_DEBUG_CTRL_IRQn = 160,              /**< CM33, CM7, DAP access IRQ */
268   EDGELOCK_REQ1_IRQn           = 161,              /**< Edgelock reuqest 1 interrupt */
269   EDGELOCK_REQ2_IRQn           = 162,              /**< Edgelock reuqest 2 interrupt */
270   EDGELOCK_REQ3_IRQn           = 163,              /**< Edgelock reuqest 3 interrupt */
271   TMR3_IRQn                    = 164,              /**< TMR3 interrupt */
272   JTAGC_IRQn                   = 165,              /**< JTAGC SRC reset source */
273   M33_SYSRESET_REQ_IRQn        = 166,              /**< CM33 SYSREQRST SRC reset source */
274   M33_LOCKUP_IRQn              = 167,              /**< CM33 LOCKUP SRC reset source */
275   M7_SYSRESET_REQ_IRQn         = 168,              /**< CM33 SYSREQRST SRC reset source */
276   M7_LOCKUP_IRQn               = 169,              /**< CM33 LOCKUP SRC reset source */
277   PWM2_FAULT_IRQn              = 170,              /**< PWM2 fault or reload error interrupt */
278   PWM2_0_IRQn                  = 171,              /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
279   PWM2_1_IRQn                  = 172,              /**< PWM2 capture 1, compare 1, or reload 1 interrupt */
280   PWM2_2_IRQn                  = 173,              /**< PWM2 capture 2, compare 2, or reload 2 interrupt */
281   PWM2_3_IRQn                  = 174,              /**< PWM2 capture 3, compare 3, or reload 3 interrupt */
282   Reserved191_IRQn             = 175,              /**< Reserved interrupt */
283   Reserved192_IRQn             = 176,              /**< Reserved interrupt */
284   Reserved193_IRQn             = 177,              /**< Reserved interrupt */
285   Reserved194_IRQn             = 178,              /**< Reserved interrupt */
286   Reserved195_IRQn             = 179,              /**< Reserved interrupt */
287   Reserved196_IRQn             = 180,              /**< Reserved interrupt */
288   Reserved197_IRQn             = 181,              /**< Reserved interrupt */
289   Reserved198_IRQn             = 182,              /**< Reserved interrupt */
290   Reserved199_IRQn             = 183,              /**< Reserved interrupt */
291   Reserved200_IRQn             = 184,              /**< Reserved interrupt */
292   EQDC1_IRQn                   = 185,              /**< EQDC1 interrupt */
293   EQDC2_IRQn                   = 186,              /**< EQDC2 interrupt */
294   Reserved203_IRQn             = 187,              /**< Reserved interrupt */
295   Reserved204_IRQn             = 188,              /**< Reserved interrupt */
296   Reserved205_IRQn             = 189,              /**< Reserved interrupt */
297   DCDC_IRQn                    = 190,              /**< DCDC brown out interrupt */
298   Reserved207_IRQn             = 191,              /**< Reserved interrupt */
299   Reserved208_IRQn             = 192,              /**< Reserved interrupt */
300   DAC_IRQn                     = 193,              /**< DAC interrupt */
301   Reserved210_IRQn             = 194,              /**< Reserved interrupt */
302   Reserved211_IRQn             = 195,              /**< Reserved interrupt */
303   LPUART7_IRQn                 = 196,              /**< LPUART7 interrupt */
304   LPUART8_IRQn                 = 197,              /**< LPUART8 interrupt */
305   SAI2_IRQn                    = 198,              /**< SAI2 interrupt */
306   SAI3_IRQn                    = 199,              /**< SAI3 interrupt */
307   ACMP1_IRQn                   = 200,              /**< CMP1 interrupt */
308   ACMP2_IRQn                   = 201,              /**< CMP2 interrupt */
309   ACMP3_IRQn                   = 202,              /**< CMP3 interrupt */
310   ACMP4_IRQn                   = 203,              /**< CMP4 interrupt */
311   CM7_PS_IRQn                  = 204,              /**< M7 PS Tag/Data Parity Error */
312   CM7_MCM_IRQn                 = 205,              /**< M7 MCM interrupt */
313   CM33_MCM_IRQn                = 206,              /**< M33 MCM interrupt */
314   ECAT_INT_IRQn                = 207,              /**< EtherCAT interrupt */
315   SAFETY_CLK_MON_IRQn          = 208,              /**< Safety clock monitor interrupt */
316   GPT1_IRQn                    = 209,              /**< GPT1 interrupt */
317   GPT2_IRQn                    = 210,              /**< GPT2 interrupt */
318   KPP_IRQn                     = 211,              /**< KPP interrupt */
319   Reserved228_IRQn             = 212,              /**< Reserved interrupt */
320   Reserved229_IRQn             = 213,              /**< Reserved interrupt */
321   Reserved230_IRQn             = 214,              /**< Reserved interrupt */
322   Reserved231_IRQn             = 215,              /**< Reserved interrupt */
323   FLEXSPI_SLV_IRQn             = 216,              /**< FLEXSPI follower interrupt */
324   NETC_IRQn                    = 217,              /**< NETC interrupt */
325   MSGINTR1_IRQn                = 218,              /**< MSGINTR1 interrupt */
326   MSGINTR2_IRQn                = 219,              /**< MSGINTR2 interrupt */
327   MSGINTR3_IRQn                = 220,              /**< MSGINTR3 interrupt */
328   MSGINTR4_IRQn                = 221,              /**< MSGINTR4 interrupt */
329   MSGINTR5_IRQn                = 222,              /**< MSGINTR5 interrupt */
330   MSGINTR6_IRQn                = 223,              /**< MSGINTR6 interrupt */
331   Reserved240_IRQn             = 224,              /**< Reserved interrupt */
332   Reserved241_IRQn             = 225,              /**< Reserved interrupt */
333   Reserved242_IRQn             = 226,              /**< Reserved interrupt */
334   Reserved243_IRQn             = 227,              /**< Reserved interrupt */
335   Reserved244_IRQn             = 228,              /**< Reserved interrupt */
336   Reserved245_IRQn             = 229,              /**< Reserved interrupt */
337   Reserved246_IRQn             = 230,              /**< Reserved interrupt */
338   Reserved247_IRQn             = 231,              /**< Reserved interrupt */
339   GPIO4_IRQn                   = 232,              /**< GPIO4 interrupt */
340   TMR2_IRQn                    = 233,              /**< TMR2 interrupt */
341   GPIO5_IRQn                   = 234,              /**< GPIO5 interrupt */
342   ASRC_IRQn                    = 235,              /**< ASRC interrupt */
343   GPIO6_IRQn                   = 236,              /**< GPIO6 interrupt */
344   DBG_TRACE_IRQn               = 237,              /**< JTAGSW DAP MDM-AP SRC reset source */
345   ECAT_RST_OUT_IRQn            = 238               /**< ECAT reset out interrupt */
346 } IRQn_Type;
347 
348 /*!
349  * @}
350  */ /* end of group Interrupt_vector_numbers */
351 
352 
353 /* ----------------------------------------------------------------------------
354    -- Cortex M33 Core Configuration
355    ---------------------------------------------------------------------------- */
356 
357 /*!
358  * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
359  * @{
360  */
361 
362 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
363 #define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
364 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
365 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
366 #define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
367 #define __SAUREGION_PRESENT            1         /**< Defines if an SAU is present or not */
368 
369 #include "core_cm33.h"                 /* Core Peripheral Access Layer */
370 #include "system_MIMXRT1182.h"         /* Device specific configuration file */
371 
372 /*!
373  * @}
374  */ /* end of group Cortex_Core_Configuration */
375 
376 
377 /* ----------------------------------------------------------------------------
378    -- Mapping Information
379    ---------------------------------------------------------------------------- */
380 
381 /*!
382  * @addtogroup Mapping_Information Mapping Information
383  * @{
384  */
385 
386 /** Mapping Information */
387 /*!
388  * @addtogroup edma_request
389  * @{
390  */
391 
392 /*******************************************************************************
393  * Definitions
394  ******************************************************************************/
395 
396 /*!
397  * @brief Structure for the DMA hardware request
398  *
399  * Defines the structure for the DMA hardware request collections.
400  */
401 typedef enum _dma_request_source
402 {
403     kDma3RequestMuxReserved0        = 0|0x100U,    /**< Reserved 0 */
404     kDma3RequestMuxCAN1             = 1|0x100U,    /**< CAN1 */
405     kDma3RequestMuxReserved2        = 2|0x100U,    /**< Reserved 2 */
406     kDma3RequestMuxGPIO1Request0    = 3|0x100U,    /**< GPIO1 channel 0 */
407     kDma3RequestMuxGPIO1Request1    = 4|0x100U,    /**< GPIO1 channel 1 */
408     kDma3RequestMuxI3C1ToBusRequest = 5|0x100U,    /**< I3C1 To-bus Request */
409     kDma3RequestMuxI3C1FromBusRequest = 6|0x100U,  /**< I3C1 From-bus Request */
410     kDma3RequestMuxLPI2C1Tx         = 7|0x100U,    /**< LPI2C1 TX */
411     kDma3RequestMuxLPI2C1Rx         = 8|0x100U,    /**< LPI2C1 RX */
412     kDma3RequestMuxLPI2C2Tx         = 9|0x100U,    /**< LPI2C2 TX */
413     kDma3RequestMuxLPI2C2Rx         = 10|0x100U,   /**< LPI2C2 RX */
414     kDma3RequestMuxLPSPI1Tx         = 11|0x100U,   /**< LPSPI1 TX */
415     kDma3RequestMuxLPSPI1Rx         = 12|0x100U,   /**< LPSPI1 RX */
416     kDma3RequestMuxLPSPI2Tx         = 13|0x100U,   /**< LPSPI2 TX */
417     kDma3RequestMuxLPSPI2Rx         = 14|0x100U,   /**< LPSPI2 RX */
418     kDma3RequestMuxLPTMR1Request    = 15|0x100U,   /**< LPTMR1 */
419     kDma3RequestMuxLPUART1Tx        = 16|0x100U,   /**< LPUART1 TX */
420     kDma3RequestMuxLPUART1Rx        = 17|0x100U,   /**< LPUART1 RX */
421     kDma3RequestMuxLPUART2Tx        = 18|0x100U,   /**< LPUART2 TX */
422     kDma3RequestMuxLPUART2Rx        = 19|0x100U,   /**< LPUART2 RX */
423     kDma3RequestMuxEdgelockRequest  = 20|0x100U,   /**< Edgelock enclave DMA Request */
424     kDma3RequestMuxSai1Tx           = 21|0x100U,   /**< SAI1 TX */
425     kDma3RequestMuxSai1Rx           = 22|0x100U,   /**< SAI1 RX */
426     kDma3RequestMuxTPM1Request0Request2 = 23|0x100U, /**< TPM1 request 0 and request 2 */
427     kDma3RequestMuxTPM1Request1Request3 = 24|0x100U, /**< TPM1 request 1 and request 3 */
428     kDma3RequestMuxTPM1OverflowRequest = 25|0x100U, /**< TPM1 Overflow request */
429     kDma3RequestMuxTPM2Request0Request2 = 26|0x100U, /**< TPM2 request 0 and request 2 */
430     kDma3RequestMuxTPM2Request1Request3 = 27|0x100U, /**< TPM2 request 1 and request 3 */
431     kDma3RequestMuxTPM2OverflowRequest = 28|0x100U, /**< TPM2 Overflow request */
432     kDma3RequestMuxLPUART7Tx        = 29|0x100U,   /**< LPUART7 TX */
433     kDma3RequestMuxLPUART7Rx        = 30|0x100U,   /**< LPUART7 RX */
434     kDma3RequestMuxFlexSPI2Tx       = 33|0x100U,   /**< FlexSPI2 TX */
435     kDma3RequestMuxFlexSPI2Rx       = 34|0x100U,   /**< FlexSPI2 RX */
436     kDma3RequestMuxReserved35       = 35|0x100U,   /**< Reserved 35 */
437     kDma3RequestMuxReserved36       = 36|0x100U,   /**< Reserved 36 */
438     kDma3RequestMuxReserved37       = 37|0x100U,   /**< Reserved 37 */
439     kDma4RequestMuxReserved0        = 0|0x200U,    /**< Reserved 0 */
440     kDma4RequestMuxCAN2             = 1|0x200U,    /**< CAN2 */
441     kDma4RequestMuxGPIO2Request0    = 2|0x200U,    /**< GPIO2 channel 0 */
442     kDma4RequestMuxGPIO2Request1    = 3|0x200U,    /**< GPIO2 channel 1 */
443     kDma4RequestMuxGPIO3Request0    = 4|0x200U,    /**< GPIO3 channel 0 */
444     kDma4RequestMuxGPIO3Request1    = 5|0x200U,    /**< GPIO3 channel 1 */
445     kDma4RequestMuxI3C2ToBusRequest = 6|0x200U,    /**< I3C2 To-bus Request */
446     kDma4RequestMuxI3C2FromBusRequest = 7|0x200U,  /**< I3C2 From-bus Request */
447     kDma4RequestMuxLPI2C3Tx         = 8|0x200U,    /**< LPI2C3 TX */
448     kDma4RequestMuxLPI2C3Rx         = 9|0x200U,    /**< LPI2C3 RX */
449     kDma4RequestMuxReserved10       = 10|0x200U,   /**< Reserved 10 */
450     kDma4RequestMuxReserved11       = 11|0x200U,   /**< Reserved 11 */
451     kDma4RequestMuxLPSPI3Tx         = 12|0x200U,   /**< LPSPI3 TX */
452     kDma4RequestMuxLPSPI3Rx         = 13|0x200U,   /**< LPSPI3 RX */
453     kDma4RequestMuxLPSPI4Tx         = 14|0x200U,   /**< LPSPI4 TX */
454     kDma4RequestMuxLPSPI4Rx         = 15|0x200U,   /**< LPSPI4 RX */
455     kDma4RequestMuxLPUART3Tx        = 17|0x200U,   /**< LPUART3 TX */
456     kDma4RequestMuxLPUART3Rx        = 18|0x200U,   /**< LPUART3 RX */
457     kDma4RequestMuxLPUART4Tx        = 19|0x200U,   /**< LPUART4 TX */
458     kDma4RequestMuxLPUART4Rx        = 20|0x200U,   /**< LPUART4 RX */
459     kDma4RequestMuxLPUART5Tx        = 21|0x200U,   /**< LPUART5 TX */
460     kDma4RequestMuxLPUART5Rx        = 22|0x200U,   /**< LPUART5 RX */
461     kDma4RequestMuxLPUART6Tx        = 23|0x200U,   /**< LPUART6 TX */
462     kDma4RequestMuxLPUART6Rx        = 24|0x200U,   /**< LPUART6 RX */
463     kDma4RequestMuxTPM3Request0Request2 = 25|0x200U, /**< TPM3 request 0 and request 2 */
464     kDma4RequestMuxTPM3Request1Request3 = 26|0x200U, /**< TPM3 request 1 and request 3 */
465     kDma4RequestMuxTPM3OverflowRequest = 27|0x200U, /**< TPM3 Overflow request */
466     kDma4RequestMuxFlexIO1Request0  = 37|0x200U,   /**< FlexIO1 Request0 */
467     kDma4RequestMuxFlexIO1Request1  = 38|0x200U,   /**< FlexIO1 Request1 */
468     kDma4RequestMuxFlexIO1Request2  = 39|0x200U,   /**< FlexIO1 Request2 */
469     kDma4RequestMuxFlexIO1Request3  = 40|0x200U,   /**< FlexIO1 Request3 */
470     kDma4RequestMuxFlexIO1Request4  = 41|0x200U,   /**< FlexIO1 Request4 */
471     kDma4RequestMuxFlexIO1Request5  = 42|0x200U,   /**< FlexIO1 Request5 */
472     kDma4RequestMuxFlexIO1Request6  = 43|0x200U,   /**< FlexIO1 Request6 */
473     kDma4RequestMuxFlexIO1Request7  = 44|0x200U,   /**< FlexIO1 Request7 */
474     kDma4RequestMuxFlexIO2Request0  = 45|0x200U,   /**< FlexIO2 Request0 */
475     kDma4RequestMuxFlexIO2Request1  = 46|0x200U,   /**< FlexIO2 Request1 */
476     kDma4RequestMuxFlexIO2Request2  = 47|0x200U,   /**< FlexIO2 Request2 */
477     kDma4RequestMuxFlexIO2Request3  = 48|0x200U,   /**< FlexIO2 Request3 */
478     kDma4RequestMuxFlexIO2Request4  = 49|0x200U,   /**< FlexIO2 Request4 */
479     kDma4RequestMuxFlexIO2Request5  = 50|0x200U,   /**< FlexIO2 Request5 */
480     kDma4RequestMuxFlexIO2Request6  = 51|0x200U,   /**< FlexIO2 Request6 */
481     kDma4RequestMuxFlexIO2Request7  = 52|0x200U,   /**< FlexIO2 Request7 */
482     kDma4RequestMuxFlexSPI1Tx       = 53|0x200U,   /**< FlexSPI1 TX */
483     kDma4RequestMuxFlexSPI1Rx       = 54|0x200U,   /**< FlexSPI1 RX */
484     kDma4RequestMuxReserved55       = 55|0x200U,   /**< Reserved 55 */
485     kDma4RequestMuxReserved56       = 56|0x200U,   /**< Reserved 56 */
486     kDma4RequestMuxADC1Request0     = 57|0x200U,   /**< ADC1 Request 0 */
487     kDma4RequestMuxFlexPWM1CaptureSub0 = 58|0x200U, /**< FlexPWM1 Capture sub-module0 */
488     kDma4RequestMuxFlexPWM1CaptureSub1 = 59|0x200U, /**< FlexPWM1 Capture sub-module1 */
489     kDma4RequestMuxFlexPWM1CaptureSub2 = 60|0x200U, /**< FlexPWM1 Capture sub-module2 */
490     kDma4RequestMuxFlexPWM1CaptureSub3 = 61|0x200U, /**< FlexPWM1 Capture sub-module3 */
491     kDma4RequestMuxFlexPWM1ValueSub0 = 62|0x200U,  /**< FlexPWM1 Value sub-module 0 */
492     kDma4RequestMuxFlexPWM1ValueSub1 = 63|0x200U,  /**< FlexPWM1 Value sub-module 1 */
493     kDma4RequestMuxFlexPWM1ValueSub2 = 64|0x200U,  /**< FlexPWM1 Value sub-module 2 */
494     kDma4RequestMuxFlexPWM1ValueSub3 = 65|0x200U,  /**< FlexPWM1 Value sub-module 3 */
495     kDma4RequestMuxFlexPWM2CaptureSub0 = 66|0x200U, /**< FlexPWM2 Capture sub-module0 */
496     kDma4RequestMuxFlexPWM2CaptureSub1 = 67|0x200U, /**< FlexPWM2 Capture sub-module1 */
497     kDma4RequestMuxFlexPWM2CaptureSub2 = 68|0x200U, /**< FlexPWM2 Capture sub-module2 */
498     kDma4RequestMuxFlexPWM2CaptureSub3 = 69|0x200U, /**< FlexPWM2 Capture sub-module3 */
499     kDma4RequestMuxFlexPWM2ValueSub0 = 70|0x200U,  /**< FlexPWM2 Value sub-module 0 */
500     kDma4RequestMuxFlexPWM2ValueSub1 = 71|0x200U,  /**< FlexPWM2 Value sub-module 1 */
501     kDma4RequestMuxFlexPWM2ValueSub2 = 72|0x200U,  /**< FlexPWM2 Value sub-module 2 */
502     kDma4RequestMuxFlexPWM2ValueSub3 = 73|0x200U,  /**< FlexPWM2 Value sub-module 3 */
503     kDma4RequestMuxQTIMER1CaptTimer0 = 90|0x200U,  /**< TMR1 Capture timer 0 */
504     kDma4RequestMuxQTIMER1CaptTimer1 = 91|0x200U,  /**< TMR1 Capture timer 1 */
505     kDma4RequestMuxQTIMER1CaptTimer2 = 92|0x200U,  /**< TMR1 Capture timer 2 */
506     kDma4RequestMuxQTIMER1CaptTimer3 = 93|0x200U,  /**< TMR1 Capture timer 3 */
507     kDma4RequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 94|0x200U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
508     kDma4RequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 95|0x200U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
509     kDma4RequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 96|0x200U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
510     kDma4RequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 97|0x200U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
511     kDma4RequestMuxQTIMER2CaptTimer0 = 98|0x200U,  /**< TMR2 Capture timer 0 */
512     kDma4RequestMuxQTIMER2CaptTimer1 = 99|0x200U,  /**< TMR2 Capture timer 1 */
513     kDma4RequestMuxQTIMER2CaptTimer2 = 100|0x200U, /**< TMR2 Capture timer 2 */
514     kDma4RequestMuxQTIMER2CaptTimer3 = 101|0x200U, /**< TMR2 Capture timer 3 */
515     kDma4RequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 102|0x200U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
516     kDma4RequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 103|0x200U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
517     kDma4RequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 104|0x200U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
518     kDma4RequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 105|0x200U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
519     kDma4RequestMuxQTIMER3CaptTimer0 = 106|0x200U, /**< TMR3 Capture timer 0 */
520     kDma4RequestMuxQTIMER3CaptTimer1 = 107|0x200U, /**< TMR3 Capture timer 1 */
521     kDma4RequestMuxQTIMER3CaptTimer2 = 108|0x200U, /**< TMR3 Capture timer 2 */
522     kDma4RequestMuxQTIMER3CaptTimer3 = 109|0x200U, /**< TMR3 Capture timer 3 */
523     kDma4RequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 110|0x200U, /**< TMR3 cmpld1 in timer 0 or cmpld2 in timer 1 */
524     kDma4RequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 111|0x200U, /**< TMR3 cmpld1 in timer 1 or cmpld2 in timer 0 */
525     kDma4RequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 112|0x200U, /**< TMR3 cmpld1 in timer 2 or cmpld2 in timer 3 */
526     kDma4RequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 113|0x200U, /**< TMR3 cmpld1 in timer 3 or cmpld2 in timer 2 */
527     kDma4RequestMuxQTIMER4CaptTimer0 = 114|0x200U, /**< TMR4 Capture timer 0 */
528     kDma4RequestMuxQTIMER4CaptTimer1 = 115|0x200U, /**< TMR4 Capture timer 1 */
529     kDma4RequestMuxQTIMER4CaptTimer2 = 116|0x200U, /**< TMR4 Capture timer 2 */
530     kDma4RequestMuxQTIMER4CaptTimer3 = 117|0x200U, /**< TMR4 Capture timer 3 */
531     kDma4RequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 118|0x200U, /**< TMR4 cmpld1 in timer 0 or cmpld2 in timer 1 */
532     kDma4RequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 119|0x200U, /**< TMR4 cmpld1 in timer 1 or cmpld2 in timer 0 */
533     kDma4RequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 120|0x200U, /**< TMR4 cmpld1 in timer 2 or cmpld2 in timer 3 */
534     kDma4RequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 121|0x200U, /**< TMR4 cmpld1 in timer 3 or cmpld2 in timer 2 */
535     kDma4RequestMuxXBAR1Request0    = 154|0x200U,  /**< XBAR1 Request 0 */
536     kDma4RequestMuxXBAR1Request1    = 155|0x200U,  /**< XBAR1 Request 1 */
537     kDma4RequestMuxXBAR1Request2    = 156|0x200U,  /**< XBAR1 Request 2 */
538     kDma4RequestMuxXBAR1Request3    = 157|0x200U,  /**< XBAR1 Request 3 */
539     kDma4RequestMuxEQDC1            = 159|0x200U,  /**< EQDC1 */
540     kDma4RequestMuxEQDC2            = 160|0x200U,  /**< EQDC2 */
541     kDma4RequestMuxReserved163      = 163|0x200U,  /**< Reserved 163 */
542     kDma4RequestMuxReserved164      = 164|0x200U,  /**< Reserved 164 */
543     kDma4RequestMuxLPUART8Tx        = 178|0x200U,  /**< LPUART8 TX */
544     kDma4RequestMuxLPUART8Rx        = 179|0x200U,  /**< LPUART8 RX */
545     kDma4RequestMuxSai2Tx           = 180|0x200U,  /**< SAI2 TX */
546     kDma4RequestMuxSai2Rx           = 181|0x200U,  /**< SAI2 RX */
547     kDma4RequestMuxSai3Tx           = 182|0x200U,  /**< SAI3 TX */
548     kDma4RequestMuxSai3Rx           = 183|0x200U,  /**< SAI3 RX */
549     kDma4RequestMuxSai4Tx           = 184|0x200U,  /**< SAI4 TX */
550     kDma4RequestMuxSai4Rx           = 185|0x200U,  /**< SAI4 RX */
551     kDma4RequestMuxDAC              = 186|0x200U,  /**< DAC */
552     kDma4RequestMuxCMP1             = 187|0x200U,  /**< CMP1 */
553     kDma4RequestMuxCMP2             = 188|0x200U,  /**< CMP2 */
554     kDma4RequestMuxCMP3             = 189|0x200U,  /**< CMP3 */
555     kDma4RequestMuxCMP4             = 190|0x200U,  /**< CMP4 */
556     kDma4RequestMuxASRCRequest1     = 191|0x200U,  /**< ASRC request 1 pair A input request */
557     kDma4RequestMuxASRCRequest2     = 192|0x200U,  /**< ASRC request 2 pair B input request */
558     kDma4RequestMuxASRCRequest3     = 193|0x200U,  /**< ASRC request 3 pair C input request */
559     kDma4RequestMuxASRCRequest4     = 194|0x200U,  /**< ASRC request 4 pair A output request */
560     kDma4RequestMuxASRCRequest5     = 195|0x200U,  /**< ASRC request 5 pair B output request */
561     kDma4RequestMuxASRCRequest6     = 196|0x200U,  /**< ASRC request 6 pair C output request */
562     kDma4RequestMuxSpdifRx          = 197|0x200U,  /**< SPDIF RX */
563     kDma4RequestMuxSpdifTx          = 198|0x200U,  /**< SPDIF TX */
564     kDma4RequestMuxPdmRx            = 199|0x200U,  /**< PDM */
565     kDma4RequestMuxGPIO4Request0    = 200|0x200U,  /**< GPIO4 channel 0 */
566     kDma4RequestMuxGPIO4Request1    = 201|0x200U,  /**< GPIO4 channel 1 */
567     kDma4RequestMuxGPIO5Request0    = 202|0x200U,  /**< GPIO5 channel 0 */
568     kDma4RequestMuxGPIO5Request1    = 203|0x200U,  /**< GPIO5 channel 1 */
569     kDma4RequestMuxGPIO6Request0    = 204|0x200U,  /**< GPIO6 channel 0 */
570     kDma4RequestMuxGPIO6Request1    = 205|0x200U,  /**< GPIO6 channel 1 */
571     kDma4RequestMuxReserved206      = 206|0x200U,  /**< Reserved 206 */
572     kDma4RequestMuxReserved207      = 207|0x200U,  /**< Reserved 207 */
573     kDma4RequestMuxADC1Request1     = 220|0x200U,  /**< ADC1 Request 1 */
574 } dma_request_source_t;
575 
576 /* @} */
577 
578 /*!
579  * @addtogroup trdc1_master_mapping
580  * @{
581  */
582 
583 /*******************************************************************************
584  * Definitions
585  ******************************************************************************/
586 
587 /*!
588  * @brief Enumeration for trdc master 1 mapping
589  * Defines the enumeration for trdc master 1 resource collections.
590  */
591 typedef enum _trdc1_master
592 {
593     kTRDC1_MasterReserved0          = 0U,          /**< Reserved */
594     kTRDC1_MasterCM33               = 1U,          /**< CM33 */
595     kTRDC1_MasterDMA3               = 2U,          /**< DMA3 */
596     kTRDC1_MasterReserved1          = 3U,          /**< Reserved */
597 } trdc1_master_t;
598 
599 /* @} */
600 
601 /*!
602  * @addtogroup trdc2_master_mapping
603  * @{
604  */
605 
606 /*******************************************************************************
607  * Definitions
608  ******************************************************************************/
609 
610 /*!
611  * @brief Enumeration for trdc master 2 mapping
612  * Defines the enumeration for trdc master 2 resource collections.
613  */
614 typedef enum _trdc2_master
615 {
616     kTRDC2_MasterCM7AHBP            = 0U,          /**< CM7 AHBP */
617     kTRDC2_MasterCM7AXI             = 1U,          /**< CM7 AXI */
618     kTRDC2_MasterDAP                = 2U,          /**< DAP AHB_AP_SYS */
619     kTRDC2_MasterCoreSight          = 3U,          /**< CoreSight */
620     kTRDC2_MasterDMA4               = 4U,          /**< DMA4 */
621     kTRDC2_MasterNETC               = 5U,          /**< NETC */
622 } trdc2_master_t;
623 
624 /* @} */
625 
626 /*!
627  * @addtogroup trdc3_master_mapping
628  * @{
629  */
630 
631 /*******************************************************************************
632  * Definitions
633  ******************************************************************************/
634 
635 /*!
636  * @brief Enumeration for trdc master 3 mapping
637  * Defines the enumeration for trdc master 3 resource collections.
638  */
639 typedef enum _trdc3_master
640 {
641     kTRDC3_MasterUSDHC1             = 0U,          /**< uSDHC1 */
642     kTRDC3_MasterUSDHC2             = 1U,          /**< uSDHC2 */
643     kTRDC3_MasterReserved0          = 2U,          /**< Reserved0 */
644     kTRDC3_MasterUsb                = 3U,          /**< USB */
645     kTRDC3_MasterFlexspiFlr         = 4U,          /**< FlexSPI_FLR */
646 } trdc3_master_t;
647 
648 /* @} */
649 
650 /*!
651  * @addtogroup iomuxc_pads
652  * @{ */
653 
654 /*******************************************************************************
655  * Definitions
656 *******************************************************************************/
657 
658 /*!
659  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
660  *
661  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
662  */
663 typedef enum _iomuxc_sw_mux_ctl_pad
664 {
665     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_MUX_CTL_PAD index */
666     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_MUX_CTL_PAD index */
667     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_MUX_CTL_PAD index */
668     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_MUX_CTL_PAD index */
669     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_MUX_CTL_PAD index */
670     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_MUX_CTL_PAD index */
671     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_MUX_CTL_PAD index */
672     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_MUX_CTL_PAD index */
673     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_MUX_CTL_PAD index */
674     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_MUX_CTL_PAD index */
675     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_MUX_CTL_PAD index */
676     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_MUX_CTL_PAD index */
677     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_MUX_CTL_PAD index */
678     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_MUX_CTL_PAD index */
679     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_MUX_CTL_PAD index */
680     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_MUX_CTL_PAD index */
681     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_MUX_CTL_PAD index */
682     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_MUX_CTL_PAD index */
683     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_MUX_CTL_PAD index */
684     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_MUX_CTL_PAD index */
685     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_MUX_CTL_PAD index */
686     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_MUX_CTL_PAD index */
687     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_MUX_CTL_PAD index */
688     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_MUX_CTL_PAD index */
689     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_MUX_CTL_PAD index */
690     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_MUX_CTL_PAD index */
691     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_MUX_CTL_PAD index */
692     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_MUX_CTL_PAD index */
693     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_MUX_CTL_PAD index */
694     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_MUX_CTL_PAD index */
695     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_MUX_CTL_PAD index */
696     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_MUX_CTL_PAD index */
697     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_MUX_CTL_PAD index */
698     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_MUX_CTL_PAD index */
699     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_MUX_CTL_PAD index */
700     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_MUX_CTL_PAD index */
701     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_MUX_CTL_PAD index */
702     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_MUX_CTL_PAD index */
703     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_MUX_CTL_PAD index */
704     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_MUX_CTL_PAD index */
705     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_MUX_CTL_PAD index */
706     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_MUX_CTL_PAD index */
707     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_MUX_CTL_PAD index */
708     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_MUX_CTL_PAD index */
709     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_MUX_CTL_PAD index */
710     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_MUX_CTL_PAD index */
711     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_MUX_CTL_PAD index */
712     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_MUX_CTL_PAD index */
713     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_MUX_CTL_PAD index */
714     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_MUX_CTL_PAD index */
715     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_MUX_CTL_PAD index */
716     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_MUX_CTL_PAD index */
717     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_MUX_CTL_PAD index */
718     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_MUX_CTL_PAD index */
719     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_MUX_CTL_PAD index */
720     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_MUX_CTL_PAD index */
721     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_MUX_CTL_PAD index */
722     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_MUX_CTL_PAD index */
723     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_MUX_CTL_PAD index */
724     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_MUX_CTL_PAD index */
725     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_MUX_CTL_PAD index */
726     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_MUX_CTL_PAD index */
727     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_MUX_CTL_PAD index */
728     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_MUX_CTL_PAD index */
729     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_MUX_CTL_PAD index */
730     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_MUX_CTL_PAD index */
731     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_MUX_CTL_PAD index */
732     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_MUX_CTL_PAD index */
733     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_MUX_CTL_PAD index */
734     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_MUX_CTL_PAD index */
735     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_MUX_CTL_PAD index */
736     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_MUX_CTL_PAD index */
737     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_MUX_CTL_PAD index */
738     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_MUX_CTL_PAD index */
739     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_MUX_CTL_PAD index */
740     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_MUX_CTL_PAD index */
741     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_MUX_CTL_PAD index */
742     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_MUX_CTL_PAD index */
743     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_MUX_CTL_PAD index */
744     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_MUX_CTL_PAD index */
745     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_MUX_CTL_PAD index */
746     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_MUX_CTL_PAD index */
747     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_MUX_CTL_PAD index */
748     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_MUX_CTL_PAD index */
749     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_MUX_CTL_PAD index */
750     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_MUX_CTL_PAD index */
751     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_MUX_CTL_PAD index */
752     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_MUX_CTL_PAD index */
753     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_MUX_CTL_PAD index */
754     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_MUX_CTL_PAD index */
755     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_MUX_CTL_PAD index */
756     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_MUX_CTL_PAD index */
757     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_MUX_CTL_PAD index */
758     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_MUX_CTL_PAD index */
759     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_MUX_CTL_PAD index */
760     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_MUX_CTL_PAD index */
761     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_MUX_CTL_PAD index */
762     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_MUX_CTL_PAD index */
763     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_MUX_CTL_PAD index */
764     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_MUX_CTL_PAD index */
765     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_MUX_CTL_PAD index */
766     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_MUX_CTL_PAD index */
767     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_MUX_CTL_PAD index */
768     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_MUX_CTL_PAD index */
769     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_MUX_CTL_PAD index */
770     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_MUX_CTL_PAD index */
771     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_MUX_CTL_PAD index */
772     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_MUX_CTL_PAD index */
773     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_MUX_CTL_PAD index */
774     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_MUX_CTL_PAD index */
775     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_MUX_CTL_PAD index */
776     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_MUX_CTL_PAD index */
777     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_MUX_CTL_PAD index */
778     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_MUX_CTL_PAD index */
779     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
780     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_MUX_CTL_PAD index */
781     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_MUX_CTL_PAD index */
782     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_12_DUMMY = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
783     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 118U,      /**< IOMUXC SW_MUX_CTL_PAD index */
784     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 119U,      /**< IOMUXC SW_MUX_CTL_PAD index */
785     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 120U,      /**< IOMUXC SW_MUX_CTL_PAD index */
786     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 121U,      /**< IOMUXC SW_MUX_CTL_PAD index */
787     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 122U,      /**< IOMUXC SW_MUX_CTL_PAD index */
788     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 123U,      /**< IOMUXC SW_MUX_CTL_PAD index */
789     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 124U,      /**< IOMUXC SW_MUX_CTL_PAD index */
790     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 125U,      /**< IOMUXC SW_MUX_CTL_PAD index */
791     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 126U,      /**< IOMUXC SW_MUX_CTL_PAD index */
792     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 127U,      /**< IOMUXC SW_MUX_CTL_PAD index */
793     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 128U,      /**< IOMUXC SW_MUX_CTL_PAD index */
794     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 129U,      /**< IOMUXC SW_MUX_CTL_PAD index */
795     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 130U,      /**< IOMUXC SW_MUX_CTL_PAD index */
796     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 131U,      /**< IOMUXC SW_MUX_CTL_PAD index */
797     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_00 = 132U,      /**< IOMUXC SW_MUX_CTL_PAD index */
798     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_01 = 133U,      /**< IOMUXC SW_MUX_CTL_PAD index */
799     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_02 = 134U,      /**< IOMUXC SW_MUX_CTL_PAD index */
800     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_03 = 135U,      /**< IOMUXC SW_MUX_CTL_PAD index */
801     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_04 = 136U,      /**< IOMUXC SW_MUX_CTL_PAD index */
802     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_05 = 137U,      /**< IOMUXC SW_MUX_CTL_PAD index */
803     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_06 = 138U,      /**< IOMUXC SW_MUX_CTL_PAD index */
804     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_07 = 139U,      /**< IOMUXC SW_MUX_CTL_PAD index */
805     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_08 = 140U,      /**< IOMUXC SW_MUX_CTL_PAD index */
806     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_09 = 141U,      /**< IOMUXC SW_MUX_CTL_PAD index */
807     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_10 = 142U,      /**< IOMUXC SW_MUX_CTL_PAD index */
808     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_11 = 143U,      /**< IOMUXC SW_MUX_CTL_PAD index */
809     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_12 = 144U,      /**< IOMUXC SW_MUX_CTL_PAD index */
810     kIOMUXC_SW_MUX_CTL_PAD_GPIO_B2_13 = 145U,      /**< IOMUXC SW_MUX_CTL_PAD index */
811 } iomuxc_sw_mux_ctl_pad_t;
812 
813 /* @} */
814 
815 /*!
816  * @addtogroup iomuxc_pads
817  * @{ */
818 
819 /*******************************************************************************
820  * Definitions
821 *******************************************************************************/
822 
823 /*!
824  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
825  *
826  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
827  */
828 typedef enum _iomuxc_sw_pad_ctl_pad
829 {
830     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_PAD_CTL_PAD index */
831     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_PAD_CTL_PAD index */
832     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_PAD_CTL_PAD index */
833     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_PAD_CTL_PAD index */
834     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_PAD_CTL_PAD index */
835     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_PAD_CTL_PAD index */
836     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_PAD_CTL_PAD index */
837     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_PAD_CTL_PAD index */
838     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_PAD_CTL_PAD index */
839     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_PAD_CTL_PAD index */
840     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_PAD_CTL_PAD index */
841     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_PAD_CTL_PAD index */
842     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_PAD_CTL_PAD index */
843     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_PAD_CTL_PAD index */
844     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_PAD_CTL_PAD index */
845     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_PAD_CTL_PAD index */
846     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_PAD_CTL_PAD index */
847     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_PAD_CTL_PAD index */
848     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_PAD_CTL_PAD index */
849     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_PAD_CTL_PAD index */
850     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_PAD_CTL_PAD index */
851     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_PAD_CTL_PAD index */
852     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_PAD_CTL_PAD index */
853     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_PAD_CTL_PAD index */
854     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_PAD_CTL_PAD index */
855     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_PAD_CTL_PAD index */
856     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_PAD_CTL_PAD index */
857     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_PAD_CTL_PAD index */
858     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_PAD_CTL_PAD index */
859     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_PAD_CTL_PAD index */
860     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_PAD_CTL_PAD index */
861     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_PAD_CTL_PAD index */
862     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_PAD_CTL_PAD index */
863     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_PAD_CTL_PAD index */
864     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_PAD_CTL_PAD index */
865     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_PAD_CTL_PAD index */
866     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_PAD_CTL_PAD index */
867     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_PAD_CTL_PAD index */
868     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_PAD_CTL_PAD index */
869     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_PAD_CTL_PAD index */
870     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_PAD_CTL_PAD index */
871     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_PAD_CTL_PAD index */
872     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_PAD_CTL_PAD index */
873     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_PAD_CTL_PAD index */
874     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_PAD_CTL_PAD index */
875     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_PAD_CTL_PAD index */
876     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_PAD_CTL_PAD index */
877     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_PAD_CTL_PAD index */
878     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_PAD_CTL_PAD index */
879     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_PAD_CTL_PAD index */
880     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_PAD_CTL_PAD index */
881     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_PAD_CTL_PAD index */
882     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_PAD_CTL_PAD index */
883     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_PAD_CTL_PAD index */
884     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_PAD_CTL_PAD index */
885     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_PAD_CTL_PAD index */
886     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_PAD_CTL_PAD index */
887     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_PAD_CTL_PAD index */
888     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_PAD_CTL_PAD index */
889     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_PAD_CTL_PAD index */
890     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_PAD_CTL_PAD index */
891     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_PAD_CTL_PAD index */
892     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_PAD_CTL_PAD index */
893     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_PAD_CTL_PAD index */
894     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_PAD_CTL_PAD index */
895     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_PAD_CTL_PAD index */
896     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_PAD_CTL_PAD index */
897     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_PAD_CTL_PAD index */
898     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_PAD_CTL_PAD index */
899     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_PAD_CTL_PAD index */
900     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_PAD_CTL_PAD index */
901     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_PAD_CTL_PAD index */
902     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_PAD_CTL_PAD index */
903     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_PAD_CTL_PAD index */
904     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_PAD_CTL_PAD index */
905     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_PAD_CTL_PAD index */
906     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_PAD_CTL_PAD index */
907     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_PAD_CTL_PAD index */
908     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_PAD_CTL_PAD index */
909     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_PAD_CTL_PAD index */
910     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_PAD_CTL_PAD index */
911     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_PAD_CTL_PAD index */
912     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_PAD_CTL_PAD index */
913     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_PAD_CTL_PAD index */
914     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_PAD_CTL_PAD index */
915     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_PAD_CTL_PAD index */
916     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_PAD_CTL_PAD index */
917     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_PAD_CTL_PAD index */
918     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_PAD_CTL_PAD index */
919     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_PAD_CTL_PAD index */
920     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_PAD_CTL_PAD index */
921     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_PAD_CTL_PAD index */
922     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_PAD_CTL_PAD index */
923     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_PAD_CTL_PAD index */
924     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_PAD_CTL_PAD index */
925     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_PAD_CTL_PAD index */
926     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_PAD_CTL_PAD index */
927     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_PAD_CTL_PAD index */
928     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_PAD_CTL_PAD index */
929     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_PAD_CTL_PAD index */
930     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_PAD_CTL_PAD index */
931     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_PAD_CTL_PAD index */
932     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_PAD_CTL_PAD index */
933     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_PAD_CTL_PAD index */
934     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_PAD_CTL_PAD index */
935     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_PAD_CTL_PAD index */
936     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_PAD_CTL_PAD index */
937     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_PAD_CTL_PAD index */
938     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_PAD_CTL_PAD index */
939     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_PAD_CTL_PAD index */
940     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_PAD_CTL_PAD index */
941     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_PAD_CTL_PAD index */
942     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_PAD_CTL_PAD index */
943     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_PAD_CTL_PAD index */
944     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_PAD_CTL_PAD index */
945     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_PAD_CTL_PAD index */
946     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_PAD_CTL_PAD index */
947     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_12_DUMMY = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
948     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 118U,      /**< IOMUXC SW_PAD_CTL_PAD index */
949     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 119U,      /**< IOMUXC SW_PAD_CTL_PAD index */
950     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 120U,      /**< IOMUXC SW_PAD_CTL_PAD index */
951     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 121U,      /**< IOMUXC SW_PAD_CTL_PAD index */
952     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 122U,      /**< IOMUXC SW_PAD_CTL_PAD index */
953     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 123U,      /**< IOMUXC SW_PAD_CTL_PAD index */
954     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 124U,      /**< IOMUXC SW_PAD_CTL_PAD index */
955     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 125U,      /**< IOMUXC SW_PAD_CTL_PAD index */
956     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 126U,      /**< IOMUXC SW_PAD_CTL_PAD index */
957     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 127U,      /**< IOMUXC SW_PAD_CTL_PAD index */
958     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 128U,      /**< IOMUXC SW_PAD_CTL_PAD index */
959     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 129U,      /**< IOMUXC SW_PAD_CTL_PAD index */
960     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 130U,      /**< IOMUXC SW_PAD_CTL_PAD index */
961     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 131U,      /**< IOMUXC SW_PAD_CTL_PAD index */
962     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_00 = 132U,      /**< IOMUXC SW_PAD_CTL_PAD index */
963     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_01 = 133U,      /**< IOMUXC SW_PAD_CTL_PAD index */
964     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_02 = 134U,      /**< IOMUXC SW_PAD_CTL_PAD index */
965     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_03 = 135U,      /**< IOMUXC SW_PAD_CTL_PAD index */
966     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_04 = 136U,      /**< IOMUXC SW_PAD_CTL_PAD index */
967     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_05 = 137U,      /**< IOMUXC SW_PAD_CTL_PAD index */
968     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_06 = 138U,      /**< IOMUXC SW_PAD_CTL_PAD index */
969     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_07 = 139U,      /**< IOMUXC SW_PAD_CTL_PAD index */
970     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_08 = 140U,      /**< IOMUXC SW_PAD_CTL_PAD index */
971     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_09 = 141U,      /**< IOMUXC SW_PAD_CTL_PAD index */
972     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_10 = 142U,      /**< IOMUXC SW_PAD_CTL_PAD index */
973     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_11 = 143U,      /**< IOMUXC SW_PAD_CTL_PAD index */
974     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_12 = 144U,      /**< IOMUXC SW_PAD_CTL_PAD index */
975     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B2_13 = 145U,      /**< IOMUXC SW_PAD_CTL_PAD index */
976 } iomuxc_sw_pad_ctl_pad_t;
977 
978 /* @} */
979 
980 /*!
981  * @brief Enumeration for the IOMUXC select input
982  *
983  * Defines the enumeration for the IOMUXC select input collections.
984  */
985 typedef enum _iomuxc_select_input
986 {
987     kIOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT = 0U,  /**< IOMUXC select input index */
988     kIOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT = 1U,  /**< IOMUXC select input index */
989     kIOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT = 2U,  /**< IOMUXC select input index */
990     kIOMUXC_ECAT_ECAT_RX_CLK_0_SELECT_INPUT = 3U,  /**< IOMUXC select input index */
991     kIOMUXC_ECAT_ECAT_RX_CLK_1_SELECT_INPUT = 4U,  /**< IOMUXC select input index */
992     kIOMUXC_ECAT_ECAT_RX_DATA0_0_SELECT_INPUT = 5U, /**< IOMUXC select input index */
993     kIOMUXC_ECAT_ECAT_RX_DATA0_1_SELECT_INPUT = 6U, /**< IOMUXC select input index */
994     kIOMUXC_ECAT_ECAT_RX_DATA1_0_SELECT_INPUT = 7U, /**< IOMUXC select input index */
995     kIOMUXC_ECAT_ECAT_RX_DATA1_1_SELECT_INPUT = 8U, /**< IOMUXC select input index */
996     kIOMUXC_ECAT_ECAT_RX_DATA2_0_SELECT_INPUT = 9U, /**< IOMUXC select input index */
997     kIOMUXC_ECAT_ECAT_RX_DATA2_1_SELECT_INPUT = 10U, /**< IOMUXC select input index */
998     kIOMUXC_ECAT_ECAT_RX_DATA3_0_SELECT_INPUT = 11U, /**< IOMUXC select input index */
999     kIOMUXC_ECAT_ECAT_RX_DATA3_1_SELECT_INPUT = 12U, /**< IOMUXC select input index */
1000     kIOMUXC_ECAT_ECAT_RX_DV_0_SELECT_INPUT = 13U,  /**< IOMUXC select input index */
1001     kIOMUXC_ECAT_ECAT_RX_DV_1_SELECT_INPUT = 14U,  /**< IOMUXC select input index */
1002     kIOMUXC_ECAT_ECAT_RX_ER_0_SELECT_INPUT = 15U,  /**< IOMUXC select input index */
1003     kIOMUXC_ECAT_ECAT_RX_ER_1_SELECT_INPUT = 16U,  /**< IOMUXC select input index */
1004     kIOMUXC_ECAT_ECAT_TX_CLK_0_SELECT_INPUT = 17U, /**< IOMUXC select input index */
1005     kIOMUXC_ECAT_ECAT_TX_CLK_1_SELECT_INPUT = 18U, /**< IOMUXC select input index */
1006     kIOMUXC_ECAT_MDIO_DATA_IN_SELECT_INPUT = 19U,  /**< IOMUXC select input index */
1007     kIOMUXC_ECAT_PROM_DATA_IN_SELECT_INPUT = 20U,  /**< IOMUXC select input index */
1008     kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 = 21U, /**< IOMUXC select input index */
1009     kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 = 22U, /**< IOMUXC select input index */
1010     kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 = 23U, /**< IOMUXC select input index */
1011     kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 = 24U, /**< IOMUXC select input index */
1012     kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 = 25U, /**< IOMUXC select input index */
1013     kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 = 26U, /**< IOMUXC select input index */
1014     kIOMUXC_FLEXPWM2_IPP_IND_PWMA_SELECT_INPUT_0 = 27U, /**< IOMUXC select input index */
1015     kIOMUXC_FLEXPWM2_IPP_IND_PWMA_SELECT_INPUT_1 = 28U, /**< IOMUXC select input index */
1016     kIOMUXC_FLEXPWM2_IPP_IND_PWMA_SELECT_INPUT_2 = 29U, /**< IOMUXC select input index */
1017     kIOMUXC_FLEXPWM2_IPP_IND_PWMB_SELECT_INPUT_0 = 30U, /**< IOMUXC select input index */
1018     kIOMUXC_FLEXPWM2_IPP_IND_PWMB_SELECT_INPUT_1 = 31U, /**< IOMUXC select input index */
1019     kIOMUXC_FLEXPWM2_IPP_IND_PWMB_SELECT_INPUT_2 = 32U, /**< IOMUXC select input index */
1020     kIOMUXC_FLEXPWM3_IPP_IND_PWMA_SELECT_INPUT_0 = 33U, /**< IOMUXC select input index */
1021     kIOMUXC_FLEXPWM3_IPP_IND_PWMA_SELECT_INPUT_1 = 34U, /**< IOMUXC select input index */
1022     kIOMUXC_FLEXPWM3_IPP_IND_PWMA_SELECT_INPUT_2 = 35U, /**< IOMUXC select input index */
1023     kIOMUXC_FLEXPWM3_IPP_IND_PWMA_SELECT_INPUT_3 = 36U, /**< IOMUXC select input index */
1024     kIOMUXC_FLEXPWM3_IPP_IND_PWMB_SELECT_INPUT_0 = 37U, /**< IOMUXC select input index */
1025     kIOMUXC_FLEXPWM3_IPP_IND_PWMB_SELECT_INPUT_1 = 38U, /**< IOMUXC select input index */
1026     kIOMUXC_FLEXPWM3_IPP_IND_PWMB_SELECT_INPUT_2 = 39U, /**< IOMUXC select input index */
1027     kIOMUXC_FLEXPWM3_IPP_IND_PWMB_SELECT_INPUT_3 = 40U, /**< IOMUXC select input index */
1028     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_DQS_FA_SELECT_INPUT = 41U, /**< IOMUXC select input index */
1029     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_DQS_FB_SELECT_INPUT = 42U, /**< IOMUXC select input index */
1030     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 43U, /**< IOMUXC select input index */
1031     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 44U, /**< IOMUXC select input index */
1032     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 45U, /**< IOMUXC select input index */
1033     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 46U, /**< IOMUXC select input index */
1034     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT4_SELECT_INPUT = 47U, /**< IOMUXC select input index */
1035     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT5_SELECT_INPUT = 48U, /**< IOMUXC select input index */
1036     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT6_SELECT_INPUT = 49U, /**< IOMUXC select input index */
1037     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_IO_FB_BIT7_SELECT_INPUT = 50U, /**< IOMUXC select input index */
1038     kIOMUXC_FLEXSPI1_BUS2BIT_IPP_IND_SCK_FB_SELECT_INPUT = 51U, /**< IOMUXC select input index */
1039     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_DQS_FA_SELECT_INPUT = 52U, /**< IOMUXC select input index */
1040     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_DQS_FB_SELECT_INPUT = 53U, /**< IOMUXC select input index */
1041     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 54U, /**< IOMUXC select input index */
1042     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 55U, /**< IOMUXC select input index */
1043     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 56U, /**< IOMUXC select input index */
1044     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 57U, /**< IOMUXC select input index */
1045     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 58U, /**< IOMUXC select input index */
1046     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 59U, /**< IOMUXC select input index */
1047     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 60U, /**< IOMUXC select input index */
1048     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 61U, /**< IOMUXC select input index */
1049     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_SCK_FA_SELECT_INPUT = 62U, /**< IOMUXC select input index */
1050     kIOMUXC_FLEXSPI2_BUS2BIT_IPP_IND_SCK_FB_SELECT_INPUT = 63U, /**< IOMUXC select input index */
1051     kIOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT = 64U,    /**< IOMUXC select input index */
1052     kIOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT = 65U,    /**< IOMUXC select input index */
1053     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_0 = 66U,  /**< IOMUXC select input index */
1054     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_1 = 67U,  /**< IOMUXC select input index */
1055     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_2 = 68U,  /**< IOMUXC select input index */
1056     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_3 = 69U,  /**< IOMUXC select input index */
1057     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_4 = 70U,  /**< IOMUXC select input index */
1058     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5 = 71U,  /**< IOMUXC select input index */
1059     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6 = 72U,  /**< IOMUXC select input index */
1060     kIOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7 = 73U,  /**< IOMUXC select input index */
1061     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_0 = 74U,  /**< IOMUXC select input index */
1062     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_1 = 75U,  /**< IOMUXC select input index */
1063     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_2 = 76U,  /**< IOMUXC select input index */
1064     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_3 = 77U,  /**< IOMUXC select input index */
1065     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_4 = 78U,  /**< IOMUXC select input index */
1066     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5 = 79U,  /**< IOMUXC select input index */
1067     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6 = 80U,  /**< IOMUXC select input index */
1068     kIOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7 = 81U,  /**< IOMUXC select input index */
1069     kIOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT = 82U, /**< IOMUXC select input index */
1070     kIOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT = 83U, /**< IOMUXC select input index */
1071     kIOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT = 84U, /**< IOMUXC select input index */
1072     kIOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT = 85U, /**< IOMUXC select input index */
1073     kIOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 86U, /**< IOMUXC select input index */
1074     kIOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 87U, /**< IOMUXC select input index */
1075     kIOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 88U, /**< IOMUXC select input index */
1076     kIOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 89U, /**< IOMUXC select input index */
1077     kIOMUXC_LPSPI3_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 90U, /**< IOMUXC select input index */
1078     kIOMUXC_LPSPI3_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 = 91U, /**< IOMUXC select input index */
1079     kIOMUXC_LPSPI3_IPP_IND_LPSPI_PCS_SELECT_INPUT_2 = 92U, /**< IOMUXC select input index */
1080     kIOMUXC_LPSPI3_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 = 93U, /**< IOMUXC select input index */
1081     kIOMUXC_LPSPI3_IPP_IND_LPSPI_SCK_SELECT_INPUT = 94U, /**< IOMUXC select input index */
1082     kIOMUXC_LPSPI3_IPP_IND_LPSPI_SDI_SELECT_INPUT = 95U, /**< IOMUXC select input index */
1083     kIOMUXC_LPSPI3_IPP_IND_LPSPI_SDO_SELECT_INPUT = 96U, /**< IOMUXC select input index */
1084     kIOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 97U, /**< IOMUXC select input index */
1085     kIOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT = 98U, /**< IOMUXC select input index */
1086     kIOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT = 99U, /**< IOMUXC select input index */
1087     kIOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT = 100U, /**< IOMUXC select input index */
1088     kIOMUXC_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 101U, /**< IOMUXC select input index */
1089     kIOMUXC_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 = 102U, /**< IOMUXC select input index */
1090     kIOMUXC_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_2 = 103U, /**< IOMUXC select input index */
1091     kIOMUXC_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 = 104U, /**< IOMUXC select input index */
1092     kIOMUXC_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 105U, /**< IOMUXC select input index */
1093     kIOMUXC_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 106U, /**< IOMUXC select input index */
1094     kIOMUXC_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 107U, /**< IOMUXC select input index */
1095     kIOMUXC_LPSPI6_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 108U, /**< IOMUXC select input index */
1096     kIOMUXC_LPSPI6_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 = 109U, /**< IOMUXC select input index */
1097     kIOMUXC_LPSPI6_IPP_IND_LPSPI_PCS_SELECT_INPUT_2 = 110U, /**< IOMUXC select input index */
1098     kIOMUXC_LPSPI6_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 = 111U, /**< IOMUXC select input index */
1099     kIOMUXC_LPSPI6_IPP_IND_LPSPI_SCK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
1100     kIOMUXC_LPSPI6_IPP_IND_LPSPI_SDI_SELECT_INPUT = 113U, /**< IOMUXC select input index */
1101     kIOMUXC_LPSPI6_IPP_IND_LPSPI_SDO_SELECT_INPUT = 114U, /**< IOMUXC select input index */
1102     kIOMUXC_LPUART10_IPP_IND_LPUART_RXD_SELECT_INPUT = 115U, /**< IOMUXC select input index */
1103     kIOMUXC_LPUART10_IPP_IND_LPUART_TXD_SELECT_INPUT = 116U, /**< IOMUXC select input index */
1104     kIOMUXC_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 117U, /**< IOMUXC select input index */
1105     kIOMUXC_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 118U, /**< IOMUXC select input index */
1106     kIOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 119U, /**< IOMUXC select input index */
1107     kIOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT = 120U, /**< IOMUXC select input index */
1108     kIOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT = 121U, /**< IOMUXC select input index */
1109     kIOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 122U, /**< IOMUXC select input index */
1110     kIOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 123U, /**< IOMUXC select input index */
1111     kIOMUXC_LPUART5_IPP_IND_LPUART_DCD_N_SELECT_INPUT = 124U, /**< IOMUXC select input index */
1112     kIOMUXC_LPUART5_IPP_IND_LPUART_DSR_N_SELECT_INPUT = 125U, /**< IOMUXC select input index */
1113     kIOMUXC_LPUART5_IPP_IND_LPUART_RI_N_SELECT_INPUT = 126U, /**< IOMUXC select input index */
1114     kIOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT = 127U, /**< IOMUXC select input index */
1115     kIOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT = 128U, /**< IOMUXC select input index */
1116     kIOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 129U, /**< IOMUXC select input index */
1117     kIOMUXC_LPUART6_IPP_IND_LPUART_DCD_N_SELECT_INPUT = 130U, /**< IOMUXC select input index */
1118     kIOMUXC_LPUART6_IPP_IND_LPUART_DSR_N_SELECT_INPUT = 131U, /**< IOMUXC select input index */
1119     kIOMUXC_LPUART6_IPP_IND_LPUART_RI_N_SELECT_INPUT = 132U, /**< IOMUXC select input index */
1120     kIOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT = 133U, /**< IOMUXC select input index */
1121     kIOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT = 134U, /**< IOMUXC select input index */
1122     kIOMUXC_LPUART8_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 135U, /**< IOMUXC select input index */
1123     kIOMUXC_LPUART8_IPP_IND_LPUART_RXD_SELECT_INPUT = 136U, /**< IOMUXC select input index */
1124     kIOMUXC_LPUART8_IPP_IND_LPUART_TXD_SELECT_INPUT = 137U, /**< IOMUXC select input index */
1125     kIOMUXC_LPUART9_IPP_IND_LPUART_RXD_SELECT_INPUT = 138U, /**< IOMUXC select input index */
1126     kIOMUXC_LPUART9_IPP_IND_LPUART_TXD_SELECT_INPUT = 139U, /**< IOMUXC select input index */
1127     kIOMUXC_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 140U, /**< IOMUXC select input index */
1128     kIOMUXC_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 141U, /**< IOMUXC select input index */
1129     kIOMUXC_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 142U, /**< IOMUXC select input index */
1130     kIOMUXC_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 143U, /**< IOMUXC select input index */
1131     kIOMUXC_NETC_EMDIO_IN_SELECT_INPUT = 190U,     /**< IOMUXC select input index */
1132     kIOMUXC_NETC_ETH2_COL_SELECT_INPUT = 191U,     /**< IOMUXC select input index */
1133     kIOMUXC_NETC_ETH2_CRS_SELECT_INPUT = 192U,     /**< IOMUXC select input index */
1134     kIOMUXC_NETC_ETH2_SLV_MDC_IN_SELECT_INPUT = 193U, /**< IOMUXC select input index */
1135     kIOMUXC_NETC_ETH2_SLV_MDIO_IN_SELECT_INPUT = 194U, /**< IOMUXC select input index */
1136     kIOMUXC_NETC_ETH3_COL_SELECT_INPUT = 195U,     /**< IOMUXC select input index */
1137     kIOMUXC_NETC_ETH3_CRS_SELECT_INPUT = 196U,     /**< IOMUXC select input index */
1138     kIOMUXC_NETC_ETH3_SLV_MDC_IN_SELECT_INPUT = 197U, /**< IOMUXC select input index */
1139     kIOMUXC_NETC_ETH3_SLV_MDIO_IN_SELECT_INPUT = 198U, /**< IOMUXC select input index */
1140     kIOMUXC_NETC_ETH4_COL_SELECT_INPUT = 199U,     /**< IOMUXC select input index */
1141     kIOMUXC_NETC_ETH4_CRS_SELECT_INPUT = 200U,     /**< IOMUXC select input index */
1142     kIOMUXC_NETC_ETH4_SLV_MDC_IN_SELECT_INPUT = 201U, /**< IOMUXC select input index */
1143     kIOMUXC_NETC_ETH4_SLV_MDIO_IN_SELECT_INPUT = 202U, /**< IOMUXC select input index */
1144     kIOMUXC_NETC_TMR_TRIG1_SELECT_INPUT = 203U,    /**< IOMUXC select input index */
1145     kIOMUXC_NETC_TMR_TRIG2_SELECT_INPUT = 204U,    /**< IOMUXC select input index */
1146     kIOMUXC_NETC_CLKGEN_IPP_TMR_CLK_SELECT_INPUT = 205U, /**< IOMUXC select input index */
1147     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RX_CLK_SELECT_INPUT = 206U, /**< IOMUXC select input index */
1148     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RX_DV_SELECT_INPUT = 207U, /**< IOMUXC select input index */
1149     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RX_ER_SELECT_INPUT = 208U, /**< IOMUXC select input index */
1150     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RXD_SELECT_INPUT_0 = 209U, /**< IOMUXC select input index */
1151     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RXD_SELECT_INPUT_1 = 210U, /**< IOMUXC select input index */
1152     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RXD_SELECT_INPUT_2 = 211U, /**< IOMUXC select input index */
1153     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_RXD_SELECT_INPUT_3 = 212U, /**< IOMUXC select input index */
1154     kIOMUXC_NETC_PINMUX_IPP_IND_ETH0_TX_CLK_SELECT_INPUT = 213U, /**< IOMUXC select input index */
1155     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RX_CLK_SELECT_INPUT = 214U, /**< IOMUXC select input index */
1156     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RX_DV_SELECT_INPUT = 215U, /**< IOMUXC select input index */
1157     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RX_ER_SELECT_INPUT = 216U, /**< IOMUXC select input index */
1158     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RXD_SELECT_INPUT_0 = 217U, /**< IOMUXC select input index */
1159     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RXD_SELECT_INPUT_1 = 218U, /**< IOMUXC select input index */
1160     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RXD_SELECT_INPUT_2 = 219U, /**< IOMUXC select input index */
1161     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_RXD_SELECT_INPUT_3 = 220U, /**< IOMUXC select input index */
1162     kIOMUXC_NETC_PINMUX_IPP_IND_ETH2_TX_CLK_SELECT_INPUT = 221U, /**< IOMUXC select input index */
1163     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RX_CLK_SELECT_INPUT = 222U, /**< IOMUXC select input index */
1164     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RX_DV_SELECT_INPUT = 223U, /**< IOMUXC select input index */
1165     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RX_ER_SELECT_INPUT = 224U, /**< IOMUXC select input index */
1166     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RXD_SELECT_INPUT_0 = 225U, /**< IOMUXC select input index */
1167     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RXD_SELECT_INPUT_1 = 226U, /**< IOMUXC select input index */
1168     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RXD_SELECT_INPUT_2 = 227U, /**< IOMUXC select input index */
1169     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_RXD_SELECT_INPUT_3 = 228U, /**< IOMUXC select input index */
1170     kIOMUXC_NETC_PINMUX_IPP_IND_ETH3_TX_CLK_SELECT_INPUT = 229U, /**< IOMUXC select input index */
1171     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RX_CLK_SELECT_INPUT = 230U, /**< IOMUXC select input index */
1172     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RX_DV_SELECT_INPUT = 231U, /**< IOMUXC select input index */
1173     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RX_ER_SELECT_INPUT = 232U, /**< IOMUXC select input index */
1174     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RXD_SELECT_INPUT_0 = 233U, /**< IOMUXC select input index */
1175     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RXD_SELECT_INPUT_1 = 234U, /**< IOMUXC select input index */
1176     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RXD_SELECT_INPUT_2 = 235U, /**< IOMUXC select input index */
1177     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_RXD_SELECT_INPUT_3 = 236U, /**< IOMUXC select input index */
1178     kIOMUXC_NETC_PINMUX_IPP_IND_ETH4_TX_CLK_SELECT_INPUT = 237U, /**< IOMUXC select input index */
1179     kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 238U, /**< IOMUXC select input index */
1180     kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 239U, /**< IOMUXC select input index */
1181     kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 240U, /**< IOMUXC select input index */
1182     kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 241U, /**< IOMUXC select input index */
1183     kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 242U, /**< IOMUXC select input index */
1184     kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 243U, /**< IOMUXC select input index */
1185     kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 244U, /**< IOMUXC select input index */
1186     kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 245U, /**< IOMUXC select input index */
1187     kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 246U, /**< IOMUXC select input index */
1188     kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 247U, /**< IOMUXC select input index */
1189     kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 248U, /**< IOMUXC select input index */
1190     kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 249U, /**< IOMUXC select input index */
1191     kIOMUXC_QTIMER5_TMR0_INPUT_SELECT_INPUT = 250U, /**< IOMUXC select input index */
1192     kIOMUXC_QTIMER5_TMR1_INPUT_SELECT_INPUT = 251U, /**< IOMUXC select input index */
1193     kIOMUXC_QTIMER5_TMR2_INPUT_SELECT_INPUT = 252U, /**< IOMUXC select input index */
1194     kIOMUXC_QTIMER6_TMR0_INPUT_SELECT_INPUT = 253U, /**< IOMUXC select input index */
1195     kIOMUXC_QTIMER6_TMR1_INPUT_SELECT_INPUT = 254U, /**< IOMUXC select input index */
1196     kIOMUXC_QTIMER6_TMR2_INPUT_SELECT_INPUT = 255U, /**< IOMUXC select input index */
1197     kIOMUXC_QTIMER7_TMR0_INPUT_SELECT_INPUT = 256U, /**< IOMUXC select input index */
1198     kIOMUXC_QTIMER7_TMR1_INPUT_SELECT_INPUT = 257U, /**< IOMUXC select input index */
1199     kIOMUXC_QTIMER8_TMR0_INPUT_SELECT_INPUT = 258U, /**< IOMUXC select input index */
1200     kIOMUXC_QTIMER8_TMR1_INPUT_SELECT_INPUT = 259U, /**< IOMUXC select input index */
1201     kIOMUXC_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 260U, /**< IOMUXC select input index */
1202     kIOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 261U, /**< IOMUXC select input index */
1203     kIOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 262U, /**< IOMUXC select input index */
1204     kIOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 = 263U, /**< IOMUXC select input index */
1205     kIOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 264U, /**< IOMUXC select input index */
1206     kIOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 265U, /**< IOMUXC select input index */
1207     kIOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 266U, /**< IOMUXC select input index */
1208     kIOMUXC_SINC1_IPP_IND_EMBIT_SELECT_INPUT_0 = 269U, /**< IOMUXC select input index */
1209     kIOMUXC_SINC1_IPP_IND_EMBIT_SELECT_INPUT_1 = 270U, /**< IOMUXC select input index */
1210     kIOMUXC_SINC1_IPP_IND_EMBIT_SELECT_INPUT_2 = 271U, /**< IOMUXC select input index */
1211     kIOMUXC_SINC1_IPP_IND_EMBIT_SELECT_INPUT_3 = 272U, /**< IOMUXC select input index */
1212     kIOMUXC_SINC1_IPP_IND_EMCLK_SELECT_INPUT_0 = 273U, /**< IOMUXC select input index */
1213     kIOMUXC_SINC1_IPP_IND_EMCLK_SELECT_INPUT_1 = 274U, /**< IOMUXC select input index */
1214     kIOMUXC_SINC1_IPP_IND_EMCLK_SELECT_INPUT_2 = 275U, /**< IOMUXC select input index */
1215     kIOMUXC_SINC1_IPP_IND_EMCLK_SELECT_INPUT_3 = 276U, /**< IOMUXC select input index */
1216     kIOMUXC_SINC2_IPP_IND_EMBIT_SELECT_INPUT_2 = 277U, /**< IOMUXC select input index */
1217     kIOMUXC_SINC2_IPP_IND_EMBIT_SELECT_INPUT_3 = 278U, /**< IOMUXC select input index */
1218     kIOMUXC_SINC2_IPP_IND_EMCLK_SELECT_INPUT_0 = 279U, /**< IOMUXC select input index */
1219     kIOMUXC_SINC2_IPP_IND_EMCLK_SELECT_INPUT_2 = 280U, /**< IOMUXC select input index */
1220     kIOMUXC_SINC2_IPP_IND_EMCLK_SELECT_INPUT_3 = 281U, /**< IOMUXC select input index */
1221     kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 282U,   /**< IOMUXC select input index */
1222     kIOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT = 285U, /**< IOMUXC select input index */
1223     kIOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT = 286U, /**< IOMUXC select input index */
1224     kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 287U,    /**< IOMUXC select input index */
1225     kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 288U,    /**< IOMUXC select input index */
1226     kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 289U, /**< IOMUXC select input index */
1227     kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 290U,  /**< IOMUXC select input index */
1228     kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 291U, /**< IOMUXC select input index */
1229     kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 292U,  /**< IOMUXC select input index */
1230     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_14 = 293U,  /**< IOMUXC select input index */
1231     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_15 = 294U,  /**< IOMUXC select input index */
1232     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_17 = 295U,  /**< IOMUXC select input index */
1233     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_18 = 296U,  /**< IOMUXC select input index */
1234     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_19 = 297U,  /**< IOMUXC select input index */
1235     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_20 = 298U,  /**< IOMUXC select input index */
1236     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_21 = 299U,  /**< IOMUXC select input index */
1237     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_22 = 300U,  /**< IOMUXC select input index */
1238     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_23 = 301U,  /**< IOMUXC select input index */
1239     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_24 = 302U,  /**< IOMUXC select input index */
1240     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_25 = 303U,  /**< IOMUXC select input index */
1241     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_26 = 304U,  /**< IOMUXC select input index */
1242     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_27 = 305U,  /**< IOMUXC select input index */
1243     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_28 = 306U,  /**< IOMUXC select input index */
1244     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_29 = 307U,  /**< IOMUXC select input index */
1245     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_30 = 308U,  /**< IOMUXC select input index */
1246     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_31 = 309U,  /**< IOMUXC select input index */
1247     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_32 = 310U,  /**< IOMUXC select input index */
1248     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_33 = 311U,  /**< IOMUXC select input index */
1249     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_34 = 312U,  /**< IOMUXC select input index */
1250     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_35 = 313U,  /**< IOMUXC select input index */
1251     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_36 = 314U,  /**< IOMUXC select input index */
1252     kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_37 = 315U,  /**< IOMUXC select input index */
1253     kIOMUXC_XSPI_SLV_IPP_IND_CS_SELECT_INPUT = 344U, /**< IOMUXC select input index */
1254     kIOMUXC_XSPI_SLV_IPP_IND_DQS_SELECT_INPUT = 345U, /**< IOMUXC select input index */
1255     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0 = 346U, /**< IOMUXC select input index */
1256     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1 = 347U, /**< IOMUXC select input index */
1257     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2 = 348U, /**< IOMUXC select input index */
1258     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3 = 349U, /**< IOMUXC select input index */
1259     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4 = 350U, /**< IOMUXC select input index */
1260     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5 = 351U, /**< IOMUXC select input index */
1261     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6 = 352U, /**< IOMUXC select input index */
1262     kIOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7 = 353U, /**< IOMUXC select input index */
1263     kIOMUXC_XSPI_SLV_IPP_IND_SCK_SELECT_INPUT = 354U, /**< IOMUXC select input index */
1264 } iomuxc_select_input_t;
1265 
1266 /*!
1267  * @addtogroup iomuxc_aon_pads
1268  * @{ */
1269 
1270 /*******************************************************************************
1271  * Definitions
1272 *******************************************************************************/
1273 
1274 /*!
1275  * @brief Enumeration for the IOMUXC_AON SW_MUX_CTL_PAD
1276  *
1277  * Defines the enumeration for the IOMUXC_AON SW_MUX_CTL_PAD collections.
1278  */
1279 typedef enum _iomuxc_aon_sw_mux_ctl_pad
1280 {
1281     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_00 = 0U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1282     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_01 = 1U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1283     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_02 = 2U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1284     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_03 = 3U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1285     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_04 = 4U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1286     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_05 = 5U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1287     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_06 = 6U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1288     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_07 = 7U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1289     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_08 = 8U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1290     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_09 = 9U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1291     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_10 = 10U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1292     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_11 = 11U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1293     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_12 = 12U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1294     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_13 = 13U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1295     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_14 = 14U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1296     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_15 = 15U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1297     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_16 = 16U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1298     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_17 = 17U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1299     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_18 = 18U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1300     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_19 = 19U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1301     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_20 = 20U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1302     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_21 = 21U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1303     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_22 = 22U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1304     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_23 = 23U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1305     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_24 = 24U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1306     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_25 = 25U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1307     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_26 = 26U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1308     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_27 = 27U,  /**< IOMUXC SW_MUX_CTL_PAD index */
1309     kIOMUXC_AON_SW_MUX_CTL_PAD_GPIO_AON_28_DUMMY = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
1310 } iomuxc_aon_sw_mux_ctl_pad_t;
1311 
1312 /* @} */
1313 
1314 /*!
1315  * @addtogroup iomuxc_aon_pads
1316  * @{ */
1317 
1318 /*******************************************************************************
1319  * Definitions
1320 *******************************************************************************/
1321 
1322 /*!
1323  * @brief Enumeration for the IOMUXC_AON SW_PAD_CTL_PAD
1324  *
1325  * Defines the enumeration for the IOMUXC_AON SW_PAD_CTL_PAD collections.
1326  */
1327 typedef enum _iomuxc_aon_sw_pad_ctl_pad
1328 {
1329     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_00 = 0U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1330     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_01 = 1U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1331     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_02 = 2U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1332     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_03 = 3U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1333     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_04 = 4U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1334     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_05 = 5U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1335     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_06 = 6U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1336     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_07 = 7U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1337     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_08 = 8U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1338     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_09 = 9U,   /**< IOMUXC SW_PAD_CTL_PAD index */
1339     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_10 = 10U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1340     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_11 = 11U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1341     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_12 = 12U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1342     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_13 = 13U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1343     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_14 = 14U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1344     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_15 = 15U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1345     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_16 = 16U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1346     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_17 = 17U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1347     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_18 = 18U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1348     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_19 = 19U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1349     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_20 = 20U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1350     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_21 = 21U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1351     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_22 = 22U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1352     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_23 = 23U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1353     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_24 = 24U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1354     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_25 = 25U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1355     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_26 = 26U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1356     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_27 = 27U,  /**< IOMUXC SW_PAD_CTL_PAD index */
1357     kIOMUXC_AON_SW_PAD_CTL_PAD_GPIO_AON_28_DUMMY = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
1358 } iomuxc_aon_sw_pad_ctl_pad_t;
1359 
1360 /* @} */
1361 
1362 /*!
1363  * @brief Enumeration for the IOMUXC_AON select input
1364  *
1365  * Defines the enumeration for the IOMUXC_AON select input collections.
1366  */
1367 typedef enum _iomuxc_aon_select_input
1368 {
1369     kIOMUXC_AON_I3C1_PIN_SCL_IN_SELECT_INPUT = 0U, /**< IOMUXC select input index */
1370     kIOMUXC_AON_I3C1_PIN_SDA_IN_SELECT_INPUT = 1U, /**< IOMUXC select input index */
1371     kIOMUXC_AON_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT = 2U, /**< IOMUXC select input index */
1372     kIOMUXC_AON_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT = 3U, /**< IOMUXC select input index */
1373     kIOMUXC_AON_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT = 4U, /**< IOMUXC select input index */
1374     kIOMUXC_AON_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT = 5U, /**< IOMUXC select input index */
1375     kIOMUXC_AON_LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */
1376     kIOMUXC_AON_LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 = 7U, /**< IOMUXC select input index */
1377     kIOMUXC_AON_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT = 8U, /**< IOMUXC select input index */
1378     kIOMUXC_AON_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT = 9U, /**< IOMUXC select input index */
1379     kIOMUXC_AON_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT = 10U, /**< IOMUXC select input index */
1380     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 11U, /**< IOMUXC select input index */
1381     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 = 12U, /**< IOMUXC select input index */
1382     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 = 13U, /**< IOMUXC select input index */
1383     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT = 14U, /**< IOMUXC select input index */
1384     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT = 15U, /**< IOMUXC select input index */
1385     kIOMUXC_AON_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT = 16U, /**< IOMUXC select input index */
1386     kIOMUXC_AON_LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_1 = 17U, /**< IOMUXC select input index */
1387     kIOMUXC_AON_LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_2 = 18U, /**< IOMUXC select input index */
1388     kIOMUXC_AON_LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_3 = 19U, /**< IOMUXC select input index */
1389     kIOMUXC_AON_LPUART1_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 20U, /**< IOMUXC select input index */
1390     kIOMUXC_AON_LPUART1_IPP_IND_LPUART_DCD_N_SELECT_INPUT = 21U, /**< IOMUXC select input index */
1391     kIOMUXC_AON_LPUART1_IPP_IND_LPUART_DSR_N_SELECT_INPUT = 22U, /**< IOMUXC select input index */
1392     kIOMUXC_AON_LPUART12_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 23U, /**< IOMUXC select input index */
1393     kIOMUXC_AON_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 24U, /**< IOMUXC select input index */
1394     kIOMUXC_AON_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 25U, /**< IOMUXC select input index */
1395     kIOMUXC_AON_LPUART2_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 26U, /**< IOMUXC select input index */
1396     kIOMUXC_AON_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT = 27U, /**< IOMUXC select input index */
1397     kIOMUXC_AON_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT = 28U, /**< IOMUXC select input index */
1398     kIOMUXC_AON_LPUART7_IPP_IND_LPUART_CTS_N_SELECT_INPUT = 29U, /**< IOMUXC select input index */
1399     kIOMUXC_AON_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT = 30U, /**< IOMUXC select input index */
1400     kIOMUXC_AON_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT = 31U, /**< IOMUXC select input index */
1401     kIOMUXC_AON_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 32U, /**< IOMUXC select input index */
1402     kIOMUXC_AON_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 33U, /**< IOMUXC select input index */
1403     kIOMUXC_AON_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 34U, /**< IOMUXC select input index */
1404     kIOMUXC_AON_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 = 35U, /**< IOMUXC select input index */
1405     kIOMUXC_AON_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 36U, /**< IOMUXC select input index */
1406     kIOMUXC_AON_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 37U, /**< IOMUXC select input index */
1407     kIOMUXC_AON_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 38U, /**< IOMUXC select input index */
1408 } iomuxc_aon_select_input_t;
1409 
1410 /*!
1411  * @addtogroup asrc_clock_source_mapping
1412  * @{
1413  */
1414 
1415 /*******************************************************************************
1416  * Definitions
1417  ******************************************************************************/
1418 
1419 /*!
1420  * @brief The ASRC clock source
1421  */
1422 typedef enum _asrc_clock_source
1423 {
1424     kASRC_ClockSourceNotAvalible    = -1,          /**< not avalible */
1425     kASRC_ClockSourceBitClock0_SAI1_TX = 0U,       /**< SAI1 TX */
1426     kASRC_ClockSourceBitClock1_SAI1_RX = 1U,       /**< SAI1 RX */
1427     kASRC_ClockSourceBitClock2_SAI2_TX = 2U,       /**< SAI2 TX */
1428     kASRC_ClockSourceBitClock3_SAI2_RX = 3U,       /**< SAI2 RX */
1429     kASRC_ClockSourceBitClock4_SAI3_TX = 4U,       /**< SAI3 TX */
1430     kASRC_ClockSourceBitClock5_SAI3_RX = 5U,       /**< SAI3 RX */
1431     kASRC_ClockSourceBitClock6_SAI4_TX = 6U,       /**< SAI4 TX */
1432     kASRC_ClockSourceBitClock7_SAI4_RX = 7U,       /**< SAI4 RX */
1433     kASRC_ClockSourceBitClock8_SPDIF_TX = 8U,      /**< SPDIF TX */
1434     kASRC_ClockSourceBitClock9_SPDIF_RX = 9U,      /**< SPDIF RX */
1435     kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */
1436     kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */
1437     kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */
1438     kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */
1439     kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */
1440 } asrc_clock_source_t;
1441 
1442 /* @} */
1443 
1444 typedef enum _xbar_input_signal
1445 {
1446     kXBAR1_InputLogicLow            = 0|0x100U,    /**< LOGIC_LOW output assigned to XBAR1_IN0 input. */
1447     kXBAR1_InputLogicHigh           = 1|0x100U,    /**< LOGIC_HIGH output assigned to XBAR1_IN1 input. */
1448     kXBAR1_InputLogicLow1           = 2|0x100U,    /**< LOGIC_LOW1 output assigned to XBAR1_IN2 input. */
1449     kXBAR1_InputLogicHigh1          = 3|0x100U,    /**< LOGIC_HIGH1 output assigned to XBAR1_IN3 input. */
1450     kXBAR1_InputIomuxXbarInout04    = 4|0x100U,    /**< IOMUX_XBAR_INOUT04 output assigned to XBAR1_IN4 input. */
1451     kXBAR1_InputIomuxXbarInout05    = 5|0x100U,    /**< IOMUX_XBAR_INOUT05 output assigned to XBAR1_IN5 input. */
1452     kXBAR1_InputIomuxXbarInout06    = 6|0x100U,    /**< IOMUX_XBAR_INOUT06 output assigned to XBAR1_IN6 input. */
1453     kXBAR1_InputIomuxXbarInout07    = 7|0x100U,    /**< IOMUX_XBAR_INOUT07 output assigned to XBAR1_IN7 input. */
1454     kXBAR1_InputIomuxXbarInout08    = 8|0x100U,    /**< IOMUX_XBAR_INOUT08 output assigned to XBAR1_IN8 input. */
1455     kXBAR1_InputIomuxXbarInout09    = 9|0x100U,    /**< IOMUX_XBAR_INOUT09 output assigned to XBAR1_IN9 input. */
1456     kXBAR1_InputIomuxXbarInout10    = 10|0x100U,   /**< IOMUX_XBAR_INOUT10 output assigned to XBAR1_IN10 input. */
1457     kXBAR1_InputIomuxXbarInout11    = 11|0x100U,   /**< IOMUX_XBAR_INOUT11 output assigned to XBAR1_IN11 input. */
1458     kXBAR1_InputIomuxXbarInout12    = 12|0x100U,   /**< IOMUX_XBAR_INOUT12 output assigned to XBAR1_IN12 input. */
1459     kXBAR1_InputIomuxXbarInout13    = 13|0x100U,   /**< IOMUX_XBAR_INOUT13 output assigned to XBAR1_IN13 input. */
1460     kXBAR1_InputIomuxXbarInout14    = 14|0x100U,   /**< IOMUX_XBAR_INOUT14 output assigned to XBAR1_IN14 input. */
1461     kXBAR1_InputIomuxXbarInout15    = 15|0x100U,   /**< IOMUX_XBAR_INOUT15 output assigned to XBAR1_IN15 input. */
1462     kXBAR1_InputIomuxXbarInout16    = 16|0x100U,   /**< IOMUX_XBAR_INOUT16 output assigned to XBAR1_IN16 input. */
1463     kXBAR1_InputIomuxXbarInout17    = 17|0x100U,   /**< IOMUX_XBAR_INOUT17 output assigned to XBAR1_IN17 input. */
1464     kXBAR1_InputIomuxXbarInout18    = 18|0x100U,   /**< IOMUX_XBAR_INOUT18 output assigned to XBAR1_IN18 input. */
1465     kXBAR1_InputIomuxXbarInout19    = 19|0x100U,   /**< IOMUX_XBAR_INOUT19 output assigned to XBAR1_IN19 input. */
1466     kXBAR1_InputIomuxXbarInout20    = 20|0x100U,   /**< IOMUX_XBAR_INOUT20 output assigned to XBAR1_IN20 input. */
1467     kXBAR1_InputIomuxXbarInout21    = 21|0x100U,   /**< IOMUX_XBAR_INOUT21 output assigned to XBAR1_IN21 input. */
1468     kXBAR1_InputIomuxXbarInout22    = 22|0x100U,   /**< IOMUX_XBAR_INOUT22 output assigned to XBAR1_IN22 input. */
1469     kXBAR1_InputIomuxXbarInout23    = 23|0x100U,   /**< IOMUX_XBAR_INOUT23 output assigned to XBAR1_IN23 input. */
1470     kXBAR1_InputIomuxXbarInout24    = 24|0x100U,   /**< IOMUX_XBAR_INOUT24 output assigned to XBAR1_IN24 input. */
1471     kXBAR1_InputIomuxXbarInout25    = 25|0x100U,   /**< IOMUX_XBAR_INOUT25 output assigned to XBAR1_IN25 input. */
1472     kXBAR1_InputIomuxXbarInout26    = 26|0x100U,   /**< IOMUX_XBAR_INOUT26 output assigned to XBAR1_IN26 input. */
1473     kXBAR1_InputIomuxXbarInout27    = 27|0x100U,   /**< IOMUX_XBAR_INOUT27 output assigned to XBAR1_IN27 input. */
1474     kXBAR1_InputIomuxXbarInout28    = 28|0x100U,   /**< IOMUX_XBAR_INOUT28 output assigned to XBAR1_IN28 input. */
1475     kXBAR1_InputIomuxXbarInout29    = 29|0x100U,   /**< IOMUX_XBAR_INOUT29 output assigned to XBAR1_IN29 input. */
1476     kXBAR1_InputIomuxXbarInout30    = 30|0x100U,   /**< IOMUX_XBAR_INOUT30 output assigned to XBAR1_IN30 input. */
1477     kXBAR1_InputIomuxXbarInout31    = 31|0x100U,   /**< IOMUX_XBAR_INOUT31 output assigned to XBAR1_IN31 input. */
1478     kXBAR1_InputIomuxXbarInout32    = 32|0x100U,   /**< IOMUX_XBAR_INOUT32 output assigned to XBAR1_IN32 input. */
1479     kXBAR1_InputIomuxXbarInout33    = 33|0x100U,   /**< IOMUX_XBAR_INOUT33 output assigned to XBAR1_IN33 input. */
1480     kXBAR1_InputIomuxXbarInout34    = 34|0x100U,   /**< IOMUX_XBAR_INOUT34 output assigned to XBAR1_IN34 input. */
1481     kXBAR1_InputIomuxXbarInout35    = 35|0x100U,   /**< IOMUX_XBAR_INOUT35 output assigned to XBAR1_IN35 input. */
1482     kXBAR1_InputIomuxXbarInout36    = 36|0x100U,   /**< IOMUX_XBAR_INOUT36 output assigned to XBAR1_IN36 input. */
1483     kXBAR1_InputIomuxXbarInout37    = 37|0x100U,   /**< IOMUX_XBAR_INOUT37 output assigned to XBAR1_IN37 input. */
1484     kXBAR1_InputAcmp1Out            = 38|0x100U,   /**< ACMP1_OUT output assigned to XBAR1_IN38 input. */
1485     kXBAR1_InputAcmp2Out            = 39|0x100U,   /**< ACMP2_OUT output assigned to XBAR1_IN39 input. */
1486     kXBAR1_InputAcmp3Out            = 40|0x100U,   /**< ACMP3_OUT output assigned to XBAR1_IN40 input. */
1487     kXBAR1_InputAcmp4Out            = 41|0x100U,   /**< ACMP4_OUT output assigned to XBAR1_IN41 input. */
1488     kXBAR1_InputQtimer1Timer0       = 42|0x100U,   /**< QTIMER1_TIMER0 output assigned to XBAR1_IN42 input. */
1489     kXBAR1_InputQtimer1Timer1       = 43|0x100U,   /**< QTIMER1_TIMER1 output assigned to XBAR1_IN43 input. */
1490     kXBAR1_InputQtimer1Timer2       = 44|0x100U,   /**< QTIMER1_TIMER2 output assigned to XBAR1_IN44 input. */
1491     kXBAR1_InputQtimer1Timer3       = 45|0x100U,   /**< QTIMER1_TIMER3 output assigned to XBAR1_IN45 input. */
1492     kXBAR1_InputQtimer2Timer0       = 46|0x100U,   /**< QTIMER2_TIMER0 output assigned to XBAR1_IN46 input. */
1493     kXBAR1_InputQtimer2Timer1       = 47|0x100U,   /**< QTIMER2_TIMER1 output assigned to XBAR1_IN47 input. */
1494     kXBAR1_InputQtimer2Timer2       = 48|0x100U,   /**< QTIMER2_TIMER2 output assigned to XBAR1_IN48 input. */
1495     kXBAR1_InputQtimer2Timer3       = 49|0x100U,   /**< QTIMER2_TIMER3 output assigned to XBAR1_IN49 input. */
1496     kXBAR1_InputQtimer3Timer0       = 50|0x100U,   /**< QTIMER3_TIMER0 output assigned to XBAR1_IN50 input. */
1497     kXBAR1_InputQtimer3Timer1       = 51|0x100U,   /**< QTIMER3_TIMER1 output assigned to XBAR1_IN51 input. */
1498     kXBAR1_InputQtimer3Timer2       = 52|0x100U,   /**< QTIMER3_TIMER2 output assigned to XBAR1_IN52 input. */
1499     kXBAR1_InputQtimer3Timer3       = 53|0x100U,   /**< QTIMER3_TIMER3 output assigned to XBAR1_IN53 input. */
1500     kXBAR1_InputQtimer4Timer0       = 54|0x100U,   /**< QTIMER4_TIMER0 output assigned to XBAR1_IN54 input. */
1501     kXBAR1_InputQtimer4Timer1       = 55|0x100U,   /**< QTIMER4_TIMER1 output assigned to XBAR1_IN55 input. */
1502     kXBAR1_InputQtimer4Timer2       = 56|0x100U,   /**< QTIMER4_TIMER2 output assigned to XBAR1_IN56 input. */
1503     kXBAR1_InputQtimer4Timer3       = 57|0x100U,   /**< QTIMER4_TIMER3 output assigned to XBAR1_IN57 input. */
1504     kXBAR1_InputRESERVED58          = 58|0x100U,   /**< XBAR1_IN58 input is reserved. */
1505     kXBAR1_InputRESERVED59          = 59|0x100U,   /**< XBAR1_IN59 input is reserved. */
1506     kXBAR1_InputRESERVED60          = 60|0x100U,   /**< XBAR1_IN60 input is reserved. */
1507     kXBAR1_InputRESERVED61          = 61|0x100U,   /**< XBAR1_IN61 input is reserved. */
1508     kXBAR1_InputRESERVED62          = 62|0x100U,   /**< XBAR1_IN62 input is reserved. */
1509     kXBAR1_InputRESERVED63          = 63|0x100U,   /**< XBAR1_IN63 input is reserved. */
1510     kXBAR1_InputRESERVED64          = 64|0x100U,   /**< XBAR1_IN64 input is reserved. */
1511     kXBAR1_InputRESERVED65          = 65|0x100U,   /**< XBAR1_IN65 input is reserved. */
1512     kXBAR1_InputRESERVED66          = 66|0x100U,   /**< XBAR1_IN66 input is reserved. */
1513     kXBAR1_InputRESERVED67          = 67|0x100U,   /**< XBAR1_IN67 input is reserved. */
1514     kXBAR1_InputRESERVED68          = 68|0x100U,   /**< XBAR1_IN68 input is reserved. */
1515     kXBAR1_InputRESERVED69          = 69|0x100U,   /**< XBAR1_IN69 input is reserved. */
1516     kXBAR1_InputRESERVED70          = 70|0x100U,   /**< XBAR1_IN70 input is reserved. */
1517     kXBAR1_InputRESERVED71          = 71|0x100U,   /**< XBAR1_IN71 input is reserved. */
1518     kXBAR1_InputRESERVED72          = 72|0x100U,   /**< XBAR1_IN72 input is reserved. */
1519     kXBAR1_InputRESERVED73          = 73|0x100U,   /**< XBAR1_IN73 input is reserved. */
1520     kXBAR1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U,  /**< FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBAR1_IN74 input. */
1521     kXBAR1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U,  /**< FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBAR1_IN75 input. */
1522     kXBAR1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U,  /**< FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBAR1_IN76 input. */
1523     kXBAR1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U,  /**< FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBAR1_IN77 input. */
1524     kXBAR1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U,  /**< FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBAR1_IN78 input. */
1525     kXBAR1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U,  /**< FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBAR1_IN79 input. */
1526     kXBAR1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U,  /**< FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBAR1_IN80 input. */
1527     kXBAR1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U,  /**< FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBAR1_IN81 input. */
1528     kXBAR1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBAR1_IN82 input. */
1529     kXBAR1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBAR1_IN83 input. */
1530     kXBAR1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBAR1_IN84 input. */
1531     kXBAR1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBAR1_IN85 input. */
1532     kXBAR1_InputRESERVED86          = 86|0x100U,   /**< XBAR1_IN86 input is reserved. */
1533     kXBAR1_InputRESERVED87          = 87|0x100U,   /**< XBAR1_IN87 input is reserved. */
1534     kXBAR1_InputRESERVED88          = 88|0x100U,   /**< XBAR1_IN88 input is reserved. */
1535     kXBAR1_InputRESERVED89          = 89|0x100U,   /**< XBAR1_IN89 input is reserved. */
1536     kXBAR1_InputRESERVED90          = 90|0x100U,   /**< XBAR1_IN90 input is reserved. */
1537     kXBAR1_InputRESERVED91          = 91|0x100U,   /**< XBAR1_IN91 input is reserved. */
1538     kXBAR1_InputRESERVED92          = 92|0x100U,   /**< XBAR1_IN92 input is reserved. */
1539     kXBAR1_InputRESERVED93          = 93|0x100U,   /**< XBAR1_IN93 input is reserved. */
1540     kXBAR1_InputPit1Trigger0        = 94|0x100U,   /**< PIT1_TRIGGER0 output assigned to XBAR1_IN94 input. */
1541     kXBAR1_InputPit1Trigger1        = 95|0x100U,   /**< PIT1_TRIGGER1 output assigned to XBAR1_IN95 input. */
1542     kXBAR1_InputPit1Trigger2        = 96|0x100U,   /**< PIT1_TRIGGER2 output assigned to XBAR1_IN96 input. */
1543     kXBAR1_InputPit1Trigger3        = 97|0x100U,   /**< PIT1_TRIGGER3 output assigned to XBAR1_IN97 input. */
1544     kXBAR1_InputPit2Trigger0        = 98|0x100U,   /**< PIT2_TRIGGER0 output assigned to XBAR1_IN98 input. */
1545     kXBAR1_InputPit2Trigger1        = 99|0x100U,   /**< PIT2_TRIGGER1 output assigned to XBAR1_IN99 input. */
1546     kXBAR1_InputPit2Trigger2        = 100|0x100U,  /**< PIT2_TRIGGER2 output assigned to XBAR1_IN100 input. */
1547     kXBAR1_InputPit2Trigger3        = 101|0x100U,  /**< PIT2_TRIGGER3 output assigned to XBAR1_IN101 input. */
1548     kXBAR1_InputPit3Trigger0        = 102|0x100U,  /**< PIT3_TRIGGER0 output assigned to XBAR1_IN102 input. */
1549     kXBAR1_InputPit3Trigger1        = 103|0x100U,  /**< PIT3_TRIGGER1 output assigned to XBAR1_IN103 input. */
1550     kXBAR1_InputPit3Trigger2        = 104|0x100U,  /**< PIT3_TRIGGER2 output assigned to XBAR1_IN104 input. */
1551     kXBAR1_InputPit3Trigger3        = 105|0x100U,  /**< PIT3_TRIGGER3 output assigned to XBAR1_IN105 input. */
1552     kXBAR1_InputTriggerSyncOut0     = 106|0x100U,  /**< TRIGGER_SYNC_OUT0 output assigned to XBAR1_IN106 input. */
1553     kXBAR1_InputTriggerSyncOut1     = 107|0x100U,  /**< TRIGGER_SYNC_OUT1 output assigned to XBAR1_IN107 input. */
1554     kXBAR1_InputTriggerSyncOut2     = 108|0x100U,  /**< TRIGGER_SYNC_OUT2 output assigned to XBAR1_IN108 input. */
1555     kXBAR1_InputTriggerSyncOut3     = 109|0x100U,  /**< TRIGGER_SYNC_OUT3 output assigned to XBAR1_IN109 input. */
1556     kXBAR1_InputDma4TriggerOut0     = 110|0x100U,  /**< DMA4_TRIGGER_OUT0 output assigned to XBAR1_IN110 input. */
1557     kXBAR1_InputDma4TriggerOut1     = 111|0x100U,  /**< DMA4_TRIGGER_OUT1 output assigned to XBAR1_IN111 input. */
1558     kXBAR1_InputDma4TriggerOut2     = 112|0x100U,  /**< DMA4_TRIGGER_OUT2 output assigned to XBAR1_IN112 input. */
1559     kXBAR1_InputDma4TriggerOut3     = 113|0x100U,  /**< DMA4_TRIGGER_OUT3 output assigned to XBAR1_IN113 input. */
1560     kXBAR1_InputDma4TriggerOut4     = 114|0x100U,  /**< DMA4_TRIGGER_OUT4 output assigned to XBAR1_IN114 input. */
1561     kXBAR1_InputDma4TriggerOut5     = 115|0x100U,  /**< DMA4_TRIGGER_OUT5 output assigned to XBAR1_IN115 input. */
1562     kXBAR1_InputDma4TriggerOut6     = 116|0x100U,  /**< DMA4_TRIGGER_OUT6 output assigned to XBAR1_IN116 input. */
1563     kXBAR1_InputDma4TriggerOut7     = 117|0x100U,  /**< DMA4_TRIGGER_OUT7 output assigned to XBAR1_IN117 input. */
1564     kXBAR1_InputDma3TriggerOut0     = 118|0x100U,  /**< DMA3_TRIGGER_OUT0 output assigned to XBAR1_IN118 input. */
1565     kXBAR1_InputDma3TriggerOut1     = 119|0x100U,  /**< DMA3_TRIGGER_OUT1 output assigned to XBAR1_IN119 input. */
1566     kXBAR1_InputDma3TriggerOut2     = 120|0x100U,  /**< DMA3_TRIGGER_OUT2 output assigned to XBAR1_IN120 input. */
1567     kXBAR1_InputDma3TriggerOut3     = 121|0x100U,  /**< DMA3_TRIGGER_OUT3 output assigned to XBAR1_IN121 input. */
1568     kXBAR1_InputDma3TriggerOut4     = 122|0x100U,  /**< DMA3_TRIGGER_OUT4 output assigned to XBAR1_IN122 input. */
1569     kXBAR1_InputDma3TriggerOut5     = 123|0x100U,  /**< DMA3_TRIGGER_OUT5 output assigned to XBAR1_IN123 input. */
1570     kXBAR1_InputDma3TriggerOut6     = 124|0x100U,  /**< DMA3_TRIGGER_OUT6 output assigned to XBAR1_IN124 input. */
1571     kXBAR1_InputDma3TriggerOut7     = 125|0x100U,  /**< DMA3_TRIGGER_OUT7 output assigned to XBAR1_IN125 input. */
1572     kXBAR1_InputAdc1TcompPulse0     = 126|0x100U,  /**< ADC1_TCOMP_PULSE0 output assigned to XBAR1_IN126 input. */
1573     kXBAR1_InputAdc1TcompPulse1     = 127|0x100U,  /**< ADC1_TCOMP_PULSE1 output assigned to XBAR1_IN127 input. */
1574     kXBAR1_InputAdc1TcompPulse2     = 128|0x100U,  /**< ADC1_TCOMP_PULSE2 output assigned to XBAR1_IN128 input. */
1575     kXBAR1_InputAdc1TcompPulse3     = 129|0x100U,  /**< ADC1_TCOMP_PULSE3 output assigned to XBAR1_IN129 input. */
1576     kXBAR1_InputAdc1TcompPulse4     = 130|0x100U,  /**< ADC1_TCOMP_PULSE4 output assigned to XBAR1_IN130 input. */
1577     kXBAR1_InputAdc1TcompPulse5     = 131|0x100U,  /**< ADC1_TCOMP_PULSE5 output assigned to XBAR1_IN131 input. */
1578     kXBAR1_InputAdc1TcompPulse6     = 132|0x100U,  /**< ADC1_TCOMP_PULSE6 output assigned to XBAR1_IN132 input. */
1579     kXBAR1_InputAdc1TcompPulse7     = 133|0x100U,  /**< ADC1_TCOMP_PULSE7 output assigned to XBAR1_IN133 input. */
1580     kXBAR1_InputRESERVED134         = 134|0x100U,  /**< XBAR1_IN134 input is reserved. */
1581     kXBAR1_InputRESERVED135         = 135|0x100U,  /**< XBAR1_IN135 input is reserved. */
1582     kXBAR1_InputRESERVED136         = 136|0x100U,  /**< XBAR1_IN136 input is reserved. */
1583     kXBAR1_InputRESERVED137         = 137|0x100U,  /**< XBAR1_IN137 input is reserved. */
1584     kXBAR1_InputRESERVED138         = 138|0x100U,  /**< XBAR1_IN138 input is reserved. */
1585     kXBAR1_InputRESERVED139         = 139|0x100U,  /**< XBAR1_IN139 input is reserved. */
1586     kXBAR1_InputRESERVED140         = 140|0x100U,  /**< XBAR1_IN140 input is reserved. */
1587     kXBAR1_InputRESERVED141         = 141|0x100U,  /**< XBAR1_IN141 input is reserved. */
1588     kXBAR1_InputTpm1ChTrigger0      = 142|0x100U,  /**< TPM1_CH_TRIGGER0 output assigned to XBAR1_IN142 input. */
1589     kXBAR1_InputTpm1ChTrigger1      = 143|0x100U,  /**< TPM1_CH_TRIGGER1 output assigned to XBAR1_IN143 input. */
1590     kXBAR1_InputTpm1ChTrigger2      = 144|0x100U,  /**< TPM1_CH_TRIGGER2 output assigned to XBAR1_IN144 input. */
1591     kXBAR1_InputTpm1ChTrigger3      = 145|0x100U,  /**< TPM1_CH_TRIGGER3 output assigned to XBAR1_IN145 input. */
1592     kXBAR1_InputTpm1Trigger         = 146|0x100U,  /**< TPM1_TRIGGER output assigned to XBAR1_IN146 input. */
1593     kXBAR1_InputTpm2ChTrigger0      = 147|0x100U,  /**< TPM2_CH_TRIGGER0 output assigned to XBAR1_IN147 input. */
1594     kXBAR1_InputTpm2ChTrigger1      = 148|0x100U,  /**< TPM2_CH_TRIGGER1 output assigned to XBAR1_IN148 input. */
1595     kXBAR1_InputTpm2ChTrigger2      = 149|0x100U,  /**< TPM2_CH_TRIGGER2 output assigned to XBAR1_IN149 input. */
1596     kXBAR1_InputTpm2ChTrigger3      = 150|0x100U,  /**< TPM2_CH_TRIGGER3 output assigned to XBAR1_IN150 input. */
1597     kXBAR1_InputTpm2Trigger         = 151|0x100U,  /**< TPM2_TRIGGER output assigned to XBAR1_IN151 input. */
1598     kXBAR1_InputTpm3ChTrigger0      = 152|0x100U,  /**< TPM3_CH_TRIGGER0 output assigned to XBAR1_IN152 input. */
1599     kXBAR1_InputTpm3ChTrigger1      = 153|0x100U,  /**< TPM3_CH_TRIGGER1 output assigned to XBAR1_IN153 input. */
1600     kXBAR1_InputTpm3ChTrigger2      = 154|0x100U,  /**< TPM3_CH_TRIGGER2 output assigned to XBAR1_IN154 input. */
1601     kXBAR1_InputTpm3ChTrigger3      = 155|0x100U,  /**< TPM3_CH_TRIGGER3 output assigned to XBAR1_IN155 input. */
1602     kXBAR1_InputTpm3Trigger         = 156|0x100U,  /**< TPM3_TRIGGER output assigned to XBAR1_IN156 input. */
1603     kXBAR1_InputRESERVED157         = 157|0x100U,  /**< XBAR1_IN157 input is reserved. */
1604     kXBAR1_InputRESERVED158         = 158|0x100U,  /**< XBAR1_IN158 input is reserved. */
1605     kXBAR1_InputRESERVED159         = 159|0x100U,  /**< XBAR1_IN159 input is reserved. */
1606     kXBAR1_InputRESERVED160         = 160|0x100U,  /**< XBAR1_IN160 input is reserved. */
1607     kXBAR1_InputRESERVED161         = 161|0x100U,  /**< XBAR1_IN161 input is reserved. */
1608     kXBAR1_InputRESERVED162         = 162|0x100U,  /**< XBAR1_IN162 input is reserved. */
1609     kXBAR1_InputRESERVED163         = 163|0x100U,  /**< XBAR1_IN163 input is reserved. */
1610     kXBAR1_InputRESERVED164         = 164|0x100U,  /**< XBAR1_IN164 input is reserved. */
1611     kXBAR1_InputRESERVED165         = 165|0x100U,  /**< XBAR1_IN165 input is reserved. */
1612     kXBAR1_InputRESERVED166         = 166|0x100U,  /**< XBAR1_IN166 input is reserved. */
1613     kXBAR1_InputRESERVED167         = 167|0x100U,  /**< XBAR1_IN167 input is reserved. */
1614     kXBAR1_InputRESERVED168         = 168|0x100U,  /**< XBAR1_IN168 input is reserved. */
1615     kXBAR1_InputRESERVED169         = 169|0x100U,  /**< XBAR1_IN169 input is reserved. */
1616     kXBAR1_InputRESERVED170         = 170|0x100U,  /**< XBAR1_IN170 input is reserved. */
1617     kXBAR1_InputRESERVED171         = 171|0x100U,  /**< XBAR1_IN171 input is reserved. */
1618     kXBAR1_InputLptmr1TriggerDelay  = 172|0x100U,  /**< LPTMR1_TRIGGER_DELAY output assigned to XBAR1_IN172 input. */
1619     kXBAR1_InputRESERVED173         = 173|0x100U,  /**< XBAR1_IN173 input is reserved. */
1620     kXBAR1_InputRESERVED174         = 174|0x100U,  /**< XBAR1_IN174 input is reserved. */
1621     kXBAR1_InputNetcTmrPp1          = 175|0x100U,  /**< NETC_TMR_PP1 output assigned to XBAR1_IN175 input. */
1622     kXBAR1_InputNetcTmrPp2          = 176|0x100U,  /**< NETC_TMR_PP2 output assigned to XBAR1_IN176 input. */
1623     kXBAR1_InputNetcTmrPp3          = 177|0x100U,  /**< NETC_TMR_PP3 output assigned to XBAR1_IN177 input. */
1624     kXBAR1_InputRESERVED178         = 178|0x100U,  /**< XBAR1_IN178 input is reserved. */
1625     kXBAR1_InputRESERVED179         = 179|0x100U,  /**< XBAR1_IN179 input is reserved. */
1626     kXBAR1_InputRESERVED180         = 180|0x100U,  /**< XBAR1_IN180 input is reserved. */
1627     kXBAR1_InputRESERVED181         = 181|0x100U,  /**< XBAR1_IN181 input is reserved. */
1628     kXBAR1_InputRESERVED182         = 182|0x100U,  /**< XBAR1_IN182 input is reserved. */
1629     kXBAR1_InputRESERVED183         = 183|0x100U,  /**< XBAR1_IN183 input is reserved. */
1630     kXBAR1_InputRESERVED184         = 184|0x100U,  /**< XBAR1_IN184 input is reserved. */
1631     kXBAR1_InputRESERVED185         = 185|0x100U,  /**< XBAR1_IN185 input is reserved. */
1632     kXBAR1_InputRESERVED186         = 186|0x100U,  /**< XBAR1_IN186 input is reserved. */
1633     kXBAR1_InputRESERVED187         = 187|0x100U,  /**< XBAR1_IN187 input is reserved. */
1634     kXBAR1_InputRESERVED188         = 188|0x100U,  /**< XBAR1_IN188 input is reserved. */
1635     kXBAR1_InputRESERVED189         = 189|0x100U,  /**< XBAR1_IN189 input is reserved. */
1636     kXBAR1_InputAoi1Out0            = 190|0x100U,  /**< AOI1_OUT0 output assigned to XBAR1_IN190 input. */
1637     kXBAR1_InputAoi1Out1            = 191|0x100U,  /**< AOI1_OUT1 output assigned to XBAR1_IN191 input. */
1638     kXBAR1_InputAoi1Out2            = 192|0x100U,  /**< AOI1_OUT2 output assigned to XBAR1_IN192 input. */
1639     kXBAR1_InputAoi1Out3            = 193|0x100U,  /**< AOI1_OUT3 output assigned to XBAR1_IN193 input. */
1640     kXBAR1_InputAoi2Out0            = 194|0x100U,  /**< AOI2_OUT0 output assigned to XBAR1_IN194 input. */
1641     kXBAR1_InputAoi2Out1            = 195|0x100U,  /**< AOI2_OUT1 output assigned to XBAR1_IN195 input. */
1642     kXBAR1_InputAoi2Out2            = 196|0x100U,  /**< AOI2_OUT2 output assigned to XBAR1_IN196 input. */
1643     kXBAR1_InputAoi2Out3            = 197|0x100U,  /**< AOI2_OUT3 output assigned to XBAR1_IN197 input. */
1644     kXBAR1_InputTriggerSyncOut4     = 198|0x100U,  /**< TRIGGER_SYNC_OUT4 output assigned to XBAR1_IN198 input. */
1645     kXBAR1_InputTriggerSyncOut5     = 199|0x100U,  /**< TRIGGER_SYNC_OUT5 output assigned to XBAR1_IN199 input. */
1646     kXBAR1_InputTriggerSyncOut6     = 200|0x100U,  /**< TRIGGER_SYNC_OUT6 output assigned to XBAR1_IN200 input. */
1647     kXBAR1_InputTriggerSyncOut7     = 201|0x100U,  /**< TRIGGER_SYNC_OUT7 output assigned to XBAR1_IN201 input. */
1648     kXBAR1_InputRESERVED202         = 202|0x100U,  /**< XBAR1_IN202 input is reserved. */
1649     kXBAR1_InputRESERVED203         = 203|0x100U,  /**< XBAR1_IN203 input is reserved. */
1650     kXBAR1_InputRESERVED204         = 204|0x100U,  /**< XBAR1_IN204 input is reserved. */
1651     kXBAR1_InputRESERVED205         = 205|0x100U,  /**< XBAR1_IN205 input is reserved. */
1652     kXBAR1_InputAoi3Out0            = 206|0x100U,  /**< AOI3_OUT0 output assigned to XBAR1_IN206 input. */
1653     kXBAR1_InputAoi3Out1            = 207|0x100U,  /**< AOI3_OUT1 output assigned to XBAR1_IN207 input. */
1654     kXBAR1_InputAoi3Out2            = 208|0x100U,  /**< AOI3_OUT2 output assigned to XBAR1_IN208 input. */
1655     kXBAR1_InputAoi3Out3            = 209|0x100U,  /**< AOI3_OUT3 output assigned to XBAR1_IN209 input. */
1656     kXBAR1_InputAoi4Out0            = 210|0x100U,  /**< AOI4_OUT0 output assigned to XBAR1_IN210 input. */
1657     kXBAR1_InputAoi4Out1            = 211|0x100U,  /**< AOI4_OUT1 output assigned to XBAR1_IN211 input. */
1658     kXBAR1_InputAoi4Out2            = 212|0x100U,  /**< AOI4_OUT2 output assigned to XBAR1_IN212 input. */
1659     kXBAR1_InputAoi4Out3            = 213|0x100U,  /**< AOI4_OUT3 output assigned to XBAR1_IN213 input. */
1660     kXBAR1_InputEcatSyncOut0        = 214|0x100U,  /**< ECAT_SYNC_OUT0 output assigned to XBAR1_IN214 input. */
1661     kXBAR1_InputEcatSyncOut1        = 215|0x100U,  /**< ECAT_SYNC_OUT1 output assigned to XBAR1_IN215 input. */
1662     kXBAR2_InputLogicLow            = 0|0x200U,    /**< LOGIC_LOW output assigned to XBAR2_IN0 input. */
1663     kXBAR2_InputLogicHigh           = 1|0x200U,    /**< LOGIC_HIGH output assigned to XBAR2_IN1 input. */
1664     kXBAR2_InputLogicLow1           = 2|0x200U,    /**< LOGIC_LOW1 output assigned to XBAR2_IN2 input. */
1665     kXBAR2_InputLogicHigh1          = 3|0x200U,    /**< LOGIC_HIGH1 output assigned to XBAR2_IN3 input. */
1666     kXBAR2_InputAcmp1Out            = 4|0x200U,    /**< ACMP1_OUT output assigned to XBAR2_IN4 input. */
1667     kXBAR2_InputAcmp2Out            = 5|0x200U,    /**< ACMP2_OUT output assigned to XBAR2_IN5 input. */
1668     kXBAR2_InputAcmp3Out            = 6|0x200U,    /**< ACMP3_OUT output assigned to XBAR2_IN6 input. */
1669     kXBAR2_InputAcmp4Out            = 7|0x200U,    /**< ACMP4_OUT output assigned to XBAR2_IN7 input. */
1670     kXBAR2_InputQtimer1Timer0       = 8|0x200U,    /**< QTIMER1_TIMER0 output assigned to XBAR2_IN8 input. */
1671     kXBAR2_InputQtimer1Timer1       = 9|0x200U,    /**< QTIMER1_TIMER1 output assigned to XBAR2_IN9 input. */
1672     kXBAR2_InputQtimer1Timer2       = 10|0x200U,   /**< QTIMER1_TIMER2 output assigned to XBAR2_IN10 input. */
1673     kXBAR2_InputQtimer1Timer3       = 11|0x200U,   /**< QTIMER1_TIMER3 output assigned to XBAR2_IN11 input. */
1674     kXBAR2_InputQtimer2Timer0       = 12|0x200U,   /**< QTIMER2_TIMER0 output assigned to XBAR2_IN12 input. */
1675     kXBAR2_InputQtimer2Timer1       = 13|0x200U,   /**< QTIMER2_TIMER1 output assigned to XBAR2_IN13 input. */
1676     kXBAR2_InputQtimer2Timer2       = 14|0x200U,   /**< QTIMER2_TIMER2 output assigned to XBAR2_IN14 input. */
1677     kXBAR2_InputQtimer2Timer3       = 15|0x200U,   /**< QTIMER2_TIMER3 output assigned to XBAR2_IN15 input. */
1678     kXBAR2_InputQtimer3Timer0       = 16|0x200U,   /**< QTIMER3_TIMER0 output assigned to XBAR2_IN16 input. */
1679     kXBAR2_InputQtimer3Timer1       = 17|0x200U,   /**< QTIMER3_TIMER1 output assigned to XBAR2_IN17 input. */
1680     kXBAR2_InputQtimer3Timer2       = 18|0x200U,   /**< QTIMER3_TIMER2 output assigned to XBAR2_IN18 input. */
1681     kXBAR2_InputQtimer3Timer3       = 19|0x200U,   /**< QTIMER3_TIMER3 output assigned to XBAR2_IN19 input. */
1682     kXBAR2_InputQtimer4Timer0       = 20|0x200U,   /**< QTIMER4_TIMER0 output assigned to XBAR2_IN20 input. */
1683     kXBAR2_InputQtimer4Timer1       = 21|0x200U,   /**< QTIMER4_TIMER1 output assigned to XBAR2_IN21 input. */
1684     kXBAR2_InputQtimer4Timer2       = 22|0x200U,   /**< QTIMER4_TIMER2 output assigned to XBAR2_IN22 input. */
1685     kXBAR2_InputQtimer4Timer3       = 23|0x200U,   /**< QTIMER4_TIMER3 output assigned to XBAR2_IN23 input. */
1686     kXBAR2_InputRESERVED24          = 24|0x200U,   /**< XBAR2_IN24 input is reserved. */
1687     kXBAR2_InputRESERVED25          = 25|0x200U,   /**< XBAR2_IN25 input is reserved. */
1688     kXBAR2_InputRESERVED26          = 26|0x200U,   /**< XBAR2_IN26 input is reserved. */
1689     kXBAR2_InputRESERVED27          = 27|0x200U,   /**< XBAR2_IN27 input is reserved. */
1690     kXBAR2_InputRESERVED28          = 28|0x200U,   /**< XBAR2_IN28 input is reserved. */
1691     kXBAR2_InputRESERVED29          = 29|0x200U,   /**< XBAR2_IN29 input is reserved. */
1692     kXBAR2_InputRESERVED30          = 30|0x200U,   /**< XBAR2_IN30 input is reserved. */
1693     kXBAR2_InputRESERVED31          = 31|0x200U,   /**< XBAR2_IN31 input is reserved. */
1694     kXBAR2_InputRESERVED32          = 32|0x200U,   /**< XBAR2_IN32 input is reserved. */
1695     kXBAR2_InputRESERVED33          = 33|0x200U,   /**< XBAR2_IN33 input is reserved. */
1696     kXBAR2_InputRESERVED34          = 34|0x200U,   /**< XBAR2_IN34 input is reserved. */
1697     kXBAR2_InputRESERVED35          = 35|0x200U,   /**< XBAR2_IN35 input is reserved. */
1698     kXBAR2_InputRESERVED36          = 36|0x200U,   /**< XBAR2_IN36 input is reserved. */
1699     kXBAR2_InputRESERVED37          = 37|0x200U,   /**< XBAR2_IN37 input is reserved. */
1700     kXBAR2_InputRESERVED38          = 38|0x200U,   /**< XBAR2_IN38 input is reserved. */
1701     kXBAR2_InputRESERVED39          = 39|0x200U,   /**< XBAR2_IN39 input is reserved. */
1702     kXBAR2_InputFlexpwm1Pwm0OutTrig01 = 40|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBAR2_IN40 input. */
1703     kXBAR2_InputFlexpwm1Pwm1OutTrig01 = 41|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBAR2_IN41 input. */
1704     kXBAR2_InputFlexpwm1Pwm2OutTrig01 = 42|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBAR2_IN42 input. */
1705     kXBAR2_InputFlexpwm1Pwm3OutTrig01 = 43|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBAR2_IN43 input. */
1706     kXBAR2_InputFlexpwm2Pwm0OutTrig01 = 44|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBAR2_IN44 input. */
1707     kXBAR2_InputFlexpwm2Pwm1OutTrig01 = 45|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBAR2_IN45 input. */
1708     kXBAR2_InputFlexpwm2Pwm2OutTrig01 = 46|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBAR2_IN46 input. */
1709     kXBAR2_InputFlexpwm2Pwm3OutTrig01 = 47|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBAR2_IN47 input. */
1710     kXBAR2_InputRESERVED48          = 48|0x200U,   /**< XBAR2_IN48 input is reserved. */
1711     kXBAR2_InputRESERVED49          = 49|0x200U,   /**< XBAR2_IN49 input is reserved. */
1712     kXBAR2_InputRESERVED50          = 50|0x200U,   /**< XBAR2_IN50 input is reserved. */
1713     kXBAR2_InputRESERVED51          = 51|0x200U,   /**< XBAR2_IN51 input is reserved. */
1714     kXBAR2_InputRESERVED52          = 52|0x200U,   /**< XBAR2_IN52 input is reserved. */
1715     kXBAR2_InputRESERVED53          = 53|0x200U,   /**< XBAR2_IN53 input is reserved. */
1716     kXBAR2_InputRESERVED54          = 54|0x200U,   /**< XBAR2_IN54 input is reserved. */
1717     kXBAR2_InputRESERVED55          = 55|0x200U,   /**< XBAR2_IN55 input is reserved. */
1718     kXBAR2_InputPit1Trigger0        = 56|0x200U,   /**< PIT1_TRIGGER0 output assigned to XBAR2_IN56 input. */
1719     kXBAR2_InputPit1Trigger1        = 57|0x200U,   /**< PIT1_TRIGGER1 output assigned to XBAR2_IN57 input. */
1720     kXBAR2_InputPit1Trigger2        = 58|0x200U,   /**< PIT1_TRIGGER2 output assigned to XBAR2_IN58 input. */
1721     kXBAR2_InputPit1Trigger3        = 59|0x200U,   /**< PIT1_TRIGGER3 output assigned to XBAR2_IN59 input. */
1722     kXBAR2_InputPit2Trigger0        = 60|0x200U,   /**< PIT2_TRIGGER0 output assigned to XBAR2_IN60 input. */
1723     kXBAR2_InputPit2Trigger1        = 61|0x200U,   /**< PIT2_TRIGGER1 output assigned to XBAR2_IN61 input. */
1724     kXBAR2_InputPit2Trigger2        = 62|0x200U,   /**< PIT2_TRIGGER2 output assigned to XBAR2_IN62 input. */
1725     kXBAR2_InputPit2Trigger3        = 63|0x200U,   /**< PIT2_TRIGGER3 output assigned to XBAR2_IN63 input. */
1726     kXBAR2_InputPit3Trigger0        = 64|0x200U,   /**< PIT3_TRIGGER0 output assigned to XBAR2_IN64 input. */
1727     kXBAR2_InputPit3Trigger1        = 65|0x200U,   /**< PIT3_TRIGGER1 output assigned to XBAR2_IN65 input. */
1728     kXBAR2_InputPit3Trigger2        = 66|0x200U,   /**< PIT3_TRIGGER2 output assigned to XBAR2_IN66 input. */
1729     kXBAR2_InputPit3Trigger3        = 67|0x200U,   /**< PIT3_TRIGGER3 output assigned to XBAR2_IN67 input. */
1730     kXBAR2_InputRESERVED68          = 68|0x200U,   /**< XBAR2_IN68 input is reserved. */
1731     kXBAR2_InputRESERVED69          = 69|0x200U,   /**< XBAR2_IN69 input is reserved. */
1732     kXBAR2_InputRESERVED70          = 70|0x200U,   /**< XBAR2_IN70 input is reserved. */
1733     kXBAR2_InputRESERVED71          = 71|0x200U,   /**< XBAR2_IN71 input is reserved. */
1734     kXBAR2_InputDma4TriggerOut0     = 72|0x200U,   /**< DMA4_TRIGGER_OUT0 output assigned to XBAR2_IN72 input. */
1735     kXBAR2_InputDma4TriggerOut1     = 73|0x200U,   /**< DMA4_TRIGGER_OUT1 output assigned to XBAR2_IN73 input. */
1736     kXBAR2_InputDma4TriggerOut2     = 74|0x200U,   /**< DMA4_TRIGGER_OUT2 output assigned to XBAR2_IN74 input. */
1737     kXBAR2_InputDma4TriggerOut3     = 75|0x200U,   /**< DMA4_TRIGGER_OUT3 output assigned to XBAR2_IN75 input. */
1738     kXBAR2_InputDma4TriggerOut4     = 76|0x200U,   /**< DMA4_TRIGGER_OUT4 output assigned to XBAR2_IN76 input. */
1739     kXBAR2_InputDma4TriggerOut5     = 77|0x200U,   /**< DMA4_TRIGGER_OUT5 output assigned to XBAR2_IN77 input. */
1740     kXBAR2_InputDma4TriggerOut6     = 78|0x200U,   /**< DMA4_TRIGGER_OUT6 output assigned to XBAR2_IN78 input. */
1741     kXBAR2_InputDma4TriggerOut7     = 79|0x200U,   /**< DMA4_TRIGGER_OUT7 output assigned to XBAR2_IN79 input. */
1742     kXBAR2_InputDma3TriggerOut0     = 80|0x200U,   /**< DMA3_TRIGGER_OUT0 output assigned to XBAR2_IN80 input. */
1743     kXBAR2_InputDma3TriggerOut1     = 81|0x200U,   /**< DMA3_TRIGGER_OUT1 output assigned to XBAR2_IN81 input. */
1744     kXBAR2_InputDma3TriggerOut2     = 82|0x200U,   /**< DMA3_TRIGGER_OUT2 output assigned to XBAR2_IN82 input. */
1745     kXBAR2_InputDma3TriggerOut3     = 83|0x200U,   /**< DMA3_TRIGGER_OUT3 output assigned to XBAR2_IN83 input. */
1746     kXBAR2_InputDma3TriggerOut4     = 84|0x200U,   /**< DMA3_TRIGGER_OUT4 output assigned to XBAR2_IN84 input. */
1747     kXBAR2_InputDma3TriggerOut5     = 85|0x200U,   /**< DMA3_TRIGGER_OUT5 output assigned to XBAR2_IN85 input. */
1748     kXBAR2_InputDma3TriggerOut6     = 86|0x200U,   /**< DMA3_TRIGGER_OUT6 output assigned to XBAR2_IN86 input. */
1749     kXBAR2_InputDma3TriggerOut7     = 87|0x200U,   /**< DMA3_TRIGGER_OUT7 output assigned to XBAR2_IN87 input. */
1750     kXBAR2_InputAdc1TcompPulse0     = 88|0x200U,   /**< ADC1_TCOMP_PULSE0 output assigned to XBAR2_IN88 input. */
1751     kXBAR2_InputAdc1TcompPulse1     = 89|0x200U,   /**< ADC1_TCOMP_PULSE1 output assigned to XBAR2_IN89 input. */
1752     kXBAR2_InputAdc1TcompPulse2     = 90|0x200U,   /**< ADC1_TCOMP_PULSE2 output assigned to XBAR2_IN90 input. */
1753     kXBAR2_InputAdc1TcompPulse3     = 91|0x200U,   /**< ADC1_TCOMP_PULSE3 output assigned to XBAR2_IN91 input. */
1754     kXBAR2_InputAdc1TcompPulse4     = 92|0x200U,   /**< ADC1_TCOMP_PULSE4 output assigned to XBAR2_IN92 input. */
1755     kXBAR2_InputAdc1TcompPulse5     = 93|0x200U,   /**< ADC1_TCOMP_PULSE5 output assigned to XBAR2_IN93 input. */
1756     kXBAR2_InputAdc1TcompPulse6     = 94|0x200U,   /**< ADC1_TCOMP_PULSE6 output assigned to XBAR2_IN94 input. */
1757     kXBAR2_InputAdc1TcompPulse7     = 95|0x200U,   /**< ADC1_TCOMP_PULSE7 output assigned to XBAR2_IN95 input. */
1758     kXBAR2_InputRESERVED96          = 96|0x200U,   /**< XBAR2_IN96 input is reserved. */
1759     kXBAR2_InputRESERVED97          = 97|0x200U,   /**< XBAR2_IN97 input is reserved. */
1760     kXBAR2_InputRESERVED98          = 98|0x200U,   /**< XBAR2_IN98 input is reserved. */
1761     kXBAR2_InputRESERVED99          = 99|0x200U,   /**< XBAR2_IN99 input is reserved. */
1762     kXBAR2_InputRESERVED100         = 100|0x200U,  /**< XBAR2_IN100 input is reserved. */
1763     kXBAR2_InputRESERVED101         = 101|0x200U,  /**< XBAR2_IN101 input is reserved. */
1764     kXBAR2_InputRESERVED102         = 102|0x200U,  /**< XBAR2_IN102 input is reserved. */
1765     kXBAR2_InputRESERVED103         = 103|0x200U,  /**< XBAR2_IN103 input is reserved. */
1766     kXBAR2_InputTpm1ChTrigger0      = 104|0x200U,  /**< TPM1_CH_TRIGGER0 output assigned to XBAR2_IN104 input. */
1767     kXBAR2_InputTpm1ChTrigger1      = 105|0x200U,  /**< TPM1_CH_TRIGGER1 output assigned to XBAR2_IN105 input. */
1768     kXBAR2_InputTpm1ChTrigger2      = 106|0x200U,  /**< TPM1_CH_TRIGGER2 output assigned to XBAR2_IN106 input. */
1769     kXBAR2_InputTpm1ChTrigger3      = 107|0x200U,  /**< TPM1_CH_TRIGGER3 output assigned to XBAR2_IN107 input. */
1770     kXBAR2_InputTpm1Trigger         = 108|0x200U,  /**< TPM1_TRIGGER output assigned to XBAR2_IN108 input. */
1771     kXBAR2_InputTpm2ChTrigger0      = 109|0x200U,  /**< TPM2_CH_TRIGGER0 output assigned to XBAR2_IN109 input. */
1772     kXBAR2_InputTpm2ChTrigger1      = 110|0x200U,  /**< TPM2_CH_TRIGGER1 output assigned to XBAR2_IN110 input. */
1773     kXBAR2_InputTpm2ChTrigger2      = 111|0x200U,  /**< TPM2_CH_TRIGGER2 output assigned to XBAR2_IN111 input. */
1774     kXBAR2_InputTpm2ChTrigger3      = 112|0x200U,  /**< TPM2_CH_TRIGGER3 output assigned to XBAR2_IN112 input. */
1775     kXBAR2_InputTpm2Trigger         = 113|0x200U,  /**< TPM2_TRIGGER output assigned to XBAR2_IN113 input. */
1776     kXBAR2_InputTpm3ChTrigger0      = 114|0x200U,  /**< TPM3_CH_TRIGGER0 output assigned to XBAR2_IN114 input. */
1777     kXBAR2_InputTpm3ChTrigger1      = 115|0x200U,  /**< TPM3_CH_TRIGGER1 output assigned to XBAR2_IN115 input. */
1778     kXBAR2_InputTpm3ChTrigger2      = 116|0x200U,  /**< TPM3_CH_TRIGGER2 output assigned to XBAR2_IN116 input. */
1779     kXBAR2_InputTpm3ChTrigger3      = 117|0x200U,  /**< TPM3_CH_TRIGGER3 output assigned to XBAR2_IN117 input. */
1780     kXBAR2_InputTpm3Trigger         = 118|0x200U,  /**< TPM3_TRIGGER output assigned to XBAR2_IN118 input. */
1781     kXBAR2_InputRESERVED119         = 119|0x200U,  /**< XBAR2_IN119 input is reserved. */
1782     kXBAR2_InputRESERVED120         = 120|0x200U,  /**< XBAR2_IN120 input is reserved. */
1783     kXBAR2_InputRESERVED121         = 121|0x200U,  /**< XBAR2_IN121 input is reserved. */
1784     kXBAR2_InputRESERVED122         = 122|0x200U,  /**< XBAR2_IN122 input is reserved. */
1785     kXBAR2_InputRESERVED123         = 123|0x200U,  /**< XBAR2_IN123 input is reserved. */
1786     kXBAR2_InputRESERVED124         = 124|0x200U,  /**< XBAR2_IN124 input is reserved. */
1787     kXBAR2_InputRESERVED125         = 125|0x200U,  /**< XBAR2_IN125 input is reserved. */
1788     kXBAR2_InputRESERVED126         = 126|0x200U,  /**< XBAR2_IN126 input is reserved. */
1789     kXBAR2_InputRESERVED127         = 127|0x200U,  /**< XBAR2_IN127 input is reserved. */
1790     kXBAR2_InputRESERVED128         = 128|0x200U,  /**< XBAR2_IN128 input is reserved. */
1791     kXBAR2_InputRESERVED129         = 129|0x200U,  /**< XBAR2_IN129 input is reserved. */
1792     kXBAR2_InputRESERVED130         = 130|0x200U,  /**< XBAR2_IN130 input is reserved. */
1793     kXBAR2_InputRESERVED131         = 131|0x200U,  /**< XBAR2_IN131 input is reserved. */
1794     kXBAR2_InputRESERVED132         = 132|0x200U,  /**< XBAR2_IN132 input is reserved. */
1795     kXBAR2_InputRESERVED133         = 133|0x200U,  /**< XBAR2_IN133 input is reserved. */
1796     kXBAR2_InputLptmr1TriggerDelay  = 134|0x200U,  /**< LPTMR1_TRIGGER_DELAY output assigned to XBAR2_IN134 input. */
1797     kXBAR2_InputRESERVED135         = 135|0x200U,  /**< XBAR2_IN135 input is reserved. */
1798     kXBAR2_InputRESERVED136         = 136|0x200U,  /**< XBAR2_IN136 input is reserved. */
1799     kXBAR2_InputNetcTmrPp1          = 137|0x200U,  /**< NETC_TMR_PP1 output assigned to XBAR2_IN137 input. */
1800     kXBAR2_InputNetcTmrPp2          = 138|0x200U,  /**< NETC_TMR_PP2 output assigned to XBAR2_IN138 input. */
1801     kXBAR2_InputNetcTmrPp3          = 139|0x200U,  /**< NETC_TMR_PP3 output assigned to XBAR2_IN139 input. */
1802     kXBAR2_InputRESERVED140         = 140|0x200U,  /**< XBAR2_IN140 input is reserved. */
1803     kXBAR2_InputRESERVED141         = 141|0x200U,  /**< XBAR2_IN141 input is reserved. */
1804     kXBAR2_InputRESERVED142         = 142|0x200U,  /**< XBAR2_IN142 input is reserved. */
1805     kXBAR2_InputRESERVED143         = 143|0x200U,  /**< XBAR2_IN143 input is reserved. */
1806     kXBAR2_InputRESERVED144         = 144|0x200U,  /**< XBAR2_IN144 input is reserved. */
1807     kXBAR2_InputRESERVED145         = 145|0x200U,  /**< XBAR2_IN145 input is reserved. */
1808     kXBAR2_InputRESERVED146         = 146|0x200U,  /**< XBAR2_IN146 input is reserved. */
1809     kXBAR2_InputRESERVED147         = 147|0x200U,  /**< XBAR2_IN147 input is reserved. */
1810     kXBAR2_InputRESERVED148         = 148|0x200U,  /**< XBAR2_IN148 input is reserved. */
1811     kXBAR2_InputRESERVED149         = 149|0x200U,  /**< XBAR2_IN149 input is reserved. */
1812     kXBAR2_InputRESERVED150         = 150|0x200U,  /**< XBAR2_IN150 input is reserved. */
1813     kXBAR2_InputRESERVED151         = 151|0x200U,  /**< XBAR2_IN151 input is reserved. */
1814     kXBAR2_InputRESERVED152         = 152|0x200U,  /**< XBAR2_IN152 input is reserved. */
1815     kXBAR2_InputRESERVED153         = 153|0x200U,  /**< XBAR2_IN153 input is reserved. */
1816     kXBAR2_InputRESERVED154         = 154|0x200U,  /**< XBAR2_IN154 input is reserved. */
1817     kXBAR2_InputRESERVED155         = 155|0x200U,  /**< XBAR2_IN155 input is reserved. */
1818     kXBAR2_InputEqdc1PosMatch0      = 156|0x200U,  /**< EQDC1_POS_MATCH0 output assigned to XBAR2_IN156 input. */
1819     kXBAR2_InputEqdc1PosMatch1      = 157|0x200U,  /**< EQDC1_POS_MATCH1 output assigned to XBAR2_IN157 input. */
1820     kXBAR2_InputEqdc1PosMatch2      = 158|0x200U,  /**< EQDC1_POS_MATCH2 output assigned to XBAR2_IN158 input. */
1821     kXBAR2_InputEqdc1PosMatch3      = 159|0x200U,  /**< EQDC1_POS_MATCH3 output assigned to XBAR2_IN159 input. */
1822     kXBAR2_InputEqdc1CompFlg0       = 160|0x200U,  /**< EQDC1_COMP_FLG0 output assigned to XBAR2_IN160 input. */
1823     kXBAR2_InputEqdc1CompFlg1       = 161|0x200U,  /**< EQDC1_COMP_FLG1 output assigned to XBAR2_IN161 input. */
1824     kXBAR2_InputEqdc1CompFlg2       = 162|0x200U,  /**< EQDC1_COMP_FLG2 output assigned to XBAR2_IN162 input. */
1825     kXBAR2_InputEqdc1CompFlg3       = 163|0x200U,  /**< EQDC1_COMP_FLG3 output assigned to XBAR2_IN163 input. */
1826     kXBAR2_InputEqdc1CntDn          = 164|0x200U,  /**< EQDC1_CNT_DN output assigned to XBAR2_IN164 input. */
1827     kXBAR2_InputEqdc1CntUp          = 165|0x200U,  /**< EQDC1_CNT_UP output assigned to XBAR2_IN165 input. */
1828     kXBAR2_InputEqdc1CntDir         = 166|0x200U,  /**< EQDC1_CNT_DIR output assigned to XBAR2_IN166 input. */
1829     kXBAR2_InputRESERVED167         = 167|0x200U,  /**< XBAR2_IN167 input is reserved. */
1830     kXBAR2_InputRESERVED168         = 168|0x200U,  /**< XBAR2_IN168 input is reserved. */
1831     kXBAR2_InputRESERVED169         = 169|0x200U,  /**< XBAR2_IN169 input is reserved. */
1832     kXBAR2_InputRESERVED170         = 170|0x200U,  /**< XBAR2_IN170 input is reserved. */
1833     kXBAR2_InputRESERVED171         = 171|0x200U,  /**< XBAR2_IN171 input is reserved. */
1834     kXBAR2_InputRESERVED172         = 172|0x200U,  /**< XBAR2_IN172 input is reserved. */
1835     kXBAR2_InputRESERVED173         = 173|0x200U,  /**< XBAR2_IN173 input is reserved. */
1836     kXBAR2_InputRESERVED174         = 174|0x200U,  /**< XBAR2_IN174 input is reserved. */
1837     kXBAR2_InputRESERVED175         = 175|0x200U,  /**< XBAR2_IN175 input is reserved. */
1838     kXBAR2_InputRESERVED176         = 176|0x200U,  /**< XBAR2_IN176 input is reserved. */
1839     kXBAR2_InputRESERVED177         = 177|0x200U,  /**< XBAR2_IN177 input is reserved. */
1840     kXBAR3_InputLogicLow            = 0|0x300U,    /**< LOGIC_LOW output assigned to XBAR3_IN0 input. */
1841     kXBAR3_InputLogicHigh           = 1|0x300U,    /**< LOGIC_HIGH output assigned to XBAR3_IN1 input. */
1842     kXBAR3_InputLogicLow1           = 2|0x300U,    /**< LOGIC_LOW1 output assigned to XBAR3_IN2 input. */
1843     kXBAR3_InputLogicHigh1          = 3|0x300U,    /**< LOGIC_HIGH1 output assigned to XBAR3_IN3 input. */
1844     kXBAR3_InputAcmp1Out            = 4|0x300U,    /**< ACMP1_OUT output assigned to XBAR3_IN4 input. */
1845     kXBAR3_InputAcmp2Out            = 5|0x300U,    /**< ACMP2_OUT output assigned to XBAR3_IN5 input. */
1846     kXBAR3_InputAcmp3Out            = 6|0x300U,    /**< ACMP3_OUT output assigned to XBAR3_IN6 input. */
1847     kXBAR3_InputAcmp4Out            = 7|0x300U,    /**< ACMP4_OUT output assigned to XBAR3_IN7 input. */
1848     kXBAR3_InputQtimer1Timer0       = 8|0x300U,    /**< QTIMER1_TIMER0 output assigned to XBAR3_IN8 input. */
1849     kXBAR3_InputQtimer1Timer1       = 9|0x300U,    /**< QTIMER1_TIMER1 output assigned to XBAR3_IN9 input. */
1850     kXBAR3_InputQtimer1Timer2       = 10|0x300U,   /**< QTIMER1_TIMER2 output assigned to XBAR3_IN10 input. */
1851     kXBAR3_InputQtimer1Timer3       = 11|0x300U,   /**< QTIMER1_TIMER3 output assigned to XBAR3_IN11 input. */
1852     kXBAR3_InputQtimer2Timer0       = 12|0x300U,   /**< QTIMER2_TIMER0 output assigned to XBAR3_IN12 input. */
1853     kXBAR3_InputQtimer2Timer1       = 13|0x300U,   /**< QTIMER2_TIMER1 output assigned to XBAR3_IN13 input. */
1854     kXBAR3_InputQtimer2Timer2       = 14|0x300U,   /**< QTIMER2_TIMER2 output assigned to XBAR3_IN14 input. */
1855     kXBAR3_InputQtimer2Timer3       = 15|0x300U,   /**< QTIMER2_TIMER3 output assigned to XBAR3_IN15 input. */
1856     kXBAR3_InputQtimer3Timer0       = 16|0x300U,   /**< QTIMER3_TIMER0 output assigned to XBAR3_IN16 input. */
1857     kXBAR3_InputQtimer3Timer1       = 17|0x300U,   /**< QTIMER3_TIMER1 output assigned to XBAR3_IN17 input. */
1858     kXBAR3_InputQtimer3Timer2       = 18|0x300U,   /**< QTIMER3_TIMER2 output assigned to XBAR3_IN18 input. */
1859     kXBAR3_InputQtimer3Timer3       = 19|0x300U,   /**< QTIMER3_TIMER3 output assigned to XBAR3_IN19 input. */
1860     kXBAR3_InputQtimer4Timer0       = 20|0x300U,   /**< QTIMER4_TIMER0 output assigned to XBAR3_IN20 input. */
1861     kXBAR3_InputQtimer4Timer1       = 21|0x300U,   /**< QTIMER4_TIMER1 output assigned to XBAR3_IN21 input. */
1862     kXBAR3_InputQtimer4Timer2       = 22|0x300U,   /**< QTIMER4_TIMER2 output assigned to XBAR3_IN22 input. */
1863     kXBAR3_InputQtimer4Timer3       = 23|0x300U,   /**< QTIMER4_TIMER3 output assigned to XBAR3_IN23 input. */
1864     kXBAR3_InputRESERVED24          = 24|0x300U,   /**< XBAR3_IN24 input is reserved. */
1865     kXBAR3_InputRESERVED25          = 25|0x300U,   /**< XBAR3_IN25 input is reserved. */
1866     kXBAR3_InputRESERVED26          = 26|0x300U,   /**< XBAR3_IN26 input is reserved. */
1867     kXBAR3_InputRESERVED27          = 27|0x300U,   /**< XBAR3_IN27 input is reserved. */
1868     kXBAR3_InputRESERVED28          = 28|0x300U,   /**< XBAR3_IN28 input is reserved. */
1869     kXBAR3_InputRESERVED29          = 29|0x300U,   /**< XBAR3_IN29 input is reserved. */
1870     kXBAR3_InputRESERVED30          = 30|0x300U,   /**< XBAR3_IN30 input is reserved. */
1871     kXBAR3_InputRESERVED31          = 31|0x300U,   /**< XBAR3_IN31 input is reserved. */
1872     kXBAR3_InputRESERVED32          = 32|0x300U,   /**< XBAR3_IN32 input is reserved. */
1873     kXBAR3_InputRESERVED33          = 33|0x300U,   /**< XBAR3_IN33 input is reserved. */
1874     kXBAR3_InputRESERVED34          = 34|0x300U,   /**< XBAR3_IN34 input is reserved. */
1875     kXBAR3_InputRESERVED35          = 35|0x300U,   /**< XBAR3_IN35 input is reserved. */
1876     kXBAR3_InputRESERVED36          = 36|0x300U,   /**< XBAR3_IN36 input is reserved. */
1877     kXBAR3_InputRESERVED37          = 37|0x300U,   /**< XBAR3_IN37 input is reserved. */
1878     kXBAR3_InputRESERVED38          = 38|0x300U,   /**< XBAR3_IN38 input is reserved. */
1879     kXBAR3_InputRESERVED39          = 39|0x300U,   /**< XBAR3_IN39 input is reserved. */
1880     kXBAR3_InputFlexpwm1Pwm0OutTrig01 = 40|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBAR3_IN40 input. */
1881     kXBAR3_InputFlexpwm1Pwm1OutTrig01 = 41|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBAR3_IN41 input. */
1882     kXBAR3_InputFlexpwm1Pwm2OutTrig01 = 42|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBAR3_IN42 input. */
1883     kXBAR3_InputFlexpwm1Pwm3OutTrig01 = 43|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBAR3_IN43 input. */
1884     kXBAR3_InputFlexpwm2Pwm0OutTrig01 = 44|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBAR3_IN44 input. */
1885     kXBAR3_InputFlexpwm2Pwm1OutTrig01 = 45|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBAR3_IN45 input. */
1886     kXBAR3_InputFlexpwm2Pwm2OutTrig01 = 46|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBAR3_IN46 input. */
1887     kXBAR3_InputFlexpwm2Pwm3OutTrig01 = 47|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBAR3_IN47 input. */
1888     kXBAR3_InputRESERVED48          = 48|0x300U,   /**< XBAR3_IN48 input is reserved. */
1889     kXBAR3_InputRESERVED49          = 49|0x300U,   /**< XBAR3_IN49 input is reserved. */
1890     kXBAR3_InputRESERVED50          = 50|0x300U,   /**< XBAR3_IN50 input is reserved. */
1891     kXBAR3_InputRESERVED51          = 51|0x300U,   /**< XBAR3_IN51 input is reserved. */
1892     kXBAR3_InputRESERVED52          = 52|0x300U,   /**< XBAR3_IN52 input is reserved. */
1893     kXBAR3_InputRESERVED53          = 53|0x300U,   /**< XBAR3_IN53 input is reserved. */
1894     kXBAR3_InputRESERVED54          = 54|0x300U,   /**< XBAR3_IN54 input is reserved. */
1895     kXBAR3_InputRESERVED55          = 55|0x300U,   /**< XBAR3_IN55 input is reserved. */
1896     kXBAR3_InputPit1Trigger0        = 56|0x300U,   /**< PIT1_TRIGGER0 output assigned to XBAR3_IN56 input. */
1897     kXBAR3_InputPit1Trigger1        = 57|0x300U,   /**< PIT1_TRIGGER1 output assigned to XBAR3_IN57 input. */
1898     kXBAR3_InputPit1Trigger2        = 58|0x300U,   /**< PIT1_TRIGGER2 output assigned to XBAR3_IN58 input. */
1899     kXBAR3_InputPit1Trigger3        = 59|0x300U,   /**< PIT1_TRIGGER3 output assigned to XBAR3_IN59 input. */
1900     kXBAR3_InputPit2Trigger0        = 60|0x300U,   /**< PIT2_TRIGGER0 output assigned to XBAR3_IN60 input. */
1901     kXBAR3_InputPit2Trigger1        = 61|0x300U,   /**< PIT2_TRIGGER1 output assigned to XBAR3_IN61 input. */
1902     kXBAR3_InputPit2Trigger2        = 62|0x300U,   /**< PIT2_TRIGGER2 output assigned to XBAR3_IN62 input. */
1903     kXBAR3_InputPit2Trigger3        = 63|0x300U,   /**< PIT2_TRIGGER3 output assigned to XBAR3_IN63 input. */
1904     kXBAR3_InputPit3Trigger0        = 64|0x300U,   /**< PIT3_TRIGGER0 output assigned to XBAR3_IN64 input. */
1905     kXBAR3_InputPit3Trigger1        = 65|0x300U,   /**< PIT3_TRIGGER1 output assigned to XBAR3_IN65 input. */
1906     kXBAR3_InputPit3Trigger2        = 66|0x300U,   /**< PIT3_TRIGGER2 output assigned to XBAR3_IN66 input. */
1907     kXBAR3_InputPit3Trigger3        = 67|0x300U,   /**< PIT3_TRIGGER3 output assigned to XBAR3_IN67 input. */
1908     kXBAR3_InputRESERVED68          = 68|0x300U,   /**< XBAR3_IN68 input is reserved. */
1909     kXBAR3_InputRESERVED69          = 69|0x300U,   /**< XBAR3_IN69 input is reserved. */
1910     kXBAR3_InputRESERVED70          = 70|0x300U,   /**< XBAR3_IN70 input is reserved. */
1911     kXBAR3_InputRESERVED71          = 71|0x300U,   /**< XBAR3_IN71 input is reserved. */
1912     kXBAR3_InputDma4TriggerOut0     = 72|0x300U,   /**< DMA4_TRIGGER_OUT0 output assigned to XBAR3_IN72 input. */
1913     kXBAR3_InputDma4TriggerOut1     = 73|0x300U,   /**< DMA4_TRIGGER_OUT1 output assigned to XBAR3_IN73 input. */
1914     kXBAR3_InputDma4TriggerOut2     = 74|0x300U,   /**< DMA4_TRIGGER_OUT2 output assigned to XBAR3_IN74 input. */
1915     kXBAR3_InputDma4TriggerOut3     = 75|0x300U,   /**< DMA4_TRIGGER_OUT3 output assigned to XBAR3_IN75 input. */
1916     kXBAR3_InputDma4TriggerOut4     = 76|0x300U,   /**< DMA4_TRIGGER_OUT4 output assigned to XBAR3_IN76 input. */
1917     kXBAR3_InputDma4TriggerOut5     = 77|0x300U,   /**< DMA4_TRIGGER_OUT5 output assigned to XBAR3_IN77 input. */
1918     kXBAR3_InputDma4TriggerOut6     = 78|0x300U,   /**< DMA4_TRIGGER_OUT6 output assigned to XBAR3_IN78 input. */
1919     kXBAR3_InputDma4TriggerOut7     = 79|0x300U,   /**< DMA4_TRIGGER_OUT7 output assigned to XBAR3_IN79 input. */
1920     kXBAR3_InputDma3TriggerOut0     = 80|0x300U,   /**< DMA3_TRIGGER_OUT0 output assigned to XBAR3_IN80 input. */
1921     kXBAR3_InputDma3TriggerOut1     = 81|0x300U,   /**< DMA3_TRIGGER_OUT1 output assigned to XBAR3_IN81 input. */
1922     kXBAR3_InputDma3TriggerOut2     = 82|0x300U,   /**< DMA3_TRIGGER_OUT2 output assigned to XBAR3_IN82 input. */
1923     kXBAR3_InputDma3TriggerOut3     = 83|0x300U,   /**< DMA3_TRIGGER_OUT3 output assigned to XBAR3_IN83 input. */
1924     kXBAR3_InputDma3TriggerOut4     = 84|0x300U,   /**< DMA3_TRIGGER_OUT4 output assigned to XBAR3_IN84 input. */
1925     kXBAR3_InputDma3TriggerOut5     = 85|0x300U,   /**< DMA3_TRIGGER_OUT5 output assigned to XBAR3_IN85 input. */
1926     kXBAR3_InputDma3TriggerOut6     = 86|0x300U,   /**< DMA3_TRIGGER_OUT6 output assigned to XBAR3_IN86 input. */
1927     kXBAR3_InputDma3TriggerOut7     = 87|0x300U,   /**< DMA3_TRIGGER_OUT7 output assigned to XBAR3_IN87 input. */
1928     kXBAR3_InputAdc1TcompPulse0     = 88|0x300U,   /**< ADC1_TCOMP_PULSE0 output assigned to XBAR3_IN88 input. */
1929     kXBAR3_InputAdc1TcompPulse1     = 89|0x300U,   /**< ADC1_TCOMP_PULSE1 output assigned to XBAR3_IN89 input. */
1930     kXBAR3_InputAdc1TcompPulse2     = 90|0x300U,   /**< ADC1_TCOMP_PULSE2 output assigned to XBAR3_IN90 input. */
1931     kXBAR3_InputAdc1TcompPulse3     = 91|0x300U,   /**< ADC1_TCOMP_PULSE3 output assigned to XBAR3_IN91 input. */
1932     kXBAR3_InputAdc1TcompPulse4     = 92|0x300U,   /**< ADC1_TCOMP_PULSE4 output assigned to XBAR3_IN92 input. */
1933     kXBAR3_InputAdc1TcompPulse5     = 93|0x300U,   /**< ADC1_TCOMP_PULSE5 output assigned to XBAR3_IN93 input. */
1934     kXBAR3_InputAdc1TcompPulse6     = 94|0x300U,   /**< ADC1_TCOMP_PULSE6 output assigned to XBAR3_IN94 input. */
1935     kXBAR3_InputAdc1TcompPulse7     = 95|0x300U,   /**< ADC1_TCOMP_PULSE7 output assigned to XBAR3_IN95 input. */
1936     kXBAR3_InputRESERVED96          = 96|0x300U,   /**< XBAR3_IN96 input is reserved. */
1937     kXBAR3_InputRESERVED97          = 97|0x300U,   /**< XBAR3_IN97 input is reserved. */
1938     kXBAR3_InputRESERVED98          = 98|0x300U,   /**< XBAR3_IN98 input is reserved. */
1939     kXBAR3_InputRESERVED99          = 99|0x300U,   /**< XBAR3_IN99 input is reserved. */
1940     kXBAR3_InputRESERVED100         = 100|0x300U,  /**< XBAR3_IN100 input is reserved. */
1941     kXBAR3_InputRESERVED101         = 101|0x300U,  /**< XBAR3_IN101 input is reserved. */
1942     kXBAR3_InputRESERVED102         = 102|0x300U,  /**< XBAR3_IN102 input is reserved. */
1943     kXBAR3_InputRESERVED103         = 103|0x300U,  /**< XBAR3_IN103 input is reserved. */
1944     kXBAR3_InputTpm1ChTrigger0      = 104|0x300U,  /**< TPM1_CH_TRIGGER0 output assigned to XBAR3_IN104 input. */
1945     kXBAR3_InputTpm1ChTrigger1      = 105|0x300U,  /**< TPM1_CH_TRIGGER1 output assigned to XBAR3_IN105 input. */
1946     kXBAR3_InputTpm1ChTrigger2      = 106|0x300U,  /**< TPM1_CH_TRIGGER2 output assigned to XBAR3_IN106 input. */
1947     kXBAR3_InputTpm1ChTrigger3      = 107|0x300U,  /**< TPM1_CH_TRIGGER3 output assigned to XBAR3_IN107 input. */
1948     kXBAR3_InputTpm1Trigger         = 108|0x300U,  /**< TPM1_TRIGGER output assigned to XBAR3_IN108 input. */
1949     kXBAR3_InputTpm2ChTrigger0      = 109|0x300U,  /**< TPM2_CH_TRIGGER0 output assigned to XBAR3_IN109 input. */
1950     kXBAR3_InputTpm2ChTrigger1      = 110|0x300U,  /**< TPM2_CH_TRIGGER1 output assigned to XBAR3_IN110 input. */
1951     kXBAR3_InputTpm2ChTrigger2      = 111|0x300U,  /**< TPM2_CH_TRIGGER2 output assigned to XBAR3_IN111 input. */
1952     kXBAR3_InputTpm2ChTrigger3      = 112|0x300U,  /**< TPM2_CH_TRIGGER3 output assigned to XBAR3_IN112 input. */
1953     kXBAR3_InputTpm2Trigger         = 113|0x300U,  /**< TPM2_TRIGGER output assigned to XBAR3_IN113 input. */
1954     kXBAR3_InputTpm3ChTrigger0      = 114|0x300U,  /**< TPM3_CH_TRIGGER0 output assigned to XBAR3_IN114 input. */
1955     kXBAR3_InputTpm3ChTrigger1      = 115|0x300U,  /**< TPM3_CH_TRIGGER1 output assigned to XBAR3_IN115 input. */
1956     kXBAR3_InputTpm3ChTrigger2      = 116|0x300U,  /**< TPM3_CH_TRIGGER2 output assigned to XBAR3_IN116 input. */
1957     kXBAR3_InputTpm3ChTrigger3      = 117|0x300U,  /**< TPM3_CH_TRIGGER3 output assigned to XBAR3_IN117 input. */
1958     kXBAR3_InputTpm3Trigger         = 118|0x300U,  /**< TPM3_TRIGGER output assigned to XBAR3_IN118 input. */
1959     kXBAR3_InputRESERVED119         = 119|0x300U,  /**< XBAR3_IN119 input is reserved. */
1960     kXBAR3_InputRESERVED120         = 120|0x300U,  /**< XBAR3_IN120 input is reserved. */
1961     kXBAR3_InputRESERVED121         = 121|0x300U,  /**< XBAR3_IN121 input is reserved. */
1962     kXBAR3_InputRESERVED122         = 122|0x300U,  /**< XBAR3_IN122 input is reserved. */
1963     kXBAR3_InputRESERVED123         = 123|0x300U,  /**< XBAR3_IN123 input is reserved. */
1964     kXBAR3_InputRESERVED124         = 124|0x300U,  /**< XBAR3_IN124 input is reserved. */
1965     kXBAR3_InputRESERVED125         = 125|0x300U,  /**< XBAR3_IN125 input is reserved. */
1966     kXBAR3_InputRESERVED126         = 126|0x300U,  /**< XBAR3_IN126 input is reserved. */
1967     kXBAR3_InputRESERVED127         = 127|0x300U,  /**< XBAR3_IN127 input is reserved. */
1968     kXBAR3_InputRESERVED128         = 128|0x300U,  /**< XBAR3_IN128 input is reserved. */
1969     kXBAR3_InputRESERVED129         = 129|0x300U,  /**< XBAR3_IN129 input is reserved. */
1970     kXBAR3_InputRESERVED130         = 130|0x300U,  /**< XBAR3_IN130 input is reserved. */
1971     kXBAR3_InputRESERVED131         = 131|0x300U,  /**< XBAR3_IN131 input is reserved. */
1972     kXBAR3_InputRESERVED132         = 132|0x300U,  /**< XBAR3_IN132 input is reserved. */
1973     kXBAR3_InputRESERVED133         = 133|0x300U,  /**< XBAR3_IN133 input is reserved. */
1974     kXBAR3_InputLptmr1TriggerDelay  = 134|0x300U,  /**< LPTMR1_TRIGGER_DELAY output assigned to XBAR3_IN134 input. */
1975     kXBAR3_InputRESERVED135         = 135|0x300U,  /**< XBAR3_IN135 input is reserved. */
1976     kXBAR3_InputRESERVED136         = 136|0x300U,  /**< XBAR3_IN136 input is reserved. */
1977     kXBAR3_InputNetcTmrPp1          = 137|0x300U,  /**< NETC_TMR_PP1 output assigned to XBAR3_IN137 input. */
1978     kXBAR3_InputNetcTmrPp2          = 138|0x300U,  /**< NETC_TMR_PP2 output assigned to XBAR3_IN138 input. */
1979     kXBAR3_InputNetcTmrPp3          = 139|0x300U,  /**< NETC_TMR_PP3 output assigned to XBAR3_IN139 input. */
1980     kXBAR3_InputRESERVED140         = 140|0x300U,  /**< XBAR3_IN140 input is reserved. */
1981     kXBAR3_InputRESERVED141         = 141|0x300U,  /**< XBAR3_IN141 input is reserved. */
1982     kXBAR3_InputRESERVED142         = 142|0x300U,  /**< XBAR3_IN142 input is reserved. */
1983     kXBAR3_InputRESERVED143         = 143|0x300U,  /**< XBAR3_IN143 input is reserved. */
1984     kXBAR3_InputRESERVED144         = 144|0x300U,  /**< XBAR3_IN144 input is reserved. */
1985     kXBAR3_InputRESERVED145         = 145|0x300U,  /**< XBAR3_IN145 input is reserved. */
1986     kXBAR3_InputRESERVED146         = 146|0x300U,  /**< XBAR3_IN146 input is reserved. */
1987     kXBAR3_InputRESERVED147         = 147|0x300U,  /**< XBAR3_IN147 input is reserved. */
1988     kXBAR3_InputRESERVED148         = 148|0x300U,  /**< XBAR3_IN148 input is reserved. */
1989     kXBAR3_InputRESERVED149         = 149|0x300U,  /**< XBAR3_IN149 input is reserved. */
1990     kXBAR3_InputRESERVED150         = 150|0x300U,  /**< XBAR3_IN150 input is reserved. */
1991     kXBAR3_InputRESERVED151         = 151|0x300U,  /**< XBAR3_IN151 input is reserved. */
1992     kXBAR3_InputRESERVED152         = 152|0x300U,  /**< XBAR3_IN152 input is reserved. */
1993     kXBAR3_InputRESERVED153         = 153|0x300U,  /**< XBAR3_IN153 input is reserved. */
1994     kXBAR3_InputRESERVED154         = 154|0x300U,  /**< XBAR3_IN154 input is reserved. */
1995     kXBAR3_InputRESERVED155         = 155|0x300U,  /**< XBAR3_IN155 input is reserved. */
1996     kXBAR3_InputEqdc2PosMatch0      = 156|0x300U,  /**< EQDC2_POS_MATCH0 output assigned to XBAR3_IN156 input. */
1997     kXBAR3_InputEqdc2PosMatch1      = 157|0x300U,  /**< EQDC2_POS_MATCH1 output assigned to XBAR3_IN157 input. */
1998     kXBAR3_InputEqdc2PosMatch2      = 158|0x300U,  /**< EQDC2_POS_MATCH2 output assigned to XBAR3_IN158 input. */
1999     kXBAR3_InputEqdc2PosMatch3      = 159|0x300U,  /**< EQDC2_POS_MATCH3 output assigned to XBAR3_IN159 input. */
2000     kXBAR3_InputEqdc2CompFlg0       = 160|0x300U,  /**< EQDC2_COMP_FLG0 output assigned to XBAR3_IN160 input. */
2001     kXBAR3_InputEqdc2CompFlg1       = 161|0x300U,  /**< EQDC2_COMP_FLG1 output assigned to XBAR3_IN161 input. */
2002     kXBAR3_InputEqdc2CompFlg2       = 162|0x300U,  /**< EQDC2_COMP_FLG2 output assigned to XBAR3_IN162 input. */
2003     kXBAR3_InputEqdc2CompFlg3       = 163|0x300U,  /**< EQDC2_COMP_FLG3 output assigned to XBAR3_IN163 input. */
2004     kXBAR3_InputEqdc2CntDn          = 164|0x300U,  /**< EQDC2_CNT_DN output assigned to XBAR3_IN164 input. */
2005     kXBAR3_InputEqdc2CntUp          = 165|0x300U,  /**< EQDC2_CNT_UP output assigned to XBAR3_IN165 input. */
2006     kXBAR3_InputEqdc2CntDir         = 166|0x300U,  /**< EQDC2_CNT_DIR output assigned to XBAR3_IN166 input. */
2007     kXBAR3_InputRESERVED167         = 167|0x300U,  /**< XBAR3_IN167 input is reserved. */
2008     kXBAR3_InputRESERVED168         = 168|0x300U,  /**< XBAR3_IN168 input is reserved. */
2009     kXBAR3_InputRESERVED169         = 169|0x300U,  /**< XBAR3_IN169 input is reserved. */
2010     kXBAR3_InputRESERVED170         = 170|0x300U,  /**< XBAR3_IN170 input is reserved. */
2011     kXBAR3_InputRESERVED171         = 171|0x300U,  /**< XBAR3_IN171 input is reserved. */
2012     kXBAR3_InputRESERVED172         = 172|0x300U,  /**< XBAR3_IN172 input is reserved. */
2013     kXBAR3_InputRESERVED173         = 173|0x300U,  /**< XBAR3_IN173 input is reserved. */
2014     kXBAR3_InputRESERVED174         = 174|0x300U,  /**< XBAR3_IN174 input is reserved. */
2015     kXBAR3_InputRESERVED175         = 175|0x300U,  /**< XBAR3_IN175 input is reserved. */
2016     kXBAR3_InputRESERVED176         = 176|0x300U,  /**< XBAR3_IN176 input is reserved. */
2017     kXBAR3_InputRESERVED177         = 177|0x300U,  /**< XBAR3_IN177 input is reserved. */
2018 } xbar_input_signal_t;
2019 
2020 typedef enum _xbar_output_signal
2021 {
2022     kXBAR1_OutputDma4MuxReq154      = 0|0x100U,    /**< XBAR1_OUT0 output assigned to DMA4_MUX_REQ154 */
2023     kXBAR1_OutputDma4MuxReq155      = 1|0x100U,    /**< XBAR1_OUT1 output assigned to DMA4_MUX_REQ155 */
2024     kXBAR1_OutputDma4MuxReq156      = 2|0x100U,    /**< XBAR1_OUT2 output assigned to DMA4_MUX_REQ156 */
2025     kXBAR1_OutputDma4MuxReq157      = 3|0x100U,    /**< XBAR1_OUT3 output assigned to DMA4_MUX_REQ157 */
2026     kXBAR1_OutputIomuxXbarInout04   = 4|0x100U,    /**< XBAR1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
2027     kXBAR1_OutputIomuxXbarInout05   = 5|0x100U,    /**< XBAR1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
2028     kXBAR1_OutputIomuxXbarInout06   = 6|0x100U,    /**< XBAR1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
2029     kXBAR1_OutputIomuxXbarInout07   = 7|0x100U,    /**< XBAR1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
2030     kXBAR1_OutputIomuxXbarInout08   = 8|0x100U,    /**< XBAR1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
2031     kXBAR1_OutputIomuxXbarInout09   = 9|0x100U,    /**< XBAR1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
2032     kXBAR1_OutputIomuxXbarInout10   = 10|0x100U,   /**< XBAR1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
2033     kXBAR1_OutputIomuxXbarInout11   = 11|0x100U,   /**< XBAR1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
2034     kXBAR1_OutputIomuxXbarInout12   = 12|0x100U,   /**< XBAR1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
2035     kXBAR1_OutputIomuxXbarInout13   = 13|0x100U,   /**< XBAR1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
2036     kXBAR1_OutputIomuxXbarInout14   = 14|0x100U,   /**< XBAR1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
2037     kXBAR1_OutputIomuxXbarInout15   = 15|0x100U,   /**< XBAR1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
2038     kXBAR1_OutputIomuxXbarInout16   = 16|0x100U,   /**< XBAR1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
2039     kXBAR1_OutputIomuxXbarInout17   = 17|0x100U,   /**< XBAR1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
2040     kXBAR1_OutputIomuxXbarInout18   = 18|0x100U,   /**< XBAR1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
2041     kXBAR1_OutputIomuxXbarInout19   = 19|0x100U,   /**< XBAR1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
2042     kXBAR1_OutputIomuxXbarInout20   = 20|0x100U,   /**< XBAR1_OUT20 output assigned to IOMUX_XBAR_INOUT20 */
2043     kXBAR1_OutputIomuxXbarInout21   = 21|0x100U,   /**< XBAR1_OUT21 output assigned to IOMUX_XBAR_INOUT21 */
2044     kXBAR1_OutputIomuxXbarInout22   = 22|0x100U,   /**< XBAR1_OUT22 output assigned to IOMUX_XBAR_INOUT22 */
2045     kXBAR1_OutputIomuxXbarInout23   = 23|0x100U,   /**< XBAR1_OUT23 output assigned to IOMUX_XBAR_INOUT23 */
2046     kXBAR1_OutputIomuxXbarInout24   = 24|0x100U,   /**< XBAR1_OUT24 output assigned to IOMUX_XBAR_INOUT24 */
2047     kXBAR1_OutputIomuxXbarInout25   = 25|0x100U,   /**< XBAR1_OUT25 output assigned to IOMUX_XBAR_INOUT25 */
2048     kXBAR1_OutputIomuxXbarInout26   = 26|0x100U,   /**< XBAR1_OUT26 output assigned to IOMUX_XBAR_INOUT26 */
2049     kXBAR1_OutputIomuxXbarInout27   = 27|0x100U,   /**< XBAR1_OUT27 output assigned to IOMUX_XBAR_INOUT27 */
2050     kXBAR1_OutputIomuxXbarInout28   = 28|0x100U,   /**< XBAR1_OUT28 output assigned to IOMUX_XBAR_INOUT28 */
2051     kXBAR1_OutputIomuxXbarInout29   = 29|0x100U,   /**< XBAR1_OUT29 output assigned to IOMUX_XBAR_INOUT29 */
2052     kXBAR1_OutputTriggerSyncIn0     = 30|0x100U,   /**< XBAR1_OUT30 output assigned to TRIGGER_SYNC_IN0 */
2053     kXBAR1_OutputTriggerSyncIn1     = 31|0x100U,   /**< XBAR1_OUT31 output assigned to TRIGGER_SYNC_IN1 */
2054     kXBAR1_OutputTriggerSyncIn2     = 32|0x100U,   /**< XBAR1_OUT32 output assigned to TRIGGER_SYNC_IN2 */
2055     kXBAR1_OutputTriggerSyncIn3     = 33|0x100U,   /**< XBAR1_OUT33 output assigned to TRIGGER_SYNC_IN3 */
2056     kXBAR1_OutputTriggerSyncIn4     = 34|0x100U,   /**< XBAR1_OUT34 output assigned to TRIGGER_SYNC_IN4 */
2057     kXBAR1_OutputTriggerSyncIn5     = 35|0x100U,   /**< XBAR1_OUT35 output assigned to TRIGGER_SYNC_IN5 */
2058     kXBAR1_OutputTriggerSyncIn6     = 36|0x100U,   /**< XBAR1_OUT36 output assigned to TRIGGER_SYNC_IN6 */
2059     kXBAR1_OutputTriggerSyncIn7     = 37|0x100U,   /**< XBAR1_OUT37 output assigned to TRIGGER_SYNC_IN7 */
2060     kXBAR1_OutputAcmp1Sample        = 38|0x100U,   /**< XBAR1_OUT38 output assigned to ACMP1_SAMPLE */
2061     kXBAR1_OutputAcmp2Sample        = 39|0x100U,   /**< XBAR1_OUT39 output assigned to ACMP2_SAMPLE */
2062     kXBAR1_OutputAcmp3Sample        = 40|0x100U,   /**< XBAR1_OUT40 output assigned to ACMP3_SAMPLE */
2063     kXBAR1_OutputAcmp4Sample        = 41|0x100U,   /**< XBAR1_OUT41 output assigned to ACMP4_SAMPLE */
2064     kXBAR1_OutputFlexpwm1Exta0      = 42|0x100U,   /**< XBAR1_OUT42 output assigned to FLEXPWM1_EXTA0 */
2065     kXBAR1_OutputFlexpwm1Exta1      = 43|0x100U,   /**< XBAR1_OUT43 output assigned to FLEXPWM1_EXTA1 */
2066     kXBAR1_OutputFlexpwm1Exta2      = 44|0x100U,   /**< XBAR1_OUT44 output assigned to FLEXPWM1_EXTA2 */
2067     kXBAR1_OutputFlexpwm1Exta3      = 45|0x100U,   /**< XBAR1_OUT45 output assigned to FLEXPWM1_EXTA3 */
2068     kXBAR1_OutputFlexpwm1ExtSync0   = 46|0x100U,   /**< XBAR1_OUT46 output assigned to FLEXPWM1_EXT_SYNC0 */
2069     kXBAR1_OutputFlexpwm1ExtSync1   = 47|0x100U,   /**< XBAR1_OUT47 output assigned to FLEXPWM1_EXT_SYNC1 */
2070     kXBAR1_OutputFlexpwm1ExtSync2   = 48|0x100U,   /**< XBAR1_OUT48 output assigned to FLEXPWM1_EXT_SYNC2 */
2071     kXBAR1_OutputFlexpwm1ExtSync3   = 49|0x100U,   /**< XBAR1_OUT49 output assigned to FLEXPWM1_EXT_SYNC3 */
2072     kXBAR1_OutputFlexpwm1ExtClk     = 50|0x100U,   /**< XBAR1_OUT50 output assigned to FLEXPWM1_EXT_CLK */
2073     kXBAR1_OutputFlexpwm1Fault0     = 51|0x100U,   /**< XBAR1_OUT51 output assigned to FLEXPWM1_FAULT0 */
2074     kXBAR1_OutputFlexpwm1Fault1     = 52|0x100U,   /**< XBAR1_OUT52 output assigned to FLEXPWM1_FAULT1 */
2075     kXBAR1_OutputFlexpwm1234Fault2  = 53|0x100U,   /**< XBAR1_OUT53 output assigned to FLEXPWM1_2_3_4_FAULT2 */
2076     kXBAR1_OutputFlexpwm1234Fault3  = 54|0x100U,   /**< XBAR1_OUT54 output assigned to FLEXPWM1_2_3_4_FAULT3 */
2077     kXBAR1_OutputFlexpwm1ExtForce   = 55|0x100U,   /**< XBAR1_OUT55 output assigned to FLEXPWM1_EXT_FORCE */
2078     kXBAR1_OutputFlexpwm2Exta0      = 56|0x100U,   /**< XBAR1_OUT56 output assigned to FLEXPWM2_EXTA0 */
2079     kXBAR1_OutputFlexpwm2Exta1      = 57|0x100U,   /**< XBAR1_OUT57 output assigned to FLEXPWM2_EXTA1 */
2080     kXBAR1_OutputFlexpwm2Exta2      = 58|0x100U,   /**< XBAR1_OUT58 output assigned to FLEXPWM2_EXTA2 */
2081     kXBAR1_OutputFlexpwm2Exta3      = 59|0x100U,   /**< XBAR1_OUT59 output assigned to FLEXPWM2_EXTA3 */
2082     kXBAR1_OutputFlexpwm2ExtSync0   = 60|0x100U,   /**< XBAR1_OUT60 output assigned to FLEXPWM2_EXT_SYNC0 */
2083     kXBAR1_OutputFlexpwm2ExtSync1   = 61|0x100U,   /**< XBAR1_OUT61 output assigned to FLEXPWM2_EXT_SYNC1 */
2084     kXBAR1_OutputFlexpwm2ExtSync2   = 62|0x100U,   /**< XBAR1_OUT62 output assigned to FLEXPWM2_EXT_SYNC2 */
2085     kXBAR1_OutputFlexpwm2ExtSync3   = 63|0x100U,   /**< XBAR1_OUT63 output assigned to FLEXPWM2_EXT_SYNC3 */
2086     kXBAR1_OutputFlexpwm2ExtClk     = 64|0x100U,   /**< XBAR1_OUT64 output assigned to FLEXPWM2_EXT_CLK */
2087     kXBAR1_OutputFlexpwm2Fault0     = 65|0x100U,   /**< XBAR1_OUT65 output assigned to FLEXPWM2_FAULT0 */
2088     kXBAR1_OutputFlexpwm2Fault1     = 66|0x100U,   /**< XBAR1_OUT66 output assigned to FLEXPWM2_FAULT1 */
2089     kXBAR1_OutputFlexpwm2ExtForce   = 67|0x100U,   /**< XBAR1_OUT67 output assigned to FLEXPWM2_EXT_FORCE */
2090     kXBAR1_OutputRESERVED68         = 68|0x100U,   /**< XBAR1_OUT68 output is reserved. */
2091     kXBAR1_OutputRESERVED69         = 69|0x100U,   /**< XBAR1_OUT69 output is reserved. */
2092     kXBAR1_OutputRESERVED70         = 70|0x100U,   /**< XBAR1_OUT70 output is reserved. */
2093     kXBAR1_OutputRESERVED71         = 71|0x100U,   /**< XBAR1_OUT71 output is reserved. */
2094     kXBAR1_OutputRESERVED72         = 72|0x100U,   /**< XBAR1_OUT72 output is reserved. */
2095     kXBAR1_OutputRESERVED73         = 73|0x100U,   /**< XBAR1_OUT73 output is reserved. */
2096     kXBAR1_OutputRESERVED74         = 74|0x100U,   /**< XBAR1_OUT74 output is reserved. */
2097     kXBAR1_OutputRESERVED75         = 75|0x100U,   /**< XBAR1_OUT75 output is reserved. */
2098     kXBAR1_OutputRESERVED76         = 76|0x100U,   /**< XBAR1_OUT76 output is reserved. */
2099     kXBAR1_OutputRESERVED77         = 77|0x100U,   /**< XBAR1_OUT77 output is reserved. */
2100     kXBAR1_OutputRESERVED78         = 78|0x100U,   /**< XBAR1_OUT78 output is reserved. */
2101     kXBAR1_OutputRESERVED79         = 79|0x100U,   /**< XBAR1_OUT79 output is reserved. */
2102     kXBAR1_OutputRESERVED80         = 80|0x100U,   /**< XBAR1_OUT80 output is reserved. */
2103     kXBAR1_OutputRESERVED81         = 81|0x100U,   /**< XBAR1_OUT81 output is reserved. */
2104     kXBAR1_OutputRESERVED82         = 82|0x100U,   /**< XBAR1_OUT82 output is reserved. */
2105     kXBAR1_OutputRESERVED83         = 83|0x100U,   /**< XBAR1_OUT83 output is reserved. */
2106     kXBAR1_OutputRESERVED84         = 84|0x100U,   /**< XBAR1_OUT84 output is reserved. */
2107     kXBAR1_OutputRESERVED85         = 85|0x100U,   /**< XBAR1_OUT85 output is reserved. */
2108     kXBAR1_OutputRESERVED86         = 86|0x100U,   /**< XBAR1_OUT86 output is reserved. */
2109     kXBAR1_OutputEqdc1Phasea        = 87|0x100U,   /**< XBAR1_OUT87 output assigned to EQDC1_PHASEA */
2110     kXBAR1_OutputEqdc1Phaseb        = 88|0x100U,   /**< XBAR1_OUT88 output assigned to EQDC1_PHASEB */
2111     kXBAR1_OutputEqdc1Index         = 89|0x100U,   /**< XBAR1_OUT89 output assigned to EQDC1_INDEX */
2112     kXBAR1_OutputEqdc1Home          = 90|0x100U,   /**< XBAR1_OUT90 output assigned to EQDC1_HOME */
2113     kXBAR1_OutputEqdc1Trigger       = 91|0x100U,   /**< XBAR1_OUT91 output assigned to EQDC1_TRIGGER */
2114     kXBAR1_OutputEqdc2Phasea        = 92|0x100U,   /**< XBAR1_OUT92 output assigned to EQDC2_PHASEA */
2115     kXBAR1_OutputEqdc2Phaseb        = 93|0x100U,   /**< XBAR1_OUT93 output assigned to EQDC2_PHASEB */
2116     kXBAR1_OutputEqdc2Index         = 94|0x100U,   /**< XBAR1_OUT94 output assigned to EQDC2_INDEX */
2117     kXBAR1_OutputEqdc2Home          = 95|0x100U,   /**< XBAR1_OUT95 output assigned to EQDC2_HOME */
2118     kXBAR1_OutputEqdc2Trigger       = 96|0x100U,   /**< XBAR1_OUT96 output assigned to EQDC2_TRIGGER */
2119     kXBAR1_OutputRESERVED97         = 97|0x100U,   /**< XBAR1_OUT97 output is reserved. */
2120     kXBAR1_OutputRESERVED98         = 98|0x100U,   /**< XBAR1_OUT98 output is reserved. */
2121     kXBAR1_OutputRESERVED99         = 99|0x100U,   /**< XBAR1_OUT99 output is reserved. */
2122     kXBAR1_OutputRESERVED100        = 100|0x100U,  /**< XBAR1_OUT100 output is reserved. */
2123     kXBAR1_OutputRESERVED101        = 101|0x100U,  /**< XBAR1_OUT101 output is reserved. */
2124     kXBAR1_OutputRESERVED102        = 102|0x100U,  /**< XBAR1_OUT102 output is reserved. */
2125     kXBAR1_OutputRESERVED103        = 103|0x100U,  /**< XBAR1_OUT103 output is reserved. */
2126     kXBAR1_OutputRESERVED104        = 104|0x100U,  /**< XBAR1_OUT104 output is reserved. */
2127     kXBAR1_OutputRESERVED105        = 105|0x100U,  /**< XBAR1_OUT105 output is reserved. */
2128     kXBAR1_OutputRESERVED106        = 106|0x100U,  /**< XBAR1_OUT106 output is reserved. */
2129     kXBAR1_OutputQtimer1Timer0      = 107|0x100U,  /**< XBAR1_OUT107 output assigned to QTIMER1_TIMER0 */
2130     kXBAR1_OutputQtimer1Timer1      = 108|0x100U,  /**< XBAR1_OUT108 output assigned to QTIMER1_TIMER1 */
2131     kXBAR1_OutputQtimer1Timer2      = 109|0x100U,  /**< XBAR1_OUT109 output assigned to QTIMER1_TIMER2 */
2132     kXBAR1_OutputQtimer1Timer3      = 110|0x100U,  /**< XBAR1_OUT110 output assigned to QTIMER1_TIMER3 */
2133     kXBAR1_OutputQtimer2Timer0      = 111|0x100U,  /**< XBAR1_OUT111 output assigned to QTIMER2_TIMER0 */
2134     kXBAR1_OutputQtimer2Timer1      = 112|0x100U,  /**< XBAR1_OUT112 output assigned to QTIMER2_TIMER1 */
2135     kXBAR1_OutputQtimer2Timer2      = 113|0x100U,  /**< XBAR1_OUT113 output assigned to QTIMER2_TIMER2 */
2136     kXBAR1_OutputQtimer2Timer3      = 114|0x100U,  /**< XBAR1_OUT114 output assigned to QTIMER2_TIMER3 */
2137     kXBAR1_OutputQtimer3Timer0      = 115|0x100U,  /**< XBAR1_OUT115 output assigned to QTIMER3_TIMER0 */
2138     kXBAR1_OutputQtimer3Timer1      = 116|0x100U,  /**< XBAR1_OUT116 output assigned to QTIMER3_TIMER1 */
2139     kXBAR1_OutputQtimer3Timer2      = 117|0x100U,  /**< XBAR1_OUT117 output assigned to QTIMER3_TIMER2 */
2140     kXBAR1_OutputQtimer3Timer3      = 118|0x100U,  /**< XBAR1_OUT118 output assigned to QTIMER3_TIMER3 */
2141     kXBAR1_OutputQtimer4Timer0      = 119|0x100U,  /**< XBAR1_OUT119 output assigned to QTIMER4_TIMER0 */
2142     kXBAR1_OutputQtimer4Timer1      = 120|0x100U,  /**< XBAR1_OUT120 output assigned to QTIMER4_TIMER1 */
2143     kXBAR1_OutputQtimer4Timer2      = 121|0x100U,  /**< XBAR1_OUT121 output assigned to QTIMER4_TIMER2 */
2144     kXBAR1_OutputQtimer4Timer3      = 122|0x100U,  /**< XBAR1_OUT122 output assigned to QTIMER4_TIMER3 */
2145     kXBAR1_OutputRESERVED123        = 123|0x100U,  /**< XBAR1_OUT123 output is reserved. */
2146     kXBAR1_OutputRESERVED124        = 124|0x100U,  /**< XBAR1_OUT124 output is reserved. */
2147     kXBAR1_OutputRESERVED125        = 125|0x100U,  /**< XBAR1_OUT125 output is reserved. */
2148     kXBAR1_OutputRESERVED126        = 126|0x100U,  /**< XBAR1_OUT126 output is reserved. */
2149     kXBAR1_OutputRESERVED127        = 127|0x100U,  /**< XBAR1_OUT127 output is reserved. */
2150     kXBAR1_OutputRESERVED128        = 128|0x100U,  /**< XBAR1_OUT128 output is reserved. */
2151     kXBAR1_OutputRESERVED129        = 129|0x100U,  /**< XBAR1_OUT129 output is reserved. */
2152     kXBAR1_OutputRESERVED130        = 130|0x100U,  /**< XBAR1_OUT130 output is reserved. */
2153     kXBAR1_OutputRESERVED131        = 131|0x100U,  /**< XBAR1_OUT131 output is reserved. */
2154     kXBAR1_OutputRESERVED132        = 132|0x100U,  /**< XBAR1_OUT132 output is reserved. */
2155     kXBAR1_OutputRESERVED133        = 133|0x100U,  /**< XBAR1_OUT133 output is reserved. */
2156     kXBAR1_OutputRESERVED134        = 134|0x100U,  /**< XBAR1_OUT134 output is reserved. */
2157     kXBAR1_OutputRESERVED135        = 135|0x100U,  /**< XBAR1_OUT135 output is reserved. */
2158     kXBAR1_OutputRESERVED136        = 136|0x100U,  /**< XBAR1_OUT136 output is reserved. */
2159     kXBAR1_OutputRESERVED137        = 137|0x100U,  /**< XBAR1_OUT137 output is reserved. */
2160     kXBAR1_OutputRESERVED138        = 138|0x100U,  /**< XBAR1_OUT138 output is reserved. */
2161     kXBAR1_OutputEwmIn              = 139|0x100U,  /**< XBAR1_OUT139 output assigned to EWM_IN */
2162     kXBAR1_OutputAdc12HwTrig0       = 140|0x100U,  /**< XBAR1_OUT140 output assigned to ADC1_2_HW_TRIG0 */
2163     kXBAR1_OutputAdc12HwTrig1       = 141|0x100U,  /**< XBAR1_OUT141 output assigned to ADC1_2_HW_TRIG1 */
2164     kXBAR1_OutputAdc12HwTrig2       = 142|0x100U,  /**< XBAR1_OUT142 output assigned to ADC1_2_HW_TRIG2 */
2165     kXBAR1_OutputAdc12HwTrig3       = 143|0x100U,  /**< XBAR1_OUT143 output assigned to ADC1_2_HW_TRIG3 */
2166     kXBAR1_OutputAdc12HwTrig4       = 144|0x100U,  /**< XBAR1_OUT144 output assigned to ADC1_2_HW_TRIG4 */
2167     kXBAR1_OutputAdc12HwTrig5       = 145|0x100U,  /**< XBAR1_OUT145 output assigned to ADC1_2_HW_TRIG5 */
2168     kXBAR1_OutputAdc12HwTrig6       = 146|0x100U,  /**< XBAR1_OUT146 output assigned to ADC1_2_HW_TRIG6 */
2169     kXBAR1_OutputAdc12HwTrig7       = 147|0x100U,  /**< XBAR1_OUT147 output assigned to ADC1_2_HW_TRIG7 */
2170     kXBAR1_OutputRESERVED148        = 148|0x100U,  /**< XBAR1_OUT148 output is reserved. */
2171     kXBAR1_OutputRESERVED149        = 149|0x100U,  /**< XBAR1_OUT149 output is reserved. */
2172     kXBAR1_OutputRESERVED150        = 150|0x100U,  /**< XBAR1_OUT150 output is reserved. */
2173     kXBAR1_OutputRESERVED151        = 151|0x100U,  /**< XBAR1_OUT151 output is reserved. */
2174     kXBAR1_OutputFlexio1TrigIn0     = 152|0x100U,  /**< XBAR1_OUT152 output assigned to FLEXIO1_TRIG_IN0 */
2175     kXBAR1_OutputFlexio1TrigIn1     = 153|0x100U,  /**< XBAR1_OUT153 output assigned to FLEXIO1_TRIG_IN1 */
2176     kXBAR1_OutputFlexio2TrigIn0     = 154|0x100U,  /**< XBAR1_OUT154 output assigned to FLEXIO2_TRIG_IN0 */
2177     kXBAR1_OutputFlexio2TrigIn1     = 155|0x100U,  /**< XBAR1_OUT155 output assigned to FLEXIO2_TRIG_IN1 */
2178     kXBAR1_OutputLpi2c1TrigIn       = 156|0x100U,  /**< XBAR1_OUT156 output assigned to LPI2C1_TRIG_IN */
2179     kXBAR1_OutputLpi2c2TrigIn       = 157|0x100U,  /**< XBAR1_OUT157 output assigned to LPI2C2_TRIG_IN */
2180     kXBAR1_OutputLpi2c3TrigIn       = 158|0x100U,  /**< XBAR1_OUT158 output assigned to LPI2C3_TRIG_IN */
2181     kXBAR1_OutputRESERVED159        = 159|0x100U,  /**< XBAR1_OUT159 output is reserved. */
2182     kXBAR1_OutputRESERVED160        = 160|0x100U,  /**< XBAR1_OUT160 output is reserved. */
2183     kXBAR1_OutputRESERVED161        = 161|0x100U,  /**< XBAR1_OUT161 output is reserved. */
2184     kXBAR1_OutputLpspi1TrigIn       = 162|0x100U,  /**< XBAR1_OUT162 output assigned to LPSPI1_TRIG_IN */
2185     kXBAR1_OutputLpspi2TrigIn       = 163|0x100U,  /**< XBAR1_OUT163 output assigned to LPSPI2_TRIG_IN */
2186     kXBAR1_OutputLpspi3TrigIn       = 164|0x100U,  /**< XBAR1_OUT164 output assigned to LPSPI3_TRIG_IN */
2187     kXBAR1_OutputLpspi4TrigIn       = 165|0x100U,  /**< XBAR1_OUT165 output assigned to LPSPI4_TRIG_IN */
2188     kXBAR1_OutputRESERVED166        = 166|0x100U,  /**< XBAR1_OUT166 output is reserved. */
2189     kXBAR1_OutputRESERVED167        = 167|0x100U,  /**< XBAR1_OUT167 output is reserved. */
2190     kXBAR1_OutputLpuart1TrigIn      = 168|0x100U,  /**< XBAR1_OUT168 output assigned to LPUART1_TRIG_IN */
2191     kXBAR1_OutputLpuart2TrigIn      = 169|0x100U,  /**< XBAR1_OUT169 output assigned to LPUART2_TRIG_IN */
2192     kXBAR1_OutputLpuart3TrigIn      = 170|0x100U,  /**< XBAR1_OUT170 output assigned to LPUART3_TRIG_IN */
2193     kXBAR1_OutputLpuart4TrigIn      = 171|0x100U,  /**< XBAR1_OUT171 output assigned to LPUART4_TRIG_IN */
2194     kXBAR1_OutputLpuart5TrigIn      = 172|0x100U,  /**< XBAR1_OUT172 output assigned to LPUART5_TRIG_IN */
2195     kXBAR1_OutputLpuart6TrigIn      = 173|0x100U,  /**< XBAR1_OUT173 output assigned to LPUART6_TRIG_IN */
2196     kXBAR1_OutputLpuart7TrigIn      = 174|0x100U,  /**< XBAR1_OUT174 output assigned to LPUART7_TRIG_IN */
2197     kXBAR1_OutputLpuart8TrigIn      = 175|0x100U,  /**< XBAR1_OUT175 output assigned to LPUART8_TRIG_IN */
2198     kXBAR1_OutputRESERVED176        = 176|0x100U,  /**< XBAR1_OUT176 output is reserved. */
2199     kXBAR1_OutputRESERVED177        = 177|0x100U,  /**< XBAR1_OUT177 output is reserved. */
2200     kXBAR1_OutputRESERVED178        = 178|0x100U,  /**< XBAR1_OUT178 output is reserved. */
2201     kXBAR1_OutputRESERVED179        = 179|0x100U,  /**< XBAR1_OUT179 output is reserved. */
2202     kXBAR1_OutputLpit123TrigIn0     = 180|0x100U,  /**< XBAR1_OUT180 output assigned to LPIT1_2_3_TRIG_IN0 */
2203     kXBAR1_OutputLpit123TrigIn1     = 181|0x100U,  /**< XBAR1_OUT181 output assigned to LPIT1_2_3_TRIG_IN1 */
2204     kXBAR1_OutputLpit123TrigIn2     = 182|0x100U,  /**< XBAR1_OUT182 output assigned to LPIT1_2_3_TRIG_IN2 */
2205     kXBAR1_OutputLpit123TrigIn3     = 183|0x100U,  /**< XBAR1_OUT183 output assigned to LPIT1_2_3_TRIG_IN3 */
2206     kXBAR1_OutputTpm123TrigIn0      = 184|0x100U,  /**< XBAR1_OUT184 output assigned to TPM1_2_3_TRIG_IN0 */
2207     kXBAR1_OutputTpm1TrigIn1        = 185|0x100U,  /**< XBAR1_OUT185 output assigned to TPM1_TRIG_IN1 */
2208     kXBAR1_OutputTpm2TrigIn1        = 186|0x100U,  /**< XBAR1_OUT186 output assigned to TPM2_TRIG_IN1 */
2209     kXBAR1_OutputTpm3TrigIn1        = 187|0x100U,  /**< XBAR1_OUT187 output assigned to TPM3_TRIG_IN1 */
2210     kXBAR1_OutputTpm123TrigIn2      = 188|0x100U,  /**< XBAR1_OUT188 output assigned to TPM1_2_3_TRIG_IN2 */
2211     kXBAR1_OutputTpm1TrigIn3        = 189|0x100U,  /**< XBAR1_OUT189 output assigned to TPM1_TRIG_IN3 */
2212     kXBAR1_OutputTpm2TrigIn3        = 190|0x100U,  /**< XBAR1_OUT190 output assigned to TPM2_TRIG_IN3 */
2213     kXBAR1_OutputTpm3TrigIn3        = 191|0x100U,  /**< XBAR1_OUT191 output assigned to TPM3_TRIG_IN3 */
2214     kXBAR1_OutputRESERVED192        = 192|0x100U,  /**< XBAR1_OUT192 output is reserved. */
2215     kXBAR1_OutputRESERVED193        = 193|0x100U,  /**< XBAR1_OUT193 output is reserved. */
2216     kXBAR1_OutputRESERVED194        = 194|0x100U,  /**< XBAR1_OUT194 output is reserved. */
2217     kXBAR1_OutputRESERVED195        = 195|0x100U,  /**< XBAR1_OUT195 output is reserved. */
2218     kXBAR1_OutputRESERVED196        = 196|0x100U,  /**< XBAR1_OUT196 output is reserved. */
2219     kXBAR1_OutputRESERVED197        = 197|0x100U,  /**< XBAR1_OUT197 output is reserved. */
2220     kXBAR1_OutputRESERVED198        = 198|0x100U,  /**< XBAR1_OUT198 output is reserved. */
2221     kXBAR1_OutputRESERVED199        = 199|0x100U,  /**< XBAR1_OUT199 output is reserved. */
2222     kXBAR1_OutputNetcTmrTrig1       = 200|0x100U,  /**< XBAR1_OUT200 output assigned to NETC_TMR_TRIG1 */
2223     kXBAR1_OutputNetcTmrTrig2       = 201|0x100U,  /**< XBAR1_OUT201 output assigned to NETC_TMR_TRIG2 */
2224     kXBAR1_OutputRESERVED202        = 202|0x100U,  /**< XBAR1_OUT202 output is reserved. */
2225     kXBAR1_OutputRESERVED203        = 203|0x100U,  /**< XBAR1_OUT203 output is reserved. */
2226     kXBAR1_OutputRESERVED204        = 204|0x100U,  /**< XBAR1_OUT204 output is reserved. */
2227     kXBAR1_OutputRESERVED205        = 205|0x100U,  /**< XBAR1_OUT205 output is reserved. */
2228     kXBAR1_OutputEqdc1Icap1         = 206|0x100U,  /**< XBAR1_OUT206 output assigned to EQDC1_ICAP1 */
2229     kXBAR1_OutputEqdc1Icap2         = 207|0x100U,  /**< XBAR1_OUT207 output assigned to EQDC1_ICAP2 */
2230     kXBAR1_OutputEqdc1Icap3         = 208|0x100U,  /**< XBAR1_OUT208 output assigned to EQDC1_ICAP3 */
2231     kXBAR1_OutputEqdc2Icap1         = 209|0x100U,  /**< XBAR1_OUT209 output assigned to EQDC2_ICAP1 */
2232     kXBAR1_OutputEqdc2Icap2         = 210|0x100U,  /**< XBAR1_OUT210 output assigned to EQDC2_ICAP2 */
2233     kXBAR1_OutputEqdc2Icap3         = 211|0x100U,  /**< XBAR1_OUT211 output assigned to EQDC2_ICAP3 */
2234     kXBAR1_OutputRESERVED212        = 212|0x100U,  /**< XBAR1_OUT212 output is reserved. */
2235     kXBAR1_OutputRESERVED213        = 213|0x100U,  /**< XBAR1_OUT213 output is reserved. */
2236     kXBAR1_OutputRESERVED214        = 214|0x100U,  /**< XBAR1_OUT214 output is reserved. */
2237     kXBAR1_OutputRESERVED215        = 215|0x100U,  /**< XBAR1_OUT215 output is reserved. */
2238     kXBAR1_OutputRESERVED216        = 216|0x100U,  /**< XBAR1_OUT216 output is reserved. */
2239     kXBAR1_OutputRESERVED217        = 217|0x100U,  /**< XBAR1_OUT217 output is reserved. */
2240     kXBAR1_OutputEcatLatchIn0       = 218|0x100U,  /**< XBAR1_OUT218 output assigned to ECAT_LATCH_IN0 */
2241     kXBAR1_OutputEcatLatchIn1       = 219|0x100U,  /**< XBAR1_OUT219 output assigned to ECAT_LATCH_IN1 */
2242     kXBAR1_OutputDutClk             = 220|0x100U,  /**< XBAR1_OUT220 output assigned to DUT_CLK */
2243     kXBAR2_OutputAoi1In00           = 0|0x200U,    /**< XBAR2_OUT0 output assigned to AOI1_IN00 */
2244     kXBAR2_OutputAoi1In01           = 1|0x200U,    /**< XBAR2_OUT1 output assigned to AOI1_IN01 */
2245     kXBAR2_OutputAoi1In02           = 2|0x200U,    /**< XBAR2_OUT2 output assigned to AOI1_IN02 */
2246     kXBAR2_OutputAoi1In03           = 3|0x200U,    /**< XBAR2_OUT3 output assigned to AOI1_IN03 */
2247     kXBAR2_OutputAoi1In04           = 4|0x200U,    /**< XBAR2_OUT4 output assigned to AOI1_IN04 */
2248     kXBAR2_OutputAoi1In05           = 5|0x200U,    /**< XBAR2_OUT5 output assigned to AOI1_IN05 */
2249     kXBAR2_OutputAoi1In06           = 6|0x200U,    /**< XBAR2_OUT6 output assigned to AOI1_IN06 */
2250     kXBAR2_OutputAoi1In07           = 7|0x200U,    /**< XBAR2_OUT7 output assigned to AOI1_IN07 */
2251     kXBAR2_OutputAoi1In08           = 8|0x200U,    /**< XBAR2_OUT8 output assigned to AOI1_IN08 */
2252     kXBAR2_OutputAoi1In09           = 9|0x200U,    /**< XBAR2_OUT9 output assigned to AOI1_IN09 */
2253     kXBAR2_OutputAoi1In10           = 10|0x200U,   /**< XBAR2_OUT10 output assigned to AOI1_IN10 */
2254     kXBAR2_OutputAoi1In11           = 11|0x200U,   /**< XBAR2_OUT11 output assigned to AOI1_IN11 */
2255     kXBAR2_OutputAoi1In12           = 12|0x200U,   /**< XBAR2_OUT12 output assigned to AOI1_IN12 */
2256     kXBAR2_OutputAoi1In13           = 13|0x200U,   /**< XBAR2_OUT13 output assigned to AOI1_IN13 */
2257     kXBAR2_OutputAoi1In14           = 14|0x200U,   /**< XBAR2_OUT14 output assigned to AOI1_IN14 */
2258     kXBAR2_OutputAoi1In15           = 15|0x200U,   /**< XBAR2_OUT15 output assigned to AOI1_IN15 */
2259     kXBAR2_OutputAoi3In00           = 16|0x200U,   /**< XBAR2_OUT16 output assigned to AOI3_IN00 */
2260     kXBAR2_OutputAoi3In01           = 17|0x200U,   /**< XBAR2_OUT17 output assigned to AOI3_IN01 */
2261     kXBAR2_OutputAoi3In02           = 18|0x200U,   /**< XBAR2_OUT18 output assigned to AOI3_IN02 */
2262     kXBAR2_OutputAoi3In03           = 19|0x200U,   /**< XBAR2_OUT19 output assigned to AOI3_IN03 */
2263     kXBAR2_OutputAoi3In04           = 20|0x200U,   /**< XBAR2_OUT20 output assigned to AOI3_IN04 */
2264     kXBAR2_OutputAoi3In05           = 21|0x200U,   /**< XBAR2_OUT21 output assigned to AOI3_IN05 */
2265     kXBAR2_OutputAoi3In06           = 22|0x200U,   /**< XBAR2_OUT22 output assigned to AOI3_IN06 */
2266     kXBAR2_OutputAoi3In07           = 23|0x200U,   /**< XBAR2_OUT23 output assigned to AOI3_IN07 */
2267     kXBAR2_OutputAoi3In08           = 24|0x200U,   /**< XBAR2_OUT24 output assigned to AOI3_IN08 */
2268     kXBAR2_OutputAoi3In09           = 25|0x200U,   /**< XBAR2_OUT25 output assigned to AOI3_IN09 */
2269     kXBAR2_OutputAoi3In10           = 26|0x200U,   /**< XBAR2_OUT26 output assigned to AOI3_IN10 */
2270     kXBAR2_OutputAoi3In11           = 27|0x200U,   /**< XBAR2_OUT27 output assigned to AOI3_IN11 */
2271     kXBAR2_OutputAoi3In12           = 28|0x200U,   /**< XBAR2_OUT28 output assigned to AOI3_IN12 */
2272     kXBAR2_OutputAoi3In13           = 29|0x200U,   /**< XBAR2_OUT29 output assigned to AOI3_IN13 */
2273     kXBAR2_OutputAoi3In14           = 30|0x200U,   /**< XBAR2_OUT30 output assigned to AOI3_IN14 */
2274     kXBAR2_OutputAoi3In15           = 31|0x200U,   /**< XBAR2_OUT31 output assigned to AOI3_IN15 */
2275     kXBAR3_OutputAoi2In00           = 0|0x300U,    /**< XBAR3_OUT0 output assigned to AOI2_IN00 */
2276     kXBAR3_OutputAoi2In01           = 1|0x300U,    /**< XBAR3_OUT1 output assigned to AOI2_IN01 */
2277     kXBAR3_OutputAoi2In02           = 2|0x300U,    /**< XBAR3_OUT2 output assigned to AOI2_IN02 */
2278     kXBAR3_OutputAoi2In03           = 3|0x300U,    /**< XBAR3_OUT3 output assigned to AOI2_IN03 */
2279     kXBAR3_OutputAoi2In04           = 4|0x300U,    /**< XBAR3_OUT4 output assigned to AOI2_IN04 */
2280     kXBAR3_OutputAoi2In05           = 5|0x300U,    /**< XBAR3_OUT5 output assigned to AOI2_IN05 */
2281     kXBAR3_OutputAoi2In06           = 6|0x300U,    /**< XBAR3_OUT6 output assigned to AOI2_IN06 */
2282     kXBAR3_OutputAoi2In07           = 7|0x300U,    /**< XBAR3_OUT7 output assigned to AOI2_IN07 */
2283     kXBAR3_OutputAoi2In08           = 8|0x300U,    /**< XBAR3_OUT8 output assigned to AOI2_IN08 */
2284     kXBAR3_OutputAoi2In09           = 9|0x300U,    /**< XBAR3_OUT9 output assigned to AOI2_IN09 */
2285     kXBAR3_OutputAoi2In10           = 10|0x300U,   /**< XBAR3_OUT10 output assigned to AOI2_IN10 */
2286     kXBAR3_OutputAoi2In11           = 11|0x300U,   /**< XBAR3_OUT11 output assigned to AOI2_IN11 */
2287     kXBAR3_OutputAoi2In12           = 12|0x300U,   /**< XBAR3_OUT12 output assigned to AOI2_IN12 */
2288     kXBAR3_OutputAoi2In13           = 13|0x300U,   /**< XBAR3_OUT13 output assigned to AOI2_IN13 */
2289     kXBAR3_OutputAoi2In14           = 14|0x300U,   /**< XBAR3_OUT14 output assigned to AOI2_IN14 */
2290     kXBAR3_OutputAoi2In15           = 15|0x300U,   /**< XBAR3_OUT15 output assigned to AOI2_IN15 */
2291     kXBAR3_OutputAoi4In00           = 16|0x300U,   /**< XBAR3_OUT16 output assigned to AOI4_IN00 */
2292     kXBAR3_OutputAoi4In01           = 17|0x300U,   /**< XBAR3_OUT17 output assigned to AOI4_IN01 */
2293     kXBAR3_OutputAoi4In02           = 18|0x300U,   /**< XBAR3_OUT18 output assigned to AOI4_IN02 */
2294     kXBAR3_OutputAoi4In03           = 19|0x300U,   /**< XBAR3_OUT19 output assigned to AOI4_IN03 */
2295     kXBAR3_OutputAoi4In04           = 20|0x300U,   /**< XBAR3_OUT20 output assigned to AOI4_IN04 */
2296     kXBAR3_OutputAoi4In05           = 21|0x300U,   /**< XBAR3_OUT21 output assigned to AOI4_IN05 */
2297     kXBAR3_OutputAoi4In06           = 22|0x300U,   /**< XBAR3_OUT22 output assigned to AOI4_IN06 */
2298     kXBAR3_OutputAoi4In07           = 23|0x300U,   /**< XBAR3_OUT23 output assigned to AOI4_IN07 */
2299     kXBAR3_OutputAoi4In08           = 24|0x300U,   /**< XBAR3_OUT24 output assigned to AOI4_IN08 */
2300     kXBAR3_OutputAoi4In09           = 25|0x300U,   /**< XBAR3_OUT25 output assigned to AOI4_IN09 */
2301     kXBAR3_OutputAoi4In10           = 26|0x300U,   /**< XBAR3_OUT26 output assigned to AOI4_IN10 */
2302     kXBAR3_OutputAoi4In11           = 27|0x300U,   /**< XBAR3_OUT27 output assigned to AOI4_IN11 */
2303     kXBAR3_OutputAoi4In12           = 28|0x300U,   /**< XBAR3_OUT28 output assigned to AOI4_IN12 */
2304     kXBAR3_OutputAoi4In13           = 29|0x300U,   /**< XBAR3_OUT29 output assigned to AOI4_IN13 */
2305     kXBAR3_OutputAoi4In14           = 30|0x300U,   /**< XBAR3_OUT30 output assigned to AOI4_IN14 */
2306     kXBAR3_OutputAoi4In15           = 31|0x300U,   /**< XBAR3_OUT31 output assigned to AOI4_IN15 */
2307 } xbar_output_signal_t;
2308 
2309 
2310 /*!
2311  * @}
2312  */ /* end of group Mapping_Information */
2313 
2314 
2315 /* ----------------------------------------------------------------------------
2316    -- Device Peripheral Access Layer
2317    ---------------------------------------------------------------------------- */
2318 
2319 /*!
2320  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
2321  * @{
2322  */
2323 
2324 
2325 /*
2326 ** Start of section using anonymous unions
2327 */
2328 
2329 #if defined(__ARMCC_VERSION)
2330   #if (__ARMCC_VERSION >= 6010050)
2331     #pragma clang diagnostic push
2332   #else
2333     #pragma push
2334     #pragma anon_unions
2335   #endif
2336 #elif defined(__GNUC__)
2337   /* anonymous unions are enabled by default */
2338 #elif defined(__IAR_SYSTEMS_ICC__)
2339   #pragma language=extended
2340 #else
2341   #error Not supported compiler type
2342 #endif
2343 
2344 /* ----------------------------------------------------------------------------
2345    -- ADC Peripheral Access Layer
2346    ---------------------------------------------------------------------------- */
2347 
2348 /*!
2349  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
2350  * @{
2351  */
2352 
2353 /** ADC - Register Layout Typedef */
2354 typedef struct {
2355   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
2356   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
2357        uint8_t RESERVED_0[8];
2358   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
2359   __IO uint32_t STAT;                              /**< Status Register, offset: 0x14 */
2360   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
2361   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
2362   __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x20 */
2363   __IO uint32_t PAUSE;                             /**< Pause Register, offset: 0x24 */
2364        uint8_t RESERVED_1[12];
2365   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
2366   __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
2367        uint8_t RESERVED_2[4];
2368   __IO uint32_t OFSTRIM16;                         /**< Offset Trim 16 bit Register, offset: 0x40 */
2369   __IO uint32_t OFSTRIM12;                         /**< Offset Trim 12 bit Register, offset: 0x44 */
2370        uint8_t RESERVED_3[88];
2371   __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
2372        uint8_t RESERVED_4[32];
2373   __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
2374        uint8_t RESERVED_5[8];
2375   __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
2376   __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
2377   struct {                                         /* offset: 0x100, array step: 0x8 */
2378     __IO uint32_t CMDL;                              /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
2379     __IO uint32_t CMDH;                              /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */
2380   } CMD[15];
2381        uint8_t RESERVED_6[136];
2382   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
2383        uint8_t RESERVED_7[240];
2384   __I  uint32_t RESFIFO[2];                        /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
2385        uint8_t RESERVED_8[248];
2386   __IO uint32_t CAL_GAR[33];                       /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
2387        uint8_t RESERVED_9[124];
2388   __IO uint32_t CAL_GBR[33];                       /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
2389        uint8_t RESERVED_10[2676];
2390   __IO uint32_t CFG2;                              /**< Configuration 2 Register, offset: 0xFF8 */
2391 } ADC_Type;
2392 
2393 /* ----------------------------------------------------------------------------
2394    -- ADC Register Masks
2395    ---------------------------------------------------------------------------- */
2396 
2397 /*!
2398  * @addtogroup ADC_Register_Masks ADC Register Masks
2399  * @{
2400  */
2401 
2402 /*! @name VERID - Version ID Register */
2403 /*! @{ */
2404 
2405 #define ADC_VERID_RES_MASK                       (0x1U)
2406 #define ADC_VERID_RES_SHIFT                      (0U)
2407 /*! RES - Resolution
2408  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
2409  *  0b1..Up to 16-bit differential/16-bit single ended resolution supported.
2410  */
2411 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
2412 
2413 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
2414 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
2415 /*! DIFFEN - Differential Supported
2416  *  0b0..Differential operation not supported.
2417  *  0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
2418  */
2419 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
2420 
2421 #define ADC_VERID_MVI_MASK                       (0x8U)
2422 #define ADC_VERID_MVI_SHIFT                      (3U)
2423 /*! MVI - Multi Vref Implemented
2424  *  0b0..Single voltage reference high (VREFH) input supported.
2425  *  0b1..Multiple voltage reference high (VREFH) inputs supported.
2426  */
2427 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
2428 
2429 #define ADC_VERID_CSW_MASK                       (0x70U)
2430 #define ADC_VERID_CSW_SHIFT                      (4U)
2431 /*! CSW - Channel Scale Width
2432  *  0b000..Channel scaling not supported. CSCALE control field not implemented.
2433  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
2434  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
2435  */
2436 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
2437 
2438 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
2439 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
2440 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
2441  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
2442  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
2443  */
2444 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
2445 
2446 #define ADC_VERID_IADCKI_MASK                    (0x200U)
2447 #define ADC_VERID_IADCKI_SHIFT                   (9U)
2448 /*! IADCKI - Internal ADC Clock Implemented
2449  *  0b0..Internal clock source not implemented.
2450  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
2451  */
2452 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
2453 
2454 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
2455 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
2456 /*! CALOFSI - Calibration Function Implemented
2457  *  0b0..Calibration Not Implemented.
2458  *  0b1..Calibration Implemented.
2459  */
2460 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
2461 
2462 #define ADC_VERID_NUM_SEC_MASK                   (0x800U)
2463 #define ADC_VERID_NUM_SEC_SHIFT                  (11U)
2464 /*! NUM_SEC - Number of Single Ended Outputs Supported
2465  *  0b0..This design supports one single ended conversion at a time.
2466  *  0b1..This design supports two simultaneous single ended conversions.
2467  */
2468 #define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
2469 
2470 #define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
2471 #define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
2472 /*! NUM_FIFO - Number of FIFOs
2473  *  0b000..N/A
2474  *  0b001..This design supports one result FIFO.
2475  *  0b010..This design supports two result FIFOs.
2476  *  0b011..This design supports three result FIFOs.
2477  *  0b100..This design supports four result FIFOs.
2478  */
2479 #define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
2480 
2481 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
2482 #define ADC_VERID_MINOR_SHIFT                    (16U)
2483 /*! MINOR - Minor Version Number */
2484 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
2485 
2486 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
2487 #define ADC_VERID_MAJOR_SHIFT                    (24U)
2488 /*! MAJOR - Major Version Number */
2489 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
2490 /*! @} */
2491 
2492 /*! @name PARAM - Parameter Register */
2493 /*! @{ */
2494 
2495 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
2496 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
2497 /*! TRIG_NUM - Trigger Number */
2498 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
2499 
2500 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
2501 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
2502 /*! FIFOSIZE - Result FIFO Depth
2503  *  0b00000001..Result FIFO depth = 2 dataword.
2504  *  0b00000100..Result FIFO depth = 4 datawords.
2505  *  0b00001000..Result FIFO depth = 8 datawords.
2506  *  0b00010000..Result FIFO depth = 16 datawords.
2507  *  0b00100000..Result FIFO depth = 32 datawords.
2508  *  0b01000000..Result FIFO depth = 64 datawords.
2509  */
2510 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
2511 
2512 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
2513 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
2514 /*! CV_NUM - Compare Value Number */
2515 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
2516 
2517 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
2518 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
2519 /*! CMD_NUM - Command Buffer Number */
2520 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
2521 /*! @} */
2522 
2523 /*! @name CTRL - Control Register */
2524 /*! @{ */
2525 
2526 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
2527 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
2528 /*! ADCEN - ADC Enable
2529  *  0b0..ADC is disabled.
2530  *  0b1..ADC is enabled.
2531  */
2532 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
2533 
2534 #define ADC_CTRL_RST_MASK                        (0x2U)
2535 #define ADC_CTRL_RST_SHIFT                       (1U)
2536 /*! RST - Software Reset
2537  *  0b0..ADC logic is not reset.
2538  *  0b1..ADC logic is reset.
2539  */
2540 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
2541 
2542 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
2543 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
2544 /*! DOZEN - Doze Enable
2545  *  0b0..ADC is enabled in low power mode.
2546  *  0b1..ADC is disabled in low power mode.
2547  */
2548 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
2549 
2550 #define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
2551 #define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
2552 /*! CAL_REQ - Auto-Calibration Request
2553  *  0b0..No request for hardware calibration has been made.
2554  *  0b1..A request for hardware calibration has been made
2555  */
2556 #define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
2557 
2558 #define ADC_CTRL_CALOFS_MASK                     (0x10U)
2559 #define ADC_CTRL_CALOFS_SHIFT                    (4U)
2560 /*! CALOFS - Offset Calibration Request
2561  *  0b0..Calibration function disabled
2562  *  0b1..Request for offset calibration function
2563  */
2564 #define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
2565 
2566 #define ADC_CTRL_CALOFSMODE_MASK                 (0x20U)
2567 #define ADC_CTRL_CALOFSMODE_SHIFT                (5U)
2568 /*! CALOFSMODE - Configure Mode for Offset Calibration Function
2569  *  0b0..Configure offset calibration for 12-bit mode.
2570  *  0b1..Configure offset calibration for 16-bit mode.
2571  */
2572 #define ADC_CTRL_CALOFSMODE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFSMODE_SHIFT)) & ADC_CTRL_CALOFSMODE_MASK)
2573 
2574 #define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
2575 #define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
2576 /*! RSTFIFO0 - Reset FIFO 0
2577  *  0b0..No effect.
2578  *  0b1..FIFO 0 is reset.
2579  */
2580 #define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
2581 
2582 #define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
2583 #define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
2584 /*! RSTFIFO1 - Reset FIFO 1
2585  *  0b0..No effect.
2586  *  0b1..FIFO 1 is reset.
2587  */
2588 #define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
2589 
2590 #define ADC_CTRL_CAL_AVGS_MASK                   (0xF0000U)
2591 #define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
2592 /*! CAL_AVGS - Auto-Calibration Averages
2593  *  0b0000..Single conversion.
2594  *  0b0001..2 conversions averaged.
2595  *  0b0010..4 conversions averaged.
2596  *  0b0011..8 conversions averaged.
2597  *  0b0100..16 conversions averaged.
2598  *  0b0101..32 conversions averaged.
2599  *  0b0110..64 conversions averaged.
2600  *  0b0111..128 conversions averaged.
2601  *  0b1000..256 conversions averaged.
2602  *  0b1001..512 conversions averaged.
2603  *  0b1010..1024 conversions averaged.
2604  */
2605 #define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
2606 /*! @} */
2607 
2608 /*! @name STAT - Status Register */
2609 /*! @{ */
2610 
2611 #define ADC_STAT_RDY0_MASK                       (0x1U)
2612 #define ADC_STAT_RDY0_SHIFT                      (0U)
2613 /*! RDY0 - Result FIFO 0 Ready Flag
2614  *  0b0..Result FIFO 0 data level not above watermark level.
2615  *  0b1..Result FIFO 0 holding data above watermark level.
2616  */
2617 #define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
2618 
2619 #define ADC_STAT_FOF0_MASK                       (0x2U)
2620 #define ADC_STAT_FOF0_SHIFT                      (1U)
2621 /*! FOF0 - Result FIFO 0 Overflow Flag
2622  *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
2623  *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
2624  */
2625 #define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
2626 
2627 #define ADC_STAT_RDY1_MASK                       (0x4U)
2628 #define ADC_STAT_RDY1_SHIFT                      (2U)
2629 /*! RDY1 - Result FIFO1 Ready Flag
2630  *  0b0..Result FIFO1 data level not above watermark level.
2631  *  0b1..Result FIFO1 holding data above watermark level.
2632  */
2633 #define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
2634 
2635 #define ADC_STAT_FOF1_MASK                       (0x8U)
2636 #define ADC_STAT_FOF1_SHIFT                      (3U)
2637 /*! FOF1 - Result FIFO1 Overflow Flag
2638  *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
2639  *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
2640  */
2641 #define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
2642 
2643 #define ADC_STAT_TEXC_INT_MASK                   (0x100U)
2644 #define ADC_STAT_TEXC_INT_SHIFT                  (8U)
2645 /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
2646  *  0b0..No trigger exceptions have occurred.
2647  *  0b1..A trigger exception has occurred and is pending acknowledgement.
2648  */
2649 #define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
2650 
2651 #define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
2652 #define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
2653 /*! TCOMP_INT - Interrupt Flag For Trigger Completion
2654  *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
2655  *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
2656  */
2657 #define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
2658 
2659 #define ADC_STAT_CAL_RDY_MASK                    (0x400U)
2660 #define ADC_STAT_CAL_RDY_SHIFT                   (10U)
2661 /*! CAL_RDY - Calibration Ready
2662  *  0b0..Calibration is incomplete or hasn't been ran.
2663  *  0b1..The ADC is calibrated.
2664  */
2665 #define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
2666 
2667 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
2668 #define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
2669 /*! ADC_ACTIVE - ADC Active
2670  *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
2671  *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
2672  */
2673 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
2674 
2675 #define ADC_STAT_TRGACT_MASK                     (0x70000U)
2676 #define ADC_STAT_TRGACT_SHIFT                    (16U)
2677 /*! TRGACT - Trigger Active
2678  *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
2679  *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
2680  *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
2681  *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
2682  */
2683 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
2684 
2685 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
2686 #define ADC_STAT_CMDACT_SHIFT                    (24U)
2687 /*! CMDACT - Command Active
2688  *  0b0000..No command is currently in progress.
2689  *  0b0001..Command 1 currently being executed.
2690  *  0b0010..Command 2 currently being executed.
2691  *  0b0011-0b1111..Associated command number is currently being executed.
2692  */
2693 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
2694 /*! @} */
2695 
2696 /*! @name IE - Interrupt Enable Register */
2697 /*! @{ */
2698 
2699 #define ADC_IE_FWMIE0_MASK                       (0x1U)
2700 #define ADC_IE_FWMIE0_SHIFT                      (0U)
2701 /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
2702  *  0b0..FIFO 0 watermark interrupts are not enabled.
2703  *  0b1..FIFO 0 watermark interrupts are enabled.
2704  */
2705 #define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
2706 
2707 #define ADC_IE_FOFIE0_MASK                       (0x2U)
2708 #define ADC_IE_FOFIE0_SHIFT                      (1U)
2709 /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
2710  *  0b0..FIFO 0 overflow interrupts are not enabled.
2711  *  0b1..FIFO 0 overflow interrupts are enabled.
2712  */
2713 #define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
2714 
2715 #define ADC_IE_FWMIE1_MASK                       (0x4U)
2716 #define ADC_IE_FWMIE1_SHIFT                      (2U)
2717 /*! FWMIE1 - FIFO1 Watermark Interrupt Enable
2718  *  0b0..FIFO1 watermark interrupts are not enabled.
2719  *  0b1..FIFO1 watermark interrupts are enabled.
2720  */
2721 #define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
2722 
2723 #define ADC_IE_FOFIE1_MASK                       (0x8U)
2724 #define ADC_IE_FOFIE1_SHIFT                      (3U)
2725 /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
2726  *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
2727  *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
2728  */
2729 #define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
2730 
2731 #define ADC_IE_TEXC_IE_MASK                      (0x100U)
2732 #define ADC_IE_TEXC_IE_SHIFT                     (8U)
2733 /*! TEXC_IE - Trigger Exception Interrupt Enable
2734  *  0b0..Trigger exception interrupts are disabled.
2735  *  0b1..Trigger exception interrupts are enabled.
2736  */
2737 #define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
2738 
2739 #define ADC_IE_TCOMP_IE_MASK                     (0xFF0000U)
2740 #define ADC_IE_TCOMP_IE_SHIFT                    (16U)
2741 /*! TCOMP_IE - Trigger Completion Interrupt Enable
2742  *  0b00000000..Trigger completion interrupts are disabled.
2743  *  0b00000001..Trigger completion interrupts are enabled for trigger source 0 only.
2744  *  0b00000010..Trigger completion interrupts are enabled for trigger source 1 only.
2745  *  0b00000011-0b11111110..Associated trigger completion interrupts are enabled.
2746  *  0b11111111..Trigger completion interrupts are enabled for every trigger source.
2747  */
2748 #define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
2749 /*! @} */
2750 
2751 /*! @name DE - DMA Enable Register */
2752 /*! @{ */
2753 
2754 #define ADC_DE_FWMDE0_MASK                       (0x1U)
2755 #define ADC_DE_FWMDE0_SHIFT                      (0U)
2756 /*! FWMDE0 - FIFO 0 Watermark DMA Enable
2757  *  0b0..DMA request disabled.
2758  *  0b1..DMA request enabled.
2759  */
2760 #define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
2761 
2762 #define ADC_DE_FWMDE1_MASK                       (0x2U)
2763 #define ADC_DE_FWMDE1_SHIFT                      (1U)
2764 /*! FWMDE1 - FIFO1 Watermark DMA Enable
2765  *  0b0..DMA request disabled.
2766  *  0b1..DMA request enabled.
2767  */
2768 #define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
2769 /*! @} */
2770 
2771 /*! @name CFG - Configuration Register */
2772 /*! @{ */
2773 
2774 #define ADC_CFG_TPRICTRL_MASK                    (0x3U)
2775 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
2776 /*! TPRICTRL - ADC Trigger Priority Control
2777  *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
2778  *        and the new command specified by the trigger is started.
2779  *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
2780  *        completing the current conversion. If averaging is enabled, the averaging loop will be completed.
2781  *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
2782  *  0b10..If a higher priority trigger is received during command processing, the current command will be
2783  *        completed (averaging, looping, compare) before servicing the higher priority trigger.
2784  *  0b11..RESERVED
2785  */
2786 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
2787 
2788 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
2789 #define ADC_CFG_REFSEL_SHIFT                     (6U)
2790 /*! REFSEL - Voltage Reference Selection
2791  *  0b00..(Default) Option 1 setting.
2792  *  0b01..Option 2 setting.
2793  *  0b10..Option 3 setting.
2794  *  0b11..Reserved
2795  */
2796 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
2797 
2798 #define ADC_CFG_TRES_MASK                        (0x100U)
2799 #define ADC_CFG_TRES_SHIFT                       (8U)
2800 /*! TRES - Trigger Resume Enable
2801  *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
2802  *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
2803  */
2804 #define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
2805 
2806 #define ADC_CFG_TCMDRES_MASK                     (0x200U)
2807 #define ADC_CFG_TCMDRES_SHIFT                    (9U)
2808 /*! TCMDRES - Trigger Command Resume
2809  *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
2810  *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
2811  */
2812 #define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
2813 
2814 #define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
2815 #define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
2816 /*! HPT_EXDI - High Priority Trigger Exception Disable
2817  *  0b0..High priority trigger exceptions are enabled.
2818  *  0b1..High priority trigger exceptions are disabled.
2819  */
2820 #define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
2821 
2822 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
2823 #define ADC_CFG_PUDLY_SHIFT                      (16U)
2824 /*! PUDLY - Power Up Delay */
2825 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
2826 
2827 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
2828 #define ADC_CFG_PWREN_SHIFT                      (28U)
2829 /*! PWREN - ADC Analog Pre-Enable
2830  *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
2831  *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
2832  *       of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately
2833  *       once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has
2834  *       passed. After this initial delay expires the analog remains pre-enabled and no additional delays are
2835  *       executed.
2836  */
2837 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
2838 /*! @} */
2839 
2840 /*! @name PAUSE - Pause Register */
2841 /*! @{ */
2842 
2843 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
2844 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
2845 /*! PAUSEDLY - Pause Delay */
2846 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
2847 
2848 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
2849 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
2850 /*! PAUSEEN - PAUSE Option Enable
2851  *  0b0..Pause operation disabled
2852  *  0b1..Pause operation enabled
2853  */
2854 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
2855 /*! @} */
2856 
2857 /*! @name SWTRIG - Software Trigger Register */
2858 /*! @{ */
2859 
2860 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
2861 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
2862 /*! SWT0 - Software Trigger 0 Event
2863  *  0b0..No trigger 0 event generated.
2864  *  0b1..Trigger 0 event generated.
2865  */
2866 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
2867 
2868 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
2869 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
2870 /*! SWT1 - Software Trigger 1 Event
2871  *  0b0..No trigger 1 event generated.
2872  *  0b1..Trigger 1 event generated.
2873  */
2874 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
2875 
2876 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
2877 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
2878 /*! SWT2 - Software Trigger 2 Event
2879  *  0b0..No trigger 2 event generated.
2880  *  0b1..Trigger 2 event generated.
2881  */
2882 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
2883 
2884 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
2885 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
2886 /*! SWT3 - Software Trigger 3 Event
2887  *  0b0..No trigger 3 event generated.
2888  *  0b1..Trigger 3 event generated.
2889  */
2890 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
2891 
2892 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
2893 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
2894 /*! SWT4 - Software trigger 4 event
2895  *  0b0..No trigger 4 event generated.
2896  *  0b1..Trigger 4 event generated.
2897  */
2898 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
2899 
2900 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
2901 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
2902 /*! SWT5 - Software trigger 5 event
2903  *  0b0..No trigger 5 event generated.
2904  *  0b1..Trigger 5 event generated.
2905  */
2906 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
2907 
2908 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
2909 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
2910 /*! SWT6 - Software trigger 6 event
2911  *  0b0..No trigger 6 event generated.
2912  *  0b1..Trigger 6 event generated.
2913  */
2914 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
2915 
2916 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
2917 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
2918 /*! SWT7 - Software trigger 7 event
2919  *  0b0..No trigger 7 event generated.
2920  *  0b1..Trigger 7 event generated.
2921  */
2922 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
2923 /*! @} */
2924 
2925 /*! @name TSTAT - Trigger Status Register */
2926 /*! @{ */
2927 
2928 #define ADC_TSTAT_TEXC_NUM_MASK                  (0xFFU)
2929 #define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
2930 /*! TEXC_NUM - Trigger Exception Number
2931  *  0b00000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
2932  *  0b00000001..Trigger 0 has been interrupted by a high priority exception.
2933  *  0b00000010..Trigger 1 has been interrupted by a high priority exception.
2934  *  0b00000011-0b11111110..Associated trigger sequence has interrupted by a high priority exception.
2935  *  0b11111111..Every trigger sequence has been interrupted by a high priority exception.
2936  */
2937 #define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
2938 
2939 #define ADC_TSTAT_TCOMP_FLAG_MASK                (0xFF0000U)
2940 #define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
2941 /*! TCOMP_FLAG - Trigger Completion Flag
2942  *  0b00000000..No triggers have been completed. Trigger completion interrupts are disabled.
2943  *  0b00000001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
2944  *  0b00000010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
2945  *  0b00000011-0b11111110..Associated trigger sequence has completed and has enabled completion interrupts.
2946  *  0b11111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
2947  */
2948 #define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
2949 /*! @} */
2950 
2951 /*! @name OFSTRIM16 - Offset Trim 16 bit Register */
2952 /*! @{ */
2953 
2954 #define ADC_OFSTRIM16_OFSTRIM_A_MASK             (0x3FFU)
2955 #define ADC_OFSTRIM16_OFSTRIM_A_SHIFT            (0U)
2956 /*! OFSTRIM_A - Trim for Offset in A-side Converter for 16-bit Conversions */
2957 #define ADC_OFSTRIM16_OFSTRIM_A(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM16_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM16_OFSTRIM_A_MASK)
2958 
2959 #define ADC_OFSTRIM16_OFSTRIM_B_MASK             (0x3FF0000U)
2960 #define ADC_OFSTRIM16_OFSTRIM_B_SHIFT            (16U)
2961 /*! OFSTRIM_B - Trim for Offset in B-side Converter for 16-bit Conversions */
2962 #define ADC_OFSTRIM16_OFSTRIM_B(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM16_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM16_OFSTRIM_B_MASK)
2963 /*! @} */
2964 
2965 /*! @name OFSTRIM12 - Offset Trim 12 bit Register */
2966 /*! @{ */
2967 
2968 #define ADC_OFSTRIM12_OFSTRIM_A_MASK             (0x3FFU)
2969 #define ADC_OFSTRIM12_OFSTRIM_A_SHIFT            (0U)
2970 /*! OFSTRIM_A - Trim for Offset in A-side Converter for 12-bit Conversions */
2971 #define ADC_OFSTRIM12_OFSTRIM_A(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM12_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM12_OFSTRIM_A_MASK)
2972 
2973 #define ADC_OFSTRIM12_OFSTRIM_B_MASK             (0x3FF0000U)
2974 #define ADC_OFSTRIM12_OFSTRIM_B_SHIFT            (16U)
2975 /*! OFSTRIM_B - Trim for Offset in B-side Converter for 12-bit Conversions */
2976 #define ADC_OFSTRIM12_OFSTRIM_B(x)               (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM12_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM12_OFSTRIM_B_MASK)
2977 /*! @} */
2978 
2979 /*! @name TCTRL - Trigger Control Register */
2980 /*! @{ */
2981 
2982 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
2983 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
2984 /*! HTEN - Trigger Enable
2985  *  0b0..Hardware trigger source disabled
2986  *  0b1..Hardware trigger source enabled
2987  */
2988 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
2989 
2990 #define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
2991 #define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
2992 /*! FIFO_SEL_A - SAR Result Destination for Channel A
2993  *  0b0..Result written to FIFO 0
2994  *  0b1..Result written to FIFO 1
2995  */
2996 #define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
2997 
2998 #define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
2999 #define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
3000 /*! FIFO_SEL_B - SAR Result Destination for Channel B
3001  *  0b0..Result written to FIFO 0
3002  *  0b1..Result written to FIFO 1
3003  */
3004 #define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
3005 
3006 #define ADC_TCTRL_TPRI_MASK                      (0x700U)
3007 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
3008 /*! TPRI - Trigger Priority Setting
3009  *  0b000..Set to highest priority, Level 1
3010  *  0b001-0b110..Set to corresponding priority level
3011  *  0b111..Set to lowest priority, Level 8
3012  */
3013 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
3014 
3015 #define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
3016 #define ADC_TCTRL_RSYNC_SHIFT                    (15U)
3017 /*! RSYNC - Trigger Resync */
3018 #define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
3019 
3020 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
3021 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
3022 /*! TDLY - Trigger Delay Select */
3023 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
3024 
3025 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
3026 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
3027 /*! TCMD - Trigger Command Select
3028  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3029  *  0b0001..CMD1 is executed
3030  *  0b0010-0b1110..Corresponding CMD is executed
3031  *  0b1111..CMD15 is executed
3032  */
3033 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
3034 /*! @} */
3035 
3036 /* The count of ADC_TCTRL */
3037 #define ADC_TCTRL_COUNT                          (8U)
3038 
3039 /*! @name FCTRL - FIFO Control Register */
3040 /*! @{ */
3041 
3042 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
3043 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
3044 /*! FCOUNT - Result FIFO Counter */
3045 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
3046 
3047 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
3048 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
3049 /*! FWMARK - Watermark Level Selection */
3050 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
3051 /*! @} */
3052 
3053 /* The count of ADC_FCTRL */
3054 #define ADC_FCTRL_COUNT                          (2U)
3055 
3056 /*! @name GCC - Gain Calibration Control */
3057 /*! @{ */
3058 
3059 #define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
3060 #define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
3061 /*! GAIN_CAL - Gain Calibration Value */
3062 #define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
3063 
3064 #define ADC_GCC_RDY_MASK                         (0x1000000U)
3065 #define ADC_GCC_RDY_SHIFT                        (24U)
3066 /*! RDY - Hardware Calculated GAIN_CAL Value Ready
3067  *  0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set.
3068  *  0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
3069  */
3070 #define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
3071 /*! @} */
3072 
3073 /* The count of ADC_GCC */
3074 #define ADC_GCC_COUNT                            (2U)
3075 
3076 /*! @name GCR - Gain Calculation Result */
3077 /*! @{ */
3078 
3079 #define ADC_GCR_GCALR_MASK                       (0x1FFFFU)
3080 #define ADC_GCR_GCALR_SHIFT                      (0U)
3081 /*! GCALR - Gain Calculation Result */
3082 #define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
3083 
3084 #define ADC_GCR_RDY_MASK                         (0x1000000U)
3085 #define ADC_GCR_RDY_SHIFT                        (24U)
3086 /*! RDY - Gain Calculation Ready
3087  *  0b0..The GCALR value is invalid.
3088  *  0b1..The GCALR value is valid.
3089  */
3090 #define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
3091 /*! @} */
3092 
3093 /* The count of ADC_GCR */
3094 #define ADC_GCR_COUNT                            (2U)
3095 
3096 /*! @name CMDL - Command Low Buffer Register */
3097 /*! @{ */
3098 
3099 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
3100 #define ADC_CMDL_ADCH_SHIFT                      (0U)
3101 /*! ADCH - Input Channel Select
3102  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
3103  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
3104  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
3105  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
3106  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
3107  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
3108  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
3109  */
3110 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
3111 
3112 #define ADC_CMDL_CTYPE_MASK                      (0x60U)
3113 #define ADC_CMDL_CTYPE_SHIFT                     (5U)
3114 /*! CTYPE - Conversion Type
3115  *  0b00..Single-Ended Mode. Only A side channel is converted.
3116  *  0b01..Single-Ended Mode. Only B side channel is converted.
3117  *  0b10..Differential Mode. A-B.
3118  *  0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
3119  */
3120 #define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
3121 
3122 #define ADC_CMDL_MODE_MASK                       (0x80U)
3123 #define ADC_CMDL_MODE_SHIFT                      (7U)
3124 /*! MODE - Select Resolution of Conversions
3125  *  0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
3126  *  0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
3127  */
3128 #define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
3129 
3130 #define ADC_CMDL_CSCALE_MASK                     (0x2000U)
3131 #define ADC_CMDL_CSCALE_SHIFT                    (13U)
3132 /*! CSCALE - Channel Scale
3133  *  0b0..Scale selected analog channel (Factor of 1/2)
3134  *  0b1..(Default) Full scale (Factor of 1)
3135  */
3136 #define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
3137 
3138 #define ADC_CMDL_ALTB_ADCH_MASK                  (0x1F0000U)
3139 #define ADC_CMDL_ALTB_ADCH_SHIFT                 (16U)
3140 /*! ALTB_ADCH - Alternate Channel B Input Channel Select
3141  *  0b00000..Select CH0B
3142  *  0b00001..Select CH1B
3143  *  0b00010..Select CH2B
3144  *  0b00011..Select CH3B
3145  *  0b00100-0b11101..Select corresponding channel CHnB
3146  *  0b11110..Select CH30B
3147  *  0b11111..Select CH31B
3148  */
3149 #define ADC_CMDL_ALTB_ADCH(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK)
3150 
3151 #define ADC_CMDL_ALTBEN_MASK                     (0x200000U)
3152 #define ADC_CMDL_ALTBEN_SHIFT                    (21U)
3153 /*! ALTBEN - Alternate Channel B Select Enable
3154  *  0b0..ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH settings.
3155  *  0b1..ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs selected by ALTB_ADCH setting.
3156  */
3157 #define ADC_CMDL_ALTBEN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK)
3158 
3159 #define ADC_CMDL_ALTB_CSCALE_MASK                (0x800000U)
3160 #define ADC_CMDL_ALTB_CSCALE_SHIFT               (23U)
3161 /*! ALTB_CSCALE - Alt Channel B Scale
3162  *  0b0..Scale selected analog channel (Factor of 1/2)
3163  *  0b1..(Default) Full scale (Factor of 1)
3164  */
3165 #define ADC_CMDL_ALTB_CSCALE(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_CSCALE_SHIFT)) & ADC_CMDL_ALTB_CSCALE_MASK)
3166 /*! @} */
3167 
3168 /* The count of ADC_CMDL */
3169 #define ADC_CMDL_COUNT                           (15U)
3170 
3171 /*! @name CMDH - Command High Buffer Register */
3172 /*! @{ */
3173 
3174 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
3175 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
3176 /*! CMPEN - Compare Function Enable
3177  *  0b00..Compare disabled.
3178  *  0b01..Reserved
3179  *  0b10..Compare enabled. Store on true.
3180  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
3181  */
3182 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
3183 
3184 #define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
3185 #define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
3186 /*! WAIT_TRIG - Wait for Trigger Assertion before Execution.
3187  *  0b0..This command will be automatically executed.
3188  *  0b1..The active trigger must be asserted again before executing this command.
3189  */
3190 #define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
3191 
3192 #define ADC_CMDH_LWI_MASK                        (0x80U)
3193 #define ADC_CMDH_LWI_SHIFT                       (7U)
3194 /*! LWI - Loop with Increment
3195  *  0b0..Auto channel increment disabled
3196  *  0b1..Auto channel increment enabled
3197  */
3198 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
3199 
3200 #define ADC_CMDH_STS_MASK                        (0x700U)
3201 #define ADC_CMDH_STS_SHIFT                       (8U)
3202 /*! STS - Sample Time Select
3203  *  0b000..Minimum sample time of 3.5 ADCK cycles.
3204  *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
3205  *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
3206  *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
3207  *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
3208  *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
3209  *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
3210  *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
3211  */
3212 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
3213 
3214 #define ADC_CMDH_AVGS_MASK                       (0xF000U)
3215 #define ADC_CMDH_AVGS_SHIFT                      (12U)
3216 /*! AVGS - Hardware Average Select
3217  *  0b0000..Single conversion.
3218  *  0b0001..2 conversions averaged.
3219  *  0b0010..4 conversions averaged.
3220  *  0b0011..8 conversions averaged.
3221  *  0b0100..16 conversions averaged.
3222  *  0b0101..32 conversions averaged.
3223  *  0b0110..64 conversions averaged.
3224  *  0b0111..128 conversions averaged.
3225  *  0b1000..256 conversions averaged.
3226  *  0b1001..512 conversions averaged.
3227  *  0b1010..1024 conversions averaged.
3228  */
3229 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
3230 
3231 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
3232 #define ADC_CMDH_LOOP_SHIFT                      (16U)
3233 /*! LOOP - Loop Count Select
3234  *  0b0000..Looping not enabled. Command executes 1 time.
3235  *  0b0001..Loop 1 time. Command executes 2 times.
3236  *  0b0010..Loop 2 times. Command executes 3 times.
3237  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
3238  *  0b1111..Loop 15 times. Command executes 16 times.
3239  */
3240 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
3241 
3242 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
3243 #define ADC_CMDH_NEXT_SHIFT                      (24U)
3244 /*! NEXT - Next Command Select
3245  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
3246  *          trigger pending, begin command associated with lower priority trigger.
3247  *  0b0001..Select CMD1 command buffer register as next command.
3248  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
3249  *  0b1111..Select CMD15 command buffer register as next command.
3250  */
3251 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
3252 /*! @} */
3253 
3254 /* The count of ADC_CMDH */
3255 #define ADC_CMDH_COUNT                           (15U)
3256 
3257 /*! @name CV - Compare Value Register */
3258 /*! @{ */
3259 
3260 #define ADC_CV_CVL_MASK                          (0xFFFFU)
3261 #define ADC_CV_CVL_SHIFT                         (0U)
3262 /*! CVL - Compare Value Low */
3263 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
3264 
3265 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
3266 #define ADC_CV_CVH_SHIFT                         (16U)
3267 /*! CVH - Compare Value High */
3268 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
3269 /*! @} */
3270 
3271 /* The count of ADC_CV */
3272 #define ADC_CV_COUNT                             (4U)
3273 
3274 /*! @name RESFIFO - Data Result FIFO Register */
3275 /*! @{ */
3276 
3277 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
3278 #define ADC_RESFIFO_D_SHIFT                      (0U)
3279 /*! D - Data Result */
3280 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
3281 
3282 #define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
3283 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
3284 /*! TSRC - Trigger Source
3285  *  0b000..Trigger source 0 initiated this conversion.
3286  *  0b001..Trigger source 1 initiated this conversion.
3287  *  0b010-0b110..Corresponding trigger source initiated this conversion.
3288  *  0b111..Trigger source 7 initiated this conversion.
3289  */
3290 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
3291 
3292 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
3293 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
3294 /*! LOOPCNT - Loop Count Value
3295  *  0b0000..Result is from initial conversion in command.
3296  *  0b0001..Result is from second conversion in command.
3297  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
3298  *  0b1111..Result is from 16th conversion in command.
3299  */
3300 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
3301 
3302 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
3303 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
3304 /*! CMDSRC - Command Buffer Source
3305  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
3306  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
3307  *  0b0001..CMD1 buffer used as control settings for this conversion.
3308  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
3309  *  0b1111..CMD15 buffer used as control settings for this conversion.
3310  */
3311 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
3312 
3313 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
3314 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
3315 /*! VALID - FIFO Entry is Valid
3316  *  0b0..FIFO is empty. Discard any read from RESFIFO.
3317  *  0b1..FIFO record read from RESFIFO is valid.
3318  */
3319 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
3320 /*! @} */
3321 
3322 /* The count of ADC_RESFIFO */
3323 #define ADC_RESFIFO_COUNT                        (2U)
3324 
3325 /*! @name CAL_GAR - Calibration General A-Side Registers */
3326 /*! @{ */
3327 
3328 #define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)
3329 #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
3330 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
3331 #define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
3332 /*! @} */
3333 
3334 /* The count of ADC_CAL_GAR */
3335 #define ADC_CAL_GAR_COUNT                        (33U)
3336 
3337 /*! @name CAL_GBR - Calibration General B-Side Registers */
3338 /*! @{ */
3339 
3340 #define ADC_CAL_GBR_CAL_GBR_VAL_MASK             (0xFFFFU)
3341 #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT            (0U)
3342 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
3343 #define ADC_CAL_GBR_CAL_GBR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
3344 /*! @} */
3345 
3346 /* The count of ADC_CAL_GBR */
3347 #define ADC_CAL_GBR_COUNT                        (33U)
3348 
3349 /*! @name CFG2 - Configuration 2 Register */
3350 /*! @{ */
3351 
3352 #define ADC_CFG2_JLEFT_MASK                      (0x100U)
3353 #define ADC_CFG2_JLEFT_SHIFT                     (8U)
3354 /*! JLEFT - Justified Left Enable register
3355  *  0b0..For 12-bit single-ended conversions, RESFIFO data format is in standard format with data presented in bits RESFIFOa[D][14:3].
3356  *  0b1..For 12-bit single-ended conversions, RESFIFO data format is left-justified.
3357  */
3358 #define ADC_CFG2_JLEFT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK)
3359 /*! @} */
3360 
3361 
3362 /*!
3363  * @}
3364  */ /* end of group ADC_Register_Masks */
3365 
3366 
3367 /* ADC - Peripheral instance base addresses */
3368 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
3369   /** Peripheral ADC1 base address */
3370   #define ADC1_BASE                                (0x52600000u)
3371   /** Peripheral ADC1 base address */
3372   #define ADC1_BASE_NS                             (0x42600000u)
3373   /** Peripheral ADC1 base pointer */
3374   #define ADC1                                     ((ADC_Type *)ADC1_BASE)
3375   /** Peripheral ADC1 base pointer */
3376   #define ADC1_NS                                  ((ADC_Type *)ADC1_BASE_NS)
3377   /** Array initializer of ADC peripheral base addresses */
3378   #define ADC_BASE_ADDRS                           { 0u, ADC1_BASE }
3379   /** Array initializer of ADC peripheral base pointers */
3380   #define ADC_BASE_PTRS                            { (ADC_Type *)0u, ADC1 }
3381   /** Array initializer of ADC peripheral base addresses */
3382   #define ADC_BASE_ADDRS_NS                        { 0u, ADC1_BASE_NS }
3383   /** Array initializer of ADC peripheral base pointers */
3384   #define ADC_BASE_PTRS_NS                         { (ADC_Type *)0u, ADC1_NS }
3385 #else
3386   /** Peripheral ADC1 base address */
3387   #define ADC1_BASE                                (0x42600000u)
3388   /** Peripheral ADC1 base pointer */
3389   #define ADC1                                     ((ADC_Type *)ADC1_BASE)
3390   /** Array initializer of ADC peripheral base addresses */
3391   #define ADC_BASE_ADDRS                           { 0u, ADC1_BASE }
3392   /** Array initializer of ADC peripheral base pointers */
3393   #define ADC_BASE_PTRS                            { (ADC_Type *)0u, ADC1 }
3394 #endif
3395 /** Interrupt vectors for the ADC peripheral type */
3396 #define ADC_IRQS                                 { NotAvail_IRQn, ADC1_IRQn }
3397 
3398 /*!
3399  * @}
3400  */ /* end of group ADC_Peripheral_Access_Layer */
3401 
3402 
3403 /* ----------------------------------------------------------------------------
3404    -- ANADIG Peripheral Access Layer
3405    ---------------------------------------------------------------------------- */
3406 
3407 /*!
3408  * @addtogroup ANADIG_Peripheral_Access_Layer ANADIG Peripheral Access Layer
3409  * @{
3410  */
3411 
3412 /** ANADIG - Register Layout Typedef */
3413 typedef struct {
3414        uint8_t RESERVED_0[19456];
3415   __IO uint32_t SLOT_CTRL[35];                     /**< Slot Control Register, array offset: 0x4C00, array step: 0x4 */
3416 } ANADIG_Type;
3417 
3418 /* ----------------------------------------------------------------------------
3419    -- ANADIG Register Masks
3420    ---------------------------------------------------------------------------- */
3421 
3422 /*!
3423  * @addtogroup ANADIG_Register_Masks ANADIG Register Masks
3424  * @{
3425  */
3426 
3427 /*! @name SLOT_CTRL - Slot Control Register */
3428 /*! @{ */
3429 
3430 #define ANADIG_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK   (0xFU)
3431 #define ANADIG_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT  (0U)
3432 /*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked */
3433 #define ANADIG_SLOT_CTRL_LOCKED_DOMAIN_ID(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & ANADIG_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
3434 
3435 #define ANADIG_SLOT_CTRL_DOMAIN_LOCK_MASK        (0x8000U)
3436 #define ANADIG_SLOT_CTRL_DOMAIN_LOCK_SHIFT       (15U)
3437 /*! DOMAIN_LOCK - Lock domain ID of this slot
3438  *  0b0..Do not lock the domain ID
3439  *  0b1..Lock the domain ID
3440  */
3441 #define ANADIG_SLOT_CTRL_DOMAIN_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & ANADIG_SLOT_CTRL_DOMAIN_LOCK_MASK)
3442 
3443 #define ANADIG_SLOT_CTRL_ALLOW_NONSECURE_MASK    (0x10000U)
3444 #define ANADIG_SLOT_CTRL_ALLOW_NONSECURE_SHIFT   (16U)
3445 /*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register
3446  *  0b0..Do not allow non-secure write access
3447  *  0b1..Allow non-secure write access
3448  */
3449 #define ANADIG_SLOT_CTRL_ALLOW_NONSECURE(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & ANADIG_SLOT_CTRL_ALLOW_NONSECURE_MASK)
3450 
3451 #define ANADIG_SLOT_CTRL_ALLOW_USER_MASK         (0x20000U)
3452 #define ANADIG_SLOT_CTRL_ALLOW_USER_SHIFT        (17U)
3453 /*! ALLOW_USER - Allow user write access to this domain control register or domain register
3454  *  0b0..Do not allow user write access
3455  *  0b1..Allow user write access
3456  */
3457 #define ANADIG_SLOT_CTRL_ALLOW_USER(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_SLOT_CTRL_ALLOW_USER_SHIFT)) & ANADIG_SLOT_CTRL_ALLOW_USER_MASK)
3458 
3459 #define ANADIG_SLOT_CTRL_LOCK_CONTROL_MASK       (0x80000000U)
3460 #define ANADIG_SLOT_CTRL_LOCK_CONTROL_SHIFT      (31U)
3461 /*! LOCK_CONTROL - Lock control of this slot
3462  *  0b0..Do not lock the control register of this slot
3463  *  0b1..Lock the control register of this slot
3464  */
3465 #define ANADIG_SLOT_CTRL_LOCK_CONTROL(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & ANADIG_SLOT_CTRL_LOCK_CONTROL_MASK)
3466 /*! @} */
3467 
3468 /* The count of ANADIG_SLOT_CTRL */
3469 #define ANADIG_SLOT_CTRL_COUNT                   (35U)
3470 
3471 
3472 /*!
3473  * @}
3474  */ /* end of group ANADIG_Register_Masks */
3475 
3476 
3477 /* ANADIG - Peripheral instance base addresses */
3478 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
3479   /** Peripheral ANADIG_SLOTS base address */
3480   #define ANADIG_SLOTS_BASE                        (0x54480000u)
3481   /** Peripheral ANADIG_SLOTS base address */
3482   #define ANADIG_SLOTS_BASE_NS                     (0x44480000u)
3483   /** Peripheral ANADIG_SLOTS base pointer */
3484   #define ANADIG_SLOTS                             ((ANADIG_Type *)ANADIG_SLOTS_BASE)
3485   /** Peripheral ANADIG_SLOTS base pointer */
3486   #define ANADIG_SLOTS_NS                          ((ANADIG_Type *)ANADIG_SLOTS_BASE_NS)
3487   /** Array initializer of ANADIG peripheral base addresses */
3488   #define ANADIG_BASE_ADDRS                        { ANADIG_SLOTS_BASE }
3489   /** Array initializer of ANADIG peripheral base pointers */
3490   #define ANADIG_BASE_PTRS                         { ANADIG_SLOTS }
3491   /** Array initializer of ANADIG peripheral base addresses */
3492   #define ANADIG_BASE_ADDRS_NS                     { ANADIG_SLOTS_BASE_NS }
3493   /** Array initializer of ANADIG peripheral base pointers */
3494   #define ANADIG_BASE_PTRS_NS                      { ANADIG_SLOTS_NS }
3495 #else
3496   /** Peripheral ANADIG_SLOTS base address */
3497   #define ANADIG_SLOTS_BASE                        (0x44480000u)
3498   /** Peripheral ANADIG_SLOTS base pointer */
3499   #define ANADIG_SLOTS                             ((ANADIG_Type *)ANADIG_SLOTS_BASE)
3500   /** Array initializer of ANADIG peripheral base addresses */
3501   #define ANADIG_BASE_ADDRS                        { ANADIG_SLOTS_BASE }
3502   /** Array initializer of ANADIG peripheral base pointers */
3503   #define ANADIG_BASE_PTRS                         { ANADIG_SLOTS }
3504 #endif
3505 
3506 /*!
3507  * @}
3508  */ /* end of group ANADIG_Peripheral_Access_Layer */
3509 
3510 
3511 /* ----------------------------------------------------------------------------
3512    -- ANADIG_LDO_BBSM Peripheral Access Layer
3513    ---------------------------------------------------------------------------- */
3514 
3515 /*!
3516  * @addtogroup ANADIG_LDO_BBSM_Peripheral_Access_Layer ANADIG_LDO_BBSM Peripheral Access Layer
3517  * @{
3518  */
3519 
3520 /** ANADIG_LDO_BBSM - Register Layout Typedef */
3521 typedef struct {
3522        uint8_t RESERVED_0[18240];
3523   __IO uint32_t PMU_LDO_AON_ANA;                   /**< PMU_LDO_AON_ANA_REGISTER, offset: 0x4740 */
3524        uint8_t RESERVED_1[28];
3525   __IO uint32_t PMU_LDO_AON_DIG;                   /**< PMU_LDO_AON_DIG_REGISTER, offset: 0x4760 */
3526 } ANADIG_LDO_BBSM_Type;
3527 
3528 /* ----------------------------------------------------------------------------
3529    -- ANADIG_LDO_BBSM Register Masks
3530    ---------------------------------------------------------------------------- */
3531 
3532 /*!
3533  * @addtogroup ANADIG_LDO_BBSM_Register_Masks ANADIG_LDO_BBSM Register Masks
3534  * @{
3535  */
3536 
3537 /*! @name PMU_LDO_AON_ANA - PMU_LDO_AON_ANA_REGISTER */
3538 /*! @{ */
3539 
3540 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK (0x1U)
3541 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_SHIFT (0U)
3542 /*! REG_LP_EN - reg_lp_en
3543  *  0b1..Disable
3544  *  0b0..Enable
3545  */
3546 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_LP_EN_MASK)
3547 
3548 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_DISABLE_MASK (0x4U)
3549 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_DISABLE_SHIFT (2U)
3550 /*! REG_DISABLE - reg_disable
3551  *  0b1..Disable
3552  *  0b0..Enable
3553  */
3554 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_REG_DISABLE_MASK)
3555 
3556 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
3557 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
3558 /*! PULL_DOWN_2MA_EN - pull_down_2ma_en
3559  *  0b0..Disable
3560  *  0b1..Enable
3561  */
3562 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_2MA_EN_MASK)
3563 
3564 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN_MASK (0x40U)
3565 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN_SHIFT (6U)
3566 /*! STANDBY_EN - standby_en
3567  *  0b0..Standby mode disable
3568  *  0b1..Standby mode enable
3569  */
3570 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_STANDBY_EN_MASK)
3571 
3572 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
3573 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
3574 /*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en */
3575 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
3576 
3577 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_TRACK_MODE_EN_MASK (0x80000U)
3578 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_TRACK_MODE_EN_SHIFT (19U)
3579 /*! TRACK_MODE_EN - Track Mode Enable
3580  *  0b0..Normal use
3581  *  0b1..Switch preparation
3582  */
3583 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_TRACK_MODE_EN_MASK)
3584 
3585 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
3586 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
3587 /*! PULL_DOWN_20UA_EN - pull_down_20ua_en
3588  *  0b0..Disable 20uA loading
3589  *  0b1..Enable 20uA loading
3590  */
3591 #define ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_ANA_PULL_DOWN_20UA_EN_MASK)
3592 /*! @} */
3593 
3594 /*! @name PMU_LDO_AON_DIG - PMU_LDO_AON_DIG_REGISTER */
3595 /*! @{ */
3596 
3597 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_REG_EN_MASK (0x4U)
3598 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_REG_EN_SHIFT (2U)
3599 /*! REG_EN - ENABLE_ILIMIT
3600  *  0b0..LDO_AON_DIG disable
3601  *  0b1..LDO_AON_DIG enable
3602  */
3603 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_REG_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_REG_EN_MASK)
3604 
3605 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_STANDBY_EN_MASK (0x40U)
3606 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_STANDBY_EN_SHIFT (6U)
3607 /*! STANDBY_EN - standby_en
3608  *  0b0..Standby disable
3609  *  0b1..Standby enable
3610  */
3611 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_STANDBY_EN_MASK)
3612 
3613 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
3614 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_SHIFT (20U)
3615 /*! VOLTAGE_SELECT - VOLTAGE_SELECT
3616  *  0b00000..Stable Voltage (range)
3617  *  0b00001..Stable Voltage (range)
3618  *  0b00010..Stable Voltage (range)
3619  *  0b00011..Stable Voltage (range)
3620  *  0b00100..Stable Voltage (range)
3621  *  0b00101..Stable Voltage (range)
3622  *  0b00110..Stable Voltage (range)
3623  *  0b00111..Stable Voltage (range)
3624  *  0b01000..Stable Voltage (range)
3625  *  0b01001..Stable Voltage (range)
3626  *  0b01010..Stable Voltage (range)
3627  *  0b01011..Stable Voltage (range)
3628  *  0b01100..Stable Voltage (range)
3629  *  0b01101..Stable Voltage (range)
3630  *  0b01110..Stable Voltage (range)
3631  *  0b01111..Stable Voltage (range)
3632  *  0b10000..Stable Voltage (range)
3633  *  0b10001..Stable Voltage (range)
3634  *  0b10010..Stable Voltage (range)
3635  *  0b10011..Stable Voltage (range)
3636  *  0b10100..Stable Voltage (range)
3637  *  0b10101..Stable Voltage (range)
3638  *  0b10110..Stable Voltage (range)
3639  *  0b10111..Stable Voltage (range)
3640  *  0b11000..Stable Voltage (range)
3641  *  0b11001..Stable Voltage (range)
3642  *  0b11010..Stable Voltage (range)
3643  *  0b11011..Stable Voltage (range)
3644  *  0b11100..Stable Voltage (range)
3645  *  0b11101..Stable Voltage (range)
3646  *  0b11110..Stable Voltage (range)
3647  *  0b11111..Stable Voltage (range)
3648  */
3649 #define ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_BBSM_PMU_LDO_AON_DIG_VOLTAGE_SELECT_MASK)
3650 /*! @} */
3651 
3652 
3653 /*!
3654  * @}
3655  */ /* end of group ANADIG_LDO_BBSM_Register_Masks */
3656 
3657 
3658 /* ANADIG_LDO_BBSM - Peripheral instance base addresses */
3659 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
3660   /** Peripheral ANADIG_LDO_BBSM base address */
3661   #define ANADIG_LDO_BBSM_BASE                     (0x54480000u)
3662   /** Peripheral ANADIG_LDO_BBSM base address */
3663   #define ANADIG_LDO_BBSM_BASE_NS                  (0x44480000u)
3664   /** Peripheral ANADIG_LDO_BBSM base pointer */
3665   #define ANADIG_LDO_BBSM                          ((ANADIG_LDO_BBSM_Type *)ANADIG_LDO_BBSM_BASE)
3666   /** Peripheral ANADIG_LDO_BBSM base pointer */
3667   #define ANADIG_LDO_BBSM_NS                       ((ANADIG_LDO_BBSM_Type *)ANADIG_LDO_BBSM_BASE_NS)
3668   /** Array initializer of ANADIG_LDO_BBSM peripheral base addresses */
3669   #define ANADIG_LDO_BBSM_BASE_ADDRS               { ANADIG_LDO_BBSM_BASE }
3670   /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */
3671   #define ANADIG_LDO_BBSM_BASE_PTRS                { ANADIG_LDO_BBSM }
3672   /** Array initializer of ANADIG_LDO_BBSM peripheral base addresses */
3673   #define ANADIG_LDO_BBSM_BASE_ADDRS_NS            { ANADIG_LDO_BBSM_BASE_NS }
3674   /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */
3675   #define ANADIG_LDO_BBSM_BASE_PTRS_NS             { ANADIG_LDO_BBSM_NS }
3676 #else
3677   /** Peripheral ANADIG_LDO_BBSM base address */
3678   #define ANADIG_LDO_BBSM_BASE                     (0x44480000u)
3679   /** Peripheral ANADIG_LDO_BBSM base pointer */
3680   #define ANADIG_LDO_BBSM                          ((ANADIG_LDO_BBSM_Type *)ANADIG_LDO_BBSM_BASE)
3681   /** Array initializer of ANADIG_LDO_BBSM peripheral base addresses */
3682   #define ANADIG_LDO_BBSM_BASE_ADDRS               { ANADIG_LDO_BBSM_BASE }
3683   /** Array initializer of ANADIG_LDO_BBSM peripheral base pointers */
3684   #define ANADIG_LDO_BBSM_BASE_PTRS                { ANADIG_LDO_BBSM }
3685 #endif
3686 
3687 /*!
3688  * @}
3689  */ /* end of group ANADIG_LDO_BBSM_Peripheral_Access_Layer */
3690 
3691 
3692 /* ----------------------------------------------------------------------------
3693    -- ANADIG_MISC Peripheral Access Layer
3694    ---------------------------------------------------------------------------- */
3695 
3696 /*!
3697  * @addtogroup ANADIG_MISC_Peripheral_Access_Layer ANADIG_MISC Peripheral Access Layer
3698  * @{
3699  */
3700 
3701 /** ANADIG_MISC - Register Layout Typedef */
3702 typedef struct {
3703        uint8_t RESERVED_0[18432];
3704   __I  uint32_t MISC_DIFPROG;                      /**< Chip Silicon Version Register, offset: 0x4800 */
3705 } ANADIG_MISC_Type;
3706 
3707 /* ----------------------------------------------------------------------------
3708    -- ANADIG_MISC Register Masks
3709    ---------------------------------------------------------------------------- */
3710 
3711 /*!
3712  * @addtogroup ANADIG_MISC_Register_Masks ANADIG_MISC Register Masks
3713  * @{
3714  */
3715 
3716 /*! @name MISC_DIFPROG - Chip Silicon Version Register */
3717 /*! @{ */
3718 
3719 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK     (0xFFFFFFFFU)
3720 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT    (0U)
3721 /*! CHIPID - Chip ID */
3722 #define ANADIG_MISC_MISC_DIFPROG_CHIPID(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
3723 /*! @} */
3724 
3725 
3726 /*!
3727  * @}
3728  */ /* end of group ANADIG_MISC_Register_Masks */
3729 
3730 
3731 /* ANADIG_MISC - Peripheral instance base addresses */
3732 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
3733   /** Peripheral ANADIG_MISC base address */
3734   #define ANADIG_MISC_BASE                         (0x54480000u)
3735   /** Peripheral ANADIG_MISC base address */
3736   #define ANADIG_MISC_BASE_NS                      (0x44480000u)
3737   /** Peripheral ANADIG_MISC base pointer */
3738   #define ANADIG_MISC                              ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
3739   /** Peripheral ANADIG_MISC base pointer */
3740   #define ANADIG_MISC_NS                           ((ANADIG_MISC_Type *)ANADIG_MISC_BASE_NS)
3741   /** Array initializer of ANADIG_MISC peripheral base addresses */
3742   #define ANADIG_MISC_BASE_ADDRS                   { ANADIG_MISC_BASE }
3743   /** Array initializer of ANADIG_MISC peripheral base pointers */
3744   #define ANADIG_MISC_BASE_PTRS                    { ANADIG_MISC }
3745   /** Array initializer of ANADIG_MISC peripheral base addresses */
3746   #define ANADIG_MISC_BASE_ADDRS_NS                { ANADIG_MISC_BASE_NS }
3747   /** Array initializer of ANADIG_MISC peripheral base pointers */
3748   #define ANADIG_MISC_BASE_PTRS_NS                 { ANADIG_MISC_NS }
3749 #else
3750   /** Peripheral ANADIG_MISC base address */
3751   #define ANADIG_MISC_BASE                         (0x44480000u)
3752   /** Peripheral ANADIG_MISC base pointer */
3753   #define ANADIG_MISC                              ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
3754   /** Array initializer of ANADIG_MISC peripheral base addresses */
3755   #define ANADIG_MISC_BASE_ADDRS                   { ANADIG_MISC_BASE }
3756   /** Array initializer of ANADIG_MISC peripheral base pointers */
3757   #define ANADIG_MISC_BASE_PTRS                    { ANADIG_MISC }
3758 #endif
3759 
3760 /*!
3761  * @}
3762  */ /* end of group ANADIG_MISC_Peripheral_Access_Layer */
3763 
3764 
3765 /* ----------------------------------------------------------------------------
3766    -- ANADIG_OSC Peripheral Access Layer
3767    ---------------------------------------------------------------------------- */
3768 
3769 /*!
3770  * @addtogroup ANADIG_OSC_Peripheral_Access_Layer ANADIG_OSC Peripheral Access Layer
3771  * @{
3772  */
3773 
3774 /** ANADIG_OSC - Register Layout Typedef */
3775 typedef struct {
3776        uint8_t RESERVED_0[17168];
3777   __IO uint32_t OSC_RC24M_CTRL;                    /**< 24MHz RCOSC Control Register, offset: 0x4310 */
3778        uint8_t RESERVED_1[12];
3779   __IO uint32_t OSC_24M_CTRL;                      /**< 24MHz OSC Control Register, offset: 0x4320 */
3780        uint8_t RESERVED_2[28];
3781   __I  uint32_t OSC_400M_CTRL0;                    /**< 400MHz RCOSC Control0 Register, offset: 0x4340 */
3782        uint8_t RESERVED_3[12];
3783   __IO uint32_t OSC_400M_CTRL1;                    /**< 400MHz RCOSC Control1 Register, offset: 0x4350 */
3784 } ANADIG_OSC_Type;
3785 
3786 /* ----------------------------------------------------------------------------
3787    -- ANADIG_OSC Register Masks
3788    ---------------------------------------------------------------------------- */
3789 
3790 /*!
3791  * @addtogroup ANADIG_OSC_Register_Masks ANADIG_OSC Register Masks
3792  * @{
3793  */
3794 
3795 /*! @name OSC_RC24M_CTRL - 24MHz RCOSC Control Register */
3796 /*! @{ */
3797 
3798 #define ANADIG_OSC_OSC_RC24M_CTRL_TEN_MASK       (0x2U)
3799 #define ANADIG_OSC_OSC_RC24M_CTRL_TEN_SHIFT      (1U)
3800 /*! TEN - RC24M Enable
3801  *  0b0..Power down
3802  *  0b1..Power up
3803  */
3804 #define ANADIG_OSC_OSC_RC24M_CTRL_TEN(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_RC24M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_RC24M_CTRL_TEN_MASK)
3805 
3806 #define ANADIG_OSC_OSC_RC24M_CTRL_SOURCE_SEL_24M_MASK (0x2000000U)
3807 #define ANADIG_OSC_OSC_RC24M_CTRL_SOURCE_SEL_24M_SHIFT (25U)
3808 /*! SOURCE_SEL_24M - source_sel_24M
3809  *  0b0..OSC_RC24M
3810  *  0b1..OSC24M
3811  */
3812 #define ANADIG_OSC_OSC_RC24M_CTRL_SOURCE_SEL_24M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_RC24M_CTRL_SOURCE_SEL_24M_SHIFT)) & ANADIG_OSC_OSC_RC24M_CTRL_SOURCE_SEL_24M_MASK)
3813 
3814 #define ANADIG_OSC_OSC_RC24M_CTRL_RC_24M_CONTROL_MODE_MASK (0x80000000U)
3815 #define ANADIG_OSC_OSC_RC24M_CTRL_RC_24M_CONTROL_MODE_SHIFT (31U)
3816 /*! RC_24M_CONTROL_MODE - RCOSC Control Mode
3817  *  0b0..Software mode (default)
3818  *  0b1..GPC mode
3819  */
3820 #define ANADIG_OSC_OSC_RC24M_CTRL_RC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_RC24M_CTRL_RC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_RC24M_CTRL_RC_24M_CONTROL_MODE_MASK)
3821 /*! @} */
3822 
3823 /*! @name OSC_24M_CTRL - 24MHz OSC Control Register */
3824 /*! @{ */
3825 
3826 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
3827 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT  (1U)
3828 /*! BYPASS_EN - 24MHz OSC Bypass Enable
3829  *  0b0..Disable
3830  *  0b1..Enable
3831  */
3832 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
3833 
3834 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK       (0x4U)
3835 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT      (2U)
3836 /*! LP_EN - 24MHz OSC Low-Power Mode Enable
3837  *  0b0..High Gain mode (HP)
3838  *  0b1..Low-power mode (LP)
3839  */
3840 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
3841 
3842 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
3843 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
3844 /*! OSC_COMP_MODE - 24MHz OSC Comparator Mode
3845  *  0b0..Single-ended mode (default)
3846  *  0b1..Differential mode (test mode)
3847  */
3848 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
3849 
3850 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK      (0x10U)
3851 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT     (4U)
3852 /*! OSC_EN - 24MHz OSC Enable
3853  *  0b0..Disable
3854  *  0b1..Enable
3855  */
3856 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
3857 
3858 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
3859 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
3860 /*! OSC_24M_GATE - 24MHz OSC Gate Control
3861  *  0b0..Not Gated
3862  *  0b1..Gated
3863  */
3864 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
3865 
3866 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
3867 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
3868 /*! OSC_24M_STABLE - 24MHz OSC Stable
3869  *  0b0..Not Stable
3870  *  0b1..Stable
3871  */
3872 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
3873 
3874 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
3875 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
3876 /*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode
3877  *  0b0..Software mode (default)
3878  *  0b1..GPC mode
3879  */
3880 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
3881 /*! @} */
3882 
3883 /*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */
3884 /*! @{ */
3885 
3886 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
3887 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
3888 /*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY */
3889 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
3890 /*! @} */
3891 
3892 /*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */
3893 /*! @{ */
3894 
3895 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK       (0x1U)
3896 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT      (0U)
3897 /*! PWD - Power down control for 400MHz RCOSC
3898  *  0b0..No Power down
3899  *  0b1..Power down
3900  */
3901 #define ANADIG_OSC_OSC_400M_CTRL1_PWD(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
3902 
3903 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
3904 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
3905 /*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC
3906  *  0b0..Not Gated
3907  *  0b1..Gated
3908  */
3909 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
3910 
3911 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
3912 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
3913 /*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode
3914  *  0b0..Software mode (default)
3915  *  0b1..GPC mode
3916  */
3917 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
3918 /*! @} */
3919 
3920 
3921 /*!
3922  * @}
3923  */ /* end of group ANADIG_OSC_Register_Masks */
3924 
3925 
3926 /* ANADIG_OSC - Peripheral instance base addresses */
3927 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
3928   /** Peripheral ANADIG_OSC base address */
3929   #define ANADIG_OSC_BASE                          (0x54480000u)
3930   /** Peripheral ANADIG_OSC base address */
3931   #define ANADIG_OSC_BASE_NS                       (0x44480000u)
3932   /** Peripheral ANADIG_OSC base pointer */
3933   #define ANADIG_OSC                               ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
3934   /** Peripheral ANADIG_OSC base pointer */
3935   #define ANADIG_OSC_NS                            ((ANADIG_OSC_Type *)ANADIG_OSC_BASE_NS)
3936   /** Array initializer of ANADIG_OSC peripheral base addresses */
3937   #define ANADIG_OSC_BASE_ADDRS                    { ANADIG_OSC_BASE }
3938   /** Array initializer of ANADIG_OSC peripheral base pointers */
3939   #define ANADIG_OSC_BASE_PTRS                     { ANADIG_OSC }
3940   /** Array initializer of ANADIG_OSC peripheral base addresses */
3941   #define ANADIG_OSC_BASE_ADDRS_NS                 { ANADIG_OSC_BASE_NS }
3942   /** Array initializer of ANADIG_OSC peripheral base pointers */
3943   #define ANADIG_OSC_BASE_PTRS_NS                  { ANADIG_OSC_NS }
3944 #else
3945   /** Peripheral ANADIG_OSC base address */
3946   #define ANADIG_OSC_BASE                          (0x44480000u)
3947   /** Peripheral ANADIG_OSC base pointer */
3948   #define ANADIG_OSC                               ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
3949   /** Array initializer of ANADIG_OSC peripheral base addresses */
3950   #define ANADIG_OSC_BASE_ADDRS                    { ANADIG_OSC_BASE }
3951   /** Array initializer of ANADIG_OSC peripheral base pointers */
3952   #define ANADIG_OSC_BASE_PTRS                     { ANADIG_OSC }
3953 #endif
3954 
3955 /*!
3956  * @}
3957  */ /* end of group ANADIG_OSC_Peripheral_Access_Layer */
3958 
3959 
3960 /* ----------------------------------------------------------------------------
3961    -- ANADIG_PLL Peripheral Access Layer
3962    ---------------------------------------------------------------------------- */
3963 
3964 /*!
3965  * @addtogroup ANADIG_PLL_Peripheral_Access_Layer ANADIG_PLL Peripheral Access Layer
3966  * @{
3967  */
3968 
3969 /** ANADIG_PLL - Register Layout Typedef */
3970 typedef struct {
3971        uint8_t RESERVED_0[16384];
3972   __IO uint32_t ARM_PLL_CTRL;                      /**< ARM_PLL_CTRL_REGISTER, offset: 0x4000 */
3973        uint8_t RESERVED_1[12];
3974   __IO uint32_t SYS_PLL3_CTRL;                     /**< SYS_PLL3_CTRL_REGISTER, offset: 0x4010 */
3975        uint8_t RESERVED_2[12];
3976   __IO uint32_t SYS_PLL3_UPDATE;                   /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x4020 */
3977        uint8_t RESERVED_3[12];
3978   __IO uint32_t SYS_PLL3_PFD;                      /**< SYS_PLL3_PFD_REGISTER, offset: 0x4030 */
3979        uint8_t RESERVED_4[12];
3980   __IO uint32_t SYS_PLL2_CTRL;                     /**< SYS_PLL2_CTRL_REGISTER, offset: 0x4040 */
3981        uint8_t RESERVED_5[12];
3982   __IO uint32_t SYS_PLL2_UPDATE;                   /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x4050 */
3983        uint8_t RESERVED_6[12];
3984   __IO uint32_t SYS_PLL2_SS;                       /**< SYS_PLL2_SS_REGISTER, offset: 0x4060 */
3985        uint8_t RESERVED_7[12];
3986   __IO uint32_t SYS_PLL2_PFD;                      /**< SYS_PLL2_PFD_REGISTER, offset: 0x4070 */
3987        uint8_t RESERVED_8[12];
3988   __IO uint32_t SYS_PLL2_MFN;                      /**< SYS_PLL2_MFN_REGISTER, offset: 0x4080 */
3989        uint8_t RESERVED_9[12];
3990   __IO uint32_t SYS_PLL2_MFI;                      /**< SYS_PLL2_MFI_REGISTER, offset: 0x4090 */
3991        uint8_t RESERVED_10[12];
3992   __IO uint32_t SYS_PLL2_MFD;                      /**< SYS_PLL2_MFD_REGISTER, offset: 0x40A0 */
3993        uint8_t RESERVED_11[92];
3994   __IO uint32_t SYS_PLL1_CTRL;                     /**< SYS_PLL1_CTRL_REGISTER, offset: 0x4100 */
3995        uint8_t RESERVED_12[252];
3996   __IO uint32_t PLL_AUDIO_CTRL;                    /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x4200 */
3997 } ANADIG_PLL_Type;
3998 
3999 /* ----------------------------------------------------------------------------
4000    -- ANADIG_PLL Register Masks
4001    ---------------------------------------------------------------------------- */
4002 
4003 /*!
4004  * @addtogroup ANADIG_PLL_Register_Masks ANADIG_PLL Register Masks
4005  * @{
4006  */
4007 
4008 /*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */
4009 /*! @{ */
4010 
4011 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK  (0xFFU)
4012 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
4013 /*! DIV_SELECT - DIV_SELECT */
4014 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
4015 
4016 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
4017 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
4018 /*! HOLD_RING_OFF - PLL Start up initialization
4019  *  0b0..Normal operation
4020  *  0b1..Initialize PLL start up
4021  */
4022 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
4023 
4024 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK     (0x2000U)
4025 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT    (13U)
4026 /*! POWERUP - Power up the PLL
4027  *  0b1..Power Up the PLL
4028  *  0b0..Power down the PLL
4029  */
4030 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
4031 
4032 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK  (0x4000U)
4033 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
4034 /*! ENABLE_CLK - Enable the clock output.
4035  *  0b0..Disable the clock
4036  *  0b1..Enable the clock
4037  */
4038 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
4039 
4040 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
4041 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
4042 /*! POST_DIV_SEL - POST_DIV_SEL
4043  *  0b00..post_div=2
4044  *  0b01..post_div=4
4045  *  0b10..post_div=8
4046  *  0b11..post_div=1
4047  */
4048 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
4049 
4050 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK      (0x20000U)
4051 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT     (17U)
4052 /*! BYPASS - Bypass the pll.
4053  *  0b1..Bypass Mode
4054  *  0b0..Function mode
4055  */
4056 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
4057 
4058 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
4059 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
4060 /*! ARM_PLL_STABLE - ARM_PLL_STABLE
4061  *  0b1..ARM PLL is stable
4062  *  0b0..ARM PLL is not stable
4063  */
4064 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
4065 
4066 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
4067 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
4068 /*! ARM_PLL_GATE - ARM_PLL_GATE
4069  *  0b1..Clock is gated
4070  *  0b0..Clock is not gated
4071  */
4072 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
4073 
4074 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
4075 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
4076 /*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode
4077  *  0b0..Software Mode (Default)
4078  *  0b1..GPC Mode
4079  */
4080 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
4081 /*! @} */
4082 
4083 /*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */
4084 /*! @{ */
4085 
4086 #define ANADIG_PLL_SYS_PLL3_CTRL_DIV_SELECT_MASK (0x7U)
4087 #define ANADIG_PLL_SYS_PLL3_CTRL_DIV_SELECT_SHIFT (0U)
4088 /*! DIV_SELECT - DIV_SELECT
4089  *  0b000..div_select=130x1: div_select=150x2
4090  *  0b001..div_select=160x3: div_select=200x4
4091  *  0b010..div_select=220x5: div_select=250x6
4092  *  0b011..div_select=300x7: div_select=240
4093  */
4094 #define ANADIG_PLL_SYS_PLL3_CTRL_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_DIV_SELECT_MASK)
4095 
4096 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
4097 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
4098 /*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate */
4099 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
4100 
4101 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
4102 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
4103 /*! PLL_REG_EN - Enable Internal PLL Regulator */
4104 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
4105 
4106 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
4107 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
4108 /*! HOLD_RING_OFF - PLL Start up initialization
4109  *  0b0..Normal operation
4110  *  0b1..Initialize PLL start up
4111  */
4112 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
4113 
4114 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
4115 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
4116 /*! ENABLE_CLK - Enable the clock output.
4117  *  0b0..Disable the clock
4118  *  0b1..Enable the clock
4119  */
4120 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
4121 
4122 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK     (0x10000U)
4123 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT    (16U)
4124 /*! BYPASS - BYPASS
4125  *  0b1..Bypass Mode
4126  *  0b0..Function mode
4127  */
4128 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
4129 
4130 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK    (0x200000U)
4131 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT   (21U)
4132 /*! POWERUP - Power up the PLL
4133  *  0b1..Power Up the PLL
4134  *  0b0..Power down the PLL
4135  */
4136 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
4137 
4138 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
4139 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
4140 /*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE
4141  *  0b0..Software Mode (Default)
4142  *  0b1..GPC Mode
4143  */
4144 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
4145 
4146 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
4147 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
4148 /*! SYS_PLL3_STABLE - SYS_PLL3_STABLE
4149  *  0b0..Not Stable
4150  *  0b1..Stable
4151  */
4152 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
4153 
4154 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
4155 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
4156 /*! SYS_PLL3_GATE - SYS_PLL3_GATE
4157  *  0b1..Clock is gated
4158  *  0b0..Clock is not gated
4159  */
4160 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
4161 
4162 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
4163 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
4164 /*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode
4165  *  0b0..Software Mode (Default)
4166  *  0b1..GPC Mode
4167  */
4168 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
4169 /*! @} */
4170 
4171 /*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */
4172 /*! @{ */
4173 
4174 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
4175 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
4176 /*! PFD0_UPDATE - PFD0_OVERRIDE */
4177 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
4178 
4179 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
4180 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
4181 /*! PFD1_UPDATE - PFD1_OVERRIDE */
4182 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
4183 
4184 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
4185 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
4186 /*! PFD2_UPDATE - PFD2_OVERRIDE */
4187 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
4188 
4189 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
4190 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
4191 /*! PFD3_UPDATE - PFD3_UPDATE */
4192 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
4193 
4194 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
4195 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
4196 /*! PFD0_CONTROL_MODE - pfd0_control_mode
4197  *  0b0..Software Mode (Default)
4198  *  0b1..GPC Mode
4199  */
4200 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
4201 
4202 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
4203 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
4204 /*! PFD1_CONTROL_MODE - pfd1_control_mode
4205  *  0b0..Software Mode (Default)
4206  *  0b1..GPC Mode
4207  */
4208 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
4209 
4210 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
4211 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
4212 /*! PFD2_CONTROL_MODE - pdf2_control_mode
4213  *  0b0..Software Mode (Default)
4214  *  0b1..GPC Mode
4215  */
4216 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_CONTROL_MODE_MASK)
4217 
4218 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
4219 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
4220 /*! PFD3_CONTROL_MODE - pfd3_control_mode
4221  *  0b0..Software Mode (Default)
4222  *  0b1..GPC Mode
4223  */
4224 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
4225 /*! @} */
4226 
4227 /*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */
4228 /*! @{ */
4229 
4230 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK   (0x3FU)
4231 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT  (0U)
4232 /*! PFD0_FRAC - PFD0_FRAC */
4233 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
4234 
4235 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
4236 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
4237 /*! PFD0_STABLE - PFD0_STABLE */
4238 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
4239 
4240 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
4241 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
4242 /*! PFD0_DIV1_CLKGATE - PFD0_CLKGATE
4243  *  0b1..Fractional divider clock (reference ref_pfd0) is off (power savings
4244  *  0b0..PFD0 fractional divider clock is enabled
4245  */
4246 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
4247 
4248 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK   (0x3F00U)
4249 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT  (8U)
4250 /*! PFD1_FRAC - PFD1_FRAC */
4251 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
4252 
4253 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
4254 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
4255 /*! PFD1_STABLE - PFD1_STABLE */
4256 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
4257 
4258 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
4259 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
4260 /*! PFD1_DIV1_CLKGATE - PFD1_CLKGATE
4261  *  0b1..Fractional divider clock (reference PFD1) is off (power savings)
4262  *  0b0..PFD1 fractional divider clock is enabled
4263  */
4264 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
4265 
4266 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK   (0x3F0000U)
4267 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT  (16U)
4268 /*! PFD2_FRAC - PFD2_FRAC */
4269 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
4270 
4271 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
4272 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
4273 /*! PFD2_STABLE - PFD2_STABLE */
4274 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
4275 
4276 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
4277 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
4278 /*! PFD2_DIV1_CLKGATE - PFD2_CLKGATE
4279  *  0b1..Fractional divider clock (reference PFD2) is off (power savings)
4280  *  0b0..PFD2 fractional divider clock is enabled
4281  */
4282 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
4283 
4284 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK   (0x3F000000U)
4285 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT  (24U)
4286 /*! PFD3_FRAC - PFD3_FRAC */
4287 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
4288 
4289 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
4290 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
4291 /*! PFD3_STABLE - PFD3_STABLE */
4292 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
4293 
4294 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
4295 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
4296 /*! PFD3_DIV1_CLKGATE - PFD3_CLKGATE
4297  *  0b1..Fractional divider clock (reference PFD3) is off (power savings)
4298  *  0b0..PFD3 fractional divider clock is enabled
4299  */
4300 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
4301 /*! @} */
4302 
4303 /*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */
4304 /*! @{ */
4305 
4306 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
4307 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
4308 /*! PLL_REG_EN - Enable Internal PLL Regulator
4309  *  0b0..Disable
4310  *  0b1..Enable
4311  */
4312 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
4313 
4314 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
4315 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
4316 /*! HOLD_RING_OFF - PLL Start up initialization
4317  *  0b0..Normal operation
4318  *  0b1..Initialize PLL start up
4319  */
4320 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
4321 
4322 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
4323 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
4324 /*! ENABLE_CLK - Enable the clock output.
4325  *  0b0..Disable the clock
4326  *  0b1..Enable the clock
4327  */
4328 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
4329 
4330 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK     (0x10000U)
4331 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT    (16U)
4332 /*! BYPASS - Bypass the pll.
4333  *  0b1..Bypass Mode
4334  *  0b0..Function mode
4335  */
4336 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
4337 
4338 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
4339 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
4340 /*! DITHER_ENABLE - DITHER_ENABLE
4341  *  0b0..Disable Dither
4342  *  0b1..Enable Dither
4343  */
4344 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
4345 
4346 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
4347 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
4348 /*! PFD_OFFSET_EN - PFD_OFFSET_EN */
4349 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
4350 
4351 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
4352 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
4353 /*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE */
4354 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
4355 
4356 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK    (0x800000U)
4357 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT   (23U)
4358 /*! POWERUP - Power up the PLL
4359  *  0b1..Power Up the PLL
4360  *  0b0..Power down the PLL
4361  */
4362 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
4363 
4364 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
4365 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
4366 /*! SYS_PLL2_STABLE - SYS_PLL2_STABLE */
4367 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
4368 
4369 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
4370 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
4371 /*! SYS_PLL2_GATE - SYS_PLL2_GATE
4372  *  0b1..Clock is gated
4373  *  0b0..Clock is not gated
4374  */
4375 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
4376 
4377 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
4378 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
4379 /*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode
4380  *  0b0..Software Mode (Default)
4381  *  0b1..GPC Mode
4382  */
4383 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
4384 /*! @} */
4385 
4386 /*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */
4387 /*! @{ */
4388 
4389 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
4390 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
4391 /*! PFD0_UPDATE - PFD0_UPDATE */
4392 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
4393 
4394 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
4395 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
4396 /*! PFD1_UPDATE - PFD1_UPDATE */
4397 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
4398 
4399 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
4400 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
4401 /*! PFD2_UPDATE - PFD2_UPDATE */
4402 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
4403 
4404 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
4405 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
4406 /*! PFD3_UPDATE - PFD3_UPDATE */
4407 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
4408 
4409 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
4410 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
4411 /*! PFD0_CONTROL_MODE - pfd0_control_mode
4412  *  0b0..Software Mode (Default)
4413  *  0b1..GPC Mode
4414  */
4415 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
4416 
4417 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
4418 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
4419 /*! PFD1_CONTROL_MODE - pfd1_control_mode
4420  *  0b0..Software Mode (Default)
4421  *  0b1..GPC Mode
4422  */
4423 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
4424 
4425 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
4426 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
4427 /*! PFD2_CONTROL_MODE - pfd2_control_mode
4428  *  0b0..Software Mode (Default)
4429  *  0b1..GPC Mode
4430  */
4431 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
4432 
4433 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
4434 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
4435 /*! PFD3_CONTROL_MODE - pfd3_control_mode
4436  *  0b0..Software Mode (Default)
4437  *  0b1..GPC Mode
4438  */
4439 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
4440 /*! @} */
4441 
4442 /*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */
4443 /*! @{ */
4444 
4445 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK         (0x7FFFU)
4446 #define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT        (0U)
4447 /*! STEP - STEP */
4448 #define ANADIG_PLL_SYS_PLL2_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
4449 
4450 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK       (0x8000U)
4451 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT      (15U)
4452 /*! ENABLE - ENABLE
4453  *  0b1..Enable Spread Spectrum
4454  *  0b0..Disable Spread Spectrum
4455  */
4456 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
4457 
4458 #define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK         (0xFFFF0000U)
4459 #define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT        (16U)
4460 /*! STOP - STOP */
4461 #define ANADIG_PLL_SYS_PLL2_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
4462 /*! @} */
4463 
4464 /*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */
4465 /*! @{ */
4466 
4467 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK   (0x3FU)
4468 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT  (0U)
4469 /*! PFD0_FRAC - PFD0_FRAC */
4470 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
4471 
4472 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
4473 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
4474 /*! PFD0_STABLE - PFD0_STABLE */
4475 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
4476 
4477 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
4478 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
4479 /*! PFD0_DIV1_CLKGATE - PFD0_CLKGATE
4480  *  0b0..PFD0 fractional divider clock is enabled.
4481  *  0b1..Fractional divider clock (reference PFD0) is off (power savings)
4482  */
4483 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
4484 
4485 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK   (0x3F00U)
4486 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT  (8U)
4487 /*! PFD1_FRAC - PFD1_FRAC */
4488 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
4489 
4490 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
4491 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
4492 /*! PFD1_STABLE - PFD1_STABLE */
4493 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
4494 
4495 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
4496 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
4497 /*! PFD1_DIV1_CLKGATE - PFD1_CLKGATE
4498  *  0b0..PFD1 fractional divider clock is enabled.
4499  *  0b1..Fractional divider clock (reference PFD1) is off (power savings)
4500  */
4501 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
4502 
4503 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK   (0x3F0000U)
4504 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT  (16U)
4505 /*! PFD2_FRAC - PFD2_FRAC */
4506 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
4507 
4508 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
4509 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
4510 /*! PFD2_STABLE - PFD2_STABLE */
4511 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
4512 
4513 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
4514 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
4515 /*! PFD2_DIV1_CLKGATE - PFD2_CLKGATE
4516  *  0b0..PFD2 fractional divider clock is enabled.
4517  *  0b1..Fractional divider clock (reference PFD2) is off (power savings)
4518  */
4519 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
4520 
4521 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK   (0x3F000000U)
4522 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT  (24U)
4523 /*! PFD3_FRAC - PFD3_FRAC */
4524 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
4525 
4526 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
4527 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
4528 /*! PFD3_STABLE - PFD3_STABLE */
4529 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
4530 
4531 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
4532 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
4533 /*! PFD3_DIV1_CLKGATE - PFD3_CLKGATE
4534  *  0b0..PFD3 fractional divider clock is enabled.
4535  *  0b1..Fractional divider clock (reference PFD3) is off (power savings)
4536  */
4537 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
4538 /*! @} */
4539 
4540 /*! @name SYS_PLL2_MFN - SYS_PLL2_MFN_REGISTER */
4541 /*! @{ */
4542 
4543 #define ANADIG_PLL_SYS_PLL2_MFN_MFN_MASK         (0x3FFFFFFFU)
4544 #define ANADIG_PLL_SYS_PLL2_MFN_MFN_SHIFT        (0U)
4545 /*! MFN - MFN */
4546 #define ANADIG_PLL_SYS_PLL2_MFN_MFN(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFN_MFN_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFN_MFN_MASK)
4547 /*! @} */
4548 
4549 /*! @name SYS_PLL2_MFI - SYS_PLL2_MFI_REGISTER */
4550 /*! @{ */
4551 
4552 #define ANADIG_PLL_SYS_PLL2_MFI_MFI_MASK         (0x7FU)
4553 #define ANADIG_PLL_SYS_PLL2_MFI_MFI_SHIFT        (0U)
4554 /*! MFI - MFI */
4555 #define ANADIG_PLL_SYS_PLL2_MFI_MFI(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFI_MFI_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFI_MFI_MASK)
4556 /*! @} */
4557 
4558 /*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */
4559 /*! @{ */
4560 
4561 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK         (0x3FFFFFFFU)
4562 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT        (0U)
4563 /*! MFD - Denominator */
4564 #define ANADIG_PLL_SYS_PLL2_MFD_MFD(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
4565 /*! @} */
4566 
4567 /*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */
4568 /*! @{ */
4569 
4570 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
4571 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
4572 /*! ENABLE_CLK - ENABLE_CLK
4573  *  0b1..Disable
4574  *  0b0..Enable
4575  */
4576 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
4577 
4578 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
4579 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
4580 /*! SYS_PLL1_GATE - SYS_PLL1_GATE
4581  *  0b1..Gate the output
4582  *  0b0..No gate
4583  */
4584 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
4585 
4586 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
4587 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
4588 /*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2
4589  *  0b1..Enabled
4590  *  0b0..Disabled
4591  */
4592 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
4593 
4594 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
4595 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
4596 /*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5
4597  *  0b1..Enabled
4598  *  0b0..Disabled
4599  */
4600 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
4601 
4602 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
4603 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
4604 /*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE
4605  *  0b0..Software Mode (Default)
4606  *  0b1..GPC Mode
4607  */
4608 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
4609 
4610 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
4611 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
4612 /*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE
4613  *  0b0..Software Mode (Default)
4614  *  0b1..GPC Mode
4615  */
4616 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
4617 
4618 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
4619 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
4620 /*! SYS_PLL1_STABLE - SYS_PLL1_STABLE
4621  *  0b0..Not Stable
4622  *  0b1..Stable
4623  */
4624 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
4625 
4626 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
4627 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
4628 /*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE
4629  *  0b0..Software Mode (Default)
4630  *  0b1..GPC Mode
4631  */
4632 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
4633 /*! @} */
4634 
4635 /*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */
4636 /*! @{ */
4637 
4638 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
4639 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
4640 /*! ENABLE_CLK - ENABLE_CLK
4641  *  0b0..Disable
4642  *  0b1..Enable
4643  */
4644 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
4645 
4646 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
4647 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
4648 /*! PLL_AUDIO_GATE - PLL_AUDIO_GATE
4649  *  0b1..Gate the output
4650  *  0b0..No gate
4651  */
4652 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
4653 
4654 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
4655 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
4656 /*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE */
4657 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
4658 
4659 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
4660 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
4661 /*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode
4662  *  0b0..Software Mode (Default)
4663  *  0b1..GPC Mode
4664  */
4665 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
4666 /*! @} */
4667 
4668 
4669 /*!
4670  * @}
4671  */ /* end of group ANADIG_PLL_Register_Masks */
4672 
4673 
4674 /* ANADIG_PLL - Peripheral instance base addresses */
4675 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
4676   /** Peripheral ANADIG_PLL base address */
4677   #define ANADIG_PLL_BASE                          (0x54480000u)
4678   /** Peripheral ANADIG_PLL base address */
4679   #define ANADIG_PLL_BASE_NS                       (0x44480000u)
4680   /** Peripheral ANADIG_PLL base pointer */
4681   #define ANADIG_PLL                               ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
4682   /** Peripheral ANADIG_PLL base pointer */
4683   #define ANADIG_PLL_NS                            ((ANADIG_PLL_Type *)ANADIG_PLL_BASE_NS)
4684   /** Array initializer of ANADIG_PLL peripheral base addresses */
4685   #define ANADIG_PLL_BASE_ADDRS                    { ANADIG_PLL_BASE }
4686   /** Array initializer of ANADIG_PLL peripheral base pointers */
4687   #define ANADIG_PLL_BASE_PTRS                     { ANADIG_PLL }
4688   /** Array initializer of ANADIG_PLL peripheral base addresses */
4689   #define ANADIG_PLL_BASE_ADDRS_NS                 { ANADIG_PLL_BASE_NS }
4690   /** Array initializer of ANADIG_PLL peripheral base pointers */
4691   #define ANADIG_PLL_BASE_PTRS_NS                  { ANADIG_PLL_NS }
4692 #else
4693   /** Peripheral ANADIG_PLL base address */
4694   #define ANADIG_PLL_BASE                          (0x44480000u)
4695   /** Peripheral ANADIG_PLL base pointer */
4696   #define ANADIG_PLL                               ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
4697   /** Array initializer of ANADIG_PLL peripheral base addresses */
4698   #define ANADIG_PLL_BASE_ADDRS                    { ANADIG_PLL_BASE }
4699   /** Array initializer of ANADIG_PLL peripheral base pointers */
4700   #define ANADIG_PLL_BASE_PTRS                     { ANADIG_PLL }
4701 #endif
4702 
4703 /*!
4704  * @}
4705  */ /* end of group ANADIG_PLL_Peripheral_Access_Layer */
4706 
4707 
4708 /* ----------------------------------------------------------------------------
4709    -- ANADIG_PMU Peripheral Access Layer
4710    ---------------------------------------------------------------------------- */
4711 
4712 /*!
4713  * @addtogroup ANADIG_PMU_Peripheral_Access_Layer ANADIG_PMU Peripheral Access Layer
4714  * @{
4715  */
4716 
4717 /** ANADIG_PMU - Register Layout Typedef */
4718 typedef struct {
4719        uint8_t RESERVED_0[17920];
4720   __IO uint32_t PMU_BIAS_CTRL;                     /**< PMU_BIAS_CTRL_REGISTER, offset: 0x4600 */
4721        uint8_t RESERVED_1[12];
4722   __IO uint32_t PMU_BIAS_CTRL2;                    /**< PMU_BIAS_CTRL2_REGISTER, offset: 0x4610 */
4723        uint8_t RESERVED_2[44];
4724   __IO uint32_t PMU_LDO_PLL;                       /**< PMU_LDO_PLL_REGISTER, offset: 0x4640 */
4725        uint8_t RESERVED_3[188];
4726   __IO uint32_t PMU_POWER_DETECT_CTRL;             /**< PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x4700 */
4727        uint8_t RESERVED_4[12];
4728   __IO uint32_t PMU_REF_CTRL;                      /**< PMU_REF_CTRL_REGISTER, offset: 0x4710 */
4729 } ANADIG_PMU_Type;
4730 
4731 /* ----------------------------------------------------------------------------
4732    -- ANADIG_PMU Register Masks
4733    ---------------------------------------------------------------------------- */
4734 
4735 /*!
4736  * @addtogroup ANADIG_PMU_Register_Masks ANADIG_PMU Register Masks
4737  * @{
4738  */
4739 
4740 /*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */
4741 /*! @{ */
4742 
4743 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
4744 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
4745 /*! WB_CFG_1P8 - wb_cfg_1p8 */
4746 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
4747 
4748 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
4749 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
4750 /*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8
4751  *  0b0..VDD_LV1
4752  *  0b1..VDD_LV2
4753  */
4754 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
4755 
4756 #define ANADIG_PMU_PMU_BIAS_CTRL_FBB_M7_STBY_EN_MASK (0x8000U)
4757 #define ANADIG_PMU_PMU_BIAS_CTRL_FBB_M7_STBY_EN_SHIFT (15U)
4758 /*! FBB_M7_STBY_EN - standby enable bit of fbb m7
4759  *  0b0..FBB_M7 will be still on when gpc give standby request. After the mode is switched to gpc mode, keep this bit as it is.
4760  *  0b1..FBB_M7 will standby when gpc give standby request.
4761  */
4762 #define ANADIG_PMU_PMU_BIAS_CTRL_FBB_M7_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_FBB_M7_STBY_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_FBB_M7_STBY_EN_MASK)
4763 
4764 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK (0xF000000U)
4765 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_SHIFT (24U)
4766 /*! WB_PW_LVL_1P8 - wb_pw_lvl_1p8 */
4767 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK)
4768 
4769 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK (0xF0000000U)
4770 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_SHIFT (28U)
4771 /*! WB_NW_LVL_1P8 - wb_nw_lvl_1p8 */
4772 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK)
4773 /*! @} */
4774 
4775 /*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */
4776 /*! @{ */
4777 
4778 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1000U)
4779 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (12U)
4780 /*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8
4781  *  0b1..WELL connected to back biasing generators.
4782  *  0b0..WELL connected to no back-biasing power supplies
4783  */
4784 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
4785 
4786 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
4787 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
4788 /*! WB_ADJ_1P8 - wb_adj_1p8
4789  *  0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF
4790  *  0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF
4791  *  0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF
4792  *  0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF
4793  *  0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF
4794  *  0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF
4795  *  0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF
4796  *  0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF
4797  *  0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF
4798  *  0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF
4799  *  0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF
4800  *  0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF
4801  *  0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF
4802  *  0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF
4803  *  0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF
4804  *  0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
4805  */
4806 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
4807 
4808 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK     (0x1000000U)
4809 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT    (24U)
4810 /*! WB_EN - wb_en
4811  *  0b0..disable
4812  *  0b1..Enable
4813  */
4814 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
4815 
4816 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK     (0x4000000U)
4817 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT    (26U)
4818 /*! WB_OK - Digital Output pin.
4819  *  0b0..Regulator is unstable.
4820  *  0b1..Regulator is stable.
4821  */
4822 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
4823 /*! @} */
4824 
4825 /*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */
4826 /*! @{ */
4827 
4828 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
4829 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
4830 /*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE
4831  *  0b0..SW Control
4832  *  0b1..HW Control
4833  */
4834 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
4835 
4836 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK (0x4U)
4837 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_SHIFT (2U)
4838 /*! LDO_PLL_STBY_EN - standby enable bit of ldopll
4839  *  0b0..phy_ldo will be still on when gpc gives standby request. After the mode is switched to gpc mode, keep this bit as it is.
4840  *  0b1..phy_ldo will standby when gpc give standby request
4841  */
4842 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK)
4843 /*! @} */
4844 
4845 /*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */
4846 /*! @{ */
4847 
4848 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_AON1P0_MASK (0x100U)
4849 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_AON1P0_SHIFT (8U)
4850 /*! CKGB_AON1P0 - ckgb_aon1p0
4851  *  0b0..To disable lpsr_1p0, ckgb need to be disabled first.
4852  *  0b1..After lpsr_1p0 start up, wait for 1ms and then set ckgb bit.
4853  */
4854 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_AON1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_AON1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_AON1P0_MASK)
4855 /*! @} */
4856 
4857 /*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */
4858 /*! @{ */
4859 
4860 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
4861 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
4862 /*! REF_CONTROL_MODE - REF_CONTROL_MODE
4863  *  0b0..SW Control
4864  *  0b1..HW Control
4865  */
4866 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
4867 
4868 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
4869 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
4870 /*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer */
4871 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
4872 
4873 #define ANADIG_PMU_PMU_REF_CTRL_REF_STBY_EN_MASK (0x40U)
4874 #define ANADIG_PMU_PMU_REF_CTRL_REF_STBY_EN_SHIFT (6U)
4875 /*! REF_STBY_EN - standby enable bit of reftop */
4876 #define ANADIG_PMU_PMU_REF_CTRL_REF_STBY_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_STBY_EN_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_STBY_EN_MASK)
4877 /*! @} */
4878 
4879 
4880 /*!
4881  * @}
4882  */ /* end of group ANADIG_PMU_Register_Masks */
4883 
4884 
4885 /* ANADIG_PMU - Peripheral instance base addresses */
4886 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
4887   /** Peripheral ANADIG_PMU base address */
4888   #define ANADIG_PMU_BASE                          (0x54480000u)
4889   /** Peripheral ANADIG_PMU base address */
4890   #define ANADIG_PMU_BASE_NS                       (0x44480000u)
4891   /** Peripheral ANADIG_PMU base pointer */
4892   #define ANADIG_PMU                               ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
4893   /** Peripheral ANADIG_PMU base pointer */
4894   #define ANADIG_PMU_NS                            ((ANADIG_PMU_Type *)ANADIG_PMU_BASE_NS)
4895   /** Array initializer of ANADIG_PMU peripheral base addresses */
4896   #define ANADIG_PMU_BASE_ADDRS                    { ANADIG_PMU_BASE }
4897   /** Array initializer of ANADIG_PMU peripheral base pointers */
4898   #define ANADIG_PMU_BASE_PTRS                     { ANADIG_PMU }
4899   /** Array initializer of ANADIG_PMU peripheral base addresses */
4900   #define ANADIG_PMU_BASE_ADDRS_NS                 { ANADIG_PMU_BASE_NS }
4901   /** Array initializer of ANADIG_PMU peripheral base pointers */
4902   #define ANADIG_PMU_BASE_PTRS_NS                  { ANADIG_PMU_NS }
4903 #else
4904   /** Peripheral ANADIG_PMU base address */
4905   #define ANADIG_PMU_BASE                          (0x44480000u)
4906   /** Peripheral ANADIG_PMU base pointer */
4907   #define ANADIG_PMU                               ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
4908   /** Array initializer of ANADIG_PMU peripheral base addresses */
4909   #define ANADIG_PMU_BASE_ADDRS                    { ANADIG_PMU_BASE }
4910   /** Array initializer of ANADIG_PMU peripheral base pointers */
4911   #define ANADIG_PMU_BASE_PTRS                     { ANADIG_PMU }
4912 #endif
4913 
4914 /*!
4915  * @}
4916  */ /* end of group ANADIG_PMU_Peripheral_Access_Layer */
4917 
4918 
4919 /* ----------------------------------------------------------------------------
4920    -- ANADIG_TEMPSENSOR Peripheral Access Layer
4921    ---------------------------------------------------------------------------- */
4922 
4923 /*!
4924  * @addtogroup ANADIG_TEMPSENSOR_Peripheral_Access_Layer ANADIG_TEMPSENSOR Peripheral Access Layer
4925  * @{
4926  */
4927 
4928 /** ANADIG_TEMPSENSOR - Register Layout Typedef */
4929 typedef struct {
4930        uint8_t RESERVED_0[17712];
4931   __I  uint32_t TEMPSNS_OTP_TRIM_VALUE;            /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x4530 */
4932 } ANADIG_TEMPSENSOR_Type;
4933 
4934 /* ----------------------------------------------------------------------------
4935    -- ANADIG_TEMPSENSOR Register Masks
4936    ---------------------------------------------------------------------------- */
4937 
4938 /*!
4939  * @addtogroup ANADIG_TEMPSENSOR_Register_Masks ANADIG_TEMPSENSOR Register Masks
4940  * @{
4941  */
4942 
4943 /*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */
4944 /*! @{ */
4945 
4946 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
4947 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
4948 /*! TEMPSNS_TEMP_VAL - Temperature Value at 25C */
4949 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK)
4950 /*! @} */
4951 
4952 
4953 /*!
4954  * @}
4955  */ /* end of group ANADIG_TEMPSENSOR_Register_Masks */
4956 
4957 
4958 /* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
4959 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
4960   /** Peripheral ANADIG_TEMPSENSOR base address */
4961   #define ANADIG_TEMPSENSOR_BASE                   (0x54480000u)
4962   /** Peripheral ANADIG_TEMPSENSOR base address */
4963   #define ANADIG_TEMPSENSOR_BASE_NS                (0x44480000u)
4964   /** Peripheral ANADIG_TEMPSENSOR base pointer */
4965   #define ANADIG_TEMPSENSOR                        ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
4966   /** Peripheral ANADIG_TEMPSENSOR base pointer */
4967   #define ANADIG_TEMPSENSOR_NS                     ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE_NS)
4968   /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
4969   #define ANADIG_TEMPSENSOR_BASE_ADDRS             { ANADIG_TEMPSENSOR_BASE }
4970   /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
4971   #define ANADIG_TEMPSENSOR_BASE_PTRS              { ANADIG_TEMPSENSOR }
4972   /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
4973   #define ANADIG_TEMPSENSOR_BASE_ADDRS_NS          { ANADIG_TEMPSENSOR_BASE_NS }
4974   /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
4975   #define ANADIG_TEMPSENSOR_BASE_PTRS_NS           { ANADIG_TEMPSENSOR_NS }
4976 #else
4977   /** Peripheral ANADIG_TEMPSENSOR base address */
4978   #define ANADIG_TEMPSENSOR_BASE                   (0x44480000u)
4979   /** Peripheral ANADIG_TEMPSENSOR base pointer */
4980   #define ANADIG_TEMPSENSOR                        ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
4981   /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
4982   #define ANADIG_TEMPSENSOR_BASE_ADDRS             { ANADIG_TEMPSENSOR_BASE }
4983   /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
4984   #define ANADIG_TEMPSENSOR_BASE_PTRS              { ANADIG_TEMPSENSOR }
4985 #endif
4986 
4987 /*!
4988  * @}
4989  */ /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
4990 
4991 
4992 /* ----------------------------------------------------------------------------
4993    -- AOI Peripheral Access Layer
4994    ---------------------------------------------------------------------------- */
4995 
4996 /*!
4997  * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
4998  * @{
4999  */
5000 
5001 /** AOI - Register Layout Typedef */
5002 typedef struct {
5003   struct {                                         /* offset: 0x0, array step: 0x4 */
5004     __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */
5005     __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */
5006   } BFCRT[4];
5007 } AOI_Type;
5008 
5009 /* ----------------------------------------------------------------------------
5010    -- AOI Register Masks
5011    ---------------------------------------------------------------------------- */
5012 
5013 /*!
5014  * @addtogroup AOI_Register_Masks AOI Register Masks
5015  * @{
5016  */
5017 
5018 /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */
5019 /*! @{ */
5020 
5021 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
5022 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
5023 /*! PT1_DC - Product Term 1, Input D Configuration
5024  *  0b00..Force input D to become 0
5025  *  0b01..Pass input D
5026  *  0b10..Complement input D
5027  *  0b11..Force input D to become 1
5028  */
5029 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
5030 
5031 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
5032 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
5033 /*! PT1_CC - Product Term 1, Input C Configuration
5034  *  0b00..Force input C to become 0
5035  *  0b01..Pass input C
5036  *  0b10..Complement input C
5037  *  0b11..Force input C to become 1
5038  */
5039 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
5040 
5041 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
5042 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
5043 /*! PT1_BC - Product Term 1, Input B Configuration
5044  *  0b00..Force input B to become 0
5045  *  0b01..Pass input B
5046  *  0b10..Complement input B
5047  *  0b11..Force input B to become 1
5048  */
5049 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
5050 
5051 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
5052 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
5053 /*! PT1_AC - Product Term 1, Input A Configuration
5054  *  0b00..Force input A to become 0
5055  *  0b01..Pass input A
5056  *  0b10..Complement input A
5057  *  0b11..Force input A to become 1
5058  */
5059 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
5060 
5061 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
5062 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
5063 /*! PT0_DC - Product Term 0, Input D Configuration
5064  *  0b00..Force input D to become 0
5065  *  0b01..Pass input D
5066  *  0b10..Complement input D
5067  *  0b11..Force input D to become 1
5068  */
5069 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
5070 
5071 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
5072 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
5073 /*! PT0_CC - Product Term 0, Input C Configuration
5074  *  0b00..Force input C to become 0
5075  *  0b01..Pass input C
5076  *  0b10..Complement input C
5077  *  0b11..Force input C to become 1
5078  */
5079 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
5080 
5081 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
5082 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
5083 /*! PT0_BC - Product Term 0, Input B Configuration
5084  *  0b00..Force input B to become 0
5085  *  0b01..Pass input B
5086  *  0b10..Complement input B
5087  *  0b11..Force input B to become 1
5088  */
5089 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
5090 
5091 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
5092 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
5093 /*! PT0_AC - Product Term 0, Input A Configuration
5094  *  0b00..Force input A to become 0
5095  *  0b01..Pass input A
5096  *  0b10..Complement input A
5097  *  0b11..Force input A to become 1
5098  */
5099 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
5100 /*! @} */
5101 
5102 /* The count of AOI_BFCRT01 */
5103 #define AOI_BFCRT01_COUNT                        (4U)
5104 
5105 /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */
5106 /*! @{ */
5107 
5108 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
5109 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
5110 /*! PT3_DC - Product Term 3, Input D Configuration
5111  *  0b00..Force input D to become 0
5112  *  0b01..Pass input D
5113  *  0b10..Complement input D
5114  *  0b11..Force input D to become 1
5115  */
5116 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
5117 
5118 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
5119 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
5120 /*! PT3_CC - Product Term 3, Input C Configuration
5121  *  0b00..Force input C to become 0
5122  *  0b01..Pass input C
5123  *  0b10..Complement input C
5124  *  0b11..Force input C to become 1
5125  */
5126 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
5127 
5128 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
5129 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
5130 /*! PT3_BC - Product Term 3, Input B Configuration
5131  *  0b00..Force input B to become 0
5132  *  0b01..Pass input B
5133  *  0b10..Complement input B
5134  *  0b11..Force input B to become 1
5135  */
5136 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
5137 
5138 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
5139 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
5140 /*! PT3_AC - Product Term 3, Input A Configuration
5141  *  0b00..Force input A to become 0
5142  *  0b01..Pass input A
5143  *  0b10..Complement input A
5144  *  0b11..Force input to become 1
5145  */
5146 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
5147 
5148 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
5149 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
5150 /*! PT2_DC - Product Term 2, Input D Configuration
5151  *  0b00..Force input D to become 0
5152  *  0b01..Pass input D
5153  *  0b10..Complement input D
5154  *  0b11..Force input D to become 1
5155  */
5156 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
5157 
5158 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
5159 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
5160 /*! PT2_CC - Product Term 2, Input C Configuration
5161  *  0b00..Force input C to become 0
5162  *  0b01..Pass input C
5163  *  0b10..Complement input C
5164  *  0b11..Force input C to become 1
5165  */
5166 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
5167 
5168 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
5169 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
5170 /*! PT2_BC - Product Term 2, Input B Configuration
5171  *  0b00..Force input B to become 0
5172  *  0b01..Pass input B
5173  *  0b10..Complement input B
5174  *  0b11..Force input B to become 1
5175  */
5176 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
5177 
5178 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
5179 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
5180 /*! PT2_AC - Product Term 2, Input A Configuration
5181  *  0b00..Force input A to become 0
5182  *  0b01..Pass input A
5183  *  0b10..Complement input A
5184  *  0b11..Force input A to become 1
5185  */
5186 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
5187 /*! @} */
5188 
5189 /* The count of AOI_BFCRT23 */
5190 #define AOI_BFCRT23_COUNT                        (4U)
5191 
5192 
5193 /*!
5194  * @}
5195  */ /* end of group AOI_Register_Masks */
5196 
5197 
5198 /* AOI - Peripheral instance base addresses */
5199 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
5200   /** Peripheral AOI1 base address */
5201   #define AOI1_BASE                                (0x52780000u)
5202   /** Peripheral AOI1 base address */
5203   #define AOI1_BASE_NS                             (0x42780000u)
5204   /** Peripheral AOI1 base pointer */
5205   #define AOI1                                     ((AOI_Type *)AOI1_BASE)
5206   /** Peripheral AOI1 base pointer */
5207   #define AOI1_NS                                  ((AOI_Type *)AOI1_BASE_NS)
5208   /** Peripheral AOI2 base address */
5209   #define AOI2_BASE                                (0x52790000u)
5210   /** Peripheral AOI2 base address */
5211   #define AOI2_BASE_NS                             (0x42790000u)
5212   /** Peripheral AOI2 base pointer */
5213   #define AOI2                                     ((AOI_Type *)AOI2_BASE)
5214   /** Peripheral AOI2 base pointer */
5215   #define AOI2_NS                                  ((AOI_Type *)AOI2_BASE_NS)
5216   /** Peripheral AOI3 base address */
5217   #define AOI3_BASE                                (0x527E0000u)
5218   /** Peripheral AOI3 base address */
5219   #define AOI3_BASE_NS                             (0x427E0000u)
5220   /** Peripheral AOI3 base pointer */
5221   #define AOI3                                     ((AOI_Type *)AOI3_BASE)
5222   /** Peripheral AOI3 base pointer */
5223   #define AOI3_NS                                  ((AOI_Type *)AOI3_BASE_NS)
5224   /** Peripheral AOI4 base address */
5225   #define AOI4_BASE                                (0x527F0000u)
5226   /** Peripheral AOI4 base address */
5227   #define AOI4_BASE_NS                             (0x427F0000u)
5228   /** Peripheral AOI4 base pointer */
5229   #define AOI4                                     ((AOI_Type *)AOI4_BASE)
5230   /** Peripheral AOI4 base pointer */
5231   #define AOI4_NS                                  ((AOI_Type *)AOI4_BASE_NS)
5232   /** Array initializer of AOI peripheral base addresses */
5233   #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE, AOI3_BASE, AOI4_BASE }
5234   /** Array initializer of AOI peripheral base pointers */
5235   #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2, AOI3, AOI4 }
5236   /** Array initializer of AOI peripheral base addresses */
5237   #define AOI_BASE_ADDRS_NS                        { 0u, AOI1_BASE_NS, AOI2_BASE_NS, AOI3_BASE_NS, AOI4_BASE_NS }
5238   /** Array initializer of AOI peripheral base pointers */
5239   #define AOI_BASE_PTRS_NS                         { (AOI_Type *)0u, AOI1_NS, AOI2_NS, AOI3_NS, AOI4_NS }
5240 #else
5241   /** Peripheral AOI1 base address */
5242   #define AOI1_BASE                                (0x42780000u)
5243   /** Peripheral AOI1 base pointer */
5244   #define AOI1                                     ((AOI_Type *)AOI1_BASE)
5245   /** Peripheral AOI2 base address */
5246   #define AOI2_BASE                                (0x42790000u)
5247   /** Peripheral AOI2 base pointer */
5248   #define AOI2                                     ((AOI_Type *)AOI2_BASE)
5249   /** Peripheral AOI3 base address */
5250   #define AOI3_BASE                                (0x427E0000u)
5251   /** Peripheral AOI3 base pointer */
5252   #define AOI3                                     ((AOI_Type *)AOI3_BASE)
5253   /** Peripheral AOI4 base address */
5254   #define AOI4_BASE                                (0x427F0000u)
5255   /** Peripheral AOI4 base pointer */
5256   #define AOI4                                     ((AOI_Type *)AOI4_BASE)
5257   /** Array initializer of AOI peripheral base addresses */
5258   #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE, AOI3_BASE, AOI4_BASE }
5259   /** Array initializer of AOI peripheral base pointers */
5260   #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2, AOI3, AOI4 }
5261 #endif
5262 
5263 /*!
5264  * @}
5265  */ /* end of group AOI_Peripheral_Access_Layer */
5266 
5267 
5268 /* ----------------------------------------------------------------------------
5269    -- ASRC Peripheral Access Layer
5270    ---------------------------------------------------------------------------- */
5271 
5272 /*!
5273  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
5274  * @{
5275  */
5276 
5277 /** ASRC - Register Layout Typedef */
5278 typedef struct {
5279   __IO uint32_t ASRCTR;                            /**< ASRC Control, offset: 0x0 */
5280   __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable, offset: 0x4 */
5281        uint8_t RESERVED_0[4];
5282   __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration, offset: 0xC */
5283   __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status, offset: 0x10 */
5284   __IO uint32_t ASRCSR;                            /**< ASRC Clock Source, offset: 0x14 */
5285   __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider 1, offset: 0x18 */
5286   __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider 2, offset: 0x1C */
5287   __I  uint32_t ASRSTR;                            /**< ASRC Status, offset: 0x20 */
5288        uint8_t RESERVED_1[28];
5289   __IO uint32_t ASRPM[5];                          /**< ASRC Parameter x, array offset: 0x40, array step: 0x4 */
5290   __IO uint32_t ASRTFR1;                           /**< ASRC Task Queue FIFO 1, offset: 0x54 */
5291        uint8_t RESERVED_2[4];
5292   __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter, offset: 0x5C */
5293   __O  uint32_t ASRDIA;                            /**< ASRC Data Input for Pair x, offset: 0x60 */
5294   __I  uint32_t ASRDOA;                            /**< ASRC Data Output for Pair x, offset: 0x64 */
5295   __O  uint32_t ASRDIB;                            /**< ASRC Data Input for Pair x, offset: 0x68 */
5296   __I  uint32_t ASRDOB;                            /**< ASRC Data Output for Pair x, offset: 0x6C */
5297   __O  uint32_t ASRDIC;                            /**< ASRC Data Input for Pair x, offset: 0x70 */
5298   __I  uint32_t ASRDOC;                            /**< ASRC Data Output for Pair x, offset: 0x74 */
5299        uint8_t RESERVED_3[8];
5300   __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
5301   __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
5302   __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
5303   __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
5304   __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
5305   __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
5306   __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period, offset: 0x98 */
5307   __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period, offset: 0x9C */
5308   __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control for Pair A, offset: 0xA0 */
5309   __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status for Pair A, offset: 0xA4 */
5310   __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control for Pair B, offset: 0xA8 */
5311   __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status for Pair B, offset: 0xAC */
5312   __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control for Pair C, offset: 0xB0 */
5313   __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status for Pair C, offset: 0xB4 */
5314        uint8_t RESERVED_4[8];
5315   __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control 1 for Pair X, array offset: 0xC0, array step: 0x4 */
5316 } ASRC_Type;
5317 
5318 /* ----------------------------------------------------------------------------
5319    -- ASRC Register Masks
5320    ---------------------------------------------------------------------------- */
5321 
5322 /*!
5323  * @addtogroup ASRC_Register_Masks ASRC Register Masks
5324  * @{
5325  */
5326 
5327 /*! @name ASRCTR - ASRC Control */
5328 /*! @{ */
5329 
5330 #define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
5331 #define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
5332 /*! ASRCEN - ASRC Enable
5333  *  0b0..Disabled
5334  *  0b1..Enabled
5335  */
5336 #define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
5337 
5338 #define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
5339 #define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
5340 /*! ASREA - ASRC Enable A
5341  *  0b0..Disabled
5342  *  0b1..Enabled
5343  */
5344 #define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
5345 
5346 #define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
5347 #define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
5348 /*! ASREB - ASRC Enable B
5349  *  0b0..Disabled
5350  *  0b1..Enabled
5351  */
5352 #define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
5353 
5354 #define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
5355 #define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
5356 /*! ASREC - ASRC Enable C
5357  *  0b0..Disabled
5358  *  0b1..Enabled
5359  */
5360 #define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
5361 
5362 #define ASRC_ASRCTR_SRST_MASK                    (0x10U)
5363 #define ASRC_ASRCTR_SRST_SHIFT                   (4U)
5364 /*! SRST - Software Reset
5365  *  0b0..ASRC Software reset cleared
5366  *  0b1..ASRC Software reset generated. NOTE: This is a self-clear bit
5367  */
5368 #define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
5369 
5370 #define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
5371 #define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
5372 /*! IDRA - Use Ideal Ratio for Pair A
5373  *  0b0..ASRC internal measured ratio is used
5374  *  0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used
5375  */
5376 #define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
5377 
5378 #define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
5379 #define ASRC_ASRCTR_USRA_SHIFT                   (14U)
5380 /*! USRA - Use Ratio for Pair A
5381  *  0b1..Use ratio as the input to ASRC for pair A
5382  *  0b0..Do not use ratio as the input to ASRC for pair A
5383  */
5384 #define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
5385 
5386 #define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
5387 #define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
5388 /*! IDRB - Use Ideal Ratio for Pair B
5389  *  0b0..ASRC internal measured ratio is used
5390  *  0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used
5391  */
5392 #define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
5393 
5394 #define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
5395 #define ASRC_ASRCTR_USRB_SHIFT                   (16U)
5396 /*! USRB - Use Ratio for Pair B
5397  *  0b1..Use ratio as the input to ASRC for pair B
5398  *  0b0..Do not use ratio as the input to ASRC for pair B
5399  */
5400 #define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
5401 
5402 #define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
5403 #define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
5404 /*! IDRC - Use Ideal Ratio for Pair C
5405  *  0b0..ASRC internal measured ratio is used
5406  *  0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used
5407  */
5408 #define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
5409 
5410 #define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
5411 #define ASRC_ASRCTR_USRC_SHIFT                   (18U)
5412 /*! USRC - Use Ratio for Pair C
5413  *  0b1..Use ratio as the input to ASRC for pair C
5414  *  0b0..Do not use ratio as the input to ASRC for pair C
5415  */
5416 #define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
5417 
5418 #define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
5419 #define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
5420 /*! ATSA - ASRC Pair A Automatic Selection For Processing Options
5421  *  0b1..Pair A automatically updates its pre-processing and post-processing options
5422  *  0b0..Pair A does not automatically update its pre-processing and post-processing options
5423  */
5424 #define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
5425 
5426 #define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
5427 #define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
5428 /*! ATSB - ASRC Pair B Automatic Selection For Processing Options
5429  *  0b1..Pair B automatically updates its pre-processing and post-processing options
5430  *  0b0..Pair B does not automatically update its pre-processing and post-processing options
5431  */
5432 #define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
5433 
5434 #define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
5435 #define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
5436 /*! ATSC - ASRC Pair C Automatic Selection For Processing Options
5437  *  0b1..Pair C automatically updates its pre-processing and post-processing options
5438  *  0b0..Pair C does not automatically update its pre-processing and post-processing options
5439  */
5440 #define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
5441 /*! @} */
5442 
5443 /*! @name ASRIER - ASRC Interrupt Enable */
5444 /*! @{ */
5445 
5446 #define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
5447 #define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
5448 /*! ADIEA - Pair A Data Input Interrupt Enable
5449  *  0b1..Enabled
5450  *  0b0..Disabled
5451  */
5452 #define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
5453 
5454 #define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
5455 #define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
5456 /*! ADIEB - Pair B Data Input Interrupt Enable
5457  *  0b1..Enabled
5458  *  0b0..Disabled
5459  */
5460 #define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
5461 
5462 #define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
5463 #define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
5464 /*! ADIEC - Pair C Data Input Interrupt Enable
5465  *  0b1..Enabled
5466  *  0b0..Disabled
5467  */
5468 #define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
5469 
5470 #define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
5471 #define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
5472 /*! ADOEA - Pair A Data Output Interrupt Enable
5473  *  0b1..Enabled
5474  *  0b0..Disabled
5475  */
5476 #define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
5477 
5478 #define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
5479 #define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
5480 /*! ADOEB - Pair B Data Output Interrupt Enable
5481  *  0b1..Enabled
5482  *  0b0..Disabled
5483  */
5484 #define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
5485 
5486 #define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
5487 #define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
5488 /*! ADOEC - Pair C Data Output Interrupt Enable
5489  *  0b1..Enabled
5490  *  0b0..Disabled
5491  */
5492 #define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
5493 
5494 #define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
5495 #define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
5496 /*! AOLIE - Overload Interrupt Enable
5497  *  0b1..Enabled
5498  *  0b0..Disabled
5499  */
5500 #define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
5501 
5502 #define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
5503 #define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
5504 /*! AFPWE - FP in Wait State Interrupt Enable
5505  *  0b1..Enabled
5506  *  0b0..Disabled
5507  */
5508 #define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
5509 /*! @} */
5510 
5511 /*! @name ASRCNCR - ASRC Channel Number Configuration */
5512 /*! @{ */
5513 
5514 #define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
5515 #define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
5516 /*! ANCA - Number of A Channels
5517  *  0b0000..0 channels in A (Pair A is disabled)
5518  *  0b0001..1 channel in A
5519  *  0b0010..2 channels in A
5520  *  0b0011..3 channels in A
5521  *  0b0100..4 channels in A
5522  *  0b0101..5 channels in A
5523  *  0b0110..6 channels in A
5524  *  0b0111..7 channels in A
5525  *  0b1000..8 channels in A
5526  *  0b1001..9 channels in A
5527  *  0b1010..10 channels in A
5528  *  0b1011-0b1111..Should not be used.
5529  */
5530 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
5531 
5532 #define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
5533 #define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
5534 /*! ANCB - Number of B Channels
5535  *  0b0000..0 channels in B (Pair B is disabled)
5536  *  0b0001..1 channel in B
5537  *  0b0010..2 channels in B
5538  *  0b0011..3 channels in B
5539  *  0b0100..4 channels in B
5540  *  0b0101..5 channels in B
5541  *  0b0110..6 channels in B
5542  *  0b0111..7 channels in B
5543  *  0b1000..8 channels in B
5544  *  0b1001..9 channels in B
5545  *  0b1010..10 channels in B
5546  *  0b1011-0b1111..Should not be used.
5547  */
5548 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
5549 
5550 #define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
5551 #define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
5552 /*! ANCC - Number of C Channels
5553  *  0b0000..0 channels in C (Pair C is disabled)
5554  *  0b0001..1 channel in C
5555  *  0b0010..2 channels in C
5556  *  0b0011..3 channels in C
5557  *  0b0100..4 channels in C
5558  *  0b0101..5 channels in C
5559  *  0b0110..6 channels in C
5560  *  0b0111..7 channels in C
5561  *  0b1000..8 channels in C
5562  *  0b1001..9 channels in C
5563  *  0b1010..10 channels in C
5564  *  0b1011-0b1111..Should not be used.
5565  */
5566 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
5567 /*! @} */
5568 
5569 /*! @name ASRCFG - ASRC Filter Configuration Status */
5570 /*! @{ */
5571 
5572 #define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
5573 #define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
5574 /*! PREMODA - Pre-Processing Configuration for Conversion Pair A
5575  *  0b00..Select Upsampling-by-2
5576  *  0b01..Select Direct-Connection
5577  *  0b10..Select Downsampling-by-2
5578  *  0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use.
5579  */
5580 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
5581 
5582 #define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
5583 #define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
5584 /*! POSTMODA - Post-Processing Configuration for Conversion Pair A
5585  *  0b00..Select Upsampling-by-2
5586  *  0b01..Select Direct-Connection
5587  *  0b10..Select Downsampling-by-2
5588  *  0b11..Reserved.
5589  */
5590 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
5591 
5592 #define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
5593 #define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
5594 /*! PREMODB - Pre-Processing Configuration for Conversion Pair B
5595  *  0b00..Select Upsampling-by-2
5596  *  0b01..Select Direct-Connection
5597  *  0b10..Select Downsampling-by-2
5598  *  0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use.
5599  */
5600 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
5601 
5602 #define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
5603 #define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
5604 /*! POSTMODB - Post-Processing Configuration for Conversion Pair B
5605  *  0b00..Select Upsampling-by-2
5606  *  0b01..Select Direct-Connection
5607  *  0b10..Select Downsampling-by-2
5608  *  0b11..Reserved.
5609  */
5610 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
5611 
5612 #define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
5613 #define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
5614 /*! PREMODC - Pre-Processing Configuration for Conversion Pair C
5615  *  0b00..Select Upsampling-by-2
5616  *  0b01..Select Direct-Connection
5617  *  0b10..Select Downsampling-by-2
5618  *  0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use.
5619  */
5620 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
5621 
5622 #define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
5623 #define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
5624 /*! POSTMODC - Post-Processing Configuration for Conversion Pair C
5625  *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
5626  *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
5627  *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
5628  *  0b11..Reserved.
5629  */
5630 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
5631 
5632 #define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
5633 #define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
5634 /*! NDPRA - Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A
5635  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
5636  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
5637  */
5638 #define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
5639 
5640 #define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
5641 #define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
5642 /*! NDPRB - Not Use Default Parameters for RAM-Stored Parameters For Conversion Pair B
5643  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
5644  *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
5645  */
5646 #define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
5647 
5648 #define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
5649 #define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
5650 /*! NDPRC - Not Use Default Parameters for RAM-Stored Parameters For Conversion Pair C
5651  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
5652  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
5653  */
5654 #define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
5655 
5656 #define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
5657 #define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
5658 /*! INIRQA - Initialization for Conversion Pair A is served
5659  *  0b0..Initialization for Conversion Pair A not served
5660  *  0b1..Initialization for Conversion Pair A served
5661  */
5662 #define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
5663 
5664 #define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
5665 #define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
5666 /*! INIRQB - Initialization for Conversion Pair B is Served
5667  *  0b0..Initialization for Conversion Pair B not served
5668  *  0b1..Initialization for Conversion Pair B served
5669  */
5670 #define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
5671 
5672 #define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
5673 #define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
5674 /*! INIRQC - Initialization for Conversion Pair C is Served
5675  *  0b0..Initialization for Conversion Pair C not served
5676  *  0b1..Initialization for Conversion Pair C served
5677  */
5678 #define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
5679 /*! @} */
5680 
5681 /*! @name ASRCSR - ASRC Clock Source */
5682 /*! @{ */
5683 
5684 #define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
5685 #define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
5686 /*! AICSA - Input Clock Source A
5687  *  0b0000..Bit clock 0
5688  *  0b0001..Bit clock 1
5689  *  0b0010..Bit clock 2
5690  *  0b0011..Bit clock 3
5691  *  0b0100..Bit clock 4
5692  *  0b0101..Bit clock 5
5693  *  0b0110..Bit clock 6
5694  *  0b0111..Bit clock 7
5695  *  0b1000..Bit clock 8
5696  *  0b1001..Bit clock 9
5697  *  0b1010..Bit clock A
5698  *  0b1011..Bit clock B
5699  *  0b1100..Bit clock C
5700  *  0b1101..Bit clock D
5701  *  0b1110..Bit clock E
5702  *  0b1111..Clock disabled, connected to zero
5703  */
5704 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
5705 
5706 #define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
5707 #define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
5708 /*! AICSB - Input Clock Source B
5709  *  0b0000..Bit clock 0
5710  *  0b0001..Bit clock 1
5711  *  0b0010..Bit clock 2
5712  *  0b0011..Bit clock 3
5713  *  0b0100..Bit clock 4
5714  *  0b0101..Bit clock 5
5715  *  0b0110..Bit clock 6
5716  *  0b0111..Bit clock 7
5717  *  0b1000..Bit clock 8
5718  *  0b1001..Bit clock 9
5719  *  0b1010..Bit clock A
5720  *  0b1011..Bit clock B
5721  *  0b1100..Bit clock C
5722  *  0b1101..Bit clock D
5723  *  0b1110..Bit clock E
5724  *  0b1111..Clock disabled, connected to zero
5725  */
5726 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
5727 
5728 #define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
5729 #define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
5730 /*! AICSC - Input Clock Source C
5731  *  0b0000..Bit clock 0
5732  *  0b0001..Bit clock 1
5733  *  0b0010..Bit clock 2
5734  *  0b0011..Bit clock 3
5735  *  0b0100..Bit clock 4
5736  *  0b0101..Bit clock 5
5737  *  0b0110..Bit clock 6
5738  *  0b0111..Bit clock 7
5739  *  0b1000..Bit clock 8
5740  *  0b1001..Bit clock 9
5741  *  0b1010..Bit clock A
5742  *  0b1011..Bit clock B
5743  *  0b1100..Bit clock C
5744  *  0b1101..Bit clock D
5745  *  0b1110..Bit clock E
5746  *  0b1111..Clock disabled, connected to zero
5747  */
5748 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
5749 
5750 #define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
5751 #define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
5752 /*! AOCSA - Output Clock Source A
5753  *  0b0000..Bit clock 0
5754  *  0b0001..Bit clock 1
5755  *  0b0010..Bit clock 2
5756  *  0b0011..Bit clock 3
5757  *  0b0100..Bit clock 4
5758  *  0b0101..Bit clock 5
5759  *  0b0110..Bit clock 6
5760  *  0b0111..Bit clock 7
5761  *  0b1000..Bit clock 8
5762  *  0b1001..Bit clock 9
5763  *  0b1010..Bit clock A
5764  *  0b1011..Bit clock B
5765  *  0b1100..Bit clock C
5766  *  0b1101..Bit clock D
5767  *  0b1110..Bit clock E
5768  *  0b1111..Clock disabled, connected to zero
5769  */
5770 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
5771 
5772 #define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
5773 #define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
5774 /*! AOCSB - Output Clock Source B
5775  *  0b0000..Bit clock 0
5776  *  0b0001..Bit clock 1
5777  *  0b0010..Bit clock 2
5778  *  0b0011..Bit clock 3
5779  *  0b0100..Bit clock 4
5780  *  0b0101..Bit clock 5
5781  *  0b0110..Bit clock 6
5782  *  0b0111..Bit clock 7
5783  *  0b1000..Bit clock 8
5784  *  0b1001..Bit clock 9
5785  *  0b1010..Bit clock A
5786  *  0b1011..Bit clock B
5787  *  0b1100..Bit clock C
5788  *  0b1101..Bit clock D
5789  *  0b1110..Bit clock E
5790  *  0b1111..Clock disabled, connected to zero
5791  */
5792 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
5793 
5794 #define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
5795 #define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
5796 /*! AOCSC - Output Clock Source C
5797  *  0b0000..Bit clock 0
5798  *  0b0001..Bit clock 1
5799  *  0b0010..Bit clock 2
5800  *  0b0011..Bit clock 3
5801  *  0b0100..Bit clock 4
5802  *  0b0101..Bit clock 5
5803  *  0b0110..Bit clock 6
5804  *  0b0111..Bit clock 7
5805  *  0b1000..Bit clock 8
5806  *  0b1001..Bit clock 9
5807  *  0b1010..Bit clock A
5808  *  0b1011..Bit clock B
5809  *  0b1100..Bit clock C
5810  *  0b1101..Bit clock D
5811  *  0b1110..Bit clock E
5812  *  0b1111..Clock disabled, connected to zero
5813  */
5814 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
5815 /*! @} */
5816 
5817 /*! @name ASRCDR1 - ASRC Clock Divider 1 */
5818 /*! @{ */
5819 
5820 #define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
5821 #define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
5822 /*! AICPA - Input Clock Prescaler A */
5823 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
5824 
5825 #define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
5826 #define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
5827 /*! AICDA - Input Clock Divider A */
5828 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
5829 
5830 #define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
5831 #define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
5832 /*! AICPB - Input Clock Prescaler B */
5833 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
5834 
5835 #define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
5836 #define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
5837 /*! AICDB - Input Clock Divider B */
5838 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
5839 
5840 #define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
5841 #define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
5842 /*! AOCPA - Output Clock Prescaler A */
5843 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
5844 
5845 #define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
5846 #define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
5847 /*! AOCDA - Output Clock Divider A */
5848 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
5849 
5850 #define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
5851 #define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
5852 /*! AOCPB - Output Clock Prescaler B */
5853 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
5854 
5855 #define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
5856 #define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
5857 /*! AOCDB - Output Clock Divider B */
5858 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
5859 /*! @} */
5860 
5861 /*! @name ASRCDR2 - ASRC Clock Divider 2 */
5862 /*! @{ */
5863 
5864 #define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
5865 #define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
5866 /*! AICPC - Input Clock Prescaler C */
5867 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
5868 
5869 #define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
5870 #define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
5871 /*! AICDC - Input Clock Divider C */
5872 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
5873 
5874 #define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
5875 #define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
5876 /*! AOCPC - Output Clock Prescaler C */
5877 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
5878 
5879 #define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
5880 #define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
5881 /*! AOCDC - Output Clock Divider C */
5882 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
5883 /*! @} */
5884 
5885 /*! @name ASRSTR - ASRC Status */
5886 /*! @{ */
5887 
5888 #define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
5889 #define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
5890 /*! AIDEA - Number of Data in Input Data Buffer A is Less than Threshold
5891  *  0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1
5892  *  0b0..The threshold has been met and no data input A interrupt is generated
5893  */
5894 #define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
5895 
5896 #define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
5897 #define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
5898 /*! AIDEB - Number of Data in Input Data Buffer B is Less than Threshold
5899  *  0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1
5900  *  0b0..The threshold has been met and no data input B interrupt is generated
5901  */
5902 #define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
5903 
5904 #define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
5905 #define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
5906 /*! AIDEC - Number of Data in Input Data Buffer C is Less than Threshold
5907  *  0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1
5908  *  0b0..The threshold has been met and no data input C interrupt is generated
5909  */
5910 #define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
5911 
5912 #define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
5913 #define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
5914 /*! AODFA - Number of Data in Output Data Buffer A is Greater than Threshold
5915  *  0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1
5916  *  0b0..The threshold has not yet been met and no data output A interrupt is generated
5917  */
5918 #define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
5919 
5920 #define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
5921 #define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
5922 /*! AODFB - Number of data in Output Data Buffer B is Greater than Threshold
5923  *  0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1
5924  *  0b0..The threshold has not yet been met and no data output B interrupt is generated
5925  */
5926 #define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
5927 
5928 #define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
5929 #define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
5930 /*! AODFC - Number of data in Output Data Buffer C is Greater than Threshold
5931  *  0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1
5932  *  0b0..The threshold has not yet been met and no data output C interrupt is generated
5933  */
5934 #define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
5935 
5936 #define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
5937 #define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
5938 /*! AOLE - Overload Error Flag
5939  *  0b1..Task rate is too high
5940  *  0b0..No overload
5941  */
5942 #define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
5943 
5944 #define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
5945 #define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
5946 /*! FPWT - FP is in Wait States
5947  *  0b0..ASRC is not in wait state
5948  *  0b1..ASRC is in wait state
5949  */
5950 #define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
5951 
5952 #define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
5953 #define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
5954 /*! AIDUA - Input Data Buffer A has Underflowed
5955  *  0b0..No Underflow in Input data buffer A
5956  *  0b1..Underflow in Input data buffer A
5957  */
5958 #define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
5959 
5960 #define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
5961 #define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
5962 /*! AIDUB - Input Data Buffer B has Underflowed
5963  *  0b0..No Underflow in Input data buffer B
5964  *  0b1..Underflow in Input data buffer B
5965  */
5966 #define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
5967 
5968 #define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
5969 #define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
5970 /*! AIDUC - Input Data Buffer C has Underflowed
5971  *  0b0..No Underflow in Input data buffer C
5972  *  0b1..Underflow in Input data buffer C
5973  */
5974 #define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
5975 
5976 #define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
5977 #define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
5978 /*! AODOA - Output Data Buffer A has Overflowed
5979  *  0b0..No Overflow in Output data buffer A
5980  *  0b1..Overflow in Output data buffer A
5981  */
5982 #define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
5983 
5984 #define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
5985 #define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
5986 /*! AODOB - Output Data Buffer B has Overflowed
5987  *  0b0..No Overflow in Output data buffer B
5988  *  0b1..Overflow in Output data buffer B
5989  */
5990 #define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
5991 
5992 #define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
5993 #define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
5994 /*! AODOC - Output Data Buffer C has Overflowed
5995  *  0b0..No Overflow in Output data buffer C
5996  *  0b1..Overflow in Output data buffer C
5997  */
5998 #define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
5999 
6000 #define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
6001 #define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
6002 /*! AIOLA - Pair A Input Task Overload
6003  *  0b0..Pair A input task is not overloaded
6004  *  0b1..Pair A input task is overloaded
6005  */
6006 #define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
6007 
6008 #define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
6009 #define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
6010 /*! AIOLB - Pair B Input Task Overload
6011  *  0b0..Pair B input task is not overloaded
6012  *  0b1..Pair B input task is overloaded
6013  */
6014 #define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
6015 
6016 #define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
6017 #define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
6018 /*! AIOLC - Pair C Input Task Overload
6019  *  0b0..Pair C input task is not overloaded
6020  *  0b1..Pair C input task is overloaded
6021  */
6022 #define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
6023 
6024 #define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
6025 #define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
6026 /*! AOOLA - Pair A Output Task Overload
6027  *  0b0..Pair A output task is not overloaded
6028  *  0b1..Pair A output task is overloaded
6029  */
6030 #define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
6031 
6032 #define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
6033 #define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
6034 /*! AOOLB - Pair B Output Task Overload
6035  *  0b0..Pair B output task is not overloaded
6036  *  0b1..Pair B output task is overloaded
6037  */
6038 #define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
6039 
6040 #define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
6041 #define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
6042 /*! AOOLC - Pair C Output Task Overload
6043  *  0b0..Pair C output task is not overloaded
6044  *  0b1..Pair C output task is overloaded
6045  */
6046 #define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
6047 
6048 #define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
6049 #define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
6050 /*! ATQOL - Task Queue FIFO overload
6051  *  0b0..Task queue FIFO logic is not overloaded
6052  *  0b1..Task queue FIFO logic is overloaded
6053  */
6054 #define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
6055 
6056 #define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
6057 #define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
6058 /*! DSLCNT - Digital Servo Loop (DSL) Counter Input to FIFO Ready
6059  *  0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO
6060  *  0b1..New DSL counter information is stored in the internal ASRC FIFO
6061  */
6062 #define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
6063 /*! @} */
6064 
6065 /*! @name ASRPM - ASRC Parameter x */
6066 /*! @{ */
6067 
6068 #define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
6069 #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
6070 /*! PARAMETER_VALUE - Parameter Value */
6071 #define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
6072 /*! @} */
6073 
6074 /* The count of ASRC_ASRPM */
6075 #define ASRC_ASRPM_COUNT                         (5U)
6076 
6077 /*! @name ASRTFR1 - ASRC Task Queue FIFO 1 */
6078 /*! @{ */
6079 
6080 #define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
6081 #define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
6082 /*! TF_BASE - Base Address for Task Queue FIFO */
6083 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
6084 
6085 #define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
6086 #define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
6087 /*! TF_FILL - Current Number of Entries in Task Queue FIFO */
6088 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
6089 /*! @} */
6090 
6091 /*! @name ASRCCR - ASRC Channel Counter */
6092 /*! @{ */
6093 
6094 #define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
6095 #define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
6096 /*! ACIA - Channel Counter for Pair A's Input FIFO */
6097 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
6098 
6099 #define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
6100 #define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
6101 /*! ACIB - Channel Counter for Pair B's Input FIFO */
6102 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
6103 
6104 #define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
6105 #define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
6106 /*! ACIC - Channel Counter for Pair C's Input FIFO */
6107 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
6108 
6109 #define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
6110 #define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
6111 /*! ACOA - Channel Counter for Pair A's Output FIFO */
6112 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
6113 
6114 #define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
6115 #define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
6116 /*! ACOB - Channel Counter for Pair B's Output FIFO */
6117 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
6118 
6119 #define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
6120 #define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
6121 /*! ACOC - Channel Counter for Pair C's Output FIFO */
6122 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
6123 /*! @} */
6124 
6125 /*! @name ASRDIA - ASRC Data Input for Pair x */
6126 /*! @{ */
6127 
6128 #define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
6129 #define ASRC_ASRDIA_DATA_SHIFT                   (0U)
6130 /*! DATA - Data */
6131 #define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
6132 /*! @} */
6133 
6134 /*! @name ASRDOA - ASRC Data Output for Pair x */
6135 /*! @{ */
6136 
6137 #define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
6138 #define ASRC_ASRDOA_DATA_SHIFT                   (0U)
6139 /*! DATA - Data */
6140 #define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
6141 /*! @} */
6142 
6143 /*! @name ASRDIB - ASRC Data Input for Pair x */
6144 /*! @{ */
6145 
6146 #define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
6147 #define ASRC_ASRDIB_DATA_SHIFT                   (0U)
6148 /*! DATA - Data */
6149 #define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
6150 /*! @} */
6151 
6152 /*! @name ASRDOB - ASRC Data Output for Pair x */
6153 /*! @{ */
6154 
6155 #define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
6156 #define ASRC_ASRDOB_DATA_SHIFT                   (0U)
6157 /*! DATA - Data */
6158 #define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
6159 /*! @} */
6160 
6161 /*! @name ASRDIC - ASRC Data Input for Pair x */
6162 /*! @{ */
6163 
6164 #define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
6165 #define ASRC_ASRDIC_DATA_SHIFT                   (0U)
6166 /*! DATA - Data */
6167 #define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
6168 /*! @} */
6169 
6170 /*! @name ASRDOC - ASRC Data Output for Pair x */
6171 /*! @{ */
6172 
6173 #define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
6174 #define ASRC_ASRDOC_DATA_SHIFT                   (0U)
6175 /*! DATA - Data */
6176 #define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
6177 /*! @} */
6178 
6179 /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
6180 /*! @{ */
6181 
6182 #define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
6183 #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
6184 /*! IDRATIOA_H - Ideal Ratio A High */
6185 #define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
6186 /*! @} */
6187 
6188 /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
6189 /*! @{ */
6190 
6191 #define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
6192 #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
6193 /*! IDRATIOA_L - Ideal Ratio A Low */
6194 #define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
6195 /*! @} */
6196 
6197 /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
6198 /*! @{ */
6199 
6200 #define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
6201 #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
6202 /*! IDRATIOB_H - Ideal Ratio B High */
6203 #define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
6204 /*! @} */
6205 
6206 /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
6207 /*! @{ */
6208 
6209 #define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
6210 #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
6211 /*! IDRATIOB_L - Ideal Ratio B Low */
6212 #define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
6213 /*! @} */
6214 
6215 /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
6216 /*! @{ */
6217 
6218 #define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
6219 #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
6220 /*! IDRATIOC_H - Ideal Ratio C High */
6221 #define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
6222 /*! @} */
6223 
6224 /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
6225 /*! @{ */
6226 
6227 #define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
6228 #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
6229 /*! IDRATIOC_L - Ideal Ratio C Low */
6230 #define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
6231 /*! @} */
6232 
6233 /*! @name ASR76K - ASRC 76 kHz Period */
6234 /*! @{ */
6235 
6236 #define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
6237 #define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
6238 /*! ASR76K - Value for the Period of the 76 kHz Sampling Clock */
6239 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
6240 /*! @} */
6241 
6242 /*! @name ASR56K - ASRC 56 kHz Period */
6243 /*! @{ */
6244 
6245 #define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
6246 #define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
6247 /*! ASR56K - Value for the Period of the 56 kHz Sampling Clock */
6248 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
6249 /*! @} */
6250 
6251 /*! @name ASRMCRA - ASRC Misc Control for Pair A */
6252 /*! @{ */
6253 
6254 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
6255 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
6256 /*! INFIFO_THRESHOLDA - Threshold for Pair A's Input FIFO per Channel */
6257 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
6258 
6259 #define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
6260 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
6261 /*! RSYNOFA - Re-sync Output FIFO Channel Counter
6262  *  0b1..Force ASRCCR[ACOA]=0
6263  *  0b0..Do not touch ASRCCR[ACOA]
6264  */
6265 #define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
6266 
6267 #define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
6268 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
6269 /*! RSYNIFA - Re-sync Input FIFO Channel Counter
6270  *  0b1..Force ASRCCR[ACIA]=0
6271  *  0b0..Do not touch ASRCCR[ACIA]
6272  */
6273 #define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
6274 
6275 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
6276 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
6277 /*! OUTFIFO_THRESHOLDA - Threshold for Pair A's Output FIFO per Channel */
6278 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
6279 
6280 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
6281 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
6282 /*! BYPASSPOLYA - Bypass Polyphase Filtering for Pair A
6283  *  0b1..Bypass polyphase filtering.
6284  *  0b0..Don't bypass polyphase filtering.
6285  */
6286 #define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
6287 
6288 #define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
6289 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
6290 /*! BUFSTALLA - Stall Pair A Conversion in Case of Buffer Near Empty/Full Condition
6291  *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
6292  *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
6293  */
6294 #define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
6295 
6296 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
6297 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
6298 /*! EXTTHRSHA - Use External Thresholds for FIFO Control of Pair A
6299  *  0b1..Use external defined thresholds.
6300  *  0b0..Use default thresholds.
6301  */
6302 #define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
6303 
6304 #define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
6305 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
6306 /*! ZEROBUFA - Zero Buffer A
6307  *  0b1..Don't zeroize the buffer
6308  *  0b0..Zeroize the buffer
6309  */
6310 #define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
6311 /*! @} */
6312 
6313 /*! @name ASRFSTA - ASRC FIFO Status for Pair A */
6314 /*! @{ */
6315 
6316 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
6317 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
6318 /*! INFIFO_FILLA - Fillings for Pair A's Input FIFO per Channel */
6319 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
6320 
6321 #define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
6322 #define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
6323 /*! IAEA - Input FIFO is Near Empty for Pair A
6324  *  0b1..Input FIFO is near empty for Pair A
6325  *  0b0..Input FIFO is not near empty for Pair A
6326  */
6327 #define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
6328 
6329 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
6330 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
6331 /*! OUTFIFO_FILLA - Fillings for Pair A's Output FIFO per Channel */
6332 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
6333 
6334 #define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
6335 #define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
6336 /*! OAFA - Output FIFO is Near Full for Pair A
6337  *  0b1..Output FIFO is near full for Pair A
6338  *  0b0..Output FIFO is not near full for Pair A
6339  */
6340 #define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
6341 /*! @} */
6342 
6343 /*! @name ASRMCRB - ASRC Misc Control for Pair B */
6344 /*! @{ */
6345 
6346 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
6347 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
6348 /*! INFIFO_THRESHOLDB - Threshold for Pair B's Input FIFO per Channel */
6349 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
6350 
6351 #define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
6352 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
6353 /*! RSYNOFB - Re-sync Output FIFO Channel Counter
6354  *  0b1..Force ASRCCR[ACOB]=0
6355  *  0b0..Do not touch ASRCCR[ACOB]
6356  */
6357 #define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
6358 
6359 #define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
6360 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
6361 /*! RSYNIFB - Re-sync Input FIFO Channel Counter
6362  *  0b1..Force ASRCCR[ACIB]=0
6363  *  0b0..Do not touch ASRCCR[ACIB]
6364  */
6365 #define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
6366 
6367 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
6368 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
6369 /*! OUTFIFO_THRESHOLDB - Threshold for Pair B's Output FIFO per Channel */
6370 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
6371 
6372 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
6373 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
6374 /*! BYPASSPOLYB - Bypass Polyphase Filtering for Pair B
6375  *  0b1..Bypass polyphase filtering.
6376  *  0b0..Don't bypass polyphase filtering.
6377  */
6378 #define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
6379 
6380 #define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
6381 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
6382 /*! BUFSTALLB - Stall Pair B Conversion in Case of Buffer Near Empty/Full Condition
6383  *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
6384  *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
6385  */
6386 #define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
6387 
6388 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
6389 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
6390 /*! EXTTHRSHB - Use External Thresholds for FIFO Control of Pair B
6391  *  0b1..Use external defined thresholds.
6392  *  0b0..Use default thresholds.
6393  */
6394 #define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
6395 
6396 #define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
6397 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
6398 /*! ZEROBUFB - Zero Buffer B
6399  *  0b1..Don't zeroize the buffer
6400  *  0b0..Zeroize the buffer
6401  */
6402 #define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
6403 /*! @} */
6404 
6405 /*! @name ASRFSTB - ASRC FIFO Status for Pair B */
6406 /*! @{ */
6407 
6408 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
6409 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
6410 /*! INFIFO_FILLB - Fillings for Pair B's Input FIFO per Channel */
6411 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
6412 
6413 #define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
6414 #define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
6415 /*! IAEB - Input FIFO is Near Empty for Pair B
6416  *  0b1..Input FIFO is near empty for Pair B
6417  *  0b0..Input FIFO is not near empty for Pair B
6418  */
6419 #define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
6420 
6421 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
6422 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
6423 /*! OUTFIFO_FILLB - Fillings for Pair B's Output FIFO per Channel */
6424 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
6425 
6426 #define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
6427 #define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
6428 /*! OAFB - Output FIFO is Near Full for Pair B
6429  *  0b1..Output FIFO is near full for Pair B
6430  *  0b0..Output FIFO is not near full for Pair B
6431  */
6432 #define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
6433 /*! @} */
6434 
6435 /*! @name ASRMCRC - ASRC Misc Control for Pair C */
6436 /*! @{ */
6437 
6438 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
6439 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
6440 /*! INFIFO_THRESHOLDC - Threshold for Pair C's Input FIFO per Channel */
6441 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
6442 
6443 #define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
6444 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
6445 /*! RSYNOFC - Re-sync Output FIFO Channel Counter
6446  *  0b1..Force ASRCCR[ACOC]=0
6447  *  0b0..Do not touch ASRCCR[ACOC]
6448  */
6449 #define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
6450 
6451 #define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
6452 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
6453 /*! RSYNIFC - Re-sync Input FIFO Channel Counter
6454  *  0b1..Force ASRCCR[ACIC]=0
6455  *  0b0..Do not touch ASRCCR[ACIC]
6456  */
6457 #define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
6458 
6459 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
6460 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
6461 /*! OUTFIFO_THRESHOLDC - Threshold for Pair C's Output FIFO per Channel */
6462 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
6463 
6464 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
6465 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
6466 /*! BYPASSPOLYC - Bypass Polyphase Filtering for Pair C
6467  *  0b1..Bypass polyphase filtering.
6468  *  0b0..Don't bypass polyphase filtering.
6469  */
6470 #define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
6471 
6472 #define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
6473 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
6474 /*! BUFSTALLC - Stall Pair C Conversion in Case of Buffer Near Empty/Full Condition
6475  *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
6476  *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
6477  */
6478 #define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
6479 
6480 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
6481 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
6482 /*! EXTTHRSHC - Use External Thresholds for FIFO Control of Pair C
6483  *  0b1..Use external defined thresholds.
6484  *  0b0..Use default thresholds.
6485  */
6486 #define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
6487 
6488 #define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
6489 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
6490 /*! ZEROBUFC - Zero Buffer C
6491  *  0b1..Don't zeroize the buffer
6492  *  0b0..Zeroize the buffer
6493  */
6494 #define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
6495 /*! @} */
6496 
6497 /*! @name ASRFSTC - ASRC FIFO Status for Pair C */
6498 /*! @{ */
6499 
6500 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
6501 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
6502 /*! INFIFO_FILLC - Fillings for Pair C's Input FIFO per Channel */
6503 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
6504 
6505 #define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
6506 #define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
6507 /*! IAEC - Input FIFO is Near Empty for Pair C
6508  *  0b1..Input FIFO is near empty for Pair C
6509  *  0b0..Input FIFO is not near empty for Pair C
6510  */
6511 #define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
6512 
6513 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
6514 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
6515 /*! OUTFIFO_FILLC - Fillings for Pair C's Output FIFO per Channel */
6516 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
6517 
6518 #define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
6519 #define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
6520 /*! OAFC - Output FIFO is Near Full for Pair C
6521  *  0b1..Output FIFO is near full for Pair C
6522  *  0b0..Output FIFO is not near full for Pair C
6523  */
6524 #define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
6525 /*! @} */
6526 
6527 /*! @name ASRMCR1 - ASRC Misc Control 1 for Pair X */
6528 /*! @{ */
6529 
6530 #define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
6531 #define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
6532 /*! OW16 - Bit Width Option of the Output FIFO
6533  *  0b1..16-bit output data
6534  *  0b0..24-bit output data
6535  */
6536 #define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
6537 
6538 #define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
6539 #define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
6540 /*! OSGN - Sign Extension Option of the Output FIFO
6541  *  0b1..Sign extension
6542  *  0b0..No sign extension
6543  */
6544 #define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
6545 
6546 #define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
6547 #define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
6548 /*! OMSB - Data Alignment of the Output FIFO
6549  *  0b1..MSB aligned
6550  *  0b0..LSB aligned
6551  */
6552 #define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
6553 
6554 #define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
6555 #define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
6556 /*! IMSB - Data Alignment of the Input FIFO
6557  *  0b1..MSB aligned
6558  *  0b0..LSB aligned
6559  */
6560 #define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
6561 
6562 #define ASRC_ASRMCR1_IWD_MASK                    (0x600U)
6563 #define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
6564 /*! IWD - Data Width of the Input FIFO
6565  *  0b00..24-bit audio data.
6566  *  0b01..16-bit audio data.
6567  *  0b10..8-bit audio data.
6568  *  0b11..Reserved.
6569  */
6570 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
6571 /*! @} */
6572 
6573 /* The count of ASRC_ASRMCR1 */
6574 #define ASRC_ASRMCR1_COUNT                       (3U)
6575 
6576 
6577 /*!
6578  * @}
6579  */ /* end of group ASRC_Register_Masks */
6580 
6581 
6582 /* ASRC - Peripheral instance base addresses */
6583 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
6584   /** Peripheral ASRC base address */
6585   #define ASRC_BASE                                (0x529A0000u)
6586   /** Peripheral ASRC base address */
6587   #define ASRC_BASE_NS                             (0x429A0000u)
6588   /** Peripheral ASRC base pointer */
6589   #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
6590   /** Peripheral ASRC base pointer */
6591   #define ASRC_NS                                  ((ASRC_Type *)ASRC_BASE_NS)
6592   /** Array initializer of ASRC peripheral base addresses */
6593   #define ASRC_BASE_ADDRS                          { ASRC_BASE }
6594   /** Array initializer of ASRC peripheral base pointers */
6595   #define ASRC_BASE_PTRS                           { ASRC }
6596   /** Array initializer of ASRC peripheral base addresses */
6597   #define ASRC_BASE_ADDRS_NS                       { ASRC_BASE_NS }
6598   /** Array initializer of ASRC peripheral base pointers */
6599   #define ASRC_BASE_PTRS_NS                        { ASRC_NS }
6600 #else
6601   /** Peripheral ASRC base address */
6602   #define ASRC_BASE                                (0x429A0000u)
6603   /** Peripheral ASRC base pointer */
6604   #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
6605   /** Array initializer of ASRC peripheral base addresses */
6606   #define ASRC_BASE_ADDRS                          { ASRC_BASE }
6607   /** Array initializer of ASRC peripheral base pointers */
6608   #define ASRC_BASE_PTRS                           { ASRC }
6609 #endif
6610 /** Interrupt vectors for the ASRC peripheral type */
6611 #define ASRC_IRQS                                { ASRC_IRQn }
6612 
6613 /*!
6614  * @}
6615  */ /* end of group ASRC_Peripheral_Access_Layer */
6616 
6617 
6618 /* ----------------------------------------------------------------------------
6619    -- AXBS Peripheral Access Layer
6620    ---------------------------------------------------------------------------- */
6621 
6622 /*!
6623  * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
6624  * @{
6625  */
6626 
6627 /** AXBS - Register Layout Typedef */
6628 typedef struct {
6629   struct {                                         /* offset: 0x0, array step: 0x100 */
6630     __IO uint32_t PRS;                               /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */
6631          uint8_t RESERVED_0[12];
6632     __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
6633          uint8_t RESERVED_1[236];
6634   } SLAVE[8];
6635 } AXBS_Type;
6636 
6637 /* ----------------------------------------------------------------------------
6638    -- AXBS Register Masks
6639    ---------------------------------------------------------------------------- */
6640 
6641 /*!
6642  * @addtogroup AXBS_Register_Masks AXBS Register Masks
6643  * @{
6644  */
6645 
6646 /*! @name PRS - Priority Slave Registers */
6647 /*! @{ */
6648 
6649 #define AXBS_PRS_M0_MASK                         (0x7U)
6650 #define AXBS_PRS_M0_SHIFT                        (0U)
6651 /*! M0 - Master 0 Priority
6652  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6653  *  0b001..This master has level 2 priority when accessing the slave port.
6654  *  0b010..This master has level 3 priority when accessing the slave port.
6655  *  0b011..This master has level 4 priority when accessing the slave port.
6656  *  0b100..This master has level 5 priority when accessing the slave port.
6657  *  0b101..This master has level 6 priority when accessing the slave port.
6658  *  0b110..This master has level 7 priority when accessing the slave port.
6659  *  0b111..This master has level 8 or the lowest priority when accessing the slave port.
6660  */
6661 #define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
6662 
6663 #define AXBS_PRS_M1_MASK                         (0x70U)
6664 #define AXBS_PRS_M1_SHIFT                        (4U)
6665 /*! M1 - Master 1 Priority
6666  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6667  *  0b001..This master has level 2 priority when accessing the slave port.
6668  *  0b010..This master has level 3 priority when accessing the slave port.
6669  *  0b011..This master has level 4 priority when accessing the slave port.
6670  *  0b100..This master has level 5 priority when accessing the slave port.
6671  *  0b101..This master has level 6 priority when accessing the slave port.
6672  *  0b110..This master has level 7 priority when accessing the slave port.
6673  *  0b111..This master has level 8 or lowest priority when accessing the slave port.
6674  */
6675 #define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
6676 
6677 #define AXBS_PRS_M2_MASK                         (0x700U)
6678 #define AXBS_PRS_M2_SHIFT                        (8U)
6679 /*! M2 - Master 2 Priority
6680  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6681  *  0b001..This master has level 2 priority when accessing the slave port.
6682  *  0b010..This master has level 3 priority when accessing the slave port.
6683  *  0b011..This master has level 4 priority when accessing the slave port.
6684  *  0b100..This master has level 5 priority when accessing the slave port.
6685  *  0b101..This master has level 6 priority when accessing the slave port.
6686  *  0b110..This master has level 7 priority when accessing the slave port.
6687  *  0b111..This master has level 8the or lowest priority when accessing the slave port.
6688  */
6689 #define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
6690 
6691 #define AXBS_PRS_M3_MASK                         (0x7000U)
6692 #define AXBS_PRS_M3_SHIFT                        (12U)
6693 /*! M3 - Master 3 Priority
6694  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6695  *  0b001..This master has level 2 priority when accessing the slave port.
6696  *  0b010..This master has level 3 priority when accessing the slave port.
6697  *  0b011..This master has level 4 priority when accessing the slave port.
6698  *  0b100..This master has level 5 priority when accessing the slave port.
6699  *  0b101..This master has level 6 priority when accessing the slave port.
6700  *  0b110..This master has level 7 priority when accessing the slave port.
6701  *  0b111..This master has level 8the or lowest priority when accessing the slave port.
6702  */
6703 #define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
6704 
6705 #define AXBS_PRS_M4_MASK                         (0x70000U)
6706 #define AXBS_PRS_M4_SHIFT                        (16U)
6707 /*! M4 - Master 4 Priority
6708  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6709  *  0b001..This master has level 2 priority when accessing the slave port.
6710  *  0b010..This master has level 3 priority when accessing the slave port.
6711  *  0b011..This master has level 4 priority when accessing the slave port.
6712  *  0b100..This master has level 5 priority when accessing the slave port.
6713  *  0b101..This master has level 6 priority when accessing the slave port.
6714  *  0b110..This master has level 7 priority when accessing the slave port.
6715  *  0b111..This master has level 8 or lowest priority when accessing the slave port.
6716  */
6717 #define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
6718 
6719 #define AXBS_PRS_M5_MASK                         (0x700000U)
6720 #define AXBS_PRS_M5_SHIFT                        (20U)
6721 /*! M5 - Master 5 Priority
6722  *  0b000..This master has level 1 or highest priority when accessing the slave port.
6723  *  0b001..This master has level 2 priority when accessing the slave port.
6724  *  0b010..This master has level 3 priority when accessing the slave port.
6725  *  0b011..This master has level 4 priority when accessing the slave port.
6726  *  0b100..This master has level 5 priority when accessing the slave port.
6727  *  0b101..This master has level 6 priority when accessing the slave port.
6728  *  0b110..This master has level 7 priority when accessing the slave port.
6729  *  0b111..This master has level 8 or lowest priority when accessing the slave port.
6730  */
6731 #define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
6732 /*! @} */
6733 
6734 /* The count of AXBS_PRS */
6735 #define AXBS_PRS_COUNT                           (8U)
6736 
6737 /*! @name CRS - Control Register */
6738 /*! @{ */
6739 
6740 #define AXBS_CRS_PARK_MASK                       (0x7U)
6741 #define AXBS_CRS_PARK_SHIFT                      (0U)
6742 /*! PARK - Park
6743  *  0b000..Park on master port M0
6744  *  0b001..Park on master port M1
6745  *  0b010..Park on master port M2
6746  *  0b011..Park on master port M3
6747  *  0b100..Park on master port M4
6748  *  0b101..Park on master port M5
6749  *  0b110..Park on master port M6
6750  *  0b111..Park on master port M7
6751  */
6752 #define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
6753 
6754 #define AXBS_CRS_PCTL_MASK                       (0x30U)
6755 #define AXBS_CRS_PCTL_SHIFT                      (4U)
6756 /*! PCTL - Parking Control
6757  *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field.
6758  *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
6759  *  0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter
6760  *        drives all outputs to a constant safe state.
6761  *  0b11..Reserved
6762  */
6763 #define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
6764 
6765 #define AXBS_CRS_ARB_MASK                        (0x300U)
6766 #define AXBS_CRS_ARB_SHIFT                       (8U)
6767 /*! ARB - Arbitration Mode
6768  *  0b00..Fixed priority
6769  *  0b01..Round-robin (rotating) priority
6770  *  0b10..Reserved
6771  *  0b11..Reserved
6772  */
6773 #define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
6774 
6775 #define AXBS_CRS_HPE0_MASK                       (0x10000U)
6776 #define AXBS_CRS_HPE0_SHIFT                      (16U)
6777 /*! HPE0 - High Priority Elevation 0
6778  *  0b0..Master high-priority elevation for master 0. is disabled on this slave port.
6779  *  0b1..Master high-priority elevation for master 0. is enabled on this slave port.
6780  */
6781 #define AXBS_CRS_HPE0(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE0_SHIFT)) & AXBS_CRS_HPE0_MASK)
6782 
6783 #define AXBS_CRS_HPE1_MASK                       (0x20000U)
6784 #define AXBS_CRS_HPE1_SHIFT                      (17U)
6785 /*! HPE1 - High Priority Elevation 1
6786  *  0b0..Master high-priority elevation for master 1. is disabled on this slave port.
6787  *  0b1..Master high-priority elevation for master 1. is enabled on this slave port.
6788  */
6789 #define AXBS_CRS_HPE1(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE1_SHIFT)) & AXBS_CRS_HPE1_MASK)
6790 
6791 #define AXBS_CRS_HPE2_MASK                       (0x40000U)
6792 #define AXBS_CRS_HPE2_SHIFT                      (18U)
6793 /*! HPE2 - High Priority Elevation 2
6794  *  0b0..Master high-priority elevation for master 2. is disabled on this slave port.
6795  *  0b1..Master high-priority elevation for master 2. is enabled on this slave port.
6796  */
6797 #define AXBS_CRS_HPE2(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE2_SHIFT)) & AXBS_CRS_HPE2_MASK)
6798 
6799 #define AXBS_CRS_HPE3_MASK                       (0x80000U)
6800 #define AXBS_CRS_HPE3_SHIFT                      (19U)
6801 /*! HPE3 - High Priority Elevation 3
6802  *  0b0..Master high-priority elevation for master 3. is disabled on this slave port.
6803  *  0b1..Master high-priority elevation for master 3. is enabled on this slave port.
6804  */
6805 #define AXBS_CRS_HPE3(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE3_SHIFT)) & AXBS_CRS_HPE3_MASK)
6806 
6807 #define AXBS_CRS_HPE4_MASK                       (0x100000U)
6808 #define AXBS_CRS_HPE4_SHIFT                      (20U)
6809 /*! HPE4 - High Priority Elevation 4
6810  *  0b0..Master high-priority elevation for master 4. is disabled on this slave port.
6811  *  0b1..Master high-priority elevation for master 4. is enabled on this slave port.
6812  */
6813 #define AXBS_CRS_HPE4(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE4_SHIFT)) & AXBS_CRS_HPE4_MASK)
6814 
6815 #define AXBS_CRS_HPE5_MASK                       (0x200000U)
6816 #define AXBS_CRS_HPE5_SHIFT                      (21U)
6817 /*! HPE5 - High Priority Elevation 5
6818  *  0b0..Master high-priority elevation for master 5. is disabled on this slave port.
6819  *  0b1..Master high-priority elevation for master 5. is enabled on this slave port.
6820  */
6821 #define AXBS_CRS_HPE5(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE5_SHIFT)) & AXBS_CRS_HPE5_MASK)
6822 
6823 #define AXBS_CRS_RO_MASK                         (0x80000000U)
6824 #define AXBS_CRS_RO_SHIFT                        (31U)
6825 /*! RO - Read Only
6826  *  0b0..The CRSn and PRSn registers are writeable
6827  *  0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the
6828  *       registers and result in a bus error response).
6829  */
6830 #define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
6831 /*! @} */
6832 
6833 /* The count of AXBS_CRS */
6834 #define AXBS_CRS_COUNT                           (8U)
6835 
6836 
6837 /*!
6838  * @}
6839  */ /* end of group AXBS_Register_Masks */
6840 
6841 
6842 /* AXBS - Peripheral instance base addresses */
6843 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
6844   /** Peripheral AXBS base address */
6845   #define AXBS_BASE                                (0x54510000u)
6846   /** Peripheral AXBS base address */
6847   #define AXBS_BASE_NS                             (0x44510000u)
6848   /** Peripheral AXBS base pointer */
6849   #define AXBS                                     ((AXBS_Type *)AXBS_BASE)
6850   /** Peripheral AXBS base pointer */
6851   #define AXBS_NS                                  ((AXBS_Type *)AXBS_BASE_NS)
6852   /** Array initializer of AXBS peripheral base addresses */
6853   #define AXBS_BASE_ADDRS                          { AXBS_BASE }
6854   /** Array initializer of AXBS peripheral base pointers */
6855   #define AXBS_BASE_PTRS                           { AXBS }
6856   /** Array initializer of AXBS peripheral base addresses */
6857   #define AXBS_BASE_ADDRS_NS                       { AXBS_BASE_NS }
6858   /** Array initializer of AXBS peripheral base pointers */
6859   #define AXBS_BASE_PTRS_NS                        { AXBS_NS }
6860 #else
6861   /** Peripheral AXBS base address */
6862   #define AXBS_BASE                                (0x44510000u)
6863   /** Peripheral AXBS base pointer */
6864   #define AXBS                                     ((AXBS_Type *)AXBS_BASE)
6865   /** Array initializer of AXBS peripheral base addresses */
6866   #define AXBS_BASE_ADDRS                          { AXBS_BASE }
6867   /** Array initializer of AXBS peripheral base pointers */
6868   #define AXBS_BASE_PTRS                           { AXBS }
6869 #endif
6870 
6871 /*!
6872  * @}
6873  */ /* end of group AXBS_Peripheral_Access_Layer */
6874 
6875 
6876 /* ----------------------------------------------------------------------------
6877    -- BBNSM Peripheral Access Layer
6878    ---------------------------------------------------------------------------- */
6879 
6880 /*!
6881  * @addtogroup BBNSM_Peripheral_Access_Layer BBNSM Peripheral Access Layer
6882  * @{
6883  */
6884 
6885 /** BBNSM - Register Layout Typedef */
6886 typedef struct {
6887   __I  uint32_t BBNSM_VID;                         /**< BBNSM Version ID Register, offset: 0x0 */
6888   __I  uint32_t BBNSM_FEATURES;                    /**< BBNSM Features Register, offset: 0x4 */
6889   __IO uint32_t BBNSM_CTRL;                        /**< BBNSM Control Register, offset: 0x8 */
6890        uint8_t RESERVED_0[4];
6891   __IO uint32_t BBNSM_INT_EN;                      /**< BBNSM Interrupt Enable Register, offset: 0x10 */
6892   __IO uint32_t BBNSM_EVENTS;                      /**< BBNSM Events Register, offset: 0x14 */
6893        uint8_t RESERVED_1[12];
6894   __IO uint32_t BBNSM_PAD_CTRL;                    /**< BBNSM External Pad Control Register, offset: 0x24 */
6895        uint8_t RESERVED_2[24];
6896   __IO uint32_t BBNSM_RTC_LS;                      /**< BBNSM Real-Time Counter LS Register, offset: 0x40 */
6897   __IO uint32_t BBNSM_RTC_MS;                      /**< BBNSM Real-Time Counter MS Register, offset: 0x44 */
6898        uint8_t RESERVED_3[8];
6899   __IO uint32_t BBNSM_TA;                          /**< BBNSM Time Alarm Register, offset: 0x50 */
6900        uint8_t RESERVED_4[684];
6901   __IO uint32_t GPR[8];                            /**< General Purpose Register Word 0..General Purpose Register Word 7, array offset: 0x300, array step: 0x4 */
6902 } BBNSM_Type;
6903 
6904 /* ----------------------------------------------------------------------------
6905    -- BBNSM Register Masks
6906    ---------------------------------------------------------------------------- */
6907 
6908 /*!
6909  * @addtogroup BBNSM_Register_Masks BBNSM Register Masks
6910  * @{
6911  */
6912 
6913 /*! @name BBNSM_VID - BBNSM Version ID Register */
6914 /*! @{ */
6915 
6916 #define BBNSM_BBNSM_VID_BBNSM_IPID_MASK          (0xFFU)
6917 #define BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT         (0U)
6918 /*! BBNSM_IPID - BBNSM IP ID */
6919 #define BBNSM_BBNSM_VID_BBNSM_IPID(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_IPID_MASK)
6920 
6921 #define BBNSM_BBNSM_VID_BBNSM_REV_MASK           (0xFF00U)
6922 #define BBNSM_BBNSM_VID_BBNSM_REV_SHIFT          (8U)
6923 /*! BBNSM_REV - BBNSM Revision */
6924 #define BBNSM_BBNSM_VID_BBNSM_REV(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_REV_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_REV_MASK)
6925 
6926 #define BBNSM_BBNSM_VID_BBNSM_VID_MASK           (0xFF0000U)
6927 #define BBNSM_BBNSM_VID_BBNSM_VID_SHIFT          (16U)
6928 /*! BBNSM_VID - BBNSM Version ID */
6929 #define BBNSM_BBNSM_VID_BBNSM_VID(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_VID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_VID_MASK)
6930 /*! @} */
6931 
6932 /*! @name BBNSM_FEATURES - BBNSM Features Register */
6933 /*! @{ */
6934 
6935 #define BBNSM_BBNSM_FEATURES_GPR_SZ_MASK         (0xFCU)
6936 #define BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT        (2U)
6937 /*! GPR_SZ - GPR Register Array Size
6938  *  0b000000..This version of BBNSM does not implement a general-purpose register array.
6939  *  *..The number of 32-bit words implemented in the general-purpose register array.
6940  */
6941 #define BBNSM_BBNSM_FEATURES_GPR_SZ(x)           (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT)) & BBNSM_BBNSM_FEATURES_GPR_SZ_MASK)
6942 /*! @} */
6943 
6944 /*! @name BBNSM_CTRL - BBNSM Control Register */
6945 /*! @{ */
6946 
6947 #define BBNSM_BBNSM_CTRL_RTC_EN_MASK             (0x3U)
6948 #define BBNSM_BBNSM_CTRL_RTC_EN_SHIFT            (0U)
6949 /*! RTC_EN - Real-Time Counter Enable
6950  *  0b01..Disable the real-time counter.
6951  *  0b10..Enable the real-time counter.
6952  */
6953 #define BBNSM_BBNSM_CTRL_RTC_EN(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_RTC_EN_SHIFT)) & BBNSM_BBNSM_CTRL_RTC_EN_MASK)
6954 
6955 #define BBNSM_BBNSM_CTRL_TA_EN_MASK              (0xCU)
6956 #define BBNSM_BBNSM_CTRL_TA_EN_SHIFT             (2U)
6957 /*! TA_EN - Time Alarm Enable
6958  *  0b01..Disable the time alarm.
6959  *  0b10..Enable the time alarm. A time alarm event occurs if the value in the real-time counter register is equal
6960  *        to the value in the time alarm register.
6961  */
6962 #define BBNSM_BBNSM_CTRL_TA_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TA_EN_SHIFT)) & BBNSM_BBNSM_CTRL_TA_EN_MASK)
6963 
6964 #define BBNSM_BBNSM_CTRL_CAL_EN_MASK             (0x10U)
6965 #define BBNSM_BBNSM_CTRL_CAL_EN_SHIFT            (4U)
6966 /*! CAL_EN - Calibration Enable
6967  *  0b0..RTC Time calibration is disabled.
6968  *  0b1..RTC Time calibration is enabled.
6969  */
6970 #define BBNSM_BBNSM_CTRL_CAL_EN(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_EN_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_EN_MASK)
6971 
6972 #define BBNSM_BBNSM_CTRL_CAL_VAL_MASK            (0x1F00U)
6973 #define BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT           (8U)
6974 /*! CAL_VAL - Calibration Value
6975  *  0b01111..+15 counts per each 32768 ticks of the counter clock.
6976  *  0b00010..+2 counts per each 32768 ticks of the counter clock.
6977  *  0b00001..+1 counts per each 32768 ticks of the counter clock.
6978  *  0b00000..+0 counts per each 32768 ticks of the counter clock.
6979  *  0b11111..-1 counts per each 32768 ticks of the counter clock.
6980  *  0b11110..-2 counts per each 32768 ticks of the counter clock.
6981  *  0b10001..-15 counts per each 32768 ticks of the counter clock.
6982  *  0b10000..-16 counts per each 32768 ticks of the counter clock.
6983  */
6984 #define BBNSM_BBNSM_CTRL_CAL_VAL(x)              (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_VAL_MASK)
6985 
6986 #define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK        (0x30000U)
6987 #define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT       (16U)
6988 /*! BTN_TIMEOUT - Button Press Timeout
6989  *  0b00..5 seconds.
6990  *  0b01..10 seconds.
6991  *  0b10..15 seconds.
6992  *  0b11..Timeout disabled. Long button presses will not request a power down.
6993  */
6994 #define BBNSM_BBNSM_CTRL_BTN_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT)) & BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK)
6995 
6996 #define BBNSM_BBNSM_CTRL_DEBOUNCE_MASK           (0xC0000U)
6997 #define BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT          (18U)
6998 /*! DEBOUNCE - Debounce Time
6999  *  0b00..50 milliseconds.
7000  *  0b01..100 milliseconds.
7001  *  0b10..500 milliseconds.
7002  *  0b11..0 milliseconds.
7003  */
7004 #define BBNSM_BBNSM_CTRL_DEBOUNCE(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT)) & BBNSM_BBNSM_CTRL_DEBOUNCE_MASK)
7005 
7006 #define BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK       (0x300000U)
7007 #define BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT      (20U)
7008 /*! TURN_ON_TIME - Turn-On Time
7009  *  0b00..500 milliseconds.
7010  *  0b01..50 milliseconds.
7011  *  0b10..100 milliseconds.
7012  *  0b11..0 milliseconds.
7013  */
7014 #define BBNSM_BBNSM_CTRL_TURN_ON_TIME(x)         (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT)) & BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK)
7015 
7016 #define BBNSM_BBNSM_CTRL_PK_EN_MASK              (0x400000U)
7017 #define BBNSM_BBNSM_CTRL_PK_EN_SHIFT             (22U)
7018 /*! PK_EN - PMIC On Request Enable
7019  *  0b0..PMIC On Request is disabled.
7020  *  0b1..PMIC On Request is enabled.
7021  */
7022 #define BBNSM_BBNSM_CTRL_PK_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_EN_SHIFT)) & BBNSM_BBNSM_CTRL_PK_EN_MASK)
7023 
7024 #define BBNSM_BBNSM_CTRL_PK_OVR_MASK             (0x800000U)
7025 #define BBNSM_BBNSM_CTRL_PK_OVR_SHIFT            (23U)
7026 /*! PK_OVR - PMIC On Request Override
7027  *  0b0..PMIC On Request Override is disabled.
7028  *  0b1..PMIC On Request Override is enabled.
7029  */
7030 #define BBNSM_BBNSM_CTRL_PK_OVR(x)               (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_OVR_SHIFT)) & BBNSM_BBNSM_CTRL_PK_OVR_MASK)
7031 
7032 #define BBNSM_BBNSM_CTRL_DP_EN_MASK              (0x1000000U)
7033 #define BBNSM_BBNSM_CTRL_DP_EN_SHIFT             (24U)
7034 /*! DP_EN - Dumb PMIC Enable
7035  *  0b0..Smart PMIC is enabled.
7036  *  0b1..Dumb PMIC is enabled.
7037  */
7038 #define BBNSM_BBNSM_CTRL_DP_EN(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DP_EN_SHIFT)) & BBNSM_BBNSM_CTRL_DP_EN_MASK)
7039 
7040 #define BBNSM_BBNSM_CTRL_TOSP_MASK               (0x2000000U)
7041 #define BBNSM_BBNSM_CTRL_TOSP_SHIFT              (25U)
7042 /*! TOSP - Turn Off System Power
7043  *  0b0..Leave system power on.
7044  *  0b1..Turn off system power when Dumb PMIC is enabled.
7045  */
7046 #define BBNSM_BBNSM_CTRL_TOSP(x)                 (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TOSP_SHIFT)) & BBNSM_BBNSM_CTRL_TOSP_MASK)
7047 /*! @} */
7048 
7049 /*! @name BBNSM_INT_EN - BBNSM Interrupt Enable Register */
7050 /*! @{ */
7051 
7052 #define BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK       (0x3U)
7053 #define BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT      (0U)
7054 /*! RTC_INT_EN - Real-Time Counter Rollover Interrupt Enable
7055  *  0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written.
7056  *  0b10..Issue an interrupt when RTC has rolled over.
7057  */
7058 #define BBNSM_BBNSM_INT_EN_RTC_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK)
7059 
7060 #define BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK        (0xCU)
7061 #define BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT       (2U)
7062 /*! TA_INT_EN - Time Alarm Interrupt Enable
7063  *  0b01..Do not issue an interrupt when RTC has reached alarm time. The interrupt is cleared when this value is written.
7064  *  0b10..Issue an interrupt when RTC has reached alarm time.
7065  */
7066 #define BBNSM_BBNSM_INT_EN_TA_INT_EN(x)          (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK)
7067 /*! @} */
7068 
7069 /*! @name BBNSM_EVENTS - BBNSM Events Register */
7070 /*! @{ */
7071 
7072 #define BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK         (0x3U)
7073 #define BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT        (0U)
7074 /*! RTC_ROLL - Real-Time Counter Rollover Event
7075  *  0b01..The real-time counter has not rolled over.
7076  *  0b10..The real-time counter has rolled over.
7077  */
7078 #define BBNSM_BBNSM_EVENTS_RTC_ROLL(x)           (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT)) & BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK)
7079 
7080 #define BBNSM_BBNSM_EVENTS_TA_MASK               (0xCU)
7081 #define BBNSM_BBNSM_EVENTS_TA_SHIFT              (2U)
7082 /*! TA - Time Alarm Event
7083  *  0b01..The real-time counter has not reached the alarm time.
7084  *  0b10..The real-time counter has reached the alarm time.
7085  */
7086 #define BBNSM_BBNSM_EVENTS_TA(x)                 (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_TA_SHIFT)) & BBNSM_BBNSM_EVENTS_TA_MASK)
7087 
7088 #define BBNSM_BBNSM_EVENTS_EMG_OFF_MASK          (0x10U)
7089 #define BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT         (4U)
7090 /*! EMG_OFF - Emergency Off Event
7091  *  0b0..An emergency power off has not been requested.
7092  *  0b1..An emergency power off has been requested.
7093  */
7094 #define BBNSM_BBNSM_EVENTS_EMG_OFF(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_EMG_OFF_MASK)
7095 
7096 #define BBNSM_BBNSM_EVENTS_PWR_OFF_MASK          (0x20U)
7097 #define BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT         (5U)
7098 /*! PWR_OFF - Set Power Off Event
7099  *  0b0..The power off interrupt has not been requested.
7100  *  0b1..The power off interrupt has been requested.
7101  */
7102 #define BBNSM_BBNSM_EVENTS_PWR_OFF(x)            (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_OFF_MASK)
7103 
7104 #define BBNSM_BBNSM_EVENTS_PWR_ON_MASK           (0x40U)
7105 #define BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT          (6U)
7106 /*! PWR_ON - Set Power On Event
7107  *  0b0..The power on interrupt has not been requested.
7108  *  0b1..The power on interrupt has been requested.
7109  */
7110 #define BBNSM_BBNSM_EVENTS_PWR_ON(x)             (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_ON_MASK)
7111 /*! @} */
7112 
7113 /*! @name BBNSM_PAD_CTRL - BBNSM External Pad Control Register */
7114 /*! @{ */
7115 
7116 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK      (0x1U)
7117 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT     (0U)
7118 /*! PAD_CTRL0 - Control I/O Pads
7119  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7120  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7121  */
7122 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK)
7123 
7124 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK      (0x2U)
7125 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT     (1U)
7126 /*! PAD_CTRL1 - Control I/O Pads
7127  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7128  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7129  */
7130 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK)
7131 
7132 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK      (0x4U)
7133 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT     (2U)
7134 /*! PAD_CTRL2 - Control I/O Pads
7135  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7136  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7137  */
7138 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK)
7139 
7140 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK      (0x8U)
7141 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT     (3U)
7142 /*! PAD_CTRL3 - Control I/O Pads
7143  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7144  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7145  */
7146 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK)
7147 
7148 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK      (0x10U)
7149 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT     (4U)
7150 /*! PAD_CTRL4 - Control I/O Pads
7151  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7152  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7153  */
7154 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK)
7155 
7156 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK      (0x20U)
7157 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT     (5U)
7158 /*! PAD_CTRL5 - Control I/O Pads
7159  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7160  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7161  */
7162 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK)
7163 
7164 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK      (0x40U)
7165 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT     (6U)
7166 /*! PAD_CTRL6 - Control I/O Pads
7167  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7168  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7169  */
7170 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK)
7171 
7172 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK      (0x80U)
7173 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT     (7U)
7174 /*! PAD_CTRL7 - Control I/O Pads
7175  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7176  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7177  */
7178 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK)
7179 
7180 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK      (0x100U)
7181 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT     (8U)
7182 /*! PAD_CTRL8 - Control I/O Pads
7183  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7184  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7185  */
7186 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK)
7187 
7188 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK      (0x200U)
7189 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT     (9U)
7190 /*! PAD_CTRL9 - Control I/O Pads
7191  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7192  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7193  */
7194 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9(x)        (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK)
7195 
7196 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK     (0x400U)
7197 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT    (10U)
7198 /*! PAD_CTRL10 - Control I/O Pads
7199  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7200  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7201  */
7202 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK)
7203 
7204 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK     (0x800U)
7205 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT    (11U)
7206 /*! PAD_CTRL11 - Control I/O Pads
7207  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7208  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7209  */
7210 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK)
7211 
7212 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK     (0x1000U)
7213 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT    (12U)
7214 /*! PAD_CTRL12 - Control I/O Pads
7215  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7216  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7217  */
7218 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK)
7219 
7220 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK     (0x2000U)
7221 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT    (13U)
7222 /*! PAD_CTRL13 - Control I/O Pads
7223  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7224  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7225  */
7226 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK)
7227 
7228 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK     (0x4000U)
7229 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT    (14U)
7230 /*! PAD_CTRL14 - Control I/O Pads
7231  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7232  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7233  */
7234 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK)
7235 
7236 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK     (0x8000U)
7237 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT    (15U)
7238 /*! PAD_CTRL15 - Control I/O Pads
7239  *  0b0..Deasserts bit n in bbnsm_pad_ctrl[n]
7240  *  0b1..Assert bit n in bbnsm_pad_ctrl[n]
7241  */
7242 #define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15(x)       (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK)
7243 /*! @} */
7244 
7245 /*! @name BBNSM_RTC_LS - BBNSM Real-Time Counter LS Register */
7246 /*! @{ */
7247 
7248 #define BBNSM_BBNSM_RTC_LS_RTC_MASK              (0xFFFFFFFFU)
7249 #define BBNSM_BBNSM_RTC_LS_RTC_SHIFT             (0U)
7250 /*! RTC - Real-time Counter */
7251 #define BBNSM_BBNSM_RTC_LS_RTC(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_LS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_LS_RTC_MASK)
7252 /*! @} */
7253 
7254 /*! @name BBNSM_RTC_MS - BBNSM Real-Time Counter MS Register */
7255 /*! @{ */
7256 
7257 #define BBNSM_BBNSM_RTC_MS_RTC_MASK              (0x7FFFU)
7258 #define BBNSM_BBNSM_RTC_MS_RTC_SHIFT             (0U)
7259 /*! RTC - Real-Time Counter */
7260 #define BBNSM_BBNSM_RTC_MS_RTC(x)                (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_MS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_MS_RTC_MASK)
7261 /*! @} */
7262 
7263 /*! @name BBNSM_TA - BBNSM Time Alarm Register */
7264 /*! @{ */
7265 
7266 #define BBNSM_BBNSM_TA_TA_MASK                   (0xFFFFFFFFU)
7267 #define BBNSM_BBNSM_TA_TA_SHIFT                  (0U)
7268 /*! TA - Time Alarm Value */
7269 #define BBNSM_BBNSM_TA_TA(x)                     (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_TA_TA_SHIFT)) & BBNSM_BBNSM_TA_TA_MASK)
7270 /*! @} */
7271 
7272 /*! @name GPR - General Purpose Register Word 0..General Purpose Register Word 7 */
7273 /*! @{ */
7274 
7275 #define BBNSM_GPR_GPR_MASK                       (0xFFFFFFFFU)
7276 #define BBNSM_GPR_GPR_SHIFT                      (0U)
7277 /*! GPR - 32 bits of the GPR. */
7278 #define BBNSM_GPR_GPR(x)                         (((uint32_t)(((uint32_t)(x)) << BBNSM_GPR_GPR_SHIFT)) & BBNSM_GPR_GPR_MASK)
7279 /*! @} */
7280 
7281 /* The count of BBNSM_GPR */
7282 #define BBNSM_GPR_COUNT                          (8U)
7283 
7284 
7285 /*!
7286  * @}
7287  */ /* end of group BBNSM_Register_Masks */
7288 
7289 
7290 /* BBNSM - Peripheral instance base addresses */
7291 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7292   /** Peripheral BBNSM base address */
7293   #define BBNSM_BASE                               (0x54440000u)
7294   /** Peripheral BBNSM base address */
7295   #define BBNSM_BASE_NS                            (0x44440000u)
7296   /** Peripheral BBNSM base pointer */
7297   #define BBNSM                                    ((BBNSM_Type *)BBNSM_BASE)
7298   /** Peripheral BBNSM base pointer */
7299   #define BBNSM_NS                                 ((BBNSM_Type *)BBNSM_BASE_NS)
7300   /** Array initializer of BBNSM peripheral base addresses */
7301   #define BBNSM_BASE_ADDRS                         { BBNSM_BASE }
7302   /** Array initializer of BBNSM peripheral base pointers */
7303   #define BBNSM_BASE_PTRS                          { BBNSM }
7304   /** Array initializer of BBNSM peripheral base addresses */
7305   #define BBNSM_BASE_ADDRS_NS                      { BBNSM_BASE_NS }
7306   /** Array initializer of BBNSM peripheral base pointers */
7307   #define BBNSM_BASE_PTRS_NS                       { BBNSM_NS }
7308 #else
7309   /** Peripheral BBNSM base address */
7310   #define BBNSM_BASE                               (0x44440000u)
7311   /** Peripheral BBNSM base pointer */
7312   #define BBNSM                                    ((BBNSM_Type *)BBNSM_BASE)
7313   /** Array initializer of BBNSM peripheral base addresses */
7314   #define BBNSM_BASE_ADDRS                         { BBNSM_BASE }
7315   /** Array initializer of BBNSM peripheral base pointers */
7316   #define BBNSM_BASE_PTRS                          { BBNSM }
7317 #endif
7318 /** Interrupt vectors for the BBNSM peripheral type */
7319 #define BBNSM_IRQS                               { BBNSM_IRQn }
7320 
7321 /*!
7322  * @}
7323  */ /* end of group BBNSM_Peripheral_Access_Layer */
7324 
7325 
7326 /* ----------------------------------------------------------------------------
7327    -- BLK_CTRL_BBSMMIX Peripheral Access Layer
7328    ---------------------------------------------------------------------------- */
7329 
7330 /*!
7331  * @addtogroup BLK_CTRL_BBSMMIX_Peripheral_Access_Layer BLK_CTRL_BBSMMIX Peripheral Access Layer
7332  * @{
7333  */
7334 
7335 /** BLK_CTRL_BBSMMIX - Register Layout Typedef */
7336 typedef struct {
7337   __IO uint32_t BBSM_MISC;                         /**< BBSM miscellaneous register, offset: 0x0 */
7338   __IO uint32_t BBSM_TRIM;                         /**< BBSM TRIM register, offset: 0x4 */
7339 } BLK_CTRL_BBSMMIX_Type;
7340 
7341 /* ----------------------------------------------------------------------------
7342    -- BLK_CTRL_BBSMMIX Register Masks
7343    ---------------------------------------------------------------------------- */
7344 
7345 /*!
7346  * @addtogroup BLK_CTRL_BBSMMIX_Register_Masks BLK_CTRL_BBSMMIX Register Masks
7347  * @{
7348  */
7349 
7350 /*! @name BBSM_MISC - BBSM miscellaneous register */
7351 /*! @{ */
7352 
7353 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_BYPASS_EN_MASK (0x4U)
7354 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_BYPASS_EN_SHIFT (2U)
7355 /*! BBSM_BYPASS_EN - LDO_BBSM_ANA bypass enable
7356  *  0b1..Enable bypass
7357  *  0b0..Disable bypass
7358  */
7359 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_BYPASS_EN_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_BYPASS_EN_MASK)
7360 
7361 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_XTAL_CLK_OK_MASK (0x100000U)
7362 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_XTAL_CLK_OK_SHIFT (20U)
7363 /*! BBSM_XTAL_CLK_OK - 32K OSC ok flag
7364  *  0b1..32K oscillator is stable into normal operation
7365  *  0b0..32K oscillator is NOT stable into normal operation
7366  */
7367 #define BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_XTAL_CLK_OK_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_MISC_BBSM_XTAL_CLK_OK_MASK)
7368 /*! @} */
7369 
7370 /*! @name BBSM_TRIM - BBSM TRIM register */
7371 /*! @{ */
7372 
7373 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
7374 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
7375 /*! BBSM_CORE_VOLT_DET_TRIM_SEL - BBSM core voltage detect trim select
7376  *  0b0..The trimming codes are selected from eFuse
7377  *  0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from BBSM_CORE_VOLT_DET_TRIM
7378  */
7379 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SEL_MASK)
7380 
7381 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_MASK (0xCU)
7382 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SHIFT (2U)
7383 /*! BBSM_CORE_VOLT_DET_TRIM - BBSM core voltage detect trim */
7384 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CORE_VOLT_DET_TRIM_MASK)
7385 
7386 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CAP_TRIM_SEL_MASK (0x800000U)
7387 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CAP_TRIM_SEL_SHIFT (23U)
7388 /*! BBSM_CAP_TRIM_SEL - BBSM OSC load capacitor trim select
7389  *  0b0..The trimming codes are selected from eFuse
7390  *  0b1..The trimming codes are used from BBSM_OSC_CAP_TRIM (osc32k's load capacitor)
7391  */
7392 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CAP_TRIM_SEL_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_CAP_TRIM_SEL_MASK)
7393 
7394 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_OSC_CAP_TRIM_MASK (0xF000000U)
7395 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_OSC_CAP_TRIM_SHIFT (24U)
7396 /*! BBSM_OSC_CAP_TRIM - BBSM OSC load capacitor trim */
7397 #define BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_OSC_CAP_TRIM_SHIFT)) & BLK_CTRL_BBSMMIX_BBSM_TRIM_BBSM_OSC_CAP_TRIM_MASK)
7398 /*! @} */
7399 
7400 
7401 /*!
7402  * @}
7403  */ /* end of group BLK_CTRL_BBSMMIX_Register_Masks */
7404 
7405 
7406 /* BLK_CTRL_BBSMMIX - Peripheral instance base addresses */
7407 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7408   /** Peripheral BLK_CTRL_BBSMMIX base address */
7409   #define BLK_CTRL_BBSMMIX_BASE                    (0x54410000u)
7410   /** Peripheral BLK_CTRL_BBSMMIX base address */
7411   #define BLK_CTRL_BBSMMIX_BASE_NS                 (0x44410000u)
7412   /** Peripheral BLK_CTRL_BBSMMIX base pointer */
7413   #define BLK_CTRL_BBSMMIX                         ((BLK_CTRL_BBSMMIX_Type *)BLK_CTRL_BBSMMIX_BASE)
7414   /** Peripheral BLK_CTRL_BBSMMIX base pointer */
7415   #define BLK_CTRL_BBSMMIX_NS                      ((BLK_CTRL_BBSMMIX_Type *)BLK_CTRL_BBSMMIX_BASE_NS)
7416   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base addresses */
7417   #define BLK_CTRL_BBSMMIX_BASE_ADDRS              { BLK_CTRL_BBSMMIX_BASE }
7418   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base pointers */
7419   #define BLK_CTRL_BBSMMIX_BASE_PTRS               { BLK_CTRL_BBSMMIX }
7420   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base addresses */
7421   #define BLK_CTRL_BBSMMIX_BASE_ADDRS_NS           { BLK_CTRL_BBSMMIX_BASE_NS }
7422   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base pointers */
7423   #define BLK_CTRL_BBSMMIX_BASE_PTRS_NS            { BLK_CTRL_BBSMMIX_NS }
7424 #else
7425   /** Peripheral BLK_CTRL_BBSMMIX base address */
7426   #define BLK_CTRL_BBSMMIX_BASE                    (0x44410000u)
7427   /** Peripheral BLK_CTRL_BBSMMIX base pointer */
7428   #define BLK_CTRL_BBSMMIX                         ((BLK_CTRL_BBSMMIX_Type *)BLK_CTRL_BBSMMIX_BASE)
7429   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base addresses */
7430   #define BLK_CTRL_BBSMMIX_BASE_ADDRS              { BLK_CTRL_BBSMMIX_BASE }
7431   /** Array initializer of BLK_CTRL_BBSMMIX peripheral base pointers */
7432   #define BLK_CTRL_BBSMMIX_BASE_PTRS               { BLK_CTRL_BBSMMIX }
7433 #endif
7434 
7435 /*!
7436  * @}
7437  */ /* end of group BLK_CTRL_BBSMMIX_Peripheral_Access_Layer */
7438 
7439 
7440 /* ----------------------------------------------------------------------------
7441    -- BLK_CTRL_NS_AONMIX Peripheral Access Layer
7442    ---------------------------------------------------------------------------- */
7443 
7444 /*!
7445  * @addtogroup BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer BLK_CTRL_NS_AONMIX Peripheral Access Layer
7446  * @{
7447  */
7448 
7449 /** BLK_CTRL_NS_AONMIX - Register Layout Typedef */
7450 typedef struct {
7451   __IO uint32_t GPC_CFG;                           /**< GPC CORE SLEEP Request Select, offset: 0x0 */
7452        uint8_t RESERVED_0[4];
7453   __IO uint32_t IPG_DEBUG;                         /**< IPG Debug mask, offset: 0x8 */
7454        uint8_t RESERVED_1[16];
7455   __IO uint32_t SSI;                               /**< offset: 0x1C */
7456   __IO uint32_t SAI1_MCLK_CTRL;                    /**< SAI1 MCLK control register, offset: 0x20 */
7457   __IO uint32_t DCDC_STATUS;                       /**< DCDC status register, offset: 0x24 */
7458   __I  uint32_t FUSE_ACC_DIS;                      /**< Fuse access disable register, offset: 0x28 */
7459   __IO uint32_t M33_NMI_CLR;                       /**< M33 NMI interrupt clear register, offset: 0x2C */
7460   __IO uint32_t I3C1_ASYNC_WAKEUP_CTRL;            /**< I3C1 async wakeup control register, offset: 0x30 */
7461   __IO uint32_t MISC_IO_CTRL;                      /**< Miscellaneous control register of IO, offset: 0x34 */
7462 } BLK_CTRL_NS_AONMIX_Type;
7463 
7464 /* ----------------------------------------------------------------------------
7465    -- BLK_CTRL_NS_AONMIX Register Masks
7466    ---------------------------------------------------------------------------- */
7467 
7468 /*!
7469  * @addtogroup BLK_CTRL_NS_AONMIX_Register_Masks BLK_CTRL_NS_AONMIX Register Masks
7470  * @{
7471  */
7472 
7473 /*! @name GPC_CFG - GPC CORE SLEEP Request Select */
7474 /*! @{ */
7475 
7476 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_MASK (0x1U)
7477 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_SHIFT (0U)
7478 /*! M33_SLEEP_SEL - M33 SLEEP Request Select
7479  *  0b0..Select SLEEPING as request source
7480  *  0b1..Select SLEEPDEEP as request source
7481  */
7482 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_SHIFT)) & BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_MASK)
7483 
7484 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_MASK (0x2U)
7485 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_SHIFT (1U)
7486 /*! M7_SLEEP_SEL - M7 SLEEP Request Select
7487  *  0b0..Select SLEEPING as request source
7488  *  0b1..Select SLEEPDEEP as request source
7489  */
7490 #define BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_SHIFT)) & BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_MASK)
7491 /*! @} */
7492 
7493 /*! @name IPG_DEBUG - IPG Debug mask */
7494 /*! @{ */
7495 
7496 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN1_MASK (0x1U)
7497 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN1_SHIFT (0U)
7498 /*! M33_CAN1 - Mask bit for CAN1 debug halted mode with M33 core
7499  *  0b1..CAN1 enters debug halted mode when CM33 is debug halted
7500  *  0b0..CAN1 does not enter debug halted mode with CM33
7501  */
7502 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN1_MASK)
7503 
7504 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_EDMA3_MASK (0x2U)
7505 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_EDMA3_SHIFT (1U)
7506 /*! M33_EDMA3 - Mask bit for EDMA3 debug halted mode with M33 core
7507  *  0b1..EDMA3 enters debug halted mode when CM33 is debug halted
7508  *  0b0..EDMA3 does not enter debug halted mode with CM33
7509  */
7510 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_EDMA3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_EDMA3_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_EDMA3_MASK)
7511 
7512 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C1_MASK (0x4U)
7513 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C1_SHIFT (2U)
7514 /*! M33_LPI2C1 - Mask bit for LPI2C1 debug halted mode with M33 core
7515  *  0b1..LPI2C1 enters debug halted mode when CM33 is debug halted
7516  *  0b0..LPI2C1 does not enter debug halted mode with CM33
7517  */
7518 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C1_MASK)
7519 
7520 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C2_MASK (0x8U)
7521 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C2_SHIFT (3U)
7522 /*! M33_LPI2C2 - Mask bit for LPI2C2 debug halted mode with M33 core
7523  *  0b1..LPI2C2 enters debug halted mode when CM33 is debug halted
7524  *  0b0..LPI2C2 does not enter debug halted mode with CM33
7525  */
7526 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPI2C2_MASK)
7527 
7528 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPIT1_MASK (0x10U)
7529 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPIT1_SHIFT (4U)
7530 /*! M33_LPIT1 - Mask bit for LPIT1 debug halted mode with M33 core
7531  *  0b1..LPIT1 enters debug halted mode when CM33 is debug halted
7532  *  0b0..LPIT1 does not enter debug halted mode with CM33
7533  */
7534 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPIT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPIT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPIT1_MASK)
7535 
7536 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI1_MASK (0x20U)
7537 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI1_SHIFT (5U)
7538 /*! M33_LPSPI1 - Mask bit for LPSPI1 debug halted mode with M33 core
7539  *  0b1..LPSPI1 enters debug halted mode when CM33 is debug halted
7540  *  0b0..LPSPI1 does not enter debug halted mode with CM33
7541  */
7542 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI1_MASK)
7543 
7544 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI2_MASK (0x40U)
7545 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI2_SHIFT (6U)
7546 /*! M33_LPSPI2 - Mask bit for LPSPI2 debug halted mode with M33 core
7547  *  0b1..LPSPI2 enters debug halted mode when CM33 is debug halted
7548  *  0b0..LPSPI2 does not enter debug halted mode with CM33
7549  */
7550 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPSPI2_MASK)
7551 
7552 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPTMR1_MASK (0x80U)
7553 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPTMR1_SHIFT (7U)
7554 /*! M33_LPTMR1 - Mask bit for LPTMR1 debug halted mode with M33 core
7555  *  0b1..LPTMR1 enters debug halted mode when CM33 is debug halted
7556  *  0b0..LPTMR1 does not enter debug halted mode with CM33
7557  */
7558 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPTMR1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_LPTMR1_MASK)
7559 
7560 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_SAI1_MASK (0x100U)
7561 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_SAI1_SHIFT (8U)
7562 /*! M33_SAI1 - Mask bit for SAI1 debug halted mode with M33 core
7563  *  0b1..SAI1 enters debug halted mode when CM33 is debug halted
7564  *  0b0..SAI1 does not enter debug halted mode with CM33
7565  */
7566 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_SAI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_SAI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_SAI1_MASK)
7567 
7568 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM1_MASK (0x200U)
7569 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM1_SHIFT (9U)
7570 /*! M33_TPM1 - Mask bit for TPM1 debug halted mode with M33 core
7571  *  0b1..TPM1 enters debug halted mode when CM33 is debug halted
7572  *  0b0..TPM1 does not enter debug halted mode with CM33
7573  */
7574 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM1_MASK)
7575 
7576 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM2_MASK (0x400U)
7577 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM2_SHIFT (10U)
7578 /*! M33_TPM2 - Mask bit for TPM2 debug halted mode with M33 core
7579  *  0b1..TPM2 enters debug halted mode when CM33 is debug halted
7580  *  0b0..TPM2 does not enter debug halted mode with CM33
7581  */
7582 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_TPM2_MASK)
7583 
7584 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG1_MASK (0x800U)
7585 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG1_SHIFT (11U)
7586 /*! M33_WDOG1 - Mask bit for WDOG1 debug halted mode with M33 core
7587  *  0b1..WDOG1 enters debug halted mode when CM33 is debug halted
7588  *  0b0..WDOG1 does not enter debug halted mode with CM33
7589  */
7590 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG1_MASK)
7591 
7592 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG2_MASK (0x1000U)
7593 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG2_SHIFT (12U)
7594 /*! M33_WDOG2 - Mask bit for WDOG2 debug halted mode with M33 core
7595  *  0b1..WDOG2 enters debug halted mode when CM33 is debug halted
7596  *  0b0..WDOG2 does not enter debug halted mode with CM33
7597  */
7598 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_WDOG2_MASK)
7599 
7600 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_GPT1_MASK (0x2000U)
7601 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_GPT1_SHIFT (13U)
7602 /*! M33_GPT1 - Mask bit for GPT1 debug halted mode with M33 core
7603  *  0b1..GPT1 enters debug halted mode when CM33 is debug halted
7604  *  0b0..GPT1 does not enter debug halted mode with CM33
7605  */
7606 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_GPT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_GPT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_GPT1_MASK)
7607 
7608 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN3_MASK (0x4000U)
7609 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN3_SHIFT (14U)
7610 /*! M33_CAN3 - Mask bit for CAN3 debug halted mode with M33 core
7611  *  0b1..CAN3 enters debug halted mode when CM33 is debug halted
7612  *  0b0..CAN3 does not enter debug halted mode with CM33
7613  */
7614 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN3_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_CAN3_MASK)
7615 
7616 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_I3C1_MASK (0x8000U)
7617 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_I3C1_SHIFT (15U)
7618 /*! M33_I3C1 - Mask bit for I3C1 debug halted mode with M33 core
7619  *  0b1..I3C1 enters debug halted mode when CM33 is debug halted
7620  *  0b0..I3C1 does not enter debug halted mode with CM33
7621  */
7622 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_I3C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_I3C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M33_I3C1_MASK)
7623 
7624 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN1_MASK (0x10000U)
7625 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN1_SHIFT (16U)
7626 /*! M7_CAN1 - Mask bit for CAN1 debug halted mode with M7 core
7627  *  0b1..CAN1 enters debug halted mode when CM7 is debug halted
7628  *  0b0..CAN1 does not enter debug halted mode with CM7
7629  */
7630 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN1(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN1_MASK)
7631 
7632 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_EDMA3_MASK (0x20000U)
7633 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_EDMA3_SHIFT (17U)
7634 /*! M7_EDMA3 - Mask bit for EDMA3 debug halted mode with M7 core
7635  *  0b1..EDMA3 enters debug halted mode when CM7 is debug halted
7636  *  0b0..EDMA3 does not enter debug halted mode with CM7
7637  */
7638 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_EDMA3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_EDMA3_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_EDMA3_MASK)
7639 
7640 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C1_MASK (0x40000U)
7641 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C1_SHIFT (18U)
7642 /*! M7_LPI2C1 - Mask bit for LPI2C1 debug halted mode with M7 core
7643  *  0b1..LPI2C1 enters debug halted mode when CM7 is debug halted
7644  *  0b0..LPI2C1 does not enter debug halted mode with CM7
7645  */
7646 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C1_MASK)
7647 
7648 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C2_MASK (0x80000U)
7649 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C2_SHIFT (19U)
7650 /*! M7_LPI2C2 - Mask bit for LPI2C2 debug halted mode with M7 core
7651  *  0b1..LPI2C2 enters debug halted mode when CM7 is debug halted
7652  *  0b0..LPI2C2 does not enter debug halted mode with CM7
7653  */
7654 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPI2C2_MASK)
7655 
7656 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPIT1_MASK (0x100000U)
7657 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPIT1_SHIFT (20U)
7658 /*! M7_LPIT1 - Mask bit for LPIT1 debug halted mode with M7 core
7659  *  0b1..LPIT1 enters debug halted mode when CM7 is debug halted
7660  *  0b0..LPIT1 does not enter debug halted mode with CM7
7661  */
7662 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPIT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPIT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPIT1_MASK)
7663 
7664 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI1_MASK (0x200000U)
7665 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI1_SHIFT (21U)
7666 /*! M7_LPSPI1 - Mask bit for LPSPI1 debug halted mode with M7 core
7667  *  0b1..LPSPI1 enters debug halted mode when CM7 is debug halted
7668  *  0b0..LPSPI1 does not enter debug halted mode with CM7
7669  */
7670 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI1_MASK)
7671 
7672 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI2_MASK (0x400000U)
7673 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI2_SHIFT (22U)
7674 /*! M7_LPSPI2 - Mask bit for LPSPI2 debug halted mode with M7 core
7675  *  0b1..LPSPI2 enters debug halted mode when CM7 is debug halted
7676  *  0b0..LPSPI2 does not enter debug halted mode with CM7
7677  */
7678 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPSPI2_MASK)
7679 
7680 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPTMR1_MASK (0x800000U)
7681 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPTMR1_SHIFT (23U)
7682 /*! M7_LPTMR1 - Mask bit for LPTMR1 debug halted mode with M7 core
7683  *  0b1..LPTMR1 enters debug halted mode when CM7 is debug halted
7684  *  0b0..LPTMR1 does not enter debug halted mode with CM7
7685  */
7686 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPTMR1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_LPTMR1_MASK)
7687 
7688 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_SAI1_MASK (0x1000000U)
7689 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_SAI1_SHIFT (24U)
7690 /*! M7_SAI1 - Mask bit for SAI1 debug halted mode with M7 core
7691  *  0b1..SAI1 enters debug halted mode when CM7 is debug halted
7692  *  0b0..SAI1 does not enter debug halted mode with CM7
7693  */
7694 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_SAI1(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_SAI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_SAI1_MASK)
7695 
7696 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM1_MASK (0x2000000U)
7697 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM1_SHIFT (25U)
7698 /*! M7_TPM1 - Mask bit for TPM1 debug halted mode with M7 core
7699  *  0b1..TPM1 enters debug halted mode when CM7 is debug halted
7700  *  0b0..TPM1 does not enter debug halted mode with CM7
7701  */
7702 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM1(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM1_MASK)
7703 
7704 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM2_MASK (0x4000000U)
7705 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM2_SHIFT (26U)
7706 /*! M7_TPM2 - Mask bit for TPM2 debug halted mode with M7 core
7707  *  0b1..TPM2 enters debug halted mode when CM7 is debug halted
7708  *  0b0..TPM2 does not enter debug halted mode with CM7
7709  */
7710 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM2(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_TPM2_MASK)
7711 
7712 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG1_MASK (0x8000000U)
7713 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG1_SHIFT (27U)
7714 /*! M7_WDOG1 - Mask bit for WDOG1 debug halted mode with M7 core
7715  *  0b1..WDOG1 enters debug halted mode when CM7 is debug halted
7716  *  0b0..WDOG1 does not enter debug halted mode with CM7
7717  */
7718 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG1_MASK)
7719 
7720 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG2_MASK (0x10000000U)
7721 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG2_SHIFT (28U)
7722 /*! M7_WDOG2 - Mask bit for WDOG2 debug halted mode with M7 core
7723  *  0b1..WDOG2 enters debug halted mode when CM7 is debug halted
7724  *  0b0..WDOG2 does not enter debug halted mode with CM7
7725  */
7726 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_WDOG2_MASK)
7727 
7728 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_GPT1_MASK (0x20000000U)
7729 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_GPT1_SHIFT (29U)
7730 /*! M7_GPT1 - Mask bit for GPT1 debug halted mode with M7 core
7731  *  0b1..GPT1 enters debug halted mode when CM7 is debug halted
7732  *  0b0..GPT1 does not enter debug halted mode with CM7
7733  */
7734 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_GPT1(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_GPT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_GPT1_MASK)
7735 
7736 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN3_MASK (0x40000000U)
7737 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN3_SHIFT (30U)
7738 /*! M7_CAN3 - Mask bit for CAN3 debug halted mode with M7 core
7739  *  0b1..CAN3 enters debug halted mode when CM7 is debug halted
7740  *  0b0..CAN3 does not enter debug halted mode with CM7
7741  */
7742 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN3(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN3_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_CAN3_MASK)
7743 
7744 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_I3C1_MASK (0x80000000U)
7745 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_I3C1_SHIFT (31U)
7746 /*! M7_I3C1 - Mask bit for I3C1 debug halted mode with M7 core
7747  *  0b1..I3C1 enters debug halted mode when CM7 is debug halted
7748  *  0b0..I3C1 does not enter debug halted mode with CM7
7749  */
7750 #define BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_I3C1(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_I3C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_M7_I3C1_MASK)
7751 /*! @} */
7752 
7753 /*! @name SSI -  */
7754 /*! @{ */
7755 
7756 #define BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_MASK   (0x1U)
7757 #define BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_SHIFT  (0U)
7758 /*! PAUSE_MODE - AON Domain SSI master pause mode
7759  *  0b0..AON Domain SSI master is not in pause mode
7760  *  0b1..AON Domain SSI master is in pause mode
7761  */
7762 #define BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_MASK)
7763 
7764 #define BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_MASK (0x2U)
7765 #define BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_SHIFT (1U)
7766 /*! BLKHOLE_MODE_B - AON Domain SSI master blackhole mode
7767  *  0b0..AON Domain SSI master will enter into blackhole mode
7768  *  0b1..AON Domain SSI master will exit from blackhole mode
7769  */
7770 #define BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_MASK)
7771 /*! @} */
7772 
7773 /*! @name SAI1_MCLK_CTRL - SAI1 MCLK control register */
7774 /*! @{ */
7775 
7776 #define BLK_CTRL_NS_AONMIX_SAI1_MCLK_CTRL_SAI1_MCLK_DIR_MASK (0x100U)
7777 #define BLK_CTRL_NS_AONMIX_SAI1_MCLK_CTRL_SAI1_MCLK_DIR_SHIFT (8U)
7778 /*! SAI1_MCLK_DIR - SAI1_MCLK IO direction control. IOMUX need select SAI1 MCLK function
7779  *  0b0..SAI1_MCLK is input signal
7780  *  0b1..SAI1_MCLK is output signal
7781  */
7782 #define BLK_CTRL_NS_AONMIX_SAI1_MCLK_CTRL_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SAI1_MCLK_CTRL_SAI1_MCLK_DIR_SHIFT)) & BLK_CTRL_NS_AONMIX_SAI1_MCLK_CTRL_SAI1_MCLK_DIR_MASK)
7783 /*! @} */
7784 
7785 /*! @name DCDC_STATUS - DCDC status register */
7786 /*! @{ */
7787 
7788 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
7789 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
7790 /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
7791  *  0b0..No change
7792  *  0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
7793  */
7794 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STATUS_CAPT_CLR_SHIFT)) & BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STATUS_CAPT_CLR_MASK)
7795 
7796 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_IN_LOW_VOL_MASK (0x10000U)
7797 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_IN_LOW_VOL_SHIFT (16U)
7798 /*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect
7799  *  0b1..Voltage on DCDC_IN is lower than 2.6V
7800  *  0b0..Voltage on DCDC_IN is higher than 2.6V
7801  */
7802 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_IN_LOW_VOL_SHIFT)) & BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_IN_LOW_VOL_MASK)
7803 
7804 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_CUR_MASK (0x20000U)
7805 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_CUR_SHIFT (17U)
7806 /*! DCDC_OVER_CUR - DCDC output over current alert
7807  *  0b1..Overcurrent on DCDC output
7808  *  0b0..No Overcurrent on DCDC output
7809  */
7810 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_CUR_SHIFT)) & BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_CUR_MASK)
7811 
7812 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_VOL_MASK (0x40000U)
7813 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_VOL_SHIFT (18U)
7814 /*! DCDC_OVER_VOL - DCDC output over voltage alert
7815  *  0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output
7816  *  0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
7817  */
7818 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_VOL_SHIFT)) & BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_OVER_VOL_MASK)
7819 
7820 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STS_DC_OK_MASK (0x80000U)
7821 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STS_DC_OK_SHIFT (19U)
7822 /*! DCDC_STS_DC_OK - DCDC status OK
7823  *  0b0..DCDC is settling
7824  *  0b1..DCDC already settled
7825  */
7826 #define BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STS_DC_OK_SHIFT)) & BLK_CTRL_NS_AONMIX_DCDC_STATUS_DCDC_STS_DC_OK_MASK)
7827 /*! @} */
7828 
7829 /*! @name FUSE_ACC_DIS - Fuse access disable register */
7830 /*! @{ */
7831 
7832 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK (0x1U)
7833 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT (0U)
7834 /*! OSCCA_FUSE_READ_DIS - Fuse read disable flag
7835  *  0b1..Read is not allowed
7836  *  0b0..Read is allowed
7837  */
7838 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT)) & BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK)
7839 
7840 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_CALIBRATED_MASK (0x2U)
7841 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_CALIBRATED_SHIFT (1U)
7842 /*! OCOTP_CALIBRATED - Fuse calibrate flag
7843  *  0b1..OCOTP is calibrated
7844  *  0b0..OCOTP is not calibrated
7845  */
7846 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_CALIBRATED_SHIFT)) & BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_CALIBRATED_MASK)
7847 
7848 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_BUSY_MASK (0x4U)
7849 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_BUSY_SHIFT (2U)
7850 /*! OCOTP_BUSY - OCOTP busy flag
7851  *  0b1..OCOTP is busy
7852  *  0b0..OCOTP is not busy
7853  */
7854 #define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_BUSY_SHIFT)) & BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OCOTP_BUSY_MASK)
7855 /*! @} */
7856 
7857 /*! @name M33_NMI_CLR - M33 NMI interrupt clear register */
7858 /*! @{ */
7859 
7860 #define BLK_CTRL_NS_AONMIX_M33_NMI_CLR_M33_NMI_CLEAR_MASK (0x1U)
7861 #define BLK_CTRL_NS_AONMIX_M33_NMI_CLR_M33_NMI_CLEAR_SHIFT (0U)
7862 /*! M33_NMI_CLEAR - Clear CM33 NMI holding register */
7863 #define BLK_CTRL_NS_AONMIX_M33_NMI_CLR_M33_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_M33_NMI_CLR_M33_NMI_CLEAR_SHIFT)) & BLK_CTRL_NS_AONMIX_M33_NMI_CLR_M33_NMI_CLEAR_MASK)
7864 /*! @} */
7865 
7866 /*! @name I3C1_ASYNC_WAKEUP_CTRL - I3C1 async wakeup control register */
7867 /*! @{ */
7868 
7869 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_CLR_MASK (0x1U)
7870 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_CLR_SHIFT (0U)
7871 /*! IRQ_CLR - Async wakeup interrupt clear */
7872 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_CLR_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_CLR_MASK)
7873 
7874 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_STATUS_MASK (0x10000U)
7875 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_STATUS_SHIFT (16U)
7876 /*! IRQ_STATUS - Async wakeup interrupt status
7877  *  0b0..Interrupt not asserted
7878  *  0b1..Interrupt asserted
7879  */
7880 #define BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_STATUS_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_ASYNC_WAKEUP_CTRL_IRQ_STATUS_MASK)
7881 /*! @} */
7882 
7883 /*! @name MISC_IO_CTRL - Miscellaneous control register of IO */
7884 /*! @{ */
7885 
7886 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_MASK (0x1U)
7887 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_SHIFT (0U)
7888 /*! I3C_ON_CHIP_STRONG_PULL_DIS - Disable I3C on-chip strong pull for I3C1
7889  *  0b0..On-chip strong pull is enabled
7890  *  0b1..On-chip strong pull is disabled
7891  */
7892 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_SHIFT)) & BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_MASK)
7893 
7894 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_HIGH_RANGE_MASK (0x2U)
7895 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_HIGH_RANGE_SHIFT (1U)
7896 /*! GPIO_AON_HIGH_RANGE - GPIO_AON IO bank supply voltage range selection */
7897 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_HIGH_RANGE_SHIFT)) & BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_HIGH_RANGE_MASK)
7898 
7899 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_LOW_RANGE_MASK (0x4U)
7900 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_LOW_RANGE_SHIFT (2U)
7901 /*! GPIO_AON_LOW_RANGE - GPIO_AON IO bank supply voltage range selection */
7902 #define BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_LOW_RANGE_SHIFT)) & BLK_CTRL_NS_AONMIX_MISC_IO_CTRL_GPIO_AON_LOW_RANGE_MASK)
7903 /*! @} */
7904 
7905 
7906 /*!
7907  * @}
7908  */ /* end of group BLK_CTRL_NS_AONMIX_Register_Masks */
7909 
7910 
7911 /* BLK_CTRL_NS_AONMIX - Peripheral instance base addresses */
7912 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
7913   /** Peripheral BLK_CTRL_NS_AONMIX base address */
7914   #define BLK_CTRL_NS_AONMIX_BASE                  (0x54210000u)
7915   /** Peripheral BLK_CTRL_NS_AONMIX base address */
7916   #define BLK_CTRL_NS_AONMIX_BASE_NS               (0x44210000u)
7917   /** Peripheral BLK_CTRL_NS_AONMIX base pointer */
7918   #define BLK_CTRL_NS_AONMIX                       ((BLK_CTRL_NS_AONMIX_Type *)BLK_CTRL_NS_AONMIX_BASE)
7919   /** Peripheral BLK_CTRL_NS_AONMIX base pointer */
7920   #define BLK_CTRL_NS_AONMIX_NS                    ((BLK_CTRL_NS_AONMIX_Type *)BLK_CTRL_NS_AONMIX_BASE_NS)
7921   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base addresses */
7922   #define BLK_CTRL_NS_AONMIX_BASE_ADDRS            { BLK_CTRL_NS_AONMIX_BASE }
7923   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base pointers */
7924   #define BLK_CTRL_NS_AONMIX_BASE_PTRS             { BLK_CTRL_NS_AONMIX }
7925   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base addresses */
7926   #define BLK_CTRL_NS_AONMIX_BASE_ADDRS_NS         { BLK_CTRL_NS_AONMIX_BASE_NS }
7927   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base pointers */
7928   #define BLK_CTRL_NS_AONMIX_BASE_PTRS_NS          { BLK_CTRL_NS_AONMIX_NS }
7929 #else
7930   /** Peripheral BLK_CTRL_NS_AONMIX base address */
7931   #define BLK_CTRL_NS_AONMIX_BASE                  (0x44210000u)
7932   /** Peripheral BLK_CTRL_NS_AONMIX base pointer */
7933   #define BLK_CTRL_NS_AONMIX                       ((BLK_CTRL_NS_AONMIX_Type *)BLK_CTRL_NS_AONMIX_BASE)
7934   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base addresses */
7935   #define BLK_CTRL_NS_AONMIX_BASE_ADDRS            { BLK_CTRL_NS_AONMIX_BASE }
7936   /** Array initializer of BLK_CTRL_NS_AONMIX peripheral base pointers */
7937   #define BLK_CTRL_NS_AONMIX_BASE_PTRS             { BLK_CTRL_NS_AONMIX }
7938 #endif
7939 
7940 /*!
7941  * @}
7942  */ /* end of group BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer */
7943 
7944 
7945 /* ----------------------------------------------------------------------------
7946    -- BLK_CTRL_S_AONMIX Peripheral Access Layer
7947    ---------------------------------------------------------------------------- */
7948 
7949 /*!
7950  * @addtogroup BLK_CTRL_S_AONMIX_Peripheral_Access_Layer BLK_CTRL_S_AONMIX Peripheral Access Layer
7951  * @{
7952  */
7953 
7954 /** BLK_CTRL_S_AONMIX - Register Layout Typedef */
7955 typedef struct {
7956   __IO uint32_t CM33_IRQ_MASK[8];                  /**< CM33_IRQ_MASK0..CM33_IRQ_MASK7, array offset: 0x0, array step: 0x4 */
7957   __IO uint32_t CM7_IRQ_MASK[8];                   /**< CM7_IRQ_MASK0..CM7_IRQ_MASK7, array offset: 0x20, array step: 0x4 */
7958        uint8_t RESERVED_0[24];
7959   __IO uint32_t EDGELOCK_RESET_REQ_MASK;           /**< EdgeLock reset request mask, offset: 0x58 */
7960   __IO uint32_t EDGELOCK_IRQ_MASK;                 /**< EdgeLock IRQ request mask, offset: 0x5C */
7961   __IO uint32_t M33_CFG;                           /**< M33 Configuration, offset: 0x60 */
7962   __IO uint32_t M33_INITSVTOR;                     /**< M33 INITSVTOR, offset: 0x64 */
7963   __IO uint32_t M33_INITNSVTOR;                    /**< M33 INITNSVTOR, offset: 0x68 */
7964        uint8_t RESERVED_1[20];
7965   __IO uint32_t M7_CFG;                            /**< M7 Configuration, offset: 0x80 */
7966        uint8_t RESERVED_2[12];
7967   __IO uint32_t AXBS_AON_CTRL;                     /**< AXBS_AON_CTRL, offset: 0x90 */
7968        uint8_t RESERVED_3[108];
7969   __IO uint32_t DAP_ACCESS_STKYBIT;                /**< DAP Access Sticky Bit, offset: 0x100 */
7970        uint8_t RESERVED_4[12];
7971   __IO uint32_t LP_HANDSHAKE;                      /**< Low power handshake enable, offset: 0x110 */
7972   __IO uint32_t EDGELOCK_HALT_ST;                  /**< EdgeLock halt status, offset: 0x114 */
7973        uint8_t RESERVED_5[8];
7974   __I  uint32_t ECC_MEM_INIT;                      /**< ECC memory hardware initialization, offset: 0x120 */
7975        uint8_t RESERVED_6[36];
7976   __IO uint32_t IOMUXC_DOMAIN_CFG;                 /**< IOMUXC domain configure, offset: 0x148 */
7977   __IO uint32_t IOMUXC_AON_DOMAIN_CFG;             /**< IOMUXC_AON domain configure, offset: 0x14C */
7978        uint8_t RESERVED_7[4];
7979   __IO uint32_t NMI_CTRL;                          /**< NMI control, offset: 0x154 */
7980   __IO uint32_t S401_NOCLK_CLEAR_CTRL;             /**< s401_ipi_noclk_ref1 clear control, offset: 0x158 */
7981 } BLK_CTRL_S_AONMIX_Type;
7982 
7983 /* ----------------------------------------------------------------------------
7984    -- BLK_CTRL_S_AONMIX Register Masks
7985    ---------------------------------------------------------------------------- */
7986 
7987 /*!
7988  * @addtogroup BLK_CTRL_S_AONMIX_Register_Masks BLK_CTRL_S_AONMIX Register Masks
7989  * @{
7990  */
7991 
7992 /*! @name CM33_IRQ_MASK - CM33_IRQ_MASK0..CM33_IRQ_MASK7 */
7993 /*! @{ */
7994 
7995 #define BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_M_MASK   (0xFFFFFFFFU)
7996 #define BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_M_SHIFT  (0U)
7997 /*! M - CM33 IRQ MASK
7998  *  0b00000000000000000000000000000001..No Mask IRQ
7999  *  0b00000000000000000000000000000000..Mask IRQ
8000  */
8001 #define BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_M(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_M_SHIFT)) & BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_M_MASK)
8002 /*! @} */
8003 
8004 /* The count of BLK_CTRL_S_AONMIX_CM33_IRQ_MASK */
8005 #define BLK_CTRL_S_AONMIX_CM33_IRQ_MASK_COUNT    (8U)
8006 
8007 /*! @name CM7_IRQ_MASK - CM7_IRQ_MASK0..CM7_IRQ_MASK7 */
8008 /*! @{ */
8009 
8010 #define BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_M_MASK    (0xFFFFFFFFU)
8011 #define BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_M_SHIFT   (0U)
8012 /*! M - CM7 IRQ MASK
8013  *  0b00000000000000000000000000000001..No Mask IRQ
8014  *  0b00000000000000000000000000000000..Mask IRQ
8015  */
8016 #define BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_M(x)      (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_M_SHIFT)) & BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_M_MASK)
8017 /*! @} */
8018 
8019 /* The count of BLK_CTRL_S_AONMIX_CM7_IRQ_MASK */
8020 #define BLK_CTRL_S_AONMIX_CM7_IRQ_MASK_COUNT     (8U)
8021 
8022 /*! @name EDGELOCK_RESET_REQ_MASK - EdgeLock reset request mask */
8023 /*! @{ */
8024 
8025 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_WDG_RESET_MASK (0x1U)
8026 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_WDG_RESET_SHIFT (0U)
8027 /*! WDG_RESET - EdgeLock Wdog reset mask
8028  *  0b1..Mask reset
8029  *  0b0..Unmask reset
8030  */
8031 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_WDG_RESET_MASK)
8032 
8033 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_PUF_RESET_MASK (0x2U)
8034 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_PUF_RESET_SHIFT (1U)
8035 /*! PUF_RESET - EdgeLock PUF reset mask
8036  *  0b1..Mask reset
8037  *  0b0..Unmask reset
8038  */
8039 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_PUF_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_PUF_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_PUF_RESET_MASK)
8040 
8041 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LC_BRICKED_MASK (0x4U)
8042 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LC_BRICKED_SHIFT (2U)
8043 /*! LC_BRICKED - EdgeLock LMDA life cycle bricked reset mask
8044  *  0b1..Mask reset
8045  *  0b0..Unmask reset
8046  */
8047 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LC_BRICKED_MASK)
8048 
8049 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK (0x8U)
8050 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT (3U)
8051 /*! LMDA_SYS_FAIL - EdgeLock system failure reset mask
8052  *  0b1..Mask reset
8053  *  0b0..Unmask reset
8054  */
8055 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK)
8056 
8057 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_32K_MASK (0x10U)
8058 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_32K_SHIFT (4U)
8059 /*! NOCLK_32K - EdgeLock 32k clock loss reset mask
8060  *  0b1..Mask reset
8061  *  0b0..Unmask reset
8062  */
8063 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_32K_MASK)
8064 
8065 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_RESET_REQ_MASK (0x20U)
8066 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT (5U)
8067 /*! LMDA_RESET_REQ - EdgeLock LMDA reset request mask
8068  *  0b1..Mask reset
8069  *  0b0..Unmask reset
8070  */
8071 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_RESET_REQ_MASK)
8072 
8073 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK (0x40U)
8074 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT (6U)
8075 /*! LMDA_32K_RESET_REQ - EdgeLock LMDA reset request from 32k clock domain mask
8076  *  0b1..Mask reset
8077  *  0b0..Unmask reset
8078  */
8079 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK)
8080 
8081 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF1_MASK (0x80U)
8082 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF1_SHIFT (7U)
8083 /*! NOCLK_REF1 - EdgeLock CM33 root clock loss reset mask
8084  *  0b1..Mask reset
8085  *  0b0..Unmask reset
8086  */
8087 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF1_MASK)
8088 
8089 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF2_MASK (0x100U)
8090 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF2_SHIFT (8U)
8091 /*! NOCLK_REF2 - EdgeLock OSC 24Mhz clock loss reset mask
8092  *  0b1..Mask reset
8093  *  0b0..Unmask reset
8094  */
8095 #define BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_RESET_REQ_MASK_NOCLK_REF2_MASK)
8096 /*! @} */
8097 
8098 /*! @name EDGELOCK_IRQ_MASK - EdgeLock IRQ request mask */
8099 /*! @{ */
8100 
8101 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_WDG_RESET_MASK (0x1U)
8102 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_WDG_RESET_SHIFT (0U)
8103 /*! WDG_RESET - EdgeLock Wdog reset interrupt mask
8104  *  0b0..Unmask interrupt
8105  *  0b1..Mask interrupt
8106  */
8107 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_WDG_RESET_MASK)
8108 
8109 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_PUF_RESET_MASK (0x2U)
8110 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_PUF_RESET_SHIFT (1U)
8111 /*! PUF_RESET - EdgeLock PUF reset interrupt mask
8112  *  0b0..Unmask interrupt
8113  *  0b1..Mask interrupt
8114  */
8115 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_PUF_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_PUF_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_PUF_RESET_MASK)
8116 
8117 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LC_BRICKED_MASK (0x4U)
8118 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LC_BRICKED_SHIFT (2U)
8119 /*! LC_BRICKED - EdgeLock LMDA life cycle bricked interrupt mask
8120  *  0b0..Unmask interrupt
8121  *  0b1..Mask interrupt
8122  */
8123 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LC_BRICKED_MASK)
8124 
8125 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_SYS_FAIL_MASK (0x8U)
8126 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_SYS_FAIL_SHIFT (3U)
8127 /*! LMDA_SYS_FAIL - EdgeLock system failure interrupt mask
8128  *  0b0..Unmask interrupt
8129  *  0b1..Mask interrupt
8130  */
8131 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_SYS_FAIL_MASK)
8132 
8133 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_32K_MASK (0x10U)
8134 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_32K_SHIFT (4U)
8135 /*! NOCLK_32K - EdgeLock 32k clock loss interrupt mask
8136  *  0b0..Unmask interrupt
8137  *  0b1..Mask interrupt
8138  */
8139 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_32K_MASK)
8140 
8141 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_RESET_REQ_MASK (0x20U)
8142 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_RESET_REQ_SHIFT (5U)
8143 /*! LMDA_RESET_REQ - EdgeLock LMDA reset request interrupt mask
8144  *  0b0..Unmask interrupt
8145  *  0b1..Mask interrupt
8146  */
8147 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_RESET_REQ_MASK)
8148 
8149 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_32K_RESET_REQ_MASK (0x40U)
8150 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT (6U)
8151 /*! LMDA_32K_RESET_REQ - EdgeLock LMDA reset request from 32k clock domain interrupt mask
8152  *  0b0..Unmask interrupt
8153  *  0b1..Mask interrupt
8154  */
8155 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_LMDA_32K_RESET_REQ_MASK)
8156 
8157 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF1_MASK (0x80U)
8158 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF1_SHIFT (7U)
8159 /*! NOCLK_REF1 - EdgeLock cm33 root clock loss interrupt mask
8160  *  0b0..Unmask interrupt
8161  *  0b1..Mask interrupt
8162  */
8163 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF1_MASK)
8164 
8165 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF2_MASK (0x100U)
8166 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF2_SHIFT (8U)
8167 /*! NOCLK_REF2 - EdgeLock OSC 24Mhz clock loss interrupt mask
8168  *  0b0..Unmask interrupt
8169  *  0b1..Mask interrupt
8170  */
8171 #define BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_IRQ_MASK_NOCLK_REF2_MASK)
8172 /*! @} */
8173 
8174 /*! @name M33_CFG - M33 Configuration */
8175 /*! @{ */
8176 
8177 #define BLK_CTRL_S_AONMIX_M33_CFG_WAIT_MASK      (0x4U)
8178 #define BLK_CTRL_S_AONMIX_M33_CFG_WAIT_SHIFT     (2U)
8179 /*! WAIT - M33 CPU WAIT */
8180 #define BLK_CTRL_S_AONMIX_M33_CFG_WAIT(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_CFG_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_M33_CFG_WAIT_MASK)
8181 
8182 #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK  (0x18U)
8183 #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT (3U)
8184 /*! TCM_SIZE - M33 TCM SIZE
8185  *  0b11..Reserved
8186  *  0b10..Double Sys TCM, 256KB Sys TCM
8187  *  0b01..Double Code TCM, 256KB Code TCM
8188  *  0b00..Regular TCM, 128KB Code TCM and 128KB Sys TCM
8189  */
8190 #define BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT)) & BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK)
8191 
8192 #define BLK_CTRL_S_AONMIX_M33_CFG_CORECLK_FORCE_ON_MASK (0x20U)
8193 #define BLK_CTRL_S_AONMIX_M33_CFG_CORECLK_FORCE_ON_SHIFT (5U)
8194 /*! CORECLK_FORCE_ON - Force CM33 core clock on in WAIT mode
8195  *  0b0..CM33 core clock is off in WAIT mode
8196  *  0b1..CM33 core clock is on in WAIT mode
8197  */
8198 #define BLK_CTRL_S_AONMIX_M33_CFG_CORECLK_FORCE_ON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_CFG_CORECLK_FORCE_ON_SHIFT)) & BLK_CTRL_S_AONMIX_M33_CFG_CORECLK_FORCE_ON_MASK)
8199 /*! @} */
8200 
8201 /*! @name M33_INITSVTOR - M33 INITSVTOR */
8202 /*! @{ */
8203 
8204 #define BLK_CTRL_S_AONMIX_M33_INITSVTOR_INITSVTOR_MASK (0x1FFFFFFU)
8205 #define BLK_CTRL_S_AONMIX_M33_INITSVTOR_INITSVTOR_SHIFT (0U)
8206 /*! INITSVTOR - M33 INITSVTOR */
8207 #define BLK_CTRL_S_AONMIX_M33_INITSVTOR_INITSVTOR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_INITSVTOR_INITSVTOR_SHIFT)) & BLK_CTRL_S_AONMIX_M33_INITSVTOR_INITSVTOR_MASK)
8208 /*! @} */
8209 
8210 /*! @name M33_INITNSVTOR - M33 INITNSVTOR */
8211 /*! @{ */
8212 
8213 #define BLK_CTRL_S_AONMIX_M33_INITNSVTOR_INITNSVTOR_MASK (0x1FFFFFFU)
8214 #define BLK_CTRL_S_AONMIX_M33_INITNSVTOR_INITNSVTOR_SHIFT (0U)
8215 /*! INITNSVTOR - M33 INITNSVTOR */
8216 #define BLK_CTRL_S_AONMIX_M33_INITNSVTOR_INITNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M33_INITNSVTOR_INITNSVTOR_SHIFT)) & BLK_CTRL_S_AONMIX_M33_INITNSVTOR_INITNSVTOR_MASK)
8217 /*! @} */
8218 
8219 /*! @name M7_CFG - M7 Configuration */
8220 /*! @{ */
8221 
8222 #define BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK   (0x7U)
8223 #define BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_SHIFT  (0U)
8224 /*! TCM_SIZE - M7 TCM SIZE
8225  *  0b111..Reserved
8226  *  0b110..Reserved
8227  *  0b101..HALF DTCM, 384KB ITCM and 128KB DTCM
8228  *  0b100..HALF ITCM, 128KB ITCM and 384KB DTCM
8229  *  0b010..Double DTCM, 512KB DTCM
8230  *  0b001..Double ITCM, 512KB ITCM
8231  *  0b000..Regular TCM, 256KB ITCM and 256KB DTCM
8232  */
8233 #define BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_SHIFT)) & BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK)
8234 
8235 #define BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK       (0x10U)
8236 #define BLK_CTRL_S_AONMIX_M7_CFG_WAIT_SHIFT      (4U)
8237 /*! WAIT - M7 CPUWAIT */
8238 #define BLK_CTRL_S_AONMIX_M7_CFG_WAIT(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M7_CFG_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK)
8239 
8240 #define BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_MASK (0x20U)
8241 #define BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_SHIFT (5U)
8242 /*! CORECLK_FORCE_ON - Force CM7 core clock on in WAIT mode
8243  *  0b0..CM7 core clock is off in WAIT mode
8244  *  0b1..CM7 core clock is on in WAIT mode
8245  */
8246 #define BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_SHIFT)) & BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_MASK)
8247 
8248 #define BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_MASK (0x40U)
8249 #define BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_SHIFT (6U)
8250 /*! HCLK_FORCE_ON - CM7 platform AHB clock enable */
8251 #define BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_SHIFT)) & BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_MASK)
8252 
8253 #define BLK_CTRL_S_AONMIX_M7_CFG_INITVTOR_MASK   (0xFFFFFF80U)
8254 #define BLK_CTRL_S_AONMIX_M7_CFG_INITVTOR_SHIFT  (7U)
8255 #define BLK_CTRL_S_AONMIX_M7_CFG_INITVTOR(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_M7_CFG_INITVTOR_SHIFT)) & BLK_CTRL_S_AONMIX_M7_CFG_INITVTOR_MASK)
8256 /*! @} */
8257 
8258 /*! @name AXBS_AON_CTRL - AXBS_AON_CTRL */
8259 /*! @{ */
8260 
8261 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_MASK (0x1U)
8262 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_SHIFT (0U)
8263 /*! FORCE_ROUND_ROBIN - AXBS_AON Force Round Robin
8264  *  0b0..Enable force round robin(default)
8265  *  0b1..Disable force round robin
8266  */
8267 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_MASK)
8268 
8269 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_MASK (0x2U)
8270 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_SHIFT (1U)
8271 /*! M0_HIGH_PRIORITY - M0 High Priority Control Bit
8272  *  0b0..Default Priority
8273  *  0b1..High Priority
8274  */
8275 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_MASK)
8276 
8277 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_MASK (0x4U)
8278 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_SHIFT (2U)
8279 /*! M1_HIGH_PRIORITY - M1 High Priority Control Bit
8280  *  0b0..Default Priority
8281  *  0b1..High Priority
8282  */
8283 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_MASK)
8284 
8285 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_MASK (0x8U)
8286 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_SHIFT (3U)
8287 /*! M2_HIGH_PRIORITY - M2 High Priority Control Bit
8288  *  0b0..Default Priority
8289  *  0b1..High Priority
8290  */
8291 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_MASK)
8292 
8293 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_MASK (0x10U)
8294 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_SHIFT (4U)
8295 /*! M3_HIGH_PRIORITY - M3 High Priority Control Bit
8296  *  0b0..Default Priority
8297  *  0b1..High Priority
8298  */
8299 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_MASK)
8300 
8301 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_MASK (0x20U)
8302 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_SHIFT (5U)
8303 /*! M4_HIGH_PRIORITY - M4 High Priority Control Bit
8304  *  0b0..Default Priority
8305  *  0b1..High Priority
8306  */
8307 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_MASK)
8308 
8309 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M5_HIGH_PRIORITY_MASK (0x40U)
8310 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M5_HIGH_PRIORITY_SHIFT (6U)
8311 /*! M5_HIGH_PRIORITY - M5 High Priority Control Bit
8312  *  0b0..Default Priority
8313  *  0b1..High Priority
8314  */
8315 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M5_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M5_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M5_HIGH_PRIORITY_MASK)
8316 
8317 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M6_HIGH_PRIORITY_MASK (0x80U)
8318 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M6_HIGH_PRIORITY_SHIFT (7U)
8319 /*! M6_HIGH_PRIORITY - M6 High Priority Control Bit
8320  *  0b0..Default Priority
8321  *  0b1..High Priority
8322  */
8323 #define BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M6_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M6_HIGH_PRIORITY_SHIFT)) & BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M6_HIGH_PRIORITY_MASK)
8324 /*! @} */
8325 
8326 /*! @name DAP_ACCESS_STKYBIT - DAP Access Sticky Bit */
8327 /*! @{ */
8328 
8329 #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_DAP_CTR_MASK (0x1U)
8330 #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_DAP_CTR_SHIFT (0U)
8331 /*! DAP_CTR - DAP access grant bit controlled by Cortex-M33 ROM, once set "1" will kept "1" unless there is a reset.
8332  *  0b0..DAP access is not granted by ROM
8333  *  0b1..DAP access is granted by ROM
8334  */
8335 #define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_DAP_CTR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_DAP_CTR_SHIFT)) & BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_DAP_CTR_MASK)
8336 /*! @} */
8337 
8338 /*! @name LP_HANDSHAKE - Low power handshake enable */
8339 /*! @{ */
8340 
8341 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_RESET_HS_EN_MASK (0x1U)
8342 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_RESET_HS_EN_SHIFT (0U)
8343 /*! CM33_RESET_HS_EN - CM33 reset handshake enable
8344  *  0b1..Handshake is enabled
8345  *  0b0..Handshake is not enabled
8346  */
8347 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_RESET_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_RESET_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_RESET_HS_EN_MASK)
8348 
8349 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_RESET_HS_EN_MASK (0x2U)
8350 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_RESET_HS_EN_SHIFT (1U)
8351 /*! CM7_RESET_HS_EN - CM7 reset handshake enable
8352  *  0b1..Handshake is enabled
8353  *  0b0..Handshake is not enabled
8354  */
8355 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_RESET_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_RESET_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_RESET_HS_EN_MASK)
8356 
8357 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_SUSPEND_HS_EN_MASK (0x4U)
8358 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_SUSPEND_HS_EN_SHIFT (2U)
8359 /*! CM7_SUSPEND_HS_EN - CM7 suspend exit reset handshake enable
8360  *  0b1..Handshake is enabled
8361  *  0b0..Handshake is not enabled
8362  */
8363 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_SUSPEND_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_SUSPEND_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_SUSPEND_HS_EN_MASK)
8364 
8365 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_RESET_HS_EN_MASK (0x8U)
8366 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_RESET_HS_EN_SHIFT (3U)
8367 /*! AONMIX_RESET_HS_EN - AONMIX reset handshake enable
8368  *  0b1..Handshake is enabled
8369  *  0b0..Handshake is not enabled
8370  */
8371 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_RESET_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_RESET_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_RESET_HS_EN_MASK)
8372 
8373 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_RESET_HS_EN_MASK (0x10U)
8374 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_RESET_HS_EN_SHIFT (4U)
8375 /*! WAKEUPMIX_RESET_HS_EN - Wakeupmix reset handshake enable
8376  *  0b1..Handshake is enabled
8377  *  0b0..Handshake is not enabled
8378  */
8379 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_RESET_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_RESET_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_RESET_HS_EN_MASK)
8380 
8381 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_RESET_HS_EN_MASK (0x20U)
8382 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_RESET_HS_EN_SHIFT (5U)
8383 /*! MEGAMIX_RESET_HS_EN - Megamix reset handshake enable
8384  *  0b1..Handshake is enabled
8385  *  0b0..Handshake is not enabled
8386  */
8387 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_RESET_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_RESET_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_RESET_HS_EN_MASK)
8388 
8389 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_LPM_HS_EN_MASK (0x40U)
8390 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_LPM_HS_EN_SHIFT (6U)
8391 /*! MEGAMIX_LPM_HS_EN - Megamix low power mode exit reset handshake enable
8392  *  0b1..Handshake is enabled
8393  *  0b0..Handshake is not enabled
8394  */
8395 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_LPM_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_LPM_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEGAMIX_LPM_HS_EN_MASK)
8396 
8397 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_OFF_HS_EN_MASK (0x80U)
8398 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_OFF_HS_EN_SHIFT (7U)
8399 /*! EDGELOCK_CLK_OFF_HS_EN - EDGELOCK clock off handshake enable
8400  *  0b1..Handshake is enabled
8401  *  0b0..Handshake is not enabled
8402  */
8403 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_OFF_HS_EN_MASK)
8404 
8405 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_OFF_HS_EN_MASK (0x100U)
8406 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_OFF_HS_EN_SHIFT (8U)
8407 /*! CM33_CLK_OFF_HS_EN - CM33 clock off handshake enable
8408  *  0b1..Handshake is enabled
8409  *  0b0..Handshake is not enabled
8410  */
8411 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_OFF_HS_EN_MASK)
8412 
8413 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_OFF_HS_EN_MASK (0x200U)
8414 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_OFF_HS_EN_SHIFT (9U)
8415 /*! CM7_CLK_OFF_HS_EN - CM7 clock off handshake enable
8416  *  0b1..Handshake is enabled
8417  *  0b0..Handshake is not enabled
8418  */
8419 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_OFF_HS_EN_MASK)
8420 
8421 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_OFF_HS_EN_MASK (0x400U)
8422 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_OFF_HS_EN_SHIFT (10U)
8423 /*! TRDC_CLK_OFF_HS_EN - TRDC clock off handshake enable
8424  *  0b1..Handshake is enabled
8425  *  0b0..Handshake is not enabled
8426  */
8427 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_OFF_HS_EN_MASK)
8428 
8429 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_OFF_HS_EN_MASK (0x800U)
8430 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_OFF_HS_EN_SHIFT (11U)
8431 /*! IEE_CLK_OFF_HS_EN - IEE clock off handshake enable
8432  *  0b1..Handshake is enabled
8433  *  0b0..Handshake is not enabled
8434  */
8435 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_OFF_HS_EN_MASK)
8436 
8437 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_OFF_HS_EN_MASK (0x1000U)
8438 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_OFF_HS_EN_SHIFT (12U)
8439 /*! OTFAD1_CLK_OFF_HS_EN - OTFAD1 clock off handshake enable
8440  *  0b1..Handshake is enabled
8441  *  0b0..Handshake is not enabled
8442  */
8443 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_OFF_HS_EN_MASK)
8444 
8445 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_OFF_HS_EN_MASK (0x2000U)
8446 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_OFF_HS_EN_SHIFT (13U)
8447 /*! OTFAD2_CLK_OFF_HS_EN - OTFAD2 clock off handshake enable
8448  *  0b1..Handshake is enabled
8449  *  0b0..Handshake is not enabled
8450  */
8451 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_OFF_HS_EN_MASK)
8452 
8453 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_ON_HS_EN_MASK (0x4000U)
8454 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_ON_HS_EN_SHIFT (14U)
8455 /*! EDGELOCK_CLK_ON_HS_EN - EDGELOCK clock on handshake enable
8456  *  0b1..Handshake is enabled
8457  *  0b0..Handshake is not enabled
8458  */
8459 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_EDGELOCK_CLK_ON_HS_EN_MASK)
8460 
8461 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_ON_HS_EN_MASK (0x8000U)
8462 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_ON_HS_EN_SHIFT (15U)
8463 /*! CM33_CLK_ON_HS_EN - CM33 clock on handshake enable
8464  *  0b1..Handshake is enabled
8465  *  0b0..Handshake is not enabled
8466  */
8467 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM33_CLK_ON_HS_EN_MASK)
8468 
8469 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_ON_HS_EN_MASK (0x10000U)
8470 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_ON_HS_EN_SHIFT (16U)
8471 /*! CM7_CLK_ON_HS_EN - CM7 clock on handshake enable
8472  *  0b1..Handshake is enabled
8473  *  0b0..Handshake is not enabled
8474  */
8475 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CM7_CLK_ON_HS_EN_MASK)
8476 
8477 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_ON_HS_EN_MASK (0x20000U)
8478 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_ON_HS_EN_SHIFT (17U)
8479 /*! TRDC_CLK_ON_HS_EN - TRDC clock on handshake enable
8480  *  0b1..Handshake is enabled
8481  *  0b0..Handshake is not enabled
8482  */
8483 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_TRDC_CLK_ON_HS_EN_MASK)
8484 
8485 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_ON_HS_EN_MASK (0x40000U)
8486 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_ON_HS_EN_SHIFT (18U)
8487 /*! IEE_CLK_ON_HS_EN - IEE clock on handshake enable
8488  *  0b1..Handshake is enabled
8489  *  0b0..Handshake is not enabled
8490  */
8491 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_IEE_CLK_ON_HS_EN_MASK)
8492 
8493 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_ON_HS_EN_MASK (0x80000U)
8494 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_ON_HS_EN_SHIFT (19U)
8495 /*! OTFAD1_CLK_ON_HS_EN - OTFAD1 clock on handshake enable
8496  *  0b1..Handshake is enabled
8497  *  0b0..Handshake is not enabled
8498  */
8499 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD1_CLK_ON_HS_EN_MASK)
8500 
8501 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_ON_HS_EN_MASK (0x100000U)
8502 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_ON_HS_EN_SHIFT (20U)
8503 /*! OTFAD2_CLK_ON_HS_EN - OTFAD2 clock on handshake enable
8504  *  0b1..Handshake is enabled
8505  *  0b0..Handshake is not enabled
8506  */
8507 #define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_OTFAD2_CLK_ON_HS_EN_MASK)
8508 /*! @} */
8509 
8510 /*! @name EDGELOCK_HALT_ST - EdgeLock halt status */
8511 /*! @{ */
8512 
8513 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_ACK_MASK (0x1U)
8514 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_ACK_SHIFT (0U)
8515 /*! EDGELOCK_HALT_ACK - EdgeLock halt and clock status
8516  *  0b0..EdgeLock is not fully halted and its clocks must be enabled
8517  *  0b1..EdgeLock is fully halted indicating clocks may be removed
8518  */
8519 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_ACK_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_ACK_MASK)
8520 
8521 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_EXIT_IRQ_CLR_MASK (0x100U)
8522 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_EXIT_IRQ_CLR_SHIFT (8U)
8523 /*! EDGELOCK_HALT_EXIT_IRQ_CLR - EdgeLock halt exit interrupt clear
8524  *  0b0..Remove the clear signal. This bit is not self-clearing and need SW to clear.
8525  *  0b1..Clear EdgeLock halt exit interrupt
8526  */
8527 #define BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_EXIT_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_EXIT_IRQ_CLR_SHIFT)) & BLK_CTRL_S_AONMIX_EDGELOCK_HALT_ST_EDGELOCK_HALT_EXIT_IRQ_CLR_MASK)
8528 /*! @} */
8529 
8530 /*! @name ECC_MEM_INIT - ECC memory hardware initialization */
8531 /*! @{ */
8532 
8533 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM1_INIT_DONE_MASK (0x10000U)
8534 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM1_INIT_DONE_SHIFT (16U)
8535 /*! OCRAM1_INIT_DONE - OCRAM1 initialization status
8536  *  0b0..OCRAM1 memory is under initialization
8537  *  0b1..OCRAM1 memory initialization is complete
8538  */
8539 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM1_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM1_INIT_DONE_SHIFT)) & BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM1_INIT_DONE_MASK)
8540 
8541 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM2_INIT_DONE_MASK (0x1000000U)
8542 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM2_INIT_DONE_SHIFT (24U)
8543 /*! OCRAM2_INIT_DONE - OCRAM2 initialization status
8544  *  0b0..OCRAM2 memory is under initialization
8545  *  0b1..OCRAM2 memory initialization is complete
8546  */
8547 #define BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM2_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM2_INIT_DONE_SHIFT)) & BLK_CTRL_S_AONMIX_ECC_MEM_INIT_OCRAM2_INIT_DONE_MASK)
8548 /*! @} */
8549 
8550 /*! @name IOMUXC_DOMAIN_CFG - IOMUXC domain configure */
8551 /*! @{ */
8552 
8553 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID0_MASK (0xFU)
8554 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID0_SHIFT (0U)
8555 /*! DID0 - Domain ID 0 */
8556 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID0_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID0_MASK)
8557 
8558 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID1_MASK (0xF0U)
8559 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID1_SHIFT (4U)
8560 /*! DID1 - Domain ID 1 */
8561 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID1_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID1_MASK)
8562 
8563 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID2_MASK (0xF00U)
8564 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID2_SHIFT (8U)
8565 /*! DID2 - Domain ID 2 */
8566 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID2_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID2_MASK)
8567 
8568 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID3_MASK (0xF000U)
8569 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID3_SHIFT (12U)
8570 /*! DID3 - Domain ID 3 */
8571 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID3_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_DID3_MASK)
8572 
8573 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_LOCK_MASK (0x80000000U)
8574 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_LOCK_SHIFT (31U)
8575 /*! LOCK - Lock bit */
8576 #define BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_LOCK_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_DOMAIN_CFG_LOCK_MASK)
8577 /*! @} */
8578 
8579 /*! @name IOMUXC_AON_DOMAIN_CFG - IOMUXC_AON domain configure */
8580 /*! @{ */
8581 
8582 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID0_MASK (0xFU)
8583 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID0_SHIFT (0U)
8584 /*! DID0 - Domain ID 0 */
8585 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID0_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID0_MASK)
8586 
8587 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID1_MASK (0xF0U)
8588 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID1_SHIFT (4U)
8589 /*! DID1 - Domain ID 1 */
8590 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID1_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID1_MASK)
8591 
8592 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID2_MASK (0xF00U)
8593 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID2_SHIFT (8U)
8594 /*! DID2 - Domain ID 2 */
8595 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID2_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID2_MASK)
8596 
8597 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID3_MASK (0xF000U)
8598 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID3_SHIFT (12U)
8599 /*! DID3 - Domain ID 3 */
8600 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID3_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_DID3_MASK)
8601 
8602 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_LOCK_MASK (0x80000000U)
8603 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_LOCK_SHIFT (31U)
8604 /*! LOCK - Lock bit */
8605 #define BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_LOCK_SHIFT)) & BLK_CTRL_S_AONMIX_IOMUXC_AON_DOMAIN_CFG_LOCK_MASK)
8606 /*! @} */
8607 
8608 /*! @name NMI_CTRL - NMI control */
8609 /*! @{ */
8610 
8611 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M7_NMI_MASK_MASK (0x1U)
8612 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M7_NMI_MASK_SHIFT (0U)
8613 /*! M7_NMI_MASK - Mask CM7 NMI pin input
8614  *  0b0..NMI input from IO to CM7 is not blocked
8615  *  0b1..NMI input from IO to CM7 is blocked
8616  */
8617 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_NMI_CTRL_M7_NMI_MASK_SHIFT)) & BLK_CTRL_S_AONMIX_NMI_CTRL_M7_NMI_MASK_MASK)
8618 
8619 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M33_NMI_MASK_MASK (0x2U)
8620 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M33_NMI_MASK_SHIFT (1U)
8621 /*! M33_NMI_MASK - Mask CM33 NMI pin input
8622  *  0b0..NMI input from IO to CM33 is not blocked
8623  *  0b1..NMI input from IO to CM33 is blocked
8624  */
8625 #define BLK_CTRL_S_AONMIX_NMI_CTRL_M33_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_NMI_CTRL_M33_NMI_MASK_SHIFT)) & BLK_CTRL_S_AONMIX_NMI_CTRL_M33_NMI_MASK_MASK)
8626 /*! @} */
8627 
8628 /*! @name S401_NOCLK_CLEAR_CTRL - s401_ipi_noclk_ref1 clear control */
8629 /*! @{ */
8630 
8631 #define BLK_CTRL_S_AONMIX_S401_NOCLK_CLEAR_CTRL_ref1_slow_clear_MASK (0x1U)
8632 #define BLK_CTRL_S_AONMIX_S401_NOCLK_CLEAR_CTRL_ref1_slow_clear_SHIFT (0U)
8633 /*! ref1_slow_clear - clear the interrupt or reset source */
8634 #define BLK_CTRL_S_AONMIX_S401_NOCLK_CLEAR_CTRL_ref1_slow_clear(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_S401_NOCLK_CLEAR_CTRL_ref1_slow_clear_SHIFT)) & BLK_CTRL_S_AONMIX_S401_NOCLK_CLEAR_CTRL_ref1_slow_clear_MASK)
8635 /*! @} */
8636 
8637 
8638 /*!
8639  * @}
8640  */ /* end of group BLK_CTRL_S_AONMIX_Register_Masks */
8641 
8642 
8643 /* BLK_CTRL_S_AONMIX - Peripheral instance base addresses */
8644 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
8645   /** Peripheral BLK_CTRL_S_AONMIX base address */
8646   #define BLK_CTRL_S_AONMIX_BASE                   (0x544F0000u)
8647   /** Peripheral BLK_CTRL_S_AONMIX base address */
8648   #define BLK_CTRL_S_AONMIX_BASE_NS                (0x444F0000u)
8649   /** Peripheral BLK_CTRL_S_AONMIX base pointer */
8650   #define BLK_CTRL_S_AONMIX                        ((BLK_CTRL_S_AONMIX_Type *)BLK_CTRL_S_AONMIX_BASE)
8651   /** Peripheral BLK_CTRL_S_AONMIX base pointer */
8652   #define BLK_CTRL_S_AONMIX_NS                     ((BLK_CTRL_S_AONMIX_Type *)BLK_CTRL_S_AONMIX_BASE_NS)
8653   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base addresses */
8654   #define BLK_CTRL_S_AONMIX_BASE_ADDRS             { BLK_CTRL_S_AONMIX_BASE }
8655   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base pointers */
8656   #define BLK_CTRL_S_AONMIX_BASE_PTRS              { BLK_CTRL_S_AONMIX }
8657   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base addresses */
8658   #define BLK_CTRL_S_AONMIX_BASE_ADDRS_NS          { BLK_CTRL_S_AONMIX_BASE_NS }
8659   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base pointers */
8660   #define BLK_CTRL_S_AONMIX_BASE_PTRS_NS           { BLK_CTRL_S_AONMIX_NS }
8661 #else
8662   /** Peripheral BLK_CTRL_S_AONMIX base address */
8663   #define BLK_CTRL_S_AONMIX_BASE                   (0x444F0000u)
8664   /** Peripheral BLK_CTRL_S_AONMIX base pointer */
8665   #define BLK_CTRL_S_AONMIX                        ((BLK_CTRL_S_AONMIX_Type *)BLK_CTRL_S_AONMIX_BASE)
8666   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base addresses */
8667   #define BLK_CTRL_S_AONMIX_BASE_ADDRS             { BLK_CTRL_S_AONMIX_BASE }
8668   /** Array initializer of BLK_CTRL_S_AONMIX peripheral base pointers */
8669   #define BLK_CTRL_S_AONMIX_BASE_PTRS              { BLK_CTRL_S_AONMIX }
8670 #endif
8671 
8672 /*!
8673  * @}
8674  */ /* end of group BLK_CTRL_S_AONMIX_Peripheral_Access_Layer */
8675 
8676 
8677 /* ----------------------------------------------------------------------------
8678    -- BLK_CTRL_WAKEUPMIX Peripheral Access Layer
8679    ---------------------------------------------------------------------------- */
8680 
8681 /*!
8682  * @addtogroup BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer BLK_CTRL_WAKEUPMIX Peripheral Access Layer
8683  * @{
8684  */
8685 
8686 /** BLK_CTRL_WAKEUPMIX - Register Layout Typedef */
8687 typedef struct {
8688        uint8_t RESERVED_0[4];
8689   __IO uint32_t IPG_DEBUG1;                        /**< IPG DEBUG mask bit, offset: 0x4 */
8690   __IO uint32_t IPG_DEBUG2;                        /**< IPG DEBUG mask bit, offset: 0x8 */
8691   __IO uint32_t IPG_DEBUG3;                        /**< IPG DEBUG mask bit, offset: 0xC */
8692        uint8_t RESERVED_1[4];
8693   __IO uint32_t SSI;                               /**< SSI master low power mode control, offset: 0x14 */
8694   __IO uint32_t ECAT_MISC_CFG;                     /**< EtherCAT miscellaneous configuration, offset: 0x18 */
8695   __IO uint32_t DEXSC_ERR;                         /**< DEXSC error response configuration, offset: 0x1C */
8696   __IO uint32_t USBPHY_MISC_CTRL;                  /**< USBPHY miscellaneous control, offset: 0x20 */
8697   __IO uint32_t NETC_PORT_MISC_CFG;                /**< NETC Port miscellaneous configuration, offset: 0x24 */
8698   __IO uint32_t M7_NMI_CLR;                        /**< M7 NMI interrupt clear register, offset: 0x28 */
8699        uint8_t RESERVED_2[4];
8700   __IO uint32_t QTIMER_CTRL1;                      /**< Qtimer miscellaneous control register 1, offset: 0x30 */
8701   __IO uint32_t QTIMER_CTRL2;                      /**< Qtimer miscellaneous control register 2, offset: 0x34 */
8702   __IO uint32_t SAI2_MCLK_CTRL;                    /**< SAI2 MCLK control register, offset: 0x38 */
8703   __IO uint32_t SAI3_MCLK_CTRL;                    /**< SAI3 MCLK control register, offset: 0x3C */
8704   __IO uint32_t SAI4_MCLK_CTRL;                    /**< SAI4 MCLK control register, offset: 0x40 */
8705   __IO uint32_t XBAR_DIR_CTRL1;                    /**< XBAR IO direction control register, offset: 0x44 */
8706   __IO uint32_t XBAR_DIR_CTRL2;                    /**< XBAR IO direction control register, offset: 0x48 */
8707   __IO uint32_t LPIT_TRIG_SEL;                     /**< LPIT trigger input select register, offset: 0x4C */
8708   __IO uint32_t AXI_ATTR_CFG;                      /**< AXI bus attribute configuration register, offset: 0x50 */
8709   __IO uint32_t SRAMCR0;                           /**< SRAM Control Register 0, offset: 0x54 */
8710   __IO uint32_t SRAMCR1;                           /**< SRAM Control Register 1, offset: 0x58 */
8711        uint8_t RESERVED_3[4];
8712   __IO uint32_t SLAVE_STOP_MODE_CFG;               /**< Slave stop mode configure register, offset: 0x60 */
8713        uint8_t RESERVED_4[16];
8714   __IO uint32_t I3C2_ASYNC_WAKEUP_CTRL;            /**< I3C2 async wakeup control register, offset: 0x74 */
8715   __IO uint32_t XBAR_AOI_WE;                       /**< XBAR and AOI write protect register, offset: 0x78 */
8716   __IO uint32_t XBAR_TRIG_SYNC_CTRL1;              /**< XBAR trigger synchronizer control register1, offset: 0x7C */
8717   __IO uint32_t XBAR_TRIG_SYNC_CTRL2;              /**< XBAR trigger synchronizer control register2, offset: 0x80 */
8718        uint8_t RESERVED_5[124];
8719   __IO uint32_t NETC_LINK_CFG[5];                  /**< NETC link configuration for port0..NETC link configuration for port4, array offset: 0x100, array step: 0x4 */
8720   __IO uint32_t NETC_REVMII_DLL[5];                /**< NETC RevMII RGMII delay line configuration for port0..NETC RevMII RGMII delay line configuration for port4, array offset: 0x114, array step: 0x4 */
8721        uint8_t RESERVED_6[8];
8722   __IO uint32_t SAFETY_CLK_MON_CS;                 /**< Safety clock monitor control and status register, offset: 0x130 */
8723   __IO uint32_t SAFETY_CLK_MON_TH;                 /**< Safety clock monitor threshold register, offset: 0x134 */
8724        uint8_t RESERVED_7[8];
8725   __IO uint32_t EMC_B1_IO_CTRL;                    /**< GPIO_EMC_B1 bank IO control, offset: 0x140 */
8726   __IO uint32_t EMC_B2_IO_CTRL;                    /**< GPIO_EMC_B2 bank IO control, offset: 0x144 */
8727   __IO uint32_t SD_B1_IO_CTRL;                     /**< GPIO_SD_B1 bank IO control, offset: 0x148 */
8728   __IO uint32_t SD_B2_IO_CTRL;                     /**< GPIO_SD_B2 bank IO control, offset: 0x14C */
8729   __IO uint32_t GPIO_B1_IO_CTRL;                   /**< GPIO_B1 bank IO control, offset: 0x150 */
8730   __IO uint32_t GPIO_B2_IO_CTRL;                   /**< GPIO_B2 bank IO control, offset: 0x154 */
8731   __IO uint32_t MISC_IO_CTRL;                      /**< Miscellaneous control register of IO, offset: 0x158 */
8732 } BLK_CTRL_WAKEUPMIX_Type;
8733 
8734 /* ----------------------------------------------------------------------------
8735    -- BLK_CTRL_WAKEUPMIX Register Masks
8736    ---------------------------------------------------------------------------- */
8737 
8738 /*!
8739  * @addtogroup BLK_CTRL_WAKEUPMIX_Register_Masks BLK_CTRL_WAKEUPMIX Register Masks
8740  * @{
8741  */
8742 
8743 /*! @name IPG_DEBUG1 - IPG DEBUG mask bit */
8744 /*! @{ */
8745 
8746 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_CAN2_MASK (0x1U)
8747 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_CAN2_SHIFT (0U)
8748 /*! M33_CAN2 - CAN2 debug halted mode with M7
8749  *  0b1..CAN2 enters debug halted mode when CM33 is debug halted
8750  *  0b0..CAN2 does not enter debug halted mode with CM33
8751  */
8752 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_CAN2_MASK)
8753 
8754 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_EDMA4_MASK (0x2U)
8755 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_EDMA4_SHIFT (1U)
8756 /*! M33_EDMA4 - EDMA4 debug halted mode with M33
8757  *  0b1..EDMA4 enters debug halted mode when CM33 is debug halted
8758  *  0b0..EDMA4 does not enter debug halted mode with CM33
8759  */
8760 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_EDMA4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_EDMA4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_EDMA4_MASK)
8761 
8762 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO1_MASK (0x4U)
8763 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO1_SHIFT (2U)
8764 /*! M33_FLEXIO1 - FLEXIO1 debug halted mode with M33
8765  *  0b1..FLEXIO1 enters debug halted mode when CM33 is debug halted
8766  *  0b0..FLEXIO1 does not enter debug halted mode with CM33
8767  */
8768 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO1_MASK)
8769 
8770 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO2_MASK (0x8U)
8771 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO2_SHIFT (3U)
8772 /*! M33_FLEXIO2 - FLEXIO2 debug halted mode with M33
8773  *  0b1..FLEXIO2 enters debug halted mode when CM33 is debug halted
8774  *  0b0..FLEXIO2 does not enter debug halted mode with CM33
8775  */
8776 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_FLEXIO2_MASK)
8777 
8778 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C3_MASK (0x10U)
8779 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C3_SHIFT (4U)
8780 /*! M33_LPI2C3 - LPI2C3 debug halted mode with M33
8781  *  0b1..enters debug halted mode when CM33 is debug halted
8782  *  0b0..LPI2C3 does not enter debug halted mode with CM33
8783  */
8784 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C3_MASK)
8785 
8786 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C4_MASK (0x20U)
8787 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C4_SHIFT (5U)
8788 /*! M33_LPI2C4 - LPI2C4 debug halted mode with M33
8789  *  0b1..LPI2C4 enters debug halted mode when CM33 is debug halted
8790  *  0b0..LPI2C4 does not enter debug halted mode with CM33
8791  */
8792 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPI2C4_MASK)
8793 
8794 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPIT2_MASK (0x40U)
8795 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPIT2_SHIFT (6U)
8796 /*! M33_LPIT2 - LPIT2 debug halted mode with M33
8797  *  0b1..LPIT2 enters debug halted mode when CM33 is debug halted
8798  *  0b0..LPIT2 does not enter debug halted mode with CM33
8799  */
8800 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPIT2_MASK)
8801 
8802 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI3_MASK (0x80U)
8803 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI3_SHIFT (7U)
8804 /*! M33_LPSPI3 - LPSPI3 debug halted mode with M33
8805  *  0b1..LPSPI3 enters debug halted mode when CM33 is debug halted
8806  *  0b0..LPSPI3 does not enter debug halted mode with CM33
8807  */
8808 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI3_MASK)
8809 
8810 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI4_MASK (0x100U)
8811 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI4_SHIFT (8U)
8812 /*! M33_LPSPI4 - LPSPI4 debug halted mode with M33
8813  *  0b1..LPSPI4 enters debug halted mode when CM33 is debug halted
8814  *  0b0..LPSPI4 does not enter debug halted mode with CM33
8815  */
8816 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPSPI4_MASK)
8817 
8818 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPTMR2_MASK (0x200U)
8819 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPTMR2_SHIFT (9U)
8820 /*! M33_LPTMR2 - LPTMR2 debug halted mode with M33
8821  *  0b1..LPTMR2 enters debug halted mode when CM33 is debug halted
8822  *  0b0..LPTMR2 does not enter debug halted mode with CM33
8823  */
8824 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_LPTMR2_MASK)
8825 
8826 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM3_MASK (0x400U)
8827 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM3_SHIFT (10U)
8828 /*! M33_TPM3 - debug halted mode with M33
8829  *  0b1..TPM3 enters debug halted mode when CM33 is debug halted
8830  *  0b0..TPM3 does not enter debug halted mode with CM33
8831  */
8832 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM3_MASK)
8833 
8834 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM4_MASK (0x800U)
8835 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM4_SHIFT (11U)
8836 /*! M33_TPM4 - TPM3 debug halted mode with M33
8837  *  0b1..enters debug halted mode when CM33 is debug halted
8838  *  0b0..does not enter debug halted mode with CM33
8839  */
8840 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM4_MASK)
8841 
8842 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM5_MASK (0x1000U)
8843 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM5_SHIFT (12U)
8844 /*! M33_TPM5 - TPM5 debug halted mode with M33
8845  *  0b1..TPM5 enters debug halted mode when CM33 is debug halted
8846  *  0b0..TPM5 does not enter debug halted mode with CM33
8847  */
8848 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM5_MASK)
8849 
8850 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM6_MASK (0x2000U)
8851 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM6_SHIFT (13U)
8852 /*! M33_TPM6 - TPM6 debug halted mode with M33
8853  *  0b1..TPM6 enters debug halted mode when CM33 is debug halted
8854  *  0b0..TPM6 does not enter debug halted mode with CM33
8855  */
8856 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_TPM6_MASK)
8857 
8858 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG3_MASK (0x4000U)
8859 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG3_SHIFT (14U)
8860 /*! M33_WDOG3 - WDOG3 debug halted mode with M33
8861  *  0b1..WDOG3 enters debug halted mode when CM33 is debug halted
8862  *  0b0..WDOG3 does not enter debug halted mode with CM33
8863  */
8864 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG3_MASK)
8865 
8866 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG4_MASK (0x8000U)
8867 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG4_SHIFT (15U)
8868 /*! M33_WDOG4 - WDOG4 debug halted mode with M33
8869  *  0b1..WDOG4 enters debug halted mode when CM33 is debug halted
8870  *  0b0..WDOG4 does not enter debug halted mode with CM33
8871  */
8872 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M33_WDOG4_MASK)
8873 
8874 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_CAN2_MASK (0x10000U)
8875 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_CAN2_SHIFT (16U)
8876 /*! M7_CAN2 - CAN2 debug halted mode with M7
8877  *  0b1..CAN2 enters debug halted mode when CM7 is debug halted
8878  *  0b0..CAN2 does not enter debug halted mode with CM7
8879  */
8880 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_CAN2_MASK)
8881 
8882 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_EDMA4_MASK (0x20000U)
8883 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_EDMA4_SHIFT (17U)
8884 /*! M7_EDMA4 - EDMA4 debug halted mode with M7
8885  *  0b1..EDMA4 enters debug halted mode when CM7 is debug halted
8886  *  0b0..EDMA4 does not enter debug halted mode with CM7
8887  */
8888 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_EDMA4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_EDMA4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_EDMA4_MASK)
8889 
8890 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO1_MASK (0x40000U)
8891 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO1_SHIFT (18U)
8892 /*! M7_FLEXIO1 - FLEXIO1 debug halted mode with M7
8893  *  0b1..FLEXIO1 enters debug halted mode when CM7 is debug halted
8894  *  0b0..FLEXIO1 does not enter debug halted mode with CM7
8895  */
8896 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO1_MASK)
8897 
8898 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO2_MASK (0x80000U)
8899 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO2_SHIFT (19U)
8900 /*! M7_FLEXIO2 - FLEXIO2 debug halted mode with M7
8901  *  0b1..FLEXIO2 enters debug halted mode when CM7 is debug halted
8902  *  0b0..FLEXIO2 does not enter debug halted mode with CM7
8903  */
8904 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_FLEXIO2_MASK)
8905 
8906 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C3_MASK (0x100000U)
8907 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C3_SHIFT (20U)
8908 /*! M7_LPI2C3 - LPI2C3 debug halted mode with M7
8909  *  0b1..LPI2C3 enters debug halted mode when CM7 is debug halted
8910  *  0b0..LPI2C3 does not enter debug halted mode with CM7
8911  */
8912 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C3_MASK)
8913 
8914 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C4_MASK (0x200000U)
8915 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C4_SHIFT (21U)
8916 /*! M7_LPI2C4 - LPI2C4 debug halted mode with M7
8917  *  0b1..LPI2C4 enters debug halted mode when CM7 is debug halted
8918  *  0b0..LPI2C4 does not enter debug halted mode with CM7
8919  */
8920 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPI2C4_MASK)
8921 
8922 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPIT2_MASK (0x400000U)
8923 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPIT2_SHIFT (22U)
8924 /*! M7_LPIT2 - LPIT2 debug halted mode with M7
8925  *  0b1..LPIT2 enters debug halted mode when CM7 is debug halted
8926  *  0b0..LPIT2 does not enter debug halted mode with CM7
8927  */
8928 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPIT2_MASK)
8929 
8930 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI3_MASK (0x800000U)
8931 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI3_SHIFT (23U)
8932 /*! M7_LPSPI3 - WDOG3 debug halted mode with M7
8933  *  0b1..WDOG3 enters debug halted mode when CM7 is debug halted
8934  *  0b0..WDOD3 does not enter debug halted mode with CM7
8935  */
8936 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI3_MASK)
8937 
8938 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI4_MASK (0x1000000U)
8939 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI4_SHIFT (24U)
8940 /*! M7_LPSPI4 - LPSPI4 debug halted mode with M7
8941  *  0b1..LPSPI4 enters debug halted mode when CM7 is debug halted
8942  *  0b0..LPSPI4 does not enter debug halted mode with CM7
8943  */
8944 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPSPI4_MASK)
8945 
8946 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPTMR2_MASK (0x2000000U)
8947 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPTMR2_SHIFT (25U)
8948 /*! M7_LPTMR2 - LPTMR2 debug halted mode with M7
8949  *  0b1..LPTMR2 enters debug halted mode when CM7 is debug halted
8950  *  0b0..LPTMR2 does not enter debug halted mode with CM7
8951  */
8952 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_LPTMR2_MASK)
8953 
8954 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM3_MASK (0x4000000U)
8955 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM3_SHIFT (26U)
8956 /*! M7_TPM3 - TPM3 debug halted mode with M7
8957  *  0b1..TPM3 enters debug halted mode when CM7 is debug halted
8958  *  0b0..TPM3 does not enter debug halted mode with CM7
8959  */
8960 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM3_MASK)
8961 
8962 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM4_MASK (0x8000000U)
8963 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM4_SHIFT (27U)
8964 /*! M7_TPM4 - TPM4 debug halted mode with M7
8965  *  0b1..TPM4 enters debug halted mode when CM7 is debug halted
8966  *  0b0..TPM4 does not enter debug halted mode with CM7
8967  */
8968 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM4_MASK)
8969 
8970 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM5_MASK (0x10000000U)
8971 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM5_SHIFT (28U)
8972 /*! M7_TPM5 - TPM5 debug halted mode with M7
8973  *  0b1..TPM5 enters debug halted mode when CM7 is debug halted
8974  *  0b0..TPM5 does not enter debug halted mode with CM7
8975  */
8976 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM5_MASK)
8977 
8978 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM6_MASK (0x20000000U)
8979 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM6_SHIFT (29U)
8980 /*! M7_TPM6 - TPM6 debug halted mode with M7
8981  *  0b1..TPM5 enters debug halted mode when CM7 is debug halted
8982  *  0b0..TPM5 does not enter debug halted mode with CM7
8983  */
8984 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_TPM6_MASK)
8985 
8986 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG3_MASK (0x40000000U)
8987 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG3_SHIFT (30U)
8988 /*! M7_WDOG3 - WDOG3 debug halted mode with M7 */
8989 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG3_MASK)
8990 
8991 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG4_MASK (0x80000000U)
8992 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG4_SHIFT (31U)
8993 /*! M7_WDOG4 - WDOG4 debug halted mode with M7 */
8994 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG1_M7_WDOG4_MASK)
8995 /*! @} */
8996 
8997 /*! @name IPG_DEBUG2 - IPG DEBUG mask bit */
8998 /*! @{ */
8999 
9000 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_WDOG5_MASK (0x1U)
9001 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_WDOG5_SHIFT (0U)
9002 /*! M33_WDOG5 - WDOG5 debug halted mode with M7
9003  *  0b1..WDOG5 enters debug halted mode when CM33 is debug halted
9004  *  0b0..WDOG5 does not enter debug halted mode with CM33
9005  */
9006 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_WDOG5_MASK)
9007 
9008 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPTMR3_MASK (0x2U)
9009 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPTMR3_SHIFT (1U)
9010 /*! M33_LPTMR3 - LPTMR3 debug halted mode with M33
9011  *  0b1..LPTMR3 enters debug halted mode when CM33 is debug halted
9012  *  0b0..LPTMR3 does not enter debug halted mode with CM33
9013  */
9014 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPTMR3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPTMR3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPTMR3_MASK)
9015 
9016 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI5_MASK (0x4U)
9017 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI5_SHIFT (2U)
9018 /*! M33_LPSPI5 - LPSPI5 debug halted mode with M33
9019  *  0b1..LPSPI5 enters debug halted mode when CM33 is debug halted
9020  *  0b0..LPSPI5 does not enter debug halted mode with CM33
9021  */
9022 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI5_MASK)
9023 
9024 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI6_MASK (0x8U)
9025 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI6_SHIFT (3U)
9026 /*! M33_LPSPI6 - LPSPI6 debug halted mode with M33
9027  *  0b1..LPSPI6 enters debug halted mode when CM33 is debug halted
9028  *  0b0..LPSPI6 does not enter debug halted mode with CM33
9029  */
9030 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPSPI6_MASK)
9031 
9032 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPIT3_MASK (0x10U)
9033 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPIT3_SHIFT (4U)
9034 /*! M33_LPIT3 - LPIT3 debug halted mode with M33
9035  *  0b1..LPIT3 enters debug halted mode when CM33 is debug halted
9036  *  0b0..LPIT3 does not enter debug halted mode with CM33
9037  */
9038 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPIT3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPIT3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPIT3_MASK)
9039 
9040 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C5_MASK (0x20U)
9041 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C5_SHIFT (5U)
9042 /*! M33_LPI2C5 - LPI2C5 debug halted mode with M33
9043  *  0b1..LPI2C5 enters debug halted mode when CM33 is debug halted
9044  *  0b0..LPI2C5 does not enter debug halted mode with CM33
9045  */
9046 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C5_MASK)
9047 
9048 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C6_MASK (0x40U)
9049 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C6_SHIFT (6U)
9050 /*! M33_LPI2C6 - LPI2C6 debug halted mode with M33
9051  *  0b1..LPI2C6 enters debug halted mode when CM33 is debug halted
9052  *  0b0..LPI2C6 does not enter debug halted mode with CM33
9053  */
9054 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_LPI2C6_MASK)
9055 
9056 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_GPT2_MASK (0x80U)
9057 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_GPT2_SHIFT (7U)
9058 /*! M33_GPT2 - GPT2 debug halted mode with M33
9059  *  0b1..GPT2 enters debug halted mode when CM33 is debug halted
9060  *  0b0..GPT2 does not enter debug halted mode with CM33
9061  */
9062 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_GPT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_GPT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_GPT2_MASK)
9063 
9064 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM1_MASK (0x100U)
9065 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM1_SHIFT (8U)
9066 /*! M33_FLEXPWM1 - FLEXPWM1 debug halted mode with M33
9067  *  0b1..FLEXPWM1 enters debug halted mode when CM33 is debug halted
9068  *  0b0..FLEXPWM1 does not enter debug halted mode with CM33
9069  */
9070 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM1_MASK)
9071 
9072 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM2_MASK (0x200U)
9073 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM2_SHIFT (9U)
9074 /*! M33_FLEXPWM2 - FLEXPWM2 debug halted mode with M33
9075  *  0b1..FLEXPWM2 enters debug halted mode when CM33 is debug halted
9076  *  0b0..FLEXPWM2 does not enter debug halted mode with CM33
9077  */
9078 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM2_MASK)
9079 
9080 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM3_MASK (0x400U)
9081 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM3_SHIFT (10U)
9082 /*! M33_FLEXPWM3 - FLEXPWM3 debug halted mode with M33
9083  *  0b1..FLEXPWM3 enters debug halted mode when CM33 is debug halted
9084  *  0b0..FLEXPWM3 does not enter debug halted mode with CM33
9085  */
9086 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM3_MASK)
9087 
9088 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM4_MASK (0x800U)
9089 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM4_SHIFT (11U)
9090 /*! M33_FLEXPWM4 - FLEXPWM4 debug halted mode with M33
9091  *  0b1..FLEXPWM4 enters debug halted mode when CM33 is debug halted
9092  *  0b0..FLEXPWM4 does not enter debug halted mode with CM33
9093  */
9094 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_FLEXPWM4_MASK)
9095 
9096 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_MIC_MASK (0x1000U)
9097 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_MIC_SHIFT (12U)
9098 /*! M33_MIC - MIC debug halted mode with M33
9099  *  0b1..MIC enters debug halted mode when CM33 is debug halted
9100  *  0b0..MIC does not enter debug halted mode with CM33
9101  */
9102 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_MIC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_MIC_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_MIC_MASK)
9103 
9104 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI2_MASK (0x2000U)
9105 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI2_SHIFT (13U)
9106 /*! M33_SAI2 - SAI2 debug halted mode with M33
9107  *  0b1..SAI2 enters debug halted mode when CM33 is debug halted
9108  *  0b0..SAI2 does not enter debug halted mode with CM33
9109  */
9110 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI2_MASK)
9111 
9112 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI3_MASK (0x4000U)
9113 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI3_SHIFT (14U)
9114 /*! M33_SAI3 - SAI3 debug halted mode with M33
9115  *  0b1..SAI3 enters debug halted mode when CM33 is debug halted
9116  *  0b0..SAI3 does not enter debug halted mode with CM33
9117  */
9118 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI3_MASK)
9119 
9120 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI4_MASK (0x8000U)
9121 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI4_SHIFT (15U)
9122 /*! M33_SAI4 - SAI4 debug halted mode with M33
9123  *  0b1..SAI4 enters debug halted mode when CM33 is debug halted
9124  *  0b0..SAI4 does not enter debug halted mode with CM33
9125  */
9126 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M33_SAI4_MASK)
9127 
9128 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_WDOG5_MASK (0x10000U)
9129 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_WDOG5_SHIFT (16U)
9130 /*! M7_WDOG5 - WDOG5 debug halted mode with M7
9131  *  0b1..WDOG5 enters debug halted mode when CM7 is debug halted
9132  *  0b0..WDOG5 does not enter debug halted mode with CM7
9133  */
9134 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_WDOG5_MASK)
9135 
9136 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPTMR3_MASK (0x20000U)
9137 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPTMR3_SHIFT (17U)
9138 /*! M7_LPTMR3 - LPTMR3 debug halted mode with M7
9139  *  0b1..LPTMR3 enters debug halted mode when CM7 is debug halted
9140  *  0b0..LPTMR3 does not enter debug halted mode with CM7
9141  */
9142 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPTMR3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPTMR3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPTMR3_MASK)
9143 
9144 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI5_MASK (0x40000U)
9145 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI5_SHIFT (18U)
9146 /*! M7_LPSPI5 - LPTMR3 debug halted mode with M7
9147  *  0b1..enters debug halted mode when CM7 is debug halted
9148  *  0b0..LPTMR3 does not enter debug halted mode with CM7
9149  */
9150 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI5_MASK)
9151 
9152 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI6_MASK (0x80000U)
9153 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI6_SHIFT (19U)
9154 /*! M7_LPSPI6 - LPSPI6 debug halted mode with M7
9155  *  0b1..LPSPI6 enters debug halted mode when CM7 is debug halted
9156  *  0b0..LPSPI6 does not enter debug halted mode with CM7
9157  */
9158 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPSPI6_MASK)
9159 
9160 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPIT3_MASK (0x100000U)
9161 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPIT3_SHIFT (20U)
9162 /*! M7_LPIT3 - LPIT3 debug halted mode with M7
9163  *  0b1..LPIT3 enters debug halted mode when CM7 is debug halted
9164  *  0b0..LPIT3 does not enter debug halted mode with CM7
9165  */
9166 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPIT3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPIT3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPIT3_MASK)
9167 
9168 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C5_MASK (0x200000U)
9169 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C5_SHIFT (21U)
9170 /*! M7_LPI2C5 - LPI2C5 debug halted mode with M7
9171  *  0b1..LPI2C5 enters debug halted mode when CM7 is debug halted
9172  *  0b0..LPI2C5 does not enter debug halted mode with CM7
9173  */
9174 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C5_MASK)
9175 
9176 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C6_MASK (0x400000U)
9177 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C6_SHIFT (22U)
9178 /*! M7_LPI2C6 - LPI2C6" debug halted mode with M7
9179  *  0b1..LPI2C6" enters debug halted mode when CM7 is debug halted
9180  *  0b0..LPI2C6" does not enter debug halted mode with CM7
9181  */
9182 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_LPI2C6_MASK)
9183 
9184 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_GPT2_MASK (0x800000U)
9185 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_GPT2_SHIFT (23U)
9186 /*! M7_GPT2 - GPT2 debug halted mode with M7
9187  *  0b1..GPT2 enters debug halted mode when CM7 is debug halted
9188  *  0b0..GPT2 does not enter debug halted mode with CM7
9189  */
9190 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_GPT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_GPT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_GPT2_MASK)
9191 
9192 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM1_MASK (0x1000000U)
9193 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM1_SHIFT (24U)
9194 /*! M7_FLEXPWM1 - FLEXPWM1 debug halted mode with M7
9195  *  0b1..FLEXPWM1 enters debug halted mode when CM7 is debug halted
9196  *  0b0..FLEXPWM1 does not enter debug halted mode with CM7
9197  */
9198 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM1_MASK)
9199 
9200 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM2_MASK (0x2000000U)
9201 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM2_SHIFT (25U)
9202 /*! M7_FLEXPWM2 - FLEXPWM2 debug halted mode with M7
9203  *  0b1..FLEXPWM2 enters debug halted mode when CM7 is debug halted
9204  *  0b0..FLEXPWM2 does not enter debug halted mode with CM7
9205  */
9206 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM2_MASK)
9207 
9208 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM3_MASK (0x4000000U)
9209 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM3_SHIFT (26U)
9210 /*! M7_FLEXPWM3 - FLEXPWM3 debug halted mode with M7
9211  *  0b1..FLEXPWM3 enters debug halted mode when CM7 is debug halted
9212  *  0b0..FLEXPWM3 does not enter debug halted mode with CM7
9213  */
9214 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM3_MASK)
9215 
9216 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM4_MASK (0x8000000U)
9217 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM4_SHIFT (27U)
9218 /*! M7_FLEXPWM4 - FLEXPWM4 debug halted mode with M7
9219  *  0b1..FLEXPWM4 enters debug halted mode when CM7 is debug halted
9220  *  0b0..FLEXPWM4 does not enter debug halted mode with CM7
9221  */
9222 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_FLEXPWM4_MASK)
9223 
9224 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_MIC_MASK (0x10000000U)
9225 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_MIC_SHIFT (28U)
9226 /*! M7_MIC - MIC debug halted mode with M7
9227  *  0b1..MIC enters debug halted mode when CM7 is debug halted
9228  *  0b0..MIC does not enter debug halted mode with CM7
9229  */
9230 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_MIC(x)  (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_MIC_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_MIC_MASK)
9231 
9232 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI2_MASK (0x20000000U)
9233 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI2_SHIFT (29U)
9234 /*! M7_SAI2 - SAI2 debug halted mode with M7
9235  *  0b1..SAI2 enters debug halted mode when CM7 is debug halted
9236  *  0b0..SAI2 does not enter debug halted mode with CM7
9237  */
9238 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI2_MASK)
9239 
9240 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI3_MASK (0x40000000U)
9241 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI3_SHIFT (30U)
9242 /*! M7_SAI3 - SAI3 debug halted mode with M7
9243  *  0b1..SAI3 enters debug halted mode when CM7 is debug halted
9244  *  0b0..SAI3 does not enter debug halted mode with CM7
9245  */
9246 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI3_MASK)
9247 
9248 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI4_MASK (0x80000000U)
9249 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI4_SHIFT (31U)
9250 /*! M7_SAI4 - SAI4 debug halted mode with M7
9251  *  0b1..SAI4 enters debug halted mode when CM7 is debug halted
9252  *  0b0..SAI4 does not enter debug halted mode with CM7
9253  */
9254 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG2_M7_SAI4_MASK)
9255 /*! @} */
9256 
9257 /*! @name IPG_DEBUG3 - IPG DEBUG mask bit */
9258 /*! @{ */
9259 
9260 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC1_MASK (0x1U)
9261 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC1_SHIFT (0U)
9262 /*! M33_SINC1 - I3C2 debug halted mode with M33
9263  *  0b1..I3C2 enters debug halted mode when CM33 is debug halted
9264  *  0b0..I3C2 does not enter debug halted mode with CM33
9265  */
9266 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC1_MASK)
9267 
9268 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC2_MASK (0x2U)
9269 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC2_SHIFT (1U)
9270 /*! M33_SINC2 - SINC2 debug halted mode with M33
9271  *  0b1..SINC2 enters debug halted mode when CM33 is debug halted
9272  *  0b0..SINC2 does not enter debug halted mode with CM33
9273  */
9274 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC2_MASK)
9275 
9276 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC3_MASK (0x4U)
9277 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC3_SHIFT (2U)
9278 /*! M33_SINC3 - SINC3 debug halted mode with M33
9279  *  0b1..SINC3 enters debug halted mode when CM33 is debug halted
9280  *  0b0..SINC3 does not enter debug halted mode with CM33
9281  */
9282 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_SINC3_MASK)
9283 
9284 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER1_MASK (0x8U)
9285 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER1_SHIFT (3U)
9286 /*! M33_QTIMER1 - QTIMER1 debug halted mode with M33
9287  *  0b1..QTIMER1 enters debug halted mode when CM33 is debug halted
9288  *  0b0..QTIMER1 does not enter debug halted mode with CM33
9289  */
9290 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER1_MASK)
9291 
9292 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER2_MASK (0x10U)
9293 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER2_SHIFT (4U)
9294 /*! M33_QTIMER2 - QTIMER2 debug halted mode with M33
9295  *  0b1..QTIMER2 enters debug halted mode when CM33 is debug halted
9296  *  0b0..QTIMER2 does not enter debug halted mode with CM33
9297  */
9298 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER2_MASK)
9299 
9300 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER3_MASK (0x20U)
9301 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER3_SHIFT (5U)
9302 /*! M33_QTIMER3 - QTIMER3 debug halted mode with M33
9303  *  0b1..QTIMER3 enters debug halted mode when CM33 is debug halted
9304  *  0b0..QTIMER3 does not enter debug halted mode with CM33
9305  */
9306 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER3_MASK)
9307 
9308 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER4_MASK (0x40U)
9309 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER4_SHIFT (6U)
9310 /*! M33_QTIMER4 - QTIMER4 debug halted mode with M33
9311  *  0b1..QTIMER4 enters debug halted mode when CM33 is debug halted
9312  *  0b0..QTIMER4 does not enter debug halted mode with CM33
9313  */
9314 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER4_MASK)
9315 
9316 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER5_MASK (0x80U)
9317 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER5_SHIFT (7U)
9318 /*! M33_QTIMER5 - QTIMER5 debug halted mode with M33
9319  *  0b1..QTIMER5 enters debug halted mode when CM33 is debug halted
9320  *  0b0..QTIMER5 does not enter debug halted mode with CM33
9321  */
9322 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER5_MASK)
9323 
9324 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER6_MASK (0x100U)
9325 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER6_SHIFT (8U)
9326 /*! M33_QTIMER6 - QTIMER6 debug halted mode with M33
9327  *  0b1..QTIMER6 enters debug halted mode when CM33 is debug halted
9328  *  0b0..QTIMER6 does not enter debug halted mode with CM33
9329  */
9330 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER6_MASK)
9331 
9332 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER7_MASK (0x200U)
9333 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER7_SHIFT (9U)
9334 /*! M33_QTIMER7 - QTIMER7 debug halted mode with M33
9335  *  0b1..QTIMER7 enters debug halted mode when CM33 is debug halted
9336  *  0b0..QTIMER7 does not enter debug halted mode with CM33
9337  */
9338 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER7_MASK)
9339 
9340 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER8_MASK (0x400U)
9341 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER8_SHIFT (10U)
9342 /*! M33_QTIMER8 - QTIMER8 debug halted mode with M33
9343  *  0b1..QTIMER8 enters debug halted mode when CM33 is debug halted
9344  *  0b0..QTIMER8 does not enter debug halted mode with CM33
9345  */
9346 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_QTIMER8_MASK)
9347 
9348 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_I3C2_MASK (0x800U)
9349 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_I3C2_SHIFT (11U)
9350 /*! M33_I3C2 - I3C2 debug halted mode with M33
9351  *  0b1..I3C2 enters debug halted mode when CM33 is debug halted
9352  *  0b0..I3C2 does not enter debug halted mode with CM33
9353  */
9354 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M33_I3C2_MASK)
9355 
9356 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC1_MASK (0x10000U)
9357 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC1_SHIFT (16U)
9358 /*! M7_SINC1 - SINC1 debug halted mode with M7
9359  *  0b1..SINC1 enters debug halted mode when CM7 is debug halted
9360  *  0b0..SINC1 does not enter debug halted mode with CM7
9361  */
9362 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC1_MASK)
9363 
9364 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC2_MASK (0x20000U)
9365 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC2_SHIFT (17U)
9366 /*! M7_SINC2 - SINC2 debug halted mode with M7
9367  *  0b1..SINC2 enters debug halted mode when CM7 is debug halted
9368  *  0b0..SINC2 does not enter debug halted mode with CM7
9369  */
9370 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC2_MASK)
9371 
9372 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC3_MASK (0x40000U)
9373 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC3_SHIFT (18U)
9374 /*! M7_SINC3 - SINC3 debug halted mode with M7
9375  *  0b1..SINC3 enters debug halted mode when CM7 is debug halted
9376  *  0b0..SINC3 does not enter debug halted mode with CM7
9377  */
9378 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_SINC3_MASK)
9379 
9380 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER1_MASK (0x80000U)
9381 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER1_SHIFT (19U)
9382 /*! M7_QTIMER1 - QTIMER1 debug halted mode with M7
9383  *  0b1..QTIMER1 enters debug halted mode when CM7 is debug halted
9384  *  0b0..QTIMER1 does not enter debug halted mode with CM7
9385  */
9386 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER1_MASK)
9387 
9388 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER2_MASK (0x100000U)
9389 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER2_SHIFT (20U)
9390 /*! M7_QTIMER2 - QTIMER2 debug halted mode with M7
9391  *  0b1..QTIMER2 enters debug halted mode when CM7 is debug halted
9392  *  0b0..QTIMER2 does not enter debug halted mode with CM7
9393  */
9394 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER2_MASK)
9395 
9396 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER3_MASK (0x200000U)
9397 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER3_SHIFT (21U)
9398 /*! M7_QTIMER3 - QTIMER3 debug halted mode with M7
9399  *  0b1..QTIMER3 enters debug halted mode when CM7 is debug halted
9400  *  0b0..QTIMER3 does not enter debug halted mode with CM7
9401  */
9402 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER3_MASK)
9403 
9404 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER4_MASK (0x400000U)
9405 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER4_SHIFT (22U)
9406 /*! M7_QTIMER4 - QTIMER4 debug halted mode with M7
9407  *  0b1..QTIMER4 enters debug halted mode when CM7 is debug halted
9408  *  0b0..QTIMER4 does not enter debug halted mode with CM7
9409  */
9410 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER4_MASK)
9411 
9412 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER5_MASK (0x800000U)
9413 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER5_SHIFT (23U)
9414 /*! M7_QTIMER5 - QTIMER5 debug halted mode with M7
9415  *  0b1..QTIMER5 enters debug halted mode when CM7 is debug halted
9416  *  0b0..QTIMER5 does not enter debug halted mode with CM7
9417  */
9418 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER5_MASK)
9419 
9420 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER6_MASK (0x1000000U)
9421 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER6_SHIFT (24U)
9422 /*! M7_QTIMER6 - debug halted mode with M7
9423  *  0b1..enters debug halted mode when CM7 is debug halted
9424  *  0b0..does not enter debug halted mode with CM7
9425  */
9426 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER6_MASK)
9427 
9428 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER7_MASK (0x2000000U)
9429 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER7_SHIFT (25U)
9430 /*! M7_QTIMER7 - QTIMER7 debug halted mode with M7
9431  *  0b1..QTIMER7 enters debug halted mode when CM7 is debug halted
9432  *  0b0..QTIMER7 does not enter debug halted mode with CM7
9433  */
9434 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER7_MASK)
9435 
9436 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER8_MASK (0x4000000U)
9437 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER8_SHIFT (26U)
9438 /*! M7_QTIMER8 - QTIMER8 debug halted mode with M7
9439  *  0b1..QTIMER8 enters debug halted mode when CM7 is debug halted
9440  *  0b0..QTIMER8 does not enter debug halted mode with CM7
9441  */
9442 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_QTIMER8_MASK)
9443 
9444 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_I3C2_MASK (0x8000000U)
9445 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_I3C2_SHIFT (27U)
9446 /*! M7_I3C2 - debug halted mode with M7
9447  *  0b1..I3C2 enters debug halted mode when CM7 is debug halted
9448  *  0b0..I3C2 does not enter debug halted mode with CM7
9449  */
9450 #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG3_M7_I3C2_MASK)
9451 /*! @} */
9452 
9453 /*! @name SSI - SSI master low power mode control */
9454 /*! @{ */
9455 
9456 #define BLK_CTRL_WAKEUPMIX_SSI_SSI_IDLE_MASK     (0x1U)
9457 #define BLK_CTRL_WAKEUPMIX_SSI_SSI_IDLE_SHIFT    (0U)
9458 /*! SSI_IDLE - WAKEUP Domain to M7 SSI master idle
9459  *  0b1..WAKEUP Domain to M7 SSI master is idle
9460  *  0b0..WAKEUP Domain to M7 SSI master is not idle
9461  */
9462 #define BLK_CTRL_WAKEUPMIX_SSI_SSI_IDLE(x)       (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SSI_IDLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SSI_IDLE_MASK)
9463 
9464 #define BLK_CTRL_WAKEUPMIX_SSI_BLKHOLE_MODE_B_MASK (0x2U)
9465 #define BLK_CTRL_WAKEUPMIX_SSI_BLKHOLE_MODE_B_SHIFT (1U)
9466 /*! BLKHOLE_MODE_B - WAKEUP Domain to M7 SSI master blackhole mode
9467  *  0b1..WAKEUP Domain to M7 SSI master will enter blackhole mode
9468  *  0b0..WAKEUP Domain to M7 SSI master will exit blackhole mode
9469  */
9470 #define BLK_CTRL_WAKEUPMIX_SSI_BLKHOLE_MODE_B(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_BLKHOLE_MODE_B_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_BLKHOLE_MODE_B_MASK)
9471 
9472 #define BLK_CTRL_WAKEUPMIX_SSI_PAUSE_MODE_MASK   (0x4U)
9473 #define BLK_CTRL_WAKEUPMIX_SSI_PAUSE_MODE_SHIFT  (2U)
9474 /*! PAUSE_MODE - WAKEUP Domain to M7 SSI master pause mode
9475  *  0b1..WAKEUP Domain to M7 SSI master will exit pause mode
9476  *  0b0..WAKEUP Domain to M7 SSI master will enter pause mode
9477  */
9478 #define BLK_CTRL_WAKEUPMIX_SSI_PAUSE_MODE(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_PAUSE_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_PAUSE_MODE_MASK)
9479 /*! @} */
9480 
9481 /*! @name ECAT_MISC_CFG - EtherCAT miscellaneous configuration */
9482 /*! @{ */
9483 
9484 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_MASK (0x1U)
9485 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_SHIFT (0U)
9486 /*! RMII_SEL0 - RMII mode selection for EtherCAT port 0
9487  *  0b0..EtherCAT port0 is in MII mode
9488  *  0b1..EtherCAT port0 is in RMII mode
9489  */
9490 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL0_MASK)
9491 
9492 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_MASK (0x2U)
9493 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_SHIFT (1U)
9494 /*! RMII_SEL1 - RMII mode selection for EtherCAT port 1
9495  *  0b0..EtherCAT port1 is in MII mode
9496  *  0b1..EtherCAT port1 is in RMII mode
9497  */
9498 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_SEL1_MASK)
9499 
9500 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_MASK (0x4U)
9501 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_SHIFT (2U)
9502 /*! GLB_EN - Global enable of EtherCAT
9503  *  0b1..EtherCAT is on
9504  *  0b0..EtherCAT is off
9505  */
9506 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_EN_MASK)
9507 
9508 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_MASK (0x8U)
9509 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_SHIFT (3U)
9510 /*! GLB_RST - Global reset of EtherCAT
9511  *  0b0..EtherCAT is out of reset
9512  *  0b1..EtherCAT is held in reset
9513  */
9514 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_GLB_RST_MASK)
9515 
9516 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK (0x100U)
9517 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_SHIFT (8U)
9518 /*! RMII_REF_CLK_DIR0 - RMII Port0 REF_CLK direction control
9519  *  0b0..RMII REF_CLK is input
9520  *  0b1..RMII REF_CLK is output driven by ECAT_CLK_ROOT/2
9521  */
9522 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK)
9523 
9524 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK (0x200U)
9525 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_SHIFT (9U)
9526 /*! RMII_REF_CLK_DIR1 - RMII Port1 REF_CLK direction control
9527  *  0b0..RMII REF_CLK is input
9528  *  0b1..RMII REF_CLK is output driven by ECAT_CLK_ROOT/2
9529  */
9530 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK)
9531 
9532 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_MASK (0x10000U)
9533 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_SHIFT (16U)
9534 /*! PHY_OFFSET - EtherCAT PHY_OFFSET */
9535 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_MASK)
9536 
9537 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC_MASK (0x3E0000U)
9538 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC_SHIFT (17U)
9539 /*! PHY_OFFSET_VEC - EtherCAT PHY_OFFSET_VEC */
9540 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_PHY_OFFSET_VEC_MASK)
9541 
9542 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_MASK (0x400000U)
9543 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_SHIFT (22U)
9544 /*! EEPROM_SIZE_OPTION - EtherCAT EEPROM SIZE OPTION */
9545 #define BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_SHIFT)) & BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_EEPROM_SIZE_OPTION_MASK)
9546 /*! @} */
9547 
9548 /*! @name DEXSC_ERR - DEXSC error response configuration */
9549 /*! @{ */
9550 
9551 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_EXC_ERR_RESP_EN_MASK (0x1U)
9552 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_EXC_ERR_RESP_EN_SHIFT (0U)
9553 /*! EXC_ERR_RESP_EN - Exclusive error response enable
9554  *  0b0..OKAY response
9555  *  0b1..SLVError response
9556  */
9557 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_DEXSC_ERR_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_DEXSC_ERR_EXC_ERR_RESP_EN_MASK)
9558 
9559 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_LOCK_EXC_ERR_RESP_EN_MASK (0x2U)
9560 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_LOCK_EXC_ERR_RESP_EN_SHIFT (1U)
9561 /*! LOCK_EXC_ERR_RESP_EN - Lock bit of EXC_ERR_RESP_EN */
9562 #define BLK_CTRL_WAKEUPMIX_DEXSC_ERR_LOCK_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_DEXSC_ERR_LOCK_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_DEXSC_ERR_LOCK_EXC_ERR_RESP_EN_MASK)
9563 /*! @} */
9564 
9565 /*! @name USBPHY_MISC_CTRL - USBPHY miscellaneous control */
9566 /*! @{ */
9567 
9568 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
9569 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
9570 /*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable */
9571 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_IPG_CLK_ACTIVE_MASK)
9572 
9573 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_IPG_CLK_ACTIVE_MASK (0x100U)
9574 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_IPG_CLK_ACTIVE_SHIFT (8U)
9575 /*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable */
9576 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_IPG_CLK_ACTIVE_MASK)
9577 
9578 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x10000U)
9579 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (16U)
9580 /*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register */
9581 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
9582 
9583 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x1000000U)
9584 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (24U)
9585 /*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY2 wakeup interrupt holding register */
9586 #define BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_USBPHY_MISC_CTRL_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
9587 /*! @} */
9588 
9589 /*! @name NETC_PORT_MISC_CFG - NETC Port miscellaneous configuration */
9590 /*! @{ */
9591 
9592 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK (0x1U)
9593 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_SHIFT (0U)
9594 /*! PORT0_RMII_REF_CLK_DIR - Port0 RMII Reference clock direction control */
9595 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK)
9596 
9597 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK (0x2U)
9598 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_SHIFT (1U)
9599 /*! PORT1_RMII_REF_CLK_DIR - Port1 RMII Reference clock direction control
9600  *  0b0..Port1 RMII Reference clock is input
9601  *  0b1..Port1 RMII Reference clock is output
9602  */
9603 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK)
9604 
9605 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK (0x4U)
9606 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_SHIFT (2U)
9607 /*! PORT2_RMII_REF_CLK_DIR - Port2 RMII Reference clock direction control
9608  *  0b0..Port2 RMII Reference clock is input
9609  *  0b1..Port2 RMII Reference clock is output
9610  */
9611 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK)
9612 
9613 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK (0x8U)
9614 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_SHIFT (3U)
9615 /*! PORT3_RMII_REF_CLK_DIR - Port3 RMII Reference clock direction control
9616  *  0b0..Port3 RMII Reference clock is input
9617  *  0b1..Port3 RMII Reference clock is output
9618  */
9619 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK)
9620 
9621 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK (0x10U)
9622 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_SHIFT (4U)
9623 /*! PORT4_RMII_REF_CLK_DIR - Port4 RMII Reference clock direction control
9624  *  0b0..Port4 RMII Reference clock is input
9625  *  0b1..Port4 RMII Reference clock is output
9626  */
9627 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK)
9628 
9629 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_CFG_IERB_LOCK_MASK (0x100U)
9630 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_CFG_IERB_LOCK_SHIFT (8U)
9631 /*! CFG_IERB_LOCK - Default value for IERB NETCRR[LOCK] bit. Determines write accessibility of IERB registers after power-on-reset
9632  *  0b0..Unlocked after power-on-reset. Normal read/write access to all IERB registers
9633  *  0b1..Locked after power-on-reset. Write access inhibited to all IERB registers, except NETCRR
9634  */
9635 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_CFG_IERB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_CFG_IERB_LOCK_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_CFG_IERB_LOCK_MASK)
9636 
9637 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK (0x1000000U)
9638 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_SHIFT (24U)
9639 /*! TMR_EXT_CLK_SEL - 1588 timer external clock selection
9640  *  0b0..CCM tmr_1588_clk_root is selected
9641  *  0b1..External pin is selected
9642  */
9643 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK)
9644 
9645 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL_MASK (0x2000000U)
9646 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL_SHIFT (25U)
9647 /*! TMR_TRIG1_SEL - 1588 timer trigger1 input selection
9648  *  0b0..Input from IOMUX
9649  *  0b1..Input from XBAR
9650  */
9651 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL_MASK)
9652 
9653 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG2_SEL_MASK (0x4000000U)
9654 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG2_SEL_SHIFT (26U)
9655 /*! TMR_TRIG2_SEL - 1588 timer trigger2 input selection
9656  *  0b0..Input from IOMUX
9657  *  0b1..Input from XBAR
9658  */
9659 #define BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG2_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG2_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG2_SEL_MASK)
9660 /*! @} */
9661 
9662 /*! @name M7_NMI_CLR - M7 NMI interrupt clear register */
9663 /*! @{ */
9664 
9665 #define BLK_CTRL_WAKEUPMIX_M7_NMI_CLR_M7_NMI_CLEAR_MASK (0x1U)
9666 #define BLK_CTRL_WAKEUPMIX_M7_NMI_CLR_M7_NMI_CLEAR_SHIFT (0U)
9667 /*! M7_NMI_CLEAR - Clear CM7 NMI holding register */
9668 #define BLK_CTRL_WAKEUPMIX_M7_NMI_CLR_M7_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_M7_NMI_CLR_M7_NMI_CLEAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_M7_NMI_CLR_M7_NMI_CLEAR_MASK)
9669 /*! @} */
9670 
9671 /*! @name QTIMER_CTRL1 - Qtimer miscellaneous control register 1 */
9672 /*! @{ */
9673 
9674 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
9675 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
9676 /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze
9677  *  0b0..Timer counter works normally
9678  *  0b1..Reset counter and output flags
9679  */
9680 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR_CNTS_FREEZE_MASK)
9681 
9682 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR0_INPUT_SEL_MASK (0x2U)
9683 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR0_INPUT_SEL_SHIFT (1U)
9684 /*! QTIMER1_TMR0_INPUT_SEL - QTIMER1 TMR0 input select
9685  *  0b0..Input from IOMUX
9686  *  0b1..Input from XBAR
9687  */
9688 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR0_INPUT_SEL_MASK)
9689 
9690 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR1_INPUT_SEL_MASK (0x4U)
9691 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR1_INPUT_SEL_SHIFT (2U)
9692 /*! QTIMER1_TMR1_INPUT_SEL - QTIMER1 TMR1 input select
9693  *  0b0..Input from IOMUX
9694  *  0b1..Input from XBAR
9695  */
9696 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR1_INPUT_SEL_MASK)
9697 
9698 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR2_INPUT_SEL_MASK (0x8U)
9699 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR2_INPUT_SEL_SHIFT (3U)
9700 /*! QTIMER1_TMR2_INPUT_SEL - QTIMER1 TMR2 input select
9701  *  0b0..Input from IOMUX
9702  *  0b1..Input from XBAR
9703  */
9704 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR2_INPUT_SEL_MASK)
9705 
9706 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR3_INPUT_SEL_MASK (0x10U)
9707 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR3_INPUT_SEL_SHIFT (4U)
9708 /*! QTIMER1_TMR3_INPUT_SEL - QTIMER1 TMR3 input select
9709  *  0b0..Input from IOMUX
9710  *  0b1..Input from XBAR
9711  */
9712 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER1_TMR3_INPUT_SEL_MASK)
9713 
9714 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR_CNTS_FREEZE_MASK (0x100U)
9715 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR_CNTS_FREEZE_SHIFT (8U)
9716 /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze
9717  *  0b0..Timer counter works normally
9718  *  0b1..Reset counter and output flags
9719  */
9720 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR_CNTS_FREEZE_MASK)
9721 
9722 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR0_INPUT_SEL_MASK (0x200U)
9723 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR0_INPUT_SEL_SHIFT (9U)
9724 /*! QTIMER2_TMR0_INPUT_SEL - QTIMER2 TMR0 input select
9725  *  0b0..Input from IOMUX
9726  *  0b1..Input from XBAR
9727  */
9728 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR0_INPUT_SEL_MASK)
9729 
9730 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR1_INPUT_SEL_MASK (0x400U)
9731 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR1_INPUT_SEL_SHIFT (10U)
9732 /*! QTIMER2_TMR1_INPUT_SEL - QTIMER2 TMR1 input select
9733  *  0b0..Input from IOMUX
9734  *  0b1..Input from XBAR
9735  */
9736 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR1_INPUT_SEL_MASK)
9737 
9738 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR2_INPUT_SEL_MASK (0x800U)
9739 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR2_INPUT_SEL_SHIFT (11U)
9740 /*! QTIMER2_TMR2_INPUT_SEL - QTIMER2 TMR2 input select
9741  *  0b0..Input from IOMUX
9742  *  0b1..Input from XBAR
9743  */
9744 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR2_INPUT_SEL_MASK)
9745 
9746 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR3_INPUT_SEL_MASK (0x1000U)
9747 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR3_INPUT_SEL_SHIFT (12U)
9748 /*! QTIMER2_TMR3_INPUT_SEL - QTIMER2 TMR3 input select
9749  *  0b0..Input from IOMUX
9750  *  0b1..Input from XBAR
9751  */
9752 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER2_TMR3_INPUT_SEL_MASK)
9753 
9754 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR_CNTS_FREEZE_MASK (0x10000U)
9755 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR_CNTS_FREEZE_SHIFT (16U)
9756 /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze
9757  *  0b0..Timer counter works normally
9758  *  0b1..Reset counter and ouput flags
9759  */
9760 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR_CNTS_FREEZE_MASK)
9761 
9762 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR0_INPUT_SEL_MASK (0x20000U)
9763 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR0_INPUT_SEL_SHIFT (17U)
9764 /*! QTIMER3_TMR0_INPUT_SEL - QTIMER3 TMR0 input select
9765  *  0b0..Input from IOMUX
9766  *  0b1..Input from XBAR
9767  */
9768 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR0_INPUT_SEL_MASK)
9769 
9770 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR1_INPUT_SEL_MASK (0x40000U)
9771 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR1_INPUT_SEL_SHIFT (18U)
9772 /*! QTIMER3_TMR1_INPUT_SEL - QTIMER3 TMR1 input select
9773  *  0b0..Input from IOMUX
9774  *  0b1..Input from XBAR
9775  */
9776 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR1_INPUT_SEL_MASK)
9777 
9778 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR2_INPUT_SEL_MASK (0x80000U)
9779 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR2_INPUT_SEL_SHIFT (19U)
9780 /*! QTIMER3_TMR2_INPUT_SEL - QTIMER3 TMR2 input select
9781  *  0b0..Input from IOMUX
9782  *  0b1..Input from XBAR
9783  */
9784 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR2_INPUT_SEL_MASK)
9785 
9786 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR3_INPUT_SEL_MASK (0x100000U)
9787 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR3_INPUT_SEL_SHIFT (20U)
9788 /*! QTIMER3_TMR3_INPUT_SEL - QTIMER3 TMR3 input select
9789  *  0b0..Input from IOMUX
9790  *  0b1..Input from XBAR
9791  */
9792 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER3_TMR3_INPUT_SEL_MASK)
9793 
9794 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1000000U)
9795 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR_CNTS_FREEZE_SHIFT (24U)
9796 /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze
9797  *  0b0..Timer counter works normally
9798  *  0b1..Reset counter and output flags
9799  */
9800 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR_CNTS_FREEZE_MASK)
9801 
9802 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR0_INPUT_SEL_MASK (0x2000000U)
9803 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR0_INPUT_SEL_SHIFT (25U)
9804 /*! QTIMER4_TMR0_INPUT_SEL - QTIMER4 TMR0 input select
9805  *  0b0..Input from IOMUX
9806  *  0b1..Input from XBAR
9807  */
9808 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR0_INPUT_SEL_MASK)
9809 
9810 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR1_INPUT_SEL_MASK (0x4000000U)
9811 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR1_INPUT_SEL_SHIFT (26U)
9812 /*! QTIMER4_TMR1_INPUT_SEL - QTIMER4 TMR1 input select
9813  *  0b0..Input from IOMUX
9814  *  0b1..Input from XBAR
9815  */
9816 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR1_INPUT_SEL_MASK)
9817 
9818 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR2_INPUT_SEL_MASK (0x8000000U)
9819 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR2_INPUT_SEL_SHIFT (27U)
9820 /*! QTIMER4_TMR2_INPUT_SEL - QTIMER4 TMR2 input select
9821  *  0b0..Input from IOMUX
9822  *  0b1..Input from XBAR
9823  */
9824 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR2_INPUT_SEL_MASK)
9825 
9826 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR3_INPUT_SEL_MASK (0x10000000U)
9827 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR3_INPUT_SEL_SHIFT (28U)
9828 /*! QTIMER4_TMR3_INPUT_SEL - QTIMER4 TMR3 input select
9829  *  0b0..Input from IOMUX
9830  *  0b1..Input from XBAR
9831  */
9832 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL1_QTIMER4_TMR3_INPUT_SEL_MASK)
9833 /*! @} */
9834 
9835 /*! @name QTIMER_CTRL2 - Qtimer miscellaneous control register 2 */
9836 /*! @{ */
9837 
9838 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR_CNTS_FREEZE_MASK (0x1U)
9839 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR_CNTS_FREEZE_SHIFT (0U)
9840 /*! QTIMER5_TMR_CNTS_FREEZE - QTIMER5 timer counter freeze
9841  *  0b0..Timer counter works normally
9842  *  0b1..Reset counter and output flags
9843  */
9844 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR_CNTS_FREEZE_MASK)
9845 
9846 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR0_INPUT_SEL_MASK (0x2U)
9847 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR0_INPUT_SEL_SHIFT (1U)
9848 /*! QTIMER5_TMR0_INPUT_SEL - QTIMER5 TMR0 input select
9849  *  0b0..Input from IOMUX
9850  *  0b1..Input from XBAR
9851  */
9852 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR0_INPUT_SEL_MASK)
9853 
9854 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR1_INPUT_SEL_MASK (0x4U)
9855 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR1_INPUT_SEL_SHIFT (2U)
9856 /*! QTIMER5_TMR1_INPUT_SEL - QTIMER5 TMR1 input select
9857  *  0b0..Input from IOMUX
9858  *  0b1..Input from XBAR
9859  */
9860 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR1_INPUT_SEL_MASK)
9861 
9862 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR2_INPUT_SEL_MASK (0x8U)
9863 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR2_INPUT_SEL_SHIFT (3U)
9864 /*! QTIMER5_TMR2_INPUT_SEL - QTIMER5 TMR2 input select
9865  *  0b0..Input from IOMUX
9866  *  0b1..Input from XBAR
9867  */
9868 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR2_INPUT_SEL_MASK)
9869 
9870 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR3_INPUT_SEL_MASK (0x10U)
9871 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR3_INPUT_SEL_SHIFT (4U)
9872 /*! QTIMER5_TMR3_INPUT_SEL - QTIMER5 TMR3 input select
9873  *  0b0..Input from IOMUX
9874  *  0b1..Input from XBAR
9875  */
9876 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER5_TMR3_INPUT_SEL_MASK)
9877 
9878 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR_CNTS_FREEZE_MASK (0x100U)
9879 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR_CNTS_FREEZE_SHIFT (8U)
9880 /*! QTIMER6_TMR_CNTS_FREEZE - QTIMER6 timer counter freeze */
9881 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR_CNTS_FREEZE_MASK)
9882 
9883 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR0_INPUT_SEL_MASK (0x200U)
9884 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR0_INPUT_SEL_SHIFT (9U)
9885 /*! QTIMER6_TMR0_INPUT_SEL - QTIMER6 TMR0 input select
9886  *  0b0..Input from IOMUX
9887  *  0b1..Input from XBAR
9888  */
9889 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR0_INPUT_SEL_MASK)
9890 
9891 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR1_INPUT_SEL_MASK (0x400U)
9892 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR1_INPUT_SEL_SHIFT (10U)
9893 /*! QTIMER6_TMR1_INPUT_SEL - QTIMER6 TMR1 input select
9894  *  0b0..Input from IOMUX
9895  *  0b1..Input from XBAR
9896  */
9897 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR1_INPUT_SEL_MASK)
9898 
9899 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR2_INPUT_SEL_MASK (0x800U)
9900 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR2_INPUT_SEL_SHIFT (11U)
9901 /*! QTIMER6_TMR2_INPUT_SEL - QTIMER6 TMR2 input select
9902  *  0b0..Input from IOMUX
9903  *  0b1..Input from XBAR
9904  */
9905 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR2_INPUT_SEL_MASK)
9906 
9907 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR3_INPUT_SEL_MASK (0x1000U)
9908 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR3_INPUT_SEL_SHIFT (12U)
9909 /*! QTIMER6_TMR3_INPUT_SEL - QTIMER6 TMR3 input select
9910  *  0b0..Input from IOMUX
9911  *  0b1..Input from XBAR
9912  */
9913 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER6_TMR3_INPUT_SEL_MASK)
9914 
9915 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR_CNTS_FREEZE_MASK (0x10000U)
9916 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR_CNTS_FREEZE_SHIFT (16U)
9917 /*! QTIMER7_TMR_CNTS_FREEZE - QTIMER7 timer counter freeze
9918  *  0b0..Timer counter works normally
9919  *  0b1..Reset counter and output flags
9920  */
9921 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR_CNTS_FREEZE_MASK)
9922 
9923 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR0_INPUT_SEL_MASK (0x20000U)
9924 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR0_INPUT_SEL_SHIFT (17U)
9925 /*! QTIMER7_TMR0_INPUT_SEL - QTIMER7 TMR0 input select
9926  *  0b0..Input from IOMUX
9927  *  0b1..Input from XBAR
9928  */
9929 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR0_INPUT_SEL_MASK)
9930 
9931 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR1_INPUT_SEL_MASK (0x40000U)
9932 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR1_INPUT_SEL_SHIFT (18U)
9933 /*! QTIMER7_TMR1_INPUT_SEL - QTIMER7 TMR1 input select
9934  *  0b0..Input from IOMUX
9935  *  0b1..Input from XBAR
9936  */
9937 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR1_INPUT_SEL_MASK)
9938 
9939 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR2_INPUT_SEL_MASK (0x80000U)
9940 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR2_INPUT_SEL_SHIFT (19U)
9941 /*! QTIMER7_TMR2_INPUT_SEL - QTIMER7 TMR2 input select
9942  *  0b0..Input from IOMUX
9943  *  0b1..Input from XBAR
9944  */
9945 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR2_INPUT_SEL_MASK)
9946 
9947 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR3_INPUT_SEL_MASK (0x100000U)
9948 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR3_INPUT_SEL_SHIFT (20U)
9949 /*! QTIMER7_TMR3_INPUT_SEL - QTIMER7 TMR3 input select
9950  *  0b0..Input from IOMUX
9951  *  0b1..Input from XBAR
9952  */
9953 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER7_TMR3_INPUT_SEL_MASK)
9954 
9955 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR_CNTS_FREEZE_MASK (0x1000000U)
9956 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR_CNTS_FREEZE_SHIFT (24U)
9957 /*! QTIMER8_TMR_CNTS_FREEZE - QTIMER8 timer counter freeze
9958  *  0b0..Timer counter works normally
9959  *  0b1..Reset counter and output flags
9960  */
9961 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR_CNTS_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR_CNTS_FREEZE_MASK)
9962 
9963 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR0_INPUT_SEL_MASK (0x2000000U)
9964 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR0_INPUT_SEL_SHIFT (25U)
9965 /*! QTIMER8_TMR0_INPUT_SEL - QTIMER8 TMR0 input select
9966  *  0b0..Input from IOMUX
9967  *  0b1..Input from XBAR
9968  */
9969 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR0_INPUT_SEL_MASK)
9970 
9971 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR1_INPUT_SEL_MASK (0x4000000U)
9972 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR1_INPUT_SEL_SHIFT (26U)
9973 /*! QTIMER8_TMR1_INPUT_SEL - QTIMER8 TMR1 input select
9974  *  0b0..Input from IOMUX
9975  *  0b1..Input from XBAR
9976  */
9977 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR1_INPUT_SEL_MASK)
9978 
9979 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR2_INPUT_SEL_MASK (0x8000000U)
9980 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR2_INPUT_SEL_SHIFT (27U)
9981 /*! QTIMER8_TMR2_INPUT_SEL - QTIMER8 TMR2 input select
9982  *  0b0..Input from IOMUX
9983  *  0b1..Input from XBAR
9984  */
9985 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR2_INPUT_SEL_MASK)
9986 
9987 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR3_INPUT_SEL_MASK (0x10000000U)
9988 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR3_INPUT_SEL_SHIFT (28U)
9989 /*! QTIMER8_TMR3_INPUT_SEL - QTIMER8 TMR3 input select
9990  *  0b0..Input from IOMUX
9991  *  0b1..Input from XBAR
9992  */
9993 #define BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_QTIMER_CTRL2_QTIMER8_TMR3_INPUT_SEL_MASK)
9994 /*! @} */
9995 
9996 /*! @name SAI2_MCLK_CTRL - SAI2 MCLK control register */
9997 /*! @{ */
9998 
9999 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL_MASK (0x3U)
10000 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL_SHIFT (0U)
10001 /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select
10002  *  0b00..SPDIF_CLK_ROOT
10003  *  0b01..spdif_tx_clk2
10004  *  0b10..spdif_srclk
10005  *  0b11..spdif_outclock
10006  */
10007 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK3_SEL_MASK)
10008 
10009 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK_DIR_MASK (0x100U)
10010 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK_DIR_SHIFT (8U)
10011 /*! SAI2_MCLK_DIR - SAI2_MCLK IO direction control. IOMUX need select SAI2 MCLK function.
10012  *  0b0..SAI2_MCLK is input signal
10013  *  0b1..SAI2_MCLK is output signal
10014  */
10015 #define BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI2_MCLK_CTRL_SAI2_MCLK_DIR_MASK)
10016 /*! @} */
10017 
10018 /*! @name SAI3_MCLK_CTRL - SAI3 MCLK control register */
10019 /*! @{ */
10020 
10021 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL_MASK (0x3U)
10022 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL_SHIFT (0U)
10023 /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select
10024  *  0b00..SPDIF_CLK_ROOT
10025  *  0b01..spdif_tx_clk2
10026  *  0b10..spdif_srclk
10027  *  0b11..spdif_outclock
10028  */
10029 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK3_SEL_MASK)
10030 
10031 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK_DIR_MASK (0x100U)
10032 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK_DIR_SHIFT (8U)
10033 /*! SAI3_MCLK_DIR - SAI3_MCLK IO direction control. IOMUX need select SAI3 MCLK function.
10034  *  0b0..SAI3_MCLK is input signal
10035  *  0b1..SAI3_MCLK is output signal
10036  */
10037 #define BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI3_MCLK_CTRL_SAI3_MCLK_DIR_MASK)
10038 /*! @} */
10039 
10040 /*! @name SAI4_MCLK_CTRL - SAI4 MCLK control register */
10041 /*! @{ */
10042 
10043 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL_MASK (0x7U)
10044 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL_SHIFT (0U)
10045 /*! SAI4_MCLK1_SEL - SAI4 MCLK1 source select
10046  *  0b000..SAI4_CLK_ROOT
10047  *  0b001..SAI2_CLK_ROOT
10048  *  0b011..SAI3_CLK_ROOT
10049  *  0b100..SAI4 MCLK IO pin
10050  *  0b101..SAI2 MCLK IO pin
10051  *  0b110..SAI3 MCLK IO pin
10052  *  0b111..Reserved
10053  */
10054 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK1_SEL_MASK)
10055 
10056 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL_MASK (0x38U)
10057 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL_SHIFT (3U)
10058 /*! SAI4_MCLK2_SEL - SAI4 MCLK2 source select
10059  *  0b000..SAI4_CLK_ROOT
10060  *  0b001..SAI2_CLK_ROOT
10061  *  0b011..SAI3_CLK_ROOT
10062  *  0b100..SAI4 MCLK IO pin
10063  *  0b101..SAI2 MCLK IO pin
10064  *  0b110..SAI3 MCLK IO pin
10065  *  0b111..Reserved
10066  */
10067 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK2_SEL_MASK)
10068 
10069 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL_MASK (0xC0U)
10070 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL_SHIFT (6U)
10071 /*! SAI4_MCLK3_SEL - SAI4 MCLK3 source select
10072  *  0b00..SPDIF_CLK_ROOT
10073  *  0b01..spdif_tx_clk2
10074  *  0b10..spdif_srclk
10075  *  0b11..spdif_outclock
10076  */
10077 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK3_SEL_MASK)
10078 
10079 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK_DIR_MASK (0x100U)
10080 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK_DIR_SHIFT (8U)
10081 /*! SAI4_MCLK_DIR - SAI4_MCLK IO direction control. IOMUX need select SAI4 MCLK function. */
10082 #define BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK_DIR_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI4_MCLK_CTRL_SAI4_MCLK_DIR_MASK)
10083 /*! @} */
10084 
10085 /*! @name XBAR_DIR_CTRL1 - XBAR IO direction control register */
10086 /*! @{ */
10087 
10088 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10U)
10089 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_4_SHIFT (4U)
10090 /*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select
10091  *  0b0..XBAR_INOUT as input
10092  *  0b1..XBAR_INOUT as output
10093  */
10094 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_4_MASK)
10095 
10096 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20U)
10097 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_5_SHIFT (5U)
10098 /*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select
10099  *  0b0..XBAR_INOUT as input
10100  *  0b1..XBAR_INOUT as output
10101  */
10102 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_5_MASK)
10103 
10104 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40U)
10105 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_6_SHIFT (6U)
10106 /*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select
10107  *  0b0..XBAR_INOUT as input
10108  *  0b1..XBAR_INOUT as output
10109  */
10110 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_6_MASK)
10111 
10112 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80U)
10113 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_7_SHIFT (7U)
10114 /*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select
10115  *  0b0..XBAR_INOUT as input
10116  *  0b1..XBAR_INOUT as output
10117  */
10118 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_7_MASK)
10119 
10120 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100U)
10121 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_8_SHIFT (8U)
10122 /*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select
10123  *  0b0..XBAR_INOUT as input
10124  *  0b1..XBAR_INOUT as output
10125  */
10126 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_8_MASK)
10127 
10128 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200U)
10129 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_9_SHIFT (9U)
10130 /*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select
10131  *  0b0..XBAR_INOUT as input
10132  *  0b1..XBAR_INOUT as output
10133  */
10134 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_9_MASK)
10135 
10136 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400U)
10137 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_10_SHIFT (10U)
10138 /*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select
10139  *  0b0..XBAR_INOUT as input
10140  *  0b1..XBAR_INOUT as output
10141  */
10142 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_10_MASK)
10143 
10144 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800U)
10145 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_11_SHIFT (11U)
10146 /*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select
10147  *  0b0..XBAR_INOUT as input
10148  *  0b1..XBAR_INOUT as output
10149  */
10150 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_11_MASK)
10151 
10152 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000U)
10153 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_12_SHIFT (12U)
10154 /*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select
10155  *  0b0..XBAR_INOUT as input
10156  *  0b1..XBAR_INOUT as output
10157  */
10158 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_12_MASK)
10159 
10160 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000U)
10161 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_13_SHIFT (13U)
10162 /*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select
10163  *  0b0..XBAR_INOUT as input
10164  *  0b1..XBAR_INOUT as output
10165  */
10166 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_13_MASK)
10167 
10168 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000U)
10169 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_14_SHIFT (14U)
10170 /*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select
10171  *  0b0..XBAR_INOUT as input
10172  *  0b1..XBAR_INOUT as output
10173  */
10174 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_14_MASK)
10175 
10176 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000U)
10177 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_15_SHIFT (15U)
10178 /*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select
10179  *  0b0..XBAR_INOUT as input
10180  *  0b1..XBAR_INOUT as output
10181  */
10182 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_15_MASK)
10183 
10184 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000U)
10185 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_16_SHIFT (16U)
10186 /*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select
10187  *  0b0..XBAR_INOUT as input
10188  *  0b1..XBAR_INOUT as output
10189  */
10190 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_16_MASK)
10191 
10192 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000U)
10193 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_SHIFT (17U)
10194 /*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select
10195  *  0b0..XBAR_INOUT as input
10196  *  0b1..XBAR_INOUT as output
10197  */
10198 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_17_MASK)
10199 
10200 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000U)
10201 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_SHIFT (18U)
10202 /*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select
10203  *  0b0..XBAR_INOUT as input
10204  *  0b1..XBAR_INOUT as output
10205  */
10206 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_18_MASK)
10207 
10208 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000U)
10209 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_19_SHIFT (19U)
10210 /*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select
10211  *  0b0..XBAR_INOUT as input
10212  *  0b1..XBAR_INOUT as output
10213  */
10214 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_19_MASK)
10215 
10216 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_20_MASK (0x100000U)
10217 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_20_SHIFT (20U)
10218 /*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select
10219  *  0b0..XBAR_INOUT as input
10220  *  0b1..XBAR_INOUT as output
10221  */
10222 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_20_MASK)
10223 
10224 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_21_MASK (0x200000U)
10225 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_21_SHIFT (21U)
10226 /*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select
10227  *  0b0..XBAR_INOUT as input
10228  *  0b1..XBAR_INOUT as output
10229  */
10230 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_21_MASK)
10231 
10232 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_22_MASK (0x400000U)
10233 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_22_SHIFT (22U)
10234 /*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select
10235  *  0b0..XBAR_INOUT as input
10236  *  0b1..XBAR_INOUT as output
10237  */
10238 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_22_MASK)
10239 
10240 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_23_MASK (0x800000U)
10241 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_23_SHIFT (23U)
10242 /*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select
10243  *  0b0..XBAR_INOUT as input
10244  *  0b1..XBAR_INOUT as output
10245  */
10246 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_23_MASK)
10247 
10248 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_24_MASK (0x1000000U)
10249 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_24_SHIFT (24U)
10250 /*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select
10251  *  0b0..XBAR_INOUT as input
10252  *  0b1..XBAR_INOUT as output
10253  */
10254 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_24_MASK)
10255 
10256 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_25_MASK (0x2000000U)
10257 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_25_SHIFT (25U)
10258 /*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select
10259  *  0b0..XBAR_INOUT as input
10260  *  0b1..XBAR_INOUT as output
10261  */
10262 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_25_MASK)
10263 
10264 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_26_MASK (0x4000000U)
10265 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_26_SHIFT (26U)
10266 /*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select
10267  *  0b0..XBAR_INOUT as input
10268  *  0b1..XBAR_INOUT as output
10269  */
10270 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_26_MASK)
10271 
10272 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_27_MASK (0x8000000U)
10273 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_27_SHIFT (27U)
10274 /*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select
10275  *  0b0..XBAR_INOUT as input
10276  *  0b1..XBAR_INOUT as output
10277  */
10278 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_27_MASK)
10279 
10280 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_28_MASK (0x10000000U)
10281 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_28_SHIFT (28U)
10282 /*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select
10283  *  0b0..XBAR_INOUT as input
10284  *  0b1..XBAR_INOUT as output
10285  */
10286 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_28_MASK)
10287 
10288 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_29_MASK (0x20000000U)
10289 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_29_SHIFT (29U)
10290 /*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select
10291  *  0b0..XBAR_INOUT as input
10292  *  0b1..XBAR_INOUT as output
10293  */
10294 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_29_MASK)
10295 
10296 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_30_MASK (0x40000000U)
10297 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_30_SHIFT (30U)
10298 /*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select
10299  *  0b0..XBAR_INOUT as input
10300  *  0b1..XBAR_INOUT as output
10301  */
10302 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_30_MASK)
10303 
10304 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_31_MASK (0x80000000U)
10305 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_31_SHIFT (31U)
10306 /*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select
10307  *  0b0..XBAR_INOUT as input
10308  *  0b1..XBAR_INOUT as output
10309  */
10310 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL1_IOMUXC_XBAR_DIR_SEL_31_MASK)
10311 /*! @} */
10312 
10313 /*! @name XBAR_DIR_CTRL2 - XBAR IO direction control register */
10314 /*! @{ */
10315 
10316 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
10317 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
10318 /*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select
10319  *  0b0..XBAR_INOUT as input
10320  *  0b1..XBAR_INOUT as output
10321  */
10322 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_32_MASK)
10323 
10324 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
10325 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
10326 /*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select
10327  *  0b0..XBAR_INOUT as input
10328  *  0b1..XBAR_INOUT as output
10329  */
10330 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_33_MASK)
10331 
10332 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
10333 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
10334 /*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select
10335  *  0b0..XBAR_INOUT as input
10336  *  0b1..XBAR_INOUT as output
10337  */
10338 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_34_MASK)
10339 
10340 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
10341 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
10342 /*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select
10343  *  0b0..XBAR_INOUT as input
10344  *  0b1..XBAR_INOUT as output
10345  */
10346 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_35_MASK)
10347 
10348 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
10349 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
10350 /*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select
10351  *  0b0..XBAR_INOUT as input
10352  *  0b1..XBAR_INOUT as output
10353  */
10354 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_36_MASK)
10355 
10356 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
10357 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
10358 /*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select
10359  *  0b0..XBAR_INOUT as input
10360  *  0b1..XBAR_INOUT as output
10361  */
10362 #define BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_DIR_CTRL2_IOMUXC_XBAR_DIR_SEL_37_MASK)
10363 /*! @} */
10364 
10365 /*! @name LPIT_TRIG_SEL - LPIT trigger input select register */
10366 /*! @{ */
10367 
10368 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG0_INPUT_SEL_MASK (0x1U)
10369 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG0_INPUT_SEL_SHIFT (0U)
10370 /*! LPIT1_TRIG0_INPUT_SEL - LPIT1 TRIG0 input select
10371  *  0b0..Input from IOMUX
10372  *  0b1..Input from XBAR
10373  */
10374 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG0_INPUT_SEL_MASK)
10375 
10376 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG1_INPUT_SEL_MASK (0x2U)
10377 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG1_INPUT_SEL_SHIFT (1U)
10378 /*! LPIT1_TRIG1_INPUT_SEL - LPIT1 TRIG1 input select
10379  *  0b0..Input from IOMUX
10380  *  0b1..Input from XBAR
10381  */
10382 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG1_INPUT_SEL_MASK)
10383 
10384 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG2_INPUT_SEL_MASK (0x4U)
10385 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG2_INPUT_SEL_SHIFT (2U)
10386 /*! LPIT1_TRIG2_INPUT_SEL - LPIT1 TRIG2 input select
10387  *  0b0..Input from IOMUX
10388  *  0b1..Input from XBAR
10389  */
10390 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG2_INPUT_SEL_MASK)
10391 
10392 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG3_INPUT_SEL_MASK (0x8U)
10393 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG3_INPUT_SEL_SHIFT (3U)
10394 /*! LPIT1_TRIG3_INPUT_SEL - LPIT1 TRIG3 input select
10395  *  0b0..Input from IOMUX
10396  *  0b1..Input from XBAR
10397  */
10398 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT1_TRIG3_INPUT_SEL_MASK)
10399 
10400 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG0_INPUT_SEL_MASK (0x100U)
10401 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG0_INPUT_SEL_SHIFT (8U)
10402 /*! LPIT2_TRIG0_INPUT_SEL - LPIT2 TRIG0 input select
10403  *  0b0..Input from IOMUX
10404  *  0b1..Input from XBAR
10405  */
10406 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG0_INPUT_SEL_MASK)
10407 
10408 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG1_INPUT_SEL_MASK (0x200U)
10409 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG1_INPUT_SEL_SHIFT (9U)
10410 /*! LPIT2_TRIG1_INPUT_SEL - LPIT2 TRIG1 input select
10411  *  0b0..Input from IOMUX
10412  *  0b1..Input from XBAR
10413  */
10414 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG1_INPUT_SEL_MASK)
10415 
10416 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG2_INPUT_SEL_MASK (0x400U)
10417 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG2_INPUT_SEL_SHIFT (10U)
10418 /*! LPIT2_TRIG2_INPUT_SEL - LPIT2 TRIG2 input select
10419  *  0b0..Input from IOMUX
10420  *  0b1..Input from XBAR
10421  */
10422 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG2_INPUT_SEL_MASK)
10423 
10424 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG3_INPUT_SEL_MASK (0x800U)
10425 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG3_INPUT_SEL_SHIFT (11U)
10426 /*! LPIT2_TRIG3_INPUT_SEL - LPIT2 TRIG3 input select
10427  *  0b0..Input from IOMUX
10428  *  0b1..Input from XBAR
10429  */
10430 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT2_TRIG3_INPUT_SEL_MASK)
10431 
10432 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG0_INPUT_SEL_MASK (0x10000U)
10433 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG0_INPUT_SEL_SHIFT (16U)
10434 /*! LPIT3_TRIG0_INPUT_SEL - LPIT3 TRIG0 input select
10435  *  0b0..Input from IOMUX
10436  *  0b1..Input from XBAR
10437  */
10438 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG0_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG0_INPUT_SEL_MASK)
10439 
10440 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG1_INPUT_SEL_MASK (0x20000U)
10441 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG1_INPUT_SEL_SHIFT (17U)
10442 /*! LPIT3_TRIG1_INPUT_SEL - LPIT3 TRIG1 input select
10443  *  0b0..Input from IOMUX
10444  *  0b1..Input from XBAR
10445  */
10446 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG1_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG1_INPUT_SEL_MASK)
10447 
10448 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG2_INPUT_SEL_MASK (0x40000U)
10449 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG2_INPUT_SEL_SHIFT (18U)
10450 /*! LPIT3_TRIG2_INPUT_SEL - LPIT3 TRIG2 input select
10451  *  0b0..Input from IOMUX
10452  *  0b1..Input from XBAR
10453  */
10454 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG2_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG2_INPUT_SEL_MASK)
10455 
10456 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG3_INPUT_SEL_MASK (0x80000U)
10457 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG3_INPUT_SEL_SHIFT (19U)
10458 /*! LPIT3_TRIG3_INPUT_SEL - LPIT3 TRIG3 input select
10459  *  0b0..Input from IOMUX
10460  *  0b1..Input from XBAR
10461  */
10462 #define BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG3_INPUT_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_LPIT_TRIG_SEL_LPIT3_TRIG3_INPUT_SEL_MASK)
10463 /*! @} */
10464 
10465 /*! @name AXI_ATTR_CFG - AXI bus attribute configuration register */
10466 /*! @{ */
10467 
10468 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK (0x1U)
10469 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT (0U)
10470 /*! ARCACHE_USDHC1 - uSDHC1 block cacheable attribute value of AXI read transactions
10471  *  0b0..Cacheable attribute is off for read transactions
10472  *  0b1..Cacheable attribute is on for read transactions
10473  */
10474 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK)
10475 
10476 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK (0x2U)
10477 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT (1U)
10478 /*! AWCACHE_USDHC1 - uSDHC1 block cacheable attribute value of AXI write transactions
10479  *  0b0..Cacheable attribute is off for write transactions
10480  *  0b1..Cacheable attribute is on for write transactions
10481  */
10482 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK)
10483 
10484 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK (0x4U)
10485 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT (2U)
10486 /*! ARCACHE_USDHC2 - uSDHC2 block cacheable attribute value of AXI read transactions
10487  *  0b0..Cacheable attribute is off for read transactions
10488  *  0b1..Cacheable attribute is on for read transactions
10489  */
10490 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK)
10491 
10492 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK (0x8U)
10493 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT (3U)
10494 /*! AWCACHE_USDHC2 - uSDHC2 block cacheable attribute value of AXI write transactions
10495  *  0b0..Cacheable attribute is off for write transactions
10496  *  0b1..Cacheable attribute is on for write transactions
10497  */
10498 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK)
10499 
10500 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USB_MASK (0x10U)
10501 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USB_SHIFT (4U)
10502 /*! ARCACHE_USB - USB block cacheable attribute value of AXI read transactions
10503  *  0b0..Cacheable attribute is off for read transactions
10504  *  0b1..Cacheable attribute is on for read transactions
10505  */
10506 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USB_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USB_MASK)
10507 
10508 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USB_MASK (0x20U)
10509 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USB_SHIFT (5U)
10510 /*! AWCACHE_USB - USB block cacheable attribute value of AXI write transactions
10511  *  0b0..Cacheable attribute is off for write transactions
10512  *  0b1..Cacheable attribute is on for write transactions
10513  */
10514 #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USB_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USB_MASK)
10515 /*! @} */
10516 
10517 /*! @name SRAMCR0 - SRAM Control Register 0 */
10518 /*! @{ */
10519 
10520 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO_MASK      (0xFFU)
10521 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO_SHIFT     (0U)
10522 /*! BTO - AHB Bus Timeout Wait Cycle */
10523 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_BTO_MASK)
10524 
10525 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN_MASK    (0x100U)
10526 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN_SHIFT   (8U)
10527 /*! BTOEN - AHB Bus Timeout Enable
10528  *  0b0..AHB bus timeout counter is not enabled.
10529  *  0b1..AHB bus timeout counter is enabled.
10530  */
10531 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN(x)      (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_BTOEN_MASK)
10532 
10533 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_PS_MASK       (0x200U)
10534 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_PS_SHIFT      (9U)
10535 /*! PS - Port Size
10536  *  0b0..8bit
10537  *  0b1..16bit
10538  */
10539 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_PS(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_PS_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_PS_MASK)
10540 
10541 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AM_MASK       (0x400U)
10542 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AM_SHIFT      (10U)
10543 /*! AM - Address Mode
10544  *  0b0..Address/Data MUX mode (ADMUX)
10545  *  0b1..Address/Data non-MUX mode (Non-ADMUX)
10546  */
10547 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AM(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_AM_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_AM_MASK)
10548 
10549 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP_MASK     (0x800U)
10550 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP_SHIFT    (11U)
10551 /*! ADVP - ADV# polarity
10552  *  0b0..ADV# is active low.
10553  *  0b1..ADV# is active high.
10554  */
10555 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP(x)       (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_ADVP_MASK)
10556 
10557 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CES_MASK      (0xF000U)
10558 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CES_SHIFT     (12U)
10559 /*! CES - CE setup time */
10560 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CES(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_CES_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_CES_MASK)
10561 
10562 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH_MASK      (0xF0000U)
10563 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH_SHIFT     (16U)
10564 /*! CEH - CE hold time */
10565 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_CEH_MASK)
10566 
10567 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AS_MASK       (0xF00000U)
10568 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AS_SHIFT      (20U)
10569 /*! AS - Address setup time */
10570 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AS(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_AS_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_AS_MASK)
10571 
10572 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AH_MASK       (0xF000000U)
10573 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AH_SHIFT      (24U)
10574 /*! AH - Address hold time */
10575 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_AH(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_AH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_AH_MASK)
10576 
10577 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_TA_MASK       (0xF0000000U)
10578 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_TA_SHIFT      (28U)
10579 /*! TA - Turnaround time */
10580 #define BLK_CTRL_WAKEUPMIX_SRAMCR0_TA(x)         (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR0_TA_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR0_TA_MASK)
10581 /*! @} */
10582 
10583 /*! @name SRAMCR1 - SRAM Control Register 1 */
10584 /*! @{ */
10585 
10586 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL_MASK      (0x3FU)
10587 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL_SHIFT     (0U)
10588 /*! WEL - WE low time */
10589 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR1_WEL_MASK)
10590 
10591 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH_MASK      (0x3C0U)
10592 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH_SHIFT     (6U)
10593 /*! WEH - WE high time */
10594 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR1_WEH_MASK)
10595 
10596 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REL_MASK      (0xFC00U)
10597 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REL_SHIFT     (10U)
10598 /*! REL - RE low time */
10599 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REL(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR1_REL_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR1_REL_MASK)
10600 
10601 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REH_MASK      (0xF0000U)
10602 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REH_SHIFT     (16U)
10603 /*! REH - RE high time */
10604 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_REH(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR1_REH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR1_REH_MASK)
10605 
10606 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE_MASK      (0x300000U)
10607 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE_SHIFT     (20U)
10608 /*! PRE - Prescaler timer
10609  *  0b00..Time granularity is 1 clock cycle.
10610  *  0b01..Time granularity is 2 clock cycles.
10611  *  0b10..Time granularity is 3 clock cycles.
10612  *  0b11..Time granularity is 4 clock cycles.
10613  */
10614 #define BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE(x)        (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SRAMCR1_PRE_MASK)
10615 /*! @} */
10616 
10617 /*! @name SLAVE_STOP_MODE_CFG - Slave stop mode configure register */
10618 /*! @{ */
10619 
10620 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC1_IPG_STOP_MODE_MASK (0x10U)
10621 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC1_IPG_STOP_MODE_SHIFT (4U)
10622 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection.
10623  *  0b0..This module is functional in Stop Mode
10624  *  0b1..This module is not functional in Stop Mode
10625  */
10626 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC1_IPG_STOP_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC1_IPG_STOP_MODE_MASK)
10627 
10628 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC2_IPG_STOP_MODE_MASK (0x20U)
10629 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC2_IPG_STOP_MODE_SHIFT (5U)
10630 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection.
10631  *  0b0..This module is functional in Stop Mode
10632  *  0b1..This module is not functional in Stop Mode
10633  */
10634 #define BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC2_IPG_STOP_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SLAVE_STOP_MODE_CFG_ADC2_IPG_STOP_MODE_MASK)
10635 /*! @} */
10636 
10637 /*! @name I3C2_ASYNC_WAKEUP_CTRL - I3C2 async wakeup control register */
10638 /*! @{ */
10639 
10640 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_CLR_MASK (0x1U)
10641 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_CLR_SHIFT (0U)
10642 /*! IRQ_CLR - Async wakeup interrupt clear */
10643 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_CLR_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_CLR_MASK)
10644 
10645 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_STATUS_MASK (0x10000U)
10646 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_STATUS_SHIFT (16U)
10647 /*! IRQ_STATUS - Async wakeup interrupt status
10648  *  0b0..Interrupt not asserted
10649  *  0b1..Interrupt asserted
10650  */
10651 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_STATUS_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_STATUS_MASK)
10652 
10653 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_EN_MASK (0x80000000U)
10654 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_EN_SHIFT (31U)
10655 /*! IRQ_EN - Master mode async wakeup interrupt enable
10656  *  0b0..Interrupt disabled
10657  *  0b1..Interrupt enabled
10658  */
10659 #define BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_ASYNC_WAKEUP_CTRL_IRQ_EN_MASK)
10660 /*! @} */
10661 
10662 /*! @name XBAR_AOI_WE - XBAR and AOI write protect register */
10663 /*! @{ */
10664 
10665 #define BLK_CTRL_WAKEUPMIX_XBAR_AOI_WE_WE_MASK   (0x1U)
10666 #define BLK_CTRL_WAKEUPMIX_XBAR_AOI_WE_WE_SHIFT  (0U)
10667 /*! WE - Write Enable to XBAR and AOI
10668  *  0b0..Write is disabled
10669  *  0b1..Write is enabled
10670  */
10671 #define BLK_CTRL_WAKEUPMIX_XBAR_AOI_WE_WE(x)     (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_AOI_WE_WE_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_AOI_WE_WE_MASK)
10672 /*! @} */
10673 
10674 /*! @name XBAR_TRIG_SYNC_CTRL1 - XBAR trigger synchronizer control register1 */
10675 /*! @{ */
10676 
10677 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_POL_SEL_MASK (0xFFU)
10678 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_POL_SEL_SHIFT (0U)
10679 /*! POL_SEL - Trigger out polarity select
10680  *  0b00000000..Same as trigger in
10681  *  0b00000001..Invert trigger in
10682  */
10683 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_POL_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_POL_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_POL_SEL_MASK)
10684 
10685 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_ASYNC_EN_MASK (0xFF00U)
10686 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_ASYNC_EN_SHIFT (8U)
10687 /*! ASYNC_EN - Asynchronous trigger in enable
10688  *  0b00000000..Trigger in is synchronous
10689  *  0b00000001..Trigger in is asynchronous
10690  */
10691 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_ASYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_ASYNC_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_ASYNC_EN_MASK)
10692 
10693 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_SYNC_ENABLE_MASK (0xFF0000U)
10694 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_SYNC_ENABLE_SHIFT (16U)
10695 /*! SYNC_ENABLE - Trigger out synchronizer enable
10696  *  0b00000000..Channel is disabled
10697  *  0b00000001..Channel is enabled
10698  */
10699 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_SYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_SYNC_ENABLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL1_SYNC_ENABLE_MASK)
10700 /*! @} */
10701 
10702 /*! @name XBAR_TRIG_SYNC_CTRL2 - XBAR trigger synchronizer control register2 */
10703 /*! @{ */
10704 
10705 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH0_MASK (0xFU)
10706 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH0_SHIFT (0U)
10707 /*! PULSE_WIDTH0 - Pulse width control register of channel0 */
10708 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH0_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH0_MASK)
10709 
10710 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH1_MASK (0xF0U)
10711 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH1_SHIFT (4U)
10712 /*! PULSE_WIDTH1 - Pulse width control register of channel1 */
10713 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH1_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH1_MASK)
10714 
10715 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH2_MASK (0xF00U)
10716 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH2_SHIFT (8U)
10717 /*! PULSE_WIDTH2 - Pulse width control register of channel2 */
10718 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH2_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH2_MASK)
10719 
10720 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH3_MASK (0xF000U)
10721 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH3_SHIFT (12U)
10722 /*! PULSE_WIDTH3 - Pulse width control register of channel3 */
10723 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH3_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH3_MASK)
10724 
10725 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH4_MASK (0xF0000U)
10726 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH4_SHIFT (16U)
10727 /*! PULSE_WIDTH4 - Pulse width control register of channel4 */
10728 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH4_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH4_MASK)
10729 
10730 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH5_MASK (0xF00000U)
10731 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH5_SHIFT (20U)
10732 /*! PULSE_WIDTH5 - Pulse width control register of channel5 */
10733 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH5_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH5_MASK)
10734 
10735 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH6_MASK (0xF000000U)
10736 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH6_SHIFT (24U)
10737 /*! PULSE_WIDTH6 - Pulse width control register of channel6 */
10738 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH6_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH6_MASK)
10739 
10740 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH7_MASK (0xF0000000U)
10741 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH7_SHIFT (28U)
10742 /*! PULSE_WIDTH7 - Pulse width control register of channel7 */
10743 #define BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH7_SHIFT)) & BLK_CTRL_WAKEUPMIX_XBAR_TRIG_SYNC_CTRL2_PULSE_WIDTH7_MASK)
10744 /*! @} */
10745 
10746 /*! @name NETC_LINK_CFG - NETC link configuration for port0..NETC link configuration for port4 */
10747 /*! @{ */
10748 
10749 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT_MASK (0xFU)
10750 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT_SHIFT (0U)
10751 /*! MII_PROT - MII protocol selection
10752  *  0b0000..MII
10753  *  0b0001..RMII
10754  *  0b0010..RGMII
10755  *  0b0100-0b1111..Reserved
10756  */
10757 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT_MASK)
10758 
10759 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_IO_VAR_MASK (0xF0000U)
10760 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_IO_VAR_SHIFT (16U)
10761 /*! IO_VAR - IO variant selection
10762  *  0b0000..None
10763  *  0b0001-0b1110..Reserved
10764  */
10765 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_IO_VAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_IO_VAR_MASK)
10766 
10767 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_RATE_MASK (0x1000000U)
10768 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_RATE_SHIFT (24U)
10769 /*! REVMII_RATE - When REVMII=1 and MII_PROT=MII, this bit configures RevMII rates, otherwise this field has no meaning.
10770  *  0b0..MII interface is operating at 100Mbps
10771  *  0b1..MII interface is operating at 10Mbps
10772  */
10773 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_RATE_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_RATE_MASK)
10774 
10775 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_MASK (0x80000000U)
10776 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_SHIFT (31U)
10777 /*! REVMII - RevMII selection
10778  *  0b0..RevMII not selected
10779  *  0b1..RevMII selected
10780  */
10781 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_REVMII_MASK)
10782 /*! @} */
10783 
10784 /* The count of BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG */
10785 #define BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_COUNT   (5U)
10786 
10787 /*! @name NETC_REVMII_DLL - NETC RevMII RGMII delay line configuration for port0..NETC RevMII RGMII delay line configuration for port4 */
10788 /*! @{ */
10789 
10790 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_DLY_TARGET_MASK (0xFU)
10791 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_DLY_TARGET_SHIFT (0U)
10792 /*! DLY_TARGET - Delay target of slave delay line */
10793 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_DLY_TARGET_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_DLY_TARGET_MASK)
10794 
10795 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_REF_LOCK_MASK (0x10000U)
10796 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_REF_LOCK_SHIFT (16U)
10797 /*! REF_LOCK - Reference delay line lock flag
10798  *  0b0..Reference delay line is not locked
10799  *  0b1..Reference delay line is locked
10800  */
10801 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_REF_LOCK_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_REF_LOCK_MASK)
10802 
10803 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_SLV_LOCK_MASK (0x20000U)
10804 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_SLV_LOCK_SHIFT (17U)
10805 /*! SLV_LOCK - Slave delay line lock flag
10806  *  0b0..Slave delay line is not locked
10807  *  0b1..Slave delay line is locked
10808  */
10809 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_SLV_LOCK_SHIFT)) & BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_SLV_LOCK_MASK)
10810 /*! @} */
10811 
10812 /* The count of BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL */
10813 #define BLK_CTRL_WAKEUPMIX_NETC_REVMII_DLL_COUNT (5U)
10814 
10815 /*! @name SAFETY_CLK_MON_CS - Safety clock monitor control and status register */
10816 /*! @{ */
10817 
10818 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_MON_EN_MASK (0x1U)
10819 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_MON_EN_SHIFT (0U)
10820 /*! MON_EN - Monitor enable bit
10821  *  0b0..The monitor is off
10822  *  0b1..The monitor is on
10823  */
10824 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_MON_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_MON_EN_MASK)
10825 
10826 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_IRQ_EN_MASK (0x2U)
10827 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_IRQ_EN_SHIFT (1U)
10828 /*! IRQ_EN - Interrupt enable
10829  *  0b0..Clock failure will not assert interrupt
10830  *  0b1..Clock failure will assert interrupt
10831  */
10832 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_IRQ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_IRQ_EN_MASK)
10833 
10834 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_FAST_RST_EN_MASK (0x4U)
10835 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_FAST_RST_EN_SHIFT (2U)
10836 /*! FAST_RST_EN - Reset out enable
10837  *  0b0..Clock failure will not assert EWM_OUT
10838  *  0b1..Clock failure will assert EWM_OUT_b immediately regardless EWM state
10839  */
10840 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_FAST_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_FAST_RST_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_FAST_RST_EN_MASK)
10841 
10842 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_CLR_MASK (0x100U)
10843 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_CLR_SHIFT (8U)
10844 /*! STAT_CLR - Status clear
10845  *  0b0..No effect to clock failure status bit
10846  *  0b1..Clear clock failure status bit
10847  */
10848 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_CLR_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_CLR_MASK)
10849 
10850 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_MASK (0x1000000U)
10851 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_SHIFT (24U)
10852 /*! STAT - XBAR_OUT220 clock failure status
10853  *  0b0..No failure detected by the monitor
10854  *  0b1..Clock failure has been detected by the monitor
10855  */
10856 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_CS_STAT_MASK)
10857 /*! @} */
10858 
10859 /*! @name SAFETY_CLK_MON_TH - Safety clock monitor threshold register */
10860 /*! @{ */
10861 
10862 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_LOW_MASK (0xFFFFU)
10863 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_LOW_SHIFT (0U)
10864 /*! TH_LOW - Threshold low value */
10865 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_LOW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_LOW_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_LOW_MASK)
10866 
10867 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_HIGH_MASK (0xFFFF0000U)
10868 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_HIGH_SHIFT (16U)
10869 /*! TH_HIGH - Threshold high value */
10870 #define BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_HIGH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_HIGH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAFETY_CLK_MON_TH_TH_HIGH_MASK)
10871 /*! @} */
10872 
10873 /*! @name EMC_B1_IO_CTRL - GPIO_EMC_B1 bank IO control */
10874 /*! @{ */
10875 
10876 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FREEZE_MASK (0x1U)
10877 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FREEZE_SHIFT (0U)
10878 /*! GPIO_EMC1_FREEZE - Compensation code freeze */
10879 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FREEZE_MASK)
10880 
10881 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPTQ_MASK (0x2U)
10882 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPTQ_SHIFT (1U)
10883 /*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
10884 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPTQ_MASK)
10885 
10886 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPEN_MASK (0x4U)
10887 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPEN_SHIFT (2U)
10888 /*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
10889 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPEN_MASK)
10890 
10891 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
10892 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
10893 /*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze enable */
10894 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_EN_MASK)
10895 
10896 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCP_MASK (0xF0U)
10897 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCP_SHIFT (4U)
10898 /*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core */
10899 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCP_MASK)
10900 
10901 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCN_MASK (0xF00U)
10902 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCN_SHIFT (8U)
10903 /*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core */
10904 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_RASRCN_MASK)
10905 
10906 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
10907 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
10908 /*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection */
10909 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SELECT_NASRC_MASK)
10910 
10911 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
10912 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
10913 /*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable */
10914 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_REFGEN_SLEEP_MASK)
10915 
10916 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
10917 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
10918 /*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable */
10919 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_SUPLYDET_LATCH_MASK)
10920 
10921 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_MASK (0x8000U)
10922 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_SHIFT (15U)
10923 /*! GPIO_EMC1_FASTFRZ - Compensation code fast-freeze */
10924 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_FASTFRZ_MASK)
10925 
10926 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPOK_MASK (0x100000U)
10927 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPOK_SHIFT (20U)
10928 /*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag */
10929 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_COMPOK_MASK)
10930 
10931 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_NASRC_MASK (0x1E00000U)
10932 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_NASRC_SHIFT (21U)
10933 /*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes */
10934 #define BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B1_IO_CTRL_GPIO_EMC1_NASRC_MASK)
10935 /*! @} */
10936 
10937 /*! @name EMC_B2_IO_CTRL - GPIO_EMC_B2 bank IO control */
10938 /*! @{ */
10939 
10940 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FREEZE_MASK (0x1U)
10941 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FREEZE_SHIFT (0U)
10942 /*! GPIO_EMC2_FREEZE - Compensation code freeze */
10943 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FREEZE_MASK)
10944 
10945 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPTQ_MASK (0x2U)
10946 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPTQ_SHIFT (1U)
10947 /*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
10948 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPTQ_MASK)
10949 
10950 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPEN_MASK (0x4U)
10951 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPEN_SHIFT (2U)
10952 /*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
10953 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPEN_MASK)
10954 
10955 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
10956 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
10957 /*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze enable */
10958 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_EN_MASK)
10959 
10960 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCP_MASK (0xF0U)
10961 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCP_SHIFT (4U)
10962 /*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core */
10963 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCP_MASK)
10964 
10965 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCN_MASK (0xF00U)
10966 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCN_SHIFT (8U)
10967 /*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core */
10968 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_RASRCN_MASK)
10969 
10970 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
10971 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
10972 /*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection
10973  *  0b0..Show the 4-bit PMOS compensation codes in GPIO_EMC2_NASRC field
10974  *  0b1..Show the 4-bit NMOS compensation codes in GPIO_EMC2_NASRC field
10975  */
10976 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SELECT_NASRC_MASK)
10977 
10978 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
10979 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
10980 /*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable */
10981 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_REFGEN_SLEEP_MASK)
10982 
10983 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
10984 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
10985 /*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable */
10986 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_SUPLYDET_LATCH_MASK)
10987 
10988 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_MASK (0x8000U)
10989 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_SHIFT (15U)
10990 /*! GPIO_EMC2_FASTFRZ - Compensation code fast-freeze */
10991 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_FASTFRZ_MASK)
10992 
10993 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPOK_MASK (0x100000U)
10994 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPOK_SHIFT (20U)
10995 /*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag */
10996 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_COMPOK_MASK)
10997 
10998 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_NASRC_MASK (0x1E00000U)
10999 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_NASRC_SHIFT (21U)
11000 /*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes */
11001 #define BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_EMC_B2_IO_CTRL_GPIO_EMC2_NASRC_MASK)
11002 /*! @} */
11003 
11004 /*! @name SD_B1_IO_CTRL - GPIO_SD_B1 bank IO control */
11005 /*! @{ */
11006 
11007 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FREEZE_MASK (0x1U)
11008 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FREEZE_SHIFT (0U)
11009 /*! GPIO_SD1_FREEZE - Compensation code freeze */
11010 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FREEZE_MASK)
11011 
11012 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPTQ_MASK (0x2U)
11013 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPTQ_SHIFT (1U)
11014 /*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
11015 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPTQ_MASK)
11016 
11017 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPEN_MASK (0x4U)
11018 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPEN_SHIFT (2U)
11019 /*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
11020 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPEN_MASK)
11021 
11022 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
11023 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
11024 /*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze enable */
11025 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_EN_MASK)
11026 
11027 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCP_MASK (0xF0U)
11028 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCP_SHIFT (4U)
11029 /*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core */
11030 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCP_MASK)
11031 
11032 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCN_MASK (0xF00U)
11033 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCN_SHIFT (8U)
11034 /*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core */
11035 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_RASRCN_MASK)
11036 
11037 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
11038 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
11039 /*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection */
11040 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SELECT_NASRC_MASK)
11041 
11042 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
11043 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
11044 /*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable */
11045 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_REFGEN_SLEEP_MASK)
11046 
11047 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
11048 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
11049 /*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable */
11050 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_SUPLYDET_LATCH_MASK)
11051 
11052 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_MASK (0x8000U)
11053 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_SHIFT (15U)
11054 /*! GPIO_SD1_FASTFRZ - Compensation code fast-freeze */
11055 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_FASTFRZ_MASK)
11056 
11057 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPOK_MASK (0x100000U)
11058 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPOK_SHIFT (20U)
11059 /*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag */
11060 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_COMPOK_MASK)
11061 
11062 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_NASRC_MASK (0x1E00000U)
11063 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_NASRC_SHIFT (21U)
11064 /*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes */
11065 #define BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B1_IO_CTRL_GPIO_SD1_NASRC_MASK)
11066 /*! @} */
11067 
11068 /*! @name SD_B2_IO_CTRL - GPIO_SD_B2 bank IO control */
11069 /*! @{ */
11070 
11071 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FREEZE_MASK (0x1U)
11072 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FREEZE_SHIFT (0U)
11073 /*! GPIO_SD2_FREEZE - Compensation code freeze */
11074 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FREEZE_MASK)
11075 
11076 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPTQ_MASK (0x2U)
11077 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPTQ_SHIFT (1U)
11078 /*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
11079 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPTQ_MASK)
11080 
11081 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPEN_MASK (0x4U)
11082 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPEN_SHIFT (2U)
11083 /*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
11084 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPEN_MASK)
11085 
11086 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
11087 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
11088 /*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze enable */
11089 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_EN_MASK)
11090 
11091 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCP_MASK (0xF0U)
11092 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCP_SHIFT (4U)
11093 /*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core */
11094 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCP_MASK)
11095 
11096 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCN_MASK (0xF00U)
11097 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCN_SHIFT (8U)
11098 /*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core */
11099 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_RASRCN_MASK)
11100 
11101 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
11102 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
11103 /*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection */
11104 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SELECT_NASRC_MASK)
11105 
11106 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
11107 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
11108 /*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable */
11109 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_REFGEN_SLEEP_MASK)
11110 
11111 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
11112 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
11113 /*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable */
11114 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_SUPLYDET_LATCH_MASK)
11115 
11116 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_MASK (0x8000U)
11117 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_SHIFT (15U)
11118 /*! GPIO_SD2_FASTFRZ - Compensation code fast-freeze */
11119 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_FASTFRZ_MASK)
11120 
11121 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPOK_MASK (0x100000U)
11122 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPOK_SHIFT (20U)
11123 /*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag */
11124 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_COMPOK_MASK)
11125 
11126 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_NASRC_MASK (0x1E00000U)
11127 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_NASRC_SHIFT (21U)
11128 /*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes */
11129 #define BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_SD_B2_IO_CTRL_GPIO_SD2_NASRC_MASK)
11130 /*! @} */
11131 
11132 /*! @name GPIO_B1_IO_CTRL - GPIO_B1 bank IO control */
11133 /*! @{ */
11134 
11135 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FREEZE_MASK (0x1U)
11136 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FREEZE_SHIFT (0U)
11137 /*! GPIO_B1_FREEZE - Compensation code freeze */
11138 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FREEZE_MASK)
11139 
11140 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPTQ_MASK (0x2U)
11141 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPTQ_SHIFT (1U)
11142 /*! GPIO_B1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
11143 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPTQ_MASK)
11144 
11145 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPEN_MASK (0x4U)
11146 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPEN_SHIFT (2U)
11147 /*! GPIO_B1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
11148 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPEN_MASK)
11149 
11150 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_EN_MASK (0x8U)
11151 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_EN_SHIFT (3U)
11152 /*! GPIO_B1_FASTFRZ_EN - Compensation code fast freeze enable */
11153 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_EN_MASK)
11154 
11155 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCP_MASK (0xF0U)
11156 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCP_SHIFT (4U)
11157 /*! GPIO_B1_RASRCP - GPIO_B1 IO bank's 4-bit PMOS compensation codes from core */
11158 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCP_MASK)
11159 
11160 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCN_MASK (0xF00U)
11161 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCN_SHIFT (8U)
11162 /*! GPIO_B1_RASRCN - GPIO_B1 IO bank's 4-bit NMOS compensation codes from core */
11163 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_RASRCN_MASK)
11164 
11165 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SELECT_NASRC_MASK (0x1000U)
11166 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SELECT_NASRC_SHIFT (12U)
11167 /*! GPIO_B1_SELECT_NASRC - GPIO_B1_NASRC selection
11168  *  0b0..Show the 4-bit PMOS compensation codes in GPIO_B1_NASRC field
11169  *  0b1..Show the 4-bit NMOS compensation codes in GPIO_B1_NASRC field
11170  */
11171 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SELECT_NASRC_MASK)
11172 
11173 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_REFGEN_SLEEP_MASK (0x2000U)
11174 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_REFGEN_SLEEP_SHIFT (13U)
11175 /*! GPIO_B1_REFGEN_SLEEP - GPIO_B1 IO bank reference voltage generator cell sleep enable */
11176 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_REFGEN_SLEEP_MASK)
11177 
11178 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SUPLYDET_LATCH_MASK (0x4000U)
11179 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SUPLYDET_LATCH_SHIFT (14U)
11180 /*! GPIO_B1_SUPLYDET_LATCH - GPIO_B1 IO bank power supply mode latch enable */
11181 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_SUPLYDET_LATCH_MASK)
11182 
11183 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_MASK (0x8000U)
11184 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_SHIFT (15U)
11185 /*! GPIO_B1_FASTFRZ - Compensation code fast-freeze */
11186 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_FASTFRZ_MASK)
11187 
11188 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPOK_MASK (0x100000U)
11189 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPOK_SHIFT (20U)
11190 /*! GPIO_B1_COMPOK - GPIO_B1 IO bank compensation OK flag */
11191 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_COMPOK_MASK)
11192 
11193 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_NASRC_MASK (0x1E00000U)
11194 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_NASRC_SHIFT (21U)
11195 /*! GPIO_B1_NASRC - GPIO_B1 IO bank compensation codes */
11196 #define BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B1_IO_CTRL_GPIO_B1_NASRC_MASK)
11197 /*! @} */
11198 
11199 /*! @name GPIO_B2_IO_CTRL - GPIO_B2 bank IO control */
11200 /*! @{ */
11201 
11202 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FREEZE_MASK (0x1U)
11203 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FREEZE_SHIFT (0U)
11204 /*! GPIO_B2_FREEZE - Compensation code freeze */
11205 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FREEZE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FREEZE_MASK)
11206 
11207 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPTQ_MASK (0x2U)
11208 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPTQ_SHIFT (1U)
11209 /*! GPIO_B2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
11210 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPTQ_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPTQ_MASK)
11211 
11212 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPEN_MASK (0x4U)
11213 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPEN_SHIFT (2U)
11214 /*! GPIO_B2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
11215 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPEN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPEN_MASK)
11216 
11217 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_EN_MASK (0x8U)
11218 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_EN_SHIFT (3U)
11219 /*! GPIO_B2_FASTFRZ_EN - Compensation code fast freeze enable */
11220 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_EN_MASK)
11221 
11222 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCP_MASK (0xF0U)
11223 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCP_SHIFT (4U)
11224 /*! GPIO_B2_RASRCP - GPIO_B2 IO bank's 4-bit PMOS compensation codes from core */
11225 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCP_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCP_MASK)
11226 
11227 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCN_MASK (0xF00U)
11228 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCN_SHIFT (8U)
11229 /*! GPIO_B2_RASRCN - GPIO_B2 IO bank's 4-bit NMOS compensation codes from core */
11230 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCN_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_RASRCN_MASK)
11231 
11232 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SELECT_NASRC_MASK (0x1000U)
11233 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SELECT_NASRC_SHIFT (12U)
11234 /*! GPIO_B2_SELECT_NASRC - GPIO_B2_NASRC selection */
11235 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SELECT_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SELECT_NASRC_MASK)
11236 
11237 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_REFGEN_SLEEP_MASK (0x2000U)
11238 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_REFGEN_SLEEP_SHIFT (13U)
11239 /*! GPIO_B2_REFGEN_SLEEP - GPIO_B2 IO bank reference voltage generator cell sleep enable */
11240 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_REFGEN_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_REFGEN_SLEEP_MASK)
11241 
11242 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SUPLYDET_LATCH_MASK (0x4000U)
11243 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SUPLYDET_LATCH_SHIFT (14U)
11244 /*! GPIO_B2_SUPLYDET_LATCH - GPIO_B2 IO bank power supply mode latch enable */
11245 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SUPLYDET_LATCH_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_SUPLYDET_LATCH_MASK)
11246 
11247 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_MASK (0x8000U)
11248 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_SHIFT (15U)
11249 /*! GPIO_B2_FASTFRZ - Compensation code fast-freeze */
11250 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_FASTFRZ_MASK)
11251 
11252 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPOK_MASK (0x100000U)
11253 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPOK_SHIFT (20U)
11254 /*! GPIO_B2_COMPOK - GPIO_B2 IO bank compensation OK flag */
11255 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPOK_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_COMPOK_MASK)
11256 
11257 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_NASRC_MASK (0x1E00000U)
11258 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_NASRC_SHIFT (21U)
11259 /*! GPIO_B2_NASRC - GPIO_B2 IO bank compensation codes */
11260 #define BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_NASRC_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPIO_B2_IO_CTRL_GPIO_B2_NASRC_MASK)
11261 /*! @} */
11262 
11263 /*! @name MISC_IO_CTRL - Miscellaneous control register of IO */
11264 /*! @{ */
11265 
11266 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_MASK (0x1U)
11267 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_SHIFT (0U)
11268 /*! I3C_ON_CHIP_STRONG_PULL_DIS - Disable I3C on-chip strong pull for I3C2
11269  *  0b0..On-chip strong pull is enabled
11270  *  0b1..On-chip strong pull is disabled
11271  */
11272 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_I3C_ON_CHIP_STRONG_PULL_DIS_MASK)
11273 
11274 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_HIGH_RANGE_MASK (0x10U)
11275 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_HIGH_RANGE_SHIFT (4U)
11276 /*! GPIO_AD_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */
11277 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_HIGH_RANGE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_HIGH_RANGE_MASK)
11278 
11279 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_LOW_RANGE_MASK (0x20U)
11280 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_LOW_RANGE_SHIFT (5U)
11281 /*! GPIO_AD_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */
11282 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_LOW_RANGE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_GPIO_AD_LOW_RANGE_MASK)
11283 
11284 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
11285 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
11286 /*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable */
11287 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC1_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC1_SLEEP_MASK)
11288 
11289 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
11290 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
11291 /*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable */
11292 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC2_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_EMC2_SLEEP_MASK)
11293 
11294 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
11295 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD1_SLEEP_SHIFT (12U)
11296 /*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable */
11297 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD1_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD1_SLEEP_MASK)
11298 
11299 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
11300 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD2_SLEEP_SHIFT (13U)
11301 /*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable */
11302 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD2_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_SD2_SLEEP_MASK)
11303 
11304 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B1_SLEEP_MASK (0x4000U)
11305 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B1_SLEEP_SHIFT (14U)
11306 /*! SUPLYDET_GPIO_B1_SLEEP - GPIO_GPIO_B1 IO bank supply voltage detector sleep mode enable */
11307 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B1_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B1_SLEEP_MASK)
11308 
11309 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B2_SLEEP_MASK (0x8000U)
11310 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B2_SLEEP_SHIFT (15U)
11311 /*! SUPLYDET_GPIO_B2_SLEEP - GPIO_GPIO_B1 IO bank supply voltage detector sleep mode enable */
11312 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B2_SLEEP_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_SUPLYDET_GPIO_B2_SLEEP_MASK)
11313 
11314 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_MASK (0x10000U)
11315 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_SHIFT (16U)
11316 /*! ECAT_LINK_ACT0_POL - ECAT_LINK_ACT[0] polarity control */
11317 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT0_POL_MASK)
11318 
11319 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_MASK (0x20000U)
11320 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_SHIFT (17U)
11321 /*! ECAT_LINK_ACT1_POL - ECAT_LINK_ACT[1] polarity control */
11322 #define BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_SHIFT)) & BLK_CTRL_WAKEUPMIX_MISC_IO_CTRL_ECAT_LINK_ACT1_POL_MASK)
11323 /*! @} */
11324 
11325 
11326 /*!
11327  * @}
11328  */ /* end of group BLK_CTRL_WAKEUPMIX_Register_Masks */
11329 
11330 
11331 /* BLK_CTRL_WAKEUPMIX - Peripheral instance base addresses */
11332 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
11333   /** Peripheral BLK_CTRL_WAKEUPMIX base address */
11334   #define BLK_CTRL_WAKEUPMIX_BASE                  (0x52420000u)
11335   /** Peripheral BLK_CTRL_WAKEUPMIX base address */
11336   #define BLK_CTRL_WAKEUPMIX_BASE_NS               (0x42420000u)
11337   /** Peripheral BLK_CTRL_WAKEUPMIX base pointer */
11338   #define BLK_CTRL_WAKEUPMIX                       ((BLK_CTRL_WAKEUPMIX_Type *)BLK_CTRL_WAKEUPMIX_BASE)
11339   /** Peripheral BLK_CTRL_WAKEUPMIX base pointer */
11340   #define BLK_CTRL_WAKEUPMIX_NS                    ((BLK_CTRL_WAKEUPMIX_Type *)BLK_CTRL_WAKEUPMIX_BASE_NS)
11341   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */
11342   #define BLK_CTRL_WAKEUPMIX_BASE_ADDRS            { BLK_CTRL_WAKEUPMIX_BASE }
11343   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */
11344   #define BLK_CTRL_WAKEUPMIX_BASE_PTRS             { BLK_CTRL_WAKEUPMIX }
11345   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */
11346   #define BLK_CTRL_WAKEUPMIX_BASE_ADDRS_NS         { BLK_CTRL_WAKEUPMIX_BASE_NS }
11347   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */
11348   #define BLK_CTRL_WAKEUPMIX_BASE_PTRS_NS          { BLK_CTRL_WAKEUPMIX_NS }
11349 #else
11350   /** Peripheral BLK_CTRL_WAKEUPMIX base address */
11351   #define BLK_CTRL_WAKEUPMIX_BASE                  (0x42420000u)
11352   /** Peripheral BLK_CTRL_WAKEUPMIX base pointer */
11353   #define BLK_CTRL_WAKEUPMIX                       ((BLK_CTRL_WAKEUPMIX_Type *)BLK_CTRL_WAKEUPMIX_BASE)
11354   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */
11355   #define BLK_CTRL_WAKEUPMIX_BASE_ADDRS            { BLK_CTRL_WAKEUPMIX_BASE }
11356   /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */
11357   #define BLK_CTRL_WAKEUPMIX_BASE_PTRS             { BLK_CTRL_WAKEUPMIX }
11358 #endif
11359 
11360 /*!
11361  * @}
11362  */ /* end of group BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer */
11363 
11364 
11365 /* ----------------------------------------------------------------------------
11366    -- CACHE_ECC_MCM Peripheral Access Layer
11367    ---------------------------------------------------------------------------- */
11368 
11369 /*!
11370  * @addtogroup CACHE_ECC_MCM_Peripheral_Access_Layer CACHE_ECC_MCM Peripheral Access Layer
11371  * @{
11372  */
11373 
11374 /** CACHE_ECC_MCM - Register Layout Typedef */
11375 typedef struct {
11376   __IO uint32_t CACHE_ECCR;                        /**< CACHE ECC Control, offset: 0x0 */
11377        uint8_t RESERVED_0[28];
11378   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x20 */
11379   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable, offset: 0x24 */
11380   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable, offset: 0x28 */
11381        uint8_t RESERVED_1[48];
11382   __I  uint32_t CODE_CACHE_ECC_SINGLE_ERROR_INFO;  /**< Code Cache Single-Bit ECC Error Information, offset: 0x5C */
11383   __I  uint32_t CODE_CACHE_ECC_SINGLE_ERROR_ADDR;  /**< Code Cache Single-Bit ECC Error Address, offset: 0x60 */
11384        uint8_t RESERVED_2[4];
11385   __I  uint32_t CODE_CACHE_ECC_MULTI_ERROR_INFO;   /**< Code Cache Multibit ECC Error Information, offset: 0x68 */
11386        uint8_t RESERVED_3[8];
11387   __I  uint32_t SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO; /**< System Cache Single-Bit ECC Error Information, offset: 0x74 */
11388   __I  uint32_t SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR; /**< System Cache Single-Bit ECC Error Address, offset: 0x78 */
11389        uint8_t RESERVED_4[4];
11390   __I  uint32_t SYSTEM_CACHE_ECC_MULTI_ERROR_INFO; /**< System Cache Multibit ECC Error Information, offset: 0x80 */
11391   __I  uint32_t SYSTEM_CACHE_ECC_MULTI_ERROR_DATA; /**< System Cache Multibit ECC Error Data, offset: 0x84 */
11392        uint8_t RESERVED_5[4];
11393   __IO uint32_t CODE_CACHE_TAG0_ECC_ERROR_INJEC;   /**< Code Cache TAG0 ECC Error Injection, offset: 0x8C */
11394   __IO uint32_t CODE_CACHE_TAG1_ECC_ERROR_INJEC;   /**< Code Cache TAG1 ECC Error Injection, offset: 0x90 */
11395   __IO uint32_t CODE_CACHE_DATA0_ECC_ERROR_INJEC;  /**< Code Cache DATA0 ECC Error Injection, offset: 0x94 */
11396   __IO uint32_t CODE_CACHE_DATA1_ECC_ERROR_INJEC;  /**< Code Cache DATA1 ECC Error Injection, offset: 0x98 */
11397   __IO uint32_t SYTEM_CACHE_TAG0_ECC_ERROR_INJEC;  /**< System Cache TAG0 ECC Error Injection, offset: 0x9C */
11398   __IO uint32_t SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC; /**< System Cache TAG1 ECC Error Injection, offset: 0xA0 */
11399   __IO uint32_t SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC; /**< System Cache DATA0 ECC Error Injection, offset: 0xA4 */
11400   __IO uint32_t STSTEM_CACHE_DATA1_ECC_ERROR_INJEC; /**< System Cache DATA1 ECC Error Injection, offset: 0xA8 */
11401 } CACHE_ECC_MCM_Type;
11402 
11403 /* ----------------------------------------------------------------------------
11404    -- CACHE_ECC_MCM Register Masks
11405    ---------------------------------------------------------------------------- */
11406 
11407 /*!
11408  * @addtogroup CACHE_ECC_MCM_Register_Masks CACHE_ECC_MCM Register Masks
11409  * @{
11410  */
11411 
11412 /*! @name CACHE_ECCR - CACHE ECC Control */
11413 /*! @{ */
11414 
11415 #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK   (0x1U)
11416 #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT  (0U)
11417 /*! WECC_DIS - Disable CACHE ECC Write Generation
11418  *  0b1..Disable
11419  *  0b0..Enable
11420  */
11421 #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS(x)     (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK)
11422 
11423 #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK   (0x2U)
11424 #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT  (1U)
11425 /*! RECC_DIS - Disable Cache ECC Read Check
11426  *  0b1..Disable
11427  *  0b0..Enable
11428  */
11429 #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS(x)     (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK)
11430 /*! @} */
11431 
11432 /*! @name INT_STATUS - Interrupt Status */
11433 /*! @{ */
11434 
11435 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK (0x100U)
11436 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT (8U)
11437 /*! CODE_CACHE_ECC_ERRM_INT - Code Cache Access Multibit ECC Error Interrupt Status
11438  *  0b0..No error
11439  *  0b1..Error
11440  *  0b0..No effect
11441  *  0b1..Clear the flag
11442  */
11443 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK)
11444 
11445 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK (0x200U)
11446 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT (9U)
11447 /*! CODE_CACHE_ECC_ERRS_INT - Code Cache Access Single-Bit ECC Error Interrupt Status
11448  *  0b0..No error
11449  *  0b1..Error
11450  *  0b0..No effect
11451  *  0b1..Clear the flag
11452  */
11453 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK)
11454 
11455 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK (0x400U)
11456 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT (10U)
11457 /*! CODE_CACHE_ECC_ERRM_OVER_INT - Code Cache Access Multiple Multibit ECC Error Interrupt Status
11458  *  0b0..Not more than one error
11459  *  0b1..Multiple errors
11460  *  0b0..No effect
11461  *  0b1..Clear the flag
11462  */
11463 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK)
11464 
11465 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK (0x800U)
11466 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT (11U)
11467 /*! CODE_CACHE_ECC_ERRS_OVER_INT - Code Cache Access Multiple Single-Bit ECC Error Interrupt Status
11468  *  0b0..Not more than one error
11469  *  0b1..Multiple errors
11470  *  0b0..No effect
11471  *  0b1..Clear the flag
11472  */
11473 #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK)
11474 
11475 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK (0x1000U)
11476 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT (12U)
11477 /*! SYSTEM_CACHE_ECC_ERRM_INT - System Cache Access Multibit ECC Error Interrupt Status
11478  *  0b0..No error
11479  *  0b1..Error
11480  *  0b0..No effect
11481  *  0b1..Clear the flag
11482  */
11483 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK)
11484 
11485 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK (0x2000U)
11486 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT (13U)
11487 /*! SYSTEM_CACHE_ECC_ERRS_INT - System Cache Access Single-Bit ECC Error Interrupt Status
11488  *  0b0..No error
11489  *  0b1..Error
11490  *  0b0..No effect
11491  *  0b1..Clear the flag
11492  */
11493 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK)
11494 
11495 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK (0x4000U)
11496 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT (14U)
11497 /*! SYSTEM_CACHE_ECC_ERRM_OVER_INT - System Cache Access Multiple Multibit ECC Error Interrupt Status
11498  *  0b0..Not more than one error
11499  *  0b1..Multiple errors
11500  *  0b0..No effect
11501  *  0b1..Clear the flag
11502  */
11503 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK)
11504 
11505 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK (0x8000U)
11506 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT (15U)
11507 /*! SYSTEM_CACHE_ECC_ERRS_OVER_INT - System Cache Access Multiple Single-Bit ECC Error Interrupt Status
11508  *  0b0..Not more than one error
11509  *  0b1..Multiple errors
11510  *  0b0..No effect
11511  *  0b1..Clear the flag
11512  */
11513 #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK)
11514 /*! @} */
11515 
11516 /*! @name INT_STAT_EN - Interrupt Status Enable */
11517 /*! @{ */
11518 
11519 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_MASK (0x100U)
11520 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_SHIFT (8U)
11521 /*! CODE_CACHE_ERRM_INT_EN - Code Cache Access Multibit ECC Error Interrupt Status Enable
11522  *  0b0..Mask
11523  *  0b1..Enable
11524  */
11525 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_MASK)
11526 
11527 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_MASK (0x200U)
11528 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_SHIFT (9U)
11529 /*! CODE_CACHE_ERRS_INT_EN - Code Cache Access Single-Bit ECC Error Interrupt Status Enable
11530  *  0b0..Mask
11531  *  0b1..Enable
11532  */
11533 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_MASK)
11534 
11535 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_MASK (0x400U)
11536 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_SHIFT (10U)
11537 /*! CODE_CACHE_ERRM_OVER_INT_EN - Code Cache Access Multiple Multibit ECC Error Interrupt Status Enable
11538  *  0b0..Mask
11539  *  0b1..Enable
11540  */
11541 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_MASK)
11542 
11543 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_MASK (0x800U)
11544 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_SHIFT (11U)
11545 /*! CODE_CACHE_ERRS_OVER_INT_EN - Code Cache Access Multiple Single-Bit ECC Error Interrupt Status Enable
11546  *  0b0..Mask
11547  *  0b1..Enable
11548  */
11549 #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_MASK)
11550 
11551 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_MASK (0x1000U)
11552 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_SHIFT (12U)
11553 /*! SYSTEM_CACHE_ECC_ERRM_INT_EN - System Cache Access Multibit ECC Error Interrupt Status Enable
11554  *  0b0..Mask
11555  *  0b1..Enable
11556  */
11557 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_MASK)
11558 
11559 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_MASK (0x2000U)
11560 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_SHIFT (13U)
11561 /*! SYSTEM_CACHE_ECC_ERRS_INT_EN - System Cache Access Single-Bit ECC Error Interrupt Status Enable
11562  *  0b0..Mask
11563  *  0b1..Enable
11564  */
11565 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_MASK)
11566 
11567 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_MASK (0x4000U)
11568 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_SHIFT (14U)
11569 /*! SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN - System Cache Access Multiple Multibit ECC Error Interrupt Status Enable
11570  *  0b0..Mask
11571  *  0b1..Enable
11572  */
11573 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_MASK)
11574 
11575 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_MASK (0x8000U)
11576 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_SHIFT (15U)
11577 /*! SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN - System Cache Access Multiple Single-Bit ECC Error Interrupt Status Enable
11578  *  0b0..Mask
11579  *  0b1..Enable
11580  */
11581 #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_MASK)
11582 /*! @} */
11583 
11584 /*! @name INT_SIG_EN - Interrupt Enable */
11585 /*! @{ */
11586 
11587 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_MASK (0x100U)
11588 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_SHIFT (8U)
11589 /*! CODE_CACHE_ERRM_INT_SIG_EN - Code Cache Access Multibit ECC Error Interrupt Signal Enable
11590  *  0b0..Mask
11591  *  0b1..Enable
11592  */
11593 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_MASK)
11594 
11595 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_MASK (0x200U)
11596 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_SHIFT (9U)
11597 /*! CODE_CACHE_ERRS_INT_SIG_EN - Code Cache Access Single-Bit ECC Error Interrupt Signal Enable
11598  *  0b0..Mask
11599  *  0b1..Enable
11600  */
11601 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_MASK)
11602 
11603 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_MASK (0x400U)
11604 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT (10U)
11605 /*! CODE_CACHE_ERRM_OVER_INT_SIG_EN - Code Cache Access Multiple Multibit ECC Error Interrupt Signal Enable
11606  *  0b0..Mask
11607  *  0b1..Enable
11608  */
11609 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_MASK)
11610 
11611 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_MASK (0x800U)
11612 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT (11U)
11613 /*! CODE_CACHE_ERRS_OVER_INT_SIG_EN - Code Cache Access Multiple Single-Bit ECC Error Interrupt Signal Enable
11614  *  0b0..Mask
11615  *  0b1..Enable
11616  */
11617 #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_MASK)
11618 
11619 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_MASK (0x1000U)
11620 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_SHIFT (12U)
11621 /*! SYSTEM_CACHE_ERRM_INT_SIG_EN - System Cache Access Multibit ECC Error Interrupt Signal Enable
11622  *  0b0..Mask
11623  *  0b1..Enable
11624  */
11625 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_MASK)
11626 
11627 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_MASK (0x2000U)
11628 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_SHIFT (13U)
11629 /*! SYSTEM_CACHE_ERRS_INT_SIG_EN - System Cache Access Single-Bit ECC Error Interrupt Signal Enable
11630  *  0b0..Mask
11631  *  0b1..Enable
11632  */
11633 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_MASK)
11634 
11635 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_MASK (0x4000U)
11636 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT (14U)
11637 /*! SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN - System Cache Access Multiple Multibit ECC Error Interrupt Signal Enable
11638  *  0b0..Masked
11639  *  0b1..Enabled
11640  */
11641 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_MASK)
11642 
11643 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_MASK (0x8000U)
11644 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT (15U)
11645 /*! SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN - System Cache Access Multiple Single-Bit ECC Error Interrupt Signal Enable
11646  *  0b0..Mask
11647  *  0b1..Enable
11648  */
11649 #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_MASK)
11650 /*! @} */
11651 
11652 /*! @name CODE_CACHE_ECC_SINGLE_ERROR_INFO - Code Cache Single-Bit ECC Error Information */
11653 /*! @{ */
11654 
11655 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_MASK (0x1U)
11656 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_SHIFT (0U)
11657 /*! CODE_CACHE_ECCS_TAG - Code Cache Single-Bit ECC Error
11658  *  0b1..Tag
11659  *  0b0..Data
11660  */
11661 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_MASK)
11662 
11663 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_MASK (0x2U)
11664 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_SHIFT (1U)
11665 /*! CODE_CACHE_ECCS_CMD - Code Cache Single-Bit ECC Error on Cache Command
11666  *  0b0..No error
11667  *  0b1..Error
11668  */
11669 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_MASK)
11670 
11671 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_MASK (0xF0U)
11672 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_SHIFT (4U)
11673 /*! CODE_CACHE_ECCS_EFMST - Code Cache Single-Bit ECC Error Master Number */
11674 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_MASK)
11675 
11676 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_MASK (0x3F00U)
11677 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_SHIFT (8U)
11678 /*! CODE_CACHE_ECCS_EFPRT - Code Cache Single-Bit ECC Error Protection */
11679 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_MASK)
11680 
11681 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_MASK (0x7F0000U)
11682 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_SHIFT (16U)
11683 /*! CODE_CACHE_ECCS_EFSYN - Code Cache Single-Bit ECC Error Corresponding Syndrome */
11684 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_MASK)
11685 /*! @} */
11686 
11687 /*! @name CODE_CACHE_ECC_SINGLE_ERROR_ADDR - Code Cache Single-Bit ECC Error Address */
11688 /*! @{ */
11689 
11690 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
11691 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_SHIFT (0U)
11692 /*! CODE_CACHE_ECCS_ERRED_ADDR - Code Cache Single-Bit ECC Error Address */
11693 #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_MASK)
11694 /*! @} */
11695 
11696 /*! @name CODE_CACHE_ECC_MULTI_ERROR_INFO - Code Cache Multibit ECC Error Information */
11697 /*! @{ */
11698 
11699 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_MASK (0x1U)
11700 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_SHIFT (0U)
11701 /*! CODE_CACHE_ECCM_TAG - Code Cache Multibit ECC Error
11702  *  0b1..Tag
11703  *  0b0..Data
11704  */
11705 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_MASK)
11706 
11707 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_MASK (0x2U)
11708 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_SHIFT (1U)
11709 /*! CODE_CACHE_ECCM_CMD - Code Cache Multibit ECC Error on Code Cache Command
11710  *  0b0..No error
11711  *  0b1..Error
11712  */
11713 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_MASK)
11714 
11715 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_MASK (0xF0U)
11716 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_SHIFT (4U)
11717 /*! CODE_CACHE_ECCM_EFMST - Code Cache Multibit ECC Error Master Number */
11718 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_MASK)
11719 
11720 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_MASK (0x3F00U)
11721 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_SHIFT (8U)
11722 /*! CODE_CACHE_ECCM_EFPRT - Code Cache Multibit ECC Error Protection */
11723 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_MASK)
11724 
11725 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_MASK (0x7F0000U)
11726 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_SHIFT (16U)
11727 /*! CODE_CACHE_ECCM_EFSYN - Code Cache Multibit ECC Error Corresponding Syndrome */
11728 #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_MASK)
11729 /*! @} */
11730 
11731 /*! @name SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO - System Cache Single-Bit ECC Error Information */
11732 /*! @{ */
11733 
11734 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_MASK (0x1U)
11735 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_SHIFT (0U)
11736 /*! SYSTEM_CACHE_ECCS_TAG - System Cache Single-Bit ECC Error
11737  *  0b1..Tag
11738  *  0b0..Data
11739  */
11740 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_MASK)
11741 
11742 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_MASK (0x2U)
11743 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_SHIFT (1U)
11744 /*! SYSTEM_CACHE_ECCS_CMD - System Cache Single-Bit ECC Error on Cache Command
11745  *  0b0..No error
11746  *  0b1..Error
11747  */
11748 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_MASK)
11749 
11750 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_MASK (0xF0U)
11751 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_SHIFT (4U)
11752 /*! SYSTEM_CACHE_ECCS_EFMST - System Cache Single-Bit ECC Error Master Number */
11753 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_MASK)
11754 
11755 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_MASK (0x3F00U)
11756 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_SHIFT (8U)
11757 /*! SYSTEM_CACHE_ECCS_EFPRT - System Cache Single-Bit ECC Error Protection */
11758 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_MASK)
11759 
11760 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_MASK (0x7F0000U)
11761 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_SHIFT (16U)
11762 /*! SYSTEM_CACHE_ECCS_EFSYN - System Cache Single-Bit ECC Error Corresponding Syndrome */
11763 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_MASK)
11764 /*! @} */
11765 
11766 /*! @name SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR - System Cache Single-Bit ECC Error Address */
11767 /*! @{ */
11768 
11769 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
11770 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_SHIFT (0U)
11771 /*! SYSTEM_CACHE_ECCS_ERRED_ADDR - System Cache Single-Bit ECC Error Address */
11772 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_MASK)
11773 /*! @} */
11774 
11775 /*! @name SYSTEM_CACHE_ECC_MULTI_ERROR_INFO - System Cache Multibit ECC Error Information */
11776 /*! @{ */
11777 
11778 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_MASK (0x1U)
11779 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_SHIFT (0U)
11780 /*! SYSTEM_CACHE_ECCM_TAG - System Cache Multibit ECC Error
11781  *  0b1..Tag
11782  *  0b0..Data
11783  */
11784 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_MASK)
11785 
11786 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_MASK (0x2U)
11787 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_SHIFT (1U)
11788 /*! SYSTEM_CACHE_ECCM_CMD - System Cache Multibit ECC Error on System Cache Command
11789  *  0b0..No error
11790  *  0b1..Error
11791  */
11792 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_MASK)
11793 
11794 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_MASK (0xF0U)
11795 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_SHIFT (4U)
11796 /*! SYSTEM_CACHE_ECCM_EFMST - System Cache Multibit ECC Error Master Number */
11797 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_MASK)
11798 
11799 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_MASK (0x3F00U)
11800 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_SHIFT (8U)
11801 /*! SYSTEM_CACHE_ECCM_EFPRT - System Cache Multibit ECC Error Protection */
11802 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_MASK)
11803 
11804 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_MASK (0x7F0000U)
11805 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_SHIFT (16U)
11806 /*! SYSTEM_CACHE_ECCM_EFSYN - System Cache Multibit ECC Error Corresponding Syndrome */
11807 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_MASK)
11808 /*! @} */
11809 
11810 /*! @name SYSTEM_CACHE_ECC_MULTI_ERROR_DATA - System Cache Multibit ECC Error Data */
11811 /*! @{ */
11812 
11813 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
11814 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_SHIFT (0U)
11815 /*! SYSTEM_CACHE_ECCM_ERRED_DATA - System Cache Multibit ECC Error Data */
11816 #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_MASK)
11817 /*! @} */
11818 
11819 /*! @name CODE_CACHE_TAG0_ECC_ERROR_INJEC - Code Cache TAG0 ECC Error Injection */
11820 /*! @{ */
11821 
11822 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_MASK (0x7FU)
11823 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_SHIFT (0U)
11824 /*! CODE_CACHE_TAG0_ERR1BIT - Position of First Bit to Inject ECC Error */
11825 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_MASK)
11826 
11827 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_MASK (0x7F00U)
11828 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_SHIFT (8U)
11829 /*! CODE_CACHE_TAG0_ERR2BIT - Position of Second Bit to Inject ECC Error */
11830 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_MASK)
11831 
11832 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_MASK (0x10000U)
11833 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_SHIFT (16U)
11834 /*! CODE_CACHE_TAG0_FR11BI - Force One 1-Bit Data Inversion on Code Cache TAG0 Write Access
11835  *  0b0..Disable injection
11836  *  0b1..Enable injection
11837  */
11838 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_MASK)
11839 
11840 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_MASK (0x20000U)
11841 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_SHIFT (17U)
11842 /*! CODE_CACHE_TAG0_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache TAG0 Write Access
11843  *  0b0..Disable injection
11844  *  0b1..Enable injection
11845  */
11846 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_MASK)
11847 
11848 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_MASK (0x40000U)
11849 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_SHIFT (18U)
11850 /*! CODE_CACHE_TAG0_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache TAG0 Write Access
11851  *  0b0..Disable injection
11852  *  0b1..Enable injection
11853  */
11854 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_MASK)
11855 
11856 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_MASK (0x80000U)
11857 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_SHIFT (19U)
11858 /*! CODE_CACHE_TAG0_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache TAG0 Write Access
11859  *  0b0..Disable injection
11860  *  0b1..Enable injection
11861  */
11862 #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_MASK)
11863 /*! @} */
11864 
11865 /*! @name CODE_CACHE_TAG1_ECC_ERROR_INJEC - Code Cache TAG1 ECC Error Injection */
11866 /*! @{ */
11867 
11868 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_MASK (0x7FU)
11869 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_SHIFT (0U)
11870 /*! CODE_CACHE_TAG1_ERR1BIT - Position of First Bit to Inject ECC Error */
11871 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_MASK)
11872 
11873 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_MASK (0x7F00U)
11874 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_SHIFT (8U)
11875 /*! CODE_CACHE_TAG1_ERR2BIT - Position of Second Bit to Inject ECC Error */
11876 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_MASK)
11877 
11878 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_MASK (0x10000U)
11879 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_SHIFT (16U)
11880 /*! CODE_CACHE_TAG1_FR11BI - Force One 1-Bit Data Inversion on Code Cache TAG1 Write Access
11881  *  0b0..Disable injection
11882  *  0b1..Enable injection
11883  */
11884 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_MASK)
11885 
11886 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_MASK (0x20000U)
11887 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_SHIFT (17U)
11888 /*! CODE_CACHE_TAG1_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache TAG1 Write Access
11889  *  0b0..Disable injection
11890  *  0b1..Enable injection
11891  */
11892 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_MASK)
11893 
11894 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_MASK (0x40000U)
11895 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_SHIFT (18U)
11896 /*! CODE_CACHE_TAG1_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache TAG1 Write Access
11897  *  0b0..Disable injection
11898  *  0b1..Enable injection
11899  */
11900 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_MASK)
11901 
11902 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_MASK (0x80000U)
11903 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_SHIFT (19U)
11904 /*! CODE_CACHE_TAG1_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache TAG1 Write Access
11905  *  0b0..Disable injection
11906  *  0b1..Enable injection
11907  */
11908 #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_MASK)
11909 /*! @} */
11910 
11911 /*! @name CODE_CACHE_DATA0_ECC_ERROR_INJEC - Code Cache DATA0 ECC Error Injection */
11912 /*! @{ */
11913 
11914 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_MASK (0x7FU)
11915 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_SHIFT (0U)
11916 /*! CODE_CACHE_DATA0_ERR1BIT - Position of First Bit to Inject ECC Error */
11917 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_MASK)
11918 
11919 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_MASK (0x7F00U)
11920 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_SHIFT (8U)
11921 /*! CODE_CACHE_DATA0_ERR2BIT - Position of Second Bit to Inject ECC Error */
11922 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_MASK)
11923 
11924 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_MASK (0x10000U)
11925 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_SHIFT (16U)
11926 /*! CODE_CACHE_DATA0_FR11BI - Force One 1-Bit Data Inversion on Code Cache DATA0 Write Access
11927  *  0b0..Disable injection
11928  *  0b1..Enable injection
11929  */
11930 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_MASK)
11931 
11932 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_MASK (0x20000U)
11933 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_SHIFT (17U)
11934 /*! CODE_CACHE_DATA0_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache DATA0 Write Access
11935  *  0b0..Disable injection
11936  *  0b1..Enable injection
11937  */
11938 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_MASK)
11939 
11940 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_MASK (0x40000U)
11941 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_SHIFT (18U)
11942 /*! CODE_CACHE_DATA0_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache DATA0 Write Access
11943  *  0b0..Disable injection
11944  *  0b1..Enable injection
11945  */
11946 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_MASK)
11947 
11948 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_MASK (0x80000U)
11949 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_SHIFT (19U)
11950 /*! CODE_CACHE_DATA0_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache DATA0 Write Access
11951  *  0b0..Disable injection
11952  *  0b1..Enable injection
11953  */
11954 #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_MASK)
11955 /*! @} */
11956 
11957 /*! @name CODE_CACHE_DATA1_ECC_ERROR_INJEC - Code Cache DATA1 ECC Error Injection */
11958 /*! @{ */
11959 
11960 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_MASK (0x7FU)
11961 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_SHIFT (0U)
11962 /*! CODE_CACHE_DATA1_ERR1BIT - Position of First Bit to Inject ECC Error */
11963 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_MASK)
11964 
11965 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_MASK (0x7F00U)
11966 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_SHIFT (8U)
11967 /*! CODE_CACHE_DATA1_ERR2BIT - Position of Second Bit to Inject ECC Error */
11968 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_MASK)
11969 
11970 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_MASK (0x10000U)
11971 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_SHIFT (16U)
11972 /*! CODE_CACHE_DATA1_FR11BI - Force One 1-Bit Data Inversion on Code Cache DATA1 Write Access
11973  *  0b0..Disable injection
11974  *  0b1..Enable injection
11975  */
11976 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_MASK)
11977 
11978 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_MASK (0x20000U)
11979 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_SHIFT (17U)
11980 /*! CODE_CACHE_DATA1_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache DATA1 Write Access
11981  *  0b0..Disable injection
11982  *  0b1..Enable injection
11983  */
11984 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_MASK)
11985 
11986 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_MASK (0x40000U)
11987 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_SHIFT (18U)
11988 /*! CODE_CACHE_DATA1_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache DATA1 Write Access
11989  *  0b0..Disable injection
11990  *  0b1..Enable injection
11991  */
11992 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_MASK)
11993 
11994 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_MASK (0x80000U)
11995 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_SHIFT (19U)
11996 /*! CODE_CACHE_DATA1_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache DATA1 Write Access
11997  *  0b0..Disable injection
11998  *  0b1..Enable injection
11999  */
12000 #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_MASK)
12001 /*! @} */
12002 
12003 /*! @name SYTEM_CACHE_TAG0_ECC_ERROR_INJEC - System Cache TAG0 ECC Error Injection */
12004 /*! @{ */
12005 
12006 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_MASK (0x7FU)
12007 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_SHIFT (0U)
12008 /*! SYSTEM_CACHE_TAG0_ERR1BIT - Position of First Bit to Inject ECC Error */
12009 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_MASK)
12010 
12011 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_MASK (0x7F00U)
12012 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_SHIFT (8U)
12013 /*! SYSTEM_CACHE_TAG0_ERR2BIT - Position of Second Bit to Inject ECC Error */
12014 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_MASK)
12015 
12016 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_MASK (0x10000U)
12017 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_SHIFT (16U)
12018 /*! SYSTEM_CACHE_TAG0_FR11BI - Force One 1-Bit Data Inversion on System Cache TAG0 Write Access
12019  *  0b0..Disable injection
12020  *  0b1..Enable injection
12021  */
12022 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_MASK)
12023 
12024 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_MASK (0x20000U)
12025 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_SHIFT (17U)
12026 /*! SYSTEM_CACHE_TAG0_FR1NCI - Force One Noncorrectable Data Inversion on System Cache TAG0 Write Access
12027  *  0b0..Disable injection
12028  *  0b1..Enable injection
12029  */
12030 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_MASK)
12031 
12032 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_MASK (0x40000U)
12033 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_SHIFT (18U)
12034 /*! SYSTEM_CACHE_TAG0_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache TAG0 Write Access
12035  *  0b0..Disable injection
12036  *  0b1..Enable injection
12037  */
12038 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_MASK)
12039 
12040 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_MASK (0x80000U)
12041 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_SHIFT (19U)
12042 /*! SYSTEM_CACHE_TAG0_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache TAG0 Write Access
12043  *  0b0..Disable injection
12044  *  0b1..Enable injection
12045  */
12046 #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_MASK)
12047 /*! @} */
12048 
12049 /*! @name SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC - System Cache TAG1 ECC Error Injection */
12050 /*! @{ */
12051 
12052 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_MASK (0x7FU)
12053 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_SHIFT (0U)
12054 /*! SYSTEM_CACHE_TAG1_ERR1BIT - Position of First Bit to Inject ECC Error */
12055 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_MASK)
12056 
12057 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_MASK (0x7F00U)
12058 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_SHIFT (8U)
12059 /*! SYSTEMCACHE_TAG1_ERR2BIT - Position of Second Bit to Inject ECC Error */
12060 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_MASK)
12061 
12062 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_MASK (0x10000U)
12063 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_SHIFT (16U)
12064 /*! SYSTEM_CACHE_TAG1_FR11BI - Force One 1-Bit Data Inversion on System Cache TAG1 Write Access
12065  *  0b0..Disable injection
12066  *  0b1..Enable injection
12067  */
12068 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_MASK)
12069 
12070 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_MASK (0x20000U)
12071 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_SHIFT (17U)
12072 /*! SYSTEM_CACHE_TAG1_FR1NCI - Force One Noncorrectable Data Inversion on System Cache TAG1 Write Access
12073  *  0b0..Disable injection
12074  *  0b1..Enable injection
12075  */
12076 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_MASK)
12077 
12078 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_MASK (0x40000U)
12079 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_SHIFT (18U)
12080 /*! SYSTEM_CACHE_TAG1_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache TAG1 Write Access
12081  *  0b0..Disable injection
12082  *  0b1..Enable injection
12083  */
12084 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_MASK)
12085 
12086 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_MASK (0x80000U)
12087 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_SHIFT (19U)
12088 /*! SYSTEM_CACHE_TAG1_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache TAG1 Write Access
12089  *  0b0..Disable injection
12090  *  0b1..Enable injection
12091  */
12092 #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_MASK)
12093 /*! @} */
12094 
12095 /*! @name SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC - System Cache DATA0 ECC Error Injection */
12096 /*! @{ */
12097 
12098 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_MASK (0x7FU)
12099 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_SHIFT (0U)
12100 /*! SYSTEM_CACHE_DATA0_ERR1BIT - Position of First Bit to Inject ECC Error */
12101 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_MASK)
12102 
12103 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_MASK (0x7F00U)
12104 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_SHIFT (8U)
12105 /*! SYSTEM_CACHE_DATA0_ERR2BIT - Position of Second Bit to Inject ECC Error */
12106 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_MASK)
12107 
12108 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_MASK (0x10000U)
12109 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_SHIFT (16U)
12110 /*! SYSTEM_CACHE_DATA0_FR11BI - Force One 1-Bit Data Inversion on System Cache DATA0 Write Access
12111  *  0b0..Disable injection
12112  *  0b1..Enable injection
12113  */
12114 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_MASK)
12115 
12116 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_MASK (0x20000U)
12117 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_SHIFT (17U)
12118 /*! SYSTEM_CACHE_DATA0_FR1NCI - Force One Noncorrectable Data Inversion on System Cache DATA0 Write Access
12119  *  0b0..Disable injection
12120  *  0b1..Enable injection
12121  */
12122 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_MASK)
12123 
12124 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_MASK (0x40000U)
12125 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_SHIFT (18U)
12126 /*! SYSTEM_CACHE_DATA0_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache DATA0 Write Access
12127  *  0b0..Disable injection
12128  *  0b1..Enable injection
12129  */
12130 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_MASK)
12131 
12132 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_MASK (0x80000U)
12133 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_SHIFT (19U)
12134 /*! SYSTEM_CACHE_DATA0_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache DATA0 Write Access
12135  *  0b0..Disable injection
12136  *  0b1..Enable injection
12137  */
12138 #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_MASK)
12139 /*! @} */
12140 
12141 /*! @name STSTEM_CACHE_DATA1_ECC_ERROR_INJEC - System Cache DATA1 ECC Error Injection */
12142 /*! @{ */
12143 
12144 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_MASK (0x7FU)
12145 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_SHIFT (0U)
12146 /*! SYSTEM_CACHE_DATA1_ERR1BIT - Position of First Bit to Inject ECC Error */
12147 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_MASK)
12148 
12149 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_MASK (0x7F00U)
12150 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_SHIFT (8U)
12151 /*! SYSTEM_CACHE_DATA1_ERR2BIT - Position of Second Bit to Inject ECC Error */
12152 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_MASK)
12153 
12154 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_MASK (0x10000U)
12155 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_SHIFT (16U)
12156 /*! SYSTEM_CACHE_DATA1_FR11BI - Force One 1-Bit Data Inversion on System Cache DATA1 Write Access
12157  *  0b0..Disable injection
12158  *  0b1..Enable injection
12159  */
12160 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_MASK)
12161 
12162 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_MASK (0x20000U)
12163 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_SHIFT (17U)
12164 /*! SYSTEM_CACHE_DATA1_FR1NCI - Force One Noncorrectable Data Inversion on System Cache DATA1 Write Access
12165  *  0b0..Disable injection
12166  *  0b1..Enable injection
12167  */
12168 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_MASK)
12169 
12170 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_MASK (0x40000U)
12171 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_SHIFT (18U)
12172 /*! SYSTEM_CACHE_DATA1_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache DATA1 Write Access
12173  *  0b0..Disable injection
12174  *  0b1..Enable injection
12175  */
12176 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_MASK)
12177 
12178 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_MASK (0x80000U)
12179 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_SHIFT (19U)
12180 /*! SYSTEM_CACHE_DATA1_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache DATA1 Write Access
12181  *  0b0..Disable injection
12182  *  0b1..Enable injection
12183  */
12184 #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_MASK)
12185 /*! @} */
12186 
12187 
12188 /*!
12189  * @}
12190  */ /* end of group CACHE_ECC_MCM_Register_Masks */
12191 
12192 
12193 /* CACHE_ECC_MCM - Peripheral instance base addresses */
12194 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
12195   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base address */
12196   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE (0x54401000u)
12197   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base address */
12198   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE_NS (0x44401000u)
12199   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base pointer */
12200   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM      ((CACHE_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE)
12201   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base pointer */
12202   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_NS   ((CACHE_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE_NS)
12203   /** Array initializer of CACHE_ECC_MCM peripheral base addresses */
12204   #define CACHE_ECC_MCM_BASE_ADDRS                 { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE }
12205   /** Array initializer of CACHE_ECC_MCM peripheral base pointers */
12206   #define CACHE_ECC_MCM_BASE_PTRS                  { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM }
12207   /** Array initializer of CACHE_ECC_MCM peripheral base addresses */
12208   #define CACHE_ECC_MCM_BASE_ADDRS_NS              { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE_NS }
12209   /** Array initializer of CACHE_ECC_MCM peripheral base pointers */
12210   #define CACHE_ECC_MCM_BASE_PTRS_NS               { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_NS }
12211 #else
12212   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base address */
12213   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE (0x44401000u)
12214   /** Peripheral CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM base pointer */
12215   #define CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM      ((CACHE_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE)
12216   /** Array initializer of CACHE_ECC_MCM peripheral base addresses */
12217   #define CACHE_ECC_MCM_BASE_ADDRS                 { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM_BASE }
12218   /** Array initializer of CACHE_ECC_MCM peripheral base pointers */
12219   #define CACHE_ECC_MCM_BASE_PTRS                  { CP_CM33_IMX9RTC__CM33_CACHE_ECC_MCM }
12220 #endif
12221 
12222 /*!
12223  * @}
12224  */ /* end of group CACHE_ECC_MCM_Peripheral_Access_Layer */
12225 
12226 
12227 /* ----------------------------------------------------------------------------
12228    -- CAN Peripheral Access Layer
12229    ---------------------------------------------------------------------------- */
12230 
12231 /*!
12232  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
12233  * @{
12234  */
12235 
12236 /** CAN - Register Layout Typedef */
12237 typedef struct {
12238   __IO uint32_t MCR;                               /**< Module Configuration, offset: 0x0 */
12239   __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x4 */
12240   __IO uint32_t TIMER;                             /**< Free-Running Timer, offset: 0x8 */
12241        uint8_t RESERVED_0[4];
12242   __IO uint32_t RXMGMASK;                          /**< RX Message Buffers Global Mask, offset: 0x10 */
12243   __IO uint32_t RX14MASK;                          /**< Receive 14 Mask, offset: 0x14 */
12244   __IO uint32_t RX15MASK;                          /**< Receive 15 Mask, offset: 0x18 */
12245   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
12246   __IO uint32_t ESR1;                              /**< Error and Status 1, offset: 0x20 */
12247   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2, offset: 0x24 */
12248   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1, offset: 0x28 */
12249   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2, offset: 0x2C */
12250   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1, offset: 0x30 */
12251   __IO uint32_t CTRL2;                             /**< Control 2, offset: 0x34 */
12252   __I  uint32_t ESR2;                              /**< Error and Status 2, offset: 0x38 */
12253        uint8_t RESERVED_1[8];
12254   __I  uint32_t CRCR;                              /**< Cyclic Redundancy Check, offset: 0x44 */
12255   __IO uint32_t RXFGMASK;                          /**< Legacy RX FIFO Global Mask, offset: 0x48 */
12256   __I  uint32_t RXFIR;                             /**< Legacy RX FIFO Information, offset: 0x4C */
12257   __IO uint32_t CBT;                               /**< CAN Bit Timing, offset: 0x50 */
12258        uint8_t RESERVED_2[24];
12259   __IO uint32_t IMASK3;                            /**< Interrupt Masks 3, offset: 0x6C */
12260        uint8_t RESERVED_3[4];
12261   __IO uint32_t IFLAG3;                            /**< Interrupt Flags 3, offset: 0x74 */
12262        uint8_t RESERVED_4[8];
12263   union {                                          /* offset: 0x80 */
12264     struct {                                         /* offset: 0x80, array step: 0x10 */
12265       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */
12266       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */
12267       __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 95 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
12268     } MB_8B[96];
12269     struct {                                         /* offset: 0x80 */
12270       struct {                                         /* offset: 0x80, array step: 0x18 */
12271         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
12272         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
12273         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
12274       } MB_16B_L[21];
12275            uint8_t RESERVED_0[8];
12276       struct {                                         /* offset: 0x280, array step: 0x18 */
12277         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18 */
12278         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18 */
12279         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4 */
12280       } MB_16B_M[21];
12281            uint8_t RESERVED_1[8];
12282       struct {                                         /* offset: 0x480, array step: 0x18 */
12283         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x480, array step: 0x18 */
12284         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x484, array step: 0x18 */
12285         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x488, array step: index*0x18, index2*0x4 */
12286       } MB_16B_H[21];
12287     } MB_16B;
12288     struct {                                         /* offset: 0x80 */
12289       struct {                                         /* offset: 0x80, array step: 0x28 */
12290         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
12291         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
12292         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
12293       } MB_32B_L[12];
12294            uint8_t RESERVED_0[32];
12295       struct {                                         /* offset: 0x280, array step: 0x28 */
12296         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28 */
12297         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28 */
12298         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4 */
12299       } MB_32B_M[12];
12300            uint8_t RESERVED_1[32];
12301       struct {                                         /* offset: 0x480, array step: 0x28 */
12302         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x480, array step: 0x28 */
12303         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x484, array step: 0x28 */
12304         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x488, array step: index*0x28, index2*0x4 */
12305       } MB_32B_H[12];
12306     } MB_32B;
12307     struct {                                         /* offset: 0x80 */
12308       struct {                                         /* offset: 0x80, array step: 0x48 */
12309         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
12310         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
12311         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
12312       } MB_64B_L[7];
12313            uint8_t RESERVED_0[8];
12314       struct {                                         /* offset: 0x280, array step: 0x48 */
12315         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48 */
12316         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48 */
12317         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4 */
12318       } MB_64B_M[7];
12319            uint8_t RESERVED_1[8];
12320       struct {                                         /* offset: 0x480, array step: 0x48 */
12321         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x480, array step: 0x48 */
12322         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x484, array step: 0x48 */
12323         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x488, array step: index*0x48, index2*0x4 */
12324       } MB_64B_H[7];
12325     } MB_64B;
12326     struct {                                         /* offset: 0x80, array step: 0x10 */
12327       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */
12328       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */
12329       __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register, array offset: 0x88, array step: 0x10 */
12330       __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register, array offset: 0x8C, array step: 0x10 */
12331     } MB[96];
12332   };
12333        uint8_t RESERVED_5[512];
12334   __IO uint32_t RXIMR[96];                         /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */
12335        uint8_t RESERVED_6[224];
12336   __IO uint32_t MECR;                              /**< Memory Error Control, offset: 0xAE0 */
12337   __IO uint32_t ERRIAR;                            /**< Error Injection Address, offset: 0xAE4 */
12338   __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern, offset: 0xAE8 */
12339   __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern, offset: 0xAEC */
12340   __I  uint32_t RERRAR;                            /**< Error Report Address, offset: 0xAF0 */
12341   __I  uint32_t RERRDR;                            /**< Error Report Data, offset: 0xAF4 */
12342   __I  uint32_t RERRSYNR;                          /**< Error Report Syndrome, offset: 0xAF8 */
12343   __IO uint32_t ERRSR;                             /**< Error Status, offset: 0xAFC */
12344        uint8_t RESERVED_7[240];
12345   __IO uint32_t EPRS;                              /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
12346   __IO uint32_t ENCBT;                             /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
12347   __IO uint32_t EDCBT;                             /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */
12348   __IO uint32_t ETDC;                              /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
12349   __IO uint32_t FDCTRL;                            /**< CAN FD Control, offset: 0xC00 */
12350   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing, offset: 0xC04 */
12351   __I  uint32_t FDCRC;                             /**< CAN FD CRC, offset: 0xC08 */
12352   __IO uint32_t ERFCR;                             /**< Enhanced RX FIFO Control, offset: 0xC0C */
12353   __IO uint32_t ERFIER;                            /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */
12354   __IO uint32_t ERFSR;                             /**< Enhanced RX FIFO Status, offset: 0xC14 */
12355        uint8_t RESERVED_8[24];
12356   __IO uint32_t HR_TIME_STAMP[96];                 /**< High-Resolution Timestamp, array offset: 0xC30, array step: 0x4 */
12357        uint8_t RESERVED_9[8784];
12358   __IO uint32_t ERFFEL[128];                       /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
12359 } CAN_Type;
12360 
12361 /* ----------------------------------------------------------------------------
12362    -- CAN Register Masks
12363    ---------------------------------------------------------------------------- */
12364 
12365 /*!
12366  * @addtogroup CAN_Register_Masks CAN Register Masks
12367  * @{
12368  */
12369 
12370 /*! @name MCR - Module Configuration */
12371 /*! @{ */
12372 
12373 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
12374 #define CAN_MCR_MAXMB_SHIFT                      (0U)
12375 /*! MAXMB - Number of the Last Message Buffer */
12376 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
12377 
12378 #define CAN_MCR_IDAM_MASK                        (0x300U)
12379 #define CAN_MCR_IDAM_SHIFT                       (8U)
12380 /*! IDAM - ID Acceptance Mode
12381  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
12382  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
12383  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
12384  *  0b11..Format D: All frames rejected.
12385  */
12386 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
12387 
12388 #define CAN_MCR_FDEN_MASK                        (0x800U)
12389 #define CAN_MCR_FDEN_SHIFT                       (11U)
12390 /*! FDEN - CAN FD Operation Enable
12391  *  0b1..Enable
12392  *  0b0..Disable
12393  */
12394 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
12395 
12396 #define CAN_MCR_AEN_MASK                         (0x1000U)
12397 #define CAN_MCR_AEN_SHIFT                        (12U)
12398 /*! AEN - Abort Enable
12399  *  0b0..Disabled
12400  *  0b1..Enabled
12401  */
12402 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
12403 
12404 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
12405 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
12406 /*! LPRIOEN - Local Priority Enable
12407  *  0b0..Disable
12408  *  0b1..Enable
12409  */
12410 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
12411 
12412 #define CAN_MCR_DMA_MASK                         (0x8000U)
12413 #define CAN_MCR_DMA_SHIFT                        (15U)
12414 /*! DMA - DMA Enable
12415  *  0b0..Disable
12416  *  0b1..Enable
12417  */
12418 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
12419 
12420 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
12421 #define CAN_MCR_IRMQ_SHIFT                       (16U)
12422 /*! IRMQ - Individual RX Masking and Queue Enable
12423  *  0b0..Disable
12424  *  0b1..Enable
12425  */
12426 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
12427 
12428 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
12429 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
12430 /*! SRXDIS - Self-Reception Disable
12431  *  0b0..Enable
12432  *  0b1..Disable
12433  */
12434 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
12435 
12436 #define CAN_MCR_DOZE_MASK                        (0x40000U)
12437 #define CAN_MCR_DOZE_SHIFT                       (18U)
12438 /*! DOZE - Doze Mode Enable
12439  *  0b0..Disable
12440  *  0b1..Enable
12441  */
12442 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
12443 
12444 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
12445 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
12446 /*! WAKSRC - Wake-Up Source
12447  *  0b0..No filter applied
12448  *  0b1..Filter applied
12449  */
12450 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
12451 
12452 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
12453 #define CAN_MCR_LPMACK_SHIFT                     (20U)
12454 /*! LPMACK - Low-Power Mode Acknowledge
12455  *  0b0..Not in a low-power mode
12456  *  0b1..In a low-power mode
12457  */
12458 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
12459 
12460 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
12461 #define CAN_MCR_WRNEN_SHIFT                      (21U)
12462 /*! WRNEN - Warning Interrupt Enable
12463  *  0b0..Disable
12464  *  0b1..Enable
12465  */
12466 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
12467 
12468 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
12469 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
12470 /*! SLFWAK - Self Wake-up
12471  *  0b0..Disable
12472  *  0b1..Enable
12473  */
12474 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
12475 
12476 #define CAN_MCR_SUPV_MASK                        (0x800000U)
12477 #define CAN_MCR_SUPV_SHIFT                       (23U)
12478 /*! SUPV - Supervisor Mode
12479  *  0b0..User mode
12480  *  0b1..Supervisor mode
12481  */
12482 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
12483 
12484 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
12485 #define CAN_MCR_FRZACK_SHIFT                     (24U)
12486 /*! FRZACK - Freeze Mode Acknowledge
12487  *  0b0..Not in Freeze mode, prescaler running.
12488  *  0b1..In Freeze mode, prescaler stopped.
12489  */
12490 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
12491 
12492 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
12493 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
12494 /*! SOFTRST - Soft Reset
12495  *  0b0..No reset
12496  *  0b1..Soft reset affects reset registers
12497  */
12498 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
12499 
12500 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
12501 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
12502 /*! WAKMSK - Wake-up Interrupt Mask
12503  *  0b0..Disabled
12504  *  0b1..Enabled
12505  */
12506 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
12507 
12508 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
12509 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
12510 /*! NOTRDY - FlexCAN Not Ready
12511  *  0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode.
12512  *  0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode.
12513  */
12514 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
12515 
12516 #define CAN_MCR_HALT_MASK                        (0x10000000U)
12517 #define CAN_MCR_HALT_SHIFT                       (28U)
12518 /*! HALT - Halt FlexCAN
12519  *  0b0..No request
12520  *  0b1..Enter Freeze mode, if MCR[FRZ] = 1.
12521  */
12522 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
12523 
12524 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
12525 #define CAN_MCR_RFEN_SHIFT                       (29U)
12526 /*! RFEN - Legacy RX FIFO Enable
12527  *  0b0..Disable
12528  *  0b1..Enable
12529  */
12530 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
12531 
12532 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
12533 #define CAN_MCR_FRZ_SHIFT                        (30U)
12534 /*! FRZ - Freeze Enable
12535  *  0b0..Disable
12536  *  0b1..Enable
12537  */
12538 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
12539 
12540 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
12541 #define CAN_MCR_MDIS_SHIFT                       (31U)
12542 /*! MDIS - Module Disable
12543  *  0b0..Enable
12544  *  0b1..Disable
12545  */
12546 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
12547 /*! @} */
12548 
12549 /*! @name CTRL1 - Control 1 */
12550 /*! @{ */
12551 
12552 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
12553 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
12554 /*! PROPSEG - Propagation Segment */
12555 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
12556 
12557 #define CAN_CTRL1_LOM_MASK                       (0x8U)
12558 #define CAN_CTRL1_LOM_SHIFT                      (3U)
12559 /*! LOM - Listen-Only Mode
12560  *  0b0..Listen-Only mode is deactivated.
12561  *  0b1..FlexCAN module operates in Listen-Only mode.
12562  */
12563 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
12564 
12565 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
12566 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
12567 /*! LBUF - Lowest Buffer Transmitted First
12568  *  0b0..Buffer with highest priority is transmitted first.
12569  *  0b1..Lowest number buffer is transmitted first.
12570  */
12571 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
12572 
12573 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
12574 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
12575 /*! TSYN - Timer Sync
12576  *  0b0..Disable
12577  *  0b1..Enable
12578  */
12579 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
12580 
12581 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
12582 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
12583 /*! BOFFREC - Bus Off Recovery
12584  *  0b0..Enabled
12585  *  0b1..Disabled
12586  */
12587 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
12588 
12589 #define CAN_CTRL1_SMP_MASK                       (0x80U)
12590 #define CAN_CTRL1_SMP_SHIFT                      (7U)
12591 /*! SMP - CAN Bit Sampling
12592  *  0b0..One sample is used to determine the bit value.
12593  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
12594  *       preceding samples. A majority rule is used.
12595  */
12596 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
12597 
12598 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
12599 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
12600 /*! RWRNMSK - RX Warning Interrupt Mask
12601  *  0b0..Disabled
12602  *  0b1..Enabled
12603  */
12604 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
12605 
12606 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
12607 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
12608 /*! TWRNMSK - TX Warning Interrupt Mask
12609  *  0b0..Disabled
12610  *  0b1..Enabled
12611  */
12612 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
12613 
12614 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
12615 #define CAN_CTRL1_LPB_SHIFT                      (12U)
12616 /*! LPB - Loopback Mode
12617  *  0b0..Disabled
12618  *  0b1..Enabled
12619  */
12620 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
12621 
12622 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
12623 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
12624 /*! CLKSRC - CAN Engine Clock Source
12625  *  0b0..Peripheral clock
12626  *  0b1..Bus clock
12627  */
12628 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
12629 
12630 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
12631 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
12632 /*! ERRMSK - Error Interrupt Mask
12633  *  0b0..Interrupt disabled
12634  *  0b1..Interrupt enabled
12635  */
12636 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
12637 
12638 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
12639 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
12640 /*! BOFFMSK - Bus Off Interrupt Mask
12641  *  0b0..Interrupt disabled
12642  *  0b1..Interrupt enabled
12643  */
12644 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
12645 
12646 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
12647 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
12648 /*! PSEG2 - Phase Segment 2 */
12649 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
12650 
12651 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
12652 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
12653 /*! PSEG1 - Phase Segment 1 */
12654 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
12655 
12656 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
12657 #define CAN_CTRL1_RJW_SHIFT                      (22U)
12658 /*! RJW - Resync Jump Width */
12659 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
12660 
12661 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
12662 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
12663 /*! PRESDIV - Prescaler Division Factor */
12664 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
12665 /*! @} */
12666 
12667 /*! @name TIMER - Free-Running Timer */
12668 /*! @{ */
12669 
12670 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
12671 #define CAN_TIMER_TIMER_SHIFT                    (0U)
12672 /*! TIMER - Timer Value */
12673 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
12674 /*! @} */
12675 
12676 /*! @name RXMGMASK - RX Message Buffers Global Mask */
12677 /*! @{ */
12678 
12679 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
12680 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
12681 /*! MG - Global Mask for RX Message Buffers */
12682 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
12683 /*! @} */
12684 
12685 /*! @name RX14MASK - Receive 14 Mask */
12686 /*! @{ */
12687 
12688 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
12689 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
12690 /*! RX14M - RX Buffer 14 Mask Bits */
12691 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
12692 /*! @} */
12693 
12694 /*! @name RX15MASK - Receive 15 Mask */
12695 /*! @{ */
12696 
12697 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
12698 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
12699 /*! RX15M - RX Buffer 15 Mask Bits */
12700 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
12701 /*! @} */
12702 
12703 /*! @name ECR - Error Counter */
12704 /*! @{ */
12705 
12706 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
12707 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
12708 /*! TXERRCNT - Transmit Error Counter */
12709 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
12710 
12711 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
12712 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
12713 /*! RXERRCNT - Receive Error Counter */
12714 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
12715 
12716 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
12717 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
12718 /*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */
12719 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
12720 
12721 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
12722 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
12723 /*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */
12724 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
12725 /*! @} */
12726 
12727 /*! @name ESR1 - Error and Status 1 */
12728 /*! @{ */
12729 
12730 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
12731 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
12732 /*! WAKINT - Wake-up Interrupt Flag
12733  *  0b0..No such occurrence.
12734  *  0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus.
12735  */
12736 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
12737 
12738 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
12739 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
12740 /*! ERRINT - Error Interrupt Flag
12741  *  0b0..No such occurrence.
12742  *  0b1..Indicates setting of any error flag in the Error and Status register.
12743  */
12744 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
12745 
12746 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
12747 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
12748 /*! BOFFINT - Bus Off Interrupt Flag
12749  *  0b0..No such occurrence.
12750  *  0b1..FlexCAN module entered Bus Off state.
12751  */
12752 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
12753 
12754 #define CAN_ESR1_RX_MASK                         (0x8U)
12755 #define CAN_ESR1_RX_SHIFT                        (3U)
12756 /*! RX - FlexCAN in Reception Flag
12757  *  0b0..Not receiving
12758  *  0b1..Receiving
12759  */
12760 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
12761 
12762 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
12763 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
12764 /*! FLTCONF - Fault Confinement State
12765  *  0b00..Error Active
12766  *  0b01..Error Passive
12767  *  0b1x..Bus Off
12768  */
12769 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
12770 
12771 #define CAN_ESR1_TX_MASK                         (0x40U)
12772 #define CAN_ESR1_TX_SHIFT                        (6U)
12773 /*! TX - FlexCAN In Transmission
12774  *  0b0..Not transmitting
12775  *  0b1..Transmitting
12776  */
12777 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
12778 
12779 #define CAN_ESR1_IDLE_MASK                       (0x80U)
12780 #define CAN_ESR1_IDLE_SHIFT                      (7U)
12781 /*! IDLE - Idle
12782  *  0b0..Not IDLE
12783  *  0b1..IDLE
12784  */
12785 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
12786 
12787 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
12788 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
12789 /*! RXWRN - RX Error Warning Flag
12790  *  0b0..No such occurrence.
12791  *  0b1..RXERRCNT is greater than or equal to 96.
12792  */
12793 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
12794 
12795 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
12796 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
12797 /*! TXWRN - TX Error Warning Flag
12798  *  0b0..No such occurrence.
12799  *  0b1..TXERRCNT is 96 or greater.
12800  */
12801 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
12802 
12803 #define CAN_ESR1_STFERR_MASK                     (0x400U)
12804 #define CAN_ESR1_STFERR_SHIFT                    (10U)
12805 /*! STFERR - Stuffing Error Flag
12806  *  0b0..No error
12807  *  0b1..Error occurred since last read of this register.
12808  */
12809 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
12810 
12811 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
12812 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
12813 /*! FRMERR - Form Error Flag
12814  *  0b0..No error
12815  *  0b1..Error occurred since last read of this register.
12816  */
12817 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
12818 
12819 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
12820 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
12821 /*! CRCERR - Cyclic Redundancy Check Error Flag
12822  *  0b0..No error
12823  *  0b1..Error occurred since last read of this register.
12824  */
12825 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
12826 
12827 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
12828 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
12829 /*! ACKERR - Acknowledge Error Flag
12830  *  0b0..No error
12831  *  0b1..Error occurred since last read of this register.
12832  */
12833 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
12834 
12835 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
12836 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
12837 /*! BIT0ERR - Bit0 Error Flag
12838  *  0b0..No such occurrence.
12839  *  0b1..At least one bit sent as dominant is received as recessive.
12840  */
12841 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
12842 
12843 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
12844 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
12845 /*! BIT1ERR - Bit1 Error Flag
12846  *  0b0..No such occurrence.
12847  *  0b1..At least one bit sent as recessive is received as dominant.
12848  */
12849 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
12850 
12851 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
12852 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
12853 /*! RWRNINT - RX Warning Interrupt Flag
12854  *  0b0..No such occurrence
12855  *  0b1..RX error counter changed from less than 96 to greater than or equal to 96.
12856  */
12857 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
12858 
12859 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
12860 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
12861 /*! TWRNINT - TX Warning Interrupt Flag
12862  *  0b0..No such occurrence
12863  *  0b1..TX error counter changed from less than 96 to greater than or equal to 96.
12864  */
12865 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
12866 
12867 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
12868 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
12869 /*! SYNCH - CAN Synchronization Status Flag
12870  *  0b0..Not synchronized
12871  *  0b1..Synchronized
12872  */
12873 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
12874 
12875 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
12876 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
12877 /*! BOFFDONEINT - Bus Off Done Interrupt Flag
12878  *  0b0..No such occurrence
12879  *  0b1..FlexCAN module has completed Bus Off process.
12880  */
12881 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
12882 
12883 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
12884 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
12885 /*! ERRINT_FAST - Fast Error Interrupt Flag
12886  *  0b0..No such occurrence.
12887  *  0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1.
12888  */
12889 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
12890 
12891 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
12892 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
12893 /*! ERROVR - Error Overrun Flag
12894  *  0b0..No overrun
12895  *  0b1..Overrun
12896  */
12897 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
12898 
12899 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
12900 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
12901 /*! STFERR_FAST - Fast Stuffing Error Flag
12902  *  0b0..No such occurrence.
12903  *  0b1..A stuffing error occurred since last read of this register.
12904  */
12905 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
12906 
12907 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
12908 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
12909 /*! FRMERR_FAST - Fast Form Error Flag
12910  *  0b0..No such occurrence.
12911  *  0b1..A form error occurred since last read of this register.
12912  */
12913 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
12914 
12915 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
12916 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
12917 /*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag
12918  *  0b0..No such occurrence.
12919  *  0b1..A CRC error occurred since last read of this register.
12920  */
12921 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
12922 
12923 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
12924 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
12925 /*! BIT0ERR_FAST - Fast Bit0 Error Flag
12926  *  0b0..No such occurrence.
12927  *  0b1..At least one bit transmitted as dominant is received as recessive.
12928  */
12929 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
12930 
12931 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
12932 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
12933 /*! BIT1ERR_FAST - Fast Bit1 Error Flag
12934  *  0b0..No such occurrence.
12935  *  0b1..At least one bit transmitted as recessive is received as dominant.
12936  */
12937 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
12938 /*! @} */
12939 
12940 /*! @name IMASK2 - Interrupt Masks 2 */
12941 /*! @{ */
12942 
12943 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
12944 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
12945 /*! BUF63TO32M - Buffer MBi Mask */
12946 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
12947 /*! @} */
12948 
12949 /*! @name IMASK1 - Interrupt Masks 1 */
12950 /*! @{ */
12951 
12952 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
12953 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
12954 /*! BUF31TO0M - Buffer MBi Mask */
12955 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
12956 /*! @} */
12957 
12958 /*! @name IFLAG2 - Interrupt Flags 2 */
12959 /*! @{ */
12960 
12961 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
12962 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
12963 /*! BUF63TO32I - Buffer MBi Interrupt */
12964 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
12965 /*! @} */
12966 
12967 /*! @name IFLAG1 - Interrupt Flags 1 */
12968 /*! @{ */
12969 
12970 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
12971 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
12972 /*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit
12973  *  0b0..MB0 has no occurrence of successfully completed transmission or reception.
12974  *  0b1..MB0 has successfully completed transmission or reception.
12975  */
12976 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
12977 
12978 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
12979 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
12980 /*! BUF4TO1I - Buffer MBi Interrupt or Reserved */
12981 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
12982 
12983 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
12984 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
12985 /*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO
12986  *  0b0..No occurrence of completed transmission or reception, or no frames available
12987  *  0b1..MB5 completed transmission or reception, or frames available
12988  */
12989 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
12990 
12991 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
12992 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
12993 /*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning
12994  *  0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full.
12995  *  0b1..MB6 completed transmission or reception, or FIFO almost full.
12996  */
12997 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
12998 
12999 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
13000 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
13001 /*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow
13002  *  0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow.
13003  *  0b1..MB7 completed transmission or reception, or FIFO overflow.
13004  */
13005 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
13006 
13007 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
13008 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
13009 /*! BUF31TO8I - Buffer MBi Interrupt */
13010 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
13011 /*! @} */
13012 
13013 /*! @name CTRL2 - Control 2 */
13014 /*! @{ */
13015 
13016 #define CAN_CTRL2_TSTAMPCAP_MASK                 (0xC0U)
13017 #define CAN_CTRL2_TSTAMPCAP_SHIFT                (6U)
13018 /*! TSTAMPCAP - Timestamp Capture Point
13019  *  0b00..Disabled
13020  *  0b01..End of the CAN frame
13021  *  0b10..Start of the CAN frame
13022  *  0b11..Start of frame for classical CAN frames; res bit for CAN FD frames
13023  */
13024 #define CAN_CTRL2_TSTAMPCAP(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)
13025 
13026 #define CAN_CTRL2_MBTSBASE_MASK                  (0x300U)
13027 #define CAN_CTRL2_MBTSBASE_SHIFT                 (8U)
13028 /*! MBTSBASE - Message Buffer Timestamp Base
13029  *  0b00..TIMER
13030  *  0b01..Lower 16 bits of high-resolution timer
13031  *  0b10..Upper 16 bits of high-resolution timer
13032  *  0b11..Reserved
13033  */
13034 #define CAN_CTRL2_MBTSBASE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)
13035 
13036 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
13037 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
13038 /*! EDFLTDIS - Edge Filter Disable
13039  *  0b0..Enabled
13040  *  0b1..Disabled
13041  */
13042 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
13043 
13044 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
13045 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
13046 /*! ISOCANFDEN - ISO CAN FD Enable
13047  *  0b0..Disable
13048  *  0b1..Enable
13049  */
13050 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
13051 
13052 #define CAN_CTRL2_BTE_MASK                       (0x2000U)
13053 #define CAN_CTRL2_BTE_SHIFT                      (13U)
13054 /*! BTE - Bit Timing Expansion Enable
13055  *  0b0..Disable
13056  *  0b1..Enable
13057  */
13058 #define CAN_CTRL2_BTE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
13059 
13060 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
13061 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
13062 /*! PREXCEN - Protocol Exception Enable
13063  *  0b0..Disabled
13064  *  0b1..Enabled
13065  */
13066 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
13067 
13068 #define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
13069 #define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
13070 /*! TIMER_SRC - Timer Source
13071  *  0b0..CAN bit clock
13072  *  0b1..External time tick
13073  */
13074 #define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
13075 
13076 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
13077 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
13078 /*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers
13079  *  0b0..Disable
13080  *  0b1..Enable
13081  */
13082 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
13083 
13084 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
13085 #define CAN_CTRL2_RRS_SHIFT                      (17U)
13086 /*! RRS - Remote Request Storing
13087  *  0b0..Generated
13088  *  0b1..Stored
13089  */
13090 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
13091 
13092 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
13093 #define CAN_CTRL2_MRP_SHIFT                      (18U)
13094 /*! MRP - Message Buffers Reception Priority
13095  *  0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers.
13096  *  0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO.
13097  */
13098 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
13099 
13100 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
13101 #define CAN_CTRL2_TASD_SHIFT                     (19U)
13102 /*! TASD - Transmission Arbitration Start Delay */
13103 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
13104 
13105 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
13106 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
13107 /*! RFFN - Number of Legacy Receive FIFO Filters */
13108 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
13109 
13110 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
13111 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
13112 /*! WRMFRZ - Write Access to Memory in Freeze Mode
13113  *  0b0..Disable
13114  *  0b1..Enable
13115  */
13116 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
13117 
13118 #define CAN_CTRL2_ECRWRE_MASK                    (0x20000000U)
13119 #define CAN_CTRL2_ECRWRE_SHIFT                   (29U)
13120 /*! ECRWRE - Error Correction Configuration Register Write Enable
13121  *  0b0..Disable
13122  *  0b1..Enable
13123  */
13124 #define CAN_CTRL2_ECRWRE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
13125 
13126 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
13127 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
13128 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
13129  *  0b0..Disable
13130  *  0b1..Enable
13131  */
13132 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
13133 
13134 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
13135 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
13136 /*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames
13137  *  0b0..Disable
13138  *  0b1..Enable
13139  */
13140 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
13141 /*! @} */
13142 
13143 /*! @name ESR2 - Error and Status 2 */
13144 /*! @{ */
13145 
13146 #define CAN_ESR2_IMB_MASK                        (0x2000U)
13147 #define CAN_ESR2_IMB_SHIFT                       (13U)
13148 /*! IMB - Inactive Message Buffer
13149  *  0b0..Message buffer indicated by ESR2[LPTM] is not inactive.
13150  *  0b1..At least one message buffer is inactive.
13151  */
13152 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
13153 
13154 #define CAN_ESR2_VPS_MASK                        (0x4000U)
13155 #define CAN_ESR2_VPS_SHIFT                       (14U)
13156 /*! VPS - Valid Priority Status
13157  *  0b0..Invalid
13158  *  0b1..Valid
13159  */
13160 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
13161 
13162 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
13163 #define CAN_ESR2_LPTM_SHIFT                      (16U)
13164 /*! LPTM - Lowest Priority TX Message Buffer */
13165 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
13166 /*! @} */
13167 
13168 /*! @name CRCR - Cyclic Redundancy Check */
13169 /*! @{ */
13170 
13171 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
13172 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
13173 /*! TXCRC - Transmitted CRC value */
13174 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
13175 
13176 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
13177 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
13178 /*! MBCRC - CRC Message Buffer */
13179 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
13180 /*! @} */
13181 
13182 /*! @name RXFGMASK - Legacy RX FIFO Global Mask */
13183 /*! @{ */
13184 
13185 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
13186 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
13187 /*! FGM - Legacy RX FIFO Global Mask Bits */
13188 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
13189 /*! @} */
13190 
13191 /*! @name RXFIR - Legacy RX FIFO Information */
13192 /*! @{ */
13193 
13194 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
13195 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
13196 /*! IDHIT - Identifier Acceptance Filter Hit Indicator */
13197 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
13198 /*! @} */
13199 
13200 /*! @name CBT - CAN Bit Timing */
13201 /*! @{ */
13202 
13203 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
13204 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
13205 /*! EPSEG2 - Extended Phase Segment 2 */
13206 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
13207 
13208 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
13209 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
13210 /*! EPSEG1 - Extended Phase Segment 1 */
13211 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
13212 
13213 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
13214 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
13215 /*! EPROPSEG - Extended Propagation Segment */
13216 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
13217 
13218 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
13219 #define CAN_CBT_ERJW_SHIFT                       (16U)
13220 /*! ERJW - Extended Resync Jump Width */
13221 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
13222 
13223 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
13224 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
13225 /*! EPRESDIV - Extended Prescaler Division Factor */
13226 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
13227 
13228 #define CAN_CBT_BTF_MASK                         (0x80000000U)
13229 #define CAN_CBT_BTF_SHIFT                        (31U)
13230 /*! BTF - Bit Timing Format Enable
13231  *  0b0..Disable
13232  *  0b1..Enable
13233  */
13234 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
13235 /*! @} */
13236 
13237 /*! @name IMASK3 - Interrupt Masks 3 */
13238 /*! @{ */
13239 
13240 #define CAN_IMASK3_BUF95TO64M_MASK               (0xFFFFFFFFU)
13241 #define CAN_IMASK3_BUF95TO64M_SHIFT              (0U)
13242 /*! BUF95TO64M - Buffer MBi Mask */
13243 #define CAN_IMASK3_BUF95TO64M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK3_BUF95TO64M_SHIFT)) & CAN_IMASK3_BUF95TO64M_MASK)
13244 /*! @} */
13245 
13246 /*! @name IFLAG3 - Interrupt Flags 3 */
13247 /*! @{ */
13248 
13249 #define CAN_IFLAG3_BUF95TO64_MASK                (0xFFFFFFFFU)
13250 #define CAN_IFLAG3_BUF95TO64_SHIFT               (0U)
13251 /*! BUF95TO64 - Buffer MBi Interrupt */
13252 #define CAN_IFLAG3_BUF95TO64(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG3_BUF95TO64_SHIFT)) & CAN_IFLAG3_BUF95TO64_MASK)
13253 /*! @} */
13254 
13255 /* The count of CAN_CS */
13256 #define CAN_CS_COUNT_MB8B                        (96U)
13257 
13258 /* The count of CAN_ID */
13259 #define CAN_ID_COUNT_MB8B                        (96U)
13260 
13261 /* The count of CAN_WORD */
13262 #define CAN_WORD_COUNT_MB8B                      (96U)
13263 
13264 /* The count of CAN_WORD */
13265 #define CAN_WORD_COUNT_MB8B2                     (2U)
13266 
13267 /* The count of CAN_CS */
13268 #define CAN_CS_COUNT_MB16B_L                     (21U)
13269 
13270 /* The count of CAN_ID */
13271 #define CAN_ID_COUNT_MB16B_L                     (21U)
13272 
13273 /* The count of CAN_WORD */
13274 #define CAN_WORD_COUNT_MB16B_L                   (21U)
13275 
13276 /* The count of CAN_WORD */
13277 #define CAN_WORD_COUNT_MB16B_L2                  (4U)
13278 
13279 /* The count of CAN_CS */
13280 #define CAN_CS_COUNT_MB16B_M                     (21U)
13281 
13282 /* The count of CAN_ID */
13283 #define CAN_ID_COUNT_MB16B_M                     (21U)
13284 
13285 /* The count of CAN_WORD */
13286 #define CAN_WORD_COUNT_MB16B_M                   (21U)
13287 
13288 /* The count of CAN_WORD */
13289 #define CAN_WORD_COUNT_MB16B_M2                  (4U)
13290 
13291 /* The count of CAN_CS */
13292 #define CAN_CS_COUNT_MB16B_H                     (21U)
13293 
13294 /* The count of CAN_ID */
13295 #define CAN_ID_COUNT_MB16B_H                     (21U)
13296 
13297 /* The count of CAN_WORD */
13298 #define CAN_WORD_COUNT_MB16B_H                   (21U)
13299 
13300 /* The count of CAN_WORD */
13301 #define CAN_WORD_COUNT_MB16B_H2                  (4U)
13302 
13303 /* The count of CAN_CS */
13304 #define CAN_CS_COUNT_MB32B_L                     (12U)
13305 
13306 /* The count of CAN_ID */
13307 #define CAN_ID_COUNT_MB32B_L                     (12U)
13308 
13309 /* The count of CAN_WORD */
13310 #define CAN_WORD_COUNT_MB32B_L                   (12U)
13311 
13312 /* The count of CAN_WORD */
13313 #define CAN_WORD_COUNT_MB32B_L2                  (8U)
13314 
13315 /* The count of CAN_CS */
13316 #define CAN_CS_COUNT_MB32B_M                     (12U)
13317 
13318 /* The count of CAN_ID */
13319 #define CAN_ID_COUNT_MB32B_M                     (12U)
13320 
13321 /* The count of CAN_WORD */
13322 #define CAN_WORD_COUNT_MB32B_M                   (12U)
13323 
13324 /* The count of CAN_WORD */
13325 #define CAN_WORD_COUNT_MB32B_M2                  (8U)
13326 
13327 /* The count of CAN_CS */
13328 #define CAN_CS_COUNT_MB32B_H                     (12U)
13329 
13330 /* The count of CAN_ID */
13331 #define CAN_ID_COUNT_MB32B_H                     (12U)
13332 
13333 /* The count of CAN_WORD */
13334 #define CAN_WORD_COUNT_MB32B_H                   (12U)
13335 
13336 /* The count of CAN_WORD */
13337 #define CAN_WORD_COUNT_MB32B_H2                  (8U)
13338 
13339 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
13340 /*! @{ */
13341 
13342 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
13343 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
13344 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
13345  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
13346  *    appears on the CAN bus.
13347  */
13348 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
13349 
13350 #define CAN_CS_DLC_MASK                          (0xF0000U)
13351 #define CAN_CS_DLC_SHIFT                         (16U)
13352 /*! DLC - Length of the data to be stored/transmitted. */
13353 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
13354 
13355 #define CAN_CS_RTR_MASK                          (0x100000U)
13356 #define CAN_CS_RTR_SHIFT                         (20U)
13357 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
13358 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
13359 
13360 #define CAN_CS_IDE_MASK                          (0x200000U)
13361 #define CAN_CS_IDE_SHIFT                         (21U)
13362 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
13363 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
13364 
13365 #define CAN_CS_SRR_MASK                          (0x400000U)
13366 #define CAN_CS_SRR_SHIFT                         (22U)
13367 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
13368 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
13369 
13370 #define CAN_CS_CODE_MASK                         (0xF000000U)
13371 #define CAN_CS_CODE_SHIFT                        (24U)
13372 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
13373  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
13374  */
13375 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
13376 
13377 #define CAN_CS_ESI_MASK                          (0x20000000U)
13378 #define CAN_CS_ESI_SHIFT                         (29U)
13379 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
13380 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
13381 
13382 #define CAN_CS_BRS_MASK                          (0x40000000U)
13383 #define CAN_CS_BRS_SHIFT                         (30U)
13384 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
13385 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
13386 
13387 #define CAN_CS_EDL_MASK                          (0x80000000U)
13388 #define CAN_CS_EDL_SHIFT                         (31U)
13389 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
13390  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
13391  */
13392 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
13393 /*! @} */
13394 
13395 /* The count of CAN_CS */
13396 #define CAN_CS_COUNT_MB64B_L                     (7U)
13397 
13398 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
13399 /*! @{ */
13400 
13401 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
13402 #define CAN_ID_EXT_SHIFT                         (0U)
13403 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
13404 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
13405 
13406 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
13407 #define CAN_ID_STD_SHIFT                         (18U)
13408 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
13409 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
13410 
13411 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
13412 #define CAN_ID_PRIO_SHIFT                        (29U)
13413 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
13414  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
13415  *    ID to define the transmission priority.
13416  */
13417 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
13418 /*! @} */
13419 
13420 /* The count of CAN_ID */
13421 #define CAN_ID_COUNT_MB64B_L                     (7U)
13422 
13423 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
13424 /*! @{ */
13425 
13426 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
13427 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
13428 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
13429 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
13430 
13431 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
13432 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
13433 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
13434 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
13435 
13436 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
13437 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
13438 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
13439 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
13440 
13441 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
13442 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
13443 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
13444 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
13445 
13446 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
13447 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
13448 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
13449 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
13450 
13451 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
13452 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
13453 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
13454 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
13455 
13456 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
13457 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
13458 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
13459 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
13460 
13461 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
13462 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
13463 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
13464 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
13465 
13466 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
13467 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
13468 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
13469 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
13470 
13471 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
13472 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
13473 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
13474 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
13475 
13476 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
13477 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
13478 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
13479 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
13480 
13481 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
13482 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
13483 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
13484 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
13485 
13486 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
13487 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
13488 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
13489 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
13490 
13491 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
13492 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
13493 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
13494 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
13495 
13496 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
13497 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
13498 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
13499 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
13500 
13501 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
13502 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
13503 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
13504 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
13505 
13506 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
13507 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
13508 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
13509 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
13510 
13511 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
13512 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
13513 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
13514 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
13515 
13516 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
13517 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
13518 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
13519 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
13520 
13521 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
13522 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
13523 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
13524 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
13525 
13526 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
13527 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
13528 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
13529 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
13530 
13531 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
13532 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
13533 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
13534 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
13535 
13536 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
13537 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
13538 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
13539 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
13540 
13541 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
13542 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
13543 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
13544 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
13545 
13546 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
13547 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
13548 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
13549 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
13550 
13551 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
13552 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
13553 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
13554 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
13555 
13556 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
13557 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
13558 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
13559 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
13560 
13561 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
13562 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
13563 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
13564 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
13565 
13566 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
13567 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
13568 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
13569 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
13570 
13571 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
13572 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
13573 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
13574 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
13575 
13576 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
13577 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
13578 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
13579 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
13580 
13581 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
13582 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
13583 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
13584 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
13585 
13586 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
13587 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
13588 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
13589 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
13590 
13591 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
13592 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
13593 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
13594 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
13595 
13596 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
13597 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
13598 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
13599 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
13600 
13601 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
13602 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
13603 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
13604 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
13605 
13606 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
13607 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
13608 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
13609 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
13610 
13611 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
13612 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
13613 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
13614 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
13615 
13616 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
13617 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
13618 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
13619 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
13620 
13621 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
13622 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
13623 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
13624 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
13625 
13626 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
13627 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
13628 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
13629 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
13630 
13631 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
13632 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
13633 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
13634 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
13635 
13636 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
13637 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
13638 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
13639 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
13640 
13641 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
13642 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
13643 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
13644 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
13645 
13646 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
13647 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
13648 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
13649 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
13650 
13651 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
13652 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
13653 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
13654 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
13655 
13656 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
13657 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
13658 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
13659 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
13660 
13661 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
13662 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
13663 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
13664 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
13665 
13666 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
13667 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
13668 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
13669 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
13670 
13671 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
13672 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
13673 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
13674 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
13675 
13676 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
13677 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
13678 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
13679 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
13680 
13681 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
13682 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
13683 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
13684 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
13685 
13686 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
13687 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
13688 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
13689 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
13690 
13691 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
13692 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
13693 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
13694 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
13695 
13696 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
13697 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
13698 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
13699 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
13700 
13701 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
13702 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
13703 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
13704 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
13705 
13706 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
13707 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
13708 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
13709 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
13710 
13711 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
13712 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
13713 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
13714 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
13715 
13716 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
13717 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
13718 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
13719 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
13720 
13721 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
13722 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
13723 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
13724 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
13725 
13726 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
13727 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
13728 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
13729 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
13730 
13731 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
13732 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
13733 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
13734 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
13735 
13736 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
13737 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
13738 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
13739 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
13740 
13741 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
13742 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
13743 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
13744 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
13745 /*! @} */
13746 
13747 /* The count of CAN_WORD */
13748 #define CAN_WORD_COUNT_MB64B_L                   (7U)
13749 
13750 /* The count of CAN_WORD */
13751 #define CAN_WORD_COUNT_MB64B_L2                  (16U)
13752 
13753 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
13754 /*! @{ */
13755 
13756 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
13757 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
13758 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
13759  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
13760  *    appears on the CAN bus.
13761  */
13762 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
13763 
13764 #define CAN_CS_DLC_MASK                          (0xF0000U)
13765 #define CAN_CS_DLC_SHIFT                         (16U)
13766 /*! DLC - Length of the data to be stored/transmitted. */
13767 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
13768 
13769 #define CAN_CS_RTR_MASK                          (0x100000U)
13770 #define CAN_CS_RTR_SHIFT                         (20U)
13771 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
13772 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
13773 
13774 #define CAN_CS_IDE_MASK                          (0x200000U)
13775 #define CAN_CS_IDE_SHIFT                         (21U)
13776 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
13777 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
13778 
13779 #define CAN_CS_SRR_MASK                          (0x400000U)
13780 #define CAN_CS_SRR_SHIFT                         (22U)
13781 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
13782 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
13783 
13784 #define CAN_CS_CODE_MASK                         (0xF000000U)
13785 #define CAN_CS_CODE_SHIFT                        (24U)
13786 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
13787  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
13788  */
13789 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
13790 
13791 #define CAN_CS_ESI_MASK                          (0x20000000U)
13792 #define CAN_CS_ESI_SHIFT                         (29U)
13793 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
13794 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
13795 
13796 #define CAN_CS_BRS_MASK                          (0x40000000U)
13797 #define CAN_CS_BRS_SHIFT                         (30U)
13798 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
13799 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
13800 
13801 #define CAN_CS_EDL_MASK                          (0x80000000U)
13802 #define CAN_CS_EDL_SHIFT                         (31U)
13803 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
13804  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
13805  */
13806 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
13807 /*! @} */
13808 
13809 /* The count of CAN_CS */
13810 #define CAN_CS_COUNT_MB64B_M                     (7U)
13811 
13812 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
13813 /*! @{ */
13814 
13815 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
13816 #define CAN_ID_EXT_SHIFT                         (0U)
13817 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
13818 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
13819 
13820 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
13821 #define CAN_ID_STD_SHIFT                         (18U)
13822 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
13823 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
13824 
13825 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
13826 #define CAN_ID_PRIO_SHIFT                        (29U)
13827 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
13828  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
13829  *    ID to define the transmission priority.
13830  */
13831 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
13832 /*! @} */
13833 
13834 /* The count of CAN_ID */
13835 #define CAN_ID_COUNT_MB64B_M                     (7U)
13836 
13837 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
13838 /*! @{ */
13839 
13840 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
13841 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
13842 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
13843 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
13844 
13845 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
13846 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
13847 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
13848 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
13849 
13850 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
13851 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
13852 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
13853 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
13854 
13855 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
13856 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
13857 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
13858 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
13859 
13860 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
13861 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
13862 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
13863 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
13864 
13865 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
13866 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
13867 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
13868 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
13869 
13870 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
13871 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
13872 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
13873 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
13874 
13875 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
13876 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
13877 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
13878 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
13879 
13880 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
13881 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
13882 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
13883 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
13884 
13885 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
13886 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
13887 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
13888 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
13889 
13890 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
13891 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
13892 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
13893 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
13894 
13895 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
13896 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
13897 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
13898 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
13899 
13900 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
13901 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
13902 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
13903 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
13904 
13905 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
13906 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
13907 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
13908 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
13909 
13910 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
13911 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
13912 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
13913 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
13914 
13915 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
13916 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
13917 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
13918 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
13919 
13920 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
13921 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
13922 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
13923 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
13924 
13925 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
13926 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
13927 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
13928 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
13929 
13930 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
13931 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
13932 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
13933 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
13934 
13935 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
13936 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
13937 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
13938 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
13939 
13940 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
13941 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
13942 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
13943 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
13944 
13945 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
13946 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
13947 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
13948 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
13949 
13950 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
13951 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
13952 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
13953 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
13954 
13955 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
13956 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
13957 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
13958 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
13959 
13960 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
13961 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
13962 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
13963 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
13964 
13965 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
13966 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
13967 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
13968 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
13969 
13970 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
13971 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
13972 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
13973 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
13974 
13975 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
13976 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
13977 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
13978 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
13979 
13980 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
13981 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
13982 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
13983 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
13984 
13985 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
13986 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
13987 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
13988 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
13989 
13990 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
13991 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
13992 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
13993 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
13994 
13995 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
13996 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
13997 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
13998 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
13999 
14000 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
14001 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
14002 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
14003 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
14004 
14005 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
14006 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
14007 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
14008 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
14009 
14010 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
14011 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
14012 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
14013 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
14014 
14015 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
14016 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
14017 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
14018 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
14019 
14020 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
14021 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
14022 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
14023 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
14024 
14025 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
14026 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
14027 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
14028 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
14029 
14030 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
14031 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
14032 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
14033 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
14034 
14035 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
14036 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
14037 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
14038 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
14039 
14040 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
14041 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
14042 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
14043 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
14044 
14045 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
14046 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
14047 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
14048 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
14049 
14050 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
14051 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
14052 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
14053 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
14054 
14055 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
14056 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
14057 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
14058 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
14059 
14060 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
14061 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
14062 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
14063 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
14064 
14065 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
14066 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
14067 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
14068 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
14069 
14070 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
14071 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
14072 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
14073 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
14074 
14075 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
14076 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
14077 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
14078 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
14079 
14080 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
14081 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
14082 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
14083 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
14084 
14085 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
14086 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
14087 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
14088 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
14089 
14090 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
14091 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
14092 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
14093 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
14094 
14095 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
14096 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
14097 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
14098 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
14099 
14100 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
14101 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
14102 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
14103 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
14104 
14105 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
14106 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
14107 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
14108 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
14109 
14110 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
14111 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
14112 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
14113 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
14114 
14115 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
14116 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
14117 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
14118 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
14119 
14120 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
14121 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
14122 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
14123 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
14124 
14125 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
14126 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
14127 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
14128 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
14129 
14130 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
14131 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
14132 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
14133 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
14134 
14135 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
14136 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
14137 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
14138 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
14139 
14140 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
14141 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
14142 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
14143 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
14144 
14145 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
14146 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
14147 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
14148 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
14149 
14150 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
14151 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
14152 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
14153 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
14154 
14155 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
14156 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
14157 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
14158 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
14159 /*! @} */
14160 
14161 /* The count of CAN_WORD */
14162 #define CAN_WORD_COUNT_MB64B_M                   (7U)
14163 
14164 /* The count of CAN_WORD */
14165 #define CAN_WORD_COUNT_MB64B_M2                  (16U)
14166 
14167 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
14168 /*! @{ */
14169 
14170 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
14171 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
14172 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
14173  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
14174  *    appears on the CAN bus.
14175  */
14176 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
14177 
14178 #define CAN_CS_DLC_MASK                          (0xF0000U)
14179 #define CAN_CS_DLC_SHIFT                         (16U)
14180 /*! DLC - Length of the data to be stored/transmitted. */
14181 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
14182 
14183 #define CAN_CS_RTR_MASK                          (0x100000U)
14184 #define CAN_CS_RTR_SHIFT                         (20U)
14185 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
14186 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
14187 
14188 #define CAN_CS_IDE_MASK                          (0x200000U)
14189 #define CAN_CS_IDE_SHIFT                         (21U)
14190 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
14191 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
14192 
14193 #define CAN_CS_SRR_MASK                          (0x400000U)
14194 #define CAN_CS_SRR_SHIFT                         (22U)
14195 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
14196 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
14197 
14198 #define CAN_CS_CODE_MASK                         (0xF000000U)
14199 #define CAN_CS_CODE_SHIFT                        (24U)
14200 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
14201  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
14202  */
14203 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
14204 
14205 #define CAN_CS_ESI_MASK                          (0x20000000U)
14206 #define CAN_CS_ESI_SHIFT                         (29U)
14207 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
14208 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
14209 
14210 #define CAN_CS_BRS_MASK                          (0x40000000U)
14211 #define CAN_CS_BRS_SHIFT                         (30U)
14212 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
14213 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
14214 
14215 #define CAN_CS_EDL_MASK                          (0x80000000U)
14216 #define CAN_CS_EDL_SHIFT                         (31U)
14217 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
14218  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
14219  */
14220 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
14221 /*! @} */
14222 
14223 /* The count of CAN_CS */
14224 #define CAN_CS_COUNT_MB64B_H                     (7U)
14225 
14226 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
14227 /*! @{ */
14228 
14229 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
14230 #define CAN_ID_EXT_SHIFT                         (0U)
14231 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
14232 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
14233 
14234 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
14235 #define CAN_ID_STD_SHIFT                         (18U)
14236 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
14237 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
14238 
14239 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
14240 #define CAN_ID_PRIO_SHIFT                        (29U)
14241 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
14242  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
14243  *    ID to define the transmission priority.
14244  */
14245 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
14246 /*! @} */
14247 
14248 /* The count of CAN_ID */
14249 #define CAN_ID_COUNT_MB64B_H                     (7U)
14250 
14251 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
14252 /*! @{ */
14253 
14254 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
14255 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
14256 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
14257 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
14258 
14259 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
14260 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
14261 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
14262 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
14263 
14264 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
14265 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
14266 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
14267 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
14268 
14269 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
14270 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
14271 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
14272 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
14273 
14274 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
14275 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
14276 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
14277 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
14278 
14279 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
14280 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
14281 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
14282 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
14283 
14284 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
14285 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
14286 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
14287 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
14288 
14289 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
14290 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
14291 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
14292 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
14293 
14294 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
14295 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
14296 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
14297 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
14298 
14299 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
14300 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
14301 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
14302 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
14303 
14304 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
14305 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
14306 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
14307 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
14308 
14309 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
14310 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
14311 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
14312 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
14313 
14314 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
14315 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
14316 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
14317 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
14318 
14319 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
14320 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
14321 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
14322 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
14323 
14324 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
14325 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
14326 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
14327 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
14328 
14329 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
14330 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
14331 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
14332 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
14333 
14334 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
14335 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
14336 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
14337 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
14338 
14339 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
14340 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
14341 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
14342 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
14343 
14344 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
14345 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
14346 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
14347 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
14348 
14349 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
14350 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
14351 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
14352 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
14353 
14354 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
14355 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
14356 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
14357 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
14358 
14359 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
14360 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
14361 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
14362 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
14363 
14364 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
14365 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
14366 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
14367 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
14368 
14369 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
14370 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
14371 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
14372 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
14373 
14374 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
14375 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
14376 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
14377 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
14378 
14379 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
14380 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
14381 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
14382 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
14383 
14384 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
14385 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
14386 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
14387 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
14388 
14389 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
14390 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
14391 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
14392 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
14393 
14394 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
14395 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
14396 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
14397 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
14398 
14399 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
14400 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
14401 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
14402 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
14403 
14404 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
14405 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
14406 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
14407 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
14408 
14409 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
14410 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
14411 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
14412 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
14413 
14414 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
14415 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
14416 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
14417 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
14418 
14419 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
14420 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
14421 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
14422 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
14423 
14424 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
14425 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
14426 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
14427 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
14428 
14429 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
14430 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
14431 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
14432 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
14433 
14434 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
14435 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
14436 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
14437 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
14438 
14439 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
14440 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
14441 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
14442 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
14443 
14444 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
14445 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
14446 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
14447 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
14448 
14449 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
14450 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
14451 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
14452 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
14453 
14454 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
14455 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
14456 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
14457 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
14458 
14459 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
14460 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
14461 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
14462 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
14463 
14464 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
14465 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
14466 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
14467 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
14468 
14469 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
14470 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
14471 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
14472 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
14473 
14474 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
14475 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
14476 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
14477 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
14478 
14479 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
14480 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
14481 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
14482 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
14483 
14484 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
14485 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
14486 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
14487 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
14488 
14489 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
14490 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
14491 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
14492 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
14493 
14494 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
14495 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
14496 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
14497 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
14498 
14499 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
14500 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
14501 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
14502 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
14503 
14504 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
14505 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
14506 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
14507 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
14508 
14509 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
14510 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
14511 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
14512 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
14513 
14514 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
14515 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
14516 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
14517 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
14518 
14519 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
14520 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
14521 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
14522 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
14523 
14524 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
14525 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
14526 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
14527 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
14528 
14529 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
14530 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
14531 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
14532 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
14533 
14534 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
14535 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
14536 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
14537 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
14538 
14539 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
14540 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
14541 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
14542 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
14543 
14544 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
14545 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
14546 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
14547 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
14548 
14549 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
14550 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
14551 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
14552 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
14553 
14554 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
14555 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
14556 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
14557 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
14558 
14559 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
14560 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
14561 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
14562 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
14563 
14564 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
14565 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
14566 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
14567 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
14568 
14569 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
14570 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
14571 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
14572 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
14573 /*! @} */
14574 
14575 /* The count of CAN_WORD */
14576 #define CAN_WORD_COUNT_MB64B_H                   (7U)
14577 
14578 /* The count of CAN_WORD */
14579 #define CAN_WORD_COUNT_MB64B_H2                  (16U)
14580 
14581 /* The count of CAN_CS */
14582 #define CAN_CS_COUNT                             (96U)
14583 
14584 /* The count of CAN_ID */
14585 #define CAN_ID_COUNT                             (96U)
14586 
14587 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register */
14588 /*! @{ */
14589 
14590 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
14591 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
14592 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
14593 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
14594 
14595 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
14596 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
14597 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
14598 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
14599 
14600 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
14601 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
14602 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
14603 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
14604 
14605 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
14606 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
14607 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
14608 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
14609 /*! @} */
14610 
14611 /* The count of CAN_WORD0 */
14612 #define CAN_WORD0_COUNT                          (96U)
14613 
14614 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register */
14615 /*! @{ */
14616 
14617 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
14618 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
14619 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
14620 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
14621 
14622 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
14623 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
14624 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
14625 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
14626 
14627 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
14628 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
14629 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
14630 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
14631 
14632 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
14633 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
14634 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
14635 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
14636 /*! @} */
14637 
14638 /* The count of CAN_WORD1 */
14639 #define CAN_WORD1_COUNT                          (96U)
14640 
14641 /*! @name RXIMR - Receive Individual Mask */
14642 /*! @{ */
14643 
14644 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
14645 #define CAN_RXIMR_MI_SHIFT                       (0U)
14646 /*! MI - Individual Mask Bits */
14647 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
14648 /*! @} */
14649 
14650 /* The count of CAN_RXIMR */
14651 #define CAN_RXIMR_COUNT                          (96U)
14652 
14653 /*! @name MECR - Memory Error Control */
14654 /*! @{ */
14655 
14656 #define CAN_MECR_NCEFAFRZ_MASK                   (0x80U)
14657 #define CAN_MECR_NCEFAFRZ_SHIFT                  (7U)
14658 /*! NCEFAFRZ - Noncorrectable Errors in FlexCAN Access Put Chip in Freeze Mode
14659  *  0b0..Normal operation
14660  *  0b1..Freeze mode
14661  */
14662 #define CAN_MECR_NCEFAFRZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
14663 
14664 #define CAN_MECR_ECCDIS_MASK                     (0x100U)
14665 #define CAN_MECR_ECCDIS_SHIFT                    (8U)
14666 /*! ECCDIS - Error Correction Disable
14667  *  0b0..Enable
14668  *  0b1..Disable
14669  */
14670 #define CAN_MECR_ECCDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
14671 
14672 #define CAN_MECR_RERRDIS_MASK                    (0x200U)
14673 #define CAN_MECR_RERRDIS_SHIFT                   (9U)
14674 /*! RERRDIS - Error Report Disable
14675  *  0b0..Enable
14676  *  0b1..Disable
14677  */
14678 #define CAN_MECR_RERRDIS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
14679 
14680 #define CAN_MECR_EXTERRIE_MASK                   (0x2000U)
14681 #define CAN_MECR_EXTERRIE_SHIFT                  (13U)
14682 /*! EXTERRIE - Extended Error Injection Enable
14683  *  0b0..Disable. Apply error injection only to the 32-bit word.
14684  *  0b1..Enable. Apply error injection to the 64-bit word.
14685  */
14686 #define CAN_MECR_EXTERRIE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
14687 
14688 #define CAN_MECR_FAERRIE_MASK                    (0x4000U)
14689 #define CAN_MECR_FAERRIE_SHIFT                   (14U)
14690 /*! FAERRIE - FlexCAN Access Error Injection Enable
14691  *  0b0..Disable
14692  *  0b1..Enable
14693  */
14694 #define CAN_MECR_FAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
14695 
14696 #define CAN_MECR_HAERRIE_MASK                    (0x8000U)
14697 #define CAN_MECR_HAERRIE_SHIFT                   (15U)
14698 /*! HAERRIE - Host Access Error Injection Enable
14699  *  0b0..Disable
14700  *  0b1..Enable
14701  */
14702 #define CAN_MECR_HAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
14703 
14704 #define CAN_MECR_CEI_MSK_MASK                    (0x10000U)
14705 #define CAN_MECR_CEI_MSK_SHIFT                   (16U)
14706 /*! CEI_MSK - Correctable Errors Interrupt Mask
14707  *  0b0..Disable
14708  *  0b1..Enable
14709  */
14710 #define CAN_MECR_CEI_MSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
14711 
14712 #define CAN_MECR_FANCEI_MSK_MASK                 (0x40000U)
14713 #define CAN_MECR_FANCEI_MSK_SHIFT                (18U)
14714 /*! FANCEI_MSK - FlexCAN Access with Noncorrectable Errors Interrupt Mask
14715  *  0b0..Disable
14716  *  0b1..Enable
14717  */
14718 #define CAN_MECR_FANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
14719 
14720 #define CAN_MECR_HANCEI_MSK_MASK                 (0x80000U)
14721 #define CAN_MECR_HANCEI_MSK_SHIFT                (19U)
14722 /*! HANCEI_MSK - Host Access with Noncorrectable Errors Interrupt Mask
14723  *  0b0..Disable
14724  *  0b1..Enable
14725  */
14726 #define CAN_MECR_HANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
14727 
14728 #define CAN_MECR_ECRWRDIS_MASK                   (0x80000000U)
14729 #define CAN_MECR_ECRWRDIS_SHIFT                  (31U)
14730 /*! ECRWRDIS - Error Configuration Register Write Disable
14731  *  0b0..Enable
14732  *  0b1..Disable
14733  */
14734 #define CAN_MECR_ECRWRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
14735 /*! @} */
14736 
14737 /*! @name ERRIAR - Error Injection Address */
14738 /*! @{ */
14739 
14740 #define CAN_ERRIAR_INJADDR_L_MASK                (0x3U)
14741 #define CAN_ERRIAR_INJADDR_L_SHIFT               (0U)
14742 /*! INJADDR_L - Error Injection Address Low */
14743 #define CAN_ERRIAR_INJADDR_L(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
14744 
14745 #define CAN_ERRIAR_INJADDR_H_MASK                (0x3FFCU)
14746 #define CAN_ERRIAR_INJADDR_H_SHIFT               (2U)
14747 /*! INJADDR_H - Error Injection Address High */
14748 #define CAN_ERRIAR_INJADDR_H(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
14749 /*! @} */
14750 
14751 /*! @name ERRIDPR - Error Injection Data Pattern */
14752 /*! @{ */
14753 
14754 #define CAN_ERRIDPR_DFLIP_MASK                   (0xFFFFFFFFU)
14755 #define CAN_ERRIDPR_DFLIP_SHIFT                  (0U)
14756 /*! DFLIP - Data Flip Pattern */
14757 #define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
14758 /*! @} */
14759 
14760 /*! @name ERRIPPR - Error Injection Parity Pattern */
14761 /*! @{ */
14762 
14763 #define CAN_ERRIPPR_PFLIP0_MASK                  (0x1FU)
14764 #define CAN_ERRIPPR_PFLIP0_SHIFT                 (0U)
14765 /*! PFLIP0 - Parity Flip Pattern for Byte 0 (Least Significant) */
14766 #define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
14767 
14768 #define CAN_ERRIPPR_PFLIP1_MASK                  (0x1F00U)
14769 #define CAN_ERRIPPR_PFLIP1_SHIFT                 (8U)
14770 /*! PFLIP1 - Parity Flip Pattern for Byte 1 */
14771 #define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
14772 
14773 #define CAN_ERRIPPR_PFLIP2_MASK                  (0x1F0000U)
14774 #define CAN_ERRIPPR_PFLIP2_SHIFT                 (16U)
14775 /*! PFLIP2 - Parity Flip Pattern for Byte 2 */
14776 #define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
14777 
14778 #define CAN_ERRIPPR_PFLIP3_MASK                  (0x1F000000U)
14779 #define CAN_ERRIPPR_PFLIP3_SHIFT                 (24U)
14780 /*! PFLIP3 - Parity Flip Pattern for Byte 3 (Most Significant) */
14781 #define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
14782 /*! @} */
14783 
14784 /*! @name RERRAR - Error Report Address */
14785 /*! @{ */
14786 
14787 #define CAN_RERRAR_ERRADDR_MASK                  (0x3FFFU)
14788 #define CAN_RERRAR_ERRADDR_SHIFT                 (0U)
14789 /*! ERRADDR - Address Where Error Detected */
14790 #define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
14791 
14792 #define CAN_RERRAR_SAID_MASK                     (0x70000U)
14793 #define CAN_RERRAR_SAID_SHIFT                    (16U)
14794 /*! SAID - SAID */
14795 #define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
14796 
14797 #define CAN_RERRAR_NCE_MASK                      (0x1000000U)
14798 #define CAN_RERRAR_NCE_SHIFT                     (24U)
14799 /*! NCE - Noncorrectable Error
14800  *  0b0..Reporting a correctable error
14801  *  0b1..Reporting a noncorrectable error
14802  */
14803 #define CAN_RERRAR_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
14804 /*! @} */
14805 
14806 /*! @name RERRDR - Error Report Data */
14807 /*! @{ */
14808 
14809 #define CAN_RERRDR_RDATA_MASK                    (0xFFFFFFFFU)
14810 #define CAN_RERRDR_RDATA_SHIFT                   (0U)
14811 /*! RDATA - Raw Data Word Read from Memory with Error */
14812 #define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
14813 /*! @} */
14814 
14815 /*! @name RERRSYNR - Error Report Syndrome */
14816 /*! @{ */
14817 
14818 #define CAN_RERRSYNR_SYND0_MASK                  (0x1FU)
14819 #define CAN_RERRSYNR_SYND0_SHIFT                 (0U)
14820 /*! SYND0 - Error Syndrome for Byte 0 (Least Significant) */
14821 #define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
14822 
14823 #define CAN_RERRSYNR_BE0_MASK                    (0x80U)
14824 #define CAN_RERRSYNR_BE0_SHIFT                   (7U)
14825 /*! BE0 - Byte Enabled for Byte 0 (Least Significant)
14826  *  0b0..Byte was not read.
14827  *  0b1..Byte was read.
14828  */
14829 #define CAN_RERRSYNR_BE0(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
14830 
14831 #define CAN_RERRSYNR_SYND1_MASK                  (0x1F00U)
14832 #define CAN_RERRSYNR_SYND1_SHIFT                 (8U)
14833 /*! SYND1 - Error Syndrome for Byte 1 */
14834 #define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
14835 
14836 #define CAN_RERRSYNR_BE1_MASK                    (0x8000U)
14837 #define CAN_RERRSYNR_BE1_SHIFT                   (15U)
14838 /*! BE1 - Byte Enabled for Byte 1
14839  *  0b0..Byte was not read.
14840  *  0b1..Byte was read.
14841  */
14842 #define CAN_RERRSYNR_BE1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
14843 
14844 #define CAN_RERRSYNR_SYND2_MASK                  (0x1F0000U)
14845 #define CAN_RERRSYNR_SYND2_SHIFT                 (16U)
14846 /*! SYND2 - Error Syndrome for Byte 2 */
14847 #define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
14848 
14849 #define CAN_RERRSYNR_BE2_MASK                    (0x800000U)
14850 #define CAN_RERRSYNR_BE2_SHIFT                   (23U)
14851 /*! BE2 - Byte Enabled for Byte 2
14852  *  0b0..Byte was not read.
14853  *  0b1..Byte was read.
14854  */
14855 #define CAN_RERRSYNR_BE2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
14856 
14857 #define CAN_RERRSYNR_SYND3_MASK                  (0x1F000000U)
14858 #define CAN_RERRSYNR_SYND3_SHIFT                 (24U)
14859 /*! SYND3 - Error Syndrome for Byte 3 (Most Significant) */
14860 #define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
14861 
14862 #define CAN_RERRSYNR_BE3_MASK                    (0x80000000U)
14863 #define CAN_RERRSYNR_BE3_SHIFT                   (31U)
14864 /*! BE3 - Byte Enabled for Byte 3 (Most Significant)
14865  *  0b0..Byte was not read.
14866  *  0b1..Byte was read.
14867  */
14868 #define CAN_RERRSYNR_BE3(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
14869 /*! @} */
14870 
14871 /*! @name ERRSR - Error Status */
14872 /*! @{ */
14873 
14874 #define CAN_ERRSR_CEIOF_MASK                     (0x1U)
14875 #define CAN_ERRSR_CEIOF_SHIFT                    (0U)
14876 /*! CEIOF - Correctable Error Interrupt Overrun Flag
14877  *  0b0..No errors detected
14878  *  0b1..Error detected
14879  */
14880 #define CAN_ERRSR_CEIOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
14881 
14882 #define CAN_ERRSR_FANCEIOF_MASK                  (0x4U)
14883 #define CAN_ERRSR_FANCEIOF_SHIFT                 (2U)
14884 /*! FANCEIOF - FlexCAN Access with Noncorrectable Error Interrupt Overrun Flag
14885  *  0b0..No errors detected
14886  *  0b1..Error detected
14887  */
14888 #define CAN_ERRSR_FANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
14889 
14890 #define CAN_ERRSR_HANCEIOF_MASK                  (0x8U)
14891 #define CAN_ERRSR_HANCEIOF_SHIFT                 (3U)
14892 /*! HANCEIOF - Host Access With Noncorrectable Error Interrupt Overrun Flag
14893  *  0b0..No errors detected
14894  *  0b1..Error detected
14895  */
14896 #define CAN_ERRSR_HANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
14897 
14898 #define CAN_ERRSR_CEIF_MASK                      (0x10000U)
14899 #define CAN_ERRSR_CEIF_SHIFT                     (16U)
14900 /*! CEIF - Correctable Error Interrupt Flag
14901  *  0b0..No errors detected
14902  *  0b1..Error detected
14903  */
14904 #define CAN_ERRSR_CEIF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
14905 
14906 #define CAN_ERRSR_FANCEIF_MASK                   (0x40000U)
14907 #define CAN_ERRSR_FANCEIF_SHIFT                  (18U)
14908 /*! FANCEIF - FlexCAN Access with Noncorrectable Error Interrupt Flag
14909  *  0b0..No errors detected
14910  *  0b1..Error detected
14911  */
14912 #define CAN_ERRSR_FANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
14913 
14914 #define CAN_ERRSR_HANCEIF_MASK                   (0x80000U)
14915 #define CAN_ERRSR_HANCEIF_SHIFT                  (19U)
14916 /*! HANCEIF - Host Access with Noncorrectable Error Interrupt Flag
14917  *  0b0..No errors detected
14918  *  0b1..Error detected
14919  */
14920 #define CAN_ERRSR_HANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
14921 /*! @} */
14922 
14923 /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
14924 /*! @{ */
14925 
14926 #define CAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)
14927 #define CAN_EPRS_ENPRESDIV_SHIFT                 (0U)
14928 /*! ENPRESDIV - Extended Nominal Prescaler Division Factor */
14929 #define CAN_EPRS_ENPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
14930 
14931 #define CAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)
14932 #define CAN_EPRS_EDPRESDIV_SHIFT                 (16U)
14933 /*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */
14934 #define CAN_EPRS_EDPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
14935 /*! @} */
14936 
14937 /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
14938 /*! @{ */
14939 
14940 #define CAN_ENCBT_NTSEG1_MASK                    (0xFFU)
14941 #define CAN_ENCBT_NTSEG1_SHIFT                   (0U)
14942 /*! NTSEG1 - Nominal Time Segment 1 */
14943 #define CAN_ENCBT_NTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
14944 
14945 #define CAN_ENCBT_NTSEG2_MASK                    (0x7F000U)
14946 #define CAN_ENCBT_NTSEG2_SHIFT                   (12U)
14947 /*! NTSEG2 - Nominal Time Segment 2 */
14948 #define CAN_ENCBT_NTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
14949 
14950 #define CAN_ENCBT_NRJW_MASK                      (0x1FC00000U)
14951 #define CAN_ENCBT_NRJW_SHIFT                     (22U)
14952 /*! NRJW - Nominal Resynchronization Jump Width */
14953 #define CAN_ENCBT_NRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
14954 /*! @} */
14955 
14956 /*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */
14957 /*! @{ */
14958 
14959 #define CAN_EDCBT_DTSEG1_MASK                    (0x1FU)
14960 #define CAN_EDCBT_DTSEG1_SHIFT                   (0U)
14961 /*! DTSEG1 - Data Phase Segment 1 */
14962 #define CAN_EDCBT_DTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
14963 
14964 #define CAN_EDCBT_DTSEG2_MASK                    (0xF000U)
14965 #define CAN_EDCBT_DTSEG2_SHIFT                   (12U)
14966 /*! DTSEG2 - Data Phase Time Segment 2 */
14967 #define CAN_EDCBT_DTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
14968 
14969 #define CAN_EDCBT_DRJW_MASK                      (0x3C00000U)
14970 #define CAN_EDCBT_DRJW_SHIFT                     (22U)
14971 /*! DRJW - Data Phase Resynchronization Jump Width */
14972 #define CAN_EDCBT_DRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
14973 /*! @} */
14974 
14975 /*! @name ETDC - Enhanced Transceiver Delay Compensation */
14976 /*! @{ */
14977 
14978 #define CAN_ETDC_ETDCVAL_MASK                    (0xFFU)
14979 #define CAN_ETDC_ETDCVAL_SHIFT                   (0U)
14980 /*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */
14981 #define CAN_ETDC_ETDCVAL(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
14982 
14983 #define CAN_ETDC_ETDCFAIL_MASK                   (0x8000U)
14984 #define CAN_ETDC_ETDCFAIL_SHIFT                  (15U)
14985 /*! ETDCFAIL - Transceiver Delay Compensation Fail
14986  *  0b0..In range
14987  *  0b1..Out of range
14988  */
14989 #define CAN_ETDC_ETDCFAIL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK)
14990 
14991 #define CAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)
14992 #define CAN_ETDC_ETDCOFF_SHIFT                   (16U)
14993 /*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */
14994 #define CAN_ETDC_ETDCOFF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
14995 
14996 #define CAN_ETDC_TDMDIS_MASK                     (0x40000000U)
14997 #define CAN_ETDC_TDMDIS_SHIFT                    (30U)
14998 /*! TDMDIS - Transceiver Delay Measurement Disable
14999  *  0b0..Enable
15000  *  0b1..Disable
15001  */
15002 #define CAN_ETDC_TDMDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
15003 
15004 #define CAN_ETDC_ETDCEN_MASK                     (0x80000000U)
15005 #define CAN_ETDC_ETDCEN_SHIFT                    (31U)
15006 /*! ETDCEN - Transceiver Delay Compensation Enable
15007  *  0b0..Disable
15008  *  0b1..Enable
15009  */
15010 #define CAN_ETDC_ETDCEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK)
15011 /*! @} */
15012 
15013 /*! @name FDCTRL - CAN FD Control */
15014 /*! @{ */
15015 
15016 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
15017 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
15018 /*! TDCVAL - Transceiver Delay Compensation Value */
15019 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
15020 
15021 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
15022 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
15023 /*! TDCOFF - Transceiver Delay Compensation Offset */
15024 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
15025 
15026 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
15027 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
15028 /*! TDCFAIL - Transceiver Delay Compensation Fail
15029  *  0b0..In range
15030  *  0b1..Out of range
15031  */
15032 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
15033 
15034 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
15035 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
15036 /*! TDCEN - Transceiver Delay Compensation Enable
15037  *  0b0..Disable
15038  *  0b1..Enable
15039  */
15040 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
15041 
15042 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
15043 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
15044 /*! MBDSR0 - Message Buffer Data Size for Region 0
15045  *  0b00..8 bytes
15046  *  0b01..16 bytes
15047  *  0b10..32 bytes
15048  *  0b11..64 bytes
15049  */
15050 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
15051 
15052 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
15053 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
15054 /*! MBDSR1 - Message Buffer Data Size for Region 1
15055  *  0b00..8 bytes
15056  *  0b01..16 bytes
15057  *  0b10..32 bytes
15058  *  0b11..64 bytes
15059  */
15060 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
15061 
15062 #define CAN_FDCTRL_MBDSR2_MASK                   (0xC00000U)
15063 #define CAN_FDCTRL_MBDSR2_SHIFT                  (22U)
15064 /*! MBDSR2 - Message Buffer Data Size for Region 2
15065  *  0b00..8 bytes
15066  *  0b01..16 bytes
15067  *  0b10..32 bytes
15068  *  0b11..64 bytes
15069  */
15070 #define CAN_FDCTRL_MBDSR2(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR2_SHIFT)) & CAN_FDCTRL_MBDSR2_MASK)
15071 
15072 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
15073 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
15074 /*! FDRATE - Bit Rate Switch Enable
15075  *  0b0..Disable
15076  *  0b1..Enable
15077  */
15078 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
15079 /*! @} */
15080 
15081 /*! @name FDCBT - CAN FD Bit Timing */
15082 /*! @{ */
15083 
15084 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
15085 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
15086 /*! FPSEG2 - Fast Phase Segment 2 */
15087 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
15088 
15089 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
15090 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
15091 /*! FPSEG1 - Fast Phase Segment 1 */
15092 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
15093 
15094 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
15095 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
15096 /*! FPROPSEG - Fast Propagation Segment */
15097 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
15098 
15099 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
15100 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
15101 /*! FRJW - Fast Resync Jump Width */
15102 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
15103 
15104 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
15105 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
15106 /*! FPRESDIV - Fast Prescaler Division Factor */
15107 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
15108 /*! @} */
15109 
15110 /*! @name FDCRC - CAN FD CRC */
15111 /*! @{ */
15112 
15113 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
15114 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
15115 /*! FD_TXCRC - Extended Transmitted CRC value */
15116 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
15117 
15118 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
15119 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
15120 /*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */
15121 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
15122 /*! @} */
15123 
15124 /*! @name ERFCR - Enhanced RX FIFO Control */
15125 /*! @{ */
15126 
15127 #define CAN_ERFCR_ERFWM_MASK                     (0x1FU)
15128 #define CAN_ERFCR_ERFWM_SHIFT                    (0U)
15129 /*! ERFWM - Enhanced RX FIFO Watermark */
15130 #define CAN_ERFCR_ERFWM(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
15131 
15132 #define CAN_ERFCR_NFE_MASK                       (0x3F00U)
15133 #define CAN_ERFCR_NFE_SHIFT                      (8U)
15134 /*! NFE - Number of Enhanced RX FIFO Filter Elements */
15135 #define CAN_ERFCR_NFE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
15136 
15137 #define CAN_ERFCR_NEXIF_MASK                     (0x7F0000U)
15138 #define CAN_ERFCR_NEXIF_SHIFT                    (16U)
15139 /*! NEXIF - Number of Extended ID Filter Elements */
15140 #define CAN_ERFCR_NEXIF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
15141 
15142 #define CAN_ERFCR_DMALW_MASK                     (0x7C000000U)
15143 #define CAN_ERFCR_DMALW_SHIFT                    (26U)
15144 /*! DMALW - DMA Last Word */
15145 #define CAN_ERFCR_DMALW(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
15146 
15147 #define CAN_ERFCR_ERFEN_MASK                     (0x80000000U)
15148 #define CAN_ERFCR_ERFEN_SHIFT                    (31U)
15149 /*! ERFEN - Enhanced RX FIFO enable
15150  *  0b0..Disable
15151  *  0b1..Enable
15152  */
15153 #define CAN_ERFCR_ERFEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
15154 /*! @} */
15155 
15156 /*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */
15157 /*! @{ */
15158 
15159 #define CAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)
15160 #define CAN_ERFIER_ERFDAIE_SHIFT                 (28U)
15161 /*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable
15162  *  0b0..Disable
15163  *  0b1..Enable
15164  */
15165 #define CAN_ERFIER_ERFDAIE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
15166 
15167 #define CAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)
15168 #define CAN_ERFIER_ERFWMIIE_SHIFT                (29U)
15169 /*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable
15170  *  0b0..Disable
15171  *  0b1..Enable
15172  */
15173 #define CAN_ERFIER_ERFWMIIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
15174 
15175 #define CAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)
15176 #define CAN_ERFIER_ERFOVFIE_SHIFT                (30U)
15177 /*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable
15178  *  0b0..Disable
15179  *  0b1..Enable
15180  */
15181 #define CAN_ERFIER_ERFOVFIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
15182 
15183 #define CAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)
15184 #define CAN_ERFIER_ERFUFWIE_SHIFT                (31U)
15185 /*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable
15186  *  0b0..Disable
15187  *  0b1..Enable
15188  */
15189 #define CAN_ERFIER_ERFUFWIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
15190 /*! @} */
15191 
15192 /*! @name ERFSR - Enhanced RX FIFO Status */
15193 /*! @{ */
15194 
15195 #define CAN_ERFSR_ERFEL_MASK                     (0x3FU)
15196 #define CAN_ERFSR_ERFEL_SHIFT                    (0U)
15197 /*! ERFEL - Enhanced RX FIFO Elements */
15198 #define CAN_ERFSR_ERFEL(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
15199 
15200 #define CAN_ERFSR_ERFF_MASK                      (0x10000U)
15201 #define CAN_ERFSR_ERFF_SHIFT                     (16U)
15202 /*! ERFF - Enhanced RX FIFO Full Flag
15203  *  0b0..Not full
15204  *  0b1..Full
15205  */
15206 #define CAN_ERFSR_ERFF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
15207 
15208 #define CAN_ERFSR_ERFE_MASK                      (0x20000U)
15209 #define CAN_ERFSR_ERFE_SHIFT                     (17U)
15210 /*! ERFE - Enhanced RX FIFO Empty Flag
15211  *  0b0..Not empty
15212  *  0b1..Empty
15213  */
15214 #define CAN_ERFSR_ERFE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
15215 
15216 #define CAN_ERFSR_ERFCLR_MASK                    (0x8000000U)
15217 #define CAN_ERFSR_ERFCLR_SHIFT                   (27U)
15218 /*! ERFCLR - Enhanced RX FIFO Clear
15219  *  0b0..No effect
15220  *  0b1..Clear enhanced RX FIFO content
15221  */
15222 #define CAN_ERFSR_ERFCLR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
15223 
15224 #define CAN_ERFSR_ERFDA_MASK                     (0x10000000U)
15225 #define CAN_ERFSR_ERFDA_SHIFT                    (28U)
15226 /*! ERFDA - Enhanced RX FIFO Data Available Flag
15227  *  0b0..No such occurrence
15228  *  0b1..At least one message stored in Enhanced RX FIFO
15229  */
15230 #define CAN_ERFSR_ERFDA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
15231 
15232 #define CAN_ERFSR_ERFWMI_MASK                    (0x20000000U)
15233 #define CAN_ERFSR_ERFWMI_SHIFT                   (29U)
15234 /*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag
15235  *  0b0..No such occurrence
15236  *  0b1..Number of messages in FIFO is greater than the watermark
15237  */
15238 #define CAN_ERFSR_ERFWMI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
15239 
15240 #define CAN_ERFSR_ERFOVF_MASK                    (0x40000000U)
15241 #define CAN_ERFSR_ERFOVF_SHIFT                   (30U)
15242 /*! ERFOVF - Enhanced RX FIFO Overflow Flag
15243  *  0b0..No such occurrence
15244  *  0b1..Overflow
15245  */
15246 #define CAN_ERFSR_ERFOVF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
15247 
15248 #define CAN_ERFSR_ERFUFW_MASK                    (0x80000000U)
15249 #define CAN_ERFSR_ERFUFW_SHIFT                   (31U)
15250 /*! ERFUFW - Enhanced RX FIFO Underflow Flag
15251  *  0b0..No such occurrence
15252  *  0b1..Underflow
15253  */
15254 #define CAN_ERFSR_ERFUFW(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
15255 /*! @} */
15256 
15257 /*! @name HR_TIME_STAMP - High-Resolution Timestamp */
15258 /*! @{ */
15259 
15260 #define CAN_HR_TIME_STAMP_TS_MASK                (0xFFFFFFFFU)
15261 #define CAN_HR_TIME_STAMP_TS_SHIFT               (0U)
15262 /*! TS - High-Resolution Timestamp */
15263 #define CAN_HR_TIME_STAMP_TS(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
15264 /*! @} */
15265 
15266 /* The count of CAN_HR_TIME_STAMP */
15267 #define CAN_HR_TIME_STAMP_COUNT                  (96U)
15268 
15269 /*! @name ERFFEL - Enhanced RX FIFO Filter Element */
15270 /*! @{ */
15271 
15272 #define CAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)
15273 #define CAN_ERFFEL_FEL_SHIFT                     (0U)
15274 /*! FEL - Filter Element Bits */
15275 #define CAN_ERFFEL_FEL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
15276 /*! @} */
15277 
15278 /* The count of CAN_ERFFEL */
15279 #define CAN_ERFFEL_COUNT                         (128U)
15280 
15281 
15282 /*!
15283  * @}
15284  */ /* end of group CAN_Register_Masks */
15285 
15286 
15287 /* CAN - Peripheral instance base addresses */
15288 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
15289   /** Peripheral CAN1 base address */
15290   #define CAN1_BASE                                (0x543A0000u)
15291   /** Peripheral CAN1 base address */
15292   #define CAN1_BASE_NS                             (0x443A0000u)
15293   /** Peripheral CAN1 base pointer */
15294   #define CAN1                                     ((CAN_Type *)CAN1_BASE)
15295   /** Peripheral CAN1 base pointer */
15296   #define CAN1_NS                                  ((CAN_Type *)CAN1_BASE_NS)
15297   /** Peripheral CAN2 base address */
15298   #define CAN2_BASE                                (0x525B0000u)
15299   /** Peripheral CAN2 base address */
15300   #define CAN2_BASE_NS                             (0x425B0000u)
15301   /** Peripheral CAN2 base pointer */
15302   #define CAN2                                     ((CAN_Type *)CAN2_BASE)
15303   /** Peripheral CAN2 base pointer */
15304   #define CAN2_NS                                  ((CAN_Type *)CAN2_BASE_NS)
15305   /** Array initializer of CAN peripheral base addresses */
15306   #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE }
15307   /** Array initializer of CAN peripheral base pointers */
15308   #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2 }
15309   /** Array initializer of CAN peripheral base addresses */
15310   #define CAN_BASE_ADDRS_NS                        { 0u, CAN1_BASE_NS, CAN2_BASE_NS }
15311   /** Array initializer of CAN peripheral base pointers */
15312   #define CAN_BASE_PTRS_NS                         { (CAN_Type *)0u, CAN1_NS, CAN2_NS }
15313 #else
15314   /** Peripheral CAN1 base address */
15315   #define CAN1_BASE                                (0x443A0000u)
15316   /** Peripheral CAN1 base pointer */
15317   #define CAN1                                     ((CAN_Type *)CAN1_BASE)
15318   /** Peripheral CAN2 base address */
15319   #define CAN2_BASE                                (0x425B0000u)
15320   /** Peripheral CAN2 base pointer */
15321   #define CAN2                                     ((CAN_Type *)CAN2_BASE)
15322   /** Array initializer of CAN peripheral base addresses */
15323   #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE }
15324   /** Array initializer of CAN peripheral base pointers */
15325   #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2 }
15326 #endif
15327 /** Interrupt vectors for the CAN peripheral type */
15328 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15329 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15330 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15331 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15332 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15333 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
15334 
15335 /*!
15336  * @}
15337  */ /* end of group CAN_Peripheral_Access_Layer */
15338 
15339 
15340 /* ----------------------------------------------------------------------------
15341    -- CCM Peripheral Access Layer
15342    ---------------------------------------------------------------------------- */
15343 
15344 /*!
15345  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
15346  * @{
15347  */
15348 
15349 /** CCM - Register Layout Typedef */
15350 typedef struct {
15351   struct {                                         /* offset: 0x0, array step: 0x80 */
15352     __IO uint32_t CONTROL;                           /**< Clock Root Control Register, array offset: 0x0, array step: 0x80 */
15353     __IO uint32_t CONTROL_SET;                       /**< Clock Root Control Register, array offset: 0x4, array step: 0x80 */
15354     __IO uint32_t CONTROL_CLR;                       /**< Clock Root Control Register, array offset: 0x8, array step: 0x80 */
15355     __IO uint32_t CONTROL_TOG;                       /**< Clock Root Control Register, array offset: 0xC, array step: 0x80 */
15356          uint8_t RESERVED_0[16];
15357     __I  uint32_t STATUS0;                           /**< Clock root working status, array offset: 0x20, array step: 0x80 */
15358          uint8_t RESERVED_1[12];
15359     __IO uint32_t AUTHEN;                            /**< Clock root access control, array offset: 0x30, array step: 0x80 */
15360          uint8_t RESERVED_2[76];
15361   } CLOCK_ROOT[74];
15362        uint8_t RESERVED_0[7936];
15363   struct {                                         /* offset: 0x4400, array step: 0x80 */
15364     __IO uint32_t CONTROL;                           /**< Observe control, array offset: 0x4400, array step: 0x80 */
15365     __IO uint32_t CONTROL_SET;                       /**< Observe control, array offset: 0x4404, array step: 0x80 */
15366     __IO uint32_t CONTROL_CLR;                       /**< Observe control, array offset: 0x4408, array step: 0x80 */
15367     __IO uint32_t CONTROL_TOG;                       /**< Observe control, array offset: 0x440C, array step: 0x80 */
15368          uint8_t RESERVED_0[16];
15369     __I  uint32_t STATUS;                            /**< Observe status, array offset: 0x4420, array step: 0x80 */
15370          uint8_t RESERVED_1[12];
15371     __IO uint32_t AUTHEN;                            /**< Observe access control, array offset: 0x4430, array step: 0x80 */
15372     __IO uint32_t AUTHEN_SET;                        /**< Observe access control, array offset: 0x4434, array step: 0x80 */
15373     __IO uint32_t AUTHEN_CLR;                        /**< Observe access control, array offset: 0x4438, array step: 0x80 */
15374     __IO uint32_t AUTHEN_TOG;                        /**< Observe access control, array offset: 0x443C, array step: 0x80 */
15375     __I  uint32_t FREQUENCY_CURRENT;                 /**< Current frequency detected, array offset: 0x4440, array step: 0x80 */
15376     __I  uint32_t FREQUENCY_MIN;                     /**< Minimum frequency detected, array offset: 0x4444, array step: 0x80 */
15377     __I  uint32_t FREQUENCY_MAX;                     /**< Maximum frequency detected, array offset: 0x4448, array step: 0x80 */
15378          uint8_t RESERVED_2[4];
15379     __I  uint32_t PERIOD_CURRENT;                    /**< Current period time detected, array offset: 0x4450, array step: 0x80 */
15380     __I  uint32_t PERIOD_MIN;                        /**< Minimum period time detected, array offset: 0x4454, array step: 0x80 */
15381     __I  uint32_t PERIOD_MAX;                        /**< Maximum period time detected, array offset: 0x4458, array step: 0x80 */
15382          uint8_t RESERVED_3[4];
15383     __I  uint32_t HIGH_CURRENT;                      /**< Current high level time detected, array offset: 0x4460, array step: 0x80 */
15384     __I  uint32_t HIGH_MIN;                          /**< Minimum high level time detected, array offset: 0x4464, array step: 0x80 */
15385     __I  uint32_t HIGH_MAX;                          /**< Maximum high level time detected, array offset: 0x4468, array step: 0x80 */
15386          uint8_t RESERVED_4[4];
15387     __I  uint32_t LOW_CURRENT;                       /**< Current high level time detected, array offset: 0x4470, array step: 0x80 */
15388     __I  uint32_t LOW_MIN;                           /**< Minimum high level time detected, array offset: 0x4474, array step: 0x80 */
15389     __I  uint32_t LOW_MAX;                           /**< Maximum high level time detected, array offset: 0x4478, array step: 0x80 */
15390          uint8_t RESERVED_5[4];
15391   } OBSERVE[2];
15392        uint8_t RESERVED_1[768];
15393        uint32_t GPR_SHARED0;                       /**< General Purpose Register, offset: 0x4800 */
15394        uint32_t GPR_SHARED0_SET;                   /**< General Purpose Register, offset: 0x4804 */
15395        uint32_t GPR_SHARED0_CLR;                   /**< General Purpose Register, offset: 0x4808 */
15396        uint32_t GPR_SHARED0_TOG;                   /**< General Purpose Register, offset: 0x480C */
15397   __IO uint32_t GPR_SHARED0_AUTHEN;                /**< GPR access control, offset: 0x4810 */
15398   __IO uint32_t GPR_SHARED0_AUTHEN_SET;            /**< GPR access control, offset: 0x4814 */
15399   __IO uint32_t GPR_SHARED0_AUTHEN_CLR;            /**< GPR access control, offset: 0x4818 */
15400   __IO uint32_t GPR_SHARED0_AUTHEN_TOG;            /**< GPR access control, offset: 0x481C */
15401        uint32_t GPR_SHARED1;                       /**< General Purpose Register, offset: 0x4820 */
15402        uint32_t GPR_SHARED1_SET;                   /**< General Purpose Register, offset: 0x4824 */
15403        uint32_t GPR_SHARED1_CLR;                   /**< General Purpose Register, offset: 0x4828 */
15404        uint32_t GPR_SHARED1_TOG;                   /**< General Purpose Register, offset: 0x482C */
15405   __IO uint32_t GPR_SHARED1_AUTHEN;                /**< GPR access control, offset: 0x4830 */
15406   __IO uint32_t GPR_SHARED1_AUTHEN_SET;            /**< GPR access control, offset: 0x4834 */
15407   __IO uint32_t GPR_SHARED1_AUTHEN_CLR;            /**< GPR access control, offset: 0x4838 */
15408   __IO uint32_t GPR_SHARED1_AUTHEN_TOG;            /**< GPR access control, offset: 0x483C */
15409   __IO uint32_t GPR_SHARED2;                       /**< General Purpose Register, offset: 0x4840 */
15410   __IO uint32_t GPR_SHARED2_SET;                   /**< General Purpose Register, offset: 0x4844 */
15411   __IO uint32_t GPR_SHARED2_CLR;                   /**< General Purpose Register, offset: 0x4848 */
15412   __IO uint32_t GPR_SHARED2_TOG;                   /**< General Purpose Register, offset: 0x484C */
15413   __IO uint32_t GPR_SHARED2_AUTHEN;                /**< GPR access control, offset: 0x4850 */
15414   __IO uint32_t GPR_SHARED2_AUTHEN_SET;            /**< GPR access control, offset: 0x4854 */
15415   __IO uint32_t GPR_SHARED2_AUTHEN_CLR;            /**< GPR access control, offset: 0x4858 */
15416   __IO uint32_t GPR_SHARED2_AUTHEN_TOG;            /**< GPR access control, offset: 0x485C */
15417   __IO uint32_t GPR_SHARED3;                       /**< General Purpose Register, offset: 0x4860 */
15418   __IO uint32_t GPR_SHARED3_SET;                   /**< General Purpose Register, offset: 0x4864 */
15419   __IO uint32_t GPR_SHARED3_CLR;                   /**< General Purpose Register, offset: 0x4868 */
15420   __IO uint32_t GPR_SHARED3_TOG;                   /**< General Purpose Register, offset: 0x486C */
15421   __IO uint32_t GPR_SHARED3_AUTHEN;                /**< GPR access control, offset: 0x4870 */
15422   __IO uint32_t GPR_SHARED3_AUTHEN_SET;            /**< GPR access control, offset: 0x4874 */
15423   __IO uint32_t GPR_SHARED3_AUTHEN_CLR;            /**< GPR access control, offset: 0x4878 */
15424   __IO uint32_t GPR_SHARED3_AUTHEN_TOG;            /**< GPR access control, offset: 0x487C */
15425   __IO uint32_t GPR_SHARED4;                       /**< General Purpose Register, offset: 0x4880 */
15426   __IO uint32_t GPR_SHARED4_SET;                   /**< General Purpose Register, offset: 0x4884 */
15427   __IO uint32_t GPR_SHARED4_CLR;                   /**< General Purpose Register, offset: 0x4888 */
15428   __IO uint32_t GPR_SHARED4_TOG;                   /**< General Purpose Register, offset: 0x488C */
15429   __IO uint32_t GPR_SHARED4_AUTHEN;                /**< GPR access control, offset: 0x4890 */
15430   __IO uint32_t GPR_SHARED4_AUTHEN_SET;            /**< GPR access control, offset: 0x4894 */
15431   __IO uint32_t GPR_SHARED4_AUTHEN_CLR;            /**< GPR access control, offset: 0x4898 */
15432   __IO uint32_t GPR_SHARED4_AUTHEN_TOG;            /**< GPR access control, offset: 0x489C */
15433   __IO uint32_t GPR_SHARED5;                       /**< General Purpose Register, offset: 0x48A0 */
15434   __IO uint32_t GPR_SHARED5_SET;                   /**< General Purpose Register, offset: 0x48A4 */
15435   __IO uint32_t GPR_SHARED5_CLR;                   /**< General Purpose Register, offset: 0x48A8 */
15436   __IO uint32_t GPR_SHARED5_TOG;                   /**< General Purpose Register, offset: 0x48AC */
15437   __IO uint32_t GPR_SHARED5_AUTHEN;                /**< GPR access control, offset: 0x48B0 */
15438   __IO uint32_t GPR_SHARED5_AUTHEN_SET;            /**< GPR access control, offset: 0x48B4 */
15439   __IO uint32_t GPR_SHARED5_AUTHEN_CLR;            /**< GPR access control, offset: 0x48B8 */
15440   __IO uint32_t GPR_SHARED5_AUTHEN_TOG;            /**< GPR access control, offset: 0x48BC */
15441   __IO uint32_t GPR_SHARED6;                       /**< General Purpose Register, offset: 0x48C0 */
15442   __IO uint32_t GPR_SHARED6_SET;                   /**< General Purpose Register, offset: 0x48C4 */
15443   __IO uint32_t GPR_SHARED6_CLR;                   /**< General Purpose Register, offset: 0x48C8 */
15444   __IO uint32_t GPR_SHARED6_TOG;                   /**< General Purpose Register, offset: 0x48CC */
15445   __IO uint32_t GPR_SHARED6_AUTHEN;                /**< GPR access control, offset: 0x48D0 */
15446   __IO uint32_t GPR_SHARED6_AUTHEN_SET;            /**< GPR access control, offset: 0x48D4 */
15447   __IO uint32_t GPR_SHARED6_AUTHEN_CLR;            /**< GPR access control, offset: 0x48D8 */
15448   __IO uint32_t GPR_SHARED6_AUTHEN_TOG;            /**< GPR access control, offset: 0x48DC */
15449   __IO uint32_t GPR_SHARED7;                       /**< General Purpose Register, offset: 0x48E0 */
15450   __IO uint32_t GPR_SHARED7_SET;                   /**< General Purpose Register, offset: 0x48E4 */
15451   __IO uint32_t GPR_SHARED7_CLR;                   /**< General Purpose Register, offset: 0x48E8 */
15452   __IO uint32_t GPR_SHARED7_TOG;                   /**< General Purpose Register, offset: 0x48EC */
15453   __IO uint32_t GPR_SHARED7_AUTHEN;                /**< GPR access control, offset: 0x48F0 */
15454   __IO uint32_t GPR_SHARED7_AUTHEN_SET;            /**< GPR access control, offset: 0x48F4 */
15455   __IO uint32_t GPR_SHARED7_AUTHEN_CLR;            /**< GPR access control, offset: 0x48F8 */
15456   __IO uint32_t GPR_SHARED7_AUTHEN_TOG;            /**< GPR access control, offset: 0x48FC */
15457   __IO uint32_t GPR_SHARED8;                       /**< General Purpose Register, offset: 0x4900 */
15458   __IO uint32_t GPR_SHARED8_SET;                   /**< General Purpose Register, offset: 0x4904 */
15459   __IO uint32_t GPR_SHARED8_CLR;                   /**< General Purpose Register, offset: 0x4908 */
15460   __IO uint32_t GPR_SHARED8_TOG;                   /**< General Purpose Register, offset: 0x490C */
15461   __IO uint32_t GPR_SHARED8_AUTHEN;                /**< GPR access control, offset: 0x4910 */
15462   __IO uint32_t GPR_SHARED8_AUTHEN_SET;            /**< GPR access control, offset: 0x4914 */
15463   __IO uint32_t GPR_SHARED8_AUTHEN_CLR;            /**< GPR access control, offset: 0x4918 */
15464   __IO uint32_t GPR_SHARED8_AUTHEN_TOG;            /**< GPR access control, offset: 0x491C */
15465   __IO uint32_t GPR_SHARED9;                       /**< General Purpose Register, offset: 0x4920 */
15466   __IO uint32_t GPR_SHARED9_SET;                   /**< General Purpose Register, offset: 0x4924 */
15467   __IO uint32_t GPR_SHARED9_CLR;                   /**< General Purpose Register, offset: 0x4928 */
15468   __IO uint32_t GPR_SHARED9_TOG;                   /**< General Purpose Register, offset: 0x492C */
15469   __IO uint32_t GPR_SHARED9_AUTHEN;                /**< GPR access control, offset: 0x4930 */
15470   __IO uint32_t GPR_SHARED9_AUTHEN_SET;            /**< GPR access control, offset: 0x4934 */
15471   __IO uint32_t GPR_SHARED9_AUTHEN_CLR;            /**< GPR access control, offset: 0x4938 */
15472   __IO uint32_t GPR_SHARED9_AUTHEN_TOG;            /**< GPR access control, offset: 0x493C */
15473   __IO uint32_t GPR_SHARED10;                      /**< General Purpose Register, offset: 0x4940 */
15474   __IO uint32_t GPR_SHARED10_SET;                  /**< General Purpose Register, offset: 0x4944 */
15475   __IO uint32_t GPR_SHARED10_CLR;                  /**< General Purpose Register, offset: 0x4948 */
15476   __IO uint32_t GPR_SHARED10_TOG;                  /**< General Purpose Register, offset: 0x494C */
15477   __IO uint32_t GPR_SHARED10_AUTHEN;               /**< GPR access control, offset: 0x4950 */
15478   __IO uint32_t GPR_SHARED10_AUTHEN_SET;           /**< GPR access control, offset: 0x4954 */
15479   __IO uint32_t GPR_SHARED10_AUTHEN_CLR;           /**< GPR access control, offset: 0x4958 */
15480   __IO uint32_t GPR_SHARED10_AUTHEN_TOG;           /**< GPR access control, offset: 0x495C */
15481   __IO uint32_t GPR_SHARED11;                      /**< General Purpose Register, offset: 0x4960 */
15482   __IO uint32_t GPR_SHARED11_SET;                  /**< General Purpose Register, offset: 0x4964 */
15483   __IO uint32_t GPR_SHARED11_CLR;                  /**< General Purpose Register, offset: 0x4968 */
15484   __IO uint32_t GPR_SHARED11_TOG;                  /**< General Purpose Register, offset: 0x496C */
15485   __IO uint32_t GPR_SHARED11_AUTHEN;               /**< GPR access control, offset: 0x4970 */
15486   __IO uint32_t GPR_SHARED11_AUTHEN_SET;           /**< GPR access control, offset: 0x4974 */
15487   __IO uint32_t GPR_SHARED11_AUTHEN_CLR;           /**< GPR access control, offset: 0x4978 */
15488   __IO uint32_t GPR_SHARED11_AUTHEN_TOG;           /**< GPR access control, offset: 0x497C */
15489   __IO uint32_t GPR_SHARED12;                      /**< General Purpose Register, offset: 0x4980 */
15490   __IO uint32_t GPR_SHARED12_SET;                  /**< General Purpose Register, offset: 0x4984 */
15491   __IO uint32_t GPR_SHARED12_CLR;                  /**< General Purpose Register, offset: 0x4988 */
15492   __IO uint32_t GPR_SHARED12_TOG;                  /**< General Purpose Register, offset: 0x498C */
15493   __IO uint32_t GPR_SHARED12_AUTHEN;               /**< GPR access control, offset: 0x4990 */
15494   __IO uint32_t GPR_SHARED12_AUTHEN_SET;           /**< GPR access control, offset: 0x4994 */
15495   __IO uint32_t GPR_SHARED12_AUTHEN_CLR;           /**< GPR access control, offset: 0x4998 */
15496   __IO uint32_t GPR_SHARED12_AUTHEN_TOG;           /**< GPR access control, offset: 0x499C */
15497   __IO uint32_t GPR_SHARED13;                      /**< General Purpose Register, offset: 0x49A0 */
15498   __IO uint32_t GPR_SHARED13_SET;                  /**< General Purpose Register, offset: 0x49A4 */
15499   __IO uint32_t GPR_SHARED13_CLR;                  /**< General Purpose Register, offset: 0x49A8 */
15500   __IO uint32_t GPR_SHARED13_TOG;                  /**< General Purpose Register, offset: 0x49AC */
15501   __IO uint32_t GPR_SHARED13_AUTHEN;               /**< GPR access control, offset: 0x49B0 */
15502   __IO uint32_t GPR_SHARED13_AUTHEN_SET;           /**< GPR access control, offset: 0x49B4 */
15503   __IO uint32_t GPR_SHARED13_AUTHEN_CLR;           /**< GPR access control, offset: 0x49B8 */
15504   __IO uint32_t GPR_SHARED13_AUTHEN_TOG;           /**< GPR access control, offset: 0x49BC */
15505   __IO uint32_t GPR_SHARED14;                      /**< General Purpose Register, offset: 0x49C0 */
15506   __IO uint32_t GPR_SHARED14_SET;                  /**< General Purpose Register, offset: 0x49C4 */
15507   __IO uint32_t GPR_SHARED14_CLR;                  /**< General Purpose Register, offset: 0x49C8 */
15508   __IO uint32_t GPR_SHARED14_TOG;                  /**< General Purpose Register, offset: 0x49CC */
15509   __IO uint32_t GPR_SHARED14_AUTHEN;               /**< GPR access control, offset: 0x49D0 */
15510   __IO uint32_t GPR_SHARED14_AUTHEN_SET;           /**< GPR access control, offset: 0x49D4 */
15511   __IO uint32_t GPR_SHARED14_AUTHEN_CLR;           /**< GPR access control, offset: 0x49D8 */
15512   __IO uint32_t GPR_SHARED14_AUTHEN_TOG;           /**< GPR access control, offset: 0x49DC */
15513   __IO uint32_t GPR_SHARED15;                      /**< General Purpose Register, offset: 0x49E0 */
15514   __IO uint32_t GPR_SHARED15_SET;                  /**< General Purpose Register, offset: 0x49E4 */
15515   __IO uint32_t GPR_SHARED15_CLR;                  /**< General Purpose Register, offset: 0x49E8 */
15516   __IO uint32_t GPR_SHARED15_TOG;                  /**< General Purpose Register, offset: 0x49EC */
15517   __IO uint32_t GPR_SHARED15_AUTHEN;               /**< GPR access control, offset: 0x49F0 */
15518   __IO uint32_t GPR_SHARED15_AUTHEN_SET;           /**< GPR access control, offset: 0x49F4 */
15519   __IO uint32_t GPR_SHARED15_AUTHEN_CLR;           /**< GPR access control, offset: 0x49F8 */
15520   __IO uint32_t GPR_SHARED15_AUTHEN_TOG;           /**< GPR access control, offset: 0x49FC */
15521   __I  uint32_t GPR_SHARED_STATUS[8];              /**< General purpose status register for CM33..General purpose status register for CM7, array offset: 0x4A00, array step: 0x4 */
15522        uint8_t RESERVED_2[480];
15523   struct {                                         /* offset: 0x4C00, array step: 0x20 */
15524     __IO uint32_t GPR_PRIVATE;                       /**< General purpose register, array offset: 0x4C00, array step: 0x20 */
15525     __IO uint32_t SET;                               /**< General purpose register, array offset: 0x4C04, array step: 0x20 */
15526     __IO uint32_t CLR;                               /**< General purpose register, array offset: 0x4C08, array step: 0x20 */
15527     __IO uint32_t TOG;                               /**< General purpose register, array offset: 0x4C0C, array step: 0x20 */
15528     __IO uint32_t AUTHEN;                            /**< GPR access control, array offset: 0x4C10, array step: 0x20 */
15529     __IO uint32_t AUTHEN_SET;                        /**< GPR access control, array offset: 0x4C14, array step: 0x20 */
15530     __IO uint32_t AUTHEN_CLR;                        /**< GPR access control, array offset: 0x4C18, array step: 0x20 */
15531     __IO uint32_t AUTHEN_TOG;                        /**< GPR access control, array offset: 0x4C1C, array step: 0x20 */
15532   } GPR_PRIVATE[4];
15533        uint8_t RESERVED_3[896];
15534   struct {                                         /* offset: 0x5000, array step: 0x40 */
15535     __IO uint32_t DIRECT;                            /**< Clock source direct control, array offset: 0x5000, array step: 0x40 */
15536          uint8_t RESERVED_0[12];
15537     __IO uint32_t LPM0;                              /**< Clock source low power mode setting, array offset: 0x5010, array step: 0x40 */
15538     __IO uint32_t LPM1;                              /**< clock source low power mode setting, array offset: 0x5014, array step: 0x40 */
15539          uint8_t RESERVED_1[4];
15540     __IO uint32_t LPM_CUR;                           /**< LPM setting of current CPU domain, array offset: 0x501C, array step: 0x40 */
15541     __I  uint32_t STATUS0;                           /**< Clock source working status, array offset: 0x5020, array step: 0x40 */
15542     __I  uint32_t STATUS1;                           /**< Clock source domain status, array offset: 0x5024, array step: 0x40 */
15543          uint8_t RESERVED_2[8];
15544     __IO uint32_t AUTHEN;                            /**< Clock Source access control, array offset: 0x5030, array step: 0x40 */
15545          uint8_t RESERVED_3[12];
15546   } OSCPLL[25];
15547        uint8_t RESERVED_4[10688];
15548   struct {                                         /* offset: 0x8000, array step: 0x40 */
15549     __IO uint32_t DIRECT;                            /**< LPCG direct control, array offset: 0x8000, array step: 0x40 */
15550          uint8_t RESERVED_0[12];
15551     __IO uint32_t LPM0;                              /**< Clock source low power mode setting, array offset: 0x8010, array step: 0x40 */
15552     __IO uint32_t LPM1;                              /**< clock source low power mode setting, array offset: 0x8014, array step: 0x40 */
15553          uint8_t RESERVED_1[4];
15554     __IO uint32_t LPM_CUR;                           /**< LPM setting of current CPU domain, array offset: 0x801C, array step: 0x40 */
15555     __I  uint32_t STATUS0;                           /**< LPCG working status, array offset: 0x8020, array step: 0x40 */
15556     __I  uint32_t STATUS1;                           /**< LPCG domain status, array offset: 0x8024, array step: 0x40 */
15557          uint8_t RESERVED_2[8];
15558     __IO uint32_t AUTHEN;                            /**< LPCG access control, array offset: 0x8030, array step: 0x40 */
15559          uint8_t RESERVED_3[12];
15560   } LPCG[149];
15561 } CCM_Type;
15562 
15563 /* ----------------------------------------------------------------------------
15564    -- CCM Register Masks
15565    ---------------------------------------------------------------------------- */
15566 
15567 /*!
15568  * @addtogroup CCM_Register_Masks CCM Register Masks
15569  * @{
15570  */
15571 
15572 /*! @name CLOCK_ROOT_CONTROL - Clock Root Control Register */
15573 /*! @{ */
15574 
15575 #define CCM_CLOCK_ROOT_CONTROL_DIV_MASK          (0xFFU)
15576 #define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT         (0U)
15577 /*! DIV - Clock division fraction. */
15578 #define CCM_CLOCK_ROOT_CONTROL_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
15579 
15580 #define CCM_CLOCK_ROOT_CONTROL_MUX_MASK          (0x300U)
15581 #define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT         (8U)
15582 /*! MUX - Clock multiplexer.
15583  *  0b10..Select clock source 2
15584  *  0b00..Select clock source 0
15585  *  0b01..Select clock source 1
15586  *  0b11..Select clock source 3
15587  */
15588 #define CCM_CLOCK_ROOT_CONTROL_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
15589 
15590 #define CCM_CLOCK_ROOT_CONTROL_OFF_MASK          (0x1000000U)
15591 #define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT         (24U)
15592 /*! OFF - Shutdown clock root.
15593  *  0b0..Clock root is enabled
15594  *  0b1..Clock root is disabled
15595  */
15596 #define CCM_CLOCK_ROOT_CONTROL_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
15597 /*! @} */
15598 
15599 /* The count of CCM_CLOCK_ROOT_CONTROL */
15600 #define CCM_CLOCK_ROOT_CONTROL_COUNT             (74U)
15601 
15602 /*! @name CLOCK_ROOT_CONTROL_SET - Clock Root Control Register */
15603 /*! @{ */
15604 
15605 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK      (0xFFU)
15606 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT     (0U)
15607 /*! DIV - Clock division fraction. */
15608 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
15609 
15610 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK      (0x300U)
15611 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT     (8U)
15612 /*! MUX - Clock multiplexer. */
15613 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
15614 
15615 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK      (0x1000000U)
15616 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT     (24U)
15617 /*! OFF - Shutdown clock root. */
15618 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
15619 /*! @} */
15620 
15621 /* The count of CCM_CLOCK_ROOT_CONTROL_SET */
15622 #define CCM_CLOCK_ROOT_CONTROL_SET_COUNT         (74U)
15623 
15624 /*! @name CLOCK_ROOT_CONTROL_CLR - Clock Root Control Register */
15625 /*! @{ */
15626 
15627 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK      (0xFFU)
15628 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT     (0U)
15629 /*! DIV - Clock division fraction. */
15630 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
15631 
15632 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK      (0x300U)
15633 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT     (8U)
15634 /*! MUX - Clock multiplexer. */
15635 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
15636 
15637 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK      (0x1000000U)
15638 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT     (24U)
15639 /*! OFF - Shutdown clock root. */
15640 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
15641 /*! @} */
15642 
15643 /* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
15644 #define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT         (74U)
15645 
15646 /*! @name CLOCK_ROOT_CONTROL_TOG - Clock Root Control Register */
15647 /*! @{ */
15648 
15649 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK      (0xFFU)
15650 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT     (0U)
15651 /*! DIV - Clock division fraction. */
15652 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
15653 
15654 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK      (0x300U)
15655 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT     (8U)
15656 /*! MUX - Clock multiplexer. */
15657 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
15658 
15659 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK      (0x1000000U)
15660 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT     (24U)
15661 /*! OFF - Shutdown clock root. */
15662 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
15663 /*! @} */
15664 
15665 /* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
15666 #define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT         (74U)
15667 
15668 /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */
15669 /*! @{ */
15670 
15671 #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK          (0xFFU)
15672 #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT         (0U)
15673 /*! DIV - Current clock root DIV setting */
15674 #define CCM_CLOCK_ROOT_STATUS0_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
15675 
15676 #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK          (0x300U)
15677 #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT         (8U)
15678 /*! MUX - Current clock root MUX setting */
15679 #define CCM_CLOCK_ROOT_STATUS0_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
15680 
15681 #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK          (0x1000000U)
15682 #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT         (24U)
15683 /*! OFF - Current clock root OFF setting
15684  *  0b0..Clock root is enabled
15685  *  0b1..Clock root is disabled
15686  */
15687 #define CCM_CLOCK_ROOT_STATUS0_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
15688 
15689 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
15690 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT  (28U)
15691 /*! SLICE_BUSY - Internal updating in generation logic Indication for clock generation logic is applying new setting.
15692  *  0b0..Clock generation logic is not busy
15693  *  0b1..Clock generation logic is applying the new setting
15694  */
15695 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
15696 
15697 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
15698 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
15699 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic Indication for clock status is synchronizing for clock root.
15700  *  0b0..Synchronization not in process
15701  *  0b1..Synchronization in process
15702  */
15703 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
15704 
15705 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK     (0x80000000U)
15706 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT    (31U)
15707 /*! CHANGING - Indication for clock root internal logic is updating. This status is a combination of UPDATE_FORWARD and SLICE_BUSY.
15708  *  0b0..Clock Status is not updating currently
15709  *  0b1..Clock generation logic is currently updating
15710  */
15711 #define CCM_CLOCK_ROOT_STATUS0_CHANGING(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
15712 /*! @} */
15713 
15714 /* The count of CCM_CLOCK_ROOT_STATUS0 */
15715 #define CCM_CLOCK_ROOT_STATUS0_COUNT             (74U)
15716 
15717 /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */
15718 /*! @{ */
15719 
15720 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK       (0x100U)
15721 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT      (8U)
15722 /*! TZ_USER - User access permission
15723  *  0b1..Clock Root settings can be changed in user mode.
15724  *  0b0..Clock Root settings cannot be changed in user mode.
15725  */
15726 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
15727 
15728 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK         (0x200U)
15729 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT        (9U)
15730 /*! TZ_NS - Non-secure access permission
15731  *  0b0..Cannot be changed in Non-secure mode.
15732  *  0b1..Can be changed in Non-secure mode.
15733  */
15734 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
15735 
15736 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK       (0x800U)
15737 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT      (11U)
15738 /*! LOCK_TZ - Lock TrustZone settings
15739  *  0b0..TrustZone settings is not locked.
15740  *  0b1..TrustZone settings is locked.
15741  */
15742 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
15743 
15744 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK     (0x8000U)
15745 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT    (15U)
15746 /*! LOCK_LIST - Lock white list
15747  *  0b0..Whitelist is not locked.
15748  *  0b1..Whitelist is locked.
15749  */
15750 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
15751 
15752 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK    (0xFFFF0000U)
15753 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT   (16U)
15754 /*! WHITE_LIST - Whitelist settings */
15755 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
15756 /*! @} */
15757 
15758 /* The count of CCM_CLOCK_ROOT_AUTHEN */
15759 #define CCM_CLOCK_ROOT_AUTHEN_COUNT              (74U)
15760 
15761 /*! @name OBSERVE_CONTROL - Observe control */
15762 /*! @{ */
15763 
15764 #define CCM_OBSERVE_CONTROL_SELECT_MASK          (0x1FFU)
15765 #define CCM_OBSERVE_CONTROL_SELECT_SHIFT         (0U)
15766 /*! SELECT - Observe signal selector */
15767 #define CCM_OBSERVE_CONTROL_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBSERVE_CONTROL_SELECT_MASK)
15768 
15769 #define CCM_OBSERVE_CONTROL_RAW_MASK             (0x1000U)
15770 #define CCM_OBSERVE_CONTROL_RAW_SHIFT            (12U)
15771 /*! RAW - Observe raw signal
15772  *  0b0..Select divided signal.
15773  *  0b1..Select raw signal.
15774  */
15775 #define CCM_OBSERVE_CONTROL_RAW(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBSERVE_CONTROL_RAW_MASK)
15776 
15777 #define CCM_OBSERVE_CONTROL_INV_MASK             (0x2000U)
15778 #define CCM_OBSERVE_CONTROL_INV_SHIFT            (13U)
15779 /*! INV
15780  *  0b0..Clock phase remain same.
15781  *  0b1..Invert clock phase before measurement or send to IO.
15782  */
15783 #define CCM_OBSERVE_CONTROL_INV(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBSERVE_CONTROL_INV_MASK)
15784 
15785 #define CCM_OBSERVE_CONTROL_RESET_MASK           (0x8000U)
15786 #define CCM_OBSERVE_CONTROL_RESET_SHIFT          (15U)
15787 /*! RESET - Reset observe divider
15788  *  0b0..Reset deasserts
15789  *  0b1..Reset asserts
15790  */
15791 #define CCM_OBSERVE_CONTROL_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBSERVE_CONTROL_RESET_MASK)
15792 
15793 #define CCM_OBSERVE_CONTROL_DIVIDE_MASK          (0xFF0000U)
15794 #define CCM_OBSERVE_CONTROL_DIVIDE_SHIFT         (16U)
15795 /*! DIVIDE - Division factor of the divider for observed signal */
15796 #define CCM_OBSERVE_CONTROL_DIVIDE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBSERVE_CONTROL_DIVIDE_MASK)
15797 
15798 #define CCM_OBSERVE_CONTROL_OFF_MASK             (0x1000000U)
15799 #define CCM_OBSERVE_CONTROL_OFF_SHIFT            (24U)
15800 /*! OFF - Turn off
15801  *  0b0..observe slice is on
15802  *  0b1..observe slice is off
15803  */
15804 #define CCM_OBSERVE_CONTROL_OFF(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBSERVE_CONTROL_OFF_MASK)
15805 /*! @} */
15806 
15807 /* The count of CCM_OBSERVE_CONTROL */
15808 #define CCM_OBSERVE_CONTROL_COUNT                (2U)
15809 
15810 /*! @name OBSERVE_CONTROL_SET - Observe control */
15811 /*! @{ */
15812 
15813 #define CCM_OBSERVE_CONTROL_SET_SELECT_MASK      (0x1FFU)
15814 #define CCM_OBSERVE_CONTROL_SET_SELECT_SHIFT     (0U)
15815 /*! SELECT - Observe signal selector */
15816 #define CCM_OBSERVE_CONTROL_SET_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBSERVE_CONTROL_SET_SELECT_MASK)
15817 
15818 #define CCM_OBSERVE_CONTROL_SET_RAW_MASK         (0x1000U)
15819 #define CCM_OBSERVE_CONTROL_SET_RAW_SHIFT        (12U)
15820 /*! RAW - Observe raw signal */
15821 #define CCM_OBSERVE_CONTROL_SET_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBSERVE_CONTROL_SET_RAW_MASK)
15822 
15823 #define CCM_OBSERVE_CONTROL_SET_INV_MASK         (0x2000U)
15824 #define CCM_OBSERVE_CONTROL_SET_INV_SHIFT        (13U)
15825 #define CCM_OBSERVE_CONTROL_SET_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBSERVE_CONTROL_SET_INV_MASK)
15826 
15827 #define CCM_OBSERVE_CONTROL_SET_RESET_MASK       (0x8000U)
15828 #define CCM_OBSERVE_CONTROL_SET_RESET_SHIFT      (15U)
15829 /*! RESET - Reset observe divider */
15830 #define CCM_OBSERVE_CONTROL_SET_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBSERVE_CONTROL_SET_RESET_MASK)
15831 
15832 #define CCM_OBSERVE_CONTROL_SET_DIVIDE_MASK      (0xFF0000U)
15833 #define CCM_OBSERVE_CONTROL_SET_DIVIDE_SHIFT     (16U)
15834 /*! DIVIDE - Division factor of the divider for observed signal */
15835 #define CCM_OBSERVE_CONTROL_SET_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBSERVE_CONTROL_SET_DIVIDE_MASK)
15836 
15837 #define CCM_OBSERVE_CONTROL_SET_OFF_MASK         (0x1000000U)
15838 #define CCM_OBSERVE_CONTROL_SET_OFF_SHIFT        (24U)
15839 /*! OFF - Turn off */
15840 #define CCM_OBSERVE_CONTROL_SET_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBSERVE_CONTROL_SET_OFF_MASK)
15841 /*! @} */
15842 
15843 /* The count of CCM_OBSERVE_CONTROL_SET */
15844 #define CCM_OBSERVE_CONTROL_SET_COUNT            (2U)
15845 
15846 /*! @name OBSERVE_CONTROL_CLR - Observe control */
15847 /*! @{ */
15848 
15849 #define CCM_OBSERVE_CONTROL_CLR_SELECT_MASK      (0x1FFU)
15850 #define CCM_OBSERVE_CONTROL_CLR_SELECT_SHIFT     (0U)
15851 /*! SELECT - Observe signal selector */
15852 #define CCM_OBSERVE_CONTROL_CLR_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_SELECT_MASK)
15853 
15854 #define CCM_OBSERVE_CONTROL_CLR_RAW_MASK         (0x1000U)
15855 #define CCM_OBSERVE_CONTROL_CLR_RAW_SHIFT        (12U)
15856 /*! RAW - Observe raw signal */
15857 #define CCM_OBSERVE_CONTROL_CLR_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_RAW_MASK)
15858 
15859 #define CCM_OBSERVE_CONTROL_CLR_INV_MASK         (0x2000U)
15860 #define CCM_OBSERVE_CONTROL_CLR_INV_SHIFT        (13U)
15861 #define CCM_OBSERVE_CONTROL_CLR_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_INV_MASK)
15862 
15863 #define CCM_OBSERVE_CONTROL_CLR_RESET_MASK       (0x8000U)
15864 #define CCM_OBSERVE_CONTROL_CLR_RESET_SHIFT      (15U)
15865 /*! RESET - Reset observe divider */
15866 #define CCM_OBSERVE_CONTROL_CLR_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_RESET_MASK)
15867 
15868 #define CCM_OBSERVE_CONTROL_CLR_DIVIDE_MASK      (0xFF0000U)
15869 #define CCM_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT     (16U)
15870 /*! DIVIDE - Division factor of the divider for observed signal */
15871 #define CCM_OBSERVE_CONTROL_CLR_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
15872 
15873 #define CCM_OBSERVE_CONTROL_CLR_OFF_MASK         (0x1000000U)
15874 #define CCM_OBSERVE_CONTROL_CLR_OFF_SHIFT        (24U)
15875 /*! OFF - Turn off */
15876 #define CCM_OBSERVE_CONTROL_CLR_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBSERVE_CONTROL_CLR_OFF_MASK)
15877 /*! @} */
15878 
15879 /* The count of CCM_OBSERVE_CONTROL_CLR */
15880 #define CCM_OBSERVE_CONTROL_CLR_COUNT            (2U)
15881 
15882 /*! @name OBSERVE_CONTROL_TOG - Observe control */
15883 /*! @{ */
15884 
15885 #define CCM_OBSERVE_CONTROL_TOG_SELECT_MASK      (0x1FFU)
15886 #define CCM_OBSERVE_CONTROL_TOG_SELECT_SHIFT     (0U)
15887 /*! SELECT - Observe signal selector */
15888 #define CCM_OBSERVE_CONTROL_TOG_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_SELECT_MASK)
15889 
15890 #define CCM_OBSERVE_CONTROL_TOG_RAW_MASK         (0x1000U)
15891 #define CCM_OBSERVE_CONTROL_TOG_RAW_SHIFT        (12U)
15892 /*! RAW - Observe raw signal */
15893 #define CCM_OBSERVE_CONTROL_TOG_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_RAW_MASK)
15894 
15895 #define CCM_OBSERVE_CONTROL_TOG_INV_MASK         (0x2000U)
15896 #define CCM_OBSERVE_CONTROL_TOG_INV_SHIFT        (13U)
15897 #define CCM_OBSERVE_CONTROL_TOG_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_INV_MASK)
15898 
15899 #define CCM_OBSERVE_CONTROL_TOG_RESET_MASK       (0x8000U)
15900 #define CCM_OBSERVE_CONTROL_TOG_RESET_SHIFT      (15U)
15901 /*! RESET - Reset observe divider */
15902 #define CCM_OBSERVE_CONTROL_TOG_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_RESET_MASK)
15903 
15904 #define CCM_OBSERVE_CONTROL_TOG_DIVIDE_MASK      (0xFF0000U)
15905 #define CCM_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT     (16U)
15906 /*! DIVIDE - Division factor of the divider for observed signal */
15907 #define CCM_OBSERVE_CONTROL_TOG_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
15908 
15909 #define CCM_OBSERVE_CONTROL_TOG_OFF_MASK         (0x1000000U)
15910 #define CCM_OBSERVE_CONTROL_TOG_OFF_SHIFT        (24U)
15911 /*! OFF - Turn off */
15912 #define CCM_OBSERVE_CONTROL_TOG_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBSERVE_CONTROL_TOG_OFF_MASK)
15913 /*! @} */
15914 
15915 /* The count of CCM_OBSERVE_CONTROL_TOG */
15916 #define CCM_OBSERVE_CONTROL_TOG_COUNT            (2U)
15917 
15918 /*! @name OBSERVE_STATUS - Observe status */
15919 /*! @{ */
15920 
15921 #define CCM_OBSERVE_STATUS_SELECT_MASK           (0x1FFU)
15922 #define CCM_OBSERVE_STATUS_SELECT_SHIFT          (0U)
15923 /*! SELECT - Observe signal selector */
15924 #define CCM_OBSERVE_STATUS_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_SELECT_SHIFT)) & CCM_OBSERVE_STATUS_SELECT_MASK)
15925 
15926 #define CCM_OBSERVE_STATUS_RAW_MASK              (0x1000U)
15927 #define CCM_OBSERVE_STATUS_RAW_SHIFT             (12U)
15928 /*! RAW - Observe raw signal
15929  *  0b0..Select divided signal.
15930  *  0b1..Select raw signal.
15931  */
15932 #define CCM_OBSERVE_STATUS_RAW(x)                (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_RAW_SHIFT)) & CCM_OBSERVE_STATUS_RAW_MASK)
15933 
15934 #define CCM_OBSERVE_STATUS_INV_MASK              (0x2000U)
15935 #define CCM_OBSERVE_STATUS_INV_SHIFT             (13U)
15936 /*! INV - Invert
15937  *  0b0..Clock phase remain same.
15938  *  0b1..Invert clock phase before measurement or send to IO.
15939  */
15940 #define CCM_OBSERVE_STATUS_INV(x)                (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_INV_SHIFT)) & CCM_OBSERVE_STATUS_INV_MASK)
15941 
15942 #define CCM_OBSERVE_STATUS_RESET_MASK            (0x8000U)
15943 #define CCM_OBSERVE_STATUS_RESET_SHIFT           (15U)
15944 /*! RESET - Reset state
15945  *  0b1..Observe divider is in reset state
15946  *  0b0..Observe divider is not in reset state
15947  */
15948 #define CCM_OBSERVE_STATUS_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_RESET_SHIFT)) & CCM_OBSERVE_STATUS_RESET_MASK)
15949 
15950 #define CCM_OBSERVE_STATUS_DIVIDE_MASK           (0xFF0000U)
15951 #define CCM_OBSERVE_STATUS_DIVIDE_SHIFT          (16U)
15952 /*! DIVIDE - Divider for observe signal */
15953 #define CCM_OBSERVE_STATUS_DIVIDE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_DIVIDE_SHIFT)) & CCM_OBSERVE_STATUS_DIVIDE_MASK)
15954 
15955 #define CCM_OBSERVE_STATUS_OFF_MASK              (0x1000000U)
15956 #define CCM_OBSERVE_STATUS_OFF_SHIFT             (24U)
15957 /*! OFF - Turn off slice
15958  *  0b0..observe slice is on
15959  *  0b1..observe slice is off
15960  */
15961 #define CCM_OBSERVE_STATUS_OFF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_OFF_SHIFT)) & CCM_OBSERVE_STATUS_OFF_MASK)
15962 
15963 #define CCM_OBSERVE_STATUS_FREQ_MEASURE_DONE_MASK (0x2000000U)
15964 #define CCM_OBSERVE_STATUS_FREQ_MEASURE_DONE_SHIFT (25U)
15965 /*! FREQ_MEASURE_DONE - frequency measurement done flag
15966  *  0b0..Frequency measurement is on-going or not started
15967  *  0b1..Frequency measurement is done.
15968  */
15969 #define CCM_OBSERVE_STATUS_FREQ_MEASURE_DONE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_FREQ_MEASURE_DONE_SHIFT)) & CCM_OBSERVE_STATUS_FREQ_MEASURE_DONE_MASK)
15970 
15971 #define CCM_OBSERVE_STATUS_BUSY_MASK             (0x10000000U)
15972 #define CCM_OBSERVE_STATUS_BUSY_SHIFT            (28U)
15973 /*! BUSY - Busy
15974  *  0b1..Current observe is busy
15975  *  0b0..Current observe is not busy
15976  */
15977 #define CCM_OBSERVE_STATUS_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_BUSY_SHIFT)) & CCM_OBSERVE_STATUS_BUSY_MASK)
15978 
15979 #define CCM_OBSERVE_STATUS_UPDATED_FORWARD_MASK  (0x20000000U)
15980 #define CCM_OBSERVE_STATUS_UPDATED_FORWARD_SHIFT (29U)
15981 /*! UPDATED_FORWARD - Update Forward */
15982 #define CCM_OBSERVE_STATUS_UPDATED_FORWARD(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_UPDATED_FORWARD_SHIFT)) & CCM_OBSERVE_STATUS_UPDATED_FORWARD_MASK)
15983 
15984 #define CCM_OBSERVE_STATUS_CHANGING_MASK         (0x80000000U)
15985 #define CCM_OBSERVE_STATUS_CHANGING_SHIFT        (31U)
15986 /*! CHANGING - Busy */
15987 #define CCM_OBSERVE_STATUS_CHANGING(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_STATUS_CHANGING_SHIFT)) & CCM_OBSERVE_STATUS_CHANGING_MASK)
15988 /*! @} */
15989 
15990 /* The count of CCM_OBSERVE_STATUS */
15991 #define CCM_OBSERVE_STATUS_COUNT                 (2U)
15992 
15993 /*! @name OBSERVE_AUTHEN - Observe access control */
15994 /*! @{ */
15995 
15996 #define CCM_OBSERVE_AUTHEN_TZ_USER_MASK          (0x100U)
15997 #define CCM_OBSERVE_AUTHEN_TZ_USER_SHIFT         (8U)
15998 /*! TZ_USER - User access permission
15999  *  0b1..Observe slice settings can be changed in user mode.
16000  *  0b0..Observe slice settings cannot be changed in user mode.
16001  */
16002 #define CCM_OBSERVE_AUTHEN_TZ_USER(x)            (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBSERVE_AUTHEN_TZ_USER_MASK)
16003 
16004 #define CCM_OBSERVE_AUTHEN_TZ_NS_MASK            (0x200U)
16005 #define CCM_OBSERVE_AUTHEN_TZ_NS_SHIFT           (9U)
16006 /*! TZ_NS - Non-secure access permission
16007  *  0b0..Cannot be changed in non-secure mode.
16008  *  0b1..Can be changed in non-secure mode.
16009  */
16010 #define CCM_OBSERVE_AUTHEN_TZ_NS(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBSERVE_AUTHEN_TZ_NS_MASK)
16011 
16012 #define CCM_OBSERVE_AUTHEN_LOCK_TZ_MASK          (0x800U)
16013 #define CCM_OBSERVE_AUTHEN_LOCK_TZ_SHIFT         (11U)
16014 /*! LOCK_TZ - Lock TrustZone setting
16015  *  0b0..TrustZone settings is not locked.
16016  *  0b1..TrustZone settings is locked.
16017  */
16018 #define CCM_OBSERVE_AUTHEN_LOCK_TZ(x)            (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBSERVE_AUTHEN_LOCK_TZ_MASK)
16019 
16020 #define CCM_OBSERVE_AUTHEN_LOCK_LIST_MASK        (0x8000U)
16021 #define CCM_OBSERVE_AUTHEN_LOCK_LIST_SHIFT       (15U)
16022 /*! LOCK_LIST - Lock white list
16023  *  0b0..White list is not locked.
16024  *  0b1..White list is locked.
16025  */
16026 #define CCM_OBSERVE_AUTHEN_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_LOCK_LIST_MASK)
16027 
16028 #define CCM_OBSERVE_AUTHEN_WHITE_LIST_MASK       (0xFFFF0000U)
16029 #define CCM_OBSERVE_AUTHEN_WHITE_LIST_SHIFT      (16U)
16030 /*! WHITE_LIST - Whitelist settings
16031  *  0b0000000000001111..All domain can change.
16032  *  0b0000000000000010..Domain 1 can change.
16033  *  0b0000000000000011..Domain 0 and domain 1 can change.
16034  *  0b0000000000000000..No domain can change.
16035  *  0b0000000000000100..Domain 2 can change.
16036  *  0b0000000000000001..Domain 0 can change.
16037  */
16038 #define CCM_OBSERVE_AUTHEN_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_WHITE_LIST_MASK)
16039 /*! @} */
16040 
16041 /* The count of CCM_OBSERVE_AUTHEN */
16042 #define CCM_OBSERVE_AUTHEN_COUNT                 (2U)
16043 
16044 /*! @name OBSERVE_AUTHEN_SET - Observe access control */
16045 /*! @{ */
16046 
16047 #define CCM_OBSERVE_AUTHEN_SET_TZ_USER_MASK      (0x100U)
16048 #define CCM_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT     (8U)
16049 /*! TZ_USER - User access permission */
16050 #define CCM_OBSERVE_AUTHEN_SET_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
16051 
16052 #define CCM_OBSERVE_AUTHEN_SET_TZ_NS_MASK        (0x200U)
16053 #define CCM_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT       (9U)
16054 /*! TZ_NS - Non-secure access permission */
16055 #define CCM_OBSERVE_AUTHEN_SET_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
16056 
16057 #define CCM_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK      (0x800U)
16058 #define CCM_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT     (11U)
16059 /*! LOCK_TZ - Lock TrustZone setting */
16060 #define CCM_OBSERVE_AUTHEN_SET_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
16061 
16062 #define CCM_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK    (0x8000U)
16063 #define CCM_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT   (15U)
16064 /*! LOCK_LIST - Lock white list */
16065 #define CCM_OBSERVE_AUTHEN_SET_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
16066 
16067 #define CCM_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK   (0xFFFF0000U)
16068 #define CCM_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT  (16U)
16069 /*! WHITE_LIST - Whitelist settings */
16070 #define CCM_OBSERVE_AUTHEN_SET_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
16071 /*! @} */
16072 
16073 /* The count of CCM_OBSERVE_AUTHEN_SET */
16074 #define CCM_OBSERVE_AUTHEN_SET_COUNT             (2U)
16075 
16076 /*! @name OBSERVE_AUTHEN_CLR - Observe access control */
16077 /*! @{ */
16078 
16079 #define CCM_OBSERVE_AUTHEN_CLR_TZ_USER_MASK      (0x100U)
16080 #define CCM_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT     (8U)
16081 /*! TZ_USER - User access permission */
16082 #define CCM_OBSERVE_AUTHEN_CLR_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
16083 
16084 #define CCM_OBSERVE_AUTHEN_CLR_TZ_NS_MASK        (0x200U)
16085 #define CCM_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT       (9U)
16086 /*! TZ_NS - Non-secure access permission */
16087 #define CCM_OBSERVE_AUTHEN_CLR_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
16088 
16089 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK      (0x800U)
16090 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT     (11U)
16091 /*! LOCK_TZ - Lock TrustZone setting */
16092 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
16093 
16094 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK    (0x8000U)
16095 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT   (15U)
16096 /*! LOCK_LIST - Lock white list */
16097 #define CCM_OBSERVE_AUTHEN_CLR_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
16098 
16099 #define CCM_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK   (0xFFFF0000U)
16100 #define CCM_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT  (16U)
16101 /*! WHITE_LIST - Whitelist settings */
16102 #define CCM_OBSERVE_AUTHEN_CLR_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
16103 /*! @} */
16104 
16105 /* The count of CCM_OBSERVE_AUTHEN_CLR */
16106 #define CCM_OBSERVE_AUTHEN_CLR_COUNT             (2U)
16107 
16108 /*! @name OBSERVE_AUTHEN_TOG - Observe access control */
16109 /*! @{ */
16110 
16111 #define CCM_OBSERVE_AUTHEN_TOG_TZ_USER_MASK      (0x100U)
16112 #define CCM_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT     (8U)
16113 /*! TZ_USER - User access permission */
16114 #define CCM_OBSERVE_AUTHEN_TOG_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
16115 
16116 #define CCM_OBSERVE_AUTHEN_TOG_TZ_NS_MASK        (0x200U)
16117 #define CCM_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT       (9U)
16118 /*! TZ_NS - Non-secure access permission */
16119 #define CCM_OBSERVE_AUTHEN_TOG_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
16120 
16121 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK      (0x800U)
16122 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT     (11U)
16123 /*! LOCK_TZ - Lock TrustZone setting */
16124 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
16125 
16126 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK    (0x8000U)
16127 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT   (15U)
16128 /*! LOCK_LIST - Lock white list */
16129 #define CCM_OBSERVE_AUTHEN_TOG_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
16130 
16131 #define CCM_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK   (0xFFFF0000U)
16132 #define CCM_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT  (16U)
16133 /*! WHITE_LIST - Whitelist settings */
16134 #define CCM_OBSERVE_AUTHEN_TOG_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
16135 /*! @} */
16136 
16137 /* The count of CCM_OBSERVE_AUTHEN_TOG */
16138 #define CCM_OBSERVE_AUTHEN_TOG_COUNT             (2U)
16139 
16140 /*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */
16141 /*! @{ */
16142 
16143 #define CCM_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
16144 #define CCM_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
16145 /*! FREQUENCY - Frequency */
16146 #define CCM_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
16147 /*! @} */
16148 
16149 /* The count of CCM_OBSERVE_FREQUENCY_CURRENT */
16150 #define CCM_OBSERVE_FREQUENCY_CURRENT_COUNT      (2U)
16151 
16152 /*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */
16153 /*! @{ */
16154 
16155 #define CCM_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
16156 #define CCM_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
16157 /*! FREQUENCY - Frequency */
16158 #define CCM_OBSERVE_FREQUENCY_MIN_FREQUENCY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
16159 /*! @} */
16160 
16161 /* The count of CCM_OBSERVE_FREQUENCY_MIN */
16162 #define CCM_OBSERVE_FREQUENCY_MIN_COUNT          (2U)
16163 
16164 /*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */
16165 /*! @{ */
16166 
16167 #define CCM_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
16168 #define CCM_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
16169 /*! FREQUENCY - Frequency */
16170 #define CCM_OBSERVE_FREQUENCY_MAX_FREQUENCY(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
16171 /*! @} */
16172 
16173 /* The count of CCM_OBSERVE_FREQUENCY_MAX */
16174 #define CCM_OBSERVE_FREQUENCY_MAX_COUNT          (2U)
16175 
16176 /*! @name OBSERVE_PERIOD_CURRENT - Current period time detected */
16177 /*! @{ */
16178 
16179 #define CCM_OBSERVE_PERIOD_CURRENT_PERIOD_MASK   (0xFFFFFFFFU)
16180 #define CCM_OBSERVE_PERIOD_CURRENT_PERIOD_SHIFT  (0U)
16181 /*! PERIOD - Period time */
16182 #define CCM_OBSERVE_PERIOD_CURRENT_PERIOD(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_PERIOD_CURRENT_PERIOD_SHIFT)) & CCM_OBSERVE_PERIOD_CURRENT_PERIOD_MASK)
16183 /*! @} */
16184 
16185 /* The count of CCM_OBSERVE_PERIOD_CURRENT */
16186 #define CCM_OBSERVE_PERIOD_CURRENT_COUNT         (2U)
16187 
16188 /*! @name OBSERVE_PERIOD_MIN - Minimum period time detected */
16189 /*! @{ */
16190 
16191 #define CCM_OBSERVE_PERIOD_MIN_PERIOD_MASK       (0xFFFFFFFFU)
16192 #define CCM_OBSERVE_PERIOD_MIN_PERIOD_SHIFT      (0U)
16193 /*! PERIOD - Period time */
16194 #define CCM_OBSERVE_PERIOD_MIN_PERIOD(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_PERIOD_MIN_PERIOD_SHIFT)) & CCM_OBSERVE_PERIOD_MIN_PERIOD_MASK)
16195 /*! @} */
16196 
16197 /* The count of CCM_OBSERVE_PERIOD_MIN */
16198 #define CCM_OBSERVE_PERIOD_MIN_COUNT             (2U)
16199 
16200 /*! @name OBSERVE_PERIOD_MAX - Maximum period time detected */
16201 /*! @{ */
16202 
16203 #define CCM_OBSERVE_PERIOD_MAX_PERIOD_MASK       (0xFFFFFFFFU)
16204 #define CCM_OBSERVE_PERIOD_MAX_PERIOD_SHIFT      (0U)
16205 /*! PERIOD - Period time */
16206 #define CCM_OBSERVE_PERIOD_MAX_PERIOD(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_PERIOD_MAX_PERIOD_SHIFT)) & CCM_OBSERVE_PERIOD_MAX_PERIOD_MASK)
16207 /*! @} */
16208 
16209 /* The count of CCM_OBSERVE_PERIOD_MAX */
16210 #define CCM_OBSERVE_PERIOD_MAX_COUNT             (2U)
16211 
16212 /*! @name OBSERVE_HIGH_CURRENT - Current high level time detected */
16213 /*! @{ */
16214 
16215 #define CCM_OBSERVE_HIGH_CURRENT_HIGH_MASK       (0xFFFFFFFFU)
16216 #define CCM_OBSERVE_HIGH_CURRENT_HIGH_SHIFT      (0U)
16217 /*! HIGH - High level time */
16218 #define CCM_OBSERVE_HIGH_CURRENT_HIGH(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_HIGH_CURRENT_HIGH_SHIFT)) & CCM_OBSERVE_HIGH_CURRENT_HIGH_MASK)
16219 /*! @} */
16220 
16221 /* The count of CCM_OBSERVE_HIGH_CURRENT */
16222 #define CCM_OBSERVE_HIGH_CURRENT_COUNT           (2U)
16223 
16224 /*! @name OBSERVE_HIGH_MIN - Minimum high level time detected */
16225 /*! @{ */
16226 
16227 #define CCM_OBSERVE_HIGH_MIN_HIGH_MASK           (0xFFFFFFFFU)
16228 #define CCM_OBSERVE_HIGH_MIN_HIGH_SHIFT          (0U)
16229 /*! HIGH - High level time */
16230 #define CCM_OBSERVE_HIGH_MIN_HIGH(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_HIGH_MIN_HIGH_SHIFT)) & CCM_OBSERVE_HIGH_MIN_HIGH_MASK)
16231 /*! @} */
16232 
16233 /* The count of CCM_OBSERVE_HIGH_MIN */
16234 #define CCM_OBSERVE_HIGH_MIN_COUNT               (2U)
16235 
16236 /*! @name OBSERVE_HIGH_MAX - Maximum high level time detected */
16237 /*! @{ */
16238 
16239 #define CCM_OBSERVE_HIGH_MAX_HIGH_MASK           (0xFFFFFFFFU)
16240 #define CCM_OBSERVE_HIGH_MAX_HIGH_SHIFT          (0U)
16241 /*! HIGH - High level time */
16242 #define CCM_OBSERVE_HIGH_MAX_HIGH(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_HIGH_MAX_HIGH_SHIFT)) & CCM_OBSERVE_HIGH_MAX_HIGH_MASK)
16243 /*! @} */
16244 
16245 /* The count of CCM_OBSERVE_HIGH_MAX */
16246 #define CCM_OBSERVE_HIGH_MAX_COUNT               (2U)
16247 
16248 /*! @name OBSERVE_LOW_CURRENT - Current high level time detected */
16249 /*! @{ */
16250 
16251 #define CCM_OBSERVE_LOW_CURRENT_LOW_MASK         (0xFFFFFFFFU)
16252 #define CCM_OBSERVE_LOW_CURRENT_LOW_SHIFT        (0U)
16253 /*! LOW - High level time */
16254 #define CCM_OBSERVE_LOW_CURRENT_LOW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_LOW_CURRENT_LOW_SHIFT)) & CCM_OBSERVE_LOW_CURRENT_LOW_MASK)
16255 /*! @} */
16256 
16257 /* The count of CCM_OBSERVE_LOW_CURRENT */
16258 #define CCM_OBSERVE_LOW_CURRENT_COUNT            (2U)
16259 
16260 /*! @name OBSERVE_LOW_MIN - Minimum high level time detected */
16261 /*! @{ */
16262 
16263 #define CCM_OBSERVE_LOW_MIN_LOW_MASK             (0xFFFFFFFFU)
16264 #define CCM_OBSERVE_LOW_MIN_LOW_SHIFT            (0U)
16265 /*! LOW - High level time */
16266 #define CCM_OBSERVE_LOW_MIN_LOW(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_LOW_MIN_LOW_SHIFT)) & CCM_OBSERVE_LOW_MIN_LOW_MASK)
16267 /*! @} */
16268 
16269 /* The count of CCM_OBSERVE_LOW_MIN */
16270 #define CCM_OBSERVE_LOW_MIN_COUNT                (2U)
16271 
16272 /*! @name OBSERVE_LOW_MAX - Maximum high level time detected */
16273 /*! @{ */
16274 
16275 #define CCM_OBSERVE_LOW_MAX_LOW_MASK             (0xFFFFFFFFU)
16276 #define CCM_OBSERVE_LOW_MAX_LOW_SHIFT            (0U)
16277 /*! LOW - High level time */
16278 #define CCM_OBSERVE_LOW_MAX_LOW(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OBSERVE_LOW_MAX_LOW_SHIFT)) & CCM_OBSERVE_LOW_MAX_LOW_MASK)
16279 /*! @} */
16280 
16281 /* The count of CCM_OBSERVE_LOW_MAX */
16282 #define CCM_OBSERVE_LOW_MAX_COUNT                (2U)
16283 
16284 /*! @name GPR_SHARED0_AUTHEN - GPR access control */
16285 /*! @{ */
16286 
16287 #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK      (0x100U)
16288 #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT     (8U)
16289 /*! TZ_USER - User access permission
16290  *  0b1..Registers of shared GPR slice can be changed in user mode.
16291  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
16292  */
16293 #define CCM_GPR_SHARED0_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK)
16294 
16295 #define CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK        (0x200U)
16296 #define CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT       (9U)
16297 /*! TZ_NS - Non-secure access permission
16298  *  0b0..Cannot be changed in Non-secure mode.
16299  *  0b1..Can be changed in Non-secure mode.
16300  */
16301 #define CCM_GPR_SHARED0_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK)
16302 
16303 #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK      (0x800U)
16304 #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT     (11U)
16305 /*! LOCK_TZ - Lock TrustZone settings
16306  *  0b0..TrustZone settings is not locked.
16307  *  0b1..TrustZone settings is locked.
16308  */
16309 #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK)
16310 
16311 #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK    (0x8000U)
16312 #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT   (15U)
16313 /*! LOCK_LIST - Lock white list
16314  *  0b0..Whitelist is not locked.
16315  *  0b1..Whitelist is locked.
16316  */
16317 #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK)
16318 
16319 #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
16320 #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT  (16U)
16321 /*! WHITE_LIST - Whitelist settings */
16322 #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK)
16323 /*! @} */
16324 
16325 /*! @name GPR_SHARED0_AUTHEN_SET - GPR access control */
16326 /*! @{ */
16327 
16328 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_USER_MASK  (0x100U)
16329 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_USER_SHIFT (8U)
16330 /*! TZ_USER - User access permission */
16331 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_SET_TZ_USER_MASK)
16332 
16333 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_NS_MASK    (0x200U)
16334 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_NS_SHIFT   (9U)
16335 /*! TZ_NS - Non-secure access permission */
16336 #define CCM_GPR_SHARED0_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_SET_TZ_NS_MASK)
16337 
16338 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
16339 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
16340 /*! LOCK_TZ - Lock TrustZone settings */
16341 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_SET_LOCK_TZ_MASK)
16342 
16343 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
16344 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
16345 /*! LOCK_LIST - Lock white list */
16346 #define CCM_GPR_SHARED0_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_SET_LOCK_LIST_MASK)
16347 
16348 #define CCM_GPR_SHARED0_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
16349 #define CCM_GPR_SHARED0_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
16350 /*! WHITE_LIST - Whitelist settings */
16351 #define CCM_GPR_SHARED0_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_SET_WHITE_LIST_MASK)
16352 /*! @} */
16353 
16354 /*! @name GPR_SHARED0_AUTHEN_CLR - GPR access control */
16355 /*! @{ */
16356 
16357 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
16358 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_USER_SHIFT (8U)
16359 /*! TZ_USER - User access permission */
16360 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_CLR_TZ_USER_MASK)
16361 
16362 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
16363 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
16364 /*! TZ_NS - Non-secure access permission */
16365 #define CCM_GPR_SHARED0_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_CLR_TZ_NS_MASK)
16366 
16367 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
16368 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
16369 /*! LOCK_TZ - Lock TrustZone settings */
16370 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_TZ_MASK)
16371 
16372 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
16373 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
16374 /*! LOCK_LIST - Lock white list */
16375 #define CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_CLR_LOCK_LIST_MASK)
16376 
16377 #define CCM_GPR_SHARED0_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
16378 #define CCM_GPR_SHARED0_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
16379 /*! WHITE_LIST - Whitelist settings */
16380 #define CCM_GPR_SHARED0_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_CLR_WHITE_LIST_MASK)
16381 /*! @} */
16382 
16383 /*! @name GPR_SHARED0_AUTHEN_TOG - GPR access control */
16384 /*! @{ */
16385 
16386 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
16387 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_USER_SHIFT (8U)
16388 /*! TZ_USER - User access permission */
16389 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TOG_TZ_USER_MASK)
16390 
16391 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
16392 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
16393 /*! TZ_NS - Non-secure access permission */
16394 #define CCM_GPR_SHARED0_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TOG_TZ_NS_MASK)
16395 
16396 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
16397 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
16398 /*! LOCK_TZ - Lock TrustZone settings */
16399 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_TZ_MASK)
16400 
16401 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
16402 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
16403 /*! LOCK_LIST - Lock white list */
16404 #define CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TOG_LOCK_LIST_MASK)
16405 
16406 #define CCM_GPR_SHARED0_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
16407 #define CCM_GPR_SHARED0_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
16408 /*! WHITE_LIST - Whitelist settings */
16409 #define CCM_GPR_SHARED0_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TOG_WHITE_LIST_MASK)
16410 /*! @} */
16411 
16412 /*! @name GPR_SHARED1_AUTHEN - GPR access control */
16413 /*! @{ */
16414 
16415 #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK      (0x100U)
16416 #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT     (8U)
16417 /*! TZ_USER - User access permission
16418  *  0b1..Registers of shared GPR slice can be changed in user mode.
16419  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
16420  */
16421 #define CCM_GPR_SHARED1_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK)
16422 
16423 #define CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK        (0x200U)
16424 #define CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT       (9U)
16425 /*! TZ_NS - Non-secure access permission
16426  *  0b0..Cannot be changed in Non-secure mode.
16427  *  0b1..Can be changed in Non-secure mode.
16428  */
16429 #define CCM_GPR_SHARED1_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK)
16430 
16431 #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK      (0x800U)
16432 #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT     (11U)
16433 /*! LOCK_TZ - Lock TrustZone settings
16434  *  0b0..TrustZone settings is not locked.
16435  *  0b1..TrustZone settings is locked.
16436  */
16437 #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK)
16438 
16439 #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK    (0x8000U)
16440 #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT   (15U)
16441 /*! LOCK_LIST - Lock white list
16442  *  0b0..Whitelist is not locked.
16443  *  0b1..Whitelist is locked.
16444  */
16445 #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK)
16446 
16447 #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
16448 #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT  (16U)
16449 /*! WHITE_LIST - Whitelist settings */
16450 #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK)
16451 /*! @} */
16452 
16453 /*! @name GPR_SHARED1_AUTHEN_SET - GPR access control */
16454 /*! @{ */
16455 
16456 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_USER_MASK  (0x100U)
16457 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_USER_SHIFT (8U)
16458 /*! TZ_USER - User access permission */
16459 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_SET_TZ_USER_MASK)
16460 
16461 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_NS_MASK    (0x200U)
16462 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_NS_SHIFT   (9U)
16463 /*! TZ_NS - Non-secure access permission */
16464 #define CCM_GPR_SHARED1_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_SET_TZ_NS_MASK)
16465 
16466 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
16467 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
16468 /*! LOCK_TZ - Lock TrustZone settings */
16469 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_SET_LOCK_TZ_MASK)
16470 
16471 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
16472 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
16473 /*! LOCK_LIST - Lock white list */
16474 #define CCM_GPR_SHARED1_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_SET_LOCK_LIST_MASK)
16475 
16476 #define CCM_GPR_SHARED1_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
16477 #define CCM_GPR_SHARED1_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
16478 /*! WHITE_LIST - Whitelist settings */
16479 #define CCM_GPR_SHARED1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_SET_WHITE_LIST_MASK)
16480 /*! @} */
16481 
16482 /*! @name GPR_SHARED1_AUTHEN_CLR - GPR access control */
16483 /*! @{ */
16484 
16485 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
16486 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_USER_SHIFT (8U)
16487 /*! TZ_USER - User access permission */
16488 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_CLR_TZ_USER_MASK)
16489 
16490 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
16491 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
16492 /*! TZ_NS - Non-secure access permission */
16493 #define CCM_GPR_SHARED1_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_CLR_TZ_NS_MASK)
16494 
16495 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
16496 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
16497 /*! LOCK_TZ - Lock TrustZone settings */
16498 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_TZ_MASK)
16499 
16500 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
16501 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
16502 /*! LOCK_LIST - Lock white list */
16503 #define CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_CLR_LOCK_LIST_MASK)
16504 
16505 #define CCM_GPR_SHARED1_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
16506 #define CCM_GPR_SHARED1_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
16507 /*! WHITE_LIST - Whitelist settings */
16508 #define CCM_GPR_SHARED1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_CLR_WHITE_LIST_MASK)
16509 /*! @} */
16510 
16511 /*! @name GPR_SHARED1_AUTHEN_TOG - GPR access control */
16512 /*! @{ */
16513 
16514 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
16515 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_USER_SHIFT (8U)
16516 /*! TZ_USER - User access permission */
16517 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TOG_TZ_USER_MASK)
16518 
16519 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
16520 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
16521 /*! TZ_NS - Non-secure access permission */
16522 #define CCM_GPR_SHARED1_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TOG_TZ_NS_MASK)
16523 
16524 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
16525 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
16526 /*! LOCK_TZ - Lock TrustZone settings */
16527 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_TZ_MASK)
16528 
16529 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
16530 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
16531 /*! LOCK_LIST - Lock white list */
16532 #define CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TOG_LOCK_LIST_MASK)
16533 
16534 #define CCM_GPR_SHARED1_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
16535 #define CCM_GPR_SHARED1_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
16536 /*! WHITE_LIST - Whitelist settings */
16537 #define CCM_GPR_SHARED1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TOG_WHITE_LIST_MASK)
16538 /*! @} */
16539 
16540 /*! @name GPR_SHARED2 - General Purpose Register */
16541 /*! @{ */
16542 
16543 #define CCM_GPR_SHARED2_m33_mask_cm7_MASK        (0x1U)
16544 #define CCM_GPR_SHARED2_m33_mask_cm7_SHIFT       (0U)
16545 /*! m33_mask_cm7 - m33_mask_cm7 */
16546 #define CCM_GPR_SHARED2_m33_mask_cm7(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_cm7_SHIFT)) & CCM_GPR_SHARED2_m33_mask_cm7_MASK)
16547 
16548 #define CCM_GPR_SHARED2_m33_mask_cm33_MASK       (0x2U)
16549 #define CCM_GPR_SHARED2_m33_mask_cm33_SHIFT      (1U)
16550 /*! m33_mask_cm33 - m33_mask_cm33 */
16551 #define CCM_GPR_SHARED2_m33_mask_cm33(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_cm33_SHIFT)) & CCM_GPR_SHARED2_m33_mask_cm33_MASK)
16552 
16553 #define CCM_GPR_SHARED2_m33_mask_edma3_MASK      (0x4U)
16554 #define CCM_GPR_SHARED2_m33_mask_edma3_SHIFT     (2U)
16555 /*! m33_mask_edma3 - m33_mask_edma3 */
16556 #define CCM_GPR_SHARED2_m33_mask_edma3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_edma3_SHIFT)) & CCM_GPR_SHARED2_m33_mask_edma3_MASK)
16557 
16558 #define CCM_GPR_SHARED2_m33_mask_edma4_MASK      (0x8U)
16559 #define CCM_GPR_SHARED2_m33_mask_edma4_SHIFT     (3U)
16560 /*! m33_mask_edma4 - m33_mask_edma4 */
16561 #define CCM_GPR_SHARED2_m33_mask_edma4(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_edma4_SHIFT)) & CCM_GPR_SHARED2_m33_mask_edma4_MASK)
16562 
16563 #define CCM_GPR_SHARED2_m33_mask_netc_MASK       (0x10U)
16564 #define CCM_GPR_SHARED2_m33_mask_netc_SHIFT      (4U)
16565 /*! m33_mask_netc - m33_mask_netc */
16566 #define CCM_GPR_SHARED2_m33_mask_netc(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_netc_SHIFT)) & CCM_GPR_SHARED2_m33_mask_netc_MASK)
16567 
16568 #define CCM_GPR_SHARED2_m33_mask_sim_aon_MASK    (0x100U)
16569 #define CCM_GPR_SHARED2_m33_mask_sim_aon_SHIFT   (8U)
16570 /*! m33_mask_sim_aon - m33_mask_sim_aon */
16571 #define CCM_GPR_SHARED2_m33_mask_sim_aon(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED2_m33_mask_sim_aon_MASK)
16572 
16573 #define CCM_GPR_SHARED2_m33_mask_adc1_MASK       (0x200U)
16574 #define CCM_GPR_SHARED2_m33_mask_adc1_SHIFT      (9U)
16575 /*! m33_mask_adc1 - m33_mask_adc1 */
16576 #define CCM_GPR_SHARED2_m33_mask_adc1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_adc1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_adc1_MASK)
16577 
16578 #define CCM_GPR_SHARED2_m33_mask_adc2_MASK       (0x400U)
16579 #define CCM_GPR_SHARED2_m33_mask_adc2_SHIFT      (10U)
16580 /*! m33_mask_adc2 - m33_mask_adc2 */
16581 #define CCM_GPR_SHARED2_m33_mask_adc2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_adc2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_adc2_MASK)
16582 
16583 #define CCM_GPR_SHARED2_m33_mask_flexspi1_MASK   (0x800U)
16584 #define CCM_GPR_SHARED2_m33_mask_flexspi1_SHIFT  (11U)
16585 /*! m33_mask_flexspi1 - m33_mask_flexspi1 */
16586 #define CCM_GPR_SHARED2_m33_mask_flexspi1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_flexspi1_MASK)
16587 
16588 #define CCM_GPR_SHARED2_m33_mask_flexspi2_MASK   (0x1000U)
16589 #define CCM_GPR_SHARED2_m33_mask_flexspi2_SHIFT  (12U)
16590 /*! m33_mask_flexspi2 - m33_mask_flexspi2 */
16591 #define CCM_GPR_SHARED2_m33_mask_flexspi2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_flexspi2_MASK)
16592 
16593 #define CCM_GPR_SHARED2_m33_mask_trdc_MASK       (0x2000U)
16594 #define CCM_GPR_SHARED2_m33_mask_trdc_SHIFT      (13U)
16595 /*! m33_mask_trdc - m33_mask_trdc */
16596 #define CCM_GPR_SHARED2_m33_mask_trdc(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_trdc_SHIFT)) & CCM_GPR_SHARED2_m33_mask_trdc_MASK)
16597 
16598 #define CCM_GPR_SHARED2_m33_mask_semc_MASK       (0x4000U)
16599 #define CCM_GPR_SHARED2_m33_mask_semc_SHIFT      (14U)
16600 /*! m33_mask_semc - m33_mask_semc */
16601 #define CCM_GPR_SHARED2_m33_mask_semc(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_semc_SHIFT)) & CCM_GPR_SHARED2_m33_mask_semc_MASK)
16602 
16603 #define CCM_GPR_SHARED2_m33_mask_iee_MASK        (0x8000U)
16604 #define CCM_GPR_SHARED2_m33_mask_iee_SHIFT       (15U)
16605 /*! m33_mask_iee - m33_mask_iee */
16606 #define CCM_GPR_SHARED2_m33_mask_iee(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_iee_SHIFT)) & CCM_GPR_SHARED2_m33_mask_iee_MASK)
16607 
16608 #define CCM_GPR_SHARED2_m33_mask_gpio1_MASK      (0x10000U)
16609 #define CCM_GPR_SHARED2_m33_mask_gpio1_SHIFT     (16U)
16610 /*! m33_mask_gpio1 - m33_mask_gpio1 */
16611 #define CCM_GPR_SHARED2_m33_mask_gpio1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio1_MASK)
16612 
16613 #define CCM_GPR_SHARED2_m33_mask_gpio2_MASK      (0x20000U)
16614 #define CCM_GPR_SHARED2_m33_mask_gpio2_SHIFT     (17U)
16615 /*! m33_mask_gpio2 - m33_mask_gpio2 */
16616 #define CCM_GPR_SHARED2_m33_mask_gpio2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio2_MASK)
16617 
16618 #define CCM_GPR_SHARED2_m33_mask_gpio3_MASK      (0x40000U)
16619 #define CCM_GPR_SHARED2_m33_mask_gpio3_SHIFT     (18U)
16620 /*! m33_mask_gpio3 - m33_mask_gpio3 */
16621 #define CCM_GPR_SHARED2_m33_mask_gpio3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio3_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio3_MASK)
16622 
16623 #define CCM_GPR_SHARED2_m33_mask_gpio4_MASK      (0x80000U)
16624 #define CCM_GPR_SHARED2_m33_mask_gpio4_SHIFT     (19U)
16625 /*! m33_mask_gpio4 - m33_mask_gpio4 */
16626 #define CCM_GPR_SHARED2_m33_mask_gpio4(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio4_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio4_MASK)
16627 
16628 #define CCM_GPR_SHARED2_m33_mask_gpio5_MASK      (0x100000U)
16629 #define CCM_GPR_SHARED2_m33_mask_gpio5_SHIFT     (20U)
16630 /*! m33_mask_gpio5 - m33_mask_gpio5 */
16631 #define CCM_GPR_SHARED2_m33_mask_gpio5(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio5_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio5_MASK)
16632 
16633 #define CCM_GPR_SHARED2_m33_mask_gpio6_MASK      (0x200000U)
16634 #define CCM_GPR_SHARED2_m33_mask_gpio6_SHIFT     (21U)
16635 /*! m33_mask_gpio6 - m33_mask_gpio6 */
16636 #define CCM_GPR_SHARED2_m33_mask_gpio6(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_gpio6_SHIFT)) & CCM_GPR_SHARED2_m33_mask_gpio6_MASK)
16637 
16638 #define CCM_GPR_SHARED2_m33_mask_flexio1_MASK    (0x400000U)
16639 #define CCM_GPR_SHARED2_m33_mask_flexio1_SHIFT   (22U)
16640 /*! m33_mask_flexio1 - m33_mask_flexio1 */
16641 #define CCM_GPR_SHARED2_m33_mask_flexio1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_flexio1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_flexio1_MASK)
16642 
16643 #define CCM_GPR_SHARED2_m33_mask_flexio2_MASK    (0x800000U)
16644 #define CCM_GPR_SHARED2_m33_mask_flexio2_SHIFT   (23U)
16645 /*! m33_mask_flexio2 - m33_mask_flexio2 */
16646 #define CCM_GPR_SHARED2_m33_mask_flexio2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_flexio2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_flexio2_MASK)
16647 
16648 #define CCM_GPR_SHARED2_m33_mask_lpit1_MASK      (0x1000000U)
16649 #define CCM_GPR_SHARED2_m33_mask_lpit1_SHIFT     (24U)
16650 /*! m33_mask_lpit1 - m33_mask_lpit1 */
16651 #define CCM_GPR_SHARED2_m33_mask_lpit1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_lpit1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_lpit1_MASK)
16652 
16653 #define CCM_GPR_SHARED2_m33_mask_lpit2_MASK      (0x2000000U)
16654 #define CCM_GPR_SHARED2_m33_mask_lpit2_SHIFT     (25U)
16655 /*! m33_mask_lpit2 - m33_mask_lpit2 */
16656 #define CCM_GPR_SHARED2_m33_mask_lpit2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_lpit2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_lpit2_MASK)
16657 
16658 #define CCM_GPR_SHARED2_m33_mask_lpit3_MASK      (0x4000000U)
16659 #define CCM_GPR_SHARED2_m33_mask_lpit3_SHIFT     (26U)
16660 /*! m33_mask_lpit3 - m33_mask_lpit3 */
16661 #define CCM_GPR_SHARED2_m33_mask_lpit3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_lpit3_SHIFT)) & CCM_GPR_SHARED2_m33_mask_lpit3_MASK)
16662 
16663 #define CCM_GPR_SHARED2_m33_mask_tpm1_MASK       (0x8000000U)
16664 #define CCM_GPR_SHARED2_m33_mask_tpm1_SHIFT      (27U)
16665 /*! m33_mask_tpm1 - m33_mask_tpm1 */
16666 #define CCM_GPR_SHARED2_m33_mask_tpm1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_tpm1_SHIFT)) & CCM_GPR_SHARED2_m33_mask_tpm1_MASK)
16667 
16668 #define CCM_GPR_SHARED2_m33_mask_tpm2_MASK       (0x10000000U)
16669 #define CCM_GPR_SHARED2_m33_mask_tpm2_SHIFT      (28U)
16670 /*! m33_mask_tpm2 - m33_mask_tpm2 */
16671 #define CCM_GPR_SHARED2_m33_mask_tpm2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_tpm2_SHIFT)) & CCM_GPR_SHARED2_m33_mask_tpm2_MASK)
16672 
16673 #define CCM_GPR_SHARED2_m33_mask_tpm3_MASK       (0x20000000U)
16674 #define CCM_GPR_SHARED2_m33_mask_tpm3_SHIFT      (29U)
16675 /*! m33_mask_tpm3 - m33_mask_tpm3 */
16676 #define CCM_GPR_SHARED2_m33_mask_tpm3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_tpm3_SHIFT)) & CCM_GPR_SHARED2_m33_mask_tpm3_MASK)
16677 
16678 #define CCM_GPR_SHARED2_m33_mask_tpm4_MASK       (0x40000000U)
16679 #define CCM_GPR_SHARED2_m33_mask_tpm4_SHIFT      (30U)
16680 /*! m33_mask_tpm4 - m33_mask_tpm4 */
16681 #define CCM_GPR_SHARED2_m33_mask_tpm4(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_tpm4_SHIFT)) & CCM_GPR_SHARED2_m33_mask_tpm4_MASK)
16682 
16683 #define CCM_GPR_SHARED2_m33_mask_tpm5_MASK       (0x80000000U)
16684 #define CCM_GPR_SHARED2_m33_mask_tpm5_SHIFT      (31U)
16685 /*! m33_mask_tpm5 - m33_mask_tpm5 */
16686 #define CCM_GPR_SHARED2_m33_mask_tpm5(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_m33_mask_tpm5_SHIFT)) & CCM_GPR_SHARED2_m33_mask_tpm5_MASK)
16687 /*! @} */
16688 
16689 /*! @name GPR_SHARED2_SET - General Purpose Register */
16690 /*! @{ */
16691 
16692 #define CCM_GPR_SHARED2_SET_m33_mask_cm7_MASK    (0x1U)
16693 #define CCM_GPR_SHARED2_SET_m33_mask_cm7_SHIFT   (0U)
16694 /*! m33_mask_cm7 - m33_mask_cm7 */
16695 #define CCM_GPR_SHARED2_SET_m33_mask_cm7(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_cm7_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_cm7_MASK)
16696 
16697 #define CCM_GPR_SHARED2_SET_m33_mask_cm33_MASK   (0x2U)
16698 #define CCM_GPR_SHARED2_SET_m33_mask_cm33_SHIFT  (1U)
16699 /*! m33_mask_cm33 - m33_mask_cm33 */
16700 #define CCM_GPR_SHARED2_SET_m33_mask_cm33(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_cm33_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_cm33_MASK)
16701 
16702 #define CCM_GPR_SHARED2_SET_m33_mask_edma3_MASK  (0x4U)
16703 #define CCM_GPR_SHARED2_SET_m33_mask_edma3_SHIFT (2U)
16704 /*! m33_mask_edma3 - m33_mask_edma3 */
16705 #define CCM_GPR_SHARED2_SET_m33_mask_edma3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_edma3_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_edma3_MASK)
16706 
16707 #define CCM_GPR_SHARED2_SET_m33_mask_edma4_MASK  (0x8U)
16708 #define CCM_GPR_SHARED2_SET_m33_mask_edma4_SHIFT (3U)
16709 /*! m33_mask_edma4 - m33_mask_edma4 */
16710 #define CCM_GPR_SHARED2_SET_m33_mask_edma4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_edma4_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_edma4_MASK)
16711 
16712 #define CCM_GPR_SHARED2_SET_m33_mask_netc_MASK   (0x10U)
16713 #define CCM_GPR_SHARED2_SET_m33_mask_netc_SHIFT  (4U)
16714 /*! m33_mask_netc - m33_mask_netc */
16715 #define CCM_GPR_SHARED2_SET_m33_mask_netc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_netc_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_netc_MASK)
16716 
16717 #define CCM_GPR_SHARED2_SET_m33_mask_sim_aon_MASK (0x100U)
16718 #define CCM_GPR_SHARED2_SET_m33_mask_sim_aon_SHIFT (8U)
16719 /*! m33_mask_sim_aon - m33_mask_sim_aon */
16720 #define CCM_GPR_SHARED2_SET_m33_mask_sim_aon(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_sim_aon_MASK)
16721 
16722 #define CCM_GPR_SHARED2_SET_m33_mask_adc1_MASK   (0x200U)
16723 #define CCM_GPR_SHARED2_SET_m33_mask_adc1_SHIFT  (9U)
16724 /*! m33_mask_adc1 - m33_mask_adc1 */
16725 #define CCM_GPR_SHARED2_SET_m33_mask_adc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_adc1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_adc1_MASK)
16726 
16727 #define CCM_GPR_SHARED2_SET_m33_mask_adc2_MASK   (0x400U)
16728 #define CCM_GPR_SHARED2_SET_m33_mask_adc2_SHIFT  (10U)
16729 /*! m33_mask_adc2 - m33_mask_adc2 */
16730 #define CCM_GPR_SHARED2_SET_m33_mask_adc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_adc2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_adc2_MASK)
16731 
16732 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi1_MASK (0x800U)
16733 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi1_SHIFT (11U)
16734 /*! m33_mask_flexspi1 - m33_mask_flexspi1 */
16735 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi1(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_flexspi1_MASK)
16736 
16737 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi2_MASK (0x1000U)
16738 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi2_SHIFT (12U)
16739 /*! m33_mask_flexspi2 - m33_mask_flexspi2 */
16740 #define CCM_GPR_SHARED2_SET_m33_mask_flexspi2(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_flexspi2_MASK)
16741 
16742 #define CCM_GPR_SHARED2_SET_m33_mask_trdc_MASK   (0x2000U)
16743 #define CCM_GPR_SHARED2_SET_m33_mask_trdc_SHIFT  (13U)
16744 /*! m33_mask_trdc - m33_mask_trdc */
16745 #define CCM_GPR_SHARED2_SET_m33_mask_trdc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_trdc_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_trdc_MASK)
16746 
16747 #define CCM_GPR_SHARED2_SET_m33_mask_semc_MASK   (0x4000U)
16748 #define CCM_GPR_SHARED2_SET_m33_mask_semc_SHIFT  (14U)
16749 /*! m33_mask_semc - m33_mask_semc */
16750 #define CCM_GPR_SHARED2_SET_m33_mask_semc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_semc_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_semc_MASK)
16751 
16752 #define CCM_GPR_SHARED2_SET_m33_mask_iee_MASK    (0x8000U)
16753 #define CCM_GPR_SHARED2_SET_m33_mask_iee_SHIFT   (15U)
16754 /*! m33_mask_iee - m33_mask_iee */
16755 #define CCM_GPR_SHARED2_SET_m33_mask_iee(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_iee_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_iee_MASK)
16756 
16757 #define CCM_GPR_SHARED2_SET_m33_mask_gpio1_MASK  (0x10000U)
16758 #define CCM_GPR_SHARED2_SET_m33_mask_gpio1_SHIFT (16U)
16759 /*! m33_mask_gpio1 - m33_mask_gpio1 */
16760 #define CCM_GPR_SHARED2_SET_m33_mask_gpio1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio1_MASK)
16761 
16762 #define CCM_GPR_SHARED2_SET_m33_mask_gpio2_MASK  (0x20000U)
16763 #define CCM_GPR_SHARED2_SET_m33_mask_gpio2_SHIFT (17U)
16764 /*! m33_mask_gpio2 - m33_mask_gpio2 */
16765 #define CCM_GPR_SHARED2_SET_m33_mask_gpio2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio2_MASK)
16766 
16767 #define CCM_GPR_SHARED2_SET_m33_mask_gpio3_MASK  (0x40000U)
16768 #define CCM_GPR_SHARED2_SET_m33_mask_gpio3_SHIFT (18U)
16769 /*! m33_mask_gpio3 - m33_mask_gpio3 */
16770 #define CCM_GPR_SHARED2_SET_m33_mask_gpio3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio3_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio3_MASK)
16771 
16772 #define CCM_GPR_SHARED2_SET_m33_mask_gpio4_MASK  (0x80000U)
16773 #define CCM_GPR_SHARED2_SET_m33_mask_gpio4_SHIFT (19U)
16774 /*! m33_mask_gpio4 - m33_mask_gpio4 */
16775 #define CCM_GPR_SHARED2_SET_m33_mask_gpio4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio4_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio4_MASK)
16776 
16777 #define CCM_GPR_SHARED2_SET_m33_mask_gpio5_MASK  (0x100000U)
16778 #define CCM_GPR_SHARED2_SET_m33_mask_gpio5_SHIFT (20U)
16779 /*! m33_mask_gpio5 - m33_mask_gpio5 */
16780 #define CCM_GPR_SHARED2_SET_m33_mask_gpio5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio5_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio5_MASK)
16781 
16782 #define CCM_GPR_SHARED2_SET_m33_mask_gpio6_MASK  (0x200000U)
16783 #define CCM_GPR_SHARED2_SET_m33_mask_gpio6_SHIFT (21U)
16784 /*! m33_mask_gpio6 - m33_mask_gpio6 */
16785 #define CCM_GPR_SHARED2_SET_m33_mask_gpio6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_gpio6_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_gpio6_MASK)
16786 
16787 #define CCM_GPR_SHARED2_SET_m33_mask_flexio1_MASK (0x400000U)
16788 #define CCM_GPR_SHARED2_SET_m33_mask_flexio1_SHIFT (22U)
16789 /*! m33_mask_flexio1 - m33_mask_flexio1 */
16790 #define CCM_GPR_SHARED2_SET_m33_mask_flexio1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_flexio1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_flexio1_MASK)
16791 
16792 #define CCM_GPR_SHARED2_SET_m33_mask_flexio2_MASK (0x800000U)
16793 #define CCM_GPR_SHARED2_SET_m33_mask_flexio2_SHIFT (23U)
16794 /*! m33_mask_flexio2 - m33_mask_flexio2 */
16795 #define CCM_GPR_SHARED2_SET_m33_mask_flexio2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_flexio2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_flexio2_MASK)
16796 
16797 #define CCM_GPR_SHARED2_SET_m33_mask_lpit1_MASK  (0x1000000U)
16798 #define CCM_GPR_SHARED2_SET_m33_mask_lpit1_SHIFT (24U)
16799 /*! m33_mask_lpit1 - m33_mask_lpit1 */
16800 #define CCM_GPR_SHARED2_SET_m33_mask_lpit1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_lpit1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_lpit1_MASK)
16801 
16802 #define CCM_GPR_SHARED2_SET_m33_mask_lpit2_MASK  (0x2000000U)
16803 #define CCM_GPR_SHARED2_SET_m33_mask_lpit2_SHIFT (25U)
16804 /*! m33_mask_lpit2 - m33_mask_lpit2 */
16805 #define CCM_GPR_SHARED2_SET_m33_mask_lpit2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_lpit2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_lpit2_MASK)
16806 
16807 #define CCM_GPR_SHARED2_SET_m33_mask_lpit3_MASK  (0x4000000U)
16808 #define CCM_GPR_SHARED2_SET_m33_mask_lpit3_SHIFT (26U)
16809 /*! m33_mask_lpit3 - m33_mask_lpit3 */
16810 #define CCM_GPR_SHARED2_SET_m33_mask_lpit3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_lpit3_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_lpit3_MASK)
16811 
16812 #define CCM_GPR_SHARED2_SET_m33_mask_tpm1_MASK   (0x8000000U)
16813 #define CCM_GPR_SHARED2_SET_m33_mask_tpm1_SHIFT  (27U)
16814 /*! m33_mask_tpm1 - m33_mask_tpm1 */
16815 #define CCM_GPR_SHARED2_SET_m33_mask_tpm1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_tpm1_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_tpm1_MASK)
16816 
16817 #define CCM_GPR_SHARED2_SET_m33_mask_tpm2_MASK   (0x10000000U)
16818 #define CCM_GPR_SHARED2_SET_m33_mask_tpm2_SHIFT  (28U)
16819 /*! m33_mask_tpm2 - m33_mask_tpm2 */
16820 #define CCM_GPR_SHARED2_SET_m33_mask_tpm2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_tpm2_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_tpm2_MASK)
16821 
16822 #define CCM_GPR_SHARED2_SET_m33_mask_tpm3_MASK   (0x20000000U)
16823 #define CCM_GPR_SHARED2_SET_m33_mask_tpm3_SHIFT  (29U)
16824 /*! m33_mask_tpm3 - m33_mask_tpm3 */
16825 #define CCM_GPR_SHARED2_SET_m33_mask_tpm3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_tpm3_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_tpm3_MASK)
16826 
16827 #define CCM_GPR_SHARED2_SET_m33_mask_tpm4_MASK   (0x40000000U)
16828 #define CCM_GPR_SHARED2_SET_m33_mask_tpm4_SHIFT  (30U)
16829 /*! m33_mask_tpm4 - m33_mask_tpm4 */
16830 #define CCM_GPR_SHARED2_SET_m33_mask_tpm4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_tpm4_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_tpm4_MASK)
16831 
16832 #define CCM_GPR_SHARED2_SET_m33_mask_tpm5_MASK   (0x80000000U)
16833 #define CCM_GPR_SHARED2_SET_m33_mask_tpm5_SHIFT  (31U)
16834 /*! m33_mask_tpm5 - m33_mask_tpm5 */
16835 #define CCM_GPR_SHARED2_SET_m33_mask_tpm5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_SET_m33_mask_tpm5_SHIFT)) & CCM_GPR_SHARED2_SET_m33_mask_tpm5_MASK)
16836 /*! @} */
16837 
16838 /*! @name GPR_SHARED2_CLR - General Purpose Register */
16839 /*! @{ */
16840 
16841 #define CCM_GPR_SHARED2_CLR_m33_mask_cm7_MASK    (0x1U)
16842 #define CCM_GPR_SHARED2_CLR_m33_mask_cm7_SHIFT   (0U)
16843 /*! m33_mask_cm7 - m33_mask_cm7 */
16844 #define CCM_GPR_SHARED2_CLR_m33_mask_cm7(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_cm7_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_cm7_MASK)
16845 
16846 #define CCM_GPR_SHARED2_CLR_m33_mask_cm33_MASK   (0x2U)
16847 #define CCM_GPR_SHARED2_CLR_m33_mask_cm33_SHIFT  (1U)
16848 /*! m33_mask_cm33 - m33_mask_cm33 */
16849 #define CCM_GPR_SHARED2_CLR_m33_mask_cm33(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_cm33_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_cm33_MASK)
16850 
16851 #define CCM_GPR_SHARED2_CLR_m33_mask_edma3_MASK  (0x4U)
16852 #define CCM_GPR_SHARED2_CLR_m33_mask_edma3_SHIFT (2U)
16853 /*! m33_mask_edma3 - m33_mask_edma3 */
16854 #define CCM_GPR_SHARED2_CLR_m33_mask_edma3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_edma3_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_edma3_MASK)
16855 
16856 #define CCM_GPR_SHARED2_CLR_m33_mask_edma4_MASK  (0x8U)
16857 #define CCM_GPR_SHARED2_CLR_m33_mask_edma4_SHIFT (3U)
16858 /*! m33_mask_edma4 - m33_mask_edma4 */
16859 #define CCM_GPR_SHARED2_CLR_m33_mask_edma4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_edma4_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_edma4_MASK)
16860 
16861 #define CCM_GPR_SHARED2_CLR_m33_mask_netc_MASK   (0x10U)
16862 #define CCM_GPR_SHARED2_CLR_m33_mask_netc_SHIFT  (4U)
16863 /*! m33_mask_netc - m33_mask_netc */
16864 #define CCM_GPR_SHARED2_CLR_m33_mask_netc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_netc_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_netc_MASK)
16865 
16866 #define CCM_GPR_SHARED2_CLR_m33_mask_sim_aon_MASK (0x100U)
16867 #define CCM_GPR_SHARED2_CLR_m33_mask_sim_aon_SHIFT (8U)
16868 /*! m33_mask_sim_aon - m33_mask_sim_aon */
16869 #define CCM_GPR_SHARED2_CLR_m33_mask_sim_aon(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_sim_aon_MASK)
16870 
16871 #define CCM_GPR_SHARED2_CLR_m33_mask_adc1_MASK   (0x200U)
16872 #define CCM_GPR_SHARED2_CLR_m33_mask_adc1_SHIFT  (9U)
16873 /*! m33_mask_adc1 - m33_mask_adc1 */
16874 #define CCM_GPR_SHARED2_CLR_m33_mask_adc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_adc1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_adc1_MASK)
16875 
16876 #define CCM_GPR_SHARED2_CLR_m33_mask_adc2_MASK   (0x400U)
16877 #define CCM_GPR_SHARED2_CLR_m33_mask_adc2_SHIFT  (10U)
16878 /*! m33_mask_adc2 - m33_mask_adc2 */
16879 #define CCM_GPR_SHARED2_CLR_m33_mask_adc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_adc2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_adc2_MASK)
16880 
16881 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi1_MASK (0x800U)
16882 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi1_SHIFT (11U)
16883 /*! m33_mask_flexspi1 - m33_mask_flexspi1 */
16884 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi1(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_flexspi1_MASK)
16885 
16886 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi2_MASK (0x1000U)
16887 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi2_SHIFT (12U)
16888 /*! m33_mask_flexspi2 - m33_mask_flexspi2 */
16889 #define CCM_GPR_SHARED2_CLR_m33_mask_flexspi2(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_flexspi2_MASK)
16890 
16891 #define CCM_GPR_SHARED2_CLR_m33_mask_trdc_MASK   (0x2000U)
16892 #define CCM_GPR_SHARED2_CLR_m33_mask_trdc_SHIFT  (13U)
16893 /*! m33_mask_trdc - m33_mask_trdc */
16894 #define CCM_GPR_SHARED2_CLR_m33_mask_trdc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_trdc_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_trdc_MASK)
16895 
16896 #define CCM_GPR_SHARED2_CLR_m33_mask_semc_MASK   (0x4000U)
16897 #define CCM_GPR_SHARED2_CLR_m33_mask_semc_SHIFT  (14U)
16898 /*! m33_mask_semc - m33_mask_semc */
16899 #define CCM_GPR_SHARED2_CLR_m33_mask_semc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_semc_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_semc_MASK)
16900 
16901 #define CCM_GPR_SHARED2_CLR_m33_mask_iee_MASK    (0x8000U)
16902 #define CCM_GPR_SHARED2_CLR_m33_mask_iee_SHIFT   (15U)
16903 /*! m33_mask_iee - m33_mask_iee */
16904 #define CCM_GPR_SHARED2_CLR_m33_mask_iee(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_iee_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_iee_MASK)
16905 
16906 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio1_MASK  (0x10000U)
16907 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio1_SHIFT (16U)
16908 /*! m33_mask_gpio1 - m33_mask_gpio1 */
16909 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio1_MASK)
16910 
16911 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio2_MASK  (0x20000U)
16912 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio2_SHIFT (17U)
16913 /*! m33_mask_gpio2 - m33_mask_gpio2 */
16914 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio2_MASK)
16915 
16916 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio3_MASK  (0x40000U)
16917 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio3_SHIFT (18U)
16918 /*! m33_mask_gpio3 - m33_mask_gpio3 */
16919 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio3_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio3_MASK)
16920 
16921 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio4_MASK  (0x80000U)
16922 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio4_SHIFT (19U)
16923 /*! m33_mask_gpio4 - m33_mask_gpio4 */
16924 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio4_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio4_MASK)
16925 
16926 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio5_MASK  (0x100000U)
16927 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio5_SHIFT (20U)
16928 /*! m33_mask_gpio5 - m33_mask_gpio5 */
16929 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio5_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio5_MASK)
16930 
16931 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio6_MASK  (0x200000U)
16932 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio6_SHIFT (21U)
16933 /*! m33_mask_gpio6 - m33_mask_gpio6 */
16934 #define CCM_GPR_SHARED2_CLR_m33_mask_gpio6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_gpio6_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_gpio6_MASK)
16935 
16936 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio1_MASK (0x400000U)
16937 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio1_SHIFT (22U)
16938 /*! m33_mask_flexio1 - m33_mask_flexio1 */
16939 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_flexio1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_flexio1_MASK)
16940 
16941 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio2_MASK (0x800000U)
16942 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio2_SHIFT (23U)
16943 /*! m33_mask_flexio2 - m33_mask_flexio2 */
16944 #define CCM_GPR_SHARED2_CLR_m33_mask_flexio2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_flexio2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_flexio2_MASK)
16945 
16946 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit1_MASK  (0x1000000U)
16947 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit1_SHIFT (24U)
16948 /*! m33_mask_lpit1 - m33_mask_lpit1 */
16949 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_lpit1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_lpit1_MASK)
16950 
16951 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit2_MASK  (0x2000000U)
16952 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit2_SHIFT (25U)
16953 /*! m33_mask_lpit2 - m33_mask_lpit2 */
16954 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_lpit2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_lpit2_MASK)
16955 
16956 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit3_MASK  (0x4000000U)
16957 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit3_SHIFT (26U)
16958 /*! m33_mask_lpit3 - m33_mask_lpit3 */
16959 #define CCM_GPR_SHARED2_CLR_m33_mask_lpit3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_lpit3_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_lpit3_MASK)
16960 
16961 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm1_MASK   (0x8000000U)
16962 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm1_SHIFT  (27U)
16963 /*! m33_mask_tpm1 - m33_mask_tpm1 */
16964 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_tpm1_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_tpm1_MASK)
16965 
16966 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm2_MASK   (0x10000000U)
16967 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm2_SHIFT  (28U)
16968 /*! m33_mask_tpm2 - m33_mask_tpm2 */
16969 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_tpm2_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_tpm2_MASK)
16970 
16971 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm3_MASK   (0x20000000U)
16972 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm3_SHIFT  (29U)
16973 /*! m33_mask_tpm3 - m33_mask_tpm3 */
16974 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_tpm3_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_tpm3_MASK)
16975 
16976 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm4_MASK   (0x40000000U)
16977 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm4_SHIFT  (30U)
16978 /*! m33_mask_tpm4 - m33_mask_tpm4 */
16979 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_tpm4_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_tpm4_MASK)
16980 
16981 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm5_MASK   (0x80000000U)
16982 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm5_SHIFT  (31U)
16983 /*! m33_mask_tpm5 - m33_mask_tpm5 */
16984 #define CCM_GPR_SHARED2_CLR_m33_mask_tpm5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_CLR_m33_mask_tpm5_SHIFT)) & CCM_GPR_SHARED2_CLR_m33_mask_tpm5_MASK)
16985 /*! @} */
16986 
16987 /*! @name GPR_SHARED2_TOG - General Purpose Register */
16988 /*! @{ */
16989 
16990 #define CCM_GPR_SHARED2_TOG_m33_mask_cm7_MASK    (0x1U)
16991 #define CCM_GPR_SHARED2_TOG_m33_mask_cm7_SHIFT   (0U)
16992 /*! m33_mask_cm7 - m33_mask_cm7 */
16993 #define CCM_GPR_SHARED2_TOG_m33_mask_cm7(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_cm7_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_cm7_MASK)
16994 
16995 #define CCM_GPR_SHARED2_TOG_m33_mask_cm33_MASK   (0x2U)
16996 #define CCM_GPR_SHARED2_TOG_m33_mask_cm33_SHIFT  (1U)
16997 /*! m33_mask_cm33 - m33_mask_cm33 */
16998 #define CCM_GPR_SHARED2_TOG_m33_mask_cm33(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_cm33_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_cm33_MASK)
16999 
17000 #define CCM_GPR_SHARED2_TOG_m33_mask_edma3_MASK  (0x4U)
17001 #define CCM_GPR_SHARED2_TOG_m33_mask_edma3_SHIFT (2U)
17002 /*! m33_mask_edma3 - m33_mask_edma3 */
17003 #define CCM_GPR_SHARED2_TOG_m33_mask_edma3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_edma3_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_edma3_MASK)
17004 
17005 #define CCM_GPR_SHARED2_TOG_m33_mask_edma4_MASK  (0x8U)
17006 #define CCM_GPR_SHARED2_TOG_m33_mask_edma4_SHIFT (3U)
17007 /*! m33_mask_edma4 - m33_mask_edma4 */
17008 #define CCM_GPR_SHARED2_TOG_m33_mask_edma4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_edma4_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_edma4_MASK)
17009 
17010 #define CCM_GPR_SHARED2_TOG_m33_mask_netc_MASK   (0x10U)
17011 #define CCM_GPR_SHARED2_TOG_m33_mask_netc_SHIFT  (4U)
17012 /*! m33_mask_netc - m33_mask_netc */
17013 #define CCM_GPR_SHARED2_TOG_m33_mask_netc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_netc_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_netc_MASK)
17014 
17015 #define CCM_GPR_SHARED2_TOG_m33_mask_sim_aon_MASK (0x100U)
17016 #define CCM_GPR_SHARED2_TOG_m33_mask_sim_aon_SHIFT (8U)
17017 /*! m33_mask_sim_aon - m33_mask_sim_aon */
17018 #define CCM_GPR_SHARED2_TOG_m33_mask_sim_aon(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_sim_aon_MASK)
17019 
17020 #define CCM_GPR_SHARED2_TOG_m33_mask_adc1_MASK   (0x200U)
17021 #define CCM_GPR_SHARED2_TOG_m33_mask_adc1_SHIFT  (9U)
17022 /*! m33_mask_adc1 - m33_mask_adc1 */
17023 #define CCM_GPR_SHARED2_TOG_m33_mask_adc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_adc1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_adc1_MASK)
17024 
17025 #define CCM_GPR_SHARED2_TOG_m33_mask_adc2_MASK   (0x400U)
17026 #define CCM_GPR_SHARED2_TOG_m33_mask_adc2_SHIFT  (10U)
17027 /*! m33_mask_adc2 - m33_mask_adc2 */
17028 #define CCM_GPR_SHARED2_TOG_m33_mask_adc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_adc2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_adc2_MASK)
17029 
17030 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi1_MASK (0x800U)
17031 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi1_SHIFT (11U)
17032 /*! m33_mask_flexspi1 - m33_mask_flexspi1 */
17033 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi1(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_flexspi1_MASK)
17034 
17035 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi2_MASK (0x1000U)
17036 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi2_SHIFT (12U)
17037 /*! m33_mask_flexspi2 - m33_mask_flexspi2 */
17038 #define CCM_GPR_SHARED2_TOG_m33_mask_flexspi2(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_flexspi2_MASK)
17039 
17040 #define CCM_GPR_SHARED2_TOG_m33_mask_trdc_MASK   (0x2000U)
17041 #define CCM_GPR_SHARED2_TOG_m33_mask_trdc_SHIFT  (13U)
17042 /*! m33_mask_trdc - m33_mask_trdc */
17043 #define CCM_GPR_SHARED2_TOG_m33_mask_trdc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_trdc_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_trdc_MASK)
17044 
17045 #define CCM_GPR_SHARED2_TOG_m33_mask_semc_MASK   (0x4000U)
17046 #define CCM_GPR_SHARED2_TOG_m33_mask_semc_SHIFT  (14U)
17047 /*! m33_mask_semc - m33_mask_semc */
17048 #define CCM_GPR_SHARED2_TOG_m33_mask_semc(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_semc_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_semc_MASK)
17049 
17050 #define CCM_GPR_SHARED2_TOG_m33_mask_iee_MASK    (0x8000U)
17051 #define CCM_GPR_SHARED2_TOG_m33_mask_iee_SHIFT   (15U)
17052 /*! m33_mask_iee - m33_mask_iee */
17053 #define CCM_GPR_SHARED2_TOG_m33_mask_iee(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_iee_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_iee_MASK)
17054 
17055 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio1_MASK  (0x10000U)
17056 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio1_SHIFT (16U)
17057 /*! m33_mask_gpio1 - m33_mask_gpio1 */
17058 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio1_MASK)
17059 
17060 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio2_MASK  (0x20000U)
17061 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio2_SHIFT (17U)
17062 /*! m33_mask_gpio2 - m33_mask_gpio2 */
17063 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio2_MASK)
17064 
17065 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio3_MASK  (0x40000U)
17066 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio3_SHIFT (18U)
17067 /*! m33_mask_gpio3 - m33_mask_gpio3 */
17068 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio3_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio3_MASK)
17069 
17070 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio4_MASK  (0x80000U)
17071 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio4_SHIFT (19U)
17072 /*! m33_mask_gpio4 - m33_mask_gpio4 */
17073 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio4_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio4_MASK)
17074 
17075 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio5_MASK  (0x100000U)
17076 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio5_SHIFT (20U)
17077 /*! m33_mask_gpio5 - m33_mask_gpio5 */
17078 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio5_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio5_MASK)
17079 
17080 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio6_MASK  (0x200000U)
17081 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio6_SHIFT (21U)
17082 /*! m33_mask_gpio6 - m33_mask_gpio6 */
17083 #define CCM_GPR_SHARED2_TOG_m33_mask_gpio6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_gpio6_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_gpio6_MASK)
17084 
17085 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio1_MASK (0x400000U)
17086 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio1_SHIFT (22U)
17087 /*! m33_mask_flexio1 - m33_mask_flexio1 */
17088 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_flexio1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_flexio1_MASK)
17089 
17090 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio2_MASK (0x800000U)
17091 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio2_SHIFT (23U)
17092 /*! m33_mask_flexio2 - m33_mask_flexio2 */
17093 #define CCM_GPR_SHARED2_TOG_m33_mask_flexio2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_flexio2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_flexio2_MASK)
17094 
17095 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit1_MASK  (0x1000000U)
17096 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit1_SHIFT (24U)
17097 /*! m33_mask_lpit1 - m33_mask_lpit1 */
17098 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_lpit1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_lpit1_MASK)
17099 
17100 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit2_MASK  (0x2000000U)
17101 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit2_SHIFT (25U)
17102 /*! m33_mask_lpit2 - m33_mask_lpit2 */
17103 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_lpit2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_lpit2_MASK)
17104 
17105 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit3_MASK  (0x4000000U)
17106 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit3_SHIFT (26U)
17107 /*! m33_mask_lpit3 - m33_mask_lpit3 */
17108 #define CCM_GPR_SHARED2_TOG_m33_mask_lpit3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_lpit3_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_lpit3_MASK)
17109 
17110 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm1_MASK   (0x8000000U)
17111 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm1_SHIFT  (27U)
17112 /*! m33_mask_tpm1 - m33_mask_tpm1 */
17113 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_tpm1_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_tpm1_MASK)
17114 
17115 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm2_MASK   (0x10000000U)
17116 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm2_SHIFT  (28U)
17117 /*! m33_mask_tpm2 - m33_mask_tpm2 */
17118 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_tpm2_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_tpm2_MASK)
17119 
17120 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm3_MASK   (0x20000000U)
17121 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm3_SHIFT  (29U)
17122 /*! m33_mask_tpm3 - m33_mask_tpm3 */
17123 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_tpm3_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_tpm3_MASK)
17124 
17125 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm4_MASK   (0x40000000U)
17126 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm4_SHIFT  (30U)
17127 /*! m33_mask_tpm4 - m33_mask_tpm4 */
17128 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_tpm4_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_tpm4_MASK)
17129 
17130 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm5_MASK   (0x80000000U)
17131 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm5_SHIFT  (31U)
17132 /*! m33_mask_tpm5 - m33_mask_tpm5 */
17133 #define CCM_GPR_SHARED2_TOG_m33_mask_tpm5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_TOG_m33_mask_tpm5_SHIFT)) & CCM_GPR_SHARED2_TOG_m33_mask_tpm5_MASK)
17134 /*! @} */
17135 
17136 /*! @name GPR_SHARED2_AUTHEN - GPR access control */
17137 /*! @{ */
17138 
17139 #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK      (0x100U)
17140 #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT     (8U)
17141 /*! TZ_USER - User access permission
17142  *  0b1..Registers of shared GPR slice can be changed in user mode.
17143  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
17144  */
17145 #define CCM_GPR_SHARED2_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK)
17146 
17147 #define CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK        (0x200U)
17148 #define CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT       (9U)
17149 /*! TZ_NS - Non-secure access permission
17150  *  0b0..Cannot be changed in Non-secure mode.
17151  *  0b1..Can be changed in Non-secure mode.
17152  */
17153 #define CCM_GPR_SHARED2_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK)
17154 
17155 #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK      (0x800U)
17156 #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT     (11U)
17157 /*! LOCK_TZ - Lock TrustZone settings
17158  *  0b0..TrustZone settings is not locked.
17159  *  0b1..TrustZone settings is locked.
17160  */
17161 #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK)
17162 
17163 #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK    (0x8000U)
17164 #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT   (15U)
17165 /*! LOCK_LIST - Lock white list
17166  *  0b0..Whitelist is not locked.
17167  *  0b1..Whitelist is locked.
17168  */
17169 #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK)
17170 
17171 #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
17172 #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT  (16U)
17173 /*! WHITE_LIST - Whitelist settings */
17174 #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK)
17175 /*! @} */
17176 
17177 /*! @name GPR_SHARED2_AUTHEN_SET - GPR access control */
17178 /*! @{ */
17179 
17180 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_USER_MASK  (0x100U)
17181 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_USER_SHIFT (8U)
17182 /*! TZ_USER - User access permission */
17183 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_SET_TZ_USER_MASK)
17184 
17185 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_NS_MASK    (0x200U)
17186 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_NS_SHIFT   (9U)
17187 /*! TZ_NS - Non-secure access permission */
17188 #define CCM_GPR_SHARED2_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_SET_TZ_NS_MASK)
17189 
17190 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
17191 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
17192 /*! LOCK_TZ - Lock TrustZone settings */
17193 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_SET_LOCK_TZ_MASK)
17194 
17195 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
17196 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
17197 /*! LOCK_LIST - Lock white list */
17198 #define CCM_GPR_SHARED2_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_SET_LOCK_LIST_MASK)
17199 
17200 #define CCM_GPR_SHARED2_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
17201 #define CCM_GPR_SHARED2_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
17202 /*! WHITE_LIST - Whitelist settings */
17203 #define CCM_GPR_SHARED2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_SET_WHITE_LIST_MASK)
17204 /*! @} */
17205 
17206 /*! @name GPR_SHARED2_AUTHEN_CLR - GPR access control */
17207 /*! @{ */
17208 
17209 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
17210 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_USER_SHIFT (8U)
17211 /*! TZ_USER - User access permission */
17212 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_CLR_TZ_USER_MASK)
17213 
17214 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
17215 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
17216 /*! TZ_NS - Non-secure access permission */
17217 #define CCM_GPR_SHARED2_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_CLR_TZ_NS_MASK)
17218 
17219 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
17220 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
17221 /*! LOCK_TZ - Lock TrustZone settings */
17222 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_TZ_MASK)
17223 
17224 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
17225 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
17226 /*! LOCK_LIST - Lock white list */
17227 #define CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_CLR_LOCK_LIST_MASK)
17228 
17229 #define CCM_GPR_SHARED2_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
17230 #define CCM_GPR_SHARED2_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
17231 /*! WHITE_LIST - Whitelist settings */
17232 #define CCM_GPR_SHARED2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_CLR_WHITE_LIST_MASK)
17233 /*! @} */
17234 
17235 /*! @name GPR_SHARED2_AUTHEN_TOG - GPR access control */
17236 /*! @{ */
17237 
17238 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
17239 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_USER_SHIFT (8U)
17240 /*! TZ_USER - User access permission */
17241 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TOG_TZ_USER_MASK)
17242 
17243 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
17244 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
17245 /*! TZ_NS - Non-secure access permission */
17246 #define CCM_GPR_SHARED2_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TOG_TZ_NS_MASK)
17247 
17248 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
17249 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
17250 /*! LOCK_TZ - Lock TrustZone settings */
17251 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_TZ_MASK)
17252 
17253 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
17254 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
17255 /*! LOCK_LIST - Lock white list */
17256 #define CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TOG_LOCK_LIST_MASK)
17257 
17258 #define CCM_GPR_SHARED2_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
17259 #define CCM_GPR_SHARED2_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
17260 /*! WHITE_LIST - Whitelist settings */
17261 #define CCM_GPR_SHARED2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TOG_WHITE_LIST_MASK)
17262 /*! @} */
17263 
17264 /*! @name GPR_SHARED3 - General Purpose Register */
17265 /*! @{ */
17266 
17267 #define CCM_GPR_SHARED3_m33_mask_tpm6_MASK       (0x1U)
17268 #define CCM_GPR_SHARED3_m33_mask_tpm6_SHIFT      (0U)
17269 /*! m33_mask_tpm6 - m33_mask_tpm6 */
17270 #define CCM_GPR_SHARED3_m33_mask_tpm6(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_tpm6_SHIFT)) & CCM_GPR_SHARED3_m33_mask_tpm6_MASK)
17271 
17272 #define CCM_GPR_SHARED3_m33_mask_gpt1_MASK       (0x2U)
17273 #define CCM_GPR_SHARED3_m33_mask_gpt1_SHIFT      (1U)
17274 /*! m33_mask_gpt1 - m33_mask_gpt1 */
17275 #define CCM_GPR_SHARED3_m33_mask_gpt1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_gpt1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_gpt1_MASK)
17276 
17277 #define CCM_GPR_SHARED3_m33_mask_gpt2_MASK       (0x4U)
17278 #define CCM_GPR_SHARED3_m33_mask_gpt2_SHIFT      (2U)
17279 /*! m33_mask_gpt2 - m33_mask_gpt2 */
17280 #define CCM_GPR_SHARED3_m33_mask_gpt2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_gpt2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_gpt2_MASK)
17281 
17282 #define CCM_GPR_SHARED3_m33_mask_can1_MASK       (0x8U)
17283 #define CCM_GPR_SHARED3_m33_mask_can1_SHIFT      (3U)
17284 /*! m33_mask_can1 - m33_mask_can1 */
17285 #define CCM_GPR_SHARED3_m33_mask_can1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_can1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_can1_MASK)
17286 
17287 #define CCM_GPR_SHARED3_m33_mask_can2_MASK       (0x10U)
17288 #define CCM_GPR_SHARED3_m33_mask_can2_SHIFT      (4U)
17289 /*! m33_mask_can2 - m33_mask_can2 */
17290 #define CCM_GPR_SHARED3_m33_mask_can2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_can2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_can2_MASK)
17291 
17292 #define CCM_GPR_SHARED3_m33_mask_can3_MASK       (0x20U)
17293 #define CCM_GPR_SHARED3_m33_mask_can3_SHIFT      (5U)
17294 /*! m33_mask_can3 - m33_mask_can3 */
17295 #define CCM_GPR_SHARED3_m33_mask_can3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_can3_SHIFT)) & CCM_GPR_SHARED3_m33_mask_can3_MASK)
17296 
17297 #define CCM_GPR_SHARED3_m33_mask_lpuart1_MASK    (0x40U)
17298 #define CCM_GPR_SHARED3_m33_mask_lpuart1_SHIFT   (6U)
17299 /*! m33_mask_lpuart1 - m33_mask_lpuart1 */
17300 #define CCM_GPR_SHARED3_m33_mask_lpuart1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart1_MASK)
17301 
17302 #define CCM_GPR_SHARED3_m33_mask_lpuart2_MASK    (0x80U)
17303 #define CCM_GPR_SHARED3_m33_mask_lpuart2_SHIFT   (7U)
17304 /*! m33_mask_lpuart2 - m33_mask_lpuart2 */
17305 #define CCM_GPR_SHARED3_m33_mask_lpuart2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart2_MASK)
17306 
17307 #define CCM_GPR_SHARED3_m33_mask_lpuart3_MASK    (0x100U)
17308 #define CCM_GPR_SHARED3_m33_mask_lpuart3_SHIFT   (8U)
17309 /*! m33_mask_lpuart3 - m33_mask_lpuart3 */
17310 #define CCM_GPR_SHARED3_m33_mask_lpuart3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart3_MASK)
17311 
17312 #define CCM_GPR_SHARED3_m33_mask_lpuart4_MASK    (0x200U)
17313 #define CCM_GPR_SHARED3_m33_mask_lpuart4_SHIFT   (9U)
17314 /*! m33_mask_lpuart4 - m33_mask_lpuart4 */
17315 #define CCM_GPR_SHARED3_m33_mask_lpuart4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart4_MASK)
17316 
17317 #define CCM_GPR_SHARED3_m33_mask_lpuart5_MASK    (0x400U)
17318 #define CCM_GPR_SHARED3_m33_mask_lpuart5_SHIFT   (10U)
17319 /*! m33_mask_lpuart5 - m33_mask_lpuart5 */
17320 #define CCM_GPR_SHARED3_m33_mask_lpuart5(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart5_MASK)
17321 
17322 #define CCM_GPR_SHARED3_m33_mask_lpuart6_MASK    (0x800U)
17323 #define CCM_GPR_SHARED3_m33_mask_lpuart6_SHIFT   (11U)
17324 /*! m33_mask_lpuart6 - m33_mask_lpuart6 */
17325 #define CCM_GPR_SHARED3_m33_mask_lpuart6(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart6_MASK)
17326 
17327 #define CCM_GPR_SHARED3_m33_mask_lpuart7_MASK    (0x1000U)
17328 #define CCM_GPR_SHARED3_m33_mask_lpuart7_SHIFT   (12U)
17329 /*! m33_mask_lpuart7 - m33_mask_lpuart7 */
17330 #define CCM_GPR_SHARED3_m33_mask_lpuart7(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart7_MASK)
17331 
17332 #define CCM_GPR_SHARED3_m33_mask_lpuart8_MASK    (0x2000U)
17333 #define CCM_GPR_SHARED3_m33_mask_lpuart8_SHIFT   (13U)
17334 /*! m33_mask_lpuart8 - m33_mask_lpuart8 */
17335 #define CCM_GPR_SHARED3_m33_mask_lpuart8(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart8_MASK)
17336 
17337 #define CCM_GPR_SHARED3_m33_mask_lpuart9_MASK    (0x4000U)
17338 #define CCM_GPR_SHARED3_m33_mask_lpuart9_SHIFT   (14U)
17339 /*! m33_mask_lpuart9 - m33_mask_lpuart9 */
17340 #define CCM_GPR_SHARED3_m33_mask_lpuart9(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart9_MASK)
17341 
17342 #define CCM_GPR_SHARED3_m33_mask_lpuart10_MASK   (0x8000U)
17343 #define CCM_GPR_SHARED3_m33_mask_lpuart10_SHIFT  (15U)
17344 /*! m33_mask_lpuart10 - m33_mask_lpuart10 */
17345 #define CCM_GPR_SHARED3_m33_mask_lpuart10(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart10_MASK)
17346 
17347 #define CCM_GPR_SHARED3_m33_mask_lpuart11_MASK   (0x10000U)
17348 #define CCM_GPR_SHARED3_m33_mask_lpuart11_SHIFT  (16U)
17349 /*! m33_mask_lpuart11 - m33_mask_lpuart11 */
17350 #define CCM_GPR_SHARED3_m33_mask_lpuart11(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart11_MASK)
17351 
17352 #define CCM_GPR_SHARED3_m33_mask_lpuart12_MASK   (0x20000U)
17353 #define CCM_GPR_SHARED3_m33_mask_lpuart12_SHIFT  (17U)
17354 /*! m33_mask_lpuart12 - m33_mask_lpuart12 */
17355 #define CCM_GPR_SHARED3_m33_mask_lpuart12(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpuart12_MASK)
17356 
17357 #define CCM_GPR_SHARED3_m33_mask_lpi2c1_MASK     (0x40000U)
17358 #define CCM_GPR_SHARED3_m33_mask_lpi2c1_SHIFT    (18U)
17359 /*! m33_mask_lpi2c1 - m33_mask_lpi2c1 */
17360 #define CCM_GPR_SHARED3_m33_mask_lpi2c1(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c1_MASK)
17361 
17362 #define CCM_GPR_SHARED3_m33_mask_lpi2c2_MASK     (0x80000U)
17363 #define CCM_GPR_SHARED3_m33_mask_lpi2c2_SHIFT    (19U)
17364 /*! m33_mask_lpi2c2 - m33_mask_lpi2c2 */
17365 #define CCM_GPR_SHARED3_m33_mask_lpi2c2(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c2_MASK)
17366 
17367 #define CCM_GPR_SHARED3_m33_mask_lpi2c3_MASK     (0x100000U)
17368 #define CCM_GPR_SHARED3_m33_mask_lpi2c3_SHIFT    (20U)
17369 /*! m33_mask_lpi2c3 - m33_mask_lpi2c3 */
17370 #define CCM_GPR_SHARED3_m33_mask_lpi2c3(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c3_MASK)
17371 
17372 #define CCM_GPR_SHARED3_m33_mask_lpi2c4_MASK     (0x200000U)
17373 #define CCM_GPR_SHARED3_m33_mask_lpi2c4_SHIFT    (21U)
17374 /*! m33_mask_lpi2c4 - m33_mask_lpi2c4 */
17375 #define CCM_GPR_SHARED3_m33_mask_lpi2c4(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c4_MASK)
17376 
17377 #define CCM_GPR_SHARED3_m33_mask_lpi2c5_MASK     (0x400000U)
17378 #define CCM_GPR_SHARED3_m33_mask_lpi2c5_SHIFT    (22U)
17379 /*! m33_mask_lpi2c5 - m33_mask_lpi2c5 */
17380 #define CCM_GPR_SHARED3_m33_mask_lpi2c5(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c5_MASK)
17381 
17382 #define CCM_GPR_SHARED3_m33_mask_lpi2c6_MASK     (0x800000U)
17383 #define CCM_GPR_SHARED3_m33_mask_lpi2c6_SHIFT    (23U)
17384 /*! m33_mask_lpi2c6 - m33_mask_lpi2c6 */
17385 #define CCM_GPR_SHARED3_m33_mask_lpi2c6(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpi2c6_MASK)
17386 
17387 #define CCM_GPR_SHARED3_m33_mask_lpspi1_MASK     (0x1000000U)
17388 #define CCM_GPR_SHARED3_m33_mask_lpspi1_SHIFT    (24U)
17389 /*! m33_mask_lpspi1 - m33_mask_lpspi1 */
17390 #define CCM_GPR_SHARED3_m33_mask_lpspi1(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi1_MASK)
17391 
17392 #define CCM_GPR_SHARED3_m33_mask_lpspi2_MASK     (0x2000000U)
17393 #define CCM_GPR_SHARED3_m33_mask_lpspi2_SHIFT    (25U)
17394 /*! m33_mask_lpspi2 - m33_mask_lpspi2 */
17395 #define CCM_GPR_SHARED3_m33_mask_lpspi2(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi2_MASK)
17396 
17397 #define CCM_GPR_SHARED3_m33_mask_lpspi3_MASK     (0x4000000U)
17398 #define CCM_GPR_SHARED3_m33_mask_lpspi3_SHIFT    (26U)
17399 /*! m33_mask_lpspi3 - m33_mask_lpspi3 */
17400 #define CCM_GPR_SHARED3_m33_mask_lpspi3(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi3_MASK)
17401 
17402 #define CCM_GPR_SHARED3_m33_mask_lpspi4_MASK     (0x8000000U)
17403 #define CCM_GPR_SHARED3_m33_mask_lpspi4_SHIFT    (27U)
17404 /*! m33_mask_lpspi4 - m33_mask_lpspi4 */
17405 #define CCM_GPR_SHARED3_m33_mask_lpspi4(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi4_MASK)
17406 
17407 #define CCM_GPR_SHARED3_m33_mask_lpspi5_MASK     (0x10000000U)
17408 #define CCM_GPR_SHARED3_m33_mask_lpspi5_SHIFT    (28U)
17409 /*! m33_mask_lpspi5 - m33_mask_lpspi5 */
17410 #define CCM_GPR_SHARED3_m33_mask_lpspi5(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi5_MASK)
17411 
17412 #define CCM_GPR_SHARED3_m33_mask_lpspi6_MASK     (0x20000000U)
17413 #define CCM_GPR_SHARED3_m33_mask_lpspi6_SHIFT    (29U)
17414 /*! m33_mask_lpspi6 - m33_mask_lpspi6 */
17415 #define CCM_GPR_SHARED3_m33_mask_lpspi6(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED3_m33_mask_lpspi6_MASK)
17416 
17417 #define CCM_GPR_SHARED3_m33_mask_sinc1_MASK      (0x40000000U)
17418 #define CCM_GPR_SHARED3_m33_mask_sinc1_SHIFT     (30U)
17419 /*! m33_mask_sinc1 - m33_mask_sinc1 */
17420 #define CCM_GPR_SHARED3_m33_mask_sinc1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_sinc1_SHIFT)) & CCM_GPR_SHARED3_m33_mask_sinc1_MASK)
17421 
17422 #define CCM_GPR_SHARED3_m33_mask_sinc2_MASK      (0x80000000U)
17423 #define CCM_GPR_SHARED3_m33_mask_sinc2_SHIFT     (31U)
17424 /*! m33_mask_sinc2 - m33_mask_sinc2 */
17425 #define CCM_GPR_SHARED3_m33_mask_sinc2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_m33_mask_sinc2_SHIFT)) & CCM_GPR_SHARED3_m33_mask_sinc2_MASK)
17426 /*! @} */
17427 
17428 /*! @name GPR_SHARED3_SET - General Purpose Register */
17429 /*! @{ */
17430 
17431 #define CCM_GPR_SHARED3_SET_m33_mask_tpm6_MASK   (0x1U)
17432 #define CCM_GPR_SHARED3_SET_m33_mask_tpm6_SHIFT  (0U)
17433 /*! m33_mask_tpm6 - m33_mask_tpm6 */
17434 #define CCM_GPR_SHARED3_SET_m33_mask_tpm6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_tpm6_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_tpm6_MASK)
17435 
17436 #define CCM_GPR_SHARED3_SET_m33_mask_gpt1_MASK   (0x2U)
17437 #define CCM_GPR_SHARED3_SET_m33_mask_gpt1_SHIFT  (1U)
17438 /*! m33_mask_gpt1 - m33_mask_gpt1 */
17439 #define CCM_GPR_SHARED3_SET_m33_mask_gpt1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_gpt1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_gpt1_MASK)
17440 
17441 #define CCM_GPR_SHARED3_SET_m33_mask_gpt2_MASK   (0x4U)
17442 #define CCM_GPR_SHARED3_SET_m33_mask_gpt2_SHIFT  (2U)
17443 /*! m33_mask_gpt2 - m33_mask_gpt2 */
17444 #define CCM_GPR_SHARED3_SET_m33_mask_gpt2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_gpt2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_gpt2_MASK)
17445 
17446 #define CCM_GPR_SHARED3_SET_m33_mask_can1_MASK   (0x8U)
17447 #define CCM_GPR_SHARED3_SET_m33_mask_can1_SHIFT  (3U)
17448 /*! m33_mask_can1 - m33_mask_can1 */
17449 #define CCM_GPR_SHARED3_SET_m33_mask_can1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_can1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_can1_MASK)
17450 
17451 #define CCM_GPR_SHARED3_SET_m33_mask_can2_MASK   (0x10U)
17452 #define CCM_GPR_SHARED3_SET_m33_mask_can2_SHIFT  (4U)
17453 /*! m33_mask_can2 - m33_mask_can2 */
17454 #define CCM_GPR_SHARED3_SET_m33_mask_can2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_can2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_can2_MASK)
17455 
17456 #define CCM_GPR_SHARED3_SET_m33_mask_can3_MASK   (0x20U)
17457 #define CCM_GPR_SHARED3_SET_m33_mask_can3_SHIFT  (5U)
17458 /*! m33_mask_can3 - m33_mask_can3 */
17459 #define CCM_GPR_SHARED3_SET_m33_mask_can3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_can3_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_can3_MASK)
17460 
17461 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart1_MASK (0x40U)
17462 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart1_SHIFT (6U)
17463 /*! m33_mask_lpuart1 - m33_mask_lpuart1 */
17464 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart1_MASK)
17465 
17466 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart2_MASK (0x80U)
17467 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart2_SHIFT (7U)
17468 /*! m33_mask_lpuart2 - m33_mask_lpuart2 */
17469 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart2_MASK)
17470 
17471 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart3_MASK (0x100U)
17472 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart3_SHIFT (8U)
17473 /*! m33_mask_lpuart3 - m33_mask_lpuart3 */
17474 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart3(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart3_MASK)
17475 
17476 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart4_MASK (0x200U)
17477 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart4_SHIFT (9U)
17478 /*! m33_mask_lpuart4 - m33_mask_lpuart4 */
17479 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart4(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart4_MASK)
17480 
17481 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart5_MASK (0x400U)
17482 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart5_SHIFT (10U)
17483 /*! m33_mask_lpuart5 - m33_mask_lpuart5 */
17484 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart5(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart5_MASK)
17485 
17486 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart6_MASK (0x800U)
17487 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart6_SHIFT (11U)
17488 /*! m33_mask_lpuart6 - m33_mask_lpuart6 */
17489 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart6(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart6_MASK)
17490 
17491 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart7_MASK (0x1000U)
17492 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart7_SHIFT (12U)
17493 /*! m33_mask_lpuart7 - m33_mask_lpuart7 */
17494 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart7(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart7_MASK)
17495 
17496 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart8_MASK (0x2000U)
17497 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart8_SHIFT (13U)
17498 /*! m33_mask_lpuart8 - m33_mask_lpuart8 */
17499 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart8(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart8_MASK)
17500 
17501 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart9_MASK (0x4000U)
17502 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart9_SHIFT (14U)
17503 /*! m33_mask_lpuart9 - m33_mask_lpuart9 */
17504 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart9(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart9_MASK)
17505 
17506 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart10_MASK (0x8000U)
17507 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart10_SHIFT (15U)
17508 /*! m33_mask_lpuart10 - m33_mask_lpuart10 */
17509 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart10(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart10_MASK)
17510 
17511 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart11_MASK (0x10000U)
17512 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart11_SHIFT (16U)
17513 /*! m33_mask_lpuart11 - m33_mask_lpuart11 */
17514 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart11(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart11_MASK)
17515 
17516 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart12_MASK (0x20000U)
17517 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart12_SHIFT (17U)
17518 /*! m33_mask_lpuart12 - m33_mask_lpuart12 */
17519 #define CCM_GPR_SHARED3_SET_m33_mask_lpuart12(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpuart12_MASK)
17520 
17521 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c1_MASK (0x40000U)
17522 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c1_SHIFT (18U)
17523 /*! m33_mask_lpi2c1 - m33_mask_lpi2c1 */
17524 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c1_MASK)
17525 
17526 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c2_MASK (0x80000U)
17527 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c2_SHIFT (19U)
17528 /*! m33_mask_lpi2c2 - m33_mask_lpi2c2 */
17529 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c2_MASK)
17530 
17531 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c3_MASK (0x100000U)
17532 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c3_SHIFT (20U)
17533 /*! m33_mask_lpi2c3 - m33_mask_lpi2c3 */
17534 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c3_MASK)
17535 
17536 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c4_MASK (0x200000U)
17537 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c4_SHIFT (21U)
17538 /*! m33_mask_lpi2c4 - m33_mask_lpi2c4 */
17539 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c4_MASK)
17540 
17541 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c5_MASK (0x400000U)
17542 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c5_SHIFT (22U)
17543 /*! m33_mask_lpi2c5 - m33_mask_lpi2c5 */
17544 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c5_MASK)
17545 
17546 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c6_MASK (0x800000U)
17547 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c6_SHIFT (23U)
17548 /*! m33_mask_lpi2c6 - m33_mask_lpi2c6 */
17549 #define CCM_GPR_SHARED3_SET_m33_mask_lpi2c6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpi2c6_MASK)
17550 
17551 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi1_MASK (0x1000000U)
17552 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi1_SHIFT (24U)
17553 /*! m33_mask_lpspi1 - m33_mask_lpspi1 */
17554 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi1_MASK)
17555 
17556 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi2_MASK (0x2000000U)
17557 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi2_SHIFT (25U)
17558 /*! m33_mask_lpspi2 - m33_mask_lpspi2 */
17559 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi2_MASK)
17560 
17561 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi3_MASK (0x4000000U)
17562 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi3_SHIFT (26U)
17563 /*! m33_mask_lpspi3 - m33_mask_lpspi3 */
17564 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi3_MASK)
17565 
17566 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi4_MASK (0x8000000U)
17567 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi4_SHIFT (27U)
17568 /*! m33_mask_lpspi4 - m33_mask_lpspi4 */
17569 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi4_MASK)
17570 
17571 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi5_MASK (0x10000000U)
17572 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi5_SHIFT (28U)
17573 /*! m33_mask_lpspi5 - m33_mask_lpspi5 */
17574 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi5_MASK)
17575 
17576 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi6_MASK (0x20000000U)
17577 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi6_SHIFT (29U)
17578 /*! m33_mask_lpspi6 - m33_mask_lpspi6 */
17579 #define CCM_GPR_SHARED3_SET_m33_mask_lpspi6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_lpspi6_MASK)
17580 
17581 #define CCM_GPR_SHARED3_SET_m33_mask_sinc1_MASK  (0x40000000U)
17582 #define CCM_GPR_SHARED3_SET_m33_mask_sinc1_SHIFT (30U)
17583 /*! m33_mask_sinc1 - m33_mask_sinc1 */
17584 #define CCM_GPR_SHARED3_SET_m33_mask_sinc1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_sinc1_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_sinc1_MASK)
17585 
17586 #define CCM_GPR_SHARED3_SET_m33_mask_sinc2_MASK  (0x80000000U)
17587 #define CCM_GPR_SHARED3_SET_m33_mask_sinc2_SHIFT (31U)
17588 /*! m33_mask_sinc2 - m33_mask_sinc2 */
17589 #define CCM_GPR_SHARED3_SET_m33_mask_sinc2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_SET_m33_mask_sinc2_SHIFT)) & CCM_GPR_SHARED3_SET_m33_mask_sinc2_MASK)
17590 /*! @} */
17591 
17592 /*! @name GPR_SHARED3_CLR - General Purpose Register */
17593 /*! @{ */
17594 
17595 #define CCM_GPR_SHARED3_CLR_m33_mask_tpm6_MASK   (0x1U)
17596 #define CCM_GPR_SHARED3_CLR_m33_mask_tpm6_SHIFT  (0U)
17597 /*! m33_mask_tpm6 - m33_mask_tpm6 */
17598 #define CCM_GPR_SHARED3_CLR_m33_mask_tpm6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_tpm6_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_tpm6_MASK)
17599 
17600 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt1_MASK   (0x2U)
17601 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt1_SHIFT  (1U)
17602 /*! m33_mask_gpt1 - m33_mask_gpt1 */
17603 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_gpt1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_gpt1_MASK)
17604 
17605 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt2_MASK   (0x4U)
17606 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt2_SHIFT  (2U)
17607 /*! m33_mask_gpt2 - m33_mask_gpt2 */
17608 #define CCM_GPR_SHARED3_CLR_m33_mask_gpt2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_gpt2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_gpt2_MASK)
17609 
17610 #define CCM_GPR_SHARED3_CLR_m33_mask_can1_MASK   (0x8U)
17611 #define CCM_GPR_SHARED3_CLR_m33_mask_can1_SHIFT  (3U)
17612 /*! m33_mask_can1 - m33_mask_can1 */
17613 #define CCM_GPR_SHARED3_CLR_m33_mask_can1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_can1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_can1_MASK)
17614 
17615 #define CCM_GPR_SHARED3_CLR_m33_mask_can2_MASK   (0x10U)
17616 #define CCM_GPR_SHARED3_CLR_m33_mask_can2_SHIFT  (4U)
17617 /*! m33_mask_can2 - m33_mask_can2 */
17618 #define CCM_GPR_SHARED3_CLR_m33_mask_can2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_can2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_can2_MASK)
17619 
17620 #define CCM_GPR_SHARED3_CLR_m33_mask_can3_MASK   (0x20U)
17621 #define CCM_GPR_SHARED3_CLR_m33_mask_can3_SHIFT  (5U)
17622 /*! m33_mask_can3 - m33_mask_can3 */
17623 #define CCM_GPR_SHARED3_CLR_m33_mask_can3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_can3_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_can3_MASK)
17624 
17625 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart1_MASK (0x40U)
17626 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart1_SHIFT (6U)
17627 /*! m33_mask_lpuart1 - m33_mask_lpuart1 */
17628 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart1_MASK)
17629 
17630 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart2_MASK (0x80U)
17631 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart2_SHIFT (7U)
17632 /*! m33_mask_lpuart2 - m33_mask_lpuart2 */
17633 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart2_MASK)
17634 
17635 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart3_MASK (0x100U)
17636 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart3_SHIFT (8U)
17637 /*! m33_mask_lpuart3 - m33_mask_lpuart3 */
17638 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart3(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart3_MASK)
17639 
17640 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart4_MASK (0x200U)
17641 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart4_SHIFT (9U)
17642 /*! m33_mask_lpuart4 - m33_mask_lpuart4 */
17643 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart4(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart4_MASK)
17644 
17645 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart5_MASK (0x400U)
17646 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart5_SHIFT (10U)
17647 /*! m33_mask_lpuart5 - m33_mask_lpuart5 */
17648 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart5(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart5_MASK)
17649 
17650 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart6_MASK (0x800U)
17651 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart6_SHIFT (11U)
17652 /*! m33_mask_lpuart6 - m33_mask_lpuart6 */
17653 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart6(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart6_MASK)
17654 
17655 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart7_MASK (0x1000U)
17656 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart7_SHIFT (12U)
17657 /*! m33_mask_lpuart7 - m33_mask_lpuart7 */
17658 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart7(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart7_MASK)
17659 
17660 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart8_MASK (0x2000U)
17661 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart8_SHIFT (13U)
17662 /*! m33_mask_lpuart8 - m33_mask_lpuart8 */
17663 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart8(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart8_MASK)
17664 
17665 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart9_MASK (0x4000U)
17666 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart9_SHIFT (14U)
17667 /*! m33_mask_lpuart9 - m33_mask_lpuart9 */
17668 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart9(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart9_MASK)
17669 
17670 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart10_MASK (0x8000U)
17671 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart10_SHIFT (15U)
17672 /*! m33_mask_lpuart10 - m33_mask_lpuart10 */
17673 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart10(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart10_MASK)
17674 
17675 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart11_MASK (0x10000U)
17676 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart11_SHIFT (16U)
17677 /*! m33_mask_lpuart11 - m33_mask_lpuart11 */
17678 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart11(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart11_MASK)
17679 
17680 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart12_MASK (0x20000U)
17681 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart12_SHIFT (17U)
17682 /*! m33_mask_lpuart12 - m33_mask_lpuart12 */
17683 #define CCM_GPR_SHARED3_CLR_m33_mask_lpuart12(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpuart12_MASK)
17684 
17685 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c1_MASK (0x40000U)
17686 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c1_SHIFT (18U)
17687 /*! m33_mask_lpi2c1 - m33_mask_lpi2c1 */
17688 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c1_MASK)
17689 
17690 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c2_MASK (0x80000U)
17691 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c2_SHIFT (19U)
17692 /*! m33_mask_lpi2c2 - m33_mask_lpi2c2 */
17693 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c2_MASK)
17694 
17695 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c3_MASK (0x100000U)
17696 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c3_SHIFT (20U)
17697 /*! m33_mask_lpi2c3 - m33_mask_lpi2c3 */
17698 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c3_MASK)
17699 
17700 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c4_MASK (0x200000U)
17701 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c4_SHIFT (21U)
17702 /*! m33_mask_lpi2c4 - m33_mask_lpi2c4 */
17703 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c4_MASK)
17704 
17705 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c5_MASK (0x400000U)
17706 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c5_SHIFT (22U)
17707 /*! m33_mask_lpi2c5 - m33_mask_lpi2c5 */
17708 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c5_MASK)
17709 
17710 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c6_MASK (0x800000U)
17711 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c6_SHIFT (23U)
17712 /*! m33_mask_lpi2c6 - m33_mask_lpi2c6 */
17713 #define CCM_GPR_SHARED3_CLR_m33_mask_lpi2c6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpi2c6_MASK)
17714 
17715 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi1_MASK (0x1000000U)
17716 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi1_SHIFT (24U)
17717 /*! m33_mask_lpspi1 - m33_mask_lpspi1 */
17718 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi1_MASK)
17719 
17720 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi2_MASK (0x2000000U)
17721 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi2_SHIFT (25U)
17722 /*! m33_mask_lpspi2 - m33_mask_lpspi2 */
17723 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi2_MASK)
17724 
17725 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi3_MASK (0x4000000U)
17726 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi3_SHIFT (26U)
17727 /*! m33_mask_lpspi3 - m33_mask_lpspi3 */
17728 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi3_MASK)
17729 
17730 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi4_MASK (0x8000000U)
17731 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi4_SHIFT (27U)
17732 /*! m33_mask_lpspi4 - m33_mask_lpspi4 */
17733 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi4_MASK)
17734 
17735 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi5_MASK (0x10000000U)
17736 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi5_SHIFT (28U)
17737 /*! m33_mask_lpspi5 - m33_mask_lpspi5 */
17738 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi5_MASK)
17739 
17740 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi6_MASK (0x20000000U)
17741 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi6_SHIFT (29U)
17742 /*! m33_mask_lpspi6 - m33_mask_lpspi6 */
17743 #define CCM_GPR_SHARED3_CLR_m33_mask_lpspi6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_lpspi6_MASK)
17744 
17745 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc1_MASK  (0x40000000U)
17746 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc1_SHIFT (30U)
17747 /*! m33_mask_sinc1 - m33_mask_sinc1 */
17748 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_sinc1_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_sinc1_MASK)
17749 
17750 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc2_MASK  (0x80000000U)
17751 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc2_SHIFT (31U)
17752 /*! m33_mask_sinc2 - m33_mask_sinc2 */
17753 #define CCM_GPR_SHARED3_CLR_m33_mask_sinc2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_CLR_m33_mask_sinc2_SHIFT)) & CCM_GPR_SHARED3_CLR_m33_mask_sinc2_MASK)
17754 /*! @} */
17755 
17756 /*! @name GPR_SHARED3_TOG - General Purpose Register */
17757 /*! @{ */
17758 
17759 #define CCM_GPR_SHARED3_TOG_m33_mask_tpm6_MASK   (0x1U)
17760 #define CCM_GPR_SHARED3_TOG_m33_mask_tpm6_SHIFT  (0U)
17761 /*! m33_mask_tpm6 - m33_mask_tpm6 */
17762 #define CCM_GPR_SHARED3_TOG_m33_mask_tpm6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_tpm6_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_tpm6_MASK)
17763 
17764 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt1_MASK   (0x2U)
17765 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt1_SHIFT  (1U)
17766 /*! m33_mask_gpt1 - m33_mask_gpt1 */
17767 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_gpt1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_gpt1_MASK)
17768 
17769 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt2_MASK   (0x4U)
17770 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt2_SHIFT  (2U)
17771 /*! m33_mask_gpt2 - m33_mask_gpt2 */
17772 #define CCM_GPR_SHARED3_TOG_m33_mask_gpt2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_gpt2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_gpt2_MASK)
17773 
17774 #define CCM_GPR_SHARED3_TOG_m33_mask_can1_MASK   (0x8U)
17775 #define CCM_GPR_SHARED3_TOG_m33_mask_can1_SHIFT  (3U)
17776 /*! m33_mask_can1 - m33_mask_can1 */
17777 #define CCM_GPR_SHARED3_TOG_m33_mask_can1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_can1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_can1_MASK)
17778 
17779 #define CCM_GPR_SHARED3_TOG_m33_mask_can2_MASK   (0x10U)
17780 #define CCM_GPR_SHARED3_TOG_m33_mask_can2_SHIFT  (4U)
17781 /*! m33_mask_can2 - m33_mask_can2 */
17782 #define CCM_GPR_SHARED3_TOG_m33_mask_can2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_can2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_can2_MASK)
17783 
17784 #define CCM_GPR_SHARED3_TOG_m33_mask_can3_MASK   (0x20U)
17785 #define CCM_GPR_SHARED3_TOG_m33_mask_can3_SHIFT  (5U)
17786 /*! m33_mask_can3 - m33_mask_can3 */
17787 #define CCM_GPR_SHARED3_TOG_m33_mask_can3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_can3_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_can3_MASK)
17788 
17789 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart1_MASK (0x40U)
17790 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart1_SHIFT (6U)
17791 /*! m33_mask_lpuart1 - m33_mask_lpuart1 */
17792 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart1_MASK)
17793 
17794 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart2_MASK (0x80U)
17795 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart2_SHIFT (7U)
17796 /*! m33_mask_lpuart2 - m33_mask_lpuart2 */
17797 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart2_MASK)
17798 
17799 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart3_MASK (0x100U)
17800 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart3_SHIFT (8U)
17801 /*! m33_mask_lpuart3 - m33_mask_lpuart3 */
17802 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart3(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart3_MASK)
17803 
17804 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart4_MASK (0x200U)
17805 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart4_SHIFT (9U)
17806 /*! m33_mask_lpuart4 - m33_mask_lpuart4 */
17807 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart4(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart4_MASK)
17808 
17809 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart5_MASK (0x400U)
17810 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart5_SHIFT (10U)
17811 /*! m33_mask_lpuart5 - m33_mask_lpuart5 */
17812 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart5(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart5_MASK)
17813 
17814 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart6_MASK (0x800U)
17815 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart6_SHIFT (11U)
17816 /*! m33_mask_lpuart6 - m33_mask_lpuart6 */
17817 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart6(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart6_MASK)
17818 
17819 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart7_MASK (0x1000U)
17820 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart7_SHIFT (12U)
17821 /*! m33_mask_lpuart7 - m33_mask_lpuart7 */
17822 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart7(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart7_MASK)
17823 
17824 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart8_MASK (0x2000U)
17825 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart8_SHIFT (13U)
17826 /*! m33_mask_lpuart8 - m33_mask_lpuart8 */
17827 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart8(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart8_MASK)
17828 
17829 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart9_MASK (0x4000U)
17830 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart9_SHIFT (14U)
17831 /*! m33_mask_lpuart9 - m33_mask_lpuart9 */
17832 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart9(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart9_MASK)
17833 
17834 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart10_MASK (0x8000U)
17835 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart10_SHIFT (15U)
17836 /*! m33_mask_lpuart10 - m33_mask_lpuart10 */
17837 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart10(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart10_MASK)
17838 
17839 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart11_MASK (0x10000U)
17840 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart11_SHIFT (16U)
17841 /*! m33_mask_lpuart11 - m33_mask_lpuart11 */
17842 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart11(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart11_MASK)
17843 
17844 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart12_MASK (0x20000U)
17845 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart12_SHIFT (17U)
17846 /*! m33_mask_lpuart12 - m33_mask_lpuart12 */
17847 #define CCM_GPR_SHARED3_TOG_m33_mask_lpuart12(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpuart12_MASK)
17848 
17849 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c1_MASK (0x40000U)
17850 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c1_SHIFT (18U)
17851 /*! m33_mask_lpi2c1 - m33_mask_lpi2c1 */
17852 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c1_MASK)
17853 
17854 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c2_MASK (0x80000U)
17855 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c2_SHIFT (19U)
17856 /*! m33_mask_lpi2c2 - m33_mask_lpi2c2 */
17857 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c2_MASK)
17858 
17859 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c3_MASK (0x100000U)
17860 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c3_SHIFT (20U)
17861 /*! m33_mask_lpi2c3 - m33_mask_lpi2c3 */
17862 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c3_MASK)
17863 
17864 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c4_MASK (0x200000U)
17865 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c4_SHIFT (21U)
17866 /*! m33_mask_lpi2c4 - m33_mask_lpi2c4 */
17867 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c4_MASK)
17868 
17869 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c5_MASK (0x400000U)
17870 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c5_SHIFT (22U)
17871 /*! m33_mask_lpi2c5 - m33_mask_lpi2c5 */
17872 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c5_MASK)
17873 
17874 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c6_MASK (0x800000U)
17875 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c6_SHIFT (23U)
17876 /*! m33_mask_lpi2c6 - m33_mask_lpi2c6 */
17877 #define CCM_GPR_SHARED3_TOG_m33_mask_lpi2c6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpi2c6_MASK)
17878 
17879 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi1_MASK (0x1000000U)
17880 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi1_SHIFT (24U)
17881 /*! m33_mask_lpspi1 - m33_mask_lpspi1 */
17882 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi1_MASK)
17883 
17884 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi2_MASK (0x2000000U)
17885 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi2_SHIFT (25U)
17886 /*! m33_mask_lpspi2 - m33_mask_lpspi2 */
17887 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi2_MASK)
17888 
17889 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi3_MASK (0x4000000U)
17890 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi3_SHIFT (26U)
17891 /*! m33_mask_lpspi3 - m33_mask_lpspi3 */
17892 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi3_MASK)
17893 
17894 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi4_MASK (0x8000000U)
17895 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi4_SHIFT (27U)
17896 /*! m33_mask_lpspi4 - m33_mask_lpspi4 */
17897 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi4_MASK)
17898 
17899 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi5_MASK (0x10000000U)
17900 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi5_SHIFT (28U)
17901 /*! m33_mask_lpspi5 - m33_mask_lpspi5 */
17902 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi5_MASK)
17903 
17904 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi6_MASK (0x20000000U)
17905 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi6_SHIFT (29U)
17906 /*! m33_mask_lpspi6 - m33_mask_lpspi6 */
17907 #define CCM_GPR_SHARED3_TOG_m33_mask_lpspi6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_lpspi6_MASK)
17908 
17909 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc1_MASK  (0x40000000U)
17910 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc1_SHIFT (30U)
17911 /*! m33_mask_sinc1 - m33_mask_sinc1 */
17912 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_sinc1_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_sinc1_MASK)
17913 
17914 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc2_MASK  (0x80000000U)
17915 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc2_SHIFT (31U)
17916 /*! m33_mask_sinc2 - m33_mask_sinc2 */
17917 #define CCM_GPR_SHARED3_TOG_m33_mask_sinc2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_TOG_m33_mask_sinc2_SHIFT)) & CCM_GPR_SHARED3_TOG_m33_mask_sinc2_MASK)
17918 /*! @} */
17919 
17920 /*! @name GPR_SHARED3_AUTHEN - GPR access control */
17921 /*! @{ */
17922 
17923 #define CCM_GPR_SHARED3_AUTHEN_TZ_USER_MASK      (0x100U)
17924 #define CCM_GPR_SHARED3_AUTHEN_TZ_USER_SHIFT     (8U)
17925 /*! TZ_USER - User access permission
17926  *  0b1..Registers of shared GPR slice can be changed in user mode.
17927  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
17928  */
17929 #define CCM_GPR_SHARED3_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TZ_USER_MASK)
17930 
17931 #define CCM_GPR_SHARED3_AUTHEN_TZ_NS_MASK        (0x200U)
17932 #define CCM_GPR_SHARED3_AUTHEN_TZ_NS_SHIFT       (9U)
17933 /*! TZ_NS - Non-secure access permission
17934  *  0b0..Cannot be changed in Non-secure mode.
17935  *  0b1..Can be changed in Non-secure mode.
17936  */
17937 #define CCM_GPR_SHARED3_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TZ_NS_MASK)
17938 
17939 #define CCM_GPR_SHARED3_AUTHEN_LOCK_TZ_MASK      (0x800U)
17940 #define CCM_GPR_SHARED3_AUTHEN_LOCK_TZ_SHIFT     (11U)
17941 /*! LOCK_TZ - Lock TrustZone settings
17942  *  0b0..TrustZone settings is not locked.
17943  *  0b1..TrustZone settings is locked.
17944  */
17945 #define CCM_GPR_SHARED3_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_LOCK_TZ_MASK)
17946 
17947 #define CCM_GPR_SHARED3_AUTHEN_LOCK_LIST_MASK    (0x8000U)
17948 #define CCM_GPR_SHARED3_AUTHEN_LOCK_LIST_SHIFT   (15U)
17949 /*! LOCK_LIST - Lock white list
17950  *  0b0..Whitelist is not locked.
17951  *  0b1..Whitelist is locked.
17952  */
17953 #define CCM_GPR_SHARED3_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_LOCK_LIST_MASK)
17954 
17955 #define CCM_GPR_SHARED3_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
17956 #define CCM_GPR_SHARED3_AUTHEN_WHITE_LIST_SHIFT  (16U)
17957 /*! WHITE_LIST - Whitelist settings */
17958 #define CCM_GPR_SHARED3_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_WHITE_LIST_MASK)
17959 /*! @} */
17960 
17961 /*! @name GPR_SHARED3_AUTHEN_SET - GPR access control */
17962 /*! @{ */
17963 
17964 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_USER_MASK  (0x100U)
17965 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_USER_SHIFT (8U)
17966 /*! TZ_USER - User access permission */
17967 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_SET_TZ_USER_MASK)
17968 
17969 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_NS_MASK    (0x200U)
17970 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_NS_SHIFT   (9U)
17971 /*! TZ_NS - Non-secure access permission */
17972 #define CCM_GPR_SHARED3_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_SET_TZ_NS_MASK)
17973 
17974 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
17975 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
17976 /*! LOCK_TZ - Lock TrustZone settings */
17977 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_SET_LOCK_TZ_MASK)
17978 
17979 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
17980 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
17981 /*! LOCK_LIST - Lock white list */
17982 #define CCM_GPR_SHARED3_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_SET_LOCK_LIST_MASK)
17983 
17984 #define CCM_GPR_SHARED3_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
17985 #define CCM_GPR_SHARED3_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
17986 /*! WHITE_LIST - Whitelist settings */
17987 #define CCM_GPR_SHARED3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_SET_WHITE_LIST_MASK)
17988 /*! @} */
17989 
17990 /*! @name GPR_SHARED3_AUTHEN_CLR - GPR access control */
17991 /*! @{ */
17992 
17993 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
17994 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_USER_SHIFT (8U)
17995 /*! TZ_USER - User access permission */
17996 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_CLR_TZ_USER_MASK)
17997 
17998 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
17999 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
18000 /*! TZ_NS - Non-secure access permission */
18001 #define CCM_GPR_SHARED3_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_CLR_TZ_NS_MASK)
18002 
18003 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
18004 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
18005 /*! LOCK_TZ - Lock TrustZone settings */
18006 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_TZ_MASK)
18007 
18008 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
18009 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
18010 /*! LOCK_LIST - Lock white list */
18011 #define CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_CLR_LOCK_LIST_MASK)
18012 
18013 #define CCM_GPR_SHARED3_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
18014 #define CCM_GPR_SHARED3_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
18015 /*! WHITE_LIST - Whitelist settings */
18016 #define CCM_GPR_SHARED3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_CLR_WHITE_LIST_MASK)
18017 /*! @} */
18018 
18019 /*! @name GPR_SHARED3_AUTHEN_TOG - GPR access control */
18020 /*! @{ */
18021 
18022 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
18023 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_USER_SHIFT (8U)
18024 /*! TZ_USER - User access permission */
18025 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TOG_TZ_USER_MASK)
18026 
18027 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
18028 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
18029 /*! TZ_NS - Non-secure access permission */
18030 #define CCM_GPR_SHARED3_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TOG_TZ_NS_MASK)
18031 
18032 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
18033 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
18034 /*! LOCK_TZ - Lock TrustZone settings */
18035 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_TZ_MASK)
18036 
18037 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
18038 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
18039 /*! LOCK_LIST - Lock white list */
18040 #define CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TOG_LOCK_LIST_MASK)
18041 
18042 #define CCM_GPR_SHARED3_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
18043 #define CCM_GPR_SHARED3_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
18044 /*! WHITE_LIST - Whitelist settings */
18045 #define CCM_GPR_SHARED3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED3_AUTHEN_TOG_WHITE_LIST_MASK)
18046 /*! @} */
18047 
18048 /*! @name GPR_SHARED4 - General Purpose Register */
18049 /*! @{ */
18050 
18051 #define CCM_GPR_SHARED4_m33_mask_sinc3_MASK      (0x1U)
18052 #define CCM_GPR_SHARED4_m33_mask_sinc3_SHIFT     (0U)
18053 /*! m33_mask_sinc3 - m33_mask_sinc3 */
18054 #define CCM_GPR_SHARED4_m33_mask_sinc3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_sinc3_SHIFT)) & CCM_GPR_SHARED4_m33_mask_sinc3_MASK)
18055 
18056 #define CCM_GPR_SHARED4_m33_mask_sai1_MASK       (0x2U)
18057 #define CCM_GPR_SHARED4_m33_mask_sai1_SHIFT      (1U)
18058 /*! m33_mask_sai1 - m33_mask_sai1 */
18059 #define CCM_GPR_SHARED4_m33_mask_sai1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_sai1_SHIFT)) & CCM_GPR_SHARED4_m33_mask_sai1_MASK)
18060 
18061 #define CCM_GPR_SHARED4_m33_mask_sai2_MASK       (0x4U)
18062 #define CCM_GPR_SHARED4_m33_mask_sai2_SHIFT      (2U)
18063 /*! m33_mask_sai2 - m33_mask_sai2 */
18064 #define CCM_GPR_SHARED4_m33_mask_sai2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_sai2_SHIFT)) & CCM_GPR_SHARED4_m33_mask_sai2_MASK)
18065 
18066 #define CCM_GPR_SHARED4_m33_mask_sai3_MASK       (0x8U)
18067 #define CCM_GPR_SHARED4_m33_mask_sai3_SHIFT      (3U)
18068 /*! m33_mask_sai3 - m33_mask_sai3 */
18069 #define CCM_GPR_SHARED4_m33_mask_sai3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_sai3_SHIFT)) & CCM_GPR_SHARED4_m33_mask_sai3_MASK)
18070 
18071 #define CCM_GPR_SHARED4_m33_mask_sai4_MASK       (0x10U)
18072 #define CCM_GPR_SHARED4_m33_mask_sai4_SHIFT      (4U)
18073 /*! m33_mask_sai4 - m33_mask_sai4 */
18074 #define CCM_GPR_SHARED4_m33_mask_sai4(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_sai4_SHIFT)) & CCM_GPR_SHARED4_m33_mask_sai4_MASK)
18075 
18076 #define CCM_GPR_SHARED4_m33_mask_mic_MASK        (0x20U)
18077 #define CCM_GPR_SHARED4_m33_mask_mic_SHIFT       (5U)
18078 /*! m33_mask_mic - m33_mask_mic */
18079 #define CCM_GPR_SHARED4_m33_mask_mic(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_m33_mask_mic_SHIFT)) & CCM_GPR_SHARED4_m33_mask_mic_MASK)
18080 /*! @} */
18081 
18082 /*! @name GPR_SHARED4_SET - General Purpose Register */
18083 /*! @{ */
18084 
18085 #define CCM_GPR_SHARED4_SET_m33_mask_sinc3_MASK  (0x1U)
18086 #define CCM_GPR_SHARED4_SET_m33_mask_sinc3_SHIFT (0U)
18087 /*! m33_mask_sinc3 - m33_mask_sinc3 */
18088 #define CCM_GPR_SHARED4_SET_m33_mask_sinc3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_sinc3_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_sinc3_MASK)
18089 
18090 #define CCM_GPR_SHARED4_SET_m33_mask_sai1_MASK   (0x2U)
18091 #define CCM_GPR_SHARED4_SET_m33_mask_sai1_SHIFT  (1U)
18092 /*! m33_mask_sai1 - m33_mask_sai1 */
18093 #define CCM_GPR_SHARED4_SET_m33_mask_sai1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_sai1_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_sai1_MASK)
18094 
18095 #define CCM_GPR_SHARED4_SET_m33_mask_sai2_MASK   (0x4U)
18096 #define CCM_GPR_SHARED4_SET_m33_mask_sai2_SHIFT  (2U)
18097 /*! m33_mask_sai2 - m33_mask_sai2 */
18098 #define CCM_GPR_SHARED4_SET_m33_mask_sai2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_sai2_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_sai2_MASK)
18099 
18100 #define CCM_GPR_SHARED4_SET_m33_mask_sai3_MASK   (0x8U)
18101 #define CCM_GPR_SHARED4_SET_m33_mask_sai3_SHIFT  (3U)
18102 /*! m33_mask_sai3 - m33_mask_sai3 */
18103 #define CCM_GPR_SHARED4_SET_m33_mask_sai3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_sai3_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_sai3_MASK)
18104 
18105 #define CCM_GPR_SHARED4_SET_m33_mask_sai4_MASK   (0x10U)
18106 #define CCM_GPR_SHARED4_SET_m33_mask_sai4_SHIFT  (4U)
18107 /*! m33_mask_sai4 - m33_mask_sai4 */
18108 #define CCM_GPR_SHARED4_SET_m33_mask_sai4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_sai4_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_sai4_MASK)
18109 
18110 #define CCM_GPR_SHARED4_SET_m33_mask_mic_MASK    (0x20U)
18111 #define CCM_GPR_SHARED4_SET_m33_mask_mic_SHIFT   (5U)
18112 /*! m33_mask_mic - m33_mask_mic */
18113 #define CCM_GPR_SHARED4_SET_m33_mask_mic(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_SET_m33_mask_mic_SHIFT)) & CCM_GPR_SHARED4_SET_m33_mask_mic_MASK)
18114 /*! @} */
18115 
18116 /*! @name GPR_SHARED4_CLR - General Purpose Register */
18117 /*! @{ */
18118 
18119 #define CCM_GPR_SHARED4_CLR_m33_mask_sinc3_MASK  (0x1U)
18120 #define CCM_GPR_SHARED4_CLR_m33_mask_sinc3_SHIFT (0U)
18121 /*! m33_mask_sinc3 - m33_mask_sinc3 */
18122 #define CCM_GPR_SHARED4_CLR_m33_mask_sinc3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_sinc3_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_sinc3_MASK)
18123 
18124 #define CCM_GPR_SHARED4_CLR_m33_mask_sai1_MASK   (0x2U)
18125 #define CCM_GPR_SHARED4_CLR_m33_mask_sai1_SHIFT  (1U)
18126 /*! m33_mask_sai1 - m33_mask_sai1 */
18127 #define CCM_GPR_SHARED4_CLR_m33_mask_sai1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_sai1_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_sai1_MASK)
18128 
18129 #define CCM_GPR_SHARED4_CLR_m33_mask_sai2_MASK   (0x4U)
18130 #define CCM_GPR_SHARED4_CLR_m33_mask_sai2_SHIFT  (2U)
18131 /*! m33_mask_sai2 - m33_mask_sai2 */
18132 #define CCM_GPR_SHARED4_CLR_m33_mask_sai2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_sai2_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_sai2_MASK)
18133 
18134 #define CCM_GPR_SHARED4_CLR_m33_mask_sai3_MASK   (0x8U)
18135 #define CCM_GPR_SHARED4_CLR_m33_mask_sai3_SHIFT  (3U)
18136 /*! m33_mask_sai3 - m33_mask_sai3 */
18137 #define CCM_GPR_SHARED4_CLR_m33_mask_sai3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_sai3_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_sai3_MASK)
18138 
18139 #define CCM_GPR_SHARED4_CLR_m33_mask_sai4_MASK   (0x10U)
18140 #define CCM_GPR_SHARED4_CLR_m33_mask_sai4_SHIFT  (4U)
18141 /*! m33_mask_sai4 - m33_mask_sai4 */
18142 #define CCM_GPR_SHARED4_CLR_m33_mask_sai4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_sai4_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_sai4_MASK)
18143 
18144 #define CCM_GPR_SHARED4_CLR_m33_mask_mic_MASK    (0x20U)
18145 #define CCM_GPR_SHARED4_CLR_m33_mask_mic_SHIFT   (5U)
18146 /*! m33_mask_mic - m33_mask_mic */
18147 #define CCM_GPR_SHARED4_CLR_m33_mask_mic(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_CLR_m33_mask_mic_SHIFT)) & CCM_GPR_SHARED4_CLR_m33_mask_mic_MASK)
18148 /*! @} */
18149 
18150 /*! @name GPR_SHARED4_TOG - General Purpose Register */
18151 /*! @{ */
18152 
18153 #define CCM_GPR_SHARED4_TOG_m33_mask_sinc3_MASK  (0x1U)
18154 #define CCM_GPR_SHARED4_TOG_m33_mask_sinc3_SHIFT (0U)
18155 /*! m33_mask_sinc3 - m33_mask_sinc3 */
18156 #define CCM_GPR_SHARED4_TOG_m33_mask_sinc3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_sinc3_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_sinc3_MASK)
18157 
18158 #define CCM_GPR_SHARED4_TOG_m33_mask_sai1_MASK   (0x2U)
18159 #define CCM_GPR_SHARED4_TOG_m33_mask_sai1_SHIFT  (1U)
18160 /*! m33_mask_sai1 - m33_mask_sai1 */
18161 #define CCM_GPR_SHARED4_TOG_m33_mask_sai1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_sai1_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_sai1_MASK)
18162 
18163 #define CCM_GPR_SHARED4_TOG_m33_mask_sai2_MASK   (0x4U)
18164 #define CCM_GPR_SHARED4_TOG_m33_mask_sai2_SHIFT  (2U)
18165 /*! m33_mask_sai2 - m33_mask_sai2 */
18166 #define CCM_GPR_SHARED4_TOG_m33_mask_sai2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_sai2_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_sai2_MASK)
18167 
18168 #define CCM_GPR_SHARED4_TOG_m33_mask_sai3_MASK   (0x8U)
18169 #define CCM_GPR_SHARED4_TOG_m33_mask_sai3_SHIFT  (3U)
18170 /*! m33_mask_sai3 - m33_mask_sai3 */
18171 #define CCM_GPR_SHARED4_TOG_m33_mask_sai3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_sai3_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_sai3_MASK)
18172 
18173 #define CCM_GPR_SHARED4_TOG_m33_mask_sai4_MASK   (0x10U)
18174 #define CCM_GPR_SHARED4_TOG_m33_mask_sai4_SHIFT  (4U)
18175 /*! m33_mask_sai4 - m33_mask_sai4 */
18176 #define CCM_GPR_SHARED4_TOG_m33_mask_sai4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_sai4_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_sai4_MASK)
18177 
18178 #define CCM_GPR_SHARED4_TOG_m33_mask_mic_MASK    (0x20U)
18179 #define CCM_GPR_SHARED4_TOG_m33_mask_mic_SHIFT   (5U)
18180 /*! m33_mask_mic - m33_mask_mic */
18181 #define CCM_GPR_SHARED4_TOG_m33_mask_mic(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_TOG_m33_mask_mic_SHIFT)) & CCM_GPR_SHARED4_TOG_m33_mask_mic_MASK)
18182 /*! @} */
18183 
18184 /*! @name GPR_SHARED4_AUTHEN - GPR access control */
18185 /*! @{ */
18186 
18187 #define CCM_GPR_SHARED4_AUTHEN_TZ_USER_MASK      (0x100U)
18188 #define CCM_GPR_SHARED4_AUTHEN_TZ_USER_SHIFT     (8U)
18189 /*! TZ_USER - User access permission
18190  *  0b1..Registers of shared GPR slice can be changed in user mode.
18191  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
18192  */
18193 #define CCM_GPR_SHARED4_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TZ_USER_MASK)
18194 
18195 #define CCM_GPR_SHARED4_AUTHEN_TZ_NS_MASK        (0x200U)
18196 #define CCM_GPR_SHARED4_AUTHEN_TZ_NS_SHIFT       (9U)
18197 /*! TZ_NS - Non-secure access permission
18198  *  0b0..Cannot be changed in Non-secure mode.
18199  *  0b1..Can be changed in Non-secure mode.
18200  */
18201 #define CCM_GPR_SHARED4_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TZ_NS_MASK)
18202 
18203 #define CCM_GPR_SHARED4_AUTHEN_LOCK_TZ_MASK      (0x800U)
18204 #define CCM_GPR_SHARED4_AUTHEN_LOCK_TZ_SHIFT     (11U)
18205 /*! LOCK_TZ - Lock TrustZone settings
18206  *  0b0..TrustZone settings is not locked.
18207  *  0b1..TrustZone settings is locked.
18208  */
18209 #define CCM_GPR_SHARED4_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_LOCK_TZ_MASK)
18210 
18211 #define CCM_GPR_SHARED4_AUTHEN_LOCK_LIST_MASK    (0x8000U)
18212 #define CCM_GPR_SHARED4_AUTHEN_LOCK_LIST_SHIFT   (15U)
18213 /*! LOCK_LIST - Lock white list
18214  *  0b0..Whitelist is not locked.
18215  *  0b1..Whitelist is locked.
18216  */
18217 #define CCM_GPR_SHARED4_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_LOCK_LIST_MASK)
18218 
18219 #define CCM_GPR_SHARED4_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
18220 #define CCM_GPR_SHARED4_AUTHEN_WHITE_LIST_SHIFT  (16U)
18221 /*! WHITE_LIST - Whitelist settings */
18222 #define CCM_GPR_SHARED4_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_WHITE_LIST_MASK)
18223 /*! @} */
18224 
18225 /*! @name GPR_SHARED4_AUTHEN_SET - GPR access control */
18226 /*! @{ */
18227 
18228 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_USER_MASK  (0x100U)
18229 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_USER_SHIFT (8U)
18230 /*! TZ_USER - User access permission */
18231 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_SET_TZ_USER_MASK)
18232 
18233 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_NS_MASK    (0x200U)
18234 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_NS_SHIFT   (9U)
18235 /*! TZ_NS - Non-secure access permission */
18236 #define CCM_GPR_SHARED4_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_SET_TZ_NS_MASK)
18237 
18238 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
18239 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
18240 /*! LOCK_TZ - Lock TrustZone settings */
18241 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_SET_LOCK_TZ_MASK)
18242 
18243 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
18244 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
18245 /*! LOCK_LIST - Lock white list */
18246 #define CCM_GPR_SHARED4_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_SET_LOCK_LIST_MASK)
18247 
18248 #define CCM_GPR_SHARED4_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
18249 #define CCM_GPR_SHARED4_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
18250 /*! WHITE_LIST - Whitelist settings */
18251 #define CCM_GPR_SHARED4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_SET_WHITE_LIST_MASK)
18252 /*! @} */
18253 
18254 /*! @name GPR_SHARED4_AUTHEN_CLR - GPR access control */
18255 /*! @{ */
18256 
18257 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
18258 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_USER_SHIFT (8U)
18259 /*! TZ_USER - User access permission */
18260 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_CLR_TZ_USER_MASK)
18261 
18262 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
18263 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
18264 /*! TZ_NS - Non-secure access permission */
18265 #define CCM_GPR_SHARED4_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_CLR_TZ_NS_MASK)
18266 
18267 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
18268 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
18269 /*! LOCK_TZ - Lock TrustZone settings */
18270 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_TZ_MASK)
18271 
18272 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
18273 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
18274 /*! LOCK_LIST - Lock white list */
18275 #define CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_CLR_LOCK_LIST_MASK)
18276 
18277 #define CCM_GPR_SHARED4_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
18278 #define CCM_GPR_SHARED4_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
18279 /*! WHITE_LIST - Whitelist settings */
18280 #define CCM_GPR_SHARED4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_CLR_WHITE_LIST_MASK)
18281 /*! @} */
18282 
18283 /*! @name GPR_SHARED4_AUTHEN_TOG - GPR access control */
18284 /*! @{ */
18285 
18286 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
18287 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_USER_SHIFT (8U)
18288 /*! TZ_USER - User access permission */
18289 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TOG_TZ_USER_MASK)
18290 
18291 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
18292 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
18293 /*! TZ_NS - Non-secure access permission */
18294 #define CCM_GPR_SHARED4_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TOG_TZ_NS_MASK)
18295 
18296 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
18297 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
18298 /*! LOCK_TZ - Lock TrustZone settings */
18299 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_TZ_MASK)
18300 
18301 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
18302 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
18303 /*! LOCK_LIST - Lock white list */
18304 #define CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TOG_LOCK_LIST_MASK)
18305 
18306 #define CCM_GPR_SHARED4_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
18307 #define CCM_GPR_SHARED4_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
18308 /*! WHITE_LIST - Whitelist settings */
18309 #define CCM_GPR_SHARED4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED4_AUTHEN_TOG_WHITE_LIST_MASK)
18310 /*! @} */
18311 
18312 /*! @name GPR_SHARED5 - General Purpose Register */
18313 /*! @{ */
18314 
18315 #define CCM_GPR_SHARED5_m7_mask_cm7_MASK         (0x1U)
18316 #define CCM_GPR_SHARED5_m7_mask_cm7_SHIFT        (0U)
18317 /*! m7_mask_cm7 - m7_mask_cm7 */
18318 #define CCM_GPR_SHARED5_m7_mask_cm7(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_cm7_SHIFT)) & CCM_GPR_SHARED5_m7_mask_cm7_MASK)
18319 
18320 #define CCM_GPR_SHARED5_m7_mask_cm33_MASK        (0x2U)
18321 #define CCM_GPR_SHARED5_m7_mask_cm33_SHIFT       (1U)
18322 /*! m7_mask_cm33 - m7_mask_cm33 */
18323 #define CCM_GPR_SHARED5_m7_mask_cm33(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_cm33_SHIFT)) & CCM_GPR_SHARED5_m7_mask_cm33_MASK)
18324 
18325 #define CCM_GPR_SHARED5_m7_mask_edma3_MASK       (0x4U)
18326 #define CCM_GPR_SHARED5_m7_mask_edma3_SHIFT      (2U)
18327 /*! m7_mask_edma3 - m7_mask_edma3 */
18328 #define CCM_GPR_SHARED5_m7_mask_edma3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_edma3_SHIFT)) & CCM_GPR_SHARED5_m7_mask_edma3_MASK)
18329 
18330 #define CCM_GPR_SHARED5_m7_mask_edma4_MASK       (0x8U)
18331 #define CCM_GPR_SHARED5_m7_mask_edma4_SHIFT      (3U)
18332 /*! m7_mask_edma4 - m7_mask_edma4 */
18333 #define CCM_GPR_SHARED5_m7_mask_edma4(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_edma4_SHIFT)) & CCM_GPR_SHARED5_m7_mask_edma4_MASK)
18334 
18335 #define CCM_GPR_SHARED5_m7_mask_netc_MASK        (0x10U)
18336 #define CCM_GPR_SHARED5_m7_mask_netc_SHIFT       (4U)
18337 /*! m7_mask_netc - m7_mask_netc */
18338 #define CCM_GPR_SHARED5_m7_mask_netc(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_netc_SHIFT)) & CCM_GPR_SHARED5_m7_mask_netc_MASK)
18339 
18340 #define CCM_GPR_SHARED5_m7_mask_sim_aon_MASK     (0x100U)
18341 #define CCM_GPR_SHARED5_m7_mask_sim_aon_SHIFT    (8U)
18342 /*! m7_mask_sim_aon - m7_mask_sim_aon */
18343 #define CCM_GPR_SHARED5_m7_mask_sim_aon(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED5_m7_mask_sim_aon_MASK)
18344 
18345 #define CCM_GPR_SHARED5_m7_mask_adc1_MASK        (0x200U)
18346 #define CCM_GPR_SHARED5_m7_mask_adc1_SHIFT       (9U)
18347 /*! m7_mask_adc1 - m7_mask_adc1 */
18348 #define CCM_GPR_SHARED5_m7_mask_adc1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_adc1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_adc1_MASK)
18349 
18350 #define CCM_GPR_SHARED5_m7_mask_adc2_MASK        (0x400U)
18351 #define CCM_GPR_SHARED5_m7_mask_adc2_SHIFT       (10U)
18352 /*! m7_mask_adc2 - m7_mask_adc2 */
18353 #define CCM_GPR_SHARED5_m7_mask_adc2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_adc2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_adc2_MASK)
18354 
18355 #define CCM_GPR_SHARED5_m7_mask_flexspi1_MASK    (0x800U)
18356 #define CCM_GPR_SHARED5_m7_mask_flexspi1_SHIFT   (11U)
18357 /*! m7_mask_flexspi1 - m7_mask_flexspi1 */
18358 #define CCM_GPR_SHARED5_m7_mask_flexspi1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_flexspi1_MASK)
18359 
18360 #define CCM_GPR_SHARED5_m7_mask_flexspi2_MASK    (0x1000U)
18361 #define CCM_GPR_SHARED5_m7_mask_flexspi2_SHIFT   (12U)
18362 /*! m7_mask_flexspi2 - m7_mask_flexspi2 */
18363 #define CCM_GPR_SHARED5_m7_mask_flexspi2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_flexspi2_MASK)
18364 
18365 #define CCM_GPR_SHARED5_m7_mask_trdc_MASK        (0x2000U)
18366 #define CCM_GPR_SHARED5_m7_mask_trdc_SHIFT       (13U)
18367 /*! m7_mask_trdc - m7_mask_trdc */
18368 #define CCM_GPR_SHARED5_m7_mask_trdc(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_trdc_SHIFT)) & CCM_GPR_SHARED5_m7_mask_trdc_MASK)
18369 
18370 #define CCM_GPR_SHARED5_m7_mask_semc_MASK        (0x4000U)
18371 #define CCM_GPR_SHARED5_m7_mask_semc_SHIFT       (14U)
18372 /*! m7_mask_semc - m7_mask_semc */
18373 #define CCM_GPR_SHARED5_m7_mask_semc(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_semc_SHIFT)) & CCM_GPR_SHARED5_m7_mask_semc_MASK)
18374 
18375 #define CCM_GPR_SHARED5_m7_mask_iee_MASK         (0x8000U)
18376 #define CCM_GPR_SHARED5_m7_mask_iee_SHIFT        (15U)
18377 /*! m7_mask_iee - m7_mask_iee */
18378 #define CCM_GPR_SHARED5_m7_mask_iee(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_iee_SHIFT)) & CCM_GPR_SHARED5_m7_mask_iee_MASK)
18379 
18380 #define CCM_GPR_SHARED5_m7_mask_gpio1_MASK       (0x10000U)
18381 #define CCM_GPR_SHARED5_m7_mask_gpio1_SHIFT      (16U)
18382 /*! m7_mask_gpio1 - m7_mask_gpio1 */
18383 #define CCM_GPR_SHARED5_m7_mask_gpio1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio1_MASK)
18384 
18385 #define CCM_GPR_SHARED5_m7_mask_gpio2_MASK       (0x20000U)
18386 #define CCM_GPR_SHARED5_m7_mask_gpio2_SHIFT      (17U)
18387 /*! m7_mask_gpio2 - m7_mask_gpio2 */
18388 #define CCM_GPR_SHARED5_m7_mask_gpio2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio2_MASK)
18389 
18390 #define CCM_GPR_SHARED5_m7_mask_gpio3_MASK       (0x40000U)
18391 #define CCM_GPR_SHARED5_m7_mask_gpio3_SHIFT      (18U)
18392 /*! m7_mask_gpio3 - m7_mask_gpio3 */
18393 #define CCM_GPR_SHARED5_m7_mask_gpio3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio3_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio3_MASK)
18394 
18395 #define CCM_GPR_SHARED5_m7_mask_gpio4_MASK       (0x80000U)
18396 #define CCM_GPR_SHARED5_m7_mask_gpio4_SHIFT      (19U)
18397 /*! m7_mask_gpio4 - m7_mask_gpio4 */
18398 #define CCM_GPR_SHARED5_m7_mask_gpio4(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio4_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio4_MASK)
18399 
18400 #define CCM_GPR_SHARED5_m7_mask_gpio5_MASK       (0x100000U)
18401 #define CCM_GPR_SHARED5_m7_mask_gpio5_SHIFT      (20U)
18402 /*! m7_mask_gpio5 - m7_mask_gpio5 */
18403 #define CCM_GPR_SHARED5_m7_mask_gpio5(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio5_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio5_MASK)
18404 
18405 #define CCM_GPR_SHARED5_m7_mask_gpio6_MASK       (0x200000U)
18406 #define CCM_GPR_SHARED5_m7_mask_gpio6_SHIFT      (21U)
18407 /*! m7_mask_gpio6 - m7_mask_gpio6 */
18408 #define CCM_GPR_SHARED5_m7_mask_gpio6(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_gpio6_SHIFT)) & CCM_GPR_SHARED5_m7_mask_gpio6_MASK)
18409 
18410 #define CCM_GPR_SHARED5_m7_mask_flexio1_MASK     (0x400000U)
18411 #define CCM_GPR_SHARED5_m7_mask_flexio1_SHIFT    (22U)
18412 /*! m7_mask_flexio1 - m7_mask_flexio1 */
18413 #define CCM_GPR_SHARED5_m7_mask_flexio1(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_flexio1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_flexio1_MASK)
18414 
18415 #define CCM_GPR_SHARED5_m7_mask_flexio2_MASK     (0x800000U)
18416 #define CCM_GPR_SHARED5_m7_mask_flexio2_SHIFT    (23U)
18417 /*! m7_mask_flexio2 - m7_mask_flexio2 */
18418 #define CCM_GPR_SHARED5_m7_mask_flexio2(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_flexio2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_flexio2_MASK)
18419 
18420 #define CCM_GPR_SHARED5_m7_mask_lpit1_MASK       (0x1000000U)
18421 #define CCM_GPR_SHARED5_m7_mask_lpit1_SHIFT      (24U)
18422 /*! m7_mask_lpit1 - m7_mask_lpit1 */
18423 #define CCM_GPR_SHARED5_m7_mask_lpit1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_lpit1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_lpit1_MASK)
18424 
18425 #define CCM_GPR_SHARED5_m7_mask_lpit2_MASK       (0x2000000U)
18426 #define CCM_GPR_SHARED5_m7_mask_lpit2_SHIFT      (25U)
18427 /*! m7_mask_lpit2 - m7_mask_lpit2 */
18428 #define CCM_GPR_SHARED5_m7_mask_lpit2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_lpit2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_lpit2_MASK)
18429 
18430 #define CCM_GPR_SHARED5_m7_mask_lpit3_MASK       (0x4000000U)
18431 #define CCM_GPR_SHARED5_m7_mask_lpit3_SHIFT      (26U)
18432 /*! m7_mask_lpit3 - m7_mask_lpit3 */
18433 #define CCM_GPR_SHARED5_m7_mask_lpit3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_lpit3_SHIFT)) & CCM_GPR_SHARED5_m7_mask_lpit3_MASK)
18434 
18435 #define CCM_GPR_SHARED5_m7_mask_tpm1_MASK        (0x8000000U)
18436 #define CCM_GPR_SHARED5_m7_mask_tpm1_SHIFT       (27U)
18437 /*! m7_mask_tpm1 - m7_mask_tpm1 */
18438 #define CCM_GPR_SHARED5_m7_mask_tpm1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_tpm1_SHIFT)) & CCM_GPR_SHARED5_m7_mask_tpm1_MASK)
18439 
18440 #define CCM_GPR_SHARED5_m7_mask_tpm2_MASK        (0x10000000U)
18441 #define CCM_GPR_SHARED5_m7_mask_tpm2_SHIFT       (28U)
18442 /*! m7_mask_tpm2 - m7_mask_tpm2 */
18443 #define CCM_GPR_SHARED5_m7_mask_tpm2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_tpm2_SHIFT)) & CCM_GPR_SHARED5_m7_mask_tpm2_MASK)
18444 
18445 #define CCM_GPR_SHARED5_m7_mask_tpm3_MASK        (0x20000000U)
18446 #define CCM_GPR_SHARED5_m7_mask_tpm3_SHIFT       (29U)
18447 /*! m7_mask_tpm3 - m7_mask_tpm3 */
18448 #define CCM_GPR_SHARED5_m7_mask_tpm3(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_tpm3_SHIFT)) & CCM_GPR_SHARED5_m7_mask_tpm3_MASK)
18449 
18450 #define CCM_GPR_SHARED5_m7_mask_tpm4_MASK        (0x40000000U)
18451 #define CCM_GPR_SHARED5_m7_mask_tpm4_SHIFT       (30U)
18452 /*! m7_mask_tpm4 - m7_mask_tpm4 */
18453 #define CCM_GPR_SHARED5_m7_mask_tpm4(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_tpm4_SHIFT)) & CCM_GPR_SHARED5_m7_mask_tpm4_MASK)
18454 
18455 #define CCM_GPR_SHARED5_m7_mask_tpm5_MASK        (0x80000000U)
18456 #define CCM_GPR_SHARED5_m7_mask_tpm5_SHIFT       (31U)
18457 /*! m7_mask_tpm5 - m7_mask_tpm5 */
18458 #define CCM_GPR_SHARED5_m7_mask_tpm5(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_m7_mask_tpm5_SHIFT)) & CCM_GPR_SHARED5_m7_mask_tpm5_MASK)
18459 /*! @} */
18460 
18461 /*! @name GPR_SHARED5_SET - General Purpose Register */
18462 /*! @{ */
18463 
18464 #define CCM_GPR_SHARED5_SET_m7_mask_cm7_MASK     (0x1U)
18465 #define CCM_GPR_SHARED5_SET_m7_mask_cm7_SHIFT    (0U)
18466 /*! m7_mask_cm7 - m7_mask_cm7 */
18467 #define CCM_GPR_SHARED5_SET_m7_mask_cm7(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_cm7_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_cm7_MASK)
18468 
18469 #define CCM_GPR_SHARED5_SET_m7_mask_cm33_MASK    (0x2U)
18470 #define CCM_GPR_SHARED5_SET_m7_mask_cm33_SHIFT   (1U)
18471 /*! m7_mask_cm33 - m7_mask_cm33 */
18472 #define CCM_GPR_SHARED5_SET_m7_mask_cm33(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_cm33_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_cm33_MASK)
18473 
18474 #define CCM_GPR_SHARED5_SET_m7_mask_edma3_MASK   (0x4U)
18475 #define CCM_GPR_SHARED5_SET_m7_mask_edma3_SHIFT  (2U)
18476 /*! m7_mask_edma3 - m7_mask_edma3 */
18477 #define CCM_GPR_SHARED5_SET_m7_mask_edma3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_edma3_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_edma3_MASK)
18478 
18479 #define CCM_GPR_SHARED5_SET_m7_mask_edma4_MASK   (0x8U)
18480 #define CCM_GPR_SHARED5_SET_m7_mask_edma4_SHIFT  (3U)
18481 /*! m7_mask_edma4 - m7_mask_edma4 */
18482 #define CCM_GPR_SHARED5_SET_m7_mask_edma4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_edma4_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_edma4_MASK)
18483 
18484 #define CCM_GPR_SHARED5_SET_m7_mask_netc_MASK    (0x10U)
18485 #define CCM_GPR_SHARED5_SET_m7_mask_netc_SHIFT   (4U)
18486 /*! m7_mask_netc - m7_mask_netc */
18487 #define CCM_GPR_SHARED5_SET_m7_mask_netc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_netc_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_netc_MASK)
18488 
18489 #define CCM_GPR_SHARED5_SET_m7_mask_sim_aon_MASK (0x100U)
18490 #define CCM_GPR_SHARED5_SET_m7_mask_sim_aon_SHIFT (8U)
18491 /*! m7_mask_sim_aon - m7_mask_sim_aon */
18492 #define CCM_GPR_SHARED5_SET_m7_mask_sim_aon(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_sim_aon_MASK)
18493 
18494 #define CCM_GPR_SHARED5_SET_m7_mask_adc1_MASK    (0x200U)
18495 #define CCM_GPR_SHARED5_SET_m7_mask_adc1_SHIFT   (9U)
18496 /*! m7_mask_adc1 - m7_mask_adc1 */
18497 #define CCM_GPR_SHARED5_SET_m7_mask_adc1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_adc1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_adc1_MASK)
18498 
18499 #define CCM_GPR_SHARED5_SET_m7_mask_adc2_MASK    (0x400U)
18500 #define CCM_GPR_SHARED5_SET_m7_mask_adc2_SHIFT   (10U)
18501 /*! m7_mask_adc2 - m7_mask_adc2 */
18502 #define CCM_GPR_SHARED5_SET_m7_mask_adc2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_adc2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_adc2_MASK)
18503 
18504 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi1_MASK (0x800U)
18505 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi1_SHIFT (11U)
18506 /*! m7_mask_flexspi1 - m7_mask_flexspi1 */
18507 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_flexspi1_MASK)
18508 
18509 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi2_MASK (0x1000U)
18510 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi2_SHIFT (12U)
18511 /*! m7_mask_flexspi2 - m7_mask_flexspi2 */
18512 #define CCM_GPR_SHARED5_SET_m7_mask_flexspi2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_flexspi2_MASK)
18513 
18514 #define CCM_GPR_SHARED5_SET_m7_mask_trdc_MASK    (0x2000U)
18515 #define CCM_GPR_SHARED5_SET_m7_mask_trdc_SHIFT   (13U)
18516 /*! m7_mask_trdc - m7_mask_trdc */
18517 #define CCM_GPR_SHARED5_SET_m7_mask_trdc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_trdc_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_trdc_MASK)
18518 
18519 #define CCM_GPR_SHARED5_SET_m7_mask_semc_MASK    (0x4000U)
18520 #define CCM_GPR_SHARED5_SET_m7_mask_semc_SHIFT   (14U)
18521 /*! m7_mask_semc - m7_mask_semc */
18522 #define CCM_GPR_SHARED5_SET_m7_mask_semc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_semc_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_semc_MASK)
18523 
18524 #define CCM_GPR_SHARED5_SET_m7_mask_iee_MASK     (0x8000U)
18525 #define CCM_GPR_SHARED5_SET_m7_mask_iee_SHIFT    (15U)
18526 /*! m7_mask_iee - m7_mask_iee */
18527 #define CCM_GPR_SHARED5_SET_m7_mask_iee(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_iee_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_iee_MASK)
18528 
18529 #define CCM_GPR_SHARED5_SET_m7_mask_gpio1_MASK   (0x10000U)
18530 #define CCM_GPR_SHARED5_SET_m7_mask_gpio1_SHIFT  (16U)
18531 /*! m7_mask_gpio1 - m7_mask_gpio1 */
18532 #define CCM_GPR_SHARED5_SET_m7_mask_gpio1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio1_MASK)
18533 
18534 #define CCM_GPR_SHARED5_SET_m7_mask_gpio2_MASK   (0x20000U)
18535 #define CCM_GPR_SHARED5_SET_m7_mask_gpio2_SHIFT  (17U)
18536 /*! m7_mask_gpio2 - m7_mask_gpio2 */
18537 #define CCM_GPR_SHARED5_SET_m7_mask_gpio2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio2_MASK)
18538 
18539 #define CCM_GPR_SHARED5_SET_m7_mask_gpio3_MASK   (0x40000U)
18540 #define CCM_GPR_SHARED5_SET_m7_mask_gpio3_SHIFT  (18U)
18541 /*! m7_mask_gpio3 - m7_mask_gpio3 */
18542 #define CCM_GPR_SHARED5_SET_m7_mask_gpio3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio3_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio3_MASK)
18543 
18544 #define CCM_GPR_SHARED5_SET_m7_mask_gpio4_MASK   (0x80000U)
18545 #define CCM_GPR_SHARED5_SET_m7_mask_gpio4_SHIFT  (19U)
18546 /*! m7_mask_gpio4 - m7_mask_gpio4 */
18547 #define CCM_GPR_SHARED5_SET_m7_mask_gpio4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio4_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio4_MASK)
18548 
18549 #define CCM_GPR_SHARED5_SET_m7_mask_gpio5_MASK   (0x100000U)
18550 #define CCM_GPR_SHARED5_SET_m7_mask_gpio5_SHIFT  (20U)
18551 /*! m7_mask_gpio5 - m7_mask_gpio5 */
18552 #define CCM_GPR_SHARED5_SET_m7_mask_gpio5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio5_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio5_MASK)
18553 
18554 #define CCM_GPR_SHARED5_SET_m7_mask_gpio6_MASK   (0x200000U)
18555 #define CCM_GPR_SHARED5_SET_m7_mask_gpio6_SHIFT  (21U)
18556 /*! m7_mask_gpio6 - m7_mask_gpio6 */
18557 #define CCM_GPR_SHARED5_SET_m7_mask_gpio6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_gpio6_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_gpio6_MASK)
18558 
18559 #define CCM_GPR_SHARED5_SET_m7_mask_flexio1_MASK (0x400000U)
18560 #define CCM_GPR_SHARED5_SET_m7_mask_flexio1_SHIFT (22U)
18561 /*! m7_mask_flexio1 - m7_mask_flexio1 */
18562 #define CCM_GPR_SHARED5_SET_m7_mask_flexio1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_flexio1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_flexio1_MASK)
18563 
18564 #define CCM_GPR_SHARED5_SET_m7_mask_flexio2_MASK (0x800000U)
18565 #define CCM_GPR_SHARED5_SET_m7_mask_flexio2_SHIFT (23U)
18566 /*! m7_mask_flexio2 - m7_mask_flexio2 */
18567 #define CCM_GPR_SHARED5_SET_m7_mask_flexio2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_flexio2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_flexio2_MASK)
18568 
18569 #define CCM_GPR_SHARED5_SET_m7_mask_lpit1_MASK   (0x1000000U)
18570 #define CCM_GPR_SHARED5_SET_m7_mask_lpit1_SHIFT  (24U)
18571 /*! m7_mask_lpit1 - m7_mask_lpit1 */
18572 #define CCM_GPR_SHARED5_SET_m7_mask_lpit1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_lpit1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_lpit1_MASK)
18573 
18574 #define CCM_GPR_SHARED5_SET_m7_mask_lpit2_MASK   (0x2000000U)
18575 #define CCM_GPR_SHARED5_SET_m7_mask_lpit2_SHIFT  (25U)
18576 /*! m7_mask_lpit2 - m7_mask_lpit2 */
18577 #define CCM_GPR_SHARED5_SET_m7_mask_lpit2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_lpit2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_lpit2_MASK)
18578 
18579 #define CCM_GPR_SHARED5_SET_m7_mask_lpit3_MASK   (0x4000000U)
18580 #define CCM_GPR_SHARED5_SET_m7_mask_lpit3_SHIFT  (26U)
18581 /*! m7_mask_lpit3 - m7_mask_lpit3 */
18582 #define CCM_GPR_SHARED5_SET_m7_mask_lpit3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_lpit3_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_lpit3_MASK)
18583 
18584 #define CCM_GPR_SHARED5_SET_m7_mask_tpm1_MASK    (0x8000000U)
18585 #define CCM_GPR_SHARED5_SET_m7_mask_tpm1_SHIFT   (27U)
18586 /*! m7_mask_tpm1 - m7_mask_tpm1 */
18587 #define CCM_GPR_SHARED5_SET_m7_mask_tpm1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_tpm1_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_tpm1_MASK)
18588 
18589 #define CCM_GPR_SHARED5_SET_m7_mask_tpm2_MASK    (0x10000000U)
18590 #define CCM_GPR_SHARED5_SET_m7_mask_tpm2_SHIFT   (28U)
18591 /*! m7_mask_tpm2 - m7_mask_tpm2 */
18592 #define CCM_GPR_SHARED5_SET_m7_mask_tpm2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_tpm2_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_tpm2_MASK)
18593 
18594 #define CCM_GPR_SHARED5_SET_m7_mask_tpm3_MASK    (0x20000000U)
18595 #define CCM_GPR_SHARED5_SET_m7_mask_tpm3_SHIFT   (29U)
18596 /*! m7_mask_tpm3 - m7_mask_tpm3 */
18597 #define CCM_GPR_SHARED5_SET_m7_mask_tpm3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_tpm3_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_tpm3_MASK)
18598 
18599 #define CCM_GPR_SHARED5_SET_m7_mask_tpm4_MASK    (0x40000000U)
18600 #define CCM_GPR_SHARED5_SET_m7_mask_tpm4_SHIFT   (30U)
18601 /*! m7_mask_tpm4 - m7_mask_tpm4 */
18602 #define CCM_GPR_SHARED5_SET_m7_mask_tpm4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_tpm4_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_tpm4_MASK)
18603 
18604 #define CCM_GPR_SHARED5_SET_m7_mask_tpm5_MASK    (0x80000000U)
18605 #define CCM_GPR_SHARED5_SET_m7_mask_tpm5_SHIFT   (31U)
18606 /*! m7_mask_tpm5 - m7_mask_tpm5 */
18607 #define CCM_GPR_SHARED5_SET_m7_mask_tpm5(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_SET_m7_mask_tpm5_SHIFT)) & CCM_GPR_SHARED5_SET_m7_mask_tpm5_MASK)
18608 /*! @} */
18609 
18610 /*! @name GPR_SHARED5_CLR - General Purpose Register */
18611 /*! @{ */
18612 
18613 #define CCM_GPR_SHARED5_CLR_m7_mask_cm7_MASK     (0x1U)
18614 #define CCM_GPR_SHARED5_CLR_m7_mask_cm7_SHIFT    (0U)
18615 /*! m7_mask_cm7 - m7_mask_cm7 */
18616 #define CCM_GPR_SHARED5_CLR_m7_mask_cm7(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_cm7_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_cm7_MASK)
18617 
18618 #define CCM_GPR_SHARED5_CLR_m7_mask_cm33_MASK    (0x2U)
18619 #define CCM_GPR_SHARED5_CLR_m7_mask_cm33_SHIFT   (1U)
18620 /*! m7_mask_cm33 - m7_mask_cm33 */
18621 #define CCM_GPR_SHARED5_CLR_m7_mask_cm33(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_cm33_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_cm33_MASK)
18622 
18623 #define CCM_GPR_SHARED5_CLR_m7_mask_edma3_MASK   (0x4U)
18624 #define CCM_GPR_SHARED5_CLR_m7_mask_edma3_SHIFT  (2U)
18625 /*! m7_mask_edma3 - m7_mask_edma3 */
18626 #define CCM_GPR_SHARED5_CLR_m7_mask_edma3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_edma3_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_edma3_MASK)
18627 
18628 #define CCM_GPR_SHARED5_CLR_m7_mask_edma4_MASK   (0x8U)
18629 #define CCM_GPR_SHARED5_CLR_m7_mask_edma4_SHIFT  (3U)
18630 /*! m7_mask_edma4 - m7_mask_edma4 */
18631 #define CCM_GPR_SHARED5_CLR_m7_mask_edma4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_edma4_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_edma4_MASK)
18632 
18633 #define CCM_GPR_SHARED5_CLR_m7_mask_netc_MASK    (0x10U)
18634 #define CCM_GPR_SHARED5_CLR_m7_mask_netc_SHIFT   (4U)
18635 /*! m7_mask_netc - m7_mask_netc */
18636 #define CCM_GPR_SHARED5_CLR_m7_mask_netc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_netc_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_netc_MASK)
18637 
18638 #define CCM_GPR_SHARED5_CLR_m7_mask_sim_aon_MASK (0x100U)
18639 #define CCM_GPR_SHARED5_CLR_m7_mask_sim_aon_SHIFT (8U)
18640 /*! m7_mask_sim_aon - m7_mask_sim_aon */
18641 #define CCM_GPR_SHARED5_CLR_m7_mask_sim_aon(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_sim_aon_MASK)
18642 
18643 #define CCM_GPR_SHARED5_CLR_m7_mask_adc1_MASK    (0x200U)
18644 #define CCM_GPR_SHARED5_CLR_m7_mask_adc1_SHIFT   (9U)
18645 /*! m7_mask_adc1 - m7_mask_adc1 */
18646 #define CCM_GPR_SHARED5_CLR_m7_mask_adc1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_adc1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_adc1_MASK)
18647 
18648 #define CCM_GPR_SHARED5_CLR_m7_mask_adc2_MASK    (0x400U)
18649 #define CCM_GPR_SHARED5_CLR_m7_mask_adc2_SHIFT   (10U)
18650 /*! m7_mask_adc2 - m7_mask_adc2 */
18651 #define CCM_GPR_SHARED5_CLR_m7_mask_adc2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_adc2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_adc2_MASK)
18652 
18653 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi1_MASK (0x800U)
18654 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi1_SHIFT (11U)
18655 /*! m7_mask_flexspi1 - m7_mask_flexspi1 */
18656 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_flexspi1_MASK)
18657 
18658 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi2_MASK (0x1000U)
18659 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi2_SHIFT (12U)
18660 /*! m7_mask_flexspi2 - m7_mask_flexspi2 */
18661 #define CCM_GPR_SHARED5_CLR_m7_mask_flexspi2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_flexspi2_MASK)
18662 
18663 #define CCM_GPR_SHARED5_CLR_m7_mask_trdc_MASK    (0x2000U)
18664 #define CCM_GPR_SHARED5_CLR_m7_mask_trdc_SHIFT   (13U)
18665 /*! m7_mask_trdc - m7_mask_trdc */
18666 #define CCM_GPR_SHARED5_CLR_m7_mask_trdc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_trdc_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_trdc_MASK)
18667 
18668 #define CCM_GPR_SHARED5_CLR_m7_mask_semc_MASK    (0x4000U)
18669 #define CCM_GPR_SHARED5_CLR_m7_mask_semc_SHIFT   (14U)
18670 /*! m7_mask_semc - m7_mask_semc */
18671 #define CCM_GPR_SHARED5_CLR_m7_mask_semc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_semc_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_semc_MASK)
18672 
18673 #define CCM_GPR_SHARED5_CLR_m7_mask_iee_MASK     (0x8000U)
18674 #define CCM_GPR_SHARED5_CLR_m7_mask_iee_SHIFT    (15U)
18675 /*! m7_mask_iee - m7_mask_iee */
18676 #define CCM_GPR_SHARED5_CLR_m7_mask_iee(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_iee_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_iee_MASK)
18677 
18678 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio1_MASK   (0x10000U)
18679 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio1_SHIFT  (16U)
18680 /*! m7_mask_gpio1 - m7_mask_gpio1 */
18681 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio1_MASK)
18682 
18683 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio2_MASK   (0x20000U)
18684 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio2_SHIFT  (17U)
18685 /*! m7_mask_gpio2 - m7_mask_gpio2 */
18686 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio2_MASK)
18687 
18688 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio3_MASK   (0x40000U)
18689 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio3_SHIFT  (18U)
18690 /*! m7_mask_gpio3 - m7_mask_gpio3 */
18691 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio3_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio3_MASK)
18692 
18693 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio4_MASK   (0x80000U)
18694 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio4_SHIFT  (19U)
18695 /*! m7_mask_gpio4 - m7_mask_gpio4 */
18696 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio4_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio4_MASK)
18697 
18698 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio5_MASK   (0x100000U)
18699 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio5_SHIFT  (20U)
18700 /*! m7_mask_gpio5 - m7_mask_gpio5 */
18701 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio5_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio5_MASK)
18702 
18703 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio6_MASK   (0x200000U)
18704 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio6_SHIFT  (21U)
18705 /*! m7_mask_gpio6 - m7_mask_gpio6 */
18706 #define CCM_GPR_SHARED5_CLR_m7_mask_gpio6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_gpio6_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_gpio6_MASK)
18707 
18708 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio1_MASK (0x400000U)
18709 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio1_SHIFT (22U)
18710 /*! m7_mask_flexio1 - m7_mask_flexio1 */
18711 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_flexio1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_flexio1_MASK)
18712 
18713 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio2_MASK (0x800000U)
18714 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio2_SHIFT (23U)
18715 /*! m7_mask_flexio2 - m7_mask_flexio2 */
18716 #define CCM_GPR_SHARED5_CLR_m7_mask_flexio2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_flexio2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_flexio2_MASK)
18717 
18718 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit1_MASK   (0x1000000U)
18719 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit1_SHIFT  (24U)
18720 /*! m7_mask_lpit1 - m7_mask_lpit1 */
18721 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_lpit1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_lpit1_MASK)
18722 
18723 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit2_MASK   (0x2000000U)
18724 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit2_SHIFT  (25U)
18725 /*! m7_mask_lpit2 - m7_mask_lpit2 */
18726 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_lpit2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_lpit2_MASK)
18727 
18728 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit3_MASK   (0x4000000U)
18729 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit3_SHIFT  (26U)
18730 /*! m7_mask_lpit3 - m7_mask_lpit3 */
18731 #define CCM_GPR_SHARED5_CLR_m7_mask_lpit3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_lpit3_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_lpit3_MASK)
18732 
18733 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm1_MASK    (0x8000000U)
18734 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm1_SHIFT   (27U)
18735 /*! m7_mask_tpm1 - m7_mask_tpm1 */
18736 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_tpm1_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_tpm1_MASK)
18737 
18738 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm2_MASK    (0x10000000U)
18739 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm2_SHIFT   (28U)
18740 /*! m7_mask_tpm2 - m7_mask_tpm2 */
18741 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_tpm2_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_tpm2_MASK)
18742 
18743 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm3_MASK    (0x20000000U)
18744 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm3_SHIFT   (29U)
18745 /*! m7_mask_tpm3 - m7_mask_tpm3 */
18746 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_tpm3_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_tpm3_MASK)
18747 
18748 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm4_MASK    (0x40000000U)
18749 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm4_SHIFT   (30U)
18750 /*! m7_mask_tpm4 - m7_mask_tpm4 */
18751 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_tpm4_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_tpm4_MASK)
18752 
18753 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm5_MASK    (0x80000000U)
18754 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm5_SHIFT   (31U)
18755 /*! m7_mask_tpm5 - m7_mask_tpm5 */
18756 #define CCM_GPR_SHARED5_CLR_m7_mask_tpm5(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_CLR_m7_mask_tpm5_SHIFT)) & CCM_GPR_SHARED5_CLR_m7_mask_tpm5_MASK)
18757 /*! @} */
18758 
18759 /*! @name GPR_SHARED5_TOG - General Purpose Register */
18760 /*! @{ */
18761 
18762 #define CCM_GPR_SHARED5_TOG_m7_mask_cm7_MASK     (0x1U)
18763 #define CCM_GPR_SHARED5_TOG_m7_mask_cm7_SHIFT    (0U)
18764 /*! m7_mask_cm7 - m7_mask_cm7 */
18765 #define CCM_GPR_SHARED5_TOG_m7_mask_cm7(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_cm7_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_cm7_MASK)
18766 
18767 #define CCM_GPR_SHARED5_TOG_m7_mask_cm33_MASK    (0x2U)
18768 #define CCM_GPR_SHARED5_TOG_m7_mask_cm33_SHIFT   (1U)
18769 /*! m7_mask_cm33 - m7_mask_cm33 */
18770 #define CCM_GPR_SHARED5_TOG_m7_mask_cm33(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_cm33_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_cm33_MASK)
18771 
18772 #define CCM_GPR_SHARED5_TOG_m7_mask_edma3_MASK   (0x4U)
18773 #define CCM_GPR_SHARED5_TOG_m7_mask_edma3_SHIFT  (2U)
18774 /*! m7_mask_edma3 - m7_mask_edma3 */
18775 #define CCM_GPR_SHARED5_TOG_m7_mask_edma3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_edma3_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_edma3_MASK)
18776 
18777 #define CCM_GPR_SHARED5_TOG_m7_mask_edma4_MASK   (0x8U)
18778 #define CCM_GPR_SHARED5_TOG_m7_mask_edma4_SHIFT  (3U)
18779 /*! m7_mask_edma4 - m7_mask_edma4 */
18780 #define CCM_GPR_SHARED5_TOG_m7_mask_edma4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_edma4_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_edma4_MASK)
18781 
18782 #define CCM_GPR_SHARED5_TOG_m7_mask_netc_MASK    (0x10U)
18783 #define CCM_GPR_SHARED5_TOG_m7_mask_netc_SHIFT   (4U)
18784 /*! m7_mask_netc - m7_mask_netc */
18785 #define CCM_GPR_SHARED5_TOG_m7_mask_netc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_netc_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_netc_MASK)
18786 
18787 #define CCM_GPR_SHARED5_TOG_m7_mask_sim_aon_MASK (0x100U)
18788 #define CCM_GPR_SHARED5_TOG_m7_mask_sim_aon_SHIFT (8U)
18789 /*! m7_mask_sim_aon - m7_mask_sim_aon */
18790 #define CCM_GPR_SHARED5_TOG_m7_mask_sim_aon(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_sim_aon_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_sim_aon_MASK)
18791 
18792 #define CCM_GPR_SHARED5_TOG_m7_mask_adc1_MASK    (0x200U)
18793 #define CCM_GPR_SHARED5_TOG_m7_mask_adc1_SHIFT   (9U)
18794 /*! m7_mask_adc1 - m7_mask_adc1 */
18795 #define CCM_GPR_SHARED5_TOG_m7_mask_adc1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_adc1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_adc1_MASK)
18796 
18797 #define CCM_GPR_SHARED5_TOG_m7_mask_adc2_MASK    (0x400U)
18798 #define CCM_GPR_SHARED5_TOG_m7_mask_adc2_SHIFT   (10U)
18799 /*! m7_mask_adc2 - m7_mask_adc2 */
18800 #define CCM_GPR_SHARED5_TOG_m7_mask_adc2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_adc2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_adc2_MASK)
18801 
18802 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi1_MASK (0x800U)
18803 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi1_SHIFT (11U)
18804 /*! m7_mask_flexspi1 - m7_mask_flexspi1 */
18805 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi1(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_flexspi1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_flexspi1_MASK)
18806 
18807 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi2_MASK (0x1000U)
18808 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi2_SHIFT (12U)
18809 /*! m7_mask_flexspi2 - m7_mask_flexspi2 */
18810 #define CCM_GPR_SHARED5_TOG_m7_mask_flexspi2(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_flexspi2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_flexspi2_MASK)
18811 
18812 #define CCM_GPR_SHARED5_TOG_m7_mask_trdc_MASK    (0x2000U)
18813 #define CCM_GPR_SHARED5_TOG_m7_mask_trdc_SHIFT   (13U)
18814 /*! m7_mask_trdc - m7_mask_trdc */
18815 #define CCM_GPR_SHARED5_TOG_m7_mask_trdc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_trdc_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_trdc_MASK)
18816 
18817 #define CCM_GPR_SHARED5_TOG_m7_mask_semc_MASK    (0x4000U)
18818 #define CCM_GPR_SHARED5_TOG_m7_mask_semc_SHIFT   (14U)
18819 /*! m7_mask_semc - m7_mask_semc */
18820 #define CCM_GPR_SHARED5_TOG_m7_mask_semc(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_semc_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_semc_MASK)
18821 
18822 #define CCM_GPR_SHARED5_TOG_m7_mask_iee_MASK     (0x8000U)
18823 #define CCM_GPR_SHARED5_TOG_m7_mask_iee_SHIFT    (15U)
18824 /*! m7_mask_iee - m7_mask_iee */
18825 #define CCM_GPR_SHARED5_TOG_m7_mask_iee(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_iee_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_iee_MASK)
18826 
18827 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio1_MASK   (0x10000U)
18828 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio1_SHIFT  (16U)
18829 /*! m7_mask_gpio1 - m7_mask_gpio1 */
18830 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio1_MASK)
18831 
18832 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio2_MASK   (0x20000U)
18833 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio2_SHIFT  (17U)
18834 /*! m7_mask_gpio2 - m7_mask_gpio2 */
18835 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio2_MASK)
18836 
18837 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio3_MASK   (0x40000U)
18838 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio3_SHIFT  (18U)
18839 /*! m7_mask_gpio3 - m7_mask_gpio3 */
18840 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio3_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio3_MASK)
18841 
18842 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio4_MASK   (0x80000U)
18843 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio4_SHIFT  (19U)
18844 /*! m7_mask_gpio4 - m7_mask_gpio4 */
18845 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio4(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio4_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio4_MASK)
18846 
18847 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio5_MASK   (0x100000U)
18848 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio5_SHIFT  (20U)
18849 /*! m7_mask_gpio5 - m7_mask_gpio5 */
18850 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio5(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio5_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio5_MASK)
18851 
18852 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio6_MASK   (0x200000U)
18853 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio6_SHIFT  (21U)
18854 /*! m7_mask_gpio6 - m7_mask_gpio6 */
18855 #define CCM_GPR_SHARED5_TOG_m7_mask_gpio6(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_gpio6_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_gpio6_MASK)
18856 
18857 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio1_MASK (0x400000U)
18858 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio1_SHIFT (22U)
18859 /*! m7_mask_flexio1 - m7_mask_flexio1 */
18860 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_flexio1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_flexio1_MASK)
18861 
18862 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio2_MASK (0x800000U)
18863 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio2_SHIFT (23U)
18864 /*! m7_mask_flexio2 - m7_mask_flexio2 */
18865 #define CCM_GPR_SHARED5_TOG_m7_mask_flexio2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_flexio2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_flexio2_MASK)
18866 
18867 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit1_MASK   (0x1000000U)
18868 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit1_SHIFT  (24U)
18869 /*! m7_mask_lpit1 - m7_mask_lpit1 */
18870 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_lpit1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_lpit1_MASK)
18871 
18872 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit2_MASK   (0x2000000U)
18873 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit2_SHIFT  (25U)
18874 /*! m7_mask_lpit2 - m7_mask_lpit2 */
18875 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_lpit2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_lpit2_MASK)
18876 
18877 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit3_MASK   (0x4000000U)
18878 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit3_SHIFT  (26U)
18879 /*! m7_mask_lpit3 - m7_mask_lpit3 */
18880 #define CCM_GPR_SHARED5_TOG_m7_mask_lpit3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_lpit3_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_lpit3_MASK)
18881 
18882 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm1_MASK    (0x8000000U)
18883 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm1_SHIFT   (27U)
18884 /*! m7_mask_tpm1 - m7_mask_tpm1 */
18885 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_tpm1_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_tpm1_MASK)
18886 
18887 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm2_MASK    (0x10000000U)
18888 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm2_SHIFT   (28U)
18889 /*! m7_mask_tpm2 - m7_mask_tpm2 */
18890 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_tpm2_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_tpm2_MASK)
18891 
18892 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm3_MASK    (0x20000000U)
18893 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm3_SHIFT   (29U)
18894 /*! m7_mask_tpm3 - m7_mask_tpm3 */
18895 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_tpm3_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_tpm3_MASK)
18896 
18897 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm4_MASK    (0x40000000U)
18898 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm4_SHIFT   (30U)
18899 /*! m7_mask_tpm4 - m7_mask_tpm4 */
18900 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_tpm4_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_tpm4_MASK)
18901 
18902 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm5_MASK    (0x80000000U)
18903 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm5_SHIFT   (31U)
18904 /*! m7_mask_tpm5 - m7_mask_tpm5 */
18905 #define CCM_GPR_SHARED5_TOG_m7_mask_tpm5(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_TOG_m7_mask_tpm5_SHIFT)) & CCM_GPR_SHARED5_TOG_m7_mask_tpm5_MASK)
18906 /*! @} */
18907 
18908 /*! @name GPR_SHARED5_AUTHEN - GPR access control */
18909 /*! @{ */
18910 
18911 #define CCM_GPR_SHARED5_AUTHEN_TZ_USER_MASK      (0x100U)
18912 #define CCM_GPR_SHARED5_AUTHEN_TZ_USER_SHIFT     (8U)
18913 /*! TZ_USER - User access permission
18914  *  0b1..Registers of shared GPR slice can be changed in user mode.
18915  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
18916  */
18917 #define CCM_GPR_SHARED5_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TZ_USER_MASK)
18918 
18919 #define CCM_GPR_SHARED5_AUTHEN_TZ_NS_MASK        (0x200U)
18920 #define CCM_GPR_SHARED5_AUTHEN_TZ_NS_SHIFT       (9U)
18921 /*! TZ_NS - Non-secure access permission
18922  *  0b0..Cannot be changed in Non-secure mode.
18923  *  0b1..Can be changed in Non-secure mode.
18924  */
18925 #define CCM_GPR_SHARED5_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TZ_NS_MASK)
18926 
18927 #define CCM_GPR_SHARED5_AUTHEN_LOCK_TZ_MASK      (0x800U)
18928 #define CCM_GPR_SHARED5_AUTHEN_LOCK_TZ_SHIFT     (11U)
18929 /*! LOCK_TZ - Lock TrustZone settings
18930  *  0b0..TrustZone settings is not locked.
18931  *  0b1..TrustZone settings is locked.
18932  */
18933 #define CCM_GPR_SHARED5_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_LOCK_TZ_MASK)
18934 
18935 #define CCM_GPR_SHARED5_AUTHEN_LOCK_LIST_MASK    (0x8000U)
18936 #define CCM_GPR_SHARED5_AUTHEN_LOCK_LIST_SHIFT   (15U)
18937 /*! LOCK_LIST - Lock white list
18938  *  0b0..Whitelist is not locked.
18939  *  0b1..Whitelist is locked.
18940  */
18941 #define CCM_GPR_SHARED5_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_LOCK_LIST_MASK)
18942 
18943 #define CCM_GPR_SHARED5_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
18944 #define CCM_GPR_SHARED5_AUTHEN_WHITE_LIST_SHIFT  (16U)
18945 /*! WHITE_LIST - Whitelist settings */
18946 #define CCM_GPR_SHARED5_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_WHITE_LIST_MASK)
18947 /*! @} */
18948 
18949 /*! @name GPR_SHARED5_AUTHEN_SET - GPR access control */
18950 /*! @{ */
18951 
18952 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_USER_MASK  (0x100U)
18953 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_USER_SHIFT (8U)
18954 /*! TZ_USER - User access permission */
18955 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_SET_TZ_USER_MASK)
18956 
18957 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_NS_MASK    (0x200U)
18958 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_NS_SHIFT   (9U)
18959 /*! TZ_NS - Non-secure access permission */
18960 #define CCM_GPR_SHARED5_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_SET_TZ_NS_MASK)
18961 
18962 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
18963 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
18964 /*! LOCK_TZ - Lock TrustZone settings */
18965 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_SET_LOCK_TZ_MASK)
18966 
18967 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
18968 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
18969 /*! LOCK_LIST - Lock white list */
18970 #define CCM_GPR_SHARED5_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_SET_LOCK_LIST_MASK)
18971 
18972 #define CCM_GPR_SHARED5_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
18973 #define CCM_GPR_SHARED5_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
18974 /*! WHITE_LIST - Whitelist settings */
18975 #define CCM_GPR_SHARED5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_SET_WHITE_LIST_MASK)
18976 /*! @} */
18977 
18978 /*! @name GPR_SHARED5_AUTHEN_CLR - GPR access control */
18979 /*! @{ */
18980 
18981 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
18982 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_USER_SHIFT (8U)
18983 /*! TZ_USER - User access permission */
18984 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_CLR_TZ_USER_MASK)
18985 
18986 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
18987 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
18988 /*! TZ_NS - Non-secure access permission */
18989 #define CCM_GPR_SHARED5_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_CLR_TZ_NS_MASK)
18990 
18991 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
18992 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
18993 /*! LOCK_TZ - Lock TrustZone settings */
18994 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_TZ_MASK)
18995 
18996 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
18997 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
18998 /*! LOCK_LIST - Lock white list */
18999 #define CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_CLR_LOCK_LIST_MASK)
19000 
19001 #define CCM_GPR_SHARED5_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
19002 #define CCM_GPR_SHARED5_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
19003 /*! WHITE_LIST - Whitelist settings */
19004 #define CCM_GPR_SHARED5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_CLR_WHITE_LIST_MASK)
19005 /*! @} */
19006 
19007 /*! @name GPR_SHARED5_AUTHEN_TOG - GPR access control */
19008 /*! @{ */
19009 
19010 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
19011 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_USER_SHIFT (8U)
19012 /*! TZ_USER - User access permission */
19013 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TOG_TZ_USER_MASK)
19014 
19015 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
19016 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
19017 /*! TZ_NS - Non-secure access permission */
19018 #define CCM_GPR_SHARED5_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TOG_TZ_NS_MASK)
19019 
19020 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
19021 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
19022 /*! LOCK_TZ - Lock TrustZone settings */
19023 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_TZ_MASK)
19024 
19025 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
19026 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
19027 /*! LOCK_LIST - Lock white list */
19028 #define CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TOG_LOCK_LIST_MASK)
19029 
19030 #define CCM_GPR_SHARED5_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
19031 #define CCM_GPR_SHARED5_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
19032 /*! WHITE_LIST - Whitelist settings */
19033 #define CCM_GPR_SHARED5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED5_AUTHEN_TOG_WHITE_LIST_MASK)
19034 /*! @} */
19035 
19036 /*! @name GPR_SHARED6 - General Purpose Register */
19037 /*! @{ */
19038 
19039 #define CCM_GPR_SHARED6_m7_mask_tpm6_MASK        (0x1U)
19040 #define CCM_GPR_SHARED6_m7_mask_tpm6_SHIFT       (0U)
19041 /*! m7_mask_tpm6 - m7_mask_tpm6 */
19042 #define CCM_GPR_SHARED6_m7_mask_tpm6(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_tpm6_SHIFT)) & CCM_GPR_SHARED6_m7_mask_tpm6_MASK)
19043 
19044 #define CCM_GPR_SHARED6_m7_mask_gpt1_MASK        (0x2U)
19045 #define CCM_GPR_SHARED6_m7_mask_gpt1_SHIFT       (1U)
19046 /*! m7_mask_gpt1 - m7_mask_gpt1 */
19047 #define CCM_GPR_SHARED6_m7_mask_gpt1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_gpt1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_gpt1_MASK)
19048 
19049 #define CCM_GPR_SHARED6_m7_mask_gpt2_MASK        (0x4U)
19050 #define CCM_GPR_SHARED6_m7_mask_gpt2_SHIFT       (2U)
19051 /*! m7_mask_gpt2 - m7_mask_gpt2 */
19052 #define CCM_GPR_SHARED6_m7_mask_gpt2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_gpt2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_gpt2_MASK)
19053 
19054 #define CCM_GPR_SHARED6_m7_mask_can1_MASK        (0x8U)
19055 #define CCM_GPR_SHARED6_m7_mask_can1_SHIFT       (3U)
19056 /*! m7_mask_can1 - m7_mask_can1 */
19057 #define CCM_GPR_SHARED6_m7_mask_can1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_can1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_can1_MASK)
19058 
19059 #define CCM_GPR_SHARED6_m7_mask_can2_MASK        (0x10U)
19060 #define CCM_GPR_SHARED6_m7_mask_can2_SHIFT       (4U)
19061 /*! m7_mask_can2 - m7_mask_can2 */
19062 #define CCM_GPR_SHARED6_m7_mask_can2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_can2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_can2_MASK)
19063 
19064 #define CCM_GPR_SHARED6_m7_mask_can3_MASK        (0x20U)
19065 #define CCM_GPR_SHARED6_m7_mask_can3_SHIFT       (5U)
19066 /*! m7_mask_can3 - m7_mask_can3 */
19067 #define CCM_GPR_SHARED6_m7_mask_can3(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_can3_SHIFT)) & CCM_GPR_SHARED6_m7_mask_can3_MASK)
19068 
19069 #define CCM_GPR_SHARED6_m7_mask_lpuart1_MASK     (0x40U)
19070 #define CCM_GPR_SHARED6_m7_mask_lpuart1_SHIFT    (6U)
19071 /*! m7_mask_lpuart1 - m7_mask_lpuart1 */
19072 #define CCM_GPR_SHARED6_m7_mask_lpuart1(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart1_MASK)
19073 
19074 #define CCM_GPR_SHARED6_m7_mask_lpuart2_MASK     (0x80U)
19075 #define CCM_GPR_SHARED6_m7_mask_lpuart2_SHIFT    (7U)
19076 /*! m7_mask_lpuart2 - m7_mask_lpuart2 */
19077 #define CCM_GPR_SHARED6_m7_mask_lpuart2(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart2_MASK)
19078 
19079 #define CCM_GPR_SHARED6_m7_mask_lpuart3_MASK     (0x100U)
19080 #define CCM_GPR_SHARED6_m7_mask_lpuart3_SHIFT    (8U)
19081 /*! m7_mask_lpuart3 - m7_mask_lpuart3 */
19082 #define CCM_GPR_SHARED6_m7_mask_lpuart3(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart3_MASK)
19083 
19084 #define CCM_GPR_SHARED6_m7_mask_lpuart4_MASK     (0x200U)
19085 #define CCM_GPR_SHARED6_m7_mask_lpuart4_SHIFT    (9U)
19086 /*! m7_mask_lpuart4 - m7_mask_lpuart4 */
19087 #define CCM_GPR_SHARED6_m7_mask_lpuart4(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart4_MASK)
19088 
19089 #define CCM_GPR_SHARED6_m7_mask_lpuart5_MASK     (0x400U)
19090 #define CCM_GPR_SHARED6_m7_mask_lpuart5_SHIFT    (10U)
19091 /*! m7_mask_lpuart5 - m7_mask_lpuart5 */
19092 #define CCM_GPR_SHARED6_m7_mask_lpuart5(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart5_MASK)
19093 
19094 #define CCM_GPR_SHARED6_m7_mask_lpuart6_MASK     (0x800U)
19095 #define CCM_GPR_SHARED6_m7_mask_lpuart6_SHIFT    (11U)
19096 /*! m7_mask_lpuart6 - m7_mask_lpuart6 */
19097 #define CCM_GPR_SHARED6_m7_mask_lpuart6(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart6_MASK)
19098 
19099 #define CCM_GPR_SHARED6_m7_mask_lpuart7_MASK     (0x1000U)
19100 #define CCM_GPR_SHARED6_m7_mask_lpuart7_SHIFT    (12U)
19101 /*! m7_mask_lpuart7 - m7_mask_lpuart7 */
19102 #define CCM_GPR_SHARED6_m7_mask_lpuart7(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart7_MASK)
19103 
19104 #define CCM_GPR_SHARED6_m7_mask_lpuart8_MASK     (0x2000U)
19105 #define CCM_GPR_SHARED6_m7_mask_lpuart8_SHIFT    (13U)
19106 /*! m7_mask_lpuart8 - m7_mask_lpuart8 */
19107 #define CCM_GPR_SHARED6_m7_mask_lpuart8(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart8_MASK)
19108 
19109 #define CCM_GPR_SHARED6_m7_mask_lpuart9_MASK     (0x4000U)
19110 #define CCM_GPR_SHARED6_m7_mask_lpuart9_SHIFT    (14U)
19111 /*! m7_mask_lpuart9 - m7_mask_lpuart9 */
19112 #define CCM_GPR_SHARED6_m7_mask_lpuart9(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart9_MASK)
19113 
19114 #define CCM_GPR_SHARED6_m7_mask_lpuart10_MASK    (0x8000U)
19115 #define CCM_GPR_SHARED6_m7_mask_lpuart10_SHIFT   (15U)
19116 /*! m7_mask_lpuart10 - m7_mask_lpuart10 */
19117 #define CCM_GPR_SHARED6_m7_mask_lpuart10(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart10_MASK)
19118 
19119 #define CCM_GPR_SHARED6_m7_mask_lpuart11_MASK    (0x10000U)
19120 #define CCM_GPR_SHARED6_m7_mask_lpuart11_SHIFT   (16U)
19121 /*! m7_mask_lpuart11 - m7_mask_lpuart11 */
19122 #define CCM_GPR_SHARED6_m7_mask_lpuart11(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart11_MASK)
19123 
19124 #define CCM_GPR_SHARED6_m7_mask_lpuart12_MASK    (0x20000U)
19125 #define CCM_GPR_SHARED6_m7_mask_lpuart12_SHIFT   (17U)
19126 /*! m7_mask_lpuart12 - m7_mask_lpuart12 */
19127 #define CCM_GPR_SHARED6_m7_mask_lpuart12(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpuart12_MASK)
19128 
19129 #define CCM_GPR_SHARED6_m7_mask_lpi2c1_MASK      (0x40000U)
19130 #define CCM_GPR_SHARED6_m7_mask_lpi2c1_SHIFT     (18U)
19131 /*! m7_mask_lpi2c1 - m7_mask_lpi2c1 */
19132 #define CCM_GPR_SHARED6_m7_mask_lpi2c1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c1_MASK)
19133 
19134 #define CCM_GPR_SHARED6_m7_mask_lpi2c2_MASK      (0x80000U)
19135 #define CCM_GPR_SHARED6_m7_mask_lpi2c2_SHIFT     (19U)
19136 /*! m7_mask_lpi2c2 - m7_mask_lpi2c2 */
19137 #define CCM_GPR_SHARED6_m7_mask_lpi2c2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c2_MASK)
19138 
19139 #define CCM_GPR_SHARED6_m7_mask_lpi2c3_MASK      (0x100000U)
19140 #define CCM_GPR_SHARED6_m7_mask_lpi2c3_SHIFT     (20U)
19141 /*! m7_mask_lpi2c3 - m7_mask_lpi2c3 */
19142 #define CCM_GPR_SHARED6_m7_mask_lpi2c3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c3_MASK)
19143 
19144 #define CCM_GPR_SHARED6_m7_mask_lpi2c4_MASK      (0x200000U)
19145 #define CCM_GPR_SHARED6_m7_mask_lpi2c4_SHIFT     (21U)
19146 /*! m7_mask_lpi2c4 - m7_mask_lpi2c4 */
19147 #define CCM_GPR_SHARED6_m7_mask_lpi2c4(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c4_MASK)
19148 
19149 #define CCM_GPR_SHARED6_m7_mask_lpi2c5_MASK      (0x400000U)
19150 #define CCM_GPR_SHARED6_m7_mask_lpi2c5_SHIFT     (22U)
19151 /*! m7_mask_lpi2c5 - m7_mask_lpi2c5 */
19152 #define CCM_GPR_SHARED6_m7_mask_lpi2c5(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c5_MASK)
19153 
19154 #define CCM_GPR_SHARED6_m7_mask_lpi2c6_MASK      (0x800000U)
19155 #define CCM_GPR_SHARED6_m7_mask_lpi2c6_SHIFT     (23U)
19156 /*! m7_mask_lpi2c6 - m7_mask_lpi2c6 */
19157 #define CCM_GPR_SHARED6_m7_mask_lpi2c6(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpi2c6_MASK)
19158 
19159 #define CCM_GPR_SHARED6_m7_mask_lpspi1_MASK      (0x1000000U)
19160 #define CCM_GPR_SHARED6_m7_mask_lpspi1_SHIFT     (24U)
19161 /*! m7_mask_lpspi1 - m7_mask_lpspi1 */
19162 #define CCM_GPR_SHARED6_m7_mask_lpspi1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi1_MASK)
19163 
19164 #define CCM_GPR_SHARED6_m7_mask_lpspi2_MASK      (0x2000000U)
19165 #define CCM_GPR_SHARED6_m7_mask_lpspi2_SHIFT     (25U)
19166 /*! m7_mask_lpspi2 - m7_mask_lpspi2 */
19167 #define CCM_GPR_SHARED6_m7_mask_lpspi2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi2_MASK)
19168 
19169 #define CCM_GPR_SHARED6_m7_mask_lpspi3_MASK      (0x4000000U)
19170 #define CCM_GPR_SHARED6_m7_mask_lpspi3_SHIFT     (26U)
19171 /*! m7_mask_lpspi3 - m7_mask_lpspi3 */
19172 #define CCM_GPR_SHARED6_m7_mask_lpspi3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi3_MASK)
19173 
19174 #define CCM_GPR_SHARED6_m7_mask_lpspi4_MASK      (0x8000000U)
19175 #define CCM_GPR_SHARED6_m7_mask_lpspi4_SHIFT     (27U)
19176 /*! m7_mask_lpspi4 - m7_mask_lpspi4 */
19177 #define CCM_GPR_SHARED6_m7_mask_lpspi4(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi4_MASK)
19178 
19179 #define CCM_GPR_SHARED6_m7_mask_lpspi5_MASK      (0x10000000U)
19180 #define CCM_GPR_SHARED6_m7_mask_lpspi5_SHIFT     (28U)
19181 /*! m7_mask_lpspi5 - m7_mask_lpspi5 */
19182 #define CCM_GPR_SHARED6_m7_mask_lpspi5(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi5_MASK)
19183 
19184 #define CCM_GPR_SHARED6_m7_mask_lpspi6_MASK      (0x20000000U)
19185 #define CCM_GPR_SHARED6_m7_mask_lpspi6_SHIFT     (29U)
19186 /*! m7_mask_lpspi6 - m7_mask_lpspi6 */
19187 #define CCM_GPR_SHARED6_m7_mask_lpspi6(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED6_m7_mask_lpspi6_MASK)
19188 
19189 #define CCM_GPR_SHARED6_m7_mask_sinc1_MASK       (0x40000000U)
19190 #define CCM_GPR_SHARED6_m7_mask_sinc1_SHIFT      (30U)
19191 /*! m7_mask_sinc1 - m7_mask_sinc1 */
19192 #define CCM_GPR_SHARED6_m7_mask_sinc1(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_sinc1_SHIFT)) & CCM_GPR_SHARED6_m7_mask_sinc1_MASK)
19193 
19194 #define CCM_GPR_SHARED6_m7_mask_sinc2_MASK       (0x80000000U)
19195 #define CCM_GPR_SHARED6_m7_mask_sinc2_SHIFT      (31U)
19196 /*! m7_mask_sinc2 - m7_mask_sinc2 */
19197 #define CCM_GPR_SHARED6_m7_mask_sinc2(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_m7_mask_sinc2_SHIFT)) & CCM_GPR_SHARED6_m7_mask_sinc2_MASK)
19198 /*! @} */
19199 
19200 /*! @name GPR_SHARED6_SET - General Purpose Register */
19201 /*! @{ */
19202 
19203 #define CCM_GPR_SHARED6_SET_m7_mask_tpm6_MASK    (0x1U)
19204 #define CCM_GPR_SHARED6_SET_m7_mask_tpm6_SHIFT   (0U)
19205 /*! m7_mask_tpm6 - m7_mask_tpm6 */
19206 #define CCM_GPR_SHARED6_SET_m7_mask_tpm6(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_tpm6_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_tpm6_MASK)
19207 
19208 #define CCM_GPR_SHARED6_SET_m7_mask_gpt1_MASK    (0x2U)
19209 #define CCM_GPR_SHARED6_SET_m7_mask_gpt1_SHIFT   (1U)
19210 /*! m7_mask_gpt1 - m7_mask_gpt1 */
19211 #define CCM_GPR_SHARED6_SET_m7_mask_gpt1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_gpt1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_gpt1_MASK)
19212 
19213 #define CCM_GPR_SHARED6_SET_m7_mask_gpt2_MASK    (0x4U)
19214 #define CCM_GPR_SHARED6_SET_m7_mask_gpt2_SHIFT   (2U)
19215 /*! m7_mask_gpt2 - m7_mask_gpt2 */
19216 #define CCM_GPR_SHARED6_SET_m7_mask_gpt2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_gpt2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_gpt2_MASK)
19217 
19218 #define CCM_GPR_SHARED6_SET_m7_mask_can1_MASK    (0x8U)
19219 #define CCM_GPR_SHARED6_SET_m7_mask_can1_SHIFT   (3U)
19220 /*! m7_mask_can1 - m7_mask_can1 */
19221 #define CCM_GPR_SHARED6_SET_m7_mask_can1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_can1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_can1_MASK)
19222 
19223 #define CCM_GPR_SHARED6_SET_m7_mask_can2_MASK    (0x10U)
19224 #define CCM_GPR_SHARED6_SET_m7_mask_can2_SHIFT   (4U)
19225 /*! m7_mask_can2 - m7_mask_can2 */
19226 #define CCM_GPR_SHARED6_SET_m7_mask_can2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_can2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_can2_MASK)
19227 
19228 #define CCM_GPR_SHARED6_SET_m7_mask_can3_MASK    (0x20U)
19229 #define CCM_GPR_SHARED6_SET_m7_mask_can3_SHIFT   (5U)
19230 /*! m7_mask_can3 - m7_mask_can3 */
19231 #define CCM_GPR_SHARED6_SET_m7_mask_can3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_can3_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_can3_MASK)
19232 
19233 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart1_MASK (0x40U)
19234 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart1_SHIFT (6U)
19235 /*! m7_mask_lpuart1 - m7_mask_lpuart1 */
19236 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart1_MASK)
19237 
19238 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart2_MASK (0x80U)
19239 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart2_SHIFT (7U)
19240 /*! m7_mask_lpuart2 - m7_mask_lpuart2 */
19241 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart2_MASK)
19242 
19243 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart3_MASK (0x100U)
19244 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart3_SHIFT (8U)
19245 /*! m7_mask_lpuart3 - m7_mask_lpuart3 */
19246 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart3_MASK)
19247 
19248 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart4_MASK (0x200U)
19249 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart4_SHIFT (9U)
19250 /*! m7_mask_lpuart4 - m7_mask_lpuart4 */
19251 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart4_MASK)
19252 
19253 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart5_MASK (0x400U)
19254 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart5_SHIFT (10U)
19255 /*! m7_mask_lpuart5 - m7_mask_lpuart5 */
19256 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart5_MASK)
19257 
19258 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart6_MASK (0x800U)
19259 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart6_SHIFT (11U)
19260 /*! m7_mask_lpuart6 - m7_mask_lpuart6 */
19261 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart6_MASK)
19262 
19263 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart7_MASK (0x1000U)
19264 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart7_SHIFT (12U)
19265 /*! m7_mask_lpuart7 - m7_mask_lpuart7 */
19266 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart7_MASK)
19267 
19268 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart8_MASK (0x2000U)
19269 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart8_SHIFT (13U)
19270 /*! m7_mask_lpuart8 - m7_mask_lpuart8 */
19271 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart8_MASK)
19272 
19273 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart9_MASK (0x4000U)
19274 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart9_SHIFT (14U)
19275 /*! m7_mask_lpuart9 - m7_mask_lpuart9 */
19276 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart9_MASK)
19277 
19278 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart10_MASK (0x8000U)
19279 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart10_SHIFT (15U)
19280 /*! m7_mask_lpuart10 - m7_mask_lpuart10 */
19281 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart10(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart10_MASK)
19282 
19283 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart11_MASK (0x10000U)
19284 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart11_SHIFT (16U)
19285 /*! m7_mask_lpuart11 - m7_mask_lpuart11 */
19286 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart11(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart11_MASK)
19287 
19288 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart12_MASK (0x20000U)
19289 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart12_SHIFT (17U)
19290 /*! m7_mask_lpuart12 - m7_mask_lpuart12 */
19291 #define CCM_GPR_SHARED6_SET_m7_mask_lpuart12(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpuart12_MASK)
19292 
19293 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c1_MASK  (0x40000U)
19294 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c1_SHIFT (18U)
19295 /*! m7_mask_lpi2c1 - m7_mask_lpi2c1 */
19296 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c1_MASK)
19297 
19298 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c2_MASK  (0x80000U)
19299 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c2_SHIFT (19U)
19300 /*! m7_mask_lpi2c2 - m7_mask_lpi2c2 */
19301 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c2_MASK)
19302 
19303 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c3_MASK  (0x100000U)
19304 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c3_SHIFT (20U)
19305 /*! m7_mask_lpi2c3 - m7_mask_lpi2c3 */
19306 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c3_MASK)
19307 
19308 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c4_MASK  (0x200000U)
19309 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c4_SHIFT (21U)
19310 /*! m7_mask_lpi2c4 - m7_mask_lpi2c4 */
19311 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c4_MASK)
19312 
19313 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c5_MASK  (0x400000U)
19314 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c5_SHIFT (22U)
19315 /*! m7_mask_lpi2c5 - m7_mask_lpi2c5 */
19316 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c5_MASK)
19317 
19318 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c6_MASK  (0x800000U)
19319 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c6_SHIFT (23U)
19320 /*! m7_mask_lpi2c6 - m7_mask_lpi2c6 */
19321 #define CCM_GPR_SHARED6_SET_m7_mask_lpi2c6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpi2c6_MASK)
19322 
19323 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi1_MASK  (0x1000000U)
19324 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi1_SHIFT (24U)
19325 /*! m7_mask_lpspi1 - m7_mask_lpspi1 */
19326 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi1_MASK)
19327 
19328 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi2_MASK  (0x2000000U)
19329 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi2_SHIFT (25U)
19330 /*! m7_mask_lpspi2 - m7_mask_lpspi2 */
19331 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi2_MASK)
19332 
19333 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi3_MASK  (0x4000000U)
19334 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi3_SHIFT (26U)
19335 /*! m7_mask_lpspi3 - m7_mask_lpspi3 */
19336 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi3_MASK)
19337 
19338 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi4_MASK  (0x8000000U)
19339 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi4_SHIFT (27U)
19340 /*! m7_mask_lpspi4 - m7_mask_lpspi4 */
19341 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi4_MASK)
19342 
19343 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi5_MASK  (0x10000000U)
19344 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi5_SHIFT (28U)
19345 /*! m7_mask_lpspi5 - m7_mask_lpspi5 */
19346 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi5_MASK)
19347 
19348 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi6_MASK  (0x20000000U)
19349 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi6_SHIFT (29U)
19350 /*! m7_mask_lpspi6 - m7_mask_lpspi6 */
19351 #define CCM_GPR_SHARED6_SET_m7_mask_lpspi6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_lpspi6_MASK)
19352 
19353 #define CCM_GPR_SHARED6_SET_m7_mask_sinc1_MASK   (0x40000000U)
19354 #define CCM_GPR_SHARED6_SET_m7_mask_sinc1_SHIFT  (30U)
19355 /*! m7_mask_sinc1 - m7_mask_sinc1 */
19356 #define CCM_GPR_SHARED6_SET_m7_mask_sinc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_sinc1_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_sinc1_MASK)
19357 
19358 #define CCM_GPR_SHARED6_SET_m7_mask_sinc2_MASK   (0x80000000U)
19359 #define CCM_GPR_SHARED6_SET_m7_mask_sinc2_SHIFT  (31U)
19360 /*! m7_mask_sinc2 - m7_mask_sinc2 */
19361 #define CCM_GPR_SHARED6_SET_m7_mask_sinc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_SET_m7_mask_sinc2_SHIFT)) & CCM_GPR_SHARED6_SET_m7_mask_sinc2_MASK)
19362 /*! @} */
19363 
19364 /*! @name GPR_SHARED6_CLR - General Purpose Register */
19365 /*! @{ */
19366 
19367 #define CCM_GPR_SHARED6_CLR_m7_mask_tpm6_MASK    (0x1U)
19368 #define CCM_GPR_SHARED6_CLR_m7_mask_tpm6_SHIFT   (0U)
19369 /*! m7_mask_tpm6 - m7_mask_tpm6 */
19370 #define CCM_GPR_SHARED6_CLR_m7_mask_tpm6(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_tpm6_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_tpm6_MASK)
19371 
19372 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt1_MASK    (0x2U)
19373 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt1_SHIFT   (1U)
19374 /*! m7_mask_gpt1 - m7_mask_gpt1 */
19375 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_gpt1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_gpt1_MASK)
19376 
19377 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt2_MASK    (0x4U)
19378 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt2_SHIFT   (2U)
19379 /*! m7_mask_gpt2 - m7_mask_gpt2 */
19380 #define CCM_GPR_SHARED6_CLR_m7_mask_gpt2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_gpt2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_gpt2_MASK)
19381 
19382 #define CCM_GPR_SHARED6_CLR_m7_mask_can1_MASK    (0x8U)
19383 #define CCM_GPR_SHARED6_CLR_m7_mask_can1_SHIFT   (3U)
19384 /*! m7_mask_can1 - m7_mask_can1 */
19385 #define CCM_GPR_SHARED6_CLR_m7_mask_can1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_can1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_can1_MASK)
19386 
19387 #define CCM_GPR_SHARED6_CLR_m7_mask_can2_MASK    (0x10U)
19388 #define CCM_GPR_SHARED6_CLR_m7_mask_can2_SHIFT   (4U)
19389 /*! m7_mask_can2 - m7_mask_can2 */
19390 #define CCM_GPR_SHARED6_CLR_m7_mask_can2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_can2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_can2_MASK)
19391 
19392 #define CCM_GPR_SHARED6_CLR_m7_mask_can3_MASK    (0x20U)
19393 #define CCM_GPR_SHARED6_CLR_m7_mask_can3_SHIFT   (5U)
19394 /*! m7_mask_can3 - m7_mask_can3 */
19395 #define CCM_GPR_SHARED6_CLR_m7_mask_can3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_can3_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_can3_MASK)
19396 
19397 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart1_MASK (0x40U)
19398 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart1_SHIFT (6U)
19399 /*! m7_mask_lpuart1 - m7_mask_lpuart1 */
19400 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart1_MASK)
19401 
19402 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart2_MASK (0x80U)
19403 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart2_SHIFT (7U)
19404 /*! m7_mask_lpuart2 - m7_mask_lpuart2 */
19405 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart2_MASK)
19406 
19407 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart3_MASK (0x100U)
19408 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart3_SHIFT (8U)
19409 /*! m7_mask_lpuart3 - m7_mask_lpuart3 */
19410 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart3_MASK)
19411 
19412 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart4_MASK (0x200U)
19413 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart4_SHIFT (9U)
19414 /*! m7_mask_lpuart4 - m7_mask_lpuart4 */
19415 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart4_MASK)
19416 
19417 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart5_MASK (0x400U)
19418 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart5_SHIFT (10U)
19419 /*! m7_mask_lpuart5 - m7_mask_lpuart5 */
19420 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart5_MASK)
19421 
19422 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart6_MASK (0x800U)
19423 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart6_SHIFT (11U)
19424 /*! m7_mask_lpuart6 - m7_mask_lpuart6 */
19425 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart6_MASK)
19426 
19427 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart7_MASK (0x1000U)
19428 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart7_SHIFT (12U)
19429 /*! m7_mask_lpuart7 - m7_mask_lpuart7 */
19430 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart7_MASK)
19431 
19432 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart8_MASK (0x2000U)
19433 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart8_SHIFT (13U)
19434 /*! m7_mask_lpuart8 - m7_mask_lpuart8 */
19435 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart8_MASK)
19436 
19437 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart9_MASK (0x4000U)
19438 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart9_SHIFT (14U)
19439 /*! m7_mask_lpuart9 - m7_mask_lpuart9 */
19440 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart9_MASK)
19441 
19442 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart10_MASK (0x8000U)
19443 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart10_SHIFT (15U)
19444 /*! m7_mask_lpuart10 - m7_mask_lpuart10 */
19445 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart10(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart10_MASK)
19446 
19447 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart11_MASK (0x10000U)
19448 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart11_SHIFT (16U)
19449 /*! m7_mask_lpuart11 - m7_mask_lpuart11 */
19450 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart11(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart11_MASK)
19451 
19452 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart12_MASK (0x20000U)
19453 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart12_SHIFT (17U)
19454 /*! m7_mask_lpuart12 - m7_mask_lpuart12 */
19455 #define CCM_GPR_SHARED6_CLR_m7_mask_lpuart12(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpuart12_MASK)
19456 
19457 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c1_MASK  (0x40000U)
19458 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c1_SHIFT (18U)
19459 /*! m7_mask_lpi2c1 - m7_mask_lpi2c1 */
19460 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c1_MASK)
19461 
19462 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c2_MASK  (0x80000U)
19463 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c2_SHIFT (19U)
19464 /*! m7_mask_lpi2c2 - m7_mask_lpi2c2 */
19465 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c2_MASK)
19466 
19467 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c3_MASK  (0x100000U)
19468 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c3_SHIFT (20U)
19469 /*! m7_mask_lpi2c3 - m7_mask_lpi2c3 */
19470 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c3_MASK)
19471 
19472 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c4_MASK  (0x200000U)
19473 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c4_SHIFT (21U)
19474 /*! m7_mask_lpi2c4 - m7_mask_lpi2c4 */
19475 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c4_MASK)
19476 
19477 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c5_MASK  (0x400000U)
19478 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c5_SHIFT (22U)
19479 /*! m7_mask_lpi2c5 - m7_mask_lpi2c5 */
19480 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c5_MASK)
19481 
19482 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c6_MASK  (0x800000U)
19483 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c6_SHIFT (23U)
19484 /*! m7_mask_lpi2c6 - m7_mask_lpi2c6 */
19485 #define CCM_GPR_SHARED6_CLR_m7_mask_lpi2c6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpi2c6_MASK)
19486 
19487 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi1_MASK  (0x1000000U)
19488 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi1_SHIFT (24U)
19489 /*! m7_mask_lpspi1 - m7_mask_lpspi1 */
19490 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi1_MASK)
19491 
19492 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi2_MASK  (0x2000000U)
19493 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi2_SHIFT (25U)
19494 /*! m7_mask_lpspi2 - m7_mask_lpspi2 */
19495 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi2_MASK)
19496 
19497 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi3_MASK  (0x4000000U)
19498 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi3_SHIFT (26U)
19499 /*! m7_mask_lpspi3 - m7_mask_lpspi3 */
19500 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi3_MASK)
19501 
19502 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi4_MASK  (0x8000000U)
19503 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi4_SHIFT (27U)
19504 /*! m7_mask_lpspi4 - m7_mask_lpspi4 */
19505 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi4_MASK)
19506 
19507 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi5_MASK  (0x10000000U)
19508 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi5_SHIFT (28U)
19509 /*! m7_mask_lpspi5 - m7_mask_lpspi5 */
19510 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi5_MASK)
19511 
19512 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi6_MASK  (0x20000000U)
19513 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi6_SHIFT (29U)
19514 /*! m7_mask_lpspi6 - m7_mask_lpspi6 */
19515 #define CCM_GPR_SHARED6_CLR_m7_mask_lpspi6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_lpspi6_MASK)
19516 
19517 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc1_MASK   (0x40000000U)
19518 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc1_SHIFT  (30U)
19519 /*! m7_mask_sinc1 - m7_mask_sinc1 */
19520 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_sinc1_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_sinc1_MASK)
19521 
19522 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc2_MASK   (0x80000000U)
19523 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc2_SHIFT  (31U)
19524 /*! m7_mask_sinc2 - m7_mask_sinc2 */
19525 #define CCM_GPR_SHARED6_CLR_m7_mask_sinc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_CLR_m7_mask_sinc2_SHIFT)) & CCM_GPR_SHARED6_CLR_m7_mask_sinc2_MASK)
19526 /*! @} */
19527 
19528 /*! @name GPR_SHARED6_TOG - General Purpose Register */
19529 /*! @{ */
19530 
19531 #define CCM_GPR_SHARED6_TOG_m7_mask_tpm6_MASK    (0x1U)
19532 #define CCM_GPR_SHARED6_TOG_m7_mask_tpm6_SHIFT   (0U)
19533 /*! m7_mask_tpm6 - m7_mask_tpm6 */
19534 #define CCM_GPR_SHARED6_TOG_m7_mask_tpm6(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_tpm6_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_tpm6_MASK)
19535 
19536 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt1_MASK    (0x2U)
19537 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt1_SHIFT   (1U)
19538 /*! m7_mask_gpt1 - m7_mask_gpt1 */
19539 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_gpt1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_gpt1_MASK)
19540 
19541 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt2_MASK    (0x4U)
19542 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt2_SHIFT   (2U)
19543 /*! m7_mask_gpt2 - m7_mask_gpt2 */
19544 #define CCM_GPR_SHARED6_TOG_m7_mask_gpt2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_gpt2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_gpt2_MASK)
19545 
19546 #define CCM_GPR_SHARED6_TOG_m7_mask_can1_MASK    (0x8U)
19547 #define CCM_GPR_SHARED6_TOG_m7_mask_can1_SHIFT   (3U)
19548 /*! m7_mask_can1 - m7_mask_can1 */
19549 #define CCM_GPR_SHARED6_TOG_m7_mask_can1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_can1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_can1_MASK)
19550 
19551 #define CCM_GPR_SHARED6_TOG_m7_mask_can2_MASK    (0x10U)
19552 #define CCM_GPR_SHARED6_TOG_m7_mask_can2_SHIFT   (4U)
19553 /*! m7_mask_can2 - m7_mask_can2 */
19554 #define CCM_GPR_SHARED6_TOG_m7_mask_can2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_can2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_can2_MASK)
19555 
19556 #define CCM_GPR_SHARED6_TOG_m7_mask_can3_MASK    (0x20U)
19557 #define CCM_GPR_SHARED6_TOG_m7_mask_can3_SHIFT   (5U)
19558 /*! m7_mask_can3 - m7_mask_can3 */
19559 #define CCM_GPR_SHARED6_TOG_m7_mask_can3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_can3_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_can3_MASK)
19560 
19561 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart1_MASK (0x40U)
19562 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart1_SHIFT (6U)
19563 /*! m7_mask_lpuart1 - m7_mask_lpuart1 */
19564 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart1(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart1_MASK)
19565 
19566 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart2_MASK (0x80U)
19567 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart2_SHIFT (7U)
19568 /*! m7_mask_lpuart2 - m7_mask_lpuart2 */
19569 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart2(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart2_MASK)
19570 
19571 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart3_MASK (0x100U)
19572 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart3_SHIFT (8U)
19573 /*! m7_mask_lpuart3 - m7_mask_lpuart3 */
19574 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart3(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart3_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart3_MASK)
19575 
19576 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart4_MASK (0x200U)
19577 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart4_SHIFT (9U)
19578 /*! m7_mask_lpuart4 - m7_mask_lpuart4 */
19579 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart4(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart4_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart4_MASK)
19580 
19581 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart5_MASK (0x400U)
19582 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart5_SHIFT (10U)
19583 /*! m7_mask_lpuart5 - m7_mask_lpuart5 */
19584 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart5(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart5_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart5_MASK)
19585 
19586 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart6_MASK (0x800U)
19587 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart6_SHIFT (11U)
19588 /*! m7_mask_lpuart6 - m7_mask_lpuart6 */
19589 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart6(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart6_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart6_MASK)
19590 
19591 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart7_MASK (0x1000U)
19592 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart7_SHIFT (12U)
19593 /*! m7_mask_lpuart7 - m7_mask_lpuart7 */
19594 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart7(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart7_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart7_MASK)
19595 
19596 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart8_MASK (0x2000U)
19597 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart8_SHIFT (13U)
19598 /*! m7_mask_lpuart8 - m7_mask_lpuart8 */
19599 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart8(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart8_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart8_MASK)
19600 
19601 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart9_MASK (0x4000U)
19602 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart9_SHIFT (14U)
19603 /*! m7_mask_lpuart9 - m7_mask_lpuart9 */
19604 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart9(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart9_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart9_MASK)
19605 
19606 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart10_MASK (0x8000U)
19607 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart10_SHIFT (15U)
19608 /*! m7_mask_lpuart10 - m7_mask_lpuart10 */
19609 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart10(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart10_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart10_MASK)
19610 
19611 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart11_MASK (0x10000U)
19612 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart11_SHIFT (16U)
19613 /*! m7_mask_lpuart11 - m7_mask_lpuart11 */
19614 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart11(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart11_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart11_MASK)
19615 
19616 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart12_MASK (0x20000U)
19617 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart12_SHIFT (17U)
19618 /*! m7_mask_lpuart12 - m7_mask_lpuart12 */
19619 #define CCM_GPR_SHARED6_TOG_m7_mask_lpuart12(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpuart12_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpuart12_MASK)
19620 
19621 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c1_MASK  (0x40000U)
19622 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c1_SHIFT (18U)
19623 /*! m7_mask_lpi2c1 - m7_mask_lpi2c1 */
19624 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c1_MASK)
19625 
19626 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c2_MASK  (0x80000U)
19627 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c2_SHIFT (19U)
19628 /*! m7_mask_lpi2c2 - m7_mask_lpi2c2 */
19629 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c2_MASK)
19630 
19631 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c3_MASK  (0x100000U)
19632 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c3_SHIFT (20U)
19633 /*! m7_mask_lpi2c3 - m7_mask_lpi2c3 */
19634 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c3_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c3_MASK)
19635 
19636 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c4_MASK  (0x200000U)
19637 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c4_SHIFT (21U)
19638 /*! m7_mask_lpi2c4 - m7_mask_lpi2c4 */
19639 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c4_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c4_MASK)
19640 
19641 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c5_MASK  (0x400000U)
19642 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c5_SHIFT (22U)
19643 /*! m7_mask_lpi2c5 - m7_mask_lpi2c5 */
19644 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c5_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c5_MASK)
19645 
19646 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c6_MASK  (0x800000U)
19647 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c6_SHIFT (23U)
19648 /*! m7_mask_lpi2c6 - m7_mask_lpi2c6 */
19649 #define CCM_GPR_SHARED6_TOG_m7_mask_lpi2c6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpi2c6_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpi2c6_MASK)
19650 
19651 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi1_MASK  (0x1000000U)
19652 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi1_SHIFT (24U)
19653 /*! m7_mask_lpspi1 - m7_mask_lpspi1 */
19654 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi1(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi1_MASK)
19655 
19656 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi2_MASK  (0x2000000U)
19657 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi2_SHIFT (25U)
19658 /*! m7_mask_lpspi2 - m7_mask_lpspi2 */
19659 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi2(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi2_MASK)
19660 
19661 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi3_MASK  (0x4000000U)
19662 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi3_SHIFT (26U)
19663 /*! m7_mask_lpspi3 - m7_mask_lpspi3 */
19664 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi3(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi3_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi3_MASK)
19665 
19666 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi4_MASK  (0x8000000U)
19667 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi4_SHIFT (27U)
19668 /*! m7_mask_lpspi4 - m7_mask_lpspi4 */
19669 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi4(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi4_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi4_MASK)
19670 
19671 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi5_MASK  (0x10000000U)
19672 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi5_SHIFT (28U)
19673 /*! m7_mask_lpspi5 - m7_mask_lpspi5 */
19674 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi5(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi5_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi5_MASK)
19675 
19676 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi6_MASK  (0x20000000U)
19677 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi6_SHIFT (29U)
19678 /*! m7_mask_lpspi6 - m7_mask_lpspi6 */
19679 #define CCM_GPR_SHARED6_TOG_m7_mask_lpspi6(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_lpspi6_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_lpspi6_MASK)
19680 
19681 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc1_MASK   (0x40000000U)
19682 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc1_SHIFT  (30U)
19683 /*! m7_mask_sinc1 - m7_mask_sinc1 */
19684 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc1(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_sinc1_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_sinc1_MASK)
19685 
19686 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc2_MASK   (0x80000000U)
19687 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc2_SHIFT  (31U)
19688 /*! m7_mask_sinc2 - m7_mask_sinc2 */
19689 #define CCM_GPR_SHARED6_TOG_m7_mask_sinc2(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_TOG_m7_mask_sinc2_SHIFT)) & CCM_GPR_SHARED6_TOG_m7_mask_sinc2_MASK)
19690 /*! @} */
19691 
19692 /*! @name GPR_SHARED6_AUTHEN - GPR access control */
19693 /*! @{ */
19694 
19695 #define CCM_GPR_SHARED6_AUTHEN_TZ_USER_MASK      (0x100U)
19696 #define CCM_GPR_SHARED6_AUTHEN_TZ_USER_SHIFT     (8U)
19697 /*! TZ_USER - User access permission
19698  *  0b1..Registers of shared GPR slice can be changed in user mode.
19699  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
19700  */
19701 #define CCM_GPR_SHARED6_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TZ_USER_MASK)
19702 
19703 #define CCM_GPR_SHARED6_AUTHEN_TZ_NS_MASK        (0x200U)
19704 #define CCM_GPR_SHARED6_AUTHEN_TZ_NS_SHIFT       (9U)
19705 /*! TZ_NS - Non-secure access permission
19706  *  0b0..Cannot be changed in Non-secure mode.
19707  *  0b1..Can be changed in Non-secure mode.
19708  */
19709 #define CCM_GPR_SHARED6_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TZ_NS_MASK)
19710 
19711 #define CCM_GPR_SHARED6_AUTHEN_LOCK_TZ_MASK      (0x800U)
19712 #define CCM_GPR_SHARED6_AUTHEN_LOCK_TZ_SHIFT     (11U)
19713 /*! LOCK_TZ - Lock TrustZone settings
19714  *  0b0..TrustZone settings is not locked.
19715  *  0b1..TrustZone settings is locked.
19716  */
19717 #define CCM_GPR_SHARED6_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_LOCK_TZ_MASK)
19718 
19719 #define CCM_GPR_SHARED6_AUTHEN_LOCK_LIST_MASK    (0x8000U)
19720 #define CCM_GPR_SHARED6_AUTHEN_LOCK_LIST_SHIFT   (15U)
19721 /*! LOCK_LIST - Lock white list
19722  *  0b0..Whitelist is not locked.
19723  *  0b1..Whitelist is locked.
19724  */
19725 #define CCM_GPR_SHARED6_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_LOCK_LIST_MASK)
19726 
19727 #define CCM_GPR_SHARED6_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
19728 #define CCM_GPR_SHARED6_AUTHEN_WHITE_LIST_SHIFT  (16U)
19729 /*! WHITE_LIST - Whitelist settings */
19730 #define CCM_GPR_SHARED6_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_WHITE_LIST_MASK)
19731 /*! @} */
19732 
19733 /*! @name GPR_SHARED6_AUTHEN_SET - GPR access control */
19734 /*! @{ */
19735 
19736 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_USER_MASK  (0x100U)
19737 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_USER_SHIFT (8U)
19738 /*! TZ_USER - User access permission */
19739 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_SET_TZ_USER_MASK)
19740 
19741 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_NS_MASK    (0x200U)
19742 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_NS_SHIFT   (9U)
19743 /*! TZ_NS - Non-secure access permission */
19744 #define CCM_GPR_SHARED6_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_SET_TZ_NS_MASK)
19745 
19746 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
19747 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
19748 /*! LOCK_TZ - Lock TrustZone settings */
19749 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_SET_LOCK_TZ_MASK)
19750 
19751 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
19752 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
19753 /*! LOCK_LIST - Lock white list */
19754 #define CCM_GPR_SHARED6_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_SET_LOCK_LIST_MASK)
19755 
19756 #define CCM_GPR_SHARED6_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
19757 #define CCM_GPR_SHARED6_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
19758 /*! WHITE_LIST - Whitelist settings */
19759 #define CCM_GPR_SHARED6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_SET_WHITE_LIST_MASK)
19760 /*! @} */
19761 
19762 /*! @name GPR_SHARED6_AUTHEN_CLR - GPR access control */
19763 /*! @{ */
19764 
19765 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
19766 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_USER_SHIFT (8U)
19767 /*! TZ_USER - User access permission */
19768 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_CLR_TZ_USER_MASK)
19769 
19770 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
19771 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
19772 /*! TZ_NS - Non-secure access permission */
19773 #define CCM_GPR_SHARED6_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_CLR_TZ_NS_MASK)
19774 
19775 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
19776 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
19777 /*! LOCK_TZ - Lock TrustZone settings */
19778 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_TZ_MASK)
19779 
19780 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
19781 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
19782 /*! LOCK_LIST - Lock white list */
19783 #define CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_CLR_LOCK_LIST_MASK)
19784 
19785 #define CCM_GPR_SHARED6_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
19786 #define CCM_GPR_SHARED6_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
19787 /*! WHITE_LIST - Whitelist settings */
19788 #define CCM_GPR_SHARED6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_CLR_WHITE_LIST_MASK)
19789 /*! @} */
19790 
19791 /*! @name GPR_SHARED6_AUTHEN_TOG - GPR access control */
19792 /*! @{ */
19793 
19794 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
19795 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_USER_SHIFT (8U)
19796 /*! TZ_USER - User access permission */
19797 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TOG_TZ_USER_MASK)
19798 
19799 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
19800 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
19801 /*! TZ_NS - Non-secure access permission */
19802 #define CCM_GPR_SHARED6_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TOG_TZ_NS_MASK)
19803 
19804 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
19805 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
19806 /*! LOCK_TZ - Lock TrustZone settings */
19807 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_TZ_MASK)
19808 
19809 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
19810 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
19811 /*! LOCK_LIST - Lock white list */
19812 #define CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TOG_LOCK_LIST_MASK)
19813 
19814 #define CCM_GPR_SHARED6_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
19815 #define CCM_GPR_SHARED6_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
19816 /*! WHITE_LIST - Whitelist settings */
19817 #define CCM_GPR_SHARED6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED6_AUTHEN_TOG_WHITE_LIST_MASK)
19818 /*! @} */
19819 
19820 /*! @name GPR_SHARED7 - General Purpose Register */
19821 /*! @{ */
19822 
19823 #define CCM_GPR_SHARED7_m7_mask_sinc3_MASK       (0x1U)
19824 #define CCM_GPR_SHARED7_m7_mask_sinc3_SHIFT      (0U)
19825 /*! m7_mask_sinc3 - m7_mask_sinc3 */
19826 #define CCM_GPR_SHARED7_m7_mask_sinc3(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_sinc3_SHIFT)) & CCM_GPR_SHARED7_m7_mask_sinc3_MASK)
19827 
19828 #define CCM_GPR_SHARED7_m7_mask_sai1_MASK        (0x2U)
19829 #define CCM_GPR_SHARED7_m7_mask_sai1_SHIFT       (1U)
19830 /*! m7_mask_sai1 - m7_mask_sai1 */
19831 #define CCM_GPR_SHARED7_m7_mask_sai1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_sai1_SHIFT)) & CCM_GPR_SHARED7_m7_mask_sai1_MASK)
19832 
19833 #define CCM_GPR_SHARED7_m7_mask_sai2_MASK        (0x4U)
19834 #define CCM_GPR_SHARED7_m7_mask_sai2_SHIFT       (2U)
19835 /*! m7_mask_sai2 - m7_mask_sai2 */
19836 #define CCM_GPR_SHARED7_m7_mask_sai2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_sai2_SHIFT)) & CCM_GPR_SHARED7_m7_mask_sai2_MASK)
19837 
19838 #define CCM_GPR_SHARED7_m7_mask_sai3_MASK        (0x8U)
19839 #define CCM_GPR_SHARED7_m7_mask_sai3_SHIFT       (3U)
19840 /*! m7_mask_sai3 - m7_mask_sai3 */
19841 #define CCM_GPR_SHARED7_m7_mask_sai3(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_sai3_SHIFT)) & CCM_GPR_SHARED7_m7_mask_sai3_MASK)
19842 
19843 #define CCM_GPR_SHARED7_m7_mask_sai4_MASK        (0x10U)
19844 #define CCM_GPR_SHARED7_m7_mask_sai4_SHIFT       (4U)
19845 /*! m7_mask_sai4 - m7_mask_sai4 */
19846 #define CCM_GPR_SHARED7_m7_mask_sai4(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_sai4_SHIFT)) & CCM_GPR_SHARED7_m7_mask_sai4_MASK)
19847 
19848 #define CCM_GPR_SHARED7_m7_mask_mic_MASK         (0x20U)
19849 #define CCM_GPR_SHARED7_m7_mask_mic_SHIFT        (5U)
19850 /*! m7_mask_mic - m7_mask_mic */
19851 #define CCM_GPR_SHARED7_m7_mask_mic(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_m7_mask_mic_SHIFT)) & CCM_GPR_SHARED7_m7_mask_mic_MASK)
19852 /*! @} */
19853 
19854 /*! @name GPR_SHARED7_SET - General Purpose Register */
19855 /*! @{ */
19856 
19857 #define CCM_GPR_SHARED7_SET_m7_mask_sinc3_MASK   (0x1U)
19858 #define CCM_GPR_SHARED7_SET_m7_mask_sinc3_SHIFT  (0U)
19859 /*! m7_mask_sinc3 - m7_mask_sinc3 */
19860 #define CCM_GPR_SHARED7_SET_m7_mask_sinc3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_sinc3_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_sinc3_MASK)
19861 
19862 #define CCM_GPR_SHARED7_SET_m7_mask_sai1_MASK    (0x2U)
19863 #define CCM_GPR_SHARED7_SET_m7_mask_sai1_SHIFT   (1U)
19864 /*! m7_mask_sai1 - m7_mask_sai1 */
19865 #define CCM_GPR_SHARED7_SET_m7_mask_sai1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_sai1_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_sai1_MASK)
19866 
19867 #define CCM_GPR_SHARED7_SET_m7_mask_sai2_MASK    (0x4U)
19868 #define CCM_GPR_SHARED7_SET_m7_mask_sai2_SHIFT   (2U)
19869 /*! m7_mask_sai2 - m7_mask_sai2 */
19870 #define CCM_GPR_SHARED7_SET_m7_mask_sai2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_sai2_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_sai2_MASK)
19871 
19872 #define CCM_GPR_SHARED7_SET_m7_mask_sai3_MASK    (0x8U)
19873 #define CCM_GPR_SHARED7_SET_m7_mask_sai3_SHIFT   (3U)
19874 /*! m7_mask_sai3 - m7_mask_sai3 */
19875 #define CCM_GPR_SHARED7_SET_m7_mask_sai3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_sai3_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_sai3_MASK)
19876 
19877 #define CCM_GPR_SHARED7_SET_m7_mask_sai4_MASK    (0x10U)
19878 #define CCM_GPR_SHARED7_SET_m7_mask_sai4_SHIFT   (4U)
19879 /*! m7_mask_sai4 - m7_mask_sai4 */
19880 #define CCM_GPR_SHARED7_SET_m7_mask_sai4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_sai4_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_sai4_MASK)
19881 
19882 #define CCM_GPR_SHARED7_SET_m7_mask_mic_MASK     (0x20U)
19883 #define CCM_GPR_SHARED7_SET_m7_mask_mic_SHIFT    (5U)
19884 /*! m7_mask_mic - m7_mask_mic */
19885 #define CCM_GPR_SHARED7_SET_m7_mask_mic(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_SET_m7_mask_mic_SHIFT)) & CCM_GPR_SHARED7_SET_m7_mask_mic_MASK)
19886 /*! @} */
19887 
19888 /*! @name GPR_SHARED7_CLR - General Purpose Register */
19889 /*! @{ */
19890 
19891 #define CCM_GPR_SHARED7_CLR_m7_mask_sinc3_MASK   (0x1U)
19892 #define CCM_GPR_SHARED7_CLR_m7_mask_sinc3_SHIFT  (0U)
19893 /*! m7_mask_sinc3 - m7_mask_sinc3 */
19894 #define CCM_GPR_SHARED7_CLR_m7_mask_sinc3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_sinc3_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_sinc3_MASK)
19895 
19896 #define CCM_GPR_SHARED7_CLR_m7_mask_sai1_MASK    (0x2U)
19897 #define CCM_GPR_SHARED7_CLR_m7_mask_sai1_SHIFT   (1U)
19898 /*! m7_mask_sai1 - m7_mask_sai1 */
19899 #define CCM_GPR_SHARED7_CLR_m7_mask_sai1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_sai1_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_sai1_MASK)
19900 
19901 #define CCM_GPR_SHARED7_CLR_m7_mask_sai2_MASK    (0x4U)
19902 #define CCM_GPR_SHARED7_CLR_m7_mask_sai2_SHIFT   (2U)
19903 /*! m7_mask_sai2 - m7_mask_sai2 */
19904 #define CCM_GPR_SHARED7_CLR_m7_mask_sai2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_sai2_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_sai2_MASK)
19905 
19906 #define CCM_GPR_SHARED7_CLR_m7_mask_sai3_MASK    (0x8U)
19907 #define CCM_GPR_SHARED7_CLR_m7_mask_sai3_SHIFT   (3U)
19908 /*! m7_mask_sai3 - m7_mask_sai3 */
19909 #define CCM_GPR_SHARED7_CLR_m7_mask_sai3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_sai3_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_sai3_MASK)
19910 
19911 #define CCM_GPR_SHARED7_CLR_m7_mask_sai4_MASK    (0x10U)
19912 #define CCM_GPR_SHARED7_CLR_m7_mask_sai4_SHIFT   (4U)
19913 /*! m7_mask_sai4 - m7_mask_sai4 */
19914 #define CCM_GPR_SHARED7_CLR_m7_mask_sai4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_sai4_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_sai4_MASK)
19915 
19916 #define CCM_GPR_SHARED7_CLR_m7_mask_mic_MASK     (0x20U)
19917 #define CCM_GPR_SHARED7_CLR_m7_mask_mic_SHIFT    (5U)
19918 /*! m7_mask_mic - m7_mask_mic */
19919 #define CCM_GPR_SHARED7_CLR_m7_mask_mic(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_CLR_m7_mask_mic_SHIFT)) & CCM_GPR_SHARED7_CLR_m7_mask_mic_MASK)
19920 /*! @} */
19921 
19922 /*! @name GPR_SHARED7_TOG - General Purpose Register */
19923 /*! @{ */
19924 
19925 #define CCM_GPR_SHARED7_TOG_m7_mask_sinc3_MASK   (0x1U)
19926 #define CCM_GPR_SHARED7_TOG_m7_mask_sinc3_SHIFT  (0U)
19927 /*! m7_mask_sinc3 - m7_mask_sinc3 */
19928 #define CCM_GPR_SHARED7_TOG_m7_mask_sinc3(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_sinc3_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_sinc3_MASK)
19929 
19930 #define CCM_GPR_SHARED7_TOG_m7_mask_sai1_MASK    (0x2U)
19931 #define CCM_GPR_SHARED7_TOG_m7_mask_sai1_SHIFT   (1U)
19932 /*! m7_mask_sai1 - m7_mask_sai1 */
19933 #define CCM_GPR_SHARED7_TOG_m7_mask_sai1(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_sai1_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_sai1_MASK)
19934 
19935 #define CCM_GPR_SHARED7_TOG_m7_mask_sai2_MASK    (0x4U)
19936 #define CCM_GPR_SHARED7_TOG_m7_mask_sai2_SHIFT   (2U)
19937 /*! m7_mask_sai2 - m7_mask_sai2 */
19938 #define CCM_GPR_SHARED7_TOG_m7_mask_sai2(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_sai2_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_sai2_MASK)
19939 
19940 #define CCM_GPR_SHARED7_TOG_m7_mask_sai3_MASK    (0x8U)
19941 #define CCM_GPR_SHARED7_TOG_m7_mask_sai3_SHIFT   (3U)
19942 /*! m7_mask_sai3 - m7_mask_sai3 */
19943 #define CCM_GPR_SHARED7_TOG_m7_mask_sai3(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_sai3_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_sai3_MASK)
19944 
19945 #define CCM_GPR_SHARED7_TOG_m7_mask_sai4_MASK    (0x10U)
19946 #define CCM_GPR_SHARED7_TOG_m7_mask_sai4_SHIFT   (4U)
19947 /*! m7_mask_sai4 - m7_mask_sai4 */
19948 #define CCM_GPR_SHARED7_TOG_m7_mask_sai4(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_sai4_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_sai4_MASK)
19949 
19950 #define CCM_GPR_SHARED7_TOG_m7_mask_mic_MASK     (0x20U)
19951 #define CCM_GPR_SHARED7_TOG_m7_mask_mic_SHIFT    (5U)
19952 /*! m7_mask_mic - m7_mask_mic */
19953 #define CCM_GPR_SHARED7_TOG_m7_mask_mic(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_TOG_m7_mask_mic_SHIFT)) & CCM_GPR_SHARED7_TOG_m7_mask_mic_MASK)
19954 /*! @} */
19955 
19956 /*! @name GPR_SHARED7_AUTHEN - GPR access control */
19957 /*! @{ */
19958 
19959 #define CCM_GPR_SHARED7_AUTHEN_TZ_USER_MASK      (0x100U)
19960 #define CCM_GPR_SHARED7_AUTHEN_TZ_USER_SHIFT     (8U)
19961 /*! TZ_USER - User access permission
19962  *  0b1..Registers of shared GPR slice can be changed in user mode.
19963  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
19964  */
19965 #define CCM_GPR_SHARED7_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TZ_USER_MASK)
19966 
19967 #define CCM_GPR_SHARED7_AUTHEN_TZ_NS_MASK        (0x200U)
19968 #define CCM_GPR_SHARED7_AUTHEN_TZ_NS_SHIFT       (9U)
19969 /*! TZ_NS - Non-secure access permission
19970  *  0b0..Cannot be changed in Non-secure mode.
19971  *  0b1..Can be changed in Non-secure mode.
19972  */
19973 #define CCM_GPR_SHARED7_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TZ_NS_MASK)
19974 
19975 #define CCM_GPR_SHARED7_AUTHEN_LOCK_TZ_MASK      (0x800U)
19976 #define CCM_GPR_SHARED7_AUTHEN_LOCK_TZ_SHIFT     (11U)
19977 /*! LOCK_TZ - Lock TrustZone settings
19978  *  0b0..TrustZone settings is not locked.
19979  *  0b1..TrustZone settings is locked.
19980  */
19981 #define CCM_GPR_SHARED7_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_LOCK_TZ_MASK)
19982 
19983 #define CCM_GPR_SHARED7_AUTHEN_LOCK_LIST_MASK    (0x8000U)
19984 #define CCM_GPR_SHARED7_AUTHEN_LOCK_LIST_SHIFT   (15U)
19985 /*! LOCK_LIST - Lock white list
19986  *  0b0..Whitelist is not locked.
19987  *  0b1..Whitelist is locked.
19988  */
19989 #define CCM_GPR_SHARED7_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_LOCK_LIST_MASK)
19990 
19991 #define CCM_GPR_SHARED7_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
19992 #define CCM_GPR_SHARED7_AUTHEN_WHITE_LIST_SHIFT  (16U)
19993 /*! WHITE_LIST - Whitelist settings */
19994 #define CCM_GPR_SHARED7_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_WHITE_LIST_MASK)
19995 /*! @} */
19996 
19997 /*! @name GPR_SHARED7_AUTHEN_SET - GPR access control */
19998 /*! @{ */
19999 
20000 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_USER_MASK  (0x100U)
20001 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_USER_SHIFT (8U)
20002 /*! TZ_USER - User access permission */
20003 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_SET_TZ_USER_MASK)
20004 
20005 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_NS_MASK    (0x200U)
20006 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_NS_SHIFT   (9U)
20007 /*! TZ_NS - Non-secure access permission */
20008 #define CCM_GPR_SHARED7_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_SET_TZ_NS_MASK)
20009 
20010 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
20011 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
20012 /*! LOCK_TZ - Lock TrustZone settings */
20013 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_SET_LOCK_TZ_MASK)
20014 
20015 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
20016 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
20017 /*! LOCK_LIST - Lock white list */
20018 #define CCM_GPR_SHARED7_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_SET_LOCK_LIST_MASK)
20019 
20020 #define CCM_GPR_SHARED7_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
20021 #define CCM_GPR_SHARED7_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
20022 /*! WHITE_LIST - Whitelist settings */
20023 #define CCM_GPR_SHARED7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_SET_WHITE_LIST_MASK)
20024 /*! @} */
20025 
20026 /*! @name GPR_SHARED7_AUTHEN_CLR - GPR access control */
20027 /*! @{ */
20028 
20029 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
20030 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_USER_SHIFT (8U)
20031 /*! TZ_USER - User access permission */
20032 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_CLR_TZ_USER_MASK)
20033 
20034 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
20035 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
20036 /*! TZ_NS - Non-secure access permission */
20037 #define CCM_GPR_SHARED7_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_CLR_TZ_NS_MASK)
20038 
20039 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
20040 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
20041 /*! LOCK_TZ - Lock TrustZone settings */
20042 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_TZ_MASK)
20043 
20044 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
20045 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
20046 /*! LOCK_LIST - Lock white list */
20047 #define CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_CLR_LOCK_LIST_MASK)
20048 
20049 #define CCM_GPR_SHARED7_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
20050 #define CCM_GPR_SHARED7_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
20051 /*! WHITE_LIST - Whitelist settings */
20052 #define CCM_GPR_SHARED7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_CLR_WHITE_LIST_MASK)
20053 /*! @} */
20054 
20055 /*! @name GPR_SHARED7_AUTHEN_TOG - GPR access control */
20056 /*! @{ */
20057 
20058 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
20059 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_USER_SHIFT (8U)
20060 /*! TZ_USER - User access permission */
20061 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TOG_TZ_USER_MASK)
20062 
20063 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
20064 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
20065 /*! TZ_NS - Non-secure access permission */
20066 #define CCM_GPR_SHARED7_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TOG_TZ_NS_MASK)
20067 
20068 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
20069 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
20070 /*! LOCK_TZ - Lock TrustZone settings */
20071 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_TZ_MASK)
20072 
20073 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
20074 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
20075 /*! LOCK_LIST - Lock white list */
20076 #define CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TOG_LOCK_LIST_MASK)
20077 
20078 #define CCM_GPR_SHARED7_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
20079 #define CCM_GPR_SHARED7_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
20080 /*! WHITE_LIST - Whitelist settings */
20081 #define CCM_GPR_SHARED7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED7_AUTHEN_TOG_WHITE_LIST_MASK)
20082 /*! @} */
20083 
20084 /*! @name GPR_SHARED8 - General Purpose Register */
20085 /*! @{ */
20086 
20087 #define CCM_GPR_SHARED8_m33_cm7_ipg_stop_MASK    (0x1U)
20088 #define CCM_GPR_SHARED8_m33_cm7_ipg_stop_SHIFT   (0U)
20089 /*! m33_cm7_ipg_stop - m33_cm7_ipg_stop */
20090 #define CCM_GPR_SHARED8_m33_cm7_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_cm7_ipg_stop_MASK)
20091 
20092 #define CCM_GPR_SHARED8_m33_cm33_ipg_stop_MASK   (0x2U)
20093 #define CCM_GPR_SHARED8_m33_cm33_ipg_stop_SHIFT  (1U)
20094 /*! m33_cm33_ipg_stop - m33_cm33_ipg_stop */
20095 #define CCM_GPR_SHARED8_m33_cm33_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_cm33_ipg_stop_MASK)
20096 
20097 #define CCM_GPR_SHARED8_m33_edma3_ipg_stop_MASK  (0x4U)
20098 #define CCM_GPR_SHARED8_m33_edma3_ipg_stop_SHIFT (2U)
20099 /*! m33_edma3_ipg_stop - m33_edma3_ipg_stop */
20100 #define CCM_GPR_SHARED8_m33_edma3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_edma3_ipg_stop_MASK)
20101 
20102 #define CCM_GPR_SHARED8_m33_edma4_ipg_stop_MASK  (0x8U)
20103 #define CCM_GPR_SHARED8_m33_edma4_ipg_stop_SHIFT (3U)
20104 /*! m33_edma4_ipg_stop - m33_edma4_ipg_stop */
20105 #define CCM_GPR_SHARED8_m33_edma4_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_edma4_ipg_stop_MASK)
20106 
20107 #define CCM_GPR_SHARED8_m33_netc_ipg_stop_MASK   (0x10U)
20108 #define CCM_GPR_SHARED8_m33_netc_ipg_stop_SHIFT  (4U)
20109 /*! m33_netc_ipg_stop - m33_netc_ipg_stop */
20110 #define CCM_GPR_SHARED8_m33_netc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_netc_ipg_stop_MASK)
20111 
20112 #define CCM_GPR_SHARED8_m33_sim_aon_ipg_stop_MASK (0x100U)
20113 #define CCM_GPR_SHARED8_m33_sim_aon_ipg_stop_SHIFT (8U)
20114 /*! m33_sim_aon_ipg_stop - m33_sim_aon_ipg_stop */
20115 #define CCM_GPR_SHARED8_m33_sim_aon_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_sim_aon_ipg_stop_MASK)
20116 
20117 #define CCM_GPR_SHARED8_m33_adc1_ipg_stop_MASK   (0x200U)
20118 #define CCM_GPR_SHARED8_m33_adc1_ipg_stop_SHIFT  (9U)
20119 /*! m33_adc1_ipg_stop - m33_adc1_ipg_stop */
20120 #define CCM_GPR_SHARED8_m33_adc1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_adc1_ipg_stop_MASK)
20121 
20122 #define CCM_GPR_SHARED8_m33_adc2_ipg_stop_MASK   (0x400U)
20123 #define CCM_GPR_SHARED8_m33_adc2_ipg_stop_SHIFT  (10U)
20124 /*! m33_adc2_ipg_stop - m33_adc2_ipg_stop */
20125 #define CCM_GPR_SHARED8_m33_adc2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_adc2_ipg_stop_MASK)
20126 
20127 #define CCM_GPR_SHARED8_m33_flexspi1_ipg_stop_MASK (0x800U)
20128 #define CCM_GPR_SHARED8_m33_flexspi1_ipg_stop_SHIFT (11U)
20129 /*! m33_flexspi1_ipg_stop - m33_flexspi1_ipg_stop */
20130 #define CCM_GPR_SHARED8_m33_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_flexspi1_ipg_stop_MASK)
20131 
20132 #define CCM_GPR_SHARED8_m33_flexspi2_ipg_stop_MASK (0x1000U)
20133 #define CCM_GPR_SHARED8_m33_flexspi2_ipg_stop_SHIFT (12U)
20134 /*! m33_flexspi2_ipg_stop - m33_flexspi2_ipg_stop */
20135 #define CCM_GPR_SHARED8_m33_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_flexspi2_ipg_stop_MASK)
20136 
20137 #define CCM_GPR_SHARED8_m33_trdc_ipg_stop_MASK   (0x2000U)
20138 #define CCM_GPR_SHARED8_m33_trdc_ipg_stop_SHIFT  (13U)
20139 /*! m33_trdc_ipg_stop - m33_trdc_ipg_stop */
20140 #define CCM_GPR_SHARED8_m33_trdc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_trdc_ipg_stop_MASK)
20141 
20142 #define CCM_GPR_SHARED8_m33_semc_ipg_stop_MASK   (0x4000U)
20143 #define CCM_GPR_SHARED8_m33_semc_ipg_stop_SHIFT  (14U)
20144 /*! m33_semc_ipg_stop - m33_semc_ipg_stop */
20145 #define CCM_GPR_SHARED8_m33_semc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_semc_ipg_stop_MASK)
20146 
20147 #define CCM_GPR_SHARED8_m33_iee_ipg_stop_MASK    (0x8000U)
20148 #define CCM_GPR_SHARED8_m33_iee_ipg_stop_SHIFT   (15U)
20149 /*! m33_iee_ipg_stop - m33_iee_ipg_stop */
20150 #define CCM_GPR_SHARED8_m33_iee_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_iee_ipg_stop_MASK)
20151 
20152 #define CCM_GPR_SHARED8_m33_gpio1_ipg_stop_MASK  (0x10000U)
20153 #define CCM_GPR_SHARED8_m33_gpio1_ipg_stop_SHIFT (16U)
20154 /*! m33_gpio1_ipg_stop - m33_gpio1_ipg_stop */
20155 #define CCM_GPR_SHARED8_m33_gpio1_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio1_ipg_stop_MASK)
20156 
20157 #define CCM_GPR_SHARED8_m33_gpio2_ipg_stop_MASK  (0x20000U)
20158 #define CCM_GPR_SHARED8_m33_gpio2_ipg_stop_SHIFT (17U)
20159 /*! m33_gpio2_ipg_stop - m33_gpio2_ipg_stop */
20160 #define CCM_GPR_SHARED8_m33_gpio2_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio2_ipg_stop_MASK)
20161 
20162 #define CCM_GPR_SHARED8_m33_gpio3_ipg_stop_MASK  (0x40000U)
20163 #define CCM_GPR_SHARED8_m33_gpio3_ipg_stop_SHIFT (18U)
20164 /*! m33_gpio3_ipg_stop - m33_gpio3_ipg_stop */
20165 #define CCM_GPR_SHARED8_m33_gpio3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio3_ipg_stop_MASK)
20166 
20167 #define CCM_GPR_SHARED8_m33_gpio4_ipg_stop_MASK  (0x80000U)
20168 #define CCM_GPR_SHARED8_m33_gpio4_ipg_stop_SHIFT (19U)
20169 /*! m33_gpio4_ipg_stop - m33_gpio4_ipg_stop */
20170 #define CCM_GPR_SHARED8_m33_gpio4_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio4_ipg_stop_MASK)
20171 
20172 #define CCM_GPR_SHARED8_m33_gpio5_ipg_stop_MASK  (0x100000U)
20173 #define CCM_GPR_SHARED8_m33_gpio5_ipg_stop_SHIFT (20U)
20174 /*! m33_gpio5_ipg_stop - m33_gpio5_ipg_stop */
20175 #define CCM_GPR_SHARED8_m33_gpio5_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio5_ipg_stop_MASK)
20176 
20177 #define CCM_GPR_SHARED8_m33_gpio6_ipg_stop_MASK  (0x200000U)
20178 #define CCM_GPR_SHARED8_m33_gpio6_ipg_stop_SHIFT (21U)
20179 /*! m33_gpio6_ipg_stop - m33_gpio6_ipg_stop */
20180 #define CCM_GPR_SHARED8_m33_gpio6_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_gpio6_ipg_stop_MASK)
20181 
20182 #define CCM_GPR_SHARED8_m33_flexio1_ipg_stop_MASK (0x400000U)
20183 #define CCM_GPR_SHARED8_m33_flexio1_ipg_stop_SHIFT (22U)
20184 /*! m33_flexio1_ipg_stop - m33_flexio1_ipg_stop */
20185 #define CCM_GPR_SHARED8_m33_flexio1_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_flexio1_ipg_stop_MASK)
20186 
20187 #define CCM_GPR_SHARED8_m33_flexio2_ipg_stop_MASK (0x800000U)
20188 #define CCM_GPR_SHARED8_m33_flexio2_ipg_stop_SHIFT (23U)
20189 /*! m33_flexio2_ipg_stop - m33_flexio2_ipg_stop */
20190 #define CCM_GPR_SHARED8_m33_flexio2_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_flexio2_ipg_stop_MASK)
20191 
20192 #define CCM_GPR_SHARED8_m33_can1_ipg_stop_MASK   (0x1000000U)
20193 #define CCM_GPR_SHARED8_m33_can1_ipg_stop_SHIFT  (24U)
20194 /*! m33_can1_ipg_stop - m33_can1_ipg_stop */
20195 #define CCM_GPR_SHARED8_m33_can1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_can1_ipg_stop_MASK)
20196 
20197 #define CCM_GPR_SHARED8_m33_can2_ipg_stop_MASK   (0x2000000U)
20198 #define CCM_GPR_SHARED8_m33_can2_ipg_stop_SHIFT  (25U)
20199 /*! m33_can2_ipg_stop - m33_can2_ipg_stop */
20200 #define CCM_GPR_SHARED8_m33_can2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_can2_ipg_stop_MASK)
20201 
20202 #define CCM_GPR_SHARED8_m33_can3_ipg_stop_MASK   (0x4000000U)
20203 #define CCM_GPR_SHARED8_m33_can3_ipg_stop_SHIFT  (26U)
20204 /*! m33_can3_ipg_stop - m33_can3_ipg_stop */
20205 #define CCM_GPR_SHARED8_m33_can3_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_can3_ipg_stop_MASK)
20206 
20207 #define CCM_GPR_SHARED8_m33_lpuart1_ipg_stop_MASK (0x8000000U)
20208 #define CCM_GPR_SHARED8_m33_lpuart1_ipg_stop_SHIFT (27U)
20209 /*! m33_lpuart1_ipg_stop - m33_lpuart1_ipg_stop */
20210 #define CCM_GPR_SHARED8_m33_lpuart1_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_lpuart1_ipg_stop_MASK)
20211 
20212 #define CCM_GPR_SHARED8_m33_lpuart2_ipg_stop_MASK (0x10000000U)
20213 #define CCM_GPR_SHARED8_m33_lpuart2_ipg_stop_SHIFT (28U)
20214 /*! m33_lpuart2_ipg_stop - m33_lpuart2_ipg_stop */
20215 #define CCM_GPR_SHARED8_m33_lpuart2_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_lpuart2_ipg_stop_MASK)
20216 
20217 #define CCM_GPR_SHARED8_m33_lpuart3_ipg_stop_MASK (0x20000000U)
20218 #define CCM_GPR_SHARED8_m33_lpuart3_ipg_stop_SHIFT (29U)
20219 /*! m33_lpuart3_ipg_stop - m33_lpuart3_ipg_stop */
20220 #define CCM_GPR_SHARED8_m33_lpuart3_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_lpuart3_ipg_stop_MASK)
20221 
20222 #define CCM_GPR_SHARED8_m33_lpuart4_ipg_stop_MASK (0x40000000U)
20223 #define CCM_GPR_SHARED8_m33_lpuart4_ipg_stop_SHIFT (30U)
20224 /*! m33_lpuart4_ipg_stop - m33_lpuart4_ipg_stop */
20225 #define CCM_GPR_SHARED8_m33_lpuart4_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_lpuart4_ipg_stop_MASK)
20226 
20227 #define CCM_GPR_SHARED8_m33_lpuart5_ipg_stop_MASK (0x80000000U)
20228 #define CCM_GPR_SHARED8_m33_lpuart5_ipg_stop_SHIFT (31U)
20229 /*! m33_lpuart5_ipg_stop - m33_lpuart5_ipg_stop */
20230 #define CCM_GPR_SHARED8_m33_lpuart5_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_m33_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_m33_lpuart5_ipg_stop_MASK)
20231 /*! @} */
20232 
20233 /*! @name GPR_SHARED8_SET - General Purpose Register */
20234 /*! @{ */
20235 
20236 #define CCM_GPR_SHARED8_SET_m33_cm7_ipg_stop_MASK (0x1U)
20237 #define CCM_GPR_SHARED8_SET_m33_cm7_ipg_stop_SHIFT (0U)
20238 /*! m33_cm7_ipg_stop - m33_cm7_ipg_stop */
20239 #define CCM_GPR_SHARED8_SET_m33_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_cm7_ipg_stop_MASK)
20240 
20241 #define CCM_GPR_SHARED8_SET_m33_cm33_ipg_stop_MASK (0x2U)
20242 #define CCM_GPR_SHARED8_SET_m33_cm33_ipg_stop_SHIFT (1U)
20243 /*! m33_cm33_ipg_stop - m33_cm33_ipg_stop */
20244 #define CCM_GPR_SHARED8_SET_m33_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_cm33_ipg_stop_MASK)
20245 
20246 #define CCM_GPR_SHARED8_SET_m33_edma3_ipg_stop_MASK (0x4U)
20247 #define CCM_GPR_SHARED8_SET_m33_edma3_ipg_stop_SHIFT (2U)
20248 /*! m33_edma3_ipg_stop - m33_edma3_ipg_stop */
20249 #define CCM_GPR_SHARED8_SET_m33_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_edma3_ipg_stop_MASK)
20250 
20251 #define CCM_GPR_SHARED8_SET_m33_edma4_ipg_stop_MASK (0x8U)
20252 #define CCM_GPR_SHARED8_SET_m33_edma4_ipg_stop_SHIFT (3U)
20253 /*! m33_edma4_ipg_stop - m33_edma4_ipg_stop */
20254 #define CCM_GPR_SHARED8_SET_m33_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_edma4_ipg_stop_MASK)
20255 
20256 #define CCM_GPR_SHARED8_SET_m33_netc_ipg_stop_MASK (0x10U)
20257 #define CCM_GPR_SHARED8_SET_m33_netc_ipg_stop_SHIFT (4U)
20258 /*! m33_netc_ipg_stop - m33_netc_ipg_stop */
20259 #define CCM_GPR_SHARED8_SET_m33_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_netc_ipg_stop_MASK)
20260 
20261 #define CCM_GPR_SHARED8_SET_m33_sim_aon_ipg_stop_MASK (0x100U)
20262 #define CCM_GPR_SHARED8_SET_m33_sim_aon_ipg_stop_SHIFT (8U)
20263 /*! m33_sim_aon_ipg_stop - m33_sim_aon_ipg_stop */
20264 #define CCM_GPR_SHARED8_SET_m33_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_sim_aon_ipg_stop_MASK)
20265 
20266 #define CCM_GPR_SHARED8_SET_m33_adc1_ipg_stop_MASK (0x200U)
20267 #define CCM_GPR_SHARED8_SET_m33_adc1_ipg_stop_SHIFT (9U)
20268 /*! m33_adc1_ipg_stop - m33_adc1_ipg_stop */
20269 #define CCM_GPR_SHARED8_SET_m33_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_adc1_ipg_stop_MASK)
20270 
20271 #define CCM_GPR_SHARED8_SET_m33_adc2_ipg_stop_MASK (0x400U)
20272 #define CCM_GPR_SHARED8_SET_m33_adc2_ipg_stop_SHIFT (10U)
20273 /*! m33_adc2_ipg_stop - m33_adc2_ipg_stop */
20274 #define CCM_GPR_SHARED8_SET_m33_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_adc2_ipg_stop_MASK)
20275 
20276 #define CCM_GPR_SHARED8_SET_m33_flexspi1_ipg_stop_MASK (0x800U)
20277 #define CCM_GPR_SHARED8_SET_m33_flexspi1_ipg_stop_SHIFT (11U)
20278 /*! m33_flexspi1_ipg_stop - m33_flexspi1_ipg_stop */
20279 #define CCM_GPR_SHARED8_SET_m33_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_flexspi1_ipg_stop_MASK)
20280 
20281 #define CCM_GPR_SHARED8_SET_m33_flexspi2_ipg_stop_MASK (0x1000U)
20282 #define CCM_GPR_SHARED8_SET_m33_flexspi2_ipg_stop_SHIFT (12U)
20283 /*! m33_flexspi2_ipg_stop - m33_flexspi2_ipg_stop */
20284 #define CCM_GPR_SHARED8_SET_m33_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_flexspi2_ipg_stop_MASK)
20285 
20286 #define CCM_GPR_SHARED8_SET_m33_trdc_ipg_stop_MASK (0x2000U)
20287 #define CCM_GPR_SHARED8_SET_m33_trdc_ipg_stop_SHIFT (13U)
20288 /*! m33_trdc_ipg_stop - m33_trdc_ipg_stop */
20289 #define CCM_GPR_SHARED8_SET_m33_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_trdc_ipg_stop_MASK)
20290 
20291 #define CCM_GPR_SHARED8_SET_m33_semc_ipg_stop_MASK (0x4000U)
20292 #define CCM_GPR_SHARED8_SET_m33_semc_ipg_stop_SHIFT (14U)
20293 /*! m33_semc_ipg_stop - m33_semc_ipg_stop */
20294 #define CCM_GPR_SHARED8_SET_m33_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_semc_ipg_stop_MASK)
20295 
20296 #define CCM_GPR_SHARED8_SET_m33_iee_ipg_stop_MASK (0x8000U)
20297 #define CCM_GPR_SHARED8_SET_m33_iee_ipg_stop_SHIFT (15U)
20298 /*! m33_iee_ipg_stop - m33_iee_ipg_stop */
20299 #define CCM_GPR_SHARED8_SET_m33_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_iee_ipg_stop_MASK)
20300 
20301 #define CCM_GPR_SHARED8_SET_m33_gpio1_ipg_stop_MASK (0x10000U)
20302 #define CCM_GPR_SHARED8_SET_m33_gpio1_ipg_stop_SHIFT (16U)
20303 /*! m33_gpio1_ipg_stop - m33_gpio1_ipg_stop */
20304 #define CCM_GPR_SHARED8_SET_m33_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio1_ipg_stop_MASK)
20305 
20306 #define CCM_GPR_SHARED8_SET_m33_gpio2_ipg_stop_MASK (0x20000U)
20307 #define CCM_GPR_SHARED8_SET_m33_gpio2_ipg_stop_SHIFT (17U)
20308 /*! m33_gpio2_ipg_stop - m33_gpio2_ipg_stop */
20309 #define CCM_GPR_SHARED8_SET_m33_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio2_ipg_stop_MASK)
20310 
20311 #define CCM_GPR_SHARED8_SET_m33_gpio3_ipg_stop_MASK (0x40000U)
20312 #define CCM_GPR_SHARED8_SET_m33_gpio3_ipg_stop_SHIFT (18U)
20313 /*! m33_gpio3_ipg_stop - m33_gpio3_ipg_stop */
20314 #define CCM_GPR_SHARED8_SET_m33_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio3_ipg_stop_MASK)
20315 
20316 #define CCM_GPR_SHARED8_SET_m33_gpio4_ipg_stop_MASK (0x80000U)
20317 #define CCM_GPR_SHARED8_SET_m33_gpio4_ipg_stop_SHIFT (19U)
20318 /*! m33_gpio4_ipg_stop - m33_gpio4_ipg_stop */
20319 #define CCM_GPR_SHARED8_SET_m33_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio4_ipg_stop_MASK)
20320 
20321 #define CCM_GPR_SHARED8_SET_m33_gpio5_ipg_stop_MASK (0x100000U)
20322 #define CCM_GPR_SHARED8_SET_m33_gpio5_ipg_stop_SHIFT (20U)
20323 /*! m33_gpio5_ipg_stop - m33_gpio5_ipg_stop */
20324 #define CCM_GPR_SHARED8_SET_m33_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio5_ipg_stop_MASK)
20325 
20326 #define CCM_GPR_SHARED8_SET_m33_gpio6_ipg_stop_MASK (0x200000U)
20327 #define CCM_GPR_SHARED8_SET_m33_gpio6_ipg_stop_SHIFT (21U)
20328 /*! m33_gpio6_ipg_stop - m33_gpio6_ipg_stop */
20329 #define CCM_GPR_SHARED8_SET_m33_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_gpio6_ipg_stop_MASK)
20330 
20331 #define CCM_GPR_SHARED8_SET_m33_flexio1_ipg_stop_MASK (0x400000U)
20332 #define CCM_GPR_SHARED8_SET_m33_flexio1_ipg_stop_SHIFT (22U)
20333 /*! m33_flexio1_ipg_stop - m33_flexio1_ipg_stop */
20334 #define CCM_GPR_SHARED8_SET_m33_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_flexio1_ipg_stop_MASK)
20335 
20336 #define CCM_GPR_SHARED8_SET_m33_flexio2_ipg_stop_MASK (0x800000U)
20337 #define CCM_GPR_SHARED8_SET_m33_flexio2_ipg_stop_SHIFT (23U)
20338 /*! m33_flexio2_ipg_stop - m33_flexio2_ipg_stop */
20339 #define CCM_GPR_SHARED8_SET_m33_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_flexio2_ipg_stop_MASK)
20340 
20341 #define CCM_GPR_SHARED8_SET_m33_can1_ipg_stop_MASK (0x1000000U)
20342 #define CCM_GPR_SHARED8_SET_m33_can1_ipg_stop_SHIFT (24U)
20343 /*! m33_can1_ipg_stop - m33_can1_ipg_stop */
20344 #define CCM_GPR_SHARED8_SET_m33_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_can1_ipg_stop_MASK)
20345 
20346 #define CCM_GPR_SHARED8_SET_m33_can2_ipg_stop_MASK (0x2000000U)
20347 #define CCM_GPR_SHARED8_SET_m33_can2_ipg_stop_SHIFT (25U)
20348 /*! m33_can2_ipg_stop - m33_can2_ipg_stop */
20349 #define CCM_GPR_SHARED8_SET_m33_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_can2_ipg_stop_MASK)
20350 
20351 #define CCM_GPR_SHARED8_SET_m33_can3_ipg_stop_MASK (0x4000000U)
20352 #define CCM_GPR_SHARED8_SET_m33_can3_ipg_stop_SHIFT (26U)
20353 /*! m33_can3_ipg_stop - m33_can3_ipg_stop */
20354 #define CCM_GPR_SHARED8_SET_m33_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_can3_ipg_stop_MASK)
20355 
20356 #define CCM_GPR_SHARED8_SET_m33_lpuart1_ipg_stop_MASK (0x8000000U)
20357 #define CCM_GPR_SHARED8_SET_m33_lpuart1_ipg_stop_SHIFT (27U)
20358 /*! m33_lpuart1_ipg_stop - m33_lpuart1_ipg_stop */
20359 #define CCM_GPR_SHARED8_SET_m33_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_lpuart1_ipg_stop_MASK)
20360 
20361 #define CCM_GPR_SHARED8_SET_m33_lpuart2_ipg_stop_MASK (0x10000000U)
20362 #define CCM_GPR_SHARED8_SET_m33_lpuart2_ipg_stop_SHIFT (28U)
20363 /*! m33_lpuart2_ipg_stop - m33_lpuart2_ipg_stop */
20364 #define CCM_GPR_SHARED8_SET_m33_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_lpuart2_ipg_stop_MASK)
20365 
20366 #define CCM_GPR_SHARED8_SET_m33_lpuart3_ipg_stop_MASK (0x20000000U)
20367 #define CCM_GPR_SHARED8_SET_m33_lpuart3_ipg_stop_SHIFT (29U)
20368 /*! m33_lpuart3_ipg_stop - m33_lpuart3_ipg_stop */
20369 #define CCM_GPR_SHARED8_SET_m33_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_lpuart3_ipg_stop_MASK)
20370 
20371 #define CCM_GPR_SHARED8_SET_m33_lpuart4_ipg_stop_MASK (0x40000000U)
20372 #define CCM_GPR_SHARED8_SET_m33_lpuart4_ipg_stop_SHIFT (30U)
20373 /*! m33_lpuart4_ipg_stop - m33_lpuart4_ipg_stop */
20374 #define CCM_GPR_SHARED8_SET_m33_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_lpuart4_ipg_stop_MASK)
20375 
20376 #define CCM_GPR_SHARED8_SET_m33_lpuart5_ipg_stop_MASK (0x80000000U)
20377 #define CCM_GPR_SHARED8_SET_m33_lpuart5_ipg_stop_SHIFT (31U)
20378 /*! m33_lpuart5_ipg_stop - m33_lpuart5_ipg_stop */
20379 #define CCM_GPR_SHARED8_SET_m33_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_SET_m33_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_SET_m33_lpuart5_ipg_stop_MASK)
20380 /*! @} */
20381 
20382 /*! @name GPR_SHARED8_CLR - General Purpose Register */
20383 /*! @{ */
20384 
20385 #define CCM_GPR_SHARED8_CLR_m33_cm7_ipg_stop_MASK (0x1U)
20386 #define CCM_GPR_SHARED8_CLR_m33_cm7_ipg_stop_SHIFT (0U)
20387 /*! m33_cm7_ipg_stop - m33_cm7_ipg_stop */
20388 #define CCM_GPR_SHARED8_CLR_m33_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_cm7_ipg_stop_MASK)
20389 
20390 #define CCM_GPR_SHARED8_CLR_m33_cm33_ipg_stop_MASK (0x2U)
20391 #define CCM_GPR_SHARED8_CLR_m33_cm33_ipg_stop_SHIFT (1U)
20392 /*! m33_cm33_ipg_stop - m33_cm33_ipg_stop */
20393 #define CCM_GPR_SHARED8_CLR_m33_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_cm33_ipg_stop_MASK)
20394 
20395 #define CCM_GPR_SHARED8_CLR_m33_edma3_ipg_stop_MASK (0x4U)
20396 #define CCM_GPR_SHARED8_CLR_m33_edma3_ipg_stop_SHIFT (2U)
20397 /*! m33_edma3_ipg_stop - m33_edma3_ipg_stop */
20398 #define CCM_GPR_SHARED8_CLR_m33_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_edma3_ipg_stop_MASK)
20399 
20400 #define CCM_GPR_SHARED8_CLR_m33_edma4_ipg_stop_MASK (0x8U)
20401 #define CCM_GPR_SHARED8_CLR_m33_edma4_ipg_stop_SHIFT (3U)
20402 /*! m33_edma4_ipg_stop - m33_edma4_ipg_stop */
20403 #define CCM_GPR_SHARED8_CLR_m33_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_edma4_ipg_stop_MASK)
20404 
20405 #define CCM_GPR_SHARED8_CLR_m33_netc_ipg_stop_MASK (0x10U)
20406 #define CCM_GPR_SHARED8_CLR_m33_netc_ipg_stop_SHIFT (4U)
20407 /*! m33_netc_ipg_stop - m33_netc_ipg_stop */
20408 #define CCM_GPR_SHARED8_CLR_m33_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_netc_ipg_stop_MASK)
20409 
20410 #define CCM_GPR_SHARED8_CLR_m33_sim_aon_ipg_stop_MASK (0x100U)
20411 #define CCM_GPR_SHARED8_CLR_m33_sim_aon_ipg_stop_SHIFT (8U)
20412 /*! m33_sim_aon_ipg_stop - m33_sim_aon_ipg_stop */
20413 #define CCM_GPR_SHARED8_CLR_m33_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_sim_aon_ipg_stop_MASK)
20414 
20415 #define CCM_GPR_SHARED8_CLR_m33_adc1_ipg_stop_MASK (0x200U)
20416 #define CCM_GPR_SHARED8_CLR_m33_adc1_ipg_stop_SHIFT (9U)
20417 /*! m33_adc1_ipg_stop - m33_adc1_ipg_stop */
20418 #define CCM_GPR_SHARED8_CLR_m33_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_adc1_ipg_stop_MASK)
20419 
20420 #define CCM_GPR_SHARED8_CLR_m33_adc2_ipg_stop_MASK (0x400U)
20421 #define CCM_GPR_SHARED8_CLR_m33_adc2_ipg_stop_SHIFT (10U)
20422 /*! m33_adc2_ipg_stop - m33_adc2_ipg_stop */
20423 #define CCM_GPR_SHARED8_CLR_m33_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_adc2_ipg_stop_MASK)
20424 
20425 #define CCM_GPR_SHARED8_CLR_m33_flexspi1_ipg_stop_MASK (0x800U)
20426 #define CCM_GPR_SHARED8_CLR_m33_flexspi1_ipg_stop_SHIFT (11U)
20427 /*! m33_flexspi1_ipg_stop - m33_flexspi1_ipg_stop */
20428 #define CCM_GPR_SHARED8_CLR_m33_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_flexspi1_ipg_stop_MASK)
20429 
20430 #define CCM_GPR_SHARED8_CLR_m33_flexspi2_ipg_stop_MASK (0x1000U)
20431 #define CCM_GPR_SHARED8_CLR_m33_flexspi2_ipg_stop_SHIFT (12U)
20432 /*! m33_flexspi2_ipg_stop - m33_flexspi2_ipg_stop */
20433 #define CCM_GPR_SHARED8_CLR_m33_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_flexspi2_ipg_stop_MASK)
20434 
20435 #define CCM_GPR_SHARED8_CLR_m33_trdc_ipg_stop_MASK (0x2000U)
20436 #define CCM_GPR_SHARED8_CLR_m33_trdc_ipg_stop_SHIFT (13U)
20437 /*! m33_trdc_ipg_stop - m33_trdc_ipg_stop */
20438 #define CCM_GPR_SHARED8_CLR_m33_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_trdc_ipg_stop_MASK)
20439 
20440 #define CCM_GPR_SHARED8_CLR_m33_semc_ipg_stop_MASK (0x4000U)
20441 #define CCM_GPR_SHARED8_CLR_m33_semc_ipg_stop_SHIFT (14U)
20442 /*! m33_semc_ipg_stop - m33_semc_ipg_stop */
20443 #define CCM_GPR_SHARED8_CLR_m33_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_semc_ipg_stop_MASK)
20444 
20445 #define CCM_GPR_SHARED8_CLR_m33_iee_ipg_stop_MASK (0x8000U)
20446 #define CCM_GPR_SHARED8_CLR_m33_iee_ipg_stop_SHIFT (15U)
20447 /*! m33_iee_ipg_stop - m33_iee_ipg_stop */
20448 #define CCM_GPR_SHARED8_CLR_m33_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_iee_ipg_stop_MASK)
20449 
20450 #define CCM_GPR_SHARED8_CLR_m33_gpio1_ipg_stop_MASK (0x10000U)
20451 #define CCM_GPR_SHARED8_CLR_m33_gpio1_ipg_stop_SHIFT (16U)
20452 /*! m33_gpio1_ipg_stop - m33_gpio1_ipg_stop */
20453 #define CCM_GPR_SHARED8_CLR_m33_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio1_ipg_stop_MASK)
20454 
20455 #define CCM_GPR_SHARED8_CLR_m33_gpio2_ipg_stop_MASK (0x20000U)
20456 #define CCM_GPR_SHARED8_CLR_m33_gpio2_ipg_stop_SHIFT (17U)
20457 /*! m33_gpio2_ipg_stop - m33_gpio2_ipg_stop */
20458 #define CCM_GPR_SHARED8_CLR_m33_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio2_ipg_stop_MASK)
20459 
20460 #define CCM_GPR_SHARED8_CLR_m33_gpio3_ipg_stop_MASK (0x40000U)
20461 #define CCM_GPR_SHARED8_CLR_m33_gpio3_ipg_stop_SHIFT (18U)
20462 /*! m33_gpio3_ipg_stop - m33_gpio3_ipg_stop */
20463 #define CCM_GPR_SHARED8_CLR_m33_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio3_ipg_stop_MASK)
20464 
20465 #define CCM_GPR_SHARED8_CLR_m33_gpio4_ipg_stop_MASK (0x80000U)
20466 #define CCM_GPR_SHARED8_CLR_m33_gpio4_ipg_stop_SHIFT (19U)
20467 /*! m33_gpio4_ipg_stop - m33_gpio4_ipg_stop */
20468 #define CCM_GPR_SHARED8_CLR_m33_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio4_ipg_stop_MASK)
20469 
20470 #define CCM_GPR_SHARED8_CLR_m33_gpio5_ipg_stop_MASK (0x100000U)
20471 #define CCM_GPR_SHARED8_CLR_m33_gpio5_ipg_stop_SHIFT (20U)
20472 /*! m33_gpio5_ipg_stop - m33_gpio5_ipg_stop */
20473 #define CCM_GPR_SHARED8_CLR_m33_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio5_ipg_stop_MASK)
20474 
20475 #define CCM_GPR_SHARED8_CLR_m33_gpio6_ipg_stop_MASK (0x200000U)
20476 #define CCM_GPR_SHARED8_CLR_m33_gpio6_ipg_stop_SHIFT (21U)
20477 /*! m33_gpio6_ipg_stop - m33_gpio6_ipg_stop */
20478 #define CCM_GPR_SHARED8_CLR_m33_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_gpio6_ipg_stop_MASK)
20479 
20480 #define CCM_GPR_SHARED8_CLR_m33_flexio1_ipg_stop_MASK (0x400000U)
20481 #define CCM_GPR_SHARED8_CLR_m33_flexio1_ipg_stop_SHIFT (22U)
20482 /*! m33_flexio1_ipg_stop - m33_flexio1_ipg_stop */
20483 #define CCM_GPR_SHARED8_CLR_m33_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_flexio1_ipg_stop_MASK)
20484 
20485 #define CCM_GPR_SHARED8_CLR_m33_flexio2_ipg_stop_MASK (0x800000U)
20486 #define CCM_GPR_SHARED8_CLR_m33_flexio2_ipg_stop_SHIFT (23U)
20487 /*! m33_flexio2_ipg_stop - m33_flexio2_ipg_stop */
20488 #define CCM_GPR_SHARED8_CLR_m33_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_flexio2_ipg_stop_MASK)
20489 
20490 #define CCM_GPR_SHARED8_CLR_m33_can1_ipg_stop_MASK (0x1000000U)
20491 #define CCM_GPR_SHARED8_CLR_m33_can1_ipg_stop_SHIFT (24U)
20492 /*! m33_can1_ipg_stop - m33_can1_ipg_stop */
20493 #define CCM_GPR_SHARED8_CLR_m33_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_can1_ipg_stop_MASK)
20494 
20495 #define CCM_GPR_SHARED8_CLR_m33_can2_ipg_stop_MASK (0x2000000U)
20496 #define CCM_GPR_SHARED8_CLR_m33_can2_ipg_stop_SHIFT (25U)
20497 /*! m33_can2_ipg_stop - m33_can2_ipg_stop */
20498 #define CCM_GPR_SHARED8_CLR_m33_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_can2_ipg_stop_MASK)
20499 
20500 #define CCM_GPR_SHARED8_CLR_m33_can3_ipg_stop_MASK (0x4000000U)
20501 #define CCM_GPR_SHARED8_CLR_m33_can3_ipg_stop_SHIFT (26U)
20502 /*! m33_can3_ipg_stop - m33_can3_ipg_stop */
20503 #define CCM_GPR_SHARED8_CLR_m33_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_can3_ipg_stop_MASK)
20504 
20505 #define CCM_GPR_SHARED8_CLR_m33_lpuart1_ipg_stop_MASK (0x8000000U)
20506 #define CCM_GPR_SHARED8_CLR_m33_lpuart1_ipg_stop_SHIFT (27U)
20507 /*! m33_lpuart1_ipg_stop - m33_lpuart1_ipg_stop */
20508 #define CCM_GPR_SHARED8_CLR_m33_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_lpuart1_ipg_stop_MASK)
20509 
20510 #define CCM_GPR_SHARED8_CLR_m33_lpuart2_ipg_stop_MASK (0x10000000U)
20511 #define CCM_GPR_SHARED8_CLR_m33_lpuart2_ipg_stop_SHIFT (28U)
20512 /*! m33_lpuart2_ipg_stop - m33_lpuart2_ipg_stop */
20513 #define CCM_GPR_SHARED8_CLR_m33_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_lpuart2_ipg_stop_MASK)
20514 
20515 #define CCM_GPR_SHARED8_CLR_m33_lpuart3_ipg_stop_MASK (0x20000000U)
20516 #define CCM_GPR_SHARED8_CLR_m33_lpuart3_ipg_stop_SHIFT (29U)
20517 /*! m33_lpuart3_ipg_stop - m33_lpuart3_ipg_stop */
20518 #define CCM_GPR_SHARED8_CLR_m33_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_lpuart3_ipg_stop_MASK)
20519 
20520 #define CCM_GPR_SHARED8_CLR_m33_lpuart4_ipg_stop_MASK (0x40000000U)
20521 #define CCM_GPR_SHARED8_CLR_m33_lpuart4_ipg_stop_SHIFT (30U)
20522 /*! m33_lpuart4_ipg_stop - m33_lpuart4_ipg_stop */
20523 #define CCM_GPR_SHARED8_CLR_m33_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_lpuart4_ipg_stop_MASK)
20524 
20525 #define CCM_GPR_SHARED8_CLR_m33_lpuart5_ipg_stop_MASK (0x80000000U)
20526 #define CCM_GPR_SHARED8_CLR_m33_lpuart5_ipg_stop_SHIFT (31U)
20527 /*! m33_lpuart5_ipg_stop - m33_lpuart5_ipg_stop */
20528 #define CCM_GPR_SHARED8_CLR_m33_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_CLR_m33_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_CLR_m33_lpuart5_ipg_stop_MASK)
20529 /*! @} */
20530 
20531 /*! @name GPR_SHARED8_TOG - General Purpose Register */
20532 /*! @{ */
20533 
20534 #define CCM_GPR_SHARED8_TOG_m33_cm7_ipg_stop_MASK (0x1U)
20535 #define CCM_GPR_SHARED8_TOG_m33_cm7_ipg_stop_SHIFT (0U)
20536 /*! m33_cm7_ipg_stop - m33_cm7_ipg_stop */
20537 #define CCM_GPR_SHARED8_TOG_m33_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_cm7_ipg_stop_MASK)
20538 
20539 #define CCM_GPR_SHARED8_TOG_m33_cm33_ipg_stop_MASK (0x2U)
20540 #define CCM_GPR_SHARED8_TOG_m33_cm33_ipg_stop_SHIFT (1U)
20541 /*! m33_cm33_ipg_stop - m33_cm33_ipg_stop */
20542 #define CCM_GPR_SHARED8_TOG_m33_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_cm33_ipg_stop_MASK)
20543 
20544 #define CCM_GPR_SHARED8_TOG_m33_edma3_ipg_stop_MASK (0x4U)
20545 #define CCM_GPR_SHARED8_TOG_m33_edma3_ipg_stop_SHIFT (2U)
20546 /*! m33_edma3_ipg_stop - m33_edma3_ipg_stop */
20547 #define CCM_GPR_SHARED8_TOG_m33_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_edma3_ipg_stop_MASK)
20548 
20549 #define CCM_GPR_SHARED8_TOG_m33_edma4_ipg_stop_MASK (0x8U)
20550 #define CCM_GPR_SHARED8_TOG_m33_edma4_ipg_stop_SHIFT (3U)
20551 /*! m33_edma4_ipg_stop - m33_edma4_ipg_stop */
20552 #define CCM_GPR_SHARED8_TOG_m33_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_edma4_ipg_stop_MASK)
20553 
20554 #define CCM_GPR_SHARED8_TOG_m33_netc_ipg_stop_MASK (0x10U)
20555 #define CCM_GPR_SHARED8_TOG_m33_netc_ipg_stop_SHIFT (4U)
20556 /*! m33_netc_ipg_stop - m33_netc_ipg_stop */
20557 #define CCM_GPR_SHARED8_TOG_m33_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_netc_ipg_stop_MASK)
20558 
20559 #define CCM_GPR_SHARED8_TOG_m33_sim_aon_ipg_stop_MASK (0x100U)
20560 #define CCM_GPR_SHARED8_TOG_m33_sim_aon_ipg_stop_SHIFT (8U)
20561 /*! m33_sim_aon_ipg_stop - m33_sim_aon_ipg_stop */
20562 #define CCM_GPR_SHARED8_TOG_m33_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_sim_aon_ipg_stop_MASK)
20563 
20564 #define CCM_GPR_SHARED8_TOG_m33_adc1_ipg_stop_MASK (0x200U)
20565 #define CCM_GPR_SHARED8_TOG_m33_adc1_ipg_stop_SHIFT (9U)
20566 /*! m33_adc1_ipg_stop - m33_adc1_ipg_stop */
20567 #define CCM_GPR_SHARED8_TOG_m33_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_adc1_ipg_stop_MASK)
20568 
20569 #define CCM_GPR_SHARED8_TOG_m33_adc2_ipg_stop_MASK (0x400U)
20570 #define CCM_GPR_SHARED8_TOG_m33_adc2_ipg_stop_SHIFT (10U)
20571 /*! m33_adc2_ipg_stop - m33_adc2_ipg_stop */
20572 #define CCM_GPR_SHARED8_TOG_m33_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_adc2_ipg_stop_MASK)
20573 
20574 #define CCM_GPR_SHARED8_TOG_m33_flexspi1_ipg_stop_MASK (0x800U)
20575 #define CCM_GPR_SHARED8_TOG_m33_flexspi1_ipg_stop_SHIFT (11U)
20576 /*! m33_flexspi1_ipg_stop - m33_flexspi1_ipg_stop */
20577 #define CCM_GPR_SHARED8_TOG_m33_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_flexspi1_ipg_stop_MASK)
20578 
20579 #define CCM_GPR_SHARED8_TOG_m33_flexspi2_ipg_stop_MASK (0x1000U)
20580 #define CCM_GPR_SHARED8_TOG_m33_flexspi2_ipg_stop_SHIFT (12U)
20581 /*! m33_flexspi2_ipg_stop - m33_flexspi2_ipg_stop */
20582 #define CCM_GPR_SHARED8_TOG_m33_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_flexspi2_ipg_stop_MASK)
20583 
20584 #define CCM_GPR_SHARED8_TOG_m33_trdc_ipg_stop_MASK (0x2000U)
20585 #define CCM_GPR_SHARED8_TOG_m33_trdc_ipg_stop_SHIFT (13U)
20586 /*! m33_trdc_ipg_stop - m33_trdc_ipg_stop */
20587 #define CCM_GPR_SHARED8_TOG_m33_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_trdc_ipg_stop_MASK)
20588 
20589 #define CCM_GPR_SHARED8_TOG_m33_semc_ipg_stop_MASK (0x4000U)
20590 #define CCM_GPR_SHARED8_TOG_m33_semc_ipg_stop_SHIFT (14U)
20591 /*! m33_semc_ipg_stop - m33_semc_ipg_stop */
20592 #define CCM_GPR_SHARED8_TOG_m33_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_semc_ipg_stop_MASK)
20593 
20594 #define CCM_GPR_SHARED8_TOG_m33_iee_ipg_stop_MASK (0x8000U)
20595 #define CCM_GPR_SHARED8_TOG_m33_iee_ipg_stop_SHIFT (15U)
20596 /*! m33_iee_ipg_stop - m33_iee_ipg_stop */
20597 #define CCM_GPR_SHARED8_TOG_m33_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_iee_ipg_stop_MASK)
20598 
20599 #define CCM_GPR_SHARED8_TOG_m33_gpio1_ipg_stop_MASK (0x10000U)
20600 #define CCM_GPR_SHARED8_TOG_m33_gpio1_ipg_stop_SHIFT (16U)
20601 /*! m33_gpio1_ipg_stop - m33_gpio1_ipg_stop */
20602 #define CCM_GPR_SHARED8_TOG_m33_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio1_ipg_stop_MASK)
20603 
20604 #define CCM_GPR_SHARED8_TOG_m33_gpio2_ipg_stop_MASK (0x20000U)
20605 #define CCM_GPR_SHARED8_TOG_m33_gpio2_ipg_stop_SHIFT (17U)
20606 /*! m33_gpio2_ipg_stop - m33_gpio2_ipg_stop */
20607 #define CCM_GPR_SHARED8_TOG_m33_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio2_ipg_stop_MASK)
20608 
20609 #define CCM_GPR_SHARED8_TOG_m33_gpio3_ipg_stop_MASK (0x40000U)
20610 #define CCM_GPR_SHARED8_TOG_m33_gpio3_ipg_stop_SHIFT (18U)
20611 /*! m33_gpio3_ipg_stop - m33_gpio3_ipg_stop */
20612 #define CCM_GPR_SHARED8_TOG_m33_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio3_ipg_stop_MASK)
20613 
20614 #define CCM_GPR_SHARED8_TOG_m33_gpio4_ipg_stop_MASK (0x80000U)
20615 #define CCM_GPR_SHARED8_TOG_m33_gpio4_ipg_stop_SHIFT (19U)
20616 /*! m33_gpio4_ipg_stop - m33_gpio4_ipg_stop */
20617 #define CCM_GPR_SHARED8_TOG_m33_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio4_ipg_stop_MASK)
20618 
20619 #define CCM_GPR_SHARED8_TOG_m33_gpio5_ipg_stop_MASK (0x100000U)
20620 #define CCM_GPR_SHARED8_TOG_m33_gpio5_ipg_stop_SHIFT (20U)
20621 /*! m33_gpio5_ipg_stop - m33_gpio5_ipg_stop */
20622 #define CCM_GPR_SHARED8_TOG_m33_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio5_ipg_stop_MASK)
20623 
20624 #define CCM_GPR_SHARED8_TOG_m33_gpio6_ipg_stop_MASK (0x200000U)
20625 #define CCM_GPR_SHARED8_TOG_m33_gpio6_ipg_stop_SHIFT (21U)
20626 /*! m33_gpio6_ipg_stop - m33_gpio6_ipg_stop */
20627 #define CCM_GPR_SHARED8_TOG_m33_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_gpio6_ipg_stop_MASK)
20628 
20629 #define CCM_GPR_SHARED8_TOG_m33_flexio1_ipg_stop_MASK (0x400000U)
20630 #define CCM_GPR_SHARED8_TOG_m33_flexio1_ipg_stop_SHIFT (22U)
20631 /*! m33_flexio1_ipg_stop - m33_flexio1_ipg_stop */
20632 #define CCM_GPR_SHARED8_TOG_m33_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_flexio1_ipg_stop_MASK)
20633 
20634 #define CCM_GPR_SHARED8_TOG_m33_flexio2_ipg_stop_MASK (0x800000U)
20635 #define CCM_GPR_SHARED8_TOG_m33_flexio2_ipg_stop_SHIFT (23U)
20636 /*! m33_flexio2_ipg_stop - m33_flexio2_ipg_stop */
20637 #define CCM_GPR_SHARED8_TOG_m33_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_flexio2_ipg_stop_MASK)
20638 
20639 #define CCM_GPR_SHARED8_TOG_m33_can1_ipg_stop_MASK (0x1000000U)
20640 #define CCM_GPR_SHARED8_TOG_m33_can1_ipg_stop_SHIFT (24U)
20641 /*! m33_can1_ipg_stop - m33_can1_ipg_stop */
20642 #define CCM_GPR_SHARED8_TOG_m33_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_can1_ipg_stop_MASK)
20643 
20644 #define CCM_GPR_SHARED8_TOG_m33_can2_ipg_stop_MASK (0x2000000U)
20645 #define CCM_GPR_SHARED8_TOG_m33_can2_ipg_stop_SHIFT (25U)
20646 /*! m33_can2_ipg_stop - m33_can2_ipg_stop */
20647 #define CCM_GPR_SHARED8_TOG_m33_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_can2_ipg_stop_MASK)
20648 
20649 #define CCM_GPR_SHARED8_TOG_m33_can3_ipg_stop_MASK (0x4000000U)
20650 #define CCM_GPR_SHARED8_TOG_m33_can3_ipg_stop_SHIFT (26U)
20651 /*! m33_can3_ipg_stop - m33_can3_ipg_stop */
20652 #define CCM_GPR_SHARED8_TOG_m33_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_can3_ipg_stop_MASK)
20653 
20654 #define CCM_GPR_SHARED8_TOG_m33_lpuart1_ipg_stop_MASK (0x8000000U)
20655 #define CCM_GPR_SHARED8_TOG_m33_lpuart1_ipg_stop_SHIFT (27U)
20656 /*! m33_lpuart1_ipg_stop - m33_lpuart1_ipg_stop */
20657 #define CCM_GPR_SHARED8_TOG_m33_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_lpuart1_ipg_stop_MASK)
20658 
20659 #define CCM_GPR_SHARED8_TOG_m33_lpuart2_ipg_stop_MASK (0x10000000U)
20660 #define CCM_GPR_SHARED8_TOG_m33_lpuart2_ipg_stop_SHIFT (28U)
20661 /*! m33_lpuart2_ipg_stop - m33_lpuart2_ipg_stop */
20662 #define CCM_GPR_SHARED8_TOG_m33_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_lpuart2_ipg_stop_MASK)
20663 
20664 #define CCM_GPR_SHARED8_TOG_m33_lpuart3_ipg_stop_MASK (0x20000000U)
20665 #define CCM_GPR_SHARED8_TOG_m33_lpuart3_ipg_stop_SHIFT (29U)
20666 /*! m33_lpuart3_ipg_stop - m33_lpuart3_ipg_stop */
20667 #define CCM_GPR_SHARED8_TOG_m33_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_lpuart3_ipg_stop_MASK)
20668 
20669 #define CCM_GPR_SHARED8_TOG_m33_lpuart4_ipg_stop_MASK (0x40000000U)
20670 #define CCM_GPR_SHARED8_TOG_m33_lpuart4_ipg_stop_SHIFT (30U)
20671 /*! m33_lpuart4_ipg_stop - m33_lpuart4_ipg_stop */
20672 #define CCM_GPR_SHARED8_TOG_m33_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_lpuart4_ipg_stop_MASK)
20673 
20674 #define CCM_GPR_SHARED8_TOG_m33_lpuart5_ipg_stop_MASK (0x80000000U)
20675 #define CCM_GPR_SHARED8_TOG_m33_lpuart5_ipg_stop_SHIFT (31U)
20676 /*! m33_lpuart5_ipg_stop - m33_lpuart5_ipg_stop */
20677 #define CCM_GPR_SHARED8_TOG_m33_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_TOG_m33_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED8_TOG_m33_lpuart5_ipg_stop_MASK)
20678 /*! @} */
20679 
20680 /*! @name GPR_SHARED8_AUTHEN - GPR access control */
20681 /*! @{ */
20682 
20683 #define CCM_GPR_SHARED8_AUTHEN_TZ_USER_MASK      (0x100U)
20684 #define CCM_GPR_SHARED8_AUTHEN_TZ_USER_SHIFT     (8U)
20685 /*! TZ_USER - User access permission
20686  *  0b1..Registers of shared GPR slice can be changed in user mode.
20687  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
20688  */
20689 #define CCM_GPR_SHARED8_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TZ_USER_MASK)
20690 
20691 #define CCM_GPR_SHARED8_AUTHEN_TZ_NS_MASK        (0x200U)
20692 #define CCM_GPR_SHARED8_AUTHEN_TZ_NS_SHIFT       (9U)
20693 /*! TZ_NS - Non-secure access permission
20694  *  0b0..Cannot be changed in Non-secure mode.
20695  *  0b1..Can be changed in Non-secure mode.
20696  */
20697 #define CCM_GPR_SHARED8_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TZ_NS_MASK)
20698 
20699 #define CCM_GPR_SHARED8_AUTHEN_LOCK_TZ_MASK      (0x800U)
20700 #define CCM_GPR_SHARED8_AUTHEN_LOCK_TZ_SHIFT     (11U)
20701 /*! LOCK_TZ - Lock TrustZone settings
20702  *  0b0..TrustZone settings is not locked.
20703  *  0b1..TrustZone settings is locked.
20704  */
20705 #define CCM_GPR_SHARED8_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_LOCK_TZ_MASK)
20706 
20707 #define CCM_GPR_SHARED8_AUTHEN_LOCK_LIST_MASK    (0x8000U)
20708 #define CCM_GPR_SHARED8_AUTHEN_LOCK_LIST_SHIFT   (15U)
20709 /*! LOCK_LIST - Lock white list
20710  *  0b0..Whitelist is not locked.
20711  *  0b1..Whitelist is locked.
20712  */
20713 #define CCM_GPR_SHARED8_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_LOCK_LIST_MASK)
20714 
20715 #define CCM_GPR_SHARED8_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
20716 #define CCM_GPR_SHARED8_AUTHEN_WHITE_LIST_SHIFT  (16U)
20717 /*! WHITE_LIST - Whitelist settings */
20718 #define CCM_GPR_SHARED8_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_WHITE_LIST_MASK)
20719 /*! @} */
20720 
20721 /*! @name GPR_SHARED8_AUTHEN_SET - GPR access control */
20722 /*! @{ */
20723 
20724 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_USER_MASK  (0x100U)
20725 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_USER_SHIFT (8U)
20726 /*! TZ_USER - User access permission */
20727 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_SET_TZ_USER_MASK)
20728 
20729 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_NS_MASK    (0x200U)
20730 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_NS_SHIFT   (9U)
20731 /*! TZ_NS - Non-secure access permission */
20732 #define CCM_GPR_SHARED8_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_SET_TZ_NS_MASK)
20733 
20734 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
20735 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
20736 /*! LOCK_TZ - Lock TrustZone settings */
20737 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_SET_LOCK_TZ_MASK)
20738 
20739 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
20740 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
20741 /*! LOCK_LIST - Lock white list */
20742 #define CCM_GPR_SHARED8_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_SET_LOCK_LIST_MASK)
20743 
20744 #define CCM_GPR_SHARED8_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
20745 #define CCM_GPR_SHARED8_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
20746 /*! WHITE_LIST - Whitelist settings */
20747 #define CCM_GPR_SHARED8_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_SET_WHITE_LIST_MASK)
20748 /*! @} */
20749 
20750 /*! @name GPR_SHARED8_AUTHEN_CLR - GPR access control */
20751 /*! @{ */
20752 
20753 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
20754 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_USER_SHIFT (8U)
20755 /*! TZ_USER - User access permission */
20756 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_CLR_TZ_USER_MASK)
20757 
20758 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
20759 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
20760 /*! TZ_NS - Non-secure access permission */
20761 #define CCM_GPR_SHARED8_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_CLR_TZ_NS_MASK)
20762 
20763 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
20764 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
20765 /*! LOCK_TZ - Lock TrustZone settings */
20766 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_TZ_MASK)
20767 
20768 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
20769 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
20770 /*! LOCK_LIST - Lock white list */
20771 #define CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_CLR_LOCK_LIST_MASK)
20772 
20773 #define CCM_GPR_SHARED8_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
20774 #define CCM_GPR_SHARED8_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
20775 /*! WHITE_LIST - Whitelist settings */
20776 #define CCM_GPR_SHARED8_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_CLR_WHITE_LIST_MASK)
20777 /*! @} */
20778 
20779 /*! @name GPR_SHARED8_AUTHEN_TOG - GPR access control */
20780 /*! @{ */
20781 
20782 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
20783 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_USER_SHIFT (8U)
20784 /*! TZ_USER - User access permission */
20785 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TOG_TZ_USER_MASK)
20786 
20787 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
20788 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
20789 /*! TZ_NS - Non-secure access permission */
20790 #define CCM_GPR_SHARED8_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TOG_TZ_NS_MASK)
20791 
20792 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
20793 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
20794 /*! LOCK_TZ - Lock TrustZone settings */
20795 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_TZ_MASK)
20796 
20797 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
20798 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
20799 /*! LOCK_LIST - Lock white list */
20800 #define CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TOG_LOCK_LIST_MASK)
20801 
20802 #define CCM_GPR_SHARED8_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
20803 #define CCM_GPR_SHARED8_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
20804 /*! WHITE_LIST - Whitelist settings */
20805 #define CCM_GPR_SHARED8_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED8_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED8_AUTHEN_TOG_WHITE_LIST_MASK)
20806 /*! @} */
20807 
20808 /*! @name GPR_SHARED9 - General Purpose Register */
20809 /*! @{ */
20810 
20811 #define CCM_GPR_SHARED9_m33_lpuart6_ipg_stop_MASK (0x1U)
20812 #define CCM_GPR_SHARED9_m33_lpuart6_ipg_stop_SHIFT (0U)
20813 /*! m33_lpuart6_ipg_stop - m33_lpuart6_ipg_stop */
20814 #define CCM_GPR_SHARED9_m33_lpuart6_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart6_ipg_stop_MASK)
20815 
20816 #define CCM_GPR_SHARED9_m33_lpuart7_ipg_stop_MASK (0x2U)
20817 #define CCM_GPR_SHARED9_m33_lpuart7_ipg_stop_SHIFT (1U)
20818 /*! m33_lpuart7_ipg_stop - m33_lpuart7_ipg_stop */
20819 #define CCM_GPR_SHARED9_m33_lpuart7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart7_ipg_stop_MASK)
20820 
20821 #define CCM_GPR_SHARED9_m33_lpuart8_ipg_stop_MASK (0x4U)
20822 #define CCM_GPR_SHARED9_m33_lpuart8_ipg_stop_SHIFT (2U)
20823 /*! m33_lpuart8_ipg_stop - m33_lpuart8_ipg_stop */
20824 #define CCM_GPR_SHARED9_m33_lpuart8_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart8_ipg_stop_MASK)
20825 
20826 #define CCM_GPR_SHARED9_m33_lpuart9_ipg_stop_MASK (0x8U)
20827 #define CCM_GPR_SHARED9_m33_lpuart9_ipg_stop_SHIFT (3U)
20828 /*! m33_lpuart9_ipg_stop - m33_lpuart9_ipg_stop */
20829 #define CCM_GPR_SHARED9_m33_lpuart9_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart9_ipg_stop_MASK)
20830 
20831 #define CCM_GPR_SHARED9_m33_lpuart10_ipg_stop_MASK (0x10U)
20832 #define CCM_GPR_SHARED9_m33_lpuart10_ipg_stop_SHIFT (4U)
20833 /*! m33_lpuart10_ipg_stop - m33_lpuart10_ipg_stop */
20834 #define CCM_GPR_SHARED9_m33_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart10_ipg_stop_MASK)
20835 
20836 #define CCM_GPR_SHARED9_m33_lpuart11_ipg_stop_MASK (0x20U)
20837 #define CCM_GPR_SHARED9_m33_lpuart11_ipg_stop_SHIFT (5U)
20838 /*! m33_lpuart11_ipg_stop - m33_lpuart11_ipg_stop */
20839 #define CCM_GPR_SHARED9_m33_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart11_ipg_stop_MASK)
20840 
20841 #define CCM_GPR_SHARED9_m33_lpuart12_ipg_stop_MASK (0x40U)
20842 #define CCM_GPR_SHARED9_m33_lpuart12_ipg_stop_SHIFT (6U)
20843 /*! m33_lpuart12_ipg_stop - m33_lpuart12_ipg_stop */
20844 #define CCM_GPR_SHARED9_m33_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpuart12_ipg_stop_MASK)
20845 
20846 #define CCM_GPR_SHARED9_m33_lpi2c1_ipg_stop_MASK (0x80U)
20847 #define CCM_GPR_SHARED9_m33_lpi2c1_ipg_stop_SHIFT (7U)
20848 /*! m33_lpi2c1_ipg_stop - m33_lpi2c1_ipg_stop */
20849 #define CCM_GPR_SHARED9_m33_lpi2c1_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c1_ipg_stop_MASK)
20850 
20851 #define CCM_GPR_SHARED9_m33_lpi2c2_ipg_stop_MASK (0x100U)
20852 #define CCM_GPR_SHARED9_m33_lpi2c2_ipg_stop_SHIFT (8U)
20853 /*! m33_lpi2c2_ipg_stop - m33_lpi2c2_ipg_stop */
20854 #define CCM_GPR_SHARED9_m33_lpi2c2_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c2_ipg_stop_MASK)
20855 
20856 #define CCM_GPR_SHARED9_m33_lpi2c3_ipg_stop_MASK (0x200U)
20857 #define CCM_GPR_SHARED9_m33_lpi2c3_ipg_stop_SHIFT (9U)
20858 /*! m33_lpi2c3_ipg_stop - m33_lpi2c3_ipg_stop */
20859 #define CCM_GPR_SHARED9_m33_lpi2c3_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c3_ipg_stop_MASK)
20860 
20861 #define CCM_GPR_SHARED9_m33_lpi2c4_ipg_stop_MASK (0x400U)
20862 #define CCM_GPR_SHARED9_m33_lpi2c4_ipg_stop_SHIFT (10U)
20863 /*! m33_lpi2c4_ipg_stop - m33_lpi2c4_ipg_stop */
20864 #define CCM_GPR_SHARED9_m33_lpi2c4_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c4_ipg_stop_MASK)
20865 
20866 #define CCM_GPR_SHARED9_m33_lpi2c5_ipg_stop_MASK (0x800U)
20867 #define CCM_GPR_SHARED9_m33_lpi2c5_ipg_stop_SHIFT (11U)
20868 /*! m33_lpi2c5_ipg_stop - m33_lpi2c5_ipg_stop */
20869 #define CCM_GPR_SHARED9_m33_lpi2c5_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c5_ipg_stop_MASK)
20870 
20871 #define CCM_GPR_SHARED9_m33_lpi2c6_ipg_stop_MASK (0x1000U)
20872 #define CCM_GPR_SHARED9_m33_lpi2c6_ipg_stop_SHIFT (12U)
20873 /*! m33_lpi2c6_ipg_stop - m33_lpi2c6_ipg_stop */
20874 #define CCM_GPR_SHARED9_m33_lpi2c6_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpi2c6_ipg_stop_MASK)
20875 
20876 #define CCM_GPR_SHARED9_m33_lpspi1_ipg_stop_MASK (0x2000U)
20877 #define CCM_GPR_SHARED9_m33_lpspi1_ipg_stop_SHIFT (13U)
20878 /*! m33_lpspi1_ipg_stop - m33_lpspi1_ipg_stop */
20879 #define CCM_GPR_SHARED9_m33_lpspi1_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi1_ipg_stop_MASK)
20880 
20881 #define CCM_GPR_SHARED9_m33_lpspi2_ipg_stop_MASK (0x4000U)
20882 #define CCM_GPR_SHARED9_m33_lpspi2_ipg_stop_SHIFT (14U)
20883 /*! m33_lpspi2_ipg_stop - m33_lpspi2_ipg_stop */
20884 #define CCM_GPR_SHARED9_m33_lpspi2_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi2_ipg_stop_MASK)
20885 
20886 #define CCM_GPR_SHARED9_m33_lpspi3_ipg_stop_MASK (0x8000U)
20887 #define CCM_GPR_SHARED9_m33_lpspi3_ipg_stop_SHIFT (15U)
20888 /*! m33_lpspi3_ipg_stop - m33_lpspi3_ipg_stop */
20889 #define CCM_GPR_SHARED9_m33_lpspi3_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi3_ipg_stop_MASK)
20890 
20891 #define CCM_GPR_SHARED9_m33_lpspi4_ipg_stop_MASK (0x10000U)
20892 #define CCM_GPR_SHARED9_m33_lpspi4_ipg_stop_SHIFT (16U)
20893 /*! m33_lpspi4_ipg_stop - m33_lpspi4_ipg_stop */
20894 #define CCM_GPR_SHARED9_m33_lpspi4_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi4_ipg_stop_MASK)
20895 
20896 #define CCM_GPR_SHARED9_m33_lpspi5_ipg_stop_MASK (0x20000U)
20897 #define CCM_GPR_SHARED9_m33_lpspi5_ipg_stop_SHIFT (17U)
20898 /*! m33_lpspi5_ipg_stop - m33_lpspi5_ipg_stop */
20899 #define CCM_GPR_SHARED9_m33_lpspi5_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi5_ipg_stop_MASK)
20900 
20901 #define CCM_GPR_SHARED9_m33_lpspi6_ipg_stop_MASK (0x40000U)
20902 #define CCM_GPR_SHARED9_m33_lpspi6_ipg_stop_SHIFT (18U)
20903 /*! m33_lpspi6_ipg_stop - m33_lpspi6_ipg_stop */
20904 #define CCM_GPR_SHARED9_m33_lpspi6_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_lpspi6_ipg_stop_MASK)
20905 
20906 #define CCM_GPR_SHARED9_m33_sinc1_ipg_stop_MASK  (0x80000U)
20907 #define CCM_GPR_SHARED9_m33_sinc1_ipg_stop_SHIFT (19U)
20908 /*! m33_sinc1_ipg_stop - m33_sinc1_ipg_stop */
20909 #define CCM_GPR_SHARED9_m33_sinc1_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sinc1_ipg_stop_MASK)
20910 
20911 #define CCM_GPR_SHARED9_m33_sinc2_ipg_stop_MASK  (0x100000U)
20912 #define CCM_GPR_SHARED9_m33_sinc2_ipg_stop_SHIFT (20U)
20913 /*! m33_sinc2_ipg_stop - m33_sinc2_ipg_stop */
20914 #define CCM_GPR_SHARED9_m33_sinc2_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sinc2_ipg_stop_MASK)
20915 
20916 #define CCM_GPR_SHARED9_m33_sinc3_ipg_stop_MASK  (0x200000U)
20917 #define CCM_GPR_SHARED9_m33_sinc3_ipg_stop_SHIFT (21U)
20918 /*! m33_sinc3_ipg_stop - m33_sinc3_ipg_stop */
20919 #define CCM_GPR_SHARED9_m33_sinc3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sinc3_ipg_stop_MASK)
20920 
20921 #define CCM_GPR_SHARED9_m33_sai1_ipg_stop_MASK   (0x400000U)
20922 #define CCM_GPR_SHARED9_m33_sai1_ipg_stop_SHIFT  (22U)
20923 /*! m33_sai1_ipg_stop - m33_sai1_ipg_stop */
20924 #define CCM_GPR_SHARED9_m33_sai1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sai1_ipg_stop_MASK)
20925 
20926 #define CCM_GPR_SHARED9_m33_sai2_ipg_stop_MASK   (0x800000U)
20927 #define CCM_GPR_SHARED9_m33_sai2_ipg_stop_SHIFT  (23U)
20928 /*! m33_sai2_ipg_stop - m33_sai2_ipg_stop */
20929 #define CCM_GPR_SHARED9_m33_sai2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sai2_ipg_stop_MASK)
20930 
20931 #define CCM_GPR_SHARED9_m33_sai3_ipg_stop_MASK   (0x1000000U)
20932 #define CCM_GPR_SHARED9_m33_sai3_ipg_stop_SHIFT  (24U)
20933 /*! m33_sai3_ipg_stop - m33_sai3_ipg_stop */
20934 #define CCM_GPR_SHARED9_m33_sai3_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sai3_ipg_stop_MASK)
20935 
20936 #define CCM_GPR_SHARED9_m33_sai4_ipg_stop_MASK   (0x2000000U)
20937 #define CCM_GPR_SHARED9_m33_sai4_ipg_stop_SHIFT  (25U)
20938 /*! m33_sai4_ipg_stop - m33_sai4_ipg_stop */
20939 #define CCM_GPR_SHARED9_m33_sai4_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_sai4_ipg_stop_MASK)
20940 
20941 #define CCM_GPR_SHARED9_m33_mic_ipg_stop_MASK    (0x4000000U)
20942 #define CCM_GPR_SHARED9_m33_mic_ipg_stop_SHIFT   (26U)
20943 /*! m33_mic_ipg_stop - m33_mic_ipg_stop */
20944 #define CCM_GPR_SHARED9_m33_mic_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_m33_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_m33_mic_ipg_stop_MASK)
20945 /*! @} */
20946 
20947 /*! @name GPR_SHARED9_SET - General Purpose Register */
20948 /*! @{ */
20949 
20950 #define CCM_GPR_SHARED9_SET_m33_lpuart6_ipg_stop_MASK (0x1U)
20951 #define CCM_GPR_SHARED9_SET_m33_lpuart6_ipg_stop_SHIFT (0U)
20952 /*! m33_lpuart6_ipg_stop - m33_lpuart6_ipg_stop */
20953 #define CCM_GPR_SHARED9_SET_m33_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart6_ipg_stop_MASK)
20954 
20955 #define CCM_GPR_SHARED9_SET_m33_lpuart7_ipg_stop_MASK (0x2U)
20956 #define CCM_GPR_SHARED9_SET_m33_lpuart7_ipg_stop_SHIFT (1U)
20957 /*! m33_lpuart7_ipg_stop - m33_lpuart7_ipg_stop */
20958 #define CCM_GPR_SHARED9_SET_m33_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart7_ipg_stop_MASK)
20959 
20960 #define CCM_GPR_SHARED9_SET_m33_lpuart8_ipg_stop_MASK (0x4U)
20961 #define CCM_GPR_SHARED9_SET_m33_lpuart8_ipg_stop_SHIFT (2U)
20962 /*! m33_lpuart8_ipg_stop - m33_lpuart8_ipg_stop */
20963 #define CCM_GPR_SHARED9_SET_m33_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart8_ipg_stop_MASK)
20964 
20965 #define CCM_GPR_SHARED9_SET_m33_lpuart9_ipg_stop_MASK (0x8U)
20966 #define CCM_GPR_SHARED9_SET_m33_lpuart9_ipg_stop_SHIFT (3U)
20967 /*! m33_lpuart9_ipg_stop - m33_lpuart9_ipg_stop */
20968 #define CCM_GPR_SHARED9_SET_m33_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart9_ipg_stop_MASK)
20969 
20970 #define CCM_GPR_SHARED9_SET_m33_lpuart10_ipg_stop_MASK (0x10U)
20971 #define CCM_GPR_SHARED9_SET_m33_lpuart10_ipg_stop_SHIFT (4U)
20972 /*! m33_lpuart10_ipg_stop - m33_lpuart10_ipg_stop */
20973 #define CCM_GPR_SHARED9_SET_m33_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart10_ipg_stop_MASK)
20974 
20975 #define CCM_GPR_SHARED9_SET_m33_lpuart11_ipg_stop_MASK (0x20U)
20976 #define CCM_GPR_SHARED9_SET_m33_lpuart11_ipg_stop_SHIFT (5U)
20977 /*! m33_lpuart11_ipg_stop - m33_lpuart11_ipg_stop */
20978 #define CCM_GPR_SHARED9_SET_m33_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart11_ipg_stop_MASK)
20979 
20980 #define CCM_GPR_SHARED9_SET_m33_lpuart12_ipg_stop_MASK (0x40U)
20981 #define CCM_GPR_SHARED9_SET_m33_lpuart12_ipg_stop_SHIFT (6U)
20982 /*! m33_lpuart12_ipg_stop - m33_lpuart12_ipg_stop */
20983 #define CCM_GPR_SHARED9_SET_m33_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpuart12_ipg_stop_MASK)
20984 
20985 #define CCM_GPR_SHARED9_SET_m33_lpi2c1_ipg_stop_MASK (0x80U)
20986 #define CCM_GPR_SHARED9_SET_m33_lpi2c1_ipg_stop_SHIFT (7U)
20987 /*! m33_lpi2c1_ipg_stop - m33_lpi2c1_ipg_stop */
20988 #define CCM_GPR_SHARED9_SET_m33_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c1_ipg_stop_MASK)
20989 
20990 #define CCM_GPR_SHARED9_SET_m33_lpi2c2_ipg_stop_MASK (0x100U)
20991 #define CCM_GPR_SHARED9_SET_m33_lpi2c2_ipg_stop_SHIFT (8U)
20992 /*! m33_lpi2c2_ipg_stop - m33_lpi2c2_ipg_stop */
20993 #define CCM_GPR_SHARED9_SET_m33_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c2_ipg_stop_MASK)
20994 
20995 #define CCM_GPR_SHARED9_SET_m33_lpi2c3_ipg_stop_MASK (0x200U)
20996 #define CCM_GPR_SHARED9_SET_m33_lpi2c3_ipg_stop_SHIFT (9U)
20997 /*! m33_lpi2c3_ipg_stop - m33_lpi2c3_ipg_stop */
20998 #define CCM_GPR_SHARED9_SET_m33_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c3_ipg_stop_MASK)
20999 
21000 #define CCM_GPR_SHARED9_SET_m33_lpi2c4_ipg_stop_MASK (0x400U)
21001 #define CCM_GPR_SHARED9_SET_m33_lpi2c4_ipg_stop_SHIFT (10U)
21002 /*! m33_lpi2c4_ipg_stop - m33_lpi2c4_ipg_stop */
21003 #define CCM_GPR_SHARED9_SET_m33_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c4_ipg_stop_MASK)
21004 
21005 #define CCM_GPR_SHARED9_SET_m33_lpi2c5_ipg_stop_MASK (0x800U)
21006 #define CCM_GPR_SHARED9_SET_m33_lpi2c5_ipg_stop_SHIFT (11U)
21007 /*! m33_lpi2c5_ipg_stop - m33_lpi2c5_ipg_stop */
21008 #define CCM_GPR_SHARED9_SET_m33_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c5_ipg_stop_MASK)
21009 
21010 #define CCM_GPR_SHARED9_SET_m33_lpi2c6_ipg_stop_MASK (0x1000U)
21011 #define CCM_GPR_SHARED9_SET_m33_lpi2c6_ipg_stop_SHIFT (12U)
21012 /*! m33_lpi2c6_ipg_stop - m33_lpi2c6_ipg_stop */
21013 #define CCM_GPR_SHARED9_SET_m33_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpi2c6_ipg_stop_MASK)
21014 
21015 #define CCM_GPR_SHARED9_SET_m33_lpspi1_ipg_stop_MASK (0x2000U)
21016 #define CCM_GPR_SHARED9_SET_m33_lpspi1_ipg_stop_SHIFT (13U)
21017 /*! m33_lpspi1_ipg_stop - m33_lpspi1_ipg_stop */
21018 #define CCM_GPR_SHARED9_SET_m33_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi1_ipg_stop_MASK)
21019 
21020 #define CCM_GPR_SHARED9_SET_m33_lpspi2_ipg_stop_MASK (0x4000U)
21021 #define CCM_GPR_SHARED9_SET_m33_lpspi2_ipg_stop_SHIFT (14U)
21022 /*! m33_lpspi2_ipg_stop - m33_lpspi2_ipg_stop */
21023 #define CCM_GPR_SHARED9_SET_m33_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi2_ipg_stop_MASK)
21024 
21025 #define CCM_GPR_SHARED9_SET_m33_lpspi3_ipg_stop_MASK (0x8000U)
21026 #define CCM_GPR_SHARED9_SET_m33_lpspi3_ipg_stop_SHIFT (15U)
21027 /*! m33_lpspi3_ipg_stop - m33_lpspi3_ipg_stop */
21028 #define CCM_GPR_SHARED9_SET_m33_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi3_ipg_stop_MASK)
21029 
21030 #define CCM_GPR_SHARED9_SET_m33_lpspi4_ipg_stop_MASK (0x10000U)
21031 #define CCM_GPR_SHARED9_SET_m33_lpspi4_ipg_stop_SHIFT (16U)
21032 /*! m33_lpspi4_ipg_stop - m33_lpspi4_ipg_stop */
21033 #define CCM_GPR_SHARED9_SET_m33_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi4_ipg_stop_MASK)
21034 
21035 #define CCM_GPR_SHARED9_SET_m33_lpspi5_ipg_stop_MASK (0x20000U)
21036 #define CCM_GPR_SHARED9_SET_m33_lpspi5_ipg_stop_SHIFT (17U)
21037 /*! m33_lpspi5_ipg_stop - m33_lpspi5_ipg_stop */
21038 #define CCM_GPR_SHARED9_SET_m33_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi5_ipg_stop_MASK)
21039 
21040 #define CCM_GPR_SHARED9_SET_m33_lpspi6_ipg_stop_MASK (0x40000U)
21041 #define CCM_GPR_SHARED9_SET_m33_lpspi6_ipg_stop_SHIFT (18U)
21042 /*! m33_lpspi6_ipg_stop - m33_lpspi6_ipg_stop */
21043 #define CCM_GPR_SHARED9_SET_m33_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_lpspi6_ipg_stop_MASK)
21044 
21045 #define CCM_GPR_SHARED9_SET_m33_sinc1_ipg_stop_MASK (0x80000U)
21046 #define CCM_GPR_SHARED9_SET_m33_sinc1_ipg_stop_SHIFT (19U)
21047 /*! m33_sinc1_ipg_stop - m33_sinc1_ipg_stop */
21048 #define CCM_GPR_SHARED9_SET_m33_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sinc1_ipg_stop_MASK)
21049 
21050 #define CCM_GPR_SHARED9_SET_m33_sinc2_ipg_stop_MASK (0x100000U)
21051 #define CCM_GPR_SHARED9_SET_m33_sinc2_ipg_stop_SHIFT (20U)
21052 /*! m33_sinc2_ipg_stop - m33_sinc2_ipg_stop */
21053 #define CCM_GPR_SHARED9_SET_m33_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sinc2_ipg_stop_MASK)
21054 
21055 #define CCM_GPR_SHARED9_SET_m33_sinc3_ipg_stop_MASK (0x200000U)
21056 #define CCM_GPR_SHARED9_SET_m33_sinc3_ipg_stop_SHIFT (21U)
21057 /*! m33_sinc3_ipg_stop - m33_sinc3_ipg_stop */
21058 #define CCM_GPR_SHARED9_SET_m33_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sinc3_ipg_stop_MASK)
21059 
21060 #define CCM_GPR_SHARED9_SET_m33_sai1_ipg_stop_MASK (0x400000U)
21061 #define CCM_GPR_SHARED9_SET_m33_sai1_ipg_stop_SHIFT (22U)
21062 /*! m33_sai1_ipg_stop - m33_sai1_ipg_stop */
21063 #define CCM_GPR_SHARED9_SET_m33_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sai1_ipg_stop_MASK)
21064 
21065 #define CCM_GPR_SHARED9_SET_m33_sai2_ipg_stop_MASK (0x800000U)
21066 #define CCM_GPR_SHARED9_SET_m33_sai2_ipg_stop_SHIFT (23U)
21067 /*! m33_sai2_ipg_stop - m33_sai2_ipg_stop */
21068 #define CCM_GPR_SHARED9_SET_m33_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sai2_ipg_stop_MASK)
21069 
21070 #define CCM_GPR_SHARED9_SET_m33_sai3_ipg_stop_MASK (0x1000000U)
21071 #define CCM_GPR_SHARED9_SET_m33_sai3_ipg_stop_SHIFT (24U)
21072 /*! m33_sai3_ipg_stop - m33_sai3_ipg_stop */
21073 #define CCM_GPR_SHARED9_SET_m33_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sai3_ipg_stop_MASK)
21074 
21075 #define CCM_GPR_SHARED9_SET_m33_sai4_ipg_stop_MASK (0x2000000U)
21076 #define CCM_GPR_SHARED9_SET_m33_sai4_ipg_stop_SHIFT (25U)
21077 /*! m33_sai4_ipg_stop - m33_sai4_ipg_stop */
21078 #define CCM_GPR_SHARED9_SET_m33_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_sai4_ipg_stop_MASK)
21079 
21080 #define CCM_GPR_SHARED9_SET_m33_mic_ipg_stop_MASK (0x4000000U)
21081 #define CCM_GPR_SHARED9_SET_m33_mic_ipg_stop_SHIFT (26U)
21082 /*! m33_mic_ipg_stop - m33_mic_ipg_stop */
21083 #define CCM_GPR_SHARED9_SET_m33_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_SET_m33_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_SET_m33_mic_ipg_stop_MASK)
21084 /*! @} */
21085 
21086 /*! @name GPR_SHARED9_CLR - General Purpose Register */
21087 /*! @{ */
21088 
21089 #define CCM_GPR_SHARED9_CLR_m33_lpuart6_ipg_stop_MASK (0x1U)
21090 #define CCM_GPR_SHARED9_CLR_m33_lpuart6_ipg_stop_SHIFT (0U)
21091 /*! m33_lpuart6_ipg_stop - m33_lpuart6_ipg_stop */
21092 #define CCM_GPR_SHARED9_CLR_m33_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart6_ipg_stop_MASK)
21093 
21094 #define CCM_GPR_SHARED9_CLR_m33_lpuart7_ipg_stop_MASK (0x2U)
21095 #define CCM_GPR_SHARED9_CLR_m33_lpuart7_ipg_stop_SHIFT (1U)
21096 /*! m33_lpuart7_ipg_stop - m33_lpuart7_ipg_stop */
21097 #define CCM_GPR_SHARED9_CLR_m33_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart7_ipg_stop_MASK)
21098 
21099 #define CCM_GPR_SHARED9_CLR_m33_lpuart8_ipg_stop_MASK (0x4U)
21100 #define CCM_GPR_SHARED9_CLR_m33_lpuart8_ipg_stop_SHIFT (2U)
21101 /*! m33_lpuart8_ipg_stop - m33_lpuart8_ipg_stop */
21102 #define CCM_GPR_SHARED9_CLR_m33_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart8_ipg_stop_MASK)
21103 
21104 #define CCM_GPR_SHARED9_CLR_m33_lpuart9_ipg_stop_MASK (0x8U)
21105 #define CCM_GPR_SHARED9_CLR_m33_lpuart9_ipg_stop_SHIFT (3U)
21106 /*! m33_lpuart9_ipg_stop - m33_lpuart9_ipg_stop */
21107 #define CCM_GPR_SHARED9_CLR_m33_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart9_ipg_stop_MASK)
21108 
21109 #define CCM_GPR_SHARED9_CLR_m33_lpuart10_ipg_stop_MASK (0x10U)
21110 #define CCM_GPR_SHARED9_CLR_m33_lpuart10_ipg_stop_SHIFT (4U)
21111 /*! m33_lpuart10_ipg_stop - m33_lpuart10_ipg_stop */
21112 #define CCM_GPR_SHARED9_CLR_m33_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart10_ipg_stop_MASK)
21113 
21114 #define CCM_GPR_SHARED9_CLR_m33_lpuart11_ipg_stop_MASK (0x20U)
21115 #define CCM_GPR_SHARED9_CLR_m33_lpuart11_ipg_stop_SHIFT (5U)
21116 /*! m33_lpuart11_ipg_stop - m33_lpuart11_ipg_stop */
21117 #define CCM_GPR_SHARED9_CLR_m33_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart11_ipg_stop_MASK)
21118 
21119 #define CCM_GPR_SHARED9_CLR_m33_lpuart12_ipg_stop_MASK (0x40U)
21120 #define CCM_GPR_SHARED9_CLR_m33_lpuart12_ipg_stop_SHIFT (6U)
21121 /*! m33_lpuart12_ipg_stop - m33_lpuart12_ipg_stop */
21122 #define CCM_GPR_SHARED9_CLR_m33_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpuart12_ipg_stop_MASK)
21123 
21124 #define CCM_GPR_SHARED9_CLR_m33_lpi2c1_ipg_stop_MASK (0x80U)
21125 #define CCM_GPR_SHARED9_CLR_m33_lpi2c1_ipg_stop_SHIFT (7U)
21126 /*! m33_lpi2c1_ipg_stop - m33_lpi2c1_ipg_stop */
21127 #define CCM_GPR_SHARED9_CLR_m33_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c1_ipg_stop_MASK)
21128 
21129 #define CCM_GPR_SHARED9_CLR_m33_lpi2c2_ipg_stop_MASK (0x100U)
21130 #define CCM_GPR_SHARED9_CLR_m33_lpi2c2_ipg_stop_SHIFT (8U)
21131 /*! m33_lpi2c2_ipg_stop - m33_lpi2c2_ipg_stop */
21132 #define CCM_GPR_SHARED9_CLR_m33_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c2_ipg_stop_MASK)
21133 
21134 #define CCM_GPR_SHARED9_CLR_m33_lpi2c3_ipg_stop_MASK (0x200U)
21135 #define CCM_GPR_SHARED9_CLR_m33_lpi2c3_ipg_stop_SHIFT (9U)
21136 /*! m33_lpi2c3_ipg_stop - m33_lpi2c3_ipg_stop */
21137 #define CCM_GPR_SHARED9_CLR_m33_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c3_ipg_stop_MASK)
21138 
21139 #define CCM_GPR_SHARED9_CLR_m33_lpi2c4_ipg_stop_MASK (0x400U)
21140 #define CCM_GPR_SHARED9_CLR_m33_lpi2c4_ipg_stop_SHIFT (10U)
21141 /*! m33_lpi2c4_ipg_stop - m33_lpi2c4_ipg_stop */
21142 #define CCM_GPR_SHARED9_CLR_m33_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c4_ipg_stop_MASK)
21143 
21144 #define CCM_GPR_SHARED9_CLR_m33_lpi2c5_ipg_stop_MASK (0x800U)
21145 #define CCM_GPR_SHARED9_CLR_m33_lpi2c5_ipg_stop_SHIFT (11U)
21146 /*! m33_lpi2c5_ipg_stop - m33_lpi2c5_ipg_stop */
21147 #define CCM_GPR_SHARED9_CLR_m33_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c5_ipg_stop_MASK)
21148 
21149 #define CCM_GPR_SHARED9_CLR_m33_lpi2c6_ipg_stop_MASK (0x1000U)
21150 #define CCM_GPR_SHARED9_CLR_m33_lpi2c6_ipg_stop_SHIFT (12U)
21151 /*! m33_lpi2c6_ipg_stop - m33_lpi2c6_ipg_stop */
21152 #define CCM_GPR_SHARED9_CLR_m33_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpi2c6_ipg_stop_MASK)
21153 
21154 #define CCM_GPR_SHARED9_CLR_m33_lpspi1_ipg_stop_MASK (0x2000U)
21155 #define CCM_GPR_SHARED9_CLR_m33_lpspi1_ipg_stop_SHIFT (13U)
21156 /*! m33_lpspi1_ipg_stop - m33_lpspi1_ipg_stop */
21157 #define CCM_GPR_SHARED9_CLR_m33_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi1_ipg_stop_MASK)
21158 
21159 #define CCM_GPR_SHARED9_CLR_m33_lpspi2_ipg_stop_MASK (0x4000U)
21160 #define CCM_GPR_SHARED9_CLR_m33_lpspi2_ipg_stop_SHIFT (14U)
21161 /*! m33_lpspi2_ipg_stop - m33_lpspi2_ipg_stop */
21162 #define CCM_GPR_SHARED9_CLR_m33_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi2_ipg_stop_MASK)
21163 
21164 #define CCM_GPR_SHARED9_CLR_m33_lpspi3_ipg_stop_MASK (0x8000U)
21165 #define CCM_GPR_SHARED9_CLR_m33_lpspi3_ipg_stop_SHIFT (15U)
21166 /*! m33_lpspi3_ipg_stop - m33_lpspi3_ipg_stop */
21167 #define CCM_GPR_SHARED9_CLR_m33_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi3_ipg_stop_MASK)
21168 
21169 #define CCM_GPR_SHARED9_CLR_m33_lpspi4_ipg_stop_MASK (0x10000U)
21170 #define CCM_GPR_SHARED9_CLR_m33_lpspi4_ipg_stop_SHIFT (16U)
21171 /*! m33_lpspi4_ipg_stop - m33_lpspi4_ipg_stop */
21172 #define CCM_GPR_SHARED9_CLR_m33_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi4_ipg_stop_MASK)
21173 
21174 #define CCM_GPR_SHARED9_CLR_m33_lpspi5_ipg_stop_MASK (0x20000U)
21175 #define CCM_GPR_SHARED9_CLR_m33_lpspi5_ipg_stop_SHIFT (17U)
21176 /*! m33_lpspi5_ipg_stop - m33_lpspi5_ipg_stop */
21177 #define CCM_GPR_SHARED9_CLR_m33_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi5_ipg_stop_MASK)
21178 
21179 #define CCM_GPR_SHARED9_CLR_m33_lpspi6_ipg_stop_MASK (0x40000U)
21180 #define CCM_GPR_SHARED9_CLR_m33_lpspi6_ipg_stop_SHIFT (18U)
21181 /*! m33_lpspi6_ipg_stop - m33_lpspi6_ipg_stop */
21182 #define CCM_GPR_SHARED9_CLR_m33_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_lpspi6_ipg_stop_MASK)
21183 
21184 #define CCM_GPR_SHARED9_CLR_m33_sinc1_ipg_stop_MASK (0x80000U)
21185 #define CCM_GPR_SHARED9_CLR_m33_sinc1_ipg_stop_SHIFT (19U)
21186 /*! m33_sinc1_ipg_stop - m33_sinc1_ipg_stop */
21187 #define CCM_GPR_SHARED9_CLR_m33_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sinc1_ipg_stop_MASK)
21188 
21189 #define CCM_GPR_SHARED9_CLR_m33_sinc2_ipg_stop_MASK (0x100000U)
21190 #define CCM_GPR_SHARED9_CLR_m33_sinc2_ipg_stop_SHIFT (20U)
21191 /*! m33_sinc2_ipg_stop - m33_sinc2_ipg_stop */
21192 #define CCM_GPR_SHARED9_CLR_m33_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sinc2_ipg_stop_MASK)
21193 
21194 #define CCM_GPR_SHARED9_CLR_m33_sinc3_ipg_stop_MASK (0x200000U)
21195 #define CCM_GPR_SHARED9_CLR_m33_sinc3_ipg_stop_SHIFT (21U)
21196 /*! m33_sinc3_ipg_stop - m33_sinc3_ipg_stop */
21197 #define CCM_GPR_SHARED9_CLR_m33_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sinc3_ipg_stop_MASK)
21198 
21199 #define CCM_GPR_SHARED9_CLR_m33_sai1_ipg_stop_MASK (0x400000U)
21200 #define CCM_GPR_SHARED9_CLR_m33_sai1_ipg_stop_SHIFT (22U)
21201 /*! m33_sai1_ipg_stop - m33_sai1_ipg_stop */
21202 #define CCM_GPR_SHARED9_CLR_m33_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sai1_ipg_stop_MASK)
21203 
21204 #define CCM_GPR_SHARED9_CLR_m33_sai2_ipg_stop_MASK (0x800000U)
21205 #define CCM_GPR_SHARED9_CLR_m33_sai2_ipg_stop_SHIFT (23U)
21206 /*! m33_sai2_ipg_stop - m33_sai2_ipg_stop */
21207 #define CCM_GPR_SHARED9_CLR_m33_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sai2_ipg_stop_MASK)
21208 
21209 #define CCM_GPR_SHARED9_CLR_m33_sai3_ipg_stop_MASK (0x1000000U)
21210 #define CCM_GPR_SHARED9_CLR_m33_sai3_ipg_stop_SHIFT (24U)
21211 /*! m33_sai3_ipg_stop - m33_sai3_ipg_stop */
21212 #define CCM_GPR_SHARED9_CLR_m33_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sai3_ipg_stop_MASK)
21213 
21214 #define CCM_GPR_SHARED9_CLR_m33_sai4_ipg_stop_MASK (0x2000000U)
21215 #define CCM_GPR_SHARED9_CLR_m33_sai4_ipg_stop_SHIFT (25U)
21216 /*! m33_sai4_ipg_stop - m33_sai4_ipg_stop */
21217 #define CCM_GPR_SHARED9_CLR_m33_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_sai4_ipg_stop_MASK)
21218 
21219 #define CCM_GPR_SHARED9_CLR_m33_mic_ipg_stop_MASK (0x4000000U)
21220 #define CCM_GPR_SHARED9_CLR_m33_mic_ipg_stop_SHIFT (26U)
21221 /*! m33_mic_ipg_stop - m33_mic_ipg_stop */
21222 #define CCM_GPR_SHARED9_CLR_m33_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_CLR_m33_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_CLR_m33_mic_ipg_stop_MASK)
21223 /*! @} */
21224 
21225 /*! @name GPR_SHARED9_TOG - General Purpose Register */
21226 /*! @{ */
21227 
21228 #define CCM_GPR_SHARED9_TOG_m33_lpuart6_ipg_stop_MASK (0x1U)
21229 #define CCM_GPR_SHARED9_TOG_m33_lpuart6_ipg_stop_SHIFT (0U)
21230 /*! m33_lpuart6_ipg_stop - m33_lpuart6_ipg_stop */
21231 #define CCM_GPR_SHARED9_TOG_m33_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart6_ipg_stop_MASK)
21232 
21233 #define CCM_GPR_SHARED9_TOG_m33_lpuart7_ipg_stop_MASK (0x2U)
21234 #define CCM_GPR_SHARED9_TOG_m33_lpuart7_ipg_stop_SHIFT (1U)
21235 /*! m33_lpuart7_ipg_stop - m33_lpuart7_ipg_stop */
21236 #define CCM_GPR_SHARED9_TOG_m33_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart7_ipg_stop_MASK)
21237 
21238 #define CCM_GPR_SHARED9_TOG_m33_lpuart8_ipg_stop_MASK (0x4U)
21239 #define CCM_GPR_SHARED9_TOG_m33_lpuart8_ipg_stop_SHIFT (2U)
21240 /*! m33_lpuart8_ipg_stop - m33_lpuart8_ipg_stop */
21241 #define CCM_GPR_SHARED9_TOG_m33_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart8_ipg_stop_MASK)
21242 
21243 #define CCM_GPR_SHARED9_TOG_m33_lpuart9_ipg_stop_MASK (0x8U)
21244 #define CCM_GPR_SHARED9_TOG_m33_lpuart9_ipg_stop_SHIFT (3U)
21245 /*! m33_lpuart9_ipg_stop - m33_lpuart9_ipg_stop */
21246 #define CCM_GPR_SHARED9_TOG_m33_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart9_ipg_stop_MASK)
21247 
21248 #define CCM_GPR_SHARED9_TOG_m33_lpuart10_ipg_stop_MASK (0x10U)
21249 #define CCM_GPR_SHARED9_TOG_m33_lpuart10_ipg_stop_SHIFT (4U)
21250 /*! m33_lpuart10_ipg_stop - m33_lpuart10_ipg_stop */
21251 #define CCM_GPR_SHARED9_TOG_m33_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart10_ipg_stop_MASK)
21252 
21253 #define CCM_GPR_SHARED9_TOG_m33_lpuart11_ipg_stop_MASK (0x20U)
21254 #define CCM_GPR_SHARED9_TOG_m33_lpuart11_ipg_stop_SHIFT (5U)
21255 /*! m33_lpuart11_ipg_stop - m33_lpuart11_ipg_stop */
21256 #define CCM_GPR_SHARED9_TOG_m33_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart11_ipg_stop_MASK)
21257 
21258 #define CCM_GPR_SHARED9_TOG_m33_lpuart12_ipg_stop_MASK (0x40U)
21259 #define CCM_GPR_SHARED9_TOG_m33_lpuart12_ipg_stop_SHIFT (6U)
21260 /*! m33_lpuart12_ipg_stop - m33_lpuart12_ipg_stop */
21261 #define CCM_GPR_SHARED9_TOG_m33_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpuart12_ipg_stop_MASK)
21262 
21263 #define CCM_GPR_SHARED9_TOG_m33_lpi2c1_ipg_stop_MASK (0x80U)
21264 #define CCM_GPR_SHARED9_TOG_m33_lpi2c1_ipg_stop_SHIFT (7U)
21265 /*! m33_lpi2c1_ipg_stop - m33_lpi2c1_ipg_stop */
21266 #define CCM_GPR_SHARED9_TOG_m33_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c1_ipg_stop_MASK)
21267 
21268 #define CCM_GPR_SHARED9_TOG_m33_lpi2c2_ipg_stop_MASK (0x100U)
21269 #define CCM_GPR_SHARED9_TOG_m33_lpi2c2_ipg_stop_SHIFT (8U)
21270 /*! m33_lpi2c2_ipg_stop - m33_lpi2c2_ipg_stop */
21271 #define CCM_GPR_SHARED9_TOG_m33_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c2_ipg_stop_MASK)
21272 
21273 #define CCM_GPR_SHARED9_TOG_m33_lpi2c3_ipg_stop_MASK (0x200U)
21274 #define CCM_GPR_SHARED9_TOG_m33_lpi2c3_ipg_stop_SHIFT (9U)
21275 /*! m33_lpi2c3_ipg_stop - m33_lpi2c3_ipg_stop */
21276 #define CCM_GPR_SHARED9_TOG_m33_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c3_ipg_stop_MASK)
21277 
21278 #define CCM_GPR_SHARED9_TOG_m33_lpi2c4_ipg_stop_MASK (0x400U)
21279 #define CCM_GPR_SHARED9_TOG_m33_lpi2c4_ipg_stop_SHIFT (10U)
21280 /*! m33_lpi2c4_ipg_stop - m33_lpi2c4_ipg_stop */
21281 #define CCM_GPR_SHARED9_TOG_m33_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c4_ipg_stop_MASK)
21282 
21283 #define CCM_GPR_SHARED9_TOG_m33_lpi2c5_ipg_stop_MASK (0x800U)
21284 #define CCM_GPR_SHARED9_TOG_m33_lpi2c5_ipg_stop_SHIFT (11U)
21285 /*! m33_lpi2c5_ipg_stop - m33_lpi2c5_ipg_stop */
21286 #define CCM_GPR_SHARED9_TOG_m33_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c5_ipg_stop_MASK)
21287 
21288 #define CCM_GPR_SHARED9_TOG_m33_lpi2c6_ipg_stop_MASK (0x1000U)
21289 #define CCM_GPR_SHARED9_TOG_m33_lpi2c6_ipg_stop_SHIFT (12U)
21290 /*! m33_lpi2c6_ipg_stop - m33_lpi2c6_ipg_stop */
21291 #define CCM_GPR_SHARED9_TOG_m33_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpi2c6_ipg_stop_MASK)
21292 
21293 #define CCM_GPR_SHARED9_TOG_m33_lpspi1_ipg_stop_MASK (0x2000U)
21294 #define CCM_GPR_SHARED9_TOG_m33_lpspi1_ipg_stop_SHIFT (13U)
21295 /*! m33_lpspi1_ipg_stop - m33_lpspi1_ipg_stop */
21296 #define CCM_GPR_SHARED9_TOG_m33_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi1_ipg_stop_MASK)
21297 
21298 #define CCM_GPR_SHARED9_TOG_m33_lpspi2_ipg_stop_MASK (0x4000U)
21299 #define CCM_GPR_SHARED9_TOG_m33_lpspi2_ipg_stop_SHIFT (14U)
21300 /*! m33_lpspi2_ipg_stop - m33_lpspi2_ipg_stop */
21301 #define CCM_GPR_SHARED9_TOG_m33_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi2_ipg_stop_MASK)
21302 
21303 #define CCM_GPR_SHARED9_TOG_m33_lpspi3_ipg_stop_MASK (0x8000U)
21304 #define CCM_GPR_SHARED9_TOG_m33_lpspi3_ipg_stop_SHIFT (15U)
21305 /*! m33_lpspi3_ipg_stop - m33_lpspi3_ipg_stop */
21306 #define CCM_GPR_SHARED9_TOG_m33_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi3_ipg_stop_MASK)
21307 
21308 #define CCM_GPR_SHARED9_TOG_m33_lpspi4_ipg_stop_MASK (0x10000U)
21309 #define CCM_GPR_SHARED9_TOG_m33_lpspi4_ipg_stop_SHIFT (16U)
21310 /*! m33_lpspi4_ipg_stop - m33_lpspi4_ipg_stop */
21311 #define CCM_GPR_SHARED9_TOG_m33_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi4_ipg_stop_MASK)
21312 
21313 #define CCM_GPR_SHARED9_TOG_m33_lpspi5_ipg_stop_MASK (0x20000U)
21314 #define CCM_GPR_SHARED9_TOG_m33_lpspi5_ipg_stop_SHIFT (17U)
21315 /*! m33_lpspi5_ipg_stop - m33_lpspi5_ipg_stop */
21316 #define CCM_GPR_SHARED9_TOG_m33_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi5_ipg_stop_MASK)
21317 
21318 #define CCM_GPR_SHARED9_TOG_m33_lpspi6_ipg_stop_MASK (0x40000U)
21319 #define CCM_GPR_SHARED9_TOG_m33_lpspi6_ipg_stop_SHIFT (18U)
21320 /*! m33_lpspi6_ipg_stop - m33_lpspi6_ipg_stop */
21321 #define CCM_GPR_SHARED9_TOG_m33_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_lpspi6_ipg_stop_MASK)
21322 
21323 #define CCM_GPR_SHARED9_TOG_m33_sinc1_ipg_stop_MASK (0x80000U)
21324 #define CCM_GPR_SHARED9_TOG_m33_sinc1_ipg_stop_SHIFT (19U)
21325 /*! m33_sinc1_ipg_stop - m33_sinc1_ipg_stop */
21326 #define CCM_GPR_SHARED9_TOG_m33_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sinc1_ipg_stop_MASK)
21327 
21328 #define CCM_GPR_SHARED9_TOG_m33_sinc2_ipg_stop_MASK (0x100000U)
21329 #define CCM_GPR_SHARED9_TOG_m33_sinc2_ipg_stop_SHIFT (20U)
21330 /*! m33_sinc2_ipg_stop - m33_sinc2_ipg_stop */
21331 #define CCM_GPR_SHARED9_TOG_m33_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sinc2_ipg_stop_MASK)
21332 
21333 #define CCM_GPR_SHARED9_TOG_m33_sinc3_ipg_stop_MASK (0x200000U)
21334 #define CCM_GPR_SHARED9_TOG_m33_sinc3_ipg_stop_SHIFT (21U)
21335 /*! m33_sinc3_ipg_stop - m33_sinc3_ipg_stop */
21336 #define CCM_GPR_SHARED9_TOG_m33_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sinc3_ipg_stop_MASK)
21337 
21338 #define CCM_GPR_SHARED9_TOG_m33_sai1_ipg_stop_MASK (0x400000U)
21339 #define CCM_GPR_SHARED9_TOG_m33_sai1_ipg_stop_SHIFT (22U)
21340 /*! m33_sai1_ipg_stop - m33_sai1_ipg_stop */
21341 #define CCM_GPR_SHARED9_TOG_m33_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sai1_ipg_stop_MASK)
21342 
21343 #define CCM_GPR_SHARED9_TOG_m33_sai2_ipg_stop_MASK (0x800000U)
21344 #define CCM_GPR_SHARED9_TOG_m33_sai2_ipg_stop_SHIFT (23U)
21345 /*! m33_sai2_ipg_stop - m33_sai2_ipg_stop */
21346 #define CCM_GPR_SHARED9_TOG_m33_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sai2_ipg_stop_MASK)
21347 
21348 #define CCM_GPR_SHARED9_TOG_m33_sai3_ipg_stop_MASK (0x1000000U)
21349 #define CCM_GPR_SHARED9_TOG_m33_sai3_ipg_stop_SHIFT (24U)
21350 /*! m33_sai3_ipg_stop - m33_sai3_ipg_stop */
21351 #define CCM_GPR_SHARED9_TOG_m33_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sai3_ipg_stop_MASK)
21352 
21353 #define CCM_GPR_SHARED9_TOG_m33_sai4_ipg_stop_MASK (0x2000000U)
21354 #define CCM_GPR_SHARED9_TOG_m33_sai4_ipg_stop_SHIFT (25U)
21355 /*! m33_sai4_ipg_stop - m33_sai4_ipg_stop */
21356 #define CCM_GPR_SHARED9_TOG_m33_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_sai4_ipg_stop_MASK)
21357 
21358 #define CCM_GPR_SHARED9_TOG_m33_mic_ipg_stop_MASK (0x4000000U)
21359 #define CCM_GPR_SHARED9_TOG_m33_mic_ipg_stop_SHIFT (26U)
21360 /*! m33_mic_ipg_stop - m33_mic_ipg_stop */
21361 #define CCM_GPR_SHARED9_TOG_m33_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_TOG_m33_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED9_TOG_m33_mic_ipg_stop_MASK)
21362 /*! @} */
21363 
21364 /*! @name GPR_SHARED9_AUTHEN - GPR access control */
21365 /*! @{ */
21366 
21367 #define CCM_GPR_SHARED9_AUTHEN_TZ_USER_MASK      (0x100U)
21368 #define CCM_GPR_SHARED9_AUTHEN_TZ_USER_SHIFT     (8U)
21369 /*! TZ_USER - User access permission
21370  *  0b1..Registers of shared GPR slice can be changed in user mode.
21371  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
21372  */
21373 #define CCM_GPR_SHARED9_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TZ_USER_MASK)
21374 
21375 #define CCM_GPR_SHARED9_AUTHEN_TZ_NS_MASK        (0x200U)
21376 #define CCM_GPR_SHARED9_AUTHEN_TZ_NS_SHIFT       (9U)
21377 /*! TZ_NS - Non-secure access permission
21378  *  0b0..Cannot be changed in Non-secure mode.
21379  *  0b1..Can be changed in Non-secure mode.
21380  */
21381 #define CCM_GPR_SHARED9_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TZ_NS_MASK)
21382 
21383 #define CCM_GPR_SHARED9_AUTHEN_LOCK_TZ_MASK      (0x800U)
21384 #define CCM_GPR_SHARED9_AUTHEN_LOCK_TZ_SHIFT     (11U)
21385 /*! LOCK_TZ - Lock TrustZone settings
21386  *  0b0..TrustZone settings is not locked.
21387  *  0b1..TrustZone settings is locked.
21388  */
21389 #define CCM_GPR_SHARED9_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_LOCK_TZ_MASK)
21390 
21391 #define CCM_GPR_SHARED9_AUTHEN_LOCK_LIST_MASK    (0x8000U)
21392 #define CCM_GPR_SHARED9_AUTHEN_LOCK_LIST_SHIFT   (15U)
21393 /*! LOCK_LIST - Lock white list
21394  *  0b0..Whitelist is not locked.
21395  *  0b1..Whitelist is locked.
21396  */
21397 #define CCM_GPR_SHARED9_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_LOCK_LIST_MASK)
21398 
21399 #define CCM_GPR_SHARED9_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
21400 #define CCM_GPR_SHARED9_AUTHEN_WHITE_LIST_SHIFT  (16U)
21401 /*! WHITE_LIST - Whitelist settings */
21402 #define CCM_GPR_SHARED9_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_WHITE_LIST_MASK)
21403 /*! @} */
21404 
21405 /*! @name GPR_SHARED9_AUTHEN_SET - GPR access control */
21406 /*! @{ */
21407 
21408 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_USER_MASK  (0x100U)
21409 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_USER_SHIFT (8U)
21410 /*! TZ_USER - User access permission */
21411 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_SET_TZ_USER_MASK)
21412 
21413 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_NS_MASK    (0x200U)
21414 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_NS_SHIFT   (9U)
21415 /*! TZ_NS - Non-secure access permission */
21416 #define CCM_GPR_SHARED9_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_SET_TZ_NS_MASK)
21417 
21418 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
21419 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
21420 /*! LOCK_TZ - Lock TrustZone settings */
21421 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_SET_LOCK_TZ_MASK)
21422 
21423 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
21424 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
21425 /*! LOCK_LIST - Lock white list */
21426 #define CCM_GPR_SHARED9_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_SET_LOCK_LIST_MASK)
21427 
21428 #define CCM_GPR_SHARED9_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
21429 #define CCM_GPR_SHARED9_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
21430 /*! WHITE_LIST - Whitelist settings */
21431 #define CCM_GPR_SHARED9_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_SET_WHITE_LIST_MASK)
21432 /*! @} */
21433 
21434 /*! @name GPR_SHARED9_AUTHEN_CLR - GPR access control */
21435 /*! @{ */
21436 
21437 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
21438 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_USER_SHIFT (8U)
21439 /*! TZ_USER - User access permission */
21440 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_CLR_TZ_USER_MASK)
21441 
21442 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
21443 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
21444 /*! TZ_NS - Non-secure access permission */
21445 #define CCM_GPR_SHARED9_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_CLR_TZ_NS_MASK)
21446 
21447 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
21448 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
21449 /*! LOCK_TZ - Lock TrustZone settings */
21450 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_TZ_MASK)
21451 
21452 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
21453 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
21454 /*! LOCK_LIST - Lock white list */
21455 #define CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_CLR_LOCK_LIST_MASK)
21456 
21457 #define CCM_GPR_SHARED9_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
21458 #define CCM_GPR_SHARED9_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
21459 /*! WHITE_LIST - Whitelist settings */
21460 #define CCM_GPR_SHARED9_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_CLR_WHITE_LIST_MASK)
21461 /*! @} */
21462 
21463 /*! @name GPR_SHARED9_AUTHEN_TOG - GPR access control */
21464 /*! @{ */
21465 
21466 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
21467 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_USER_SHIFT (8U)
21468 /*! TZ_USER - User access permission */
21469 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TOG_TZ_USER_MASK)
21470 
21471 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
21472 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
21473 /*! TZ_NS - Non-secure access permission */
21474 #define CCM_GPR_SHARED9_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TOG_TZ_NS_MASK)
21475 
21476 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
21477 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
21478 /*! LOCK_TZ - Lock TrustZone settings */
21479 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_TZ_MASK)
21480 
21481 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
21482 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
21483 /*! LOCK_LIST - Lock white list */
21484 #define CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TOG_LOCK_LIST_MASK)
21485 
21486 #define CCM_GPR_SHARED9_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
21487 #define CCM_GPR_SHARED9_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
21488 /*! WHITE_LIST - Whitelist settings */
21489 #define CCM_GPR_SHARED9_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED9_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED9_AUTHEN_TOG_WHITE_LIST_MASK)
21490 /*! @} */
21491 
21492 /*! @name GPR_SHARED10 - General Purpose Register */
21493 /*! @{ */
21494 
21495 #define CCM_GPR_SHARED10_m33_adc1_ipg_doze_MASK  (0x1U)
21496 #define CCM_GPR_SHARED10_m33_adc1_ipg_doze_SHIFT (0U)
21497 /*! m33_adc1_ipg_doze - m33_adc1_ipg_doze */
21498 #define CCM_GPR_SHARED10_m33_adc1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_adc1_ipg_doze_MASK)
21499 
21500 #define CCM_GPR_SHARED10_m33_adc2_ipg_doze_MASK  (0x2U)
21501 #define CCM_GPR_SHARED10_m33_adc2_ipg_doze_SHIFT (1U)
21502 /*! m33_adc2_ipg_doze - m33_adc2_ipg_doze */
21503 #define CCM_GPR_SHARED10_m33_adc2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_adc2_ipg_doze_MASK)
21504 
21505 #define CCM_GPR_SHARED10_m33_flexspi1_ipg_doze_MASK (0x4U)
21506 #define CCM_GPR_SHARED10_m33_flexspi1_ipg_doze_SHIFT (2U)
21507 /*! m33_flexspi1_ipg_doze - m33_flexspi1_ipg_doze */
21508 #define CCM_GPR_SHARED10_m33_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_flexspi1_ipg_doze_MASK)
21509 
21510 #define CCM_GPR_SHARED10_m33_flexspi2_ipg_doze_MASK (0x8U)
21511 #define CCM_GPR_SHARED10_m33_flexspi2_ipg_doze_SHIFT (3U)
21512 /*! m33_flexspi2_ipg_doze - m33_flexspi2_ipg_doze */
21513 #define CCM_GPR_SHARED10_m33_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_flexspi2_ipg_doze_MASK)
21514 
21515 #define CCM_GPR_SHARED10_m33_flexio1_ipg_doze_MASK (0x10U)
21516 #define CCM_GPR_SHARED10_m33_flexio1_ipg_doze_SHIFT (4U)
21517 /*! m33_flexio1_ipg_doze - m33_flexio1_ipg_doze */
21518 #define CCM_GPR_SHARED10_m33_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_flexio1_ipg_doze_MASK)
21519 
21520 #define CCM_GPR_SHARED10_m33_flexio2_ipg_doze_MASK (0x20U)
21521 #define CCM_GPR_SHARED10_m33_flexio2_ipg_doze_SHIFT (5U)
21522 /*! m33_flexio2_ipg_doze - m33_flexio2_ipg_doze */
21523 #define CCM_GPR_SHARED10_m33_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_flexio2_ipg_doze_MASK)
21524 
21525 #define CCM_GPR_SHARED10_m33_lpit1_ipg_doze_MASK (0x40U)
21526 #define CCM_GPR_SHARED10_m33_lpit1_ipg_doze_SHIFT (6U)
21527 /*! m33_lpit1_ipg_doze - m33_lpit1_ipg_doze */
21528 #define CCM_GPR_SHARED10_m33_lpit1_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpit1_ipg_doze_MASK)
21529 
21530 #define CCM_GPR_SHARED10_m33_lpit2_ipg_doze_MASK (0x80U)
21531 #define CCM_GPR_SHARED10_m33_lpit2_ipg_doze_SHIFT (7U)
21532 /*! m33_lpit2_ipg_doze - m33_lpit2_ipg_doze */
21533 #define CCM_GPR_SHARED10_m33_lpit2_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpit2_ipg_doze_MASK)
21534 
21535 #define CCM_GPR_SHARED10_m33_lpit3_ipg_doze_MASK (0x100U)
21536 #define CCM_GPR_SHARED10_m33_lpit3_ipg_doze_SHIFT (8U)
21537 /*! m33_lpit3_ipg_doze - m33_lpit3_ipg_doze */
21538 #define CCM_GPR_SHARED10_m33_lpit3_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpit3_ipg_doze_MASK)
21539 
21540 #define CCM_GPR_SHARED10_m33_tpm1_ipg_doze_MASK  (0x200U)
21541 #define CCM_GPR_SHARED10_m33_tpm1_ipg_doze_SHIFT (9U)
21542 /*! m33_tpm1_ipg_doze - m33_tpm1_ipg_doze */
21543 #define CCM_GPR_SHARED10_m33_tpm1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm1_ipg_doze_MASK)
21544 
21545 #define CCM_GPR_SHARED10_m33_tpm2_ipg_doze_MASK  (0x400U)
21546 #define CCM_GPR_SHARED10_m33_tpm2_ipg_doze_SHIFT (10U)
21547 /*! m33_tpm2_ipg_doze - m33_tpm2_ipg_doze */
21548 #define CCM_GPR_SHARED10_m33_tpm2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm2_ipg_doze_MASK)
21549 
21550 #define CCM_GPR_SHARED10_m33_tpm3_ipg_doze_MASK  (0x800U)
21551 #define CCM_GPR_SHARED10_m33_tpm3_ipg_doze_SHIFT (11U)
21552 /*! m33_tpm3_ipg_doze - m33_tpm3_ipg_doze */
21553 #define CCM_GPR_SHARED10_m33_tpm3_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm3_ipg_doze_MASK)
21554 
21555 #define CCM_GPR_SHARED10_m33_tpm4_ipg_doze_MASK  (0x1000U)
21556 #define CCM_GPR_SHARED10_m33_tpm4_ipg_doze_SHIFT (12U)
21557 /*! m33_tpm4_ipg_doze - m33_tpm4_ipg_doze */
21558 #define CCM_GPR_SHARED10_m33_tpm4_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm4_ipg_doze_MASK)
21559 
21560 #define CCM_GPR_SHARED10_m33_tpm5_ipg_doze_MASK  (0x2000U)
21561 #define CCM_GPR_SHARED10_m33_tpm5_ipg_doze_SHIFT (13U)
21562 /*! m33_tpm5_ipg_doze - m33_tpm5_ipg_doze */
21563 #define CCM_GPR_SHARED10_m33_tpm5_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm5_ipg_doze_MASK)
21564 
21565 #define CCM_GPR_SHARED10_m33_tpm6_ipg_doze_MASK  (0x4000U)
21566 #define CCM_GPR_SHARED10_m33_tpm6_ipg_doze_SHIFT (14U)
21567 /*! m33_tpm6_ipg_doze - m33_tpm6_ipg_doze */
21568 #define CCM_GPR_SHARED10_m33_tpm6_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_tpm6_ipg_doze_MASK)
21569 
21570 #define CCM_GPR_SHARED10_m33_gpt1_ipg_doze_MASK  (0x8000U)
21571 #define CCM_GPR_SHARED10_m33_gpt1_ipg_doze_SHIFT (15U)
21572 /*! m33_gpt1_ipg_doze - m33_gpt1_ipg_doze */
21573 #define CCM_GPR_SHARED10_m33_gpt1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_gpt1_ipg_doze_MASK)
21574 
21575 #define CCM_GPR_SHARED10_m33_gpt2_ipg_doze_MASK  (0x10000U)
21576 #define CCM_GPR_SHARED10_m33_gpt2_ipg_doze_SHIFT (16U)
21577 /*! m33_gpt2_ipg_doze - m33_gpt2_ipg_doze */
21578 #define CCM_GPR_SHARED10_m33_gpt2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_gpt2_ipg_doze_MASK)
21579 
21580 #define CCM_GPR_SHARED10_m33_can1_ipg_doze_MASK  (0x20000U)
21581 #define CCM_GPR_SHARED10_m33_can1_ipg_doze_SHIFT (17U)
21582 /*! m33_can1_ipg_doze - m33_can1_ipg_doze */
21583 #define CCM_GPR_SHARED10_m33_can1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_can1_ipg_doze_MASK)
21584 
21585 #define CCM_GPR_SHARED10_m33_can2_ipg_doze_MASK  (0x40000U)
21586 #define CCM_GPR_SHARED10_m33_can2_ipg_doze_SHIFT (18U)
21587 /*! m33_can2_ipg_doze - m33_can2_ipg_doze */
21588 #define CCM_GPR_SHARED10_m33_can2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_can2_ipg_doze_MASK)
21589 
21590 #define CCM_GPR_SHARED10_m33_can3_ipg_doze_MASK  (0x80000U)
21591 #define CCM_GPR_SHARED10_m33_can3_ipg_doze_SHIFT (19U)
21592 /*! m33_can3_ipg_doze - m33_can3_ipg_doze */
21593 #define CCM_GPR_SHARED10_m33_can3_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_can3_ipg_doze_MASK)
21594 
21595 #define CCM_GPR_SHARED10_m33_lpuart1_ipg_doze_MASK (0x100000U)
21596 #define CCM_GPR_SHARED10_m33_lpuart1_ipg_doze_SHIFT (20U)
21597 /*! m33_lpuart1_ipg_doze - m33_lpuart1_ipg_doze */
21598 #define CCM_GPR_SHARED10_m33_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart1_ipg_doze_MASK)
21599 
21600 #define CCM_GPR_SHARED10_m33_lpuart2_ipg_doze_MASK (0x200000U)
21601 #define CCM_GPR_SHARED10_m33_lpuart2_ipg_doze_SHIFT (21U)
21602 /*! m33_lpuart2_ipg_doze - m33_lpuart2_ipg_doze */
21603 #define CCM_GPR_SHARED10_m33_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart2_ipg_doze_MASK)
21604 
21605 #define CCM_GPR_SHARED10_m33_lpuart3_ipg_doze_MASK (0x400000U)
21606 #define CCM_GPR_SHARED10_m33_lpuart3_ipg_doze_SHIFT (22U)
21607 /*! m33_lpuart3_ipg_doze - m33_lpuart3_ipg_doze */
21608 #define CCM_GPR_SHARED10_m33_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart3_ipg_doze_MASK)
21609 
21610 #define CCM_GPR_SHARED10_m33_lpuart4_ipg_doze_MASK (0x800000U)
21611 #define CCM_GPR_SHARED10_m33_lpuart4_ipg_doze_SHIFT (23U)
21612 /*! m33_lpuart4_ipg_doze - m33_lpuart4_ipg_doze */
21613 #define CCM_GPR_SHARED10_m33_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart4_ipg_doze_MASK)
21614 
21615 #define CCM_GPR_SHARED10_m33_lpuart5_ipg_doze_MASK (0x1000000U)
21616 #define CCM_GPR_SHARED10_m33_lpuart5_ipg_doze_SHIFT (24U)
21617 /*! m33_lpuart5_ipg_doze - m33_lpuart5_ipg_doze */
21618 #define CCM_GPR_SHARED10_m33_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart5_ipg_doze_MASK)
21619 
21620 #define CCM_GPR_SHARED10_m33_lpuart6_ipg_doze_MASK (0x2000000U)
21621 #define CCM_GPR_SHARED10_m33_lpuart6_ipg_doze_SHIFT (25U)
21622 /*! m33_lpuart6_ipg_doze - m33_lpuart6_ipg_doze */
21623 #define CCM_GPR_SHARED10_m33_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart6_ipg_doze_MASK)
21624 
21625 #define CCM_GPR_SHARED10_m33_lpuart7_ipg_doze_MASK (0x4000000U)
21626 #define CCM_GPR_SHARED10_m33_lpuart7_ipg_doze_SHIFT (26U)
21627 /*! m33_lpuart7_ipg_doze - m33_lpuart7_ipg_doze */
21628 #define CCM_GPR_SHARED10_m33_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart7_ipg_doze_MASK)
21629 
21630 #define CCM_GPR_SHARED10_m33_lpuart8_ipg_doze_MASK (0x8000000U)
21631 #define CCM_GPR_SHARED10_m33_lpuart8_ipg_doze_SHIFT (27U)
21632 /*! m33_lpuart8_ipg_doze - m33_lpuart8_ipg_doze */
21633 #define CCM_GPR_SHARED10_m33_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart8_ipg_doze_MASK)
21634 
21635 #define CCM_GPR_SHARED10_m33_lpuart9_ipg_doze_MASK (0x10000000U)
21636 #define CCM_GPR_SHARED10_m33_lpuart9_ipg_doze_SHIFT (28U)
21637 /*! m33_lpuart9_ipg_doze - m33_lpuart9_ipg_doze */
21638 #define CCM_GPR_SHARED10_m33_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart9_ipg_doze_MASK)
21639 
21640 #define CCM_GPR_SHARED10_m33_lpuart10_ipg_doze_MASK (0x20000000U)
21641 #define CCM_GPR_SHARED10_m33_lpuart10_ipg_doze_SHIFT (29U)
21642 /*! m33_lpuart10_ipg_doze - m33_lpuart10_ipg_doze */
21643 #define CCM_GPR_SHARED10_m33_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart10_ipg_doze_MASK)
21644 
21645 #define CCM_GPR_SHARED10_m33_lpuart11_ipg_doze_MASK (0x40000000U)
21646 #define CCM_GPR_SHARED10_m33_lpuart11_ipg_doze_SHIFT (30U)
21647 /*! m33_lpuart11_ipg_doze - m33_lpuart11_ipg_doze */
21648 #define CCM_GPR_SHARED10_m33_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart11_ipg_doze_MASK)
21649 
21650 #define CCM_GPR_SHARED10_m33_lpuart12_ipg_doze_MASK (0x80000000U)
21651 #define CCM_GPR_SHARED10_m33_lpuart12_ipg_doze_SHIFT (31U)
21652 /*! m33_lpuart12_ipg_doze - m33_lpuart12_ipg_doze */
21653 #define CCM_GPR_SHARED10_m33_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_m33_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_m33_lpuart12_ipg_doze_MASK)
21654 /*! @} */
21655 
21656 /*! @name GPR_SHARED10_SET - General Purpose Register */
21657 /*! @{ */
21658 
21659 #define CCM_GPR_SHARED10_SET_m33_adc1_ipg_doze_MASK (0x1U)
21660 #define CCM_GPR_SHARED10_SET_m33_adc1_ipg_doze_SHIFT (0U)
21661 /*! m33_adc1_ipg_doze - m33_adc1_ipg_doze */
21662 #define CCM_GPR_SHARED10_SET_m33_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_adc1_ipg_doze_MASK)
21663 
21664 #define CCM_GPR_SHARED10_SET_m33_adc2_ipg_doze_MASK (0x2U)
21665 #define CCM_GPR_SHARED10_SET_m33_adc2_ipg_doze_SHIFT (1U)
21666 /*! m33_adc2_ipg_doze - m33_adc2_ipg_doze */
21667 #define CCM_GPR_SHARED10_SET_m33_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_adc2_ipg_doze_MASK)
21668 
21669 #define CCM_GPR_SHARED10_SET_m33_flexspi1_ipg_doze_MASK (0x4U)
21670 #define CCM_GPR_SHARED10_SET_m33_flexspi1_ipg_doze_SHIFT (2U)
21671 /*! m33_flexspi1_ipg_doze - m33_flexspi1_ipg_doze */
21672 #define CCM_GPR_SHARED10_SET_m33_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_flexspi1_ipg_doze_MASK)
21673 
21674 #define CCM_GPR_SHARED10_SET_m33_flexspi2_ipg_doze_MASK (0x8U)
21675 #define CCM_GPR_SHARED10_SET_m33_flexspi2_ipg_doze_SHIFT (3U)
21676 /*! m33_flexspi2_ipg_doze - m33_flexspi2_ipg_doze */
21677 #define CCM_GPR_SHARED10_SET_m33_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_flexspi2_ipg_doze_MASK)
21678 
21679 #define CCM_GPR_SHARED10_SET_m33_flexio1_ipg_doze_MASK (0x10U)
21680 #define CCM_GPR_SHARED10_SET_m33_flexio1_ipg_doze_SHIFT (4U)
21681 /*! m33_flexio1_ipg_doze - m33_flexio1_ipg_doze */
21682 #define CCM_GPR_SHARED10_SET_m33_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_flexio1_ipg_doze_MASK)
21683 
21684 #define CCM_GPR_SHARED10_SET_m33_flexio2_ipg_doze_MASK (0x20U)
21685 #define CCM_GPR_SHARED10_SET_m33_flexio2_ipg_doze_SHIFT (5U)
21686 /*! m33_flexio2_ipg_doze - m33_flexio2_ipg_doze */
21687 #define CCM_GPR_SHARED10_SET_m33_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_flexio2_ipg_doze_MASK)
21688 
21689 #define CCM_GPR_SHARED10_SET_m33_lpit1_ipg_doze_MASK (0x40U)
21690 #define CCM_GPR_SHARED10_SET_m33_lpit1_ipg_doze_SHIFT (6U)
21691 /*! m33_lpit1_ipg_doze - m33_lpit1_ipg_doze */
21692 #define CCM_GPR_SHARED10_SET_m33_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpit1_ipg_doze_MASK)
21693 
21694 #define CCM_GPR_SHARED10_SET_m33_lpit2_ipg_doze_MASK (0x80U)
21695 #define CCM_GPR_SHARED10_SET_m33_lpit2_ipg_doze_SHIFT (7U)
21696 /*! m33_lpit2_ipg_doze - m33_lpit2_ipg_doze */
21697 #define CCM_GPR_SHARED10_SET_m33_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpit2_ipg_doze_MASK)
21698 
21699 #define CCM_GPR_SHARED10_SET_m33_lpit3_ipg_doze_MASK (0x100U)
21700 #define CCM_GPR_SHARED10_SET_m33_lpit3_ipg_doze_SHIFT (8U)
21701 /*! m33_lpit3_ipg_doze - m33_lpit3_ipg_doze */
21702 #define CCM_GPR_SHARED10_SET_m33_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpit3_ipg_doze_MASK)
21703 
21704 #define CCM_GPR_SHARED10_SET_m33_tpm1_ipg_doze_MASK (0x200U)
21705 #define CCM_GPR_SHARED10_SET_m33_tpm1_ipg_doze_SHIFT (9U)
21706 /*! m33_tpm1_ipg_doze - m33_tpm1_ipg_doze */
21707 #define CCM_GPR_SHARED10_SET_m33_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm1_ipg_doze_MASK)
21708 
21709 #define CCM_GPR_SHARED10_SET_m33_tpm2_ipg_doze_MASK (0x400U)
21710 #define CCM_GPR_SHARED10_SET_m33_tpm2_ipg_doze_SHIFT (10U)
21711 /*! m33_tpm2_ipg_doze - m33_tpm2_ipg_doze */
21712 #define CCM_GPR_SHARED10_SET_m33_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm2_ipg_doze_MASK)
21713 
21714 #define CCM_GPR_SHARED10_SET_m33_tpm3_ipg_doze_MASK (0x800U)
21715 #define CCM_GPR_SHARED10_SET_m33_tpm3_ipg_doze_SHIFT (11U)
21716 /*! m33_tpm3_ipg_doze - m33_tpm3_ipg_doze */
21717 #define CCM_GPR_SHARED10_SET_m33_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm3_ipg_doze_MASK)
21718 
21719 #define CCM_GPR_SHARED10_SET_m33_tpm4_ipg_doze_MASK (0x1000U)
21720 #define CCM_GPR_SHARED10_SET_m33_tpm4_ipg_doze_SHIFT (12U)
21721 /*! m33_tpm4_ipg_doze - m33_tpm4_ipg_doze */
21722 #define CCM_GPR_SHARED10_SET_m33_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm4_ipg_doze_MASK)
21723 
21724 #define CCM_GPR_SHARED10_SET_m33_tpm5_ipg_doze_MASK (0x2000U)
21725 #define CCM_GPR_SHARED10_SET_m33_tpm5_ipg_doze_SHIFT (13U)
21726 /*! m33_tpm5_ipg_doze - m33_tpm5_ipg_doze */
21727 #define CCM_GPR_SHARED10_SET_m33_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm5_ipg_doze_MASK)
21728 
21729 #define CCM_GPR_SHARED10_SET_m33_tpm6_ipg_doze_MASK (0x4000U)
21730 #define CCM_GPR_SHARED10_SET_m33_tpm6_ipg_doze_SHIFT (14U)
21731 /*! m33_tpm6_ipg_doze - m33_tpm6_ipg_doze */
21732 #define CCM_GPR_SHARED10_SET_m33_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_tpm6_ipg_doze_MASK)
21733 
21734 #define CCM_GPR_SHARED10_SET_m33_gpt1_ipg_doze_MASK (0x8000U)
21735 #define CCM_GPR_SHARED10_SET_m33_gpt1_ipg_doze_SHIFT (15U)
21736 /*! m33_gpt1_ipg_doze - m33_gpt1_ipg_doze */
21737 #define CCM_GPR_SHARED10_SET_m33_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_gpt1_ipg_doze_MASK)
21738 
21739 #define CCM_GPR_SHARED10_SET_m33_gpt2_ipg_doze_MASK (0x10000U)
21740 #define CCM_GPR_SHARED10_SET_m33_gpt2_ipg_doze_SHIFT (16U)
21741 /*! m33_gpt2_ipg_doze - m33_gpt2_ipg_doze */
21742 #define CCM_GPR_SHARED10_SET_m33_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_gpt2_ipg_doze_MASK)
21743 
21744 #define CCM_GPR_SHARED10_SET_m33_can1_ipg_doze_MASK (0x20000U)
21745 #define CCM_GPR_SHARED10_SET_m33_can1_ipg_doze_SHIFT (17U)
21746 /*! m33_can1_ipg_doze - m33_can1_ipg_doze */
21747 #define CCM_GPR_SHARED10_SET_m33_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_can1_ipg_doze_MASK)
21748 
21749 #define CCM_GPR_SHARED10_SET_m33_can2_ipg_doze_MASK (0x40000U)
21750 #define CCM_GPR_SHARED10_SET_m33_can2_ipg_doze_SHIFT (18U)
21751 /*! m33_can2_ipg_doze - m33_can2_ipg_doze */
21752 #define CCM_GPR_SHARED10_SET_m33_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_can2_ipg_doze_MASK)
21753 
21754 #define CCM_GPR_SHARED10_SET_m33_can3_ipg_doze_MASK (0x80000U)
21755 #define CCM_GPR_SHARED10_SET_m33_can3_ipg_doze_SHIFT (19U)
21756 /*! m33_can3_ipg_doze - m33_can3_ipg_doze */
21757 #define CCM_GPR_SHARED10_SET_m33_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_can3_ipg_doze_MASK)
21758 
21759 #define CCM_GPR_SHARED10_SET_m33_lpuart1_ipg_doze_MASK (0x100000U)
21760 #define CCM_GPR_SHARED10_SET_m33_lpuart1_ipg_doze_SHIFT (20U)
21761 /*! m33_lpuart1_ipg_doze - m33_lpuart1_ipg_doze */
21762 #define CCM_GPR_SHARED10_SET_m33_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart1_ipg_doze_MASK)
21763 
21764 #define CCM_GPR_SHARED10_SET_m33_lpuart2_ipg_doze_MASK (0x200000U)
21765 #define CCM_GPR_SHARED10_SET_m33_lpuart2_ipg_doze_SHIFT (21U)
21766 /*! m33_lpuart2_ipg_doze - m33_lpuart2_ipg_doze */
21767 #define CCM_GPR_SHARED10_SET_m33_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart2_ipg_doze_MASK)
21768 
21769 #define CCM_GPR_SHARED10_SET_m33_lpuart3_ipg_doze_MASK (0x400000U)
21770 #define CCM_GPR_SHARED10_SET_m33_lpuart3_ipg_doze_SHIFT (22U)
21771 /*! m33_lpuart3_ipg_doze - m33_lpuart3_ipg_doze */
21772 #define CCM_GPR_SHARED10_SET_m33_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart3_ipg_doze_MASK)
21773 
21774 #define CCM_GPR_SHARED10_SET_m33_lpuart4_ipg_doze_MASK (0x800000U)
21775 #define CCM_GPR_SHARED10_SET_m33_lpuart4_ipg_doze_SHIFT (23U)
21776 /*! m33_lpuart4_ipg_doze - m33_lpuart4_ipg_doze */
21777 #define CCM_GPR_SHARED10_SET_m33_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart4_ipg_doze_MASK)
21778 
21779 #define CCM_GPR_SHARED10_SET_m33_lpuart5_ipg_doze_MASK (0x1000000U)
21780 #define CCM_GPR_SHARED10_SET_m33_lpuart5_ipg_doze_SHIFT (24U)
21781 /*! m33_lpuart5_ipg_doze - m33_lpuart5_ipg_doze */
21782 #define CCM_GPR_SHARED10_SET_m33_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart5_ipg_doze_MASK)
21783 
21784 #define CCM_GPR_SHARED10_SET_m33_lpuart6_ipg_doze_MASK (0x2000000U)
21785 #define CCM_GPR_SHARED10_SET_m33_lpuart6_ipg_doze_SHIFT (25U)
21786 /*! m33_lpuart6_ipg_doze - m33_lpuart6_ipg_doze */
21787 #define CCM_GPR_SHARED10_SET_m33_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart6_ipg_doze_MASK)
21788 
21789 #define CCM_GPR_SHARED10_SET_m33_lpuart7_ipg_doze_MASK (0x4000000U)
21790 #define CCM_GPR_SHARED10_SET_m33_lpuart7_ipg_doze_SHIFT (26U)
21791 /*! m33_lpuart7_ipg_doze - m33_lpuart7_ipg_doze */
21792 #define CCM_GPR_SHARED10_SET_m33_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart7_ipg_doze_MASK)
21793 
21794 #define CCM_GPR_SHARED10_SET_m33_lpuart8_ipg_doze_MASK (0x8000000U)
21795 #define CCM_GPR_SHARED10_SET_m33_lpuart8_ipg_doze_SHIFT (27U)
21796 /*! m33_lpuart8_ipg_doze - m33_lpuart8_ipg_doze */
21797 #define CCM_GPR_SHARED10_SET_m33_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart8_ipg_doze_MASK)
21798 
21799 #define CCM_GPR_SHARED10_SET_m33_lpuart9_ipg_doze_MASK (0x10000000U)
21800 #define CCM_GPR_SHARED10_SET_m33_lpuart9_ipg_doze_SHIFT (28U)
21801 /*! m33_lpuart9_ipg_doze - m33_lpuart9_ipg_doze */
21802 #define CCM_GPR_SHARED10_SET_m33_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart9_ipg_doze_MASK)
21803 
21804 #define CCM_GPR_SHARED10_SET_m33_lpuart10_ipg_doze_MASK (0x20000000U)
21805 #define CCM_GPR_SHARED10_SET_m33_lpuart10_ipg_doze_SHIFT (29U)
21806 /*! m33_lpuart10_ipg_doze - m33_lpuart10_ipg_doze */
21807 #define CCM_GPR_SHARED10_SET_m33_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart10_ipg_doze_MASK)
21808 
21809 #define CCM_GPR_SHARED10_SET_m33_lpuart11_ipg_doze_MASK (0x40000000U)
21810 #define CCM_GPR_SHARED10_SET_m33_lpuart11_ipg_doze_SHIFT (30U)
21811 /*! m33_lpuart11_ipg_doze - m33_lpuart11_ipg_doze */
21812 #define CCM_GPR_SHARED10_SET_m33_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart11_ipg_doze_MASK)
21813 
21814 #define CCM_GPR_SHARED10_SET_m33_lpuart12_ipg_doze_MASK (0x80000000U)
21815 #define CCM_GPR_SHARED10_SET_m33_lpuart12_ipg_doze_SHIFT (31U)
21816 /*! m33_lpuart12_ipg_doze - m33_lpuart12_ipg_doze */
21817 #define CCM_GPR_SHARED10_SET_m33_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_SET_m33_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_SET_m33_lpuart12_ipg_doze_MASK)
21818 /*! @} */
21819 
21820 /*! @name GPR_SHARED10_CLR - General Purpose Register */
21821 /*! @{ */
21822 
21823 #define CCM_GPR_SHARED10_CLR_m33_adc1_ipg_doze_MASK (0x1U)
21824 #define CCM_GPR_SHARED10_CLR_m33_adc1_ipg_doze_SHIFT (0U)
21825 /*! m33_adc1_ipg_doze - m33_adc1_ipg_doze */
21826 #define CCM_GPR_SHARED10_CLR_m33_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_adc1_ipg_doze_MASK)
21827 
21828 #define CCM_GPR_SHARED10_CLR_m33_adc2_ipg_doze_MASK (0x2U)
21829 #define CCM_GPR_SHARED10_CLR_m33_adc2_ipg_doze_SHIFT (1U)
21830 /*! m33_adc2_ipg_doze - m33_adc2_ipg_doze */
21831 #define CCM_GPR_SHARED10_CLR_m33_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_adc2_ipg_doze_MASK)
21832 
21833 #define CCM_GPR_SHARED10_CLR_m33_flexspi1_ipg_doze_MASK (0x4U)
21834 #define CCM_GPR_SHARED10_CLR_m33_flexspi1_ipg_doze_SHIFT (2U)
21835 /*! m33_flexspi1_ipg_doze - m33_flexspi1_ipg_doze */
21836 #define CCM_GPR_SHARED10_CLR_m33_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_flexspi1_ipg_doze_MASK)
21837 
21838 #define CCM_GPR_SHARED10_CLR_m33_flexspi2_ipg_doze_MASK (0x8U)
21839 #define CCM_GPR_SHARED10_CLR_m33_flexspi2_ipg_doze_SHIFT (3U)
21840 /*! m33_flexspi2_ipg_doze - m33_flexspi2_ipg_doze */
21841 #define CCM_GPR_SHARED10_CLR_m33_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_flexspi2_ipg_doze_MASK)
21842 
21843 #define CCM_GPR_SHARED10_CLR_m33_flexio1_ipg_doze_MASK (0x10U)
21844 #define CCM_GPR_SHARED10_CLR_m33_flexio1_ipg_doze_SHIFT (4U)
21845 /*! m33_flexio1_ipg_doze - m33_flexio1_ipg_doze */
21846 #define CCM_GPR_SHARED10_CLR_m33_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_flexio1_ipg_doze_MASK)
21847 
21848 #define CCM_GPR_SHARED10_CLR_m33_flexio2_ipg_doze_MASK (0x20U)
21849 #define CCM_GPR_SHARED10_CLR_m33_flexio2_ipg_doze_SHIFT (5U)
21850 /*! m33_flexio2_ipg_doze - m33_flexio2_ipg_doze */
21851 #define CCM_GPR_SHARED10_CLR_m33_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_flexio2_ipg_doze_MASK)
21852 
21853 #define CCM_GPR_SHARED10_CLR_m33_lpit1_ipg_doze_MASK (0x40U)
21854 #define CCM_GPR_SHARED10_CLR_m33_lpit1_ipg_doze_SHIFT (6U)
21855 /*! m33_lpit1_ipg_doze - m33_lpit1_ipg_doze */
21856 #define CCM_GPR_SHARED10_CLR_m33_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpit1_ipg_doze_MASK)
21857 
21858 #define CCM_GPR_SHARED10_CLR_m33_lpit2_ipg_doze_MASK (0x80U)
21859 #define CCM_GPR_SHARED10_CLR_m33_lpit2_ipg_doze_SHIFT (7U)
21860 /*! m33_lpit2_ipg_doze - m33_lpit2_ipg_doze */
21861 #define CCM_GPR_SHARED10_CLR_m33_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpit2_ipg_doze_MASK)
21862 
21863 #define CCM_GPR_SHARED10_CLR_m33_lpit3_ipg_doze_MASK (0x100U)
21864 #define CCM_GPR_SHARED10_CLR_m33_lpit3_ipg_doze_SHIFT (8U)
21865 /*! m33_lpit3_ipg_doze - m33_lpit3_ipg_doze */
21866 #define CCM_GPR_SHARED10_CLR_m33_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpit3_ipg_doze_MASK)
21867 
21868 #define CCM_GPR_SHARED10_CLR_m33_tpm1_ipg_doze_MASK (0x200U)
21869 #define CCM_GPR_SHARED10_CLR_m33_tpm1_ipg_doze_SHIFT (9U)
21870 /*! m33_tpm1_ipg_doze - m33_tpm1_ipg_doze */
21871 #define CCM_GPR_SHARED10_CLR_m33_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm1_ipg_doze_MASK)
21872 
21873 #define CCM_GPR_SHARED10_CLR_m33_tpm2_ipg_doze_MASK (0x400U)
21874 #define CCM_GPR_SHARED10_CLR_m33_tpm2_ipg_doze_SHIFT (10U)
21875 /*! m33_tpm2_ipg_doze - m33_tpm2_ipg_doze */
21876 #define CCM_GPR_SHARED10_CLR_m33_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm2_ipg_doze_MASK)
21877 
21878 #define CCM_GPR_SHARED10_CLR_m33_tpm3_ipg_doze_MASK (0x800U)
21879 #define CCM_GPR_SHARED10_CLR_m33_tpm3_ipg_doze_SHIFT (11U)
21880 /*! m33_tpm3_ipg_doze - m33_tpm3_ipg_doze */
21881 #define CCM_GPR_SHARED10_CLR_m33_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm3_ipg_doze_MASK)
21882 
21883 #define CCM_GPR_SHARED10_CLR_m33_tpm4_ipg_doze_MASK (0x1000U)
21884 #define CCM_GPR_SHARED10_CLR_m33_tpm4_ipg_doze_SHIFT (12U)
21885 /*! m33_tpm4_ipg_doze - m33_tpm4_ipg_doze */
21886 #define CCM_GPR_SHARED10_CLR_m33_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm4_ipg_doze_MASK)
21887 
21888 #define CCM_GPR_SHARED10_CLR_m33_tpm5_ipg_doze_MASK (0x2000U)
21889 #define CCM_GPR_SHARED10_CLR_m33_tpm5_ipg_doze_SHIFT (13U)
21890 /*! m33_tpm5_ipg_doze - m33_tpm5_ipg_doze */
21891 #define CCM_GPR_SHARED10_CLR_m33_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm5_ipg_doze_MASK)
21892 
21893 #define CCM_GPR_SHARED10_CLR_m33_tpm6_ipg_doze_MASK (0x4000U)
21894 #define CCM_GPR_SHARED10_CLR_m33_tpm6_ipg_doze_SHIFT (14U)
21895 /*! m33_tpm6_ipg_doze - m33_tpm6_ipg_doze */
21896 #define CCM_GPR_SHARED10_CLR_m33_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_tpm6_ipg_doze_MASK)
21897 
21898 #define CCM_GPR_SHARED10_CLR_m33_gpt1_ipg_doze_MASK (0x8000U)
21899 #define CCM_GPR_SHARED10_CLR_m33_gpt1_ipg_doze_SHIFT (15U)
21900 /*! m33_gpt1_ipg_doze - m33_gpt1_ipg_doze */
21901 #define CCM_GPR_SHARED10_CLR_m33_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_gpt1_ipg_doze_MASK)
21902 
21903 #define CCM_GPR_SHARED10_CLR_m33_gpt2_ipg_doze_MASK (0x10000U)
21904 #define CCM_GPR_SHARED10_CLR_m33_gpt2_ipg_doze_SHIFT (16U)
21905 /*! m33_gpt2_ipg_doze - m33_gpt2_ipg_doze */
21906 #define CCM_GPR_SHARED10_CLR_m33_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_gpt2_ipg_doze_MASK)
21907 
21908 #define CCM_GPR_SHARED10_CLR_m33_can1_ipg_doze_MASK (0x20000U)
21909 #define CCM_GPR_SHARED10_CLR_m33_can1_ipg_doze_SHIFT (17U)
21910 /*! m33_can1_ipg_doze - m33_can1_ipg_doze */
21911 #define CCM_GPR_SHARED10_CLR_m33_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_can1_ipg_doze_MASK)
21912 
21913 #define CCM_GPR_SHARED10_CLR_m33_can2_ipg_doze_MASK (0x40000U)
21914 #define CCM_GPR_SHARED10_CLR_m33_can2_ipg_doze_SHIFT (18U)
21915 /*! m33_can2_ipg_doze - m33_can2_ipg_doze */
21916 #define CCM_GPR_SHARED10_CLR_m33_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_can2_ipg_doze_MASK)
21917 
21918 #define CCM_GPR_SHARED10_CLR_m33_can3_ipg_doze_MASK (0x80000U)
21919 #define CCM_GPR_SHARED10_CLR_m33_can3_ipg_doze_SHIFT (19U)
21920 /*! m33_can3_ipg_doze - m33_can3_ipg_doze */
21921 #define CCM_GPR_SHARED10_CLR_m33_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_can3_ipg_doze_MASK)
21922 
21923 #define CCM_GPR_SHARED10_CLR_m33_lpuart1_ipg_doze_MASK (0x100000U)
21924 #define CCM_GPR_SHARED10_CLR_m33_lpuart1_ipg_doze_SHIFT (20U)
21925 /*! m33_lpuart1_ipg_doze - m33_lpuart1_ipg_doze */
21926 #define CCM_GPR_SHARED10_CLR_m33_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart1_ipg_doze_MASK)
21927 
21928 #define CCM_GPR_SHARED10_CLR_m33_lpuart2_ipg_doze_MASK (0x200000U)
21929 #define CCM_GPR_SHARED10_CLR_m33_lpuart2_ipg_doze_SHIFT (21U)
21930 /*! m33_lpuart2_ipg_doze - m33_lpuart2_ipg_doze */
21931 #define CCM_GPR_SHARED10_CLR_m33_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart2_ipg_doze_MASK)
21932 
21933 #define CCM_GPR_SHARED10_CLR_m33_lpuart3_ipg_doze_MASK (0x400000U)
21934 #define CCM_GPR_SHARED10_CLR_m33_lpuart3_ipg_doze_SHIFT (22U)
21935 /*! m33_lpuart3_ipg_doze - m33_lpuart3_ipg_doze */
21936 #define CCM_GPR_SHARED10_CLR_m33_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart3_ipg_doze_MASK)
21937 
21938 #define CCM_GPR_SHARED10_CLR_m33_lpuart4_ipg_doze_MASK (0x800000U)
21939 #define CCM_GPR_SHARED10_CLR_m33_lpuart4_ipg_doze_SHIFT (23U)
21940 /*! m33_lpuart4_ipg_doze - m33_lpuart4_ipg_doze */
21941 #define CCM_GPR_SHARED10_CLR_m33_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart4_ipg_doze_MASK)
21942 
21943 #define CCM_GPR_SHARED10_CLR_m33_lpuart5_ipg_doze_MASK (0x1000000U)
21944 #define CCM_GPR_SHARED10_CLR_m33_lpuart5_ipg_doze_SHIFT (24U)
21945 /*! m33_lpuart5_ipg_doze - m33_lpuart5_ipg_doze */
21946 #define CCM_GPR_SHARED10_CLR_m33_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart5_ipg_doze_MASK)
21947 
21948 #define CCM_GPR_SHARED10_CLR_m33_lpuart6_ipg_doze_MASK (0x2000000U)
21949 #define CCM_GPR_SHARED10_CLR_m33_lpuart6_ipg_doze_SHIFT (25U)
21950 /*! m33_lpuart6_ipg_doze - m33_lpuart6_ipg_doze */
21951 #define CCM_GPR_SHARED10_CLR_m33_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart6_ipg_doze_MASK)
21952 
21953 #define CCM_GPR_SHARED10_CLR_m33_lpuart7_ipg_doze_MASK (0x4000000U)
21954 #define CCM_GPR_SHARED10_CLR_m33_lpuart7_ipg_doze_SHIFT (26U)
21955 /*! m33_lpuart7_ipg_doze - m33_lpuart7_ipg_doze */
21956 #define CCM_GPR_SHARED10_CLR_m33_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart7_ipg_doze_MASK)
21957 
21958 #define CCM_GPR_SHARED10_CLR_m33_lpuart8_ipg_doze_MASK (0x8000000U)
21959 #define CCM_GPR_SHARED10_CLR_m33_lpuart8_ipg_doze_SHIFT (27U)
21960 /*! m33_lpuart8_ipg_doze - m33_lpuart8_ipg_doze */
21961 #define CCM_GPR_SHARED10_CLR_m33_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart8_ipg_doze_MASK)
21962 
21963 #define CCM_GPR_SHARED10_CLR_m33_lpuart9_ipg_doze_MASK (0x10000000U)
21964 #define CCM_GPR_SHARED10_CLR_m33_lpuart9_ipg_doze_SHIFT (28U)
21965 /*! m33_lpuart9_ipg_doze - m33_lpuart9_ipg_doze */
21966 #define CCM_GPR_SHARED10_CLR_m33_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart9_ipg_doze_MASK)
21967 
21968 #define CCM_GPR_SHARED10_CLR_m33_lpuart10_ipg_doze_MASK (0x20000000U)
21969 #define CCM_GPR_SHARED10_CLR_m33_lpuart10_ipg_doze_SHIFT (29U)
21970 /*! m33_lpuart10_ipg_doze - m33_lpuart10_ipg_doze */
21971 #define CCM_GPR_SHARED10_CLR_m33_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart10_ipg_doze_MASK)
21972 
21973 #define CCM_GPR_SHARED10_CLR_m33_lpuart11_ipg_doze_MASK (0x40000000U)
21974 #define CCM_GPR_SHARED10_CLR_m33_lpuart11_ipg_doze_SHIFT (30U)
21975 /*! m33_lpuart11_ipg_doze - m33_lpuart11_ipg_doze */
21976 #define CCM_GPR_SHARED10_CLR_m33_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart11_ipg_doze_MASK)
21977 
21978 #define CCM_GPR_SHARED10_CLR_m33_lpuart12_ipg_doze_MASK (0x80000000U)
21979 #define CCM_GPR_SHARED10_CLR_m33_lpuart12_ipg_doze_SHIFT (31U)
21980 /*! m33_lpuart12_ipg_doze - m33_lpuart12_ipg_doze */
21981 #define CCM_GPR_SHARED10_CLR_m33_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_CLR_m33_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_CLR_m33_lpuart12_ipg_doze_MASK)
21982 /*! @} */
21983 
21984 /*! @name GPR_SHARED10_TOG - General Purpose Register */
21985 /*! @{ */
21986 
21987 #define CCM_GPR_SHARED10_TOG_m33_adc1_ipg_doze_MASK (0x1U)
21988 #define CCM_GPR_SHARED10_TOG_m33_adc1_ipg_doze_SHIFT (0U)
21989 /*! m33_adc1_ipg_doze - m33_adc1_ipg_doze */
21990 #define CCM_GPR_SHARED10_TOG_m33_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_adc1_ipg_doze_MASK)
21991 
21992 #define CCM_GPR_SHARED10_TOG_m33_adc2_ipg_doze_MASK (0x2U)
21993 #define CCM_GPR_SHARED10_TOG_m33_adc2_ipg_doze_SHIFT (1U)
21994 /*! m33_adc2_ipg_doze - m33_adc2_ipg_doze */
21995 #define CCM_GPR_SHARED10_TOG_m33_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_adc2_ipg_doze_MASK)
21996 
21997 #define CCM_GPR_SHARED10_TOG_m33_flexspi1_ipg_doze_MASK (0x4U)
21998 #define CCM_GPR_SHARED10_TOG_m33_flexspi1_ipg_doze_SHIFT (2U)
21999 /*! m33_flexspi1_ipg_doze - m33_flexspi1_ipg_doze */
22000 #define CCM_GPR_SHARED10_TOG_m33_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_flexspi1_ipg_doze_MASK)
22001 
22002 #define CCM_GPR_SHARED10_TOG_m33_flexspi2_ipg_doze_MASK (0x8U)
22003 #define CCM_GPR_SHARED10_TOG_m33_flexspi2_ipg_doze_SHIFT (3U)
22004 /*! m33_flexspi2_ipg_doze - m33_flexspi2_ipg_doze */
22005 #define CCM_GPR_SHARED10_TOG_m33_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_flexspi2_ipg_doze_MASK)
22006 
22007 #define CCM_GPR_SHARED10_TOG_m33_flexio1_ipg_doze_MASK (0x10U)
22008 #define CCM_GPR_SHARED10_TOG_m33_flexio1_ipg_doze_SHIFT (4U)
22009 /*! m33_flexio1_ipg_doze - m33_flexio1_ipg_doze */
22010 #define CCM_GPR_SHARED10_TOG_m33_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_flexio1_ipg_doze_MASK)
22011 
22012 #define CCM_GPR_SHARED10_TOG_m33_flexio2_ipg_doze_MASK (0x20U)
22013 #define CCM_GPR_SHARED10_TOG_m33_flexio2_ipg_doze_SHIFT (5U)
22014 /*! m33_flexio2_ipg_doze - m33_flexio2_ipg_doze */
22015 #define CCM_GPR_SHARED10_TOG_m33_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_flexio2_ipg_doze_MASK)
22016 
22017 #define CCM_GPR_SHARED10_TOG_m33_lpit1_ipg_doze_MASK (0x40U)
22018 #define CCM_GPR_SHARED10_TOG_m33_lpit1_ipg_doze_SHIFT (6U)
22019 /*! m33_lpit1_ipg_doze - m33_lpit1_ipg_doze */
22020 #define CCM_GPR_SHARED10_TOG_m33_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpit1_ipg_doze_MASK)
22021 
22022 #define CCM_GPR_SHARED10_TOG_m33_lpit2_ipg_doze_MASK (0x80U)
22023 #define CCM_GPR_SHARED10_TOG_m33_lpit2_ipg_doze_SHIFT (7U)
22024 /*! m33_lpit2_ipg_doze - m33_lpit2_ipg_doze */
22025 #define CCM_GPR_SHARED10_TOG_m33_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpit2_ipg_doze_MASK)
22026 
22027 #define CCM_GPR_SHARED10_TOG_m33_lpit3_ipg_doze_MASK (0x100U)
22028 #define CCM_GPR_SHARED10_TOG_m33_lpit3_ipg_doze_SHIFT (8U)
22029 /*! m33_lpit3_ipg_doze - m33_lpit3_ipg_doze */
22030 #define CCM_GPR_SHARED10_TOG_m33_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpit3_ipg_doze_MASK)
22031 
22032 #define CCM_GPR_SHARED10_TOG_m33_tpm1_ipg_doze_MASK (0x200U)
22033 #define CCM_GPR_SHARED10_TOG_m33_tpm1_ipg_doze_SHIFT (9U)
22034 /*! m33_tpm1_ipg_doze - m33_tpm1_ipg_doze */
22035 #define CCM_GPR_SHARED10_TOG_m33_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm1_ipg_doze_MASK)
22036 
22037 #define CCM_GPR_SHARED10_TOG_m33_tpm2_ipg_doze_MASK (0x400U)
22038 #define CCM_GPR_SHARED10_TOG_m33_tpm2_ipg_doze_SHIFT (10U)
22039 /*! m33_tpm2_ipg_doze - m33_tpm2_ipg_doze */
22040 #define CCM_GPR_SHARED10_TOG_m33_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm2_ipg_doze_MASK)
22041 
22042 #define CCM_GPR_SHARED10_TOG_m33_tpm3_ipg_doze_MASK (0x800U)
22043 #define CCM_GPR_SHARED10_TOG_m33_tpm3_ipg_doze_SHIFT (11U)
22044 /*! m33_tpm3_ipg_doze - m33_tpm3_ipg_doze */
22045 #define CCM_GPR_SHARED10_TOG_m33_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm3_ipg_doze_MASK)
22046 
22047 #define CCM_GPR_SHARED10_TOG_m33_tpm4_ipg_doze_MASK (0x1000U)
22048 #define CCM_GPR_SHARED10_TOG_m33_tpm4_ipg_doze_SHIFT (12U)
22049 /*! m33_tpm4_ipg_doze - m33_tpm4_ipg_doze */
22050 #define CCM_GPR_SHARED10_TOG_m33_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm4_ipg_doze_MASK)
22051 
22052 #define CCM_GPR_SHARED10_TOG_m33_tpm5_ipg_doze_MASK (0x2000U)
22053 #define CCM_GPR_SHARED10_TOG_m33_tpm5_ipg_doze_SHIFT (13U)
22054 /*! m33_tpm5_ipg_doze - m33_tpm5_ipg_doze */
22055 #define CCM_GPR_SHARED10_TOG_m33_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm5_ipg_doze_MASK)
22056 
22057 #define CCM_GPR_SHARED10_TOG_m33_tpm6_ipg_doze_MASK (0x4000U)
22058 #define CCM_GPR_SHARED10_TOG_m33_tpm6_ipg_doze_SHIFT (14U)
22059 /*! m33_tpm6_ipg_doze - m33_tpm6_ipg_doze */
22060 #define CCM_GPR_SHARED10_TOG_m33_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_tpm6_ipg_doze_MASK)
22061 
22062 #define CCM_GPR_SHARED10_TOG_m33_gpt1_ipg_doze_MASK (0x8000U)
22063 #define CCM_GPR_SHARED10_TOG_m33_gpt1_ipg_doze_SHIFT (15U)
22064 /*! m33_gpt1_ipg_doze - m33_gpt1_ipg_doze */
22065 #define CCM_GPR_SHARED10_TOG_m33_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_gpt1_ipg_doze_MASK)
22066 
22067 #define CCM_GPR_SHARED10_TOG_m33_gpt2_ipg_doze_MASK (0x10000U)
22068 #define CCM_GPR_SHARED10_TOG_m33_gpt2_ipg_doze_SHIFT (16U)
22069 /*! m33_gpt2_ipg_doze - m33_gpt2_ipg_doze */
22070 #define CCM_GPR_SHARED10_TOG_m33_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_gpt2_ipg_doze_MASK)
22071 
22072 #define CCM_GPR_SHARED10_TOG_m33_can1_ipg_doze_MASK (0x20000U)
22073 #define CCM_GPR_SHARED10_TOG_m33_can1_ipg_doze_SHIFT (17U)
22074 /*! m33_can1_ipg_doze - m33_can1_ipg_doze */
22075 #define CCM_GPR_SHARED10_TOG_m33_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_can1_ipg_doze_MASK)
22076 
22077 #define CCM_GPR_SHARED10_TOG_m33_can2_ipg_doze_MASK (0x40000U)
22078 #define CCM_GPR_SHARED10_TOG_m33_can2_ipg_doze_SHIFT (18U)
22079 /*! m33_can2_ipg_doze - m33_can2_ipg_doze */
22080 #define CCM_GPR_SHARED10_TOG_m33_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_can2_ipg_doze_MASK)
22081 
22082 #define CCM_GPR_SHARED10_TOG_m33_can3_ipg_doze_MASK (0x80000U)
22083 #define CCM_GPR_SHARED10_TOG_m33_can3_ipg_doze_SHIFT (19U)
22084 /*! m33_can3_ipg_doze - m33_can3_ipg_doze */
22085 #define CCM_GPR_SHARED10_TOG_m33_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_can3_ipg_doze_MASK)
22086 
22087 #define CCM_GPR_SHARED10_TOG_m33_lpuart1_ipg_doze_MASK (0x100000U)
22088 #define CCM_GPR_SHARED10_TOG_m33_lpuart1_ipg_doze_SHIFT (20U)
22089 /*! m33_lpuart1_ipg_doze - m33_lpuart1_ipg_doze */
22090 #define CCM_GPR_SHARED10_TOG_m33_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart1_ipg_doze_MASK)
22091 
22092 #define CCM_GPR_SHARED10_TOG_m33_lpuart2_ipg_doze_MASK (0x200000U)
22093 #define CCM_GPR_SHARED10_TOG_m33_lpuart2_ipg_doze_SHIFT (21U)
22094 /*! m33_lpuart2_ipg_doze - m33_lpuart2_ipg_doze */
22095 #define CCM_GPR_SHARED10_TOG_m33_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart2_ipg_doze_MASK)
22096 
22097 #define CCM_GPR_SHARED10_TOG_m33_lpuart3_ipg_doze_MASK (0x400000U)
22098 #define CCM_GPR_SHARED10_TOG_m33_lpuart3_ipg_doze_SHIFT (22U)
22099 /*! m33_lpuart3_ipg_doze - m33_lpuart3_ipg_doze */
22100 #define CCM_GPR_SHARED10_TOG_m33_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart3_ipg_doze_MASK)
22101 
22102 #define CCM_GPR_SHARED10_TOG_m33_lpuart4_ipg_doze_MASK (0x800000U)
22103 #define CCM_GPR_SHARED10_TOG_m33_lpuart4_ipg_doze_SHIFT (23U)
22104 /*! m33_lpuart4_ipg_doze - m33_lpuart4_ipg_doze */
22105 #define CCM_GPR_SHARED10_TOG_m33_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart4_ipg_doze_MASK)
22106 
22107 #define CCM_GPR_SHARED10_TOG_m33_lpuart5_ipg_doze_MASK (0x1000000U)
22108 #define CCM_GPR_SHARED10_TOG_m33_lpuart5_ipg_doze_SHIFT (24U)
22109 /*! m33_lpuart5_ipg_doze - m33_lpuart5_ipg_doze */
22110 #define CCM_GPR_SHARED10_TOG_m33_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart5_ipg_doze_MASK)
22111 
22112 #define CCM_GPR_SHARED10_TOG_m33_lpuart6_ipg_doze_MASK (0x2000000U)
22113 #define CCM_GPR_SHARED10_TOG_m33_lpuart6_ipg_doze_SHIFT (25U)
22114 /*! m33_lpuart6_ipg_doze - m33_lpuart6_ipg_doze */
22115 #define CCM_GPR_SHARED10_TOG_m33_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart6_ipg_doze_MASK)
22116 
22117 #define CCM_GPR_SHARED10_TOG_m33_lpuart7_ipg_doze_MASK (0x4000000U)
22118 #define CCM_GPR_SHARED10_TOG_m33_lpuart7_ipg_doze_SHIFT (26U)
22119 /*! m33_lpuart7_ipg_doze - m33_lpuart7_ipg_doze */
22120 #define CCM_GPR_SHARED10_TOG_m33_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart7_ipg_doze_MASK)
22121 
22122 #define CCM_GPR_SHARED10_TOG_m33_lpuart8_ipg_doze_MASK (0x8000000U)
22123 #define CCM_GPR_SHARED10_TOG_m33_lpuart8_ipg_doze_SHIFT (27U)
22124 /*! m33_lpuart8_ipg_doze - m33_lpuart8_ipg_doze */
22125 #define CCM_GPR_SHARED10_TOG_m33_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart8_ipg_doze_MASK)
22126 
22127 #define CCM_GPR_SHARED10_TOG_m33_lpuart9_ipg_doze_MASK (0x10000000U)
22128 #define CCM_GPR_SHARED10_TOG_m33_lpuart9_ipg_doze_SHIFT (28U)
22129 /*! m33_lpuart9_ipg_doze - m33_lpuart9_ipg_doze */
22130 #define CCM_GPR_SHARED10_TOG_m33_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart9_ipg_doze_MASK)
22131 
22132 #define CCM_GPR_SHARED10_TOG_m33_lpuart10_ipg_doze_MASK (0x20000000U)
22133 #define CCM_GPR_SHARED10_TOG_m33_lpuart10_ipg_doze_SHIFT (29U)
22134 /*! m33_lpuart10_ipg_doze - m33_lpuart10_ipg_doze */
22135 #define CCM_GPR_SHARED10_TOG_m33_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart10_ipg_doze_MASK)
22136 
22137 #define CCM_GPR_SHARED10_TOG_m33_lpuart11_ipg_doze_MASK (0x40000000U)
22138 #define CCM_GPR_SHARED10_TOG_m33_lpuart11_ipg_doze_SHIFT (30U)
22139 /*! m33_lpuart11_ipg_doze - m33_lpuart11_ipg_doze */
22140 #define CCM_GPR_SHARED10_TOG_m33_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart11_ipg_doze_MASK)
22141 
22142 #define CCM_GPR_SHARED10_TOG_m33_lpuart12_ipg_doze_MASK (0x80000000U)
22143 #define CCM_GPR_SHARED10_TOG_m33_lpuart12_ipg_doze_SHIFT (31U)
22144 /*! m33_lpuart12_ipg_doze - m33_lpuart12_ipg_doze */
22145 #define CCM_GPR_SHARED10_TOG_m33_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_TOG_m33_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED10_TOG_m33_lpuart12_ipg_doze_MASK)
22146 /*! @} */
22147 
22148 /*! @name GPR_SHARED10_AUTHEN - GPR access control */
22149 /*! @{ */
22150 
22151 #define CCM_GPR_SHARED10_AUTHEN_TZ_USER_MASK     (0x100U)
22152 #define CCM_GPR_SHARED10_AUTHEN_TZ_USER_SHIFT    (8U)
22153 /*! TZ_USER - User access permission
22154  *  0b1..Registers of shared GPR slice can be changed in user mode.
22155  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
22156  */
22157 #define CCM_GPR_SHARED10_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TZ_USER_MASK)
22158 
22159 #define CCM_GPR_SHARED10_AUTHEN_TZ_NS_MASK       (0x200U)
22160 #define CCM_GPR_SHARED10_AUTHEN_TZ_NS_SHIFT      (9U)
22161 /*! TZ_NS - Non-secure access permission
22162  *  0b0..Cannot be changed in Non-secure mode.
22163  *  0b1..Can be changed in Non-secure mode.
22164  */
22165 #define CCM_GPR_SHARED10_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TZ_NS_MASK)
22166 
22167 #define CCM_GPR_SHARED10_AUTHEN_LOCK_TZ_MASK     (0x800U)
22168 #define CCM_GPR_SHARED10_AUTHEN_LOCK_TZ_SHIFT    (11U)
22169 /*! LOCK_TZ - Lock TrustZone settings
22170  *  0b0..TrustZone settings is not locked.
22171  *  0b1..TrustZone settings is locked.
22172  */
22173 #define CCM_GPR_SHARED10_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_LOCK_TZ_MASK)
22174 
22175 #define CCM_GPR_SHARED10_AUTHEN_LOCK_LIST_MASK   (0x8000U)
22176 #define CCM_GPR_SHARED10_AUTHEN_LOCK_LIST_SHIFT  (15U)
22177 /*! LOCK_LIST - Lock white list
22178  *  0b0..Whitelist is not locked.
22179  *  0b1..Whitelist is locked.
22180  */
22181 #define CCM_GPR_SHARED10_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_LOCK_LIST_MASK)
22182 
22183 #define CCM_GPR_SHARED10_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
22184 #define CCM_GPR_SHARED10_AUTHEN_WHITE_LIST_SHIFT (16U)
22185 /*! WHITE_LIST - Whitelist settings */
22186 #define CCM_GPR_SHARED10_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_WHITE_LIST_MASK)
22187 /*! @} */
22188 
22189 /*! @name GPR_SHARED10_AUTHEN_SET - GPR access control */
22190 /*! @{ */
22191 
22192 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_USER_MASK (0x100U)
22193 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_USER_SHIFT (8U)
22194 /*! TZ_USER - User access permission */
22195 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_SET_TZ_USER_MASK)
22196 
22197 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_NS_MASK   (0x200U)
22198 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_NS_SHIFT  (9U)
22199 /*! TZ_NS - Non-secure access permission */
22200 #define CCM_GPR_SHARED10_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_SET_TZ_NS_MASK)
22201 
22202 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
22203 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
22204 /*! LOCK_TZ - Lock TrustZone settings */
22205 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_SET_LOCK_TZ_MASK)
22206 
22207 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
22208 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
22209 /*! LOCK_LIST - Lock white list */
22210 #define CCM_GPR_SHARED10_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_SET_LOCK_LIST_MASK)
22211 
22212 #define CCM_GPR_SHARED10_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
22213 #define CCM_GPR_SHARED10_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
22214 /*! WHITE_LIST - Whitelist settings */
22215 #define CCM_GPR_SHARED10_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_SET_WHITE_LIST_MASK)
22216 /*! @} */
22217 
22218 /*! @name GPR_SHARED10_AUTHEN_CLR - GPR access control */
22219 /*! @{ */
22220 
22221 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_USER_MASK (0x100U)
22222 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_USER_SHIFT (8U)
22223 /*! TZ_USER - User access permission */
22224 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_CLR_TZ_USER_MASK)
22225 
22226 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
22227 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
22228 /*! TZ_NS - Non-secure access permission */
22229 #define CCM_GPR_SHARED10_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_CLR_TZ_NS_MASK)
22230 
22231 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
22232 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
22233 /*! LOCK_TZ - Lock TrustZone settings */
22234 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_TZ_MASK)
22235 
22236 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
22237 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
22238 /*! LOCK_LIST - Lock white list */
22239 #define CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_CLR_LOCK_LIST_MASK)
22240 
22241 #define CCM_GPR_SHARED10_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
22242 #define CCM_GPR_SHARED10_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
22243 /*! WHITE_LIST - Whitelist settings */
22244 #define CCM_GPR_SHARED10_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_CLR_WHITE_LIST_MASK)
22245 /*! @} */
22246 
22247 /*! @name GPR_SHARED10_AUTHEN_TOG - GPR access control */
22248 /*! @{ */
22249 
22250 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_USER_MASK (0x100U)
22251 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_USER_SHIFT (8U)
22252 /*! TZ_USER - User access permission */
22253 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TOG_TZ_USER_MASK)
22254 
22255 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
22256 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
22257 /*! TZ_NS - Non-secure access permission */
22258 #define CCM_GPR_SHARED10_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TOG_TZ_NS_MASK)
22259 
22260 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
22261 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
22262 /*! LOCK_TZ - Lock TrustZone settings */
22263 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_TZ_MASK)
22264 
22265 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
22266 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
22267 /*! LOCK_LIST - Lock white list */
22268 #define CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TOG_LOCK_LIST_MASK)
22269 
22270 #define CCM_GPR_SHARED10_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
22271 #define CCM_GPR_SHARED10_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
22272 /*! WHITE_LIST - Whitelist settings */
22273 #define CCM_GPR_SHARED10_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED10_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED10_AUTHEN_TOG_WHITE_LIST_MASK)
22274 /*! @} */
22275 
22276 /*! @name GPR_SHARED11 - General Purpose Register */
22277 /*! @{ */
22278 
22279 #define CCM_GPR_SHARED11_m33_lpi2c1_ipg_doze_MASK (0x1U)
22280 #define CCM_GPR_SHARED11_m33_lpi2c1_ipg_doze_SHIFT (0U)
22281 /*! m33_lpi2c1_ipg_doze - m33_lpi2c1_ipg_doze */
22282 #define CCM_GPR_SHARED11_m33_lpi2c1_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c1_ipg_doze_MASK)
22283 
22284 #define CCM_GPR_SHARED11_m33_lpi2c2_ipg_doze_MASK (0x2U)
22285 #define CCM_GPR_SHARED11_m33_lpi2c2_ipg_doze_SHIFT (1U)
22286 /*! m33_lpi2c2_ipg_doze - m33_lpi2c2_ipg_doze */
22287 #define CCM_GPR_SHARED11_m33_lpi2c2_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c2_ipg_doze_MASK)
22288 
22289 #define CCM_GPR_SHARED11_m33_lpi2c3_ipg_doze_MASK (0x4U)
22290 #define CCM_GPR_SHARED11_m33_lpi2c3_ipg_doze_SHIFT (2U)
22291 /*! m33_lpi2c3_ipg_doze - m33_lpi2c3_ipg_doze */
22292 #define CCM_GPR_SHARED11_m33_lpi2c3_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c3_ipg_doze_MASK)
22293 
22294 #define CCM_GPR_SHARED11_m33_lpi2c4_ipg_doze_MASK (0x8U)
22295 #define CCM_GPR_SHARED11_m33_lpi2c4_ipg_doze_SHIFT (3U)
22296 /*! m33_lpi2c4_ipg_doze - m33_lpi2c4_ipg_doze */
22297 #define CCM_GPR_SHARED11_m33_lpi2c4_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c4_ipg_doze_MASK)
22298 
22299 #define CCM_GPR_SHARED11_m33_lpi2c5_ipg_doze_MASK (0x10U)
22300 #define CCM_GPR_SHARED11_m33_lpi2c5_ipg_doze_SHIFT (4U)
22301 /*! m33_lpi2c5_ipg_doze - m33_lpi2c5_ipg_doze */
22302 #define CCM_GPR_SHARED11_m33_lpi2c5_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c5_ipg_doze_MASK)
22303 
22304 #define CCM_GPR_SHARED11_m33_lpi2c6_ipg_doze_MASK (0x20U)
22305 #define CCM_GPR_SHARED11_m33_lpi2c6_ipg_doze_SHIFT (5U)
22306 /*! m33_lpi2c6_ipg_doze - m33_lpi2c6_ipg_doze */
22307 #define CCM_GPR_SHARED11_m33_lpi2c6_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpi2c6_ipg_doze_MASK)
22308 
22309 #define CCM_GPR_SHARED11_m33_lpspi1_ipg_doze_MASK (0x40U)
22310 #define CCM_GPR_SHARED11_m33_lpspi1_ipg_doze_SHIFT (6U)
22311 /*! m33_lpspi1_ipg_doze - m33_lpspi1_ipg_doze */
22312 #define CCM_GPR_SHARED11_m33_lpspi1_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi1_ipg_doze_MASK)
22313 
22314 #define CCM_GPR_SHARED11_m33_lpspi2_ipg_doze_MASK (0x80U)
22315 #define CCM_GPR_SHARED11_m33_lpspi2_ipg_doze_SHIFT (7U)
22316 /*! m33_lpspi2_ipg_doze - m33_lpspi2_ipg_doze */
22317 #define CCM_GPR_SHARED11_m33_lpspi2_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi2_ipg_doze_MASK)
22318 
22319 #define CCM_GPR_SHARED11_m33_lpspi3_ipg_doze_MASK (0x100U)
22320 #define CCM_GPR_SHARED11_m33_lpspi3_ipg_doze_SHIFT (8U)
22321 /*! m33_lpspi3_ipg_doze - m33_lpspi3_ipg_doze */
22322 #define CCM_GPR_SHARED11_m33_lpspi3_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi3_ipg_doze_MASK)
22323 
22324 #define CCM_GPR_SHARED11_m33_lpspi4_ipg_doze_MASK (0x200U)
22325 #define CCM_GPR_SHARED11_m33_lpspi4_ipg_doze_SHIFT (9U)
22326 /*! m33_lpspi4_ipg_doze - m33_lpspi4_ipg_doze */
22327 #define CCM_GPR_SHARED11_m33_lpspi4_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi4_ipg_doze_MASK)
22328 
22329 #define CCM_GPR_SHARED11_m33_lpspi5_ipg_doze_MASK (0x400U)
22330 #define CCM_GPR_SHARED11_m33_lpspi5_ipg_doze_SHIFT (10U)
22331 /*! m33_lpspi5_ipg_doze - m33_lpspi5_ipg_doze */
22332 #define CCM_GPR_SHARED11_m33_lpspi5_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi5_ipg_doze_MASK)
22333 
22334 #define CCM_GPR_SHARED11_m33_lpspi6_ipg_doze_MASK (0x800U)
22335 #define CCM_GPR_SHARED11_m33_lpspi6_ipg_doze_SHIFT (11U)
22336 /*! m33_lpspi6_ipg_doze - m33_lpspi6_ipg_doze */
22337 #define CCM_GPR_SHARED11_m33_lpspi6_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_lpspi6_ipg_doze_MASK)
22338 
22339 #define CCM_GPR_SHARED11_m33_sinc1_ipg_doze_MASK (0x1000U)
22340 #define CCM_GPR_SHARED11_m33_sinc1_ipg_doze_SHIFT (12U)
22341 /*! m33_sinc1_ipg_doze - m33_sinc1_ipg_doze */
22342 #define CCM_GPR_SHARED11_m33_sinc1_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_sinc1_ipg_doze_MASK)
22343 
22344 #define CCM_GPR_SHARED11_m33_sinc2_ipg_doze_MASK (0x2000U)
22345 #define CCM_GPR_SHARED11_m33_sinc2_ipg_doze_SHIFT (13U)
22346 /*! m33_sinc2_ipg_doze - m33_sinc2_ipg_doze */
22347 #define CCM_GPR_SHARED11_m33_sinc2_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_sinc2_ipg_doze_MASK)
22348 
22349 #define CCM_GPR_SHARED11_m33_sinc3_ipg_doze_MASK (0x4000U)
22350 #define CCM_GPR_SHARED11_m33_sinc3_ipg_doze_SHIFT (14U)
22351 /*! m33_sinc3_ipg_doze - m33_sinc3_ipg_doze */
22352 #define CCM_GPR_SHARED11_m33_sinc3_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_sinc3_ipg_doze_MASK)
22353 
22354 #define CCM_GPR_SHARED11_m33_mic_ipg_doze_MASK   (0x8000U)
22355 #define CCM_GPR_SHARED11_m33_mic_ipg_doze_SHIFT  (15U)
22356 /*! m33_mic_ipg_doze - m33_mic_ipg_doze */
22357 #define CCM_GPR_SHARED11_m33_mic_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_m33_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_m33_mic_ipg_doze_MASK)
22358 /*! @} */
22359 
22360 /*! @name GPR_SHARED11_SET - General Purpose Register */
22361 /*! @{ */
22362 
22363 #define CCM_GPR_SHARED11_SET_m33_lpi2c1_ipg_doze_MASK (0x1U)
22364 #define CCM_GPR_SHARED11_SET_m33_lpi2c1_ipg_doze_SHIFT (0U)
22365 /*! m33_lpi2c1_ipg_doze - m33_lpi2c1_ipg_doze */
22366 #define CCM_GPR_SHARED11_SET_m33_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c1_ipg_doze_MASK)
22367 
22368 #define CCM_GPR_SHARED11_SET_m33_lpi2c2_ipg_doze_MASK (0x2U)
22369 #define CCM_GPR_SHARED11_SET_m33_lpi2c2_ipg_doze_SHIFT (1U)
22370 /*! m33_lpi2c2_ipg_doze - m33_lpi2c2_ipg_doze */
22371 #define CCM_GPR_SHARED11_SET_m33_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c2_ipg_doze_MASK)
22372 
22373 #define CCM_GPR_SHARED11_SET_m33_lpi2c3_ipg_doze_MASK (0x4U)
22374 #define CCM_GPR_SHARED11_SET_m33_lpi2c3_ipg_doze_SHIFT (2U)
22375 /*! m33_lpi2c3_ipg_doze - m33_lpi2c3_ipg_doze */
22376 #define CCM_GPR_SHARED11_SET_m33_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c3_ipg_doze_MASK)
22377 
22378 #define CCM_GPR_SHARED11_SET_m33_lpi2c4_ipg_doze_MASK (0x8U)
22379 #define CCM_GPR_SHARED11_SET_m33_lpi2c4_ipg_doze_SHIFT (3U)
22380 /*! m33_lpi2c4_ipg_doze - m33_lpi2c4_ipg_doze */
22381 #define CCM_GPR_SHARED11_SET_m33_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c4_ipg_doze_MASK)
22382 
22383 #define CCM_GPR_SHARED11_SET_m33_lpi2c5_ipg_doze_MASK (0x10U)
22384 #define CCM_GPR_SHARED11_SET_m33_lpi2c5_ipg_doze_SHIFT (4U)
22385 /*! m33_lpi2c5_ipg_doze - m33_lpi2c5_ipg_doze */
22386 #define CCM_GPR_SHARED11_SET_m33_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c5_ipg_doze_MASK)
22387 
22388 #define CCM_GPR_SHARED11_SET_m33_lpi2c6_ipg_doze_MASK (0x20U)
22389 #define CCM_GPR_SHARED11_SET_m33_lpi2c6_ipg_doze_SHIFT (5U)
22390 /*! m33_lpi2c6_ipg_doze - m33_lpi2c6_ipg_doze */
22391 #define CCM_GPR_SHARED11_SET_m33_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpi2c6_ipg_doze_MASK)
22392 
22393 #define CCM_GPR_SHARED11_SET_m33_lpspi1_ipg_doze_MASK (0x40U)
22394 #define CCM_GPR_SHARED11_SET_m33_lpspi1_ipg_doze_SHIFT (6U)
22395 /*! m33_lpspi1_ipg_doze - m33_lpspi1_ipg_doze */
22396 #define CCM_GPR_SHARED11_SET_m33_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi1_ipg_doze_MASK)
22397 
22398 #define CCM_GPR_SHARED11_SET_m33_lpspi2_ipg_doze_MASK (0x80U)
22399 #define CCM_GPR_SHARED11_SET_m33_lpspi2_ipg_doze_SHIFT (7U)
22400 /*! m33_lpspi2_ipg_doze - m33_lpspi2_ipg_doze */
22401 #define CCM_GPR_SHARED11_SET_m33_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi2_ipg_doze_MASK)
22402 
22403 #define CCM_GPR_SHARED11_SET_m33_lpspi3_ipg_doze_MASK (0x100U)
22404 #define CCM_GPR_SHARED11_SET_m33_lpspi3_ipg_doze_SHIFT (8U)
22405 /*! m33_lpspi3_ipg_doze - m33_lpspi3_ipg_doze */
22406 #define CCM_GPR_SHARED11_SET_m33_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi3_ipg_doze_MASK)
22407 
22408 #define CCM_GPR_SHARED11_SET_m33_lpspi4_ipg_doze_MASK (0x200U)
22409 #define CCM_GPR_SHARED11_SET_m33_lpspi4_ipg_doze_SHIFT (9U)
22410 /*! m33_lpspi4_ipg_doze - m33_lpspi4_ipg_doze */
22411 #define CCM_GPR_SHARED11_SET_m33_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi4_ipg_doze_MASK)
22412 
22413 #define CCM_GPR_SHARED11_SET_m33_lpspi5_ipg_doze_MASK (0x400U)
22414 #define CCM_GPR_SHARED11_SET_m33_lpspi5_ipg_doze_SHIFT (10U)
22415 /*! m33_lpspi5_ipg_doze - m33_lpspi5_ipg_doze */
22416 #define CCM_GPR_SHARED11_SET_m33_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi5_ipg_doze_MASK)
22417 
22418 #define CCM_GPR_SHARED11_SET_m33_lpspi6_ipg_doze_MASK (0x800U)
22419 #define CCM_GPR_SHARED11_SET_m33_lpspi6_ipg_doze_SHIFT (11U)
22420 /*! m33_lpspi6_ipg_doze - m33_lpspi6_ipg_doze */
22421 #define CCM_GPR_SHARED11_SET_m33_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_lpspi6_ipg_doze_MASK)
22422 
22423 #define CCM_GPR_SHARED11_SET_m33_sinc1_ipg_doze_MASK (0x1000U)
22424 #define CCM_GPR_SHARED11_SET_m33_sinc1_ipg_doze_SHIFT (12U)
22425 /*! m33_sinc1_ipg_doze - m33_sinc1_ipg_doze */
22426 #define CCM_GPR_SHARED11_SET_m33_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_sinc1_ipg_doze_MASK)
22427 
22428 #define CCM_GPR_SHARED11_SET_m33_sinc2_ipg_doze_MASK (0x2000U)
22429 #define CCM_GPR_SHARED11_SET_m33_sinc2_ipg_doze_SHIFT (13U)
22430 /*! m33_sinc2_ipg_doze - m33_sinc2_ipg_doze */
22431 #define CCM_GPR_SHARED11_SET_m33_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_sinc2_ipg_doze_MASK)
22432 
22433 #define CCM_GPR_SHARED11_SET_m33_sinc3_ipg_doze_MASK (0x4000U)
22434 #define CCM_GPR_SHARED11_SET_m33_sinc3_ipg_doze_SHIFT (14U)
22435 /*! m33_sinc3_ipg_doze - m33_sinc3_ipg_doze */
22436 #define CCM_GPR_SHARED11_SET_m33_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_sinc3_ipg_doze_MASK)
22437 
22438 #define CCM_GPR_SHARED11_SET_m33_mic_ipg_doze_MASK (0x8000U)
22439 #define CCM_GPR_SHARED11_SET_m33_mic_ipg_doze_SHIFT (15U)
22440 /*! m33_mic_ipg_doze - m33_mic_ipg_doze */
22441 #define CCM_GPR_SHARED11_SET_m33_mic_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_SET_m33_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_SET_m33_mic_ipg_doze_MASK)
22442 /*! @} */
22443 
22444 /*! @name GPR_SHARED11_CLR - General Purpose Register */
22445 /*! @{ */
22446 
22447 #define CCM_GPR_SHARED11_CLR_m33_lpi2c1_ipg_doze_MASK (0x1U)
22448 #define CCM_GPR_SHARED11_CLR_m33_lpi2c1_ipg_doze_SHIFT (0U)
22449 /*! m33_lpi2c1_ipg_doze - m33_lpi2c1_ipg_doze */
22450 #define CCM_GPR_SHARED11_CLR_m33_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c1_ipg_doze_MASK)
22451 
22452 #define CCM_GPR_SHARED11_CLR_m33_lpi2c2_ipg_doze_MASK (0x2U)
22453 #define CCM_GPR_SHARED11_CLR_m33_lpi2c2_ipg_doze_SHIFT (1U)
22454 /*! m33_lpi2c2_ipg_doze - m33_lpi2c2_ipg_doze */
22455 #define CCM_GPR_SHARED11_CLR_m33_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c2_ipg_doze_MASK)
22456 
22457 #define CCM_GPR_SHARED11_CLR_m33_lpi2c3_ipg_doze_MASK (0x4U)
22458 #define CCM_GPR_SHARED11_CLR_m33_lpi2c3_ipg_doze_SHIFT (2U)
22459 /*! m33_lpi2c3_ipg_doze - m33_lpi2c3_ipg_doze */
22460 #define CCM_GPR_SHARED11_CLR_m33_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c3_ipg_doze_MASK)
22461 
22462 #define CCM_GPR_SHARED11_CLR_m33_lpi2c4_ipg_doze_MASK (0x8U)
22463 #define CCM_GPR_SHARED11_CLR_m33_lpi2c4_ipg_doze_SHIFT (3U)
22464 /*! m33_lpi2c4_ipg_doze - m33_lpi2c4_ipg_doze */
22465 #define CCM_GPR_SHARED11_CLR_m33_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c4_ipg_doze_MASK)
22466 
22467 #define CCM_GPR_SHARED11_CLR_m33_lpi2c5_ipg_doze_MASK (0x10U)
22468 #define CCM_GPR_SHARED11_CLR_m33_lpi2c5_ipg_doze_SHIFT (4U)
22469 /*! m33_lpi2c5_ipg_doze - m33_lpi2c5_ipg_doze */
22470 #define CCM_GPR_SHARED11_CLR_m33_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c5_ipg_doze_MASK)
22471 
22472 #define CCM_GPR_SHARED11_CLR_m33_lpi2c6_ipg_doze_MASK (0x20U)
22473 #define CCM_GPR_SHARED11_CLR_m33_lpi2c6_ipg_doze_SHIFT (5U)
22474 /*! m33_lpi2c6_ipg_doze - m33_lpi2c6_ipg_doze */
22475 #define CCM_GPR_SHARED11_CLR_m33_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpi2c6_ipg_doze_MASK)
22476 
22477 #define CCM_GPR_SHARED11_CLR_m33_lpspi1_ipg_doze_MASK (0x40U)
22478 #define CCM_GPR_SHARED11_CLR_m33_lpspi1_ipg_doze_SHIFT (6U)
22479 /*! m33_lpspi1_ipg_doze - m33_lpspi1_ipg_doze */
22480 #define CCM_GPR_SHARED11_CLR_m33_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi1_ipg_doze_MASK)
22481 
22482 #define CCM_GPR_SHARED11_CLR_m33_lpspi2_ipg_doze_MASK (0x80U)
22483 #define CCM_GPR_SHARED11_CLR_m33_lpspi2_ipg_doze_SHIFT (7U)
22484 /*! m33_lpspi2_ipg_doze - m33_lpspi2_ipg_doze */
22485 #define CCM_GPR_SHARED11_CLR_m33_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi2_ipg_doze_MASK)
22486 
22487 #define CCM_GPR_SHARED11_CLR_m33_lpspi3_ipg_doze_MASK (0x100U)
22488 #define CCM_GPR_SHARED11_CLR_m33_lpspi3_ipg_doze_SHIFT (8U)
22489 /*! m33_lpspi3_ipg_doze - m33_lpspi3_ipg_doze */
22490 #define CCM_GPR_SHARED11_CLR_m33_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi3_ipg_doze_MASK)
22491 
22492 #define CCM_GPR_SHARED11_CLR_m33_lpspi4_ipg_doze_MASK (0x200U)
22493 #define CCM_GPR_SHARED11_CLR_m33_lpspi4_ipg_doze_SHIFT (9U)
22494 /*! m33_lpspi4_ipg_doze - m33_lpspi4_ipg_doze */
22495 #define CCM_GPR_SHARED11_CLR_m33_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi4_ipg_doze_MASK)
22496 
22497 #define CCM_GPR_SHARED11_CLR_m33_lpspi5_ipg_doze_MASK (0x400U)
22498 #define CCM_GPR_SHARED11_CLR_m33_lpspi5_ipg_doze_SHIFT (10U)
22499 /*! m33_lpspi5_ipg_doze - m33_lpspi5_ipg_doze */
22500 #define CCM_GPR_SHARED11_CLR_m33_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi5_ipg_doze_MASK)
22501 
22502 #define CCM_GPR_SHARED11_CLR_m33_lpspi6_ipg_doze_MASK (0x800U)
22503 #define CCM_GPR_SHARED11_CLR_m33_lpspi6_ipg_doze_SHIFT (11U)
22504 /*! m33_lpspi6_ipg_doze - m33_lpspi6_ipg_doze */
22505 #define CCM_GPR_SHARED11_CLR_m33_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_lpspi6_ipg_doze_MASK)
22506 
22507 #define CCM_GPR_SHARED11_CLR_m33_sinc1_ipg_doze_MASK (0x1000U)
22508 #define CCM_GPR_SHARED11_CLR_m33_sinc1_ipg_doze_SHIFT (12U)
22509 /*! m33_sinc1_ipg_doze - m33_sinc1_ipg_doze */
22510 #define CCM_GPR_SHARED11_CLR_m33_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_sinc1_ipg_doze_MASK)
22511 
22512 #define CCM_GPR_SHARED11_CLR_m33_sinc2_ipg_doze_MASK (0x2000U)
22513 #define CCM_GPR_SHARED11_CLR_m33_sinc2_ipg_doze_SHIFT (13U)
22514 /*! m33_sinc2_ipg_doze - m33_sinc2_ipg_doze */
22515 #define CCM_GPR_SHARED11_CLR_m33_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_sinc2_ipg_doze_MASK)
22516 
22517 #define CCM_GPR_SHARED11_CLR_m33_sinc3_ipg_doze_MASK (0x4000U)
22518 #define CCM_GPR_SHARED11_CLR_m33_sinc3_ipg_doze_SHIFT (14U)
22519 /*! m33_sinc3_ipg_doze - m33_sinc3_ipg_doze */
22520 #define CCM_GPR_SHARED11_CLR_m33_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_sinc3_ipg_doze_MASK)
22521 
22522 #define CCM_GPR_SHARED11_CLR_m33_mic_ipg_doze_MASK (0x8000U)
22523 #define CCM_GPR_SHARED11_CLR_m33_mic_ipg_doze_SHIFT (15U)
22524 /*! m33_mic_ipg_doze - m33_mic_ipg_doze */
22525 #define CCM_GPR_SHARED11_CLR_m33_mic_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_CLR_m33_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_CLR_m33_mic_ipg_doze_MASK)
22526 /*! @} */
22527 
22528 /*! @name GPR_SHARED11_TOG - General Purpose Register */
22529 /*! @{ */
22530 
22531 #define CCM_GPR_SHARED11_TOG_m33_lpi2c1_ipg_doze_MASK (0x1U)
22532 #define CCM_GPR_SHARED11_TOG_m33_lpi2c1_ipg_doze_SHIFT (0U)
22533 /*! m33_lpi2c1_ipg_doze - m33_lpi2c1_ipg_doze */
22534 #define CCM_GPR_SHARED11_TOG_m33_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c1_ipg_doze_MASK)
22535 
22536 #define CCM_GPR_SHARED11_TOG_m33_lpi2c2_ipg_doze_MASK (0x2U)
22537 #define CCM_GPR_SHARED11_TOG_m33_lpi2c2_ipg_doze_SHIFT (1U)
22538 /*! m33_lpi2c2_ipg_doze - m33_lpi2c2_ipg_doze */
22539 #define CCM_GPR_SHARED11_TOG_m33_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c2_ipg_doze_MASK)
22540 
22541 #define CCM_GPR_SHARED11_TOG_m33_lpi2c3_ipg_doze_MASK (0x4U)
22542 #define CCM_GPR_SHARED11_TOG_m33_lpi2c3_ipg_doze_SHIFT (2U)
22543 /*! m33_lpi2c3_ipg_doze - m33_lpi2c3_ipg_doze */
22544 #define CCM_GPR_SHARED11_TOG_m33_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c3_ipg_doze_MASK)
22545 
22546 #define CCM_GPR_SHARED11_TOG_m33_lpi2c4_ipg_doze_MASK (0x8U)
22547 #define CCM_GPR_SHARED11_TOG_m33_lpi2c4_ipg_doze_SHIFT (3U)
22548 /*! m33_lpi2c4_ipg_doze - m33_lpi2c4_ipg_doze */
22549 #define CCM_GPR_SHARED11_TOG_m33_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c4_ipg_doze_MASK)
22550 
22551 #define CCM_GPR_SHARED11_TOG_m33_lpi2c5_ipg_doze_MASK (0x10U)
22552 #define CCM_GPR_SHARED11_TOG_m33_lpi2c5_ipg_doze_SHIFT (4U)
22553 /*! m33_lpi2c5_ipg_doze - m33_lpi2c5_ipg_doze */
22554 #define CCM_GPR_SHARED11_TOG_m33_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c5_ipg_doze_MASK)
22555 
22556 #define CCM_GPR_SHARED11_TOG_m33_lpi2c6_ipg_doze_MASK (0x20U)
22557 #define CCM_GPR_SHARED11_TOG_m33_lpi2c6_ipg_doze_SHIFT (5U)
22558 /*! m33_lpi2c6_ipg_doze - m33_lpi2c6_ipg_doze */
22559 #define CCM_GPR_SHARED11_TOG_m33_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpi2c6_ipg_doze_MASK)
22560 
22561 #define CCM_GPR_SHARED11_TOG_m33_lpspi1_ipg_doze_MASK (0x40U)
22562 #define CCM_GPR_SHARED11_TOG_m33_lpspi1_ipg_doze_SHIFT (6U)
22563 /*! m33_lpspi1_ipg_doze - m33_lpspi1_ipg_doze */
22564 #define CCM_GPR_SHARED11_TOG_m33_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi1_ipg_doze_MASK)
22565 
22566 #define CCM_GPR_SHARED11_TOG_m33_lpspi2_ipg_doze_MASK (0x80U)
22567 #define CCM_GPR_SHARED11_TOG_m33_lpspi2_ipg_doze_SHIFT (7U)
22568 /*! m33_lpspi2_ipg_doze - m33_lpspi2_ipg_doze */
22569 #define CCM_GPR_SHARED11_TOG_m33_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi2_ipg_doze_MASK)
22570 
22571 #define CCM_GPR_SHARED11_TOG_m33_lpspi3_ipg_doze_MASK (0x100U)
22572 #define CCM_GPR_SHARED11_TOG_m33_lpspi3_ipg_doze_SHIFT (8U)
22573 /*! m33_lpspi3_ipg_doze - m33_lpspi3_ipg_doze */
22574 #define CCM_GPR_SHARED11_TOG_m33_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi3_ipg_doze_MASK)
22575 
22576 #define CCM_GPR_SHARED11_TOG_m33_lpspi4_ipg_doze_MASK (0x200U)
22577 #define CCM_GPR_SHARED11_TOG_m33_lpspi4_ipg_doze_SHIFT (9U)
22578 /*! m33_lpspi4_ipg_doze - m33_lpspi4_ipg_doze */
22579 #define CCM_GPR_SHARED11_TOG_m33_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi4_ipg_doze_MASK)
22580 
22581 #define CCM_GPR_SHARED11_TOG_m33_lpspi5_ipg_doze_MASK (0x400U)
22582 #define CCM_GPR_SHARED11_TOG_m33_lpspi5_ipg_doze_SHIFT (10U)
22583 /*! m33_lpspi5_ipg_doze - m33_lpspi5_ipg_doze */
22584 #define CCM_GPR_SHARED11_TOG_m33_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi5_ipg_doze_MASK)
22585 
22586 #define CCM_GPR_SHARED11_TOG_m33_lpspi6_ipg_doze_MASK (0x800U)
22587 #define CCM_GPR_SHARED11_TOG_m33_lpspi6_ipg_doze_SHIFT (11U)
22588 /*! m33_lpspi6_ipg_doze - m33_lpspi6_ipg_doze */
22589 #define CCM_GPR_SHARED11_TOG_m33_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_lpspi6_ipg_doze_MASK)
22590 
22591 #define CCM_GPR_SHARED11_TOG_m33_sinc1_ipg_doze_MASK (0x1000U)
22592 #define CCM_GPR_SHARED11_TOG_m33_sinc1_ipg_doze_SHIFT (12U)
22593 /*! m33_sinc1_ipg_doze - m33_sinc1_ipg_doze */
22594 #define CCM_GPR_SHARED11_TOG_m33_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_sinc1_ipg_doze_MASK)
22595 
22596 #define CCM_GPR_SHARED11_TOG_m33_sinc2_ipg_doze_MASK (0x2000U)
22597 #define CCM_GPR_SHARED11_TOG_m33_sinc2_ipg_doze_SHIFT (13U)
22598 /*! m33_sinc2_ipg_doze - m33_sinc2_ipg_doze */
22599 #define CCM_GPR_SHARED11_TOG_m33_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_sinc2_ipg_doze_MASK)
22600 
22601 #define CCM_GPR_SHARED11_TOG_m33_sinc3_ipg_doze_MASK (0x4000U)
22602 #define CCM_GPR_SHARED11_TOG_m33_sinc3_ipg_doze_SHIFT (14U)
22603 /*! m33_sinc3_ipg_doze - m33_sinc3_ipg_doze */
22604 #define CCM_GPR_SHARED11_TOG_m33_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_sinc3_ipg_doze_MASK)
22605 
22606 #define CCM_GPR_SHARED11_TOG_m33_mic_ipg_doze_MASK (0x8000U)
22607 #define CCM_GPR_SHARED11_TOG_m33_mic_ipg_doze_SHIFT (15U)
22608 /*! m33_mic_ipg_doze - m33_mic_ipg_doze */
22609 #define CCM_GPR_SHARED11_TOG_m33_mic_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_TOG_m33_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED11_TOG_m33_mic_ipg_doze_MASK)
22610 /*! @} */
22611 
22612 /*! @name GPR_SHARED11_AUTHEN - GPR access control */
22613 /*! @{ */
22614 
22615 #define CCM_GPR_SHARED11_AUTHEN_TZ_USER_MASK     (0x100U)
22616 #define CCM_GPR_SHARED11_AUTHEN_TZ_USER_SHIFT    (8U)
22617 /*! TZ_USER - User access permission
22618  *  0b1..Registers of shared GPR slice can be changed in user mode.
22619  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
22620  */
22621 #define CCM_GPR_SHARED11_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TZ_USER_MASK)
22622 
22623 #define CCM_GPR_SHARED11_AUTHEN_TZ_NS_MASK       (0x200U)
22624 #define CCM_GPR_SHARED11_AUTHEN_TZ_NS_SHIFT      (9U)
22625 /*! TZ_NS - Non-secure access permission
22626  *  0b0..Cannot be changed in Non-secure mode.
22627  *  0b1..Can be changed in Non-secure mode.
22628  */
22629 #define CCM_GPR_SHARED11_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TZ_NS_MASK)
22630 
22631 #define CCM_GPR_SHARED11_AUTHEN_LOCK_TZ_MASK     (0x800U)
22632 #define CCM_GPR_SHARED11_AUTHEN_LOCK_TZ_SHIFT    (11U)
22633 /*! LOCK_TZ - Lock TrustZone settings
22634  *  0b0..TrustZone settings is not locked.
22635  *  0b1..TrustZone settings is locked.
22636  */
22637 #define CCM_GPR_SHARED11_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_LOCK_TZ_MASK)
22638 
22639 #define CCM_GPR_SHARED11_AUTHEN_LOCK_LIST_MASK   (0x8000U)
22640 #define CCM_GPR_SHARED11_AUTHEN_LOCK_LIST_SHIFT  (15U)
22641 /*! LOCK_LIST - Lock white list
22642  *  0b0..Whitelist is not locked.
22643  *  0b1..Whitelist is locked.
22644  */
22645 #define CCM_GPR_SHARED11_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_LOCK_LIST_MASK)
22646 
22647 #define CCM_GPR_SHARED11_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
22648 #define CCM_GPR_SHARED11_AUTHEN_WHITE_LIST_SHIFT (16U)
22649 /*! WHITE_LIST - Whitelist settings */
22650 #define CCM_GPR_SHARED11_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_WHITE_LIST_MASK)
22651 /*! @} */
22652 
22653 /*! @name GPR_SHARED11_AUTHEN_SET - GPR access control */
22654 /*! @{ */
22655 
22656 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_USER_MASK (0x100U)
22657 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_USER_SHIFT (8U)
22658 /*! TZ_USER - User access permission */
22659 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_SET_TZ_USER_MASK)
22660 
22661 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_NS_MASK   (0x200U)
22662 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_NS_SHIFT  (9U)
22663 /*! TZ_NS - Non-secure access permission */
22664 #define CCM_GPR_SHARED11_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_SET_TZ_NS_MASK)
22665 
22666 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
22667 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
22668 /*! LOCK_TZ - Lock TrustZone settings */
22669 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_SET_LOCK_TZ_MASK)
22670 
22671 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
22672 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
22673 /*! LOCK_LIST - Lock white list */
22674 #define CCM_GPR_SHARED11_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_SET_LOCK_LIST_MASK)
22675 
22676 #define CCM_GPR_SHARED11_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
22677 #define CCM_GPR_SHARED11_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
22678 /*! WHITE_LIST - Whitelist settings */
22679 #define CCM_GPR_SHARED11_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_SET_WHITE_LIST_MASK)
22680 /*! @} */
22681 
22682 /*! @name GPR_SHARED11_AUTHEN_CLR - GPR access control */
22683 /*! @{ */
22684 
22685 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_USER_MASK (0x100U)
22686 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_USER_SHIFT (8U)
22687 /*! TZ_USER - User access permission */
22688 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_CLR_TZ_USER_MASK)
22689 
22690 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
22691 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
22692 /*! TZ_NS - Non-secure access permission */
22693 #define CCM_GPR_SHARED11_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_CLR_TZ_NS_MASK)
22694 
22695 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
22696 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
22697 /*! LOCK_TZ - Lock TrustZone settings */
22698 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_TZ_MASK)
22699 
22700 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
22701 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
22702 /*! LOCK_LIST - Lock white list */
22703 #define CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_CLR_LOCK_LIST_MASK)
22704 
22705 #define CCM_GPR_SHARED11_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
22706 #define CCM_GPR_SHARED11_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
22707 /*! WHITE_LIST - Whitelist settings */
22708 #define CCM_GPR_SHARED11_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_CLR_WHITE_LIST_MASK)
22709 /*! @} */
22710 
22711 /*! @name GPR_SHARED11_AUTHEN_TOG - GPR access control */
22712 /*! @{ */
22713 
22714 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_USER_MASK (0x100U)
22715 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_USER_SHIFT (8U)
22716 /*! TZ_USER - User access permission */
22717 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TOG_TZ_USER_MASK)
22718 
22719 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
22720 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
22721 /*! TZ_NS - Non-secure access permission */
22722 #define CCM_GPR_SHARED11_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TOG_TZ_NS_MASK)
22723 
22724 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
22725 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
22726 /*! LOCK_TZ - Lock TrustZone settings */
22727 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_TZ_MASK)
22728 
22729 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
22730 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
22731 /*! LOCK_LIST - Lock white list */
22732 #define CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TOG_LOCK_LIST_MASK)
22733 
22734 #define CCM_GPR_SHARED11_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
22735 #define CCM_GPR_SHARED11_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
22736 /*! WHITE_LIST - Whitelist settings */
22737 #define CCM_GPR_SHARED11_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED11_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED11_AUTHEN_TOG_WHITE_LIST_MASK)
22738 /*! @} */
22739 
22740 /*! @name GPR_SHARED12 - General Purpose Register */
22741 /*! @{ */
22742 
22743 #define CCM_GPR_SHARED12_m7_cm7_ipg_stop_MASK    (0x1U)
22744 #define CCM_GPR_SHARED12_m7_cm7_ipg_stop_SHIFT   (0U)
22745 /*! m7_cm7_ipg_stop - m7_cm7_ipg_stop */
22746 #define CCM_GPR_SHARED12_m7_cm7_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_cm7_ipg_stop_MASK)
22747 
22748 #define CCM_GPR_SHARED12_m7_cm33_ipg_stop_MASK   (0x2U)
22749 #define CCM_GPR_SHARED12_m7_cm33_ipg_stop_SHIFT  (1U)
22750 /*! m7_cm33_ipg_stop - m7_cm33_ipg_stop */
22751 #define CCM_GPR_SHARED12_m7_cm33_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_cm33_ipg_stop_MASK)
22752 
22753 #define CCM_GPR_SHARED12_m7_edma3_ipg_stop_MASK  (0x4U)
22754 #define CCM_GPR_SHARED12_m7_edma3_ipg_stop_SHIFT (2U)
22755 /*! m7_edma3_ipg_stop - m7_edma3_ipg_stop */
22756 #define CCM_GPR_SHARED12_m7_edma3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_edma3_ipg_stop_MASK)
22757 
22758 #define CCM_GPR_SHARED12_m7_edma4_ipg_stop_MASK  (0x8U)
22759 #define CCM_GPR_SHARED12_m7_edma4_ipg_stop_SHIFT (3U)
22760 /*! m7_edma4_ipg_stop - m7_edma4_ipg_stop */
22761 #define CCM_GPR_SHARED12_m7_edma4_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_edma4_ipg_stop_MASK)
22762 
22763 #define CCM_GPR_SHARED12_m7_netc_ipg_stop_MASK   (0x10U)
22764 #define CCM_GPR_SHARED12_m7_netc_ipg_stop_SHIFT  (4U)
22765 /*! m7_netc_ipg_stop - m7_netc_ipg_stop */
22766 #define CCM_GPR_SHARED12_m7_netc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_netc_ipg_stop_MASK)
22767 
22768 #define CCM_GPR_SHARED12_m7_sim_aon_ipg_stop_MASK (0x100U)
22769 #define CCM_GPR_SHARED12_m7_sim_aon_ipg_stop_SHIFT (8U)
22770 /*! m7_sim_aon_ipg_stop - m7_sim_aon_ipg_stop */
22771 #define CCM_GPR_SHARED12_m7_sim_aon_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_sim_aon_ipg_stop_MASK)
22772 
22773 #define CCM_GPR_SHARED12_m7_adc1_ipg_stop_MASK   (0x200U)
22774 #define CCM_GPR_SHARED12_m7_adc1_ipg_stop_SHIFT  (9U)
22775 /*! m7_adc1_ipg_stop - m7_adc1_ipg_stop */
22776 #define CCM_GPR_SHARED12_m7_adc1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_adc1_ipg_stop_MASK)
22777 
22778 #define CCM_GPR_SHARED12_m7_adc2_ipg_stop_MASK   (0x400U)
22779 #define CCM_GPR_SHARED12_m7_adc2_ipg_stop_SHIFT  (10U)
22780 /*! m7_adc2_ipg_stop - m7_adc2_ipg_stop */
22781 #define CCM_GPR_SHARED12_m7_adc2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_adc2_ipg_stop_MASK)
22782 
22783 #define CCM_GPR_SHARED12_m7_flexspi1_ipg_stop_MASK (0x800U)
22784 #define CCM_GPR_SHARED12_m7_flexspi1_ipg_stop_SHIFT (11U)
22785 /*! m7_flexspi1_ipg_stop - m7_flexspi1_ipg_stop */
22786 #define CCM_GPR_SHARED12_m7_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_flexspi1_ipg_stop_MASK)
22787 
22788 #define CCM_GPR_SHARED12_m7_flexspi2_ipg_stop_MASK (0x1000U)
22789 #define CCM_GPR_SHARED12_m7_flexspi2_ipg_stop_SHIFT (12U)
22790 /*! m7_flexspi2_ipg_stop - m7_flexspi2_ipg_stop */
22791 #define CCM_GPR_SHARED12_m7_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_flexspi2_ipg_stop_MASK)
22792 
22793 #define CCM_GPR_SHARED12_m7_trdc_ipg_stop_MASK   (0x2000U)
22794 #define CCM_GPR_SHARED12_m7_trdc_ipg_stop_SHIFT  (13U)
22795 /*! m7_trdc_ipg_stop - m7_trdc_ipg_stop */
22796 #define CCM_GPR_SHARED12_m7_trdc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_trdc_ipg_stop_MASK)
22797 
22798 #define CCM_GPR_SHARED12_m7_semc_ipg_stop_MASK   (0x4000U)
22799 #define CCM_GPR_SHARED12_m7_semc_ipg_stop_SHIFT  (14U)
22800 /*! m7_semc_ipg_stop - m7_semc_ipg_stop */
22801 #define CCM_GPR_SHARED12_m7_semc_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_semc_ipg_stop_MASK)
22802 
22803 #define CCM_GPR_SHARED12_m7_iee_ipg_stop_MASK    (0x8000U)
22804 #define CCM_GPR_SHARED12_m7_iee_ipg_stop_SHIFT   (15U)
22805 /*! m7_iee_ipg_stop - m7_iee_ipg_stop */
22806 #define CCM_GPR_SHARED12_m7_iee_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_iee_ipg_stop_MASK)
22807 
22808 #define CCM_GPR_SHARED12_m7_gpio1_ipg_stop_MASK  (0x10000U)
22809 #define CCM_GPR_SHARED12_m7_gpio1_ipg_stop_SHIFT (16U)
22810 /*! m7_gpio1_ipg_stop - m7_gpio1_ipg_stop */
22811 #define CCM_GPR_SHARED12_m7_gpio1_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio1_ipg_stop_MASK)
22812 
22813 #define CCM_GPR_SHARED12_m7_gpio2_ipg_stop_MASK  (0x20000U)
22814 #define CCM_GPR_SHARED12_m7_gpio2_ipg_stop_SHIFT (17U)
22815 /*! m7_gpio2_ipg_stop - m7_gpio2_ipg_stop */
22816 #define CCM_GPR_SHARED12_m7_gpio2_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio2_ipg_stop_MASK)
22817 
22818 #define CCM_GPR_SHARED12_m7_gpio3_ipg_stop_MASK  (0x40000U)
22819 #define CCM_GPR_SHARED12_m7_gpio3_ipg_stop_SHIFT (18U)
22820 /*! m7_gpio3_ipg_stop - m7_gpio3_ipg_stop */
22821 #define CCM_GPR_SHARED12_m7_gpio3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio3_ipg_stop_MASK)
22822 
22823 #define CCM_GPR_SHARED12_m7_gpio4_ipg_stop_MASK  (0x80000U)
22824 #define CCM_GPR_SHARED12_m7_gpio4_ipg_stop_SHIFT (19U)
22825 /*! m7_gpio4_ipg_stop - m7_gpio4_ipg_stop */
22826 #define CCM_GPR_SHARED12_m7_gpio4_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio4_ipg_stop_MASK)
22827 
22828 #define CCM_GPR_SHARED12_m7_gpio5_ipg_stop_MASK  (0x100000U)
22829 #define CCM_GPR_SHARED12_m7_gpio5_ipg_stop_SHIFT (20U)
22830 /*! m7_gpio5_ipg_stop - m7_gpio5_ipg_stop */
22831 #define CCM_GPR_SHARED12_m7_gpio5_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio5_ipg_stop_MASK)
22832 
22833 #define CCM_GPR_SHARED12_m7_gpio6_ipg_stop_MASK  (0x200000U)
22834 #define CCM_GPR_SHARED12_m7_gpio6_ipg_stop_SHIFT (21U)
22835 /*! m7_gpio6_ipg_stop - m7_gpio6_ipg_stop */
22836 #define CCM_GPR_SHARED12_m7_gpio6_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_gpio6_ipg_stop_MASK)
22837 
22838 #define CCM_GPR_SHARED12_m7_flexio1_ipg_stop_MASK (0x400000U)
22839 #define CCM_GPR_SHARED12_m7_flexio1_ipg_stop_SHIFT (22U)
22840 /*! m7_flexio1_ipg_stop - m7_flexio1_ipg_stop */
22841 #define CCM_GPR_SHARED12_m7_flexio1_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_flexio1_ipg_stop_MASK)
22842 
22843 #define CCM_GPR_SHARED12_m7_flexio2_ipg_stop_MASK (0x800000U)
22844 #define CCM_GPR_SHARED12_m7_flexio2_ipg_stop_SHIFT (23U)
22845 /*! m7_flexio2_ipg_stop - m7_flexio2_ipg_stop */
22846 #define CCM_GPR_SHARED12_m7_flexio2_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_flexio2_ipg_stop_MASK)
22847 
22848 #define CCM_GPR_SHARED12_m7_can1_ipg_stop_MASK   (0x1000000U)
22849 #define CCM_GPR_SHARED12_m7_can1_ipg_stop_SHIFT  (24U)
22850 /*! m7_can1_ipg_stop - m7_can1_ipg_stop */
22851 #define CCM_GPR_SHARED12_m7_can1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_can1_ipg_stop_MASK)
22852 
22853 #define CCM_GPR_SHARED12_m7_can2_ipg_stop_MASK   (0x2000000U)
22854 #define CCM_GPR_SHARED12_m7_can2_ipg_stop_SHIFT  (25U)
22855 /*! m7_can2_ipg_stop - m7_can2_ipg_stop */
22856 #define CCM_GPR_SHARED12_m7_can2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_can2_ipg_stop_MASK)
22857 
22858 #define CCM_GPR_SHARED12_m7_can3_ipg_stop_MASK   (0x4000000U)
22859 #define CCM_GPR_SHARED12_m7_can3_ipg_stop_SHIFT  (26U)
22860 /*! m7_can3_ipg_stop - m7_can3_ipg_stop */
22861 #define CCM_GPR_SHARED12_m7_can3_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_can3_ipg_stop_MASK)
22862 
22863 #define CCM_GPR_SHARED12_m7_lpuart1_ipg_stop_MASK (0x8000000U)
22864 #define CCM_GPR_SHARED12_m7_lpuart1_ipg_stop_SHIFT (27U)
22865 /*! m7_lpuart1_ipg_stop - m7_lpuart1_ipg_stop */
22866 #define CCM_GPR_SHARED12_m7_lpuart1_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_lpuart1_ipg_stop_MASK)
22867 
22868 #define CCM_GPR_SHARED12_m7_lpuart2_ipg_stop_MASK (0x10000000U)
22869 #define CCM_GPR_SHARED12_m7_lpuart2_ipg_stop_SHIFT (28U)
22870 /*! m7_lpuart2_ipg_stop - m7_lpuart2_ipg_stop */
22871 #define CCM_GPR_SHARED12_m7_lpuart2_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_lpuart2_ipg_stop_MASK)
22872 
22873 #define CCM_GPR_SHARED12_m7_lpuart3_ipg_stop_MASK (0x20000000U)
22874 #define CCM_GPR_SHARED12_m7_lpuart3_ipg_stop_SHIFT (29U)
22875 /*! m7_lpuart3_ipg_stop - m7_lpuart3_ipg_stop */
22876 #define CCM_GPR_SHARED12_m7_lpuart3_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_lpuart3_ipg_stop_MASK)
22877 
22878 #define CCM_GPR_SHARED12_m7_lpuart4_ipg_stop_MASK (0x40000000U)
22879 #define CCM_GPR_SHARED12_m7_lpuart4_ipg_stop_SHIFT (30U)
22880 /*! m7_lpuart4_ipg_stop - m7_lpuart4_ipg_stop */
22881 #define CCM_GPR_SHARED12_m7_lpuart4_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_lpuart4_ipg_stop_MASK)
22882 
22883 #define CCM_GPR_SHARED12_m7_lpuart5_ipg_stop_MASK (0x80000000U)
22884 #define CCM_GPR_SHARED12_m7_lpuart5_ipg_stop_SHIFT (31U)
22885 /*! m7_lpuart5_ipg_stop - m7_lpuart5_ipg_stop */
22886 #define CCM_GPR_SHARED12_m7_lpuart5_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_m7_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_m7_lpuart5_ipg_stop_MASK)
22887 /*! @} */
22888 
22889 /*! @name GPR_SHARED12_SET - General Purpose Register */
22890 /*! @{ */
22891 
22892 #define CCM_GPR_SHARED12_SET_m7_cm7_ipg_stop_MASK (0x1U)
22893 #define CCM_GPR_SHARED12_SET_m7_cm7_ipg_stop_SHIFT (0U)
22894 /*! m7_cm7_ipg_stop - m7_cm7_ipg_stop */
22895 #define CCM_GPR_SHARED12_SET_m7_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_cm7_ipg_stop_MASK)
22896 
22897 #define CCM_GPR_SHARED12_SET_m7_cm33_ipg_stop_MASK (0x2U)
22898 #define CCM_GPR_SHARED12_SET_m7_cm33_ipg_stop_SHIFT (1U)
22899 /*! m7_cm33_ipg_stop - m7_cm33_ipg_stop */
22900 #define CCM_GPR_SHARED12_SET_m7_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_cm33_ipg_stop_MASK)
22901 
22902 #define CCM_GPR_SHARED12_SET_m7_edma3_ipg_stop_MASK (0x4U)
22903 #define CCM_GPR_SHARED12_SET_m7_edma3_ipg_stop_SHIFT (2U)
22904 /*! m7_edma3_ipg_stop - m7_edma3_ipg_stop */
22905 #define CCM_GPR_SHARED12_SET_m7_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_edma3_ipg_stop_MASK)
22906 
22907 #define CCM_GPR_SHARED12_SET_m7_edma4_ipg_stop_MASK (0x8U)
22908 #define CCM_GPR_SHARED12_SET_m7_edma4_ipg_stop_SHIFT (3U)
22909 /*! m7_edma4_ipg_stop - m7_edma4_ipg_stop */
22910 #define CCM_GPR_SHARED12_SET_m7_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_edma4_ipg_stop_MASK)
22911 
22912 #define CCM_GPR_SHARED12_SET_m7_netc_ipg_stop_MASK (0x10U)
22913 #define CCM_GPR_SHARED12_SET_m7_netc_ipg_stop_SHIFT (4U)
22914 /*! m7_netc_ipg_stop - m7_netc_ipg_stop */
22915 #define CCM_GPR_SHARED12_SET_m7_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_netc_ipg_stop_MASK)
22916 
22917 #define CCM_GPR_SHARED12_SET_m7_sim_aon_ipg_stop_MASK (0x100U)
22918 #define CCM_GPR_SHARED12_SET_m7_sim_aon_ipg_stop_SHIFT (8U)
22919 /*! m7_sim_aon_ipg_stop - m7_sim_aon_ipg_stop */
22920 #define CCM_GPR_SHARED12_SET_m7_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_sim_aon_ipg_stop_MASK)
22921 
22922 #define CCM_GPR_SHARED12_SET_m7_adc1_ipg_stop_MASK (0x200U)
22923 #define CCM_GPR_SHARED12_SET_m7_adc1_ipg_stop_SHIFT (9U)
22924 /*! m7_adc1_ipg_stop - m7_adc1_ipg_stop */
22925 #define CCM_GPR_SHARED12_SET_m7_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_adc1_ipg_stop_MASK)
22926 
22927 #define CCM_GPR_SHARED12_SET_m7_adc2_ipg_stop_MASK (0x400U)
22928 #define CCM_GPR_SHARED12_SET_m7_adc2_ipg_stop_SHIFT (10U)
22929 /*! m7_adc2_ipg_stop - m7_adc2_ipg_stop */
22930 #define CCM_GPR_SHARED12_SET_m7_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_adc2_ipg_stop_MASK)
22931 
22932 #define CCM_GPR_SHARED12_SET_m7_flexspi1_ipg_stop_MASK (0x800U)
22933 #define CCM_GPR_SHARED12_SET_m7_flexspi1_ipg_stop_SHIFT (11U)
22934 /*! m7_flexspi1_ipg_stop - m7_flexspi1_ipg_stop */
22935 #define CCM_GPR_SHARED12_SET_m7_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_flexspi1_ipg_stop_MASK)
22936 
22937 #define CCM_GPR_SHARED12_SET_m7_flexspi2_ipg_stop_MASK (0x1000U)
22938 #define CCM_GPR_SHARED12_SET_m7_flexspi2_ipg_stop_SHIFT (12U)
22939 /*! m7_flexspi2_ipg_stop - m7_flexspi2_ipg_stop */
22940 #define CCM_GPR_SHARED12_SET_m7_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_flexspi2_ipg_stop_MASK)
22941 
22942 #define CCM_GPR_SHARED12_SET_m7_trdc_ipg_stop_MASK (0x2000U)
22943 #define CCM_GPR_SHARED12_SET_m7_trdc_ipg_stop_SHIFT (13U)
22944 /*! m7_trdc_ipg_stop - m7_trdc_ipg_stop */
22945 #define CCM_GPR_SHARED12_SET_m7_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_trdc_ipg_stop_MASK)
22946 
22947 #define CCM_GPR_SHARED12_SET_m7_semc_ipg_stop_MASK (0x4000U)
22948 #define CCM_GPR_SHARED12_SET_m7_semc_ipg_stop_SHIFT (14U)
22949 /*! m7_semc_ipg_stop - m7_semc_ipg_stop */
22950 #define CCM_GPR_SHARED12_SET_m7_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_semc_ipg_stop_MASK)
22951 
22952 #define CCM_GPR_SHARED12_SET_m7_iee_ipg_stop_MASK (0x8000U)
22953 #define CCM_GPR_SHARED12_SET_m7_iee_ipg_stop_SHIFT (15U)
22954 /*! m7_iee_ipg_stop - m7_iee_ipg_stop */
22955 #define CCM_GPR_SHARED12_SET_m7_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_iee_ipg_stop_MASK)
22956 
22957 #define CCM_GPR_SHARED12_SET_m7_gpio1_ipg_stop_MASK (0x10000U)
22958 #define CCM_GPR_SHARED12_SET_m7_gpio1_ipg_stop_SHIFT (16U)
22959 /*! m7_gpio1_ipg_stop - m7_gpio1_ipg_stop */
22960 #define CCM_GPR_SHARED12_SET_m7_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio1_ipg_stop_MASK)
22961 
22962 #define CCM_GPR_SHARED12_SET_m7_gpio2_ipg_stop_MASK (0x20000U)
22963 #define CCM_GPR_SHARED12_SET_m7_gpio2_ipg_stop_SHIFT (17U)
22964 /*! m7_gpio2_ipg_stop - m7_gpio2_ipg_stop */
22965 #define CCM_GPR_SHARED12_SET_m7_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio2_ipg_stop_MASK)
22966 
22967 #define CCM_GPR_SHARED12_SET_m7_gpio3_ipg_stop_MASK (0x40000U)
22968 #define CCM_GPR_SHARED12_SET_m7_gpio3_ipg_stop_SHIFT (18U)
22969 /*! m7_gpio3_ipg_stop - m7_gpio3_ipg_stop */
22970 #define CCM_GPR_SHARED12_SET_m7_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio3_ipg_stop_MASK)
22971 
22972 #define CCM_GPR_SHARED12_SET_m7_gpio4_ipg_stop_MASK (0x80000U)
22973 #define CCM_GPR_SHARED12_SET_m7_gpio4_ipg_stop_SHIFT (19U)
22974 /*! m7_gpio4_ipg_stop - m7_gpio4_ipg_stop */
22975 #define CCM_GPR_SHARED12_SET_m7_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio4_ipg_stop_MASK)
22976 
22977 #define CCM_GPR_SHARED12_SET_m7_gpio5_ipg_stop_MASK (0x100000U)
22978 #define CCM_GPR_SHARED12_SET_m7_gpio5_ipg_stop_SHIFT (20U)
22979 /*! m7_gpio5_ipg_stop - m7_gpio5_ipg_stop */
22980 #define CCM_GPR_SHARED12_SET_m7_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio5_ipg_stop_MASK)
22981 
22982 #define CCM_GPR_SHARED12_SET_m7_gpio6_ipg_stop_MASK (0x200000U)
22983 #define CCM_GPR_SHARED12_SET_m7_gpio6_ipg_stop_SHIFT (21U)
22984 /*! m7_gpio6_ipg_stop - m7_gpio6_ipg_stop */
22985 #define CCM_GPR_SHARED12_SET_m7_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_gpio6_ipg_stop_MASK)
22986 
22987 #define CCM_GPR_SHARED12_SET_m7_flexio1_ipg_stop_MASK (0x400000U)
22988 #define CCM_GPR_SHARED12_SET_m7_flexio1_ipg_stop_SHIFT (22U)
22989 /*! m7_flexio1_ipg_stop - m7_flexio1_ipg_stop */
22990 #define CCM_GPR_SHARED12_SET_m7_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_flexio1_ipg_stop_MASK)
22991 
22992 #define CCM_GPR_SHARED12_SET_m7_flexio2_ipg_stop_MASK (0x800000U)
22993 #define CCM_GPR_SHARED12_SET_m7_flexio2_ipg_stop_SHIFT (23U)
22994 /*! m7_flexio2_ipg_stop - m7_flexio2_ipg_stop */
22995 #define CCM_GPR_SHARED12_SET_m7_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_flexio2_ipg_stop_MASK)
22996 
22997 #define CCM_GPR_SHARED12_SET_m7_can1_ipg_stop_MASK (0x1000000U)
22998 #define CCM_GPR_SHARED12_SET_m7_can1_ipg_stop_SHIFT (24U)
22999 /*! m7_can1_ipg_stop - m7_can1_ipg_stop */
23000 #define CCM_GPR_SHARED12_SET_m7_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_can1_ipg_stop_MASK)
23001 
23002 #define CCM_GPR_SHARED12_SET_m7_can2_ipg_stop_MASK (0x2000000U)
23003 #define CCM_GPR_SHARED12_SET_m7_can2_ipg_stop_SHIFT (25U)
23004 /*! m7_can2_ipg_stop - m7_can2_ipg_stop */
23005 #define CCM_GPR_SHARED12_SET_m7_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_can2_ipg_stop_MASK)
23006 
23007 #define CCM_GPR_SHARED12_SET_m7_can3_ipg_stop_MASK (0x4000000U)
23008 #define CCM_GPR_SHARED12_SET_m7_can3_ipg_stop_SHIFT (26U)
23009 /*! m7_can3_ipg_stop - m7_can3_ipg_stop */
23010 #define CCM_GPR_SHARED12_SET_m7_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_can3_ipg_stop_MASK)
23011 
23012 #define CCM_GPR_SHARED12_SET_m7_lpuart1_ipg_stop_MASK (0x8000000U)
23013 #define CCM_GPR_SHARED12_SET_m7_lpuart1_ipg_stop_SHIFT (27U)
23014 /*! m7_lpuart1_ipg_stop - m7_lpuart1_ipg_stop */
23015 #define CCM_GPR_SHARED12_SET_m7_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_lpuart1_ipg_stop_MASK)
23016 
23017 #define CCM_GPR_SHARED12_SET_m7_lpuart2_ipg_stop_MASK (0x10000000U)
23018 #define CCM_GPR_SHARED12_SET_m7_lpuart2_ipg_stop_SHIFT (28U)
23019 /*! m7_lpuart2_ipg_stop - m7_lpuart2_ipg_stop */
23020 #define CCM_GPR_SHARED12_SET_m7_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_lpuart2_ipg_stop_MASK)
23021 
23022 #define CCM_GPR_SHARED12_SET_m7_lpuart3_ipg_stop_MASK (0x20000000U)
23023 #define CCM_GPR_SHARED12_SET_m7_lpuart3_ipg_stop_SHIFT (29U)
23024 /*! m7_lpuart3_ipg_stop - m7_lpuart3_ipg_stop */
23025 #define CCM_GPR_SHARED12_SET_m7_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_lpuart3_ipg_stop_MASK)
23026 
23027 #define CCM_GPR_SHARED12_SET_m7_lpuart4_ipg_stop_MASK (0x40000000U)
23028 #define CCM_GPR_SHARED12_SET_m7_lpuart4_ipg_stop_SHIFT (30U)
23029 /*! m7_lpuart4_ipg_stop - m7_lpuart4_ipg_stop */
23030 #define CCM_GPR_SHARED12_SET_m7_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_lpuart4_ipg_stop_MASK)
23031 
23032 #define CCM_GPR_SHARED12_SET_m7_lpuart5_ipg_stop_MASK (0x80000000U)
23033 #define CCM_GPR_SHARED12_SET_m7_lpuart5_ipg_stop_SHIFT (31U)
23034 /*! m7_lpuart5_ipg_stop - m7_lpuart5_ipg_stop */
23035 #define CCM_GPR_SHARED12_SET_m7_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_SET_m7_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_SET_m7_lpuart5_ipg_stop_MASK)
23036 /*! @} */
23037 
23038 /*! @name GPR_SHARED12_CLR - General Purpose Register */
23039 /*! @{ */
23040 
23041 #define CCM_GPR_SHARED12_CLR_m7_cm7_ipg_stop_MASK (0x1U)
23042 #define CCM_GPR_SHARED12_CLR_m7_cm7_ipg_stop_SHIFT (0U)
23043 /*! m7_cm7_ipg_stop - m7_cm7_ipg_stop */
23044 #define CCM_GPR_SHARED12_CLR_m7_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_cm7_ipg_stop_MASK)
23045 
23046 #define CCM_GPR_SHARED12_CLR_m7_cm33_ipg_stop_MASK (0x2U)
23047 #define CCM_GPR_SHARED12_CLR_m7_cm33_ipg_stop_SHIFT (1U)
23048 /*! m7_cm33_ipg_stop - m7_cm33_ipg_stop */
23049 #define CCM_GPR_SHARED12_CLR_m7_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_cm33_ipg_stop_MASK)
23050 
23051 #define CCM_GPR_SHARED12_CLR_m7_edma3_ipg_stop_MASK (0x4U)
23052 #define CCM_GPR_SHARED12_CLR_m7_edma3_ipg_stop_SHIFT (2U)
23053 /*! m7_edma3_ipg_stop - m7_edma3_ipg_stop */
23054 #define CCM_GPR_SHARED12_CLR_m7_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_edma3_ipg_stop_MASK)
23055 
23056 #define CCM_GPR_SHARED12_CLR_m7_edma4_ipg_stop_MASK (0x8U)
23057 #define CCM_GPR_SHARED12_CLR_m7_edma4_ipg_stop_SHIFT (3U)
23058 /*! m7_edma4_ipg_stop - m7_edma4_ipg_stop */
23059 #define CCM_GPR_SHARED12_CLR_m7_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_edma4_ipg_stop_MASK)
23060 
23061 #define CCM_GPR_SHARED12_CLR_m7_netc_ipg_stop_MASK (0x10U)
23062 #define CCM_GPR_SHARED12_CLR_m7_netc_ipg_stop_SHIFT (4U)
23063 /*! m7_netc_ipg_stop - m7_netc_ipg_stop */
23064 #define CCM_GPR_SHARED12_CLR_m7_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_netc_ipg_stop_MASK)
23065 
23066 #define CCM_GPR_SHARED12_CLR_m7_sim_aon_ipg_stop_MASK (0x100U)
23067 #define CCM_GPR_SHARED12_CLR_m7_sim_aon_ipg_stop_SHIFT (8U)
23068 /*! m7_sim_aon_ipg_stop - m7_sim_aon_ipg_stop */
23069 #define CCM_GPR_SHARED12_CLR_m7_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_sim_aon_ipg_stop_MASK)
23070 
23071 #define CCM_GPR_SHARED12_CLR_m7_adc1_ipg_stop_MASK (0x200U)
23072 #define CCM_GPR_SHARED12_CLR_m7_adc1_ipg_stop_SHIFT (9U)
23073 /*! m7_adc1_ipg_stop - m7_adc1_ipg_stop */
23074 #define CCM_GPR_SHARED12_CLR_m7_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_adc1_ipg_stop_MASK)
23075 
23076 #define CCM_GPR_SHARED12_CLR_m7_adc2_ipg_stop_MASK (0x400U)
23077 #define CCM_GPR_SHARED12_CLR_m7_adc2_ipg_stop_SHIFT (10U)
23078 /*! m7_adc2_ipg_stop - m7_adc2_ipg_stop */
23079 #define CCM_GPR_SHARED12_CLR_m7_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_adc2_ipg_stop_MASK)
23080 
23081 #define CCM_GPR_SHARED12_CLR_m7_flexspi1_ipg_stop_MASK (0x800U)
23082 #define CCM_GPR_SHARED12_CLR_m7_flexspi1_ipg_stop_SHIFT (11U)
23083 /*! m7_flexspi1_ipg_stop - m7_flexspi1_ipg_stop */
23084 #define CCM_GPR_SHARED12_CLR_m7_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_flexspi1_ipg_stop_MASK)
23085 
23086 #define CCM_GPR_SHARED12_CLR_m7_flexspi2_ipg_stop_MASK (0x1000U)
23087 #define CCM_GPR_SHARED12_CLR_m7_flexspi2_ipg_stop_SHIFT (12U)
23088 /*! m7_flexspi2_ipg_stop - m7_flexspi2_ipg_stop */
23089 #define CCM_GPR_SHARED12_CLR_m7_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_flexspi2_ipg_stop_MASK)
23090 
23091 #define CCM_GPR_SHARED12_CLR_m7_trdc_ipg_stop_MASK (0x2000U)
23092 #define CCM_GPR_SHARED12_CLR_m7_trdc_ipg_stop_SHIFT (13U)
23093 /*! m7_trdc_ipg_stop - m7_trdc_ipg_stop */
23094 #define CCM_GPR_SHARED12_CLR_m7_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_trdc_ipg_stop_MASK)
23095 
23096 #define CCM_GPR_SHARED12_CLR_m7_semc_ipg_stop_MASK (0x4000U)
23097 #define CCM_GPR_SHARED12_CLR_m7_semc_ipg_stop_SHIFT (14U)
23098 /*! m7_semc_ipg_stop - m7_semc_ipg_stop */
23099 #define CCM_GPR_SHARED12_CLR_m7_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_semc_ipg_stop_MASK)
23100 
23101 #define CCM_GPR_SHARED12_CLR_m7_iee_ipg_stop_MASK (0x8000U)
23102 #define CCM_GPR_SHARED12_CLR_m7_iee_ipg_stop_SHIFT (15U)
23103 /*! m7_iee_ipg_stop - m7_iee_ipg_stop */
23104 #define CCM_GPR_SHARED12_CLR_m7_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_iee_ipg_stop_MASK)
23105 
23106 #define CCM_GPR_SHARED12_CLR_m7_gpio1_ipg_stop_MASK (0x10000U)
23107 #define CCM_GPR_SHARED12_CLR_m7_gpio1_ipg_stop_SHIFT (16U)
23108 /*! m7_gpio1_ipg_stop - m7_gpio1_ipg_stop */
23109 #define CCM_GPR_SHARED12_CLR_m7_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio1_ipg_stop_MASK)
23110 
23111 #define CCM_GPR_SHARED12_CLR_m7_gpio2_ipg_stop_MASK (0x20000U)
23112 #define CCM_GPR_SHARED12_CLR_m7_gpio2_ipg_stop_SHIFT (17U)
23113 /*! m7_gpio2_ipg_stop - m7_gpio2_ipg_stop */
23114 #define CCM_GPR_SHARED12_CLR_m7_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio2_ipg_stop_MASK)
23115 
23116 #define CCM_GPR_SHARED12_CLR_m7_gpio3_ipg_stop_MASK (0x40000U)
23117 #define CCM_GPR_SHARED12_CLR_m7_gpio3_ipg_stop_SHIFT (18U)
23118 /*! m7_gpio3_ipg_stop - m7_gpio3_ipg_stop */
23119 #define CCM_GPR_SHARED12_CLR_m7_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio3_ipg_stop_MASK)
23120 
23121 #define CCM_GPR_SHARED12_CLR_m7_gpio4_ipg_stop_MASK (0x80000U)
23122 #define CCM_GPR_SHARED12_CLR_m7_gpio4_ipg_stop_SHIFT (19U)
23123 /*! m7_gpio4_ipg_stop - m7_gpio4_ipg_stop */
23124 #define CCM_GPR_SHARED12_CLR_m7_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio4_ipg_stop_MASK)
23125 
23126 #define CCM_GPR_SHARED12_CLR_m7_gpio5_ipg_stop_MASK (0x100000U)
23127 #define CCM_GPR_SHARED12_CLR_m7_gpio5_ipg_stop_SHIFT (20U)
23128 /*! m7_gpio5_ipg_stop - m7_gpio5_ipg_stop */
23129 #define CCM_GPR_SHARED12_CLR_m7_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio5_ipg_stop_MASK)
23130 
23131 #define CCM_GPR_SHARED12_CLR_m7_gpio6_ipg_stop_MASK (0x200000U)
23132 #define CCM_GPR_SHARED12_CLR_m7_gpio6_ipg_stop_SHIFT (21U)
23133 /*! m7_gpio6_ipg_stop - m7_gpio6_ipg_stop */
23134 #define CCM_GPR_SHARED12_CLR_m7_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_gpio6_ipg_stop_MASK)
23135 
23136 #define CCM_GPR_SHARED12_CLR_m7_flexio1_ipg_stop_MASK (0x400000U)
23137 #define CCM_GPR_SHARED12_CLR_m7_flexio1_ipg_stop_SHIFT (22U)
23138 /*! m7_flexio1_ipg_stop - m7_flexio1_ipg_stop */
23139 #define CCM_GPR_SHARED12_CLR_m7_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_flexio1_ipg_stop_MASK)
23140 
23141 #define CCM_GPR_SHARED12_CLR_m7_flexio2_ipg_stop_MASK (0x800000U)
23142 #define CCM_GPR_SHARED12_CLR_m7_flexio2_ipg_stop_SHIFT (23U)
23143 /*! m7_flexio2_ipg_stop - m7_flexio2_ipg_stop */
23144 #define CCM_GPR_SHARED12_CLR_m7_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_flexio2_ipg_stop_MASK)
23145 
23146 #define CCM_GPR_SHARED12_CLR_m7_can1_ipg_stop_MASK (0x1000000U)
23147 #define CCM_GPR_SHARED12_CLR_m7_can1_ipg_stop_SHIFT (24U)
23148 /*! m7_can1_ipg_stop - m7_can1_ipg_stop */
23149 #define CCM_GPR_SHARED12_CLR_m7_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_can1_ipg_stop_MASK)
23150 
23151 #define CCM_GPR_SHARED12_CLR_m7_can2_ipg_stop_MASK (0x2000000U)
23152 #define CCM_GPR_SHARED12_CLR_m7_can2_ipg_stop_SHIFT (25U)
23153 /*! m7_can2_ipg_stop - m7_can2_ipg_stop */
23154 #define CCM_GPR_SHARED12_CLR_m7_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_can2_ipg_stop_MASK)
23155 
23156 #define CCM_GPR_SHARED12_CLR_m7_can3_ipg_stop_MASK (0x4000000U)
23157 #define CCM_GPR_SHARED12_CLR_m7_can3_ipg_stop_SHIFT (26U)
23158 /*! m7_can3_ipg_stop - m7_can3_ipg_stop */
23159 #define CCM_GPR_SHARED12_CLR_m7_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_can3_ipg_stop_MASK)
23160 
23161 #define CCM_GPR_SHARED12_CLR_m7_lpuart1_ipg_stop_MASK (0x8000000U)
23162 #define CCM_GPR_SHARED12_CLR_m7_lpuart1_ipg_stop_SHIFT (27U)
23163 /*! m7_lpuart1_ipg_stop - m7_lpuart1_ipg_stop */
23164 #define CCM_GPR_SHARED12_CLR_m7_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_lpuart1_ipg_stop_MASK)
23165 
23166 #define CCM_GPR_SHARED12_CLR_m7_lpuart2_ipg_stop_MASK (0x10000000U)
23167 #define CCM_GPR_SHARED12_CLR_m7_lpuart2_ipg_stop_SHIFT (28U)
23168 /*! m7_lpuart2_ipg_stop - m7_lpuart2_ipg_stop */
23169 #define CCM_GPR_SHARED12_CLR_m7_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_lpuart2_ipg_stop_MASK)
23170 
23171 #define CCM_GPR_SHARED12_CLR_m7_lpuart3_ipg_stop_MASK (0x20000000U)
23172 #define CCM_GPR_SHARED12_CLR_m7_lpuart3_ipg_stop_SHIFT (29U)
23173 /*! m7_lpuart3_ipg_stop - m7_lpuart3_ipg_stop */
23174 #define CCM_GPR_SHARED12_CLR_m7_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_lpuart3_ipg_stop_MASK)
23175 
23176 #define CCM_GPR_SHARED12_CLR_m7_lpuart4_ipg_stop_MASK (0x40000000U)
23177 #define CCM_GPR_SHARED12_CLR_m7_lpuart4_ipg_stop_SHIFT (30U)
23178 /*! m7_lpuart4_ipg_stop - m7_lpuart4_ipg_stop */
23179 #define CCM_GPR_SHARED12_CLR_m7_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_lpuart4_ipg_stop_MASK)
23180 
23181 #define CCM_GPR_SHARED12_CLR_m7_lpuart5_ipg_stop_MASK (0x80000000U)
23182 #define CCM_GPR_SHARED12_CLR_m7_lpuart5_ipg_stop_SHIFT (31U)
23183 /*! m7_lpuart5_ipg_stop - m7_lpuart5_ipg_stop */
23184 #define CCM_GPR_SHARED12_CLR_m7_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_CLR_m7_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_CLR_m7_lpuart5_ipg_stop_MASK)
23185 /*! @} */
23186 
23187 /*! @name GPR_SHARED12_TOG - General Purpose Register */
23188 /*! @{ */
23189 
23190 #define CCM_GPR_SHARED12_TOG_m7_cm7_ipg_stop_MASK (0x1U)
23191 #define CCM_GPR_SHARED12_TOG_m7_cm7_ipg_stop_SHIFT (0U)
23192 /*! m7_cm7_ipg_stop - m7_cm7_ipg_stop */
23193 #define CCM_GPR_SHARED12_TOG_m7_cm7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_cm7_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_cm7_ipg_stop_MASK)
23194 
23195 #define CCM_GPR_SHARED12_TOG_m7_cm33_ipg_stop_MASK (0x2U)
23196 #define CCM_GPR_SHARED12_TOG_m7_cm33_ipg_stop_SHIFT (1U)
23197 /*! m7_cm33_ipg_stop - m7_cm33_ipg_stop */
23198 #define CCM_GPR_SHARED12_TOG_m7_cm33_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_cm33_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_cm33_ipg_stop_MASK)
23199 
23200 #define CCM_GPR_SHARED12_TOG_m7_edma3_ipg_stop_MASK (0x4U)
23201 #define CCM_GPR_SHARED12_TOG_m7_edma3_ipg_stop_SHIFT (2U)
23202 /*! m7_edma3_ipg_stop - m7_edma3_ipg_stop */
23203 #define CCM_GPR_SHARED12_TOG_m7_edma3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_edma3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_edma3_ipg_stop_MASK)
23204 
23205 #define CCM_GPR_SHARED12_TOG_m7_edma4_ipg_stop_MASK (0x8U)
23206 #define CCM_GPR_SHARED12_TOG_m7_edma4_ipg_stop_SHIFT (3U)
23207 /*! m7_edma4_ipg_stop - m7_edma4_ipg_stop */
23208 #define CCM_GPR_SHARED12_TOG_m7_edma4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_edma4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_edma4_ipg_stop_MASK)
23209 
23210 #define CCM_GPR_SHARED12_TOG_m7_netc_ipg_stop_MASK (0x10U)
23211 #define CCM_GPR_SHARED12_TOG_m7_netc_ipg_stop_SHIFT (4U)
23212 /*! m7_netc_ipg_stop - m7_netc_ipg_stop */
23213 #define CCM_GPR_SHARED12_TOG_m7_netc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_netc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_netc_ipg_stop_MASK)
23214 
23215 #define CCM_GPR_SHARED12_TOG_m7_sim_aon_ipg_stop_MASK (0x100U)
23216 #define CCM_GPR_SHARED12_TOG_m7_sim_aon_ipg_stop_SHIFT (8U)
23217 /*! m7_sim_aon_ipg_stop - m7_sim_aon_ipg_stop */
23218 #define CCM_GPR_SHARED12_TOG_m7_sim_aon_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_sim_aon_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_sim_aon_ipg_stop_MASK)
23219 
23220 #define CCM_GPR_SHARED12_TOG_m7_adc1_ipg_stop_MASK (0x200U)
23221 #define CCM_GPR_SHARED12_TOG_m7_adc1_ipg_stop_SHIFT (9U)
23222 /*! m7_adc1_ipg_stop - m7_adc1_ipg_stop */
23223 #define CCM_GPR_SHARED12_TOG_m7_adc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_adc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_adc1_ipg_stop_MASK)
23224 
23225 #define CCM_GPR_SHARED12_TOG_m7_adc2_ipg_stop_MASK (0x400U)
23226 #define CCM_GPR_SHARED12_TOG_m7_adc2_ipg_stop_SHIFT (10U)
23227 /*! m7_adc2_ipg_stop - m7_adc2_ipg_stop */
23228 #define CCM_GPR_SHARED12_TOG_m7_adc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_adc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_adc2_ipg_stop_MASK)
23229 
23230 #define CCM_GPR_SHARED12_TOG_m7_flexspi1_ipg_stop_MASK (0x800U)
23231 #define CCM_GPR_SHARED12_TOG_m7_flexspi1_ipg_stop_SHIFT (11U)
23232 /*! m7_flexspi1_ipg_stop - m7_flexspi1_ipg_stop */
23233 #define CCM_GPR_SHARED12_TOG_m7_flexspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_flexspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_flexspi1_ipg_stop_MASK)
23234 
23235 #define CCM_GPR_SHARED12_TOG_m7_flexspi2_ipg_stop_MASK (0x1000U)
23236 #define CCM_GPR_SHARED12_TOG_m7_flexspi2_ipg_stop_SHIFT (12U)
23237 /*! m7_flexspi2_ipg_stop - m7_flexspi2_ipg_stop */
23238 #define CCM_GPR_SHARED12_TOG_m7_flexspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_flexspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_flexspi2_ipg_stop_MASK)
23239 
23240 #define CCM_GPR_SHARED12_TOG_m7_trdc_ipg_stop_MASK (0x2000U)
23241 #define CCM_GPR_SHARED12_TOG_m7_trdc_ipg_stop_SHIFT (13U)
23242 /*! m7_trdc_ipg_stop - m7_trdc_ipg_stop */
23243 #define CCM_GPR_SHARED12_TOG_m7_trdc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_trdc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_trdc_ipg_stop_MASK)
23244 
23245 #define CCM_GPR_SHARED12_TOG_m7_semc_ipg_stop_MASK (0x4000U)
23246 #define CCM_GPR_SHARED12_TOG_m7_semc_ipg_stop_SHIFT (14U)
23247 /*! m7_semc_ipg_stop - m7_semc_ipg_stop */
23248 #define CCM_GPR_SHARED12_TOG_m7_semc_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_semc_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_semc_ipg_stop_MASK)
23249 
23250 #define CCM_GPR_SHARED12_TOG_m7_iee_ipg_stop_MASK (0x8000U)
23251 #define CCM_GPR_SHARED12_TOG_m7_iee_ipg_stop_SHIFT (15U)
23252 /*! m7_iee_ipg_stop - m7_iee_ipg_stop */
23253 #define CCM_GPR_SHARED12_TOG_m7_iee_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_iee_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_iee_ipg_stop_MASK)
23254 
23255 #define CCM_GPR_SHARED12_TOG_m7_gpio1_ipg_stop_MASK (0x10000U)
23256 #define CCM_GPR_SHARED12_TOG_m7_gpio1_ipg_stop_SHIFT (16U)
23257 /*! m7_gpio1_ipg_stop - m7_gpio1_ipg_stop */
23258 #define CCM_GPR_SHARED12_TOG_m7_gpio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio1_ipg_stop_MASK)
23259 
23260 #define CCM_GPR_SHARED12_TOG_m7_gpio2_ipg_stop_MASK (0x20000U)
23261 #define CCM_GPR_SHARED12_TOG_m7_gpio2_ipg_stop_SHIFT (17U)
23262 /*! m7_gpio2_ipg_stop - m7_gpio2_ipg_stop */
23263 #define CCM_GPR_SHARED12_TOG_m7_gpio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio2_ipg_stop_MASK)
23264 
23265 #define CCM_GPR_SHARED12_TOG_m7_gpio3_ipg_stop_MASK (0x40000U)
23266 #define CCM_GPR_SHARED12_TOG_m7_gpio3_ipg_stop_SHIFT (18U)
23267 /*! m7_gpio3_ipg_stop - m7_gpio3_ipg_stop */
23268 #define CCM_GPR_SHARED12_TOG_m7_gpio3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio3_ipg_stop_MASK)
23269 
23270 #define CCM_GPR_SHARED12_TOG_m7_gpio4_ipg_stop_MASK (0x80000U)
23271 #define CCM_GPR_SHARED12_TOG_m7_gpio4_ipg_stop_SHIFT (19U)
23272 /*! m7_gpio4_ipg_stop - m7_gpio4_ipg_stop */
23273 #define CCM_GPR_SHARED12_TOG_m7_gpio4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio4_ipg_stop_MASK)
23274 
23275 #define CCM_GPR_SHARED12_TOG_m7_gpio5_ipg_stop_MASK (0x100000U)
23276 #define CCM_GPR_SHARED12_TOG_m7_gpio5_ipg_stop_SHIFT (20U)
23277 /*! m7_gpio5_ipg_stop - m7_gpio5_ipg_stop */
23278 #define CCM_GPR_SHARED12_TOG_m7_gpio5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio5_ipg_stop_MASK)
23279 
23280 #define CCM_GPR_SHARED12_TOG_m7_gpio6_ipg_stop_MASK (0x200000U)
23281 #define CCM_GPR_SHARED12_TOG_m7_gpio6_ipg_stop_SHIFT (21U)
23282 /*! m7_gpio6_ipg_stop - m7_gpio6_ipg_stop */
23283 #define CCM_GPR_SHARED12_TOG_m7_gpio6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_gpio6_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_gpio6_ipg_stop_MASK)
23284 
23285 #define CCM_GPR_SHARED12_TOG_m7_flexio1_ipg_stop_MASK (0x400000U)
23286 #define CCM_GPR_SHARED12_TOG_m7_flexio1_ipg_stop_SHIFT (22U)
23287 /*! m7_flexio1_ipg_stop - m7_flexio1_ipg_stop */
23288 #define CCM_GPR_SHARED12_TOG_m7_flexio1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_flexio1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_flexio1_ipg_stop_MASK)
23289 
23290 #define CCM_GPR_SHARED12_TOG_m7_flexio2_ipg_stop_MASK (0x800000U)
23291 #define CCM_GPR_SHARED12_TOG_m7_flexio2_ipg_stop_SHIFT (23U)
23292 /*! m7_flexio2_ipg_stop - m7_flexio2_ipg_stop */
23293 #define CCM_GPR_SHARED12_TOG_m7_flexio2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_flexio2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_flexio2_ipg_stop_MASK)
23294 
23295 #define CCM_GPR_SHARED12_TOG_m7_can1_ipg_stop_MASK (0x1000000U)
23296 #define CCM_GPR_SHARED12_TOG_m7_can1_ipg_stop_SHIFT (24U)
23297 /*! m7_can1_ipg_stop - m7_can1_ipg_stop */
23298 #define CCM_GPR_SHARED12_TOG_m7_can1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_can1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_can1_ipg_stop_MASK)
23299 
23300 #define CCM_GPR_SHARED12_TOG_m7_can2_ipg_stop_MASK (0x2000000U)
23301 #define CCM_GPR_SHARED12_TOG_m7_can2_ipg_stop_SHIFT (25U)
23302 /*! m7_can2_ipg_stop - m7_can2_ipg_stop */
23303 #define CCM_GPR_SHARED12_TOG_m7_can2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_can2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_can2_ipg_stop_MASK)
23304 
23305 #define CCM_GPR_SHARED12_TOG_m7_can3_ipg_stop_MASK (0x4000000U)
23306 #define CCM_GPR_SHARED12_TOG_m7_can3_ipg_stop_SHIFT (26U)
23307 /*! m7_can3_ipg_stop - m7_can3_ipg_stop */
23308 #define CCM_GPR_SHARED12_TOG_m7_can3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_can3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_can3_ipg_stop_MASK)
23309 
23310 #define CCM_GPR_SHARED12_TOG_m7_lpuart1_ipg_stop_MASK (0x8000000U)
23311 #define CCM_GPR_SHARED12_TOG_m7_lpuart1_ipg_stop_SHIFT (27U)
23312 /*! m7_lpuart1_ipg_stop - m7_lpuart1_ipg_stop */
23313 #define CCM_GPR_SHARED12_TOG_m7_lpuart1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_lpuart1_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_lpuart1_ipg_stop_MASK)
23314 
23315 #define CCM_GPR_SHARED12_TOG_m7_lpuart2_ipg_stop_MASK (0x10000000U)
23316 #define CCM_GPR_SHARED12_TOG_m7_lpuart2_ipg_stop_SHIFT (28U)
23317 /*! m7_lpuart2_ipg_stop - m7_lpuart2_ipg_stop */
23318 #define CCM_GPR_SHARED12_TOG_m7_lpuart2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_lpuart2_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_lpuart2_ipg_stop_MASK)
23319 
23320 #define CCM_GPR_SHARED12_TOG_m7_lpuart3_ipg_stop_MASK (0x20000000U)
23321 #define CCM_GPR_SHARED12_TOG_m7_lpuart3_ipg_stop_SHIFT (29U)
23322 /*! m7_lpuart3_ipg_stop - m7_lpuart3_ipg_stop */
23323 #define CCM_GPR_SHARED12_TOG_m7_lpuart3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_lpuart3_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_lpuart3_ipg_stop_MASK)
23324 
23325 #define CCM_GPR_SHARED12_TOG_m7_lpuart4_ipg_stop_MASK (0x40000000U)
23326 #define CCM_GPR_SHARED12_TOG_m7_lpuart4_ipg_stop_SHIFT (30U)
23327 /*! m7_lpuart4_ipg_stop - m7_lpuart4_ipg_stop */
23328 #define CCM_GPR_SHARED12_TOG_m7_lpuart4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_lpuart4_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_lpuart4_ipg_stop_MASK)
23329 
23330 #define CCM_GPR_SHARED12_TOG_m7_lpuart5_ipg_stop_MASK (0x80000000U)
23331 #define CCM_GPR_SHARED12_TOG_m7_lpuart5_ipg_stop_SHIFT (31U)
23332 /*! m7_lpuart5_ipg_stop - m7_lpuart5_ipg_stop */
23333 #define CCM_GPR_SHARED12_TOG_m7_lpuart5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_TOG_m7_lpuart5_ipg_stop_SHIFT)) & CCM_GPR_SHARED12_TOG_m7_lpuart5_ipg_stop_MASK)
23334 /*! @} */
23335 
23336 /*! @name GPR_SHARED12_AUTHEN - GPR access control */
23337 /*! @{ */
23338 
23339 #define CCM_GPR_SHARED12_AUTHEN_TZ_USER_MASK     (0x100U)
23340 #define CCM_GPR_SHARED12_AUTHEN_TZ_USER_SHIFT    (8U)
23341 /*! TZ_USER - User access permission
23342  *  0b1..Registers of shared GPR slice can be changed in user mode.
23343  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
23344  */
23345 #define CCM_GPR_SHARED12_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TZ_USER_MASK)
23346 
23347 #define CCM_GPR_SHARED12_AUTHEN_TZ_NS_MASK       (0x200U)
23348 #define CCM_GPR_SHARED12_AUTHEN_TZ_NS_SHIFT      (9U)
23349 /*! TZ_NS - Non-secure access permission
23350  *  0b0..Cannot be changed in Non-secure mode.
23351  *  0b1..Can be changed in Non-secure mode.
23352  */
23353 #define CCM_GPR_SHARED12_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TZ_NS_MASK)
23354 
23355 #define CCM_GPR_SHARED12_AUTHEN_LOCK_TZ_MASK     (0x800U)
23356 #define CCM_GPR_SHARED12_AUTHEN_LOCK_TZ_SHIFT    (11U)
23357 /*! LOCK_TZ - Lock TrustZone settings
23358  *  0b0..TrustZone settings is not locked.
23359  *  0b1..TrustZone settings is locked.
23360  */
23361 #define CCM_GPR_SHARED12_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_LOCK_TZ_MASK)
23362 
23363 #define CCM_GPR_SHARED12_AUTHEN_LOCK_LIST_MASK   (0x8000U)
23364 #define CCM_GPR_SHARED12_AUTHEN_LOCK_LIST_SHIFT  (15U)
23365 /*! LOCK_LIST - Lock white list
23366  *  0b0..Whitelist is not locked.
23367  *  0b1..Whitelist is locked.
23368  */
23369 #define CCM_GPR_SHARED12_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_LOCK_LIST_MASK)
23370 
23371 #define CCM_GPR_SHARED12_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
23372 #define CCM_GPR_SHARED12_AUTHEN_WHITE_LIST_SHIFT (16U)
23373 /*! WHITE_LIST - Whitelist settings */
23374 #define CCM_GPR_SHARED12_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_WHITE_LIST_MASK)
23375 /*! @} */
23376 
23377 /*! @name GPR_SHARED12_AUTHEN_SET - GPR access control */
23378 /*! @{ */
23379 
23380 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_USER_MASK (0x100U)
23381 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_USER_SHIFT (8U)
23382 /*! TZ_USER - User access permission */
23383 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_SET_TZ_USER_MASK)
23384 
23385 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_NS_MASK   (0x200U)
23386 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_NS_SHIFT  (9U)
23387 /*! TZ_NS - Non-secure access permission */
23388 #define CCM_GPR_SHARED12_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_SET_TZ_NS_MASK)
23389 
23390 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
23391 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
23392 /*! LOCK_TZ - Lock TrustZone settings */
23393 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_SET_LOCK_TZ_MASK)
23394 
23395 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
23396 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
23397 /*! LOCK_LIST - Lock white list */
23398 #define CCM_GPR_SHARED12_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_SET_LOCK_LIST_MASK)
23399 
23400 #define CCM_GPR_SHARED12_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
23401 #define CCM_GPR_SHARED12_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
23402 /*! WHITE_LIST - Whitelist settings */
23403 #define CCM_GPR_SHARED12_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_SET_WHITE_LIST_MASK)
23404 /*! @} */
23405 
23406 /*! @name GPR_SHARED12_AUTHEN_CLR - GPR access control */
23407 /*! @{ */
23408 
23409 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_USER_MASK (0x100U)
23410 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_USER_SHIFT (8U)
23411 /*! TZ_USER - User access permission */
23412 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_CLR_TZ_USER_MASK)
23413 
23414 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
23415 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
23416 /*! TZ_NS - Non-secure access permission */
23417 #define CCM_GPR_SHARED12_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_CLR_TZ_NS_MASK)
23418 
23419 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
23420 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
23421 /*! LOCK_TZ - Lock TrustZone settings */
23422 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_TZ_MASK)
23423 
23424 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
23425 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
23426 /*! LOCK_LIST - Lock white list */
23427 #define CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_CLR_LOCK_LIST_MASK)
23428 
23429 #define CCM_GPR_SHARED12_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
23430 #define CCM_GPR_SHARED12_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
23431 /*! WHITE_LIST - Whitelist settings */
23432 #define CCM_GPR_SHARED12_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_CLR_WHITE_LIST_MASK)
23433 /*! @} */
23434 
23435 /*! @name GPR_SHARED12_AUTHEN_TOG - GPR access control */
23436 /*! @{ */
23437 
23438 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_USER_MASK (0x100U)
23439 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_USER_SHIFT (8U)
23440 /*! TZ_USER - User access permission */
23441 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TOG_TZ_USER_MASK)
23442 
23443 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
23444 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
23445 /*! TZ_NS - Non-secure access permission */
23446 #define CCM_GPR_SHARED12_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TOG_TZ_NS_MASK)
23447 
23448 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
23449 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
23450 /*! LOCK_TZ - Lock TrustZone settings */
23451 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_TZ_MASK)
23452 
23453 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
23454 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
23455 /*! LOCK_LIST - Lock white list */
23456 #define CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TOG_LOCK_LIST_MASK)
23457 
23458 #define CCM_GPR_SHARED12_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
23459 #define CCM_GPR_SHARED12_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
23460 /*! WHITE_LIST - Whitelist settings */
23461 #define CCM_GPR_SHARED12_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED12_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED12_AUTHEN_TOG_WHITE_LIST_MASK)
23462 /*! @} */
23463 
23464 /*! @name GPR_SHARED13 - General Purpose Register */
23465 /*! @{ */
23466 
23467 #define CCM_GPR_SHARED13_m7_lpuart6_ipg_stop_MASK (0x1U)
23468 #define CCM_GPR_SHARED13_m7_lpuart6_ipg_stop_SHIFT (0U)
23469 /*! m7_lpuart6_ipg_stop - m7_lpuart6_ipg_stop */
23470 #define CCM_GPR_SHARED13_m7_lpuart6_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart6_ipg_stop_MASK)
23471 
23472 #define CCM_GPR_SHARED13_m7_lpuart7_ipg_stop_MASK (0x2U)
23473 #define CCM_GPR_SHARED13_m7_lpuart7_ipg_stop_SHIFT (1U)
23474 /*! m7_lpuart7_ipg_stop - m7_lpuart7_ipg_stop */
23475 #define CCM_GPR_SHARED13_m7_lpuart7_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart7_ipg_stop_MASK)
23476 
23477 #define CCM_GPR_SHARED13_m7_lpuart8_ipg_stop_MASK (0x4U)
23478 #define CCM_GPR_SHARED13_m7_lpuart8_ipg_stop_SHIFT (2U)
23479 /*! m7_lpuart8_ipg_stop - m7_lpuart8_ipg_stop */
23480 #define CCM_GPR_SHARED13_m7_lpuart8_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart8_ipg_stop_MASK)
23481 
23482 #define CCM_GPR_SHARED13_m7_lpuart9_ipg_stop_MASK (0x8U)
23483 #define CCM_GPR_SHARED13_m7_lpuart9_ipg_stop_SHIFT (3U)
23484 /*! m7_lpuart9_ipg_stop - m7_lpuart9_ipg_stop */
23485 #define CCM_GPR_SHARED13_m7_lpuart9_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart9_ipg_stop_MASK)
23486 
23487 #define CCM_GPR_SHARED13_m7_lpuart10_ipg_stop_MASK (0x10U)
23488 #define CCM_GPR_SHARED13_m7_lpuart10_ipg_stop_SHIFT (4U)
23489 /*! m7_lpuart10_ipg_stop - m7_lpuart10_ipg_stop */
23490 #define CCM_GPR_SHARED13_m7_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart10_ipg_stop_MASK)
23491 
23492 #define CCM_GPR_SHARED13_m7_lpuart11_ipg_stop_MASK (0x20U)
23493 #define CCM_GPR_SHARED13_m7_lpuart11_ipg_stop_SHIFT (5U)
23494 /*! m7_lpuart11_ipg_stop - m7_lpuart11_ipg_stop */
23495 #define CCM_GPR_SHARED13_m7_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart11_ipg_stop_MASK)
23496 
23497 #define CCM_GPR_SHARED13_m7_lpuart12_ipg_stop_MASK (0x40U)
23498 #define CCM_GPR_SHARED13_m7_lpuart12_ipg_stop_SHIFT (6U)
23499 /*! m7_lpuart12_ipg_stop - m7_lpuart12_ipg_stop */
23500 #define CCM_GPR_SHARED13_m7_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpuart12_ipg_stop_MASK)
23501 
23502 #define CCM_GPR_SHARED13_m7_lpi2c1_ipg_stop_MASK (0x80U)
23503 #define CCM_GPR_SHARED13_m7_lpi2c1_ipg_stop_SHIFT (7U)
23504 /*! m7_lpi2c1_ipg_stop - m7_lpi2c1_ipg_stop */
23505 #define CCM_GPR_SHARED13_m7_lpi2c1_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c1_ipg_stop_MASK)
23506 
23507 #define CCM_GPR_SHARED13_m7_lpi2c2_ipg_stop_MASK (0x100U)
23508 #define CCM_GPR_SHARED13_m7_lpi2c2_ipg_stop_SHIFT (8U)
23509 /*! m7_lpi2c2_ipg_stop - m7_lpi2c2_ipg_stop */
23510 #define CCM_GPR_SHARED13_m7_lpi2c2_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c2_ipg_stop_MASK)
23511 
23512 #define CCM_GPR_SHARED13_m7_lpi2c3_ipg_stop_MASK (0x200U)
23513 #define CCM_GPR_SHARED13_m7_lpi2c3_ipg_stop_SHIFT (9U)
23514 /*! m7_lpi2c3_ipg_stop - m7_lpi2c3_ipg_stop */
23515 #define CCM_GPR_SHARED13_m7_lpi2c3_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c3_ipg_stop_MASK)
23516 
23517 #define CCM_GPR_SHARED13_m7_lpi2c4_ipg_stop_MASK (0x400U)
23518 #define CCM_GPR_SHARED13_m7_lpi2c4_ipg_stop_SHIFT (10U)
23519 /*! m7_lpi2c4_ipg_stop - m7_lpi2c4_ipg_stop */
23520 #define CCM_GPR_SHARED13_m7_lpi2c4_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c4_ipg_stop_MASK)
23521 
23522 #define CCM_GPR_SHARED13_m7_lpi2c5_ipg_stop_MASK (0x800U)
23523 #define CCM_GPR_SHARED13_m7_lpi2c5_ipg_stop_SHIFT (11U)
23524 /*! m7_lpi2c5_ipg_stop - m7_lpi2c5_ipg_stop */
23525 #define CCM_GPR_SHARED13_m7_lpi2c5_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c5_ipg_stop_MASK)
23526 
23527 #define CCM_GPR_SHARED13_m7_lpi2c6_ipg_stop_MASK (0x1000U)
23528 #define CCM_GPR_SHARED13_m7_lpi2c6_ipg_stop_SHIFT (12U)
23529 /*! m7_lpi2c6_ipg_stop - m7_lpi2c6_ipg_stop */
23530 #define CCM_GPR_SHARED13_m7_lpi2c6_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpi2c6_ipg_stop_MASK)
23531 
23532 #define CCM_GPR_SHARED13_m7_lpspi1_ipg_stop_MASK (0x2000U)
23533 #define CCM_GPR_SHARED13_m7_lpspi1_ipg_stop_SHIFT (13U)
23534 /*! m7_lpspi1_ipg_stop - m7_lpspi1_ipg_stop */
23535 #define CCM_GPR_SHARED13_m7_lpspi1_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi1_ipg_stop_MASK)
23536 
23537 #define CCM_GPR_SHARED13_m7_lpspi2_ipg_stop_MASK (0x4000U)
23538 #define CCM_GPR_SHARED13_m7_lpspi2_ipg_stop_SHIFT (14U)
23539 /*! m7_lpspi2_ipg_stop - m7_lpspi2_ipg_stop */
23540 #define CCM_GPR_SHARED13_m7_lpspi2_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi2_ipg_stop_MASK)
23541 
23542 #define CCM_GPR_SHARED13_m7_lpspi3_ipg_stop_MASK (0x8000U)
23543 #define CCM_GPR_SHARED13_m7_lpspi3_ipg_stop_SHIFT (15U)
23544 /*! m7_lpspi3_ipg_stop - m7_lpspi3_ipg_stop */
23545 #define CCM_GPR_SHARED13_m7_lpspi3_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi3_ipg_stop_MASK)
23546 
23547 #define CCM_GPR_SHARED13_m7_lpspi4_ipg_stop_MASK (0x10000U)
23548 #define CCM_GPR_SHARED13_m7_lpspi4_ipg_stop_SHIFT (16U)
23549 /*! m7_lpspi4_ipg_stop - m7_lpspi4_ipg_stop */
23550 #define CCM_GPR_SHARED13_m7_lpspi4_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi4_ipg_stop_MASK)
23551 
23552 #define CCM_GPR_SHARED13_m7_lpspi5_ipg_stop_MASK (0x20000U)
23553 #define CCM_GPR_SHARED13_m7_lpspi5_ipg_stop_SHIFT (17U)
23554 /*! m7_lpspi5_ipg_stop - m7_lpspi5_ipg_stop */
23555 #define CCM_GPR_SHARED13_m7_lpspi5_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi5_ipg_stop_MASK)
23556 
23557 #define CCM_GPR_SHARED13_m7_lpspi6_ipg_stop_MASK (0x40000U)
23558 #define CCM_GPR_SHARED13_m7_lpspi6_ipg_stop_SHIFT (18U)
23559 /*! m7_lpspi6_ipg_stop - m7_lpspi6_ipg_stop */
23560 #define CCM_GPR_SHARED13_m7_lpspi6_ipg_stop(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_lpspi6_ipg_stop_MASK)
23561 
23562 #define CCM_GPR_SHARED13_m7_sinc1_ipg_stop_MASK  (0x80000U)
23563 #define CCM_GPR_SHARED13_m7_sinc1_ipg_stop_SHIFT (19U)
23564 /*! m7_sinc1_ipg_stop - m7_sinc1_ipg_stop */
23565 #define CCM_GPR_SHARED13_m7_sinc1_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sinc1_ipg_stop_MASK)
23566 
23567 #define CCM_GPR_SHARED13_m7_sinc2_ipg_stop_MASK  (0x100000U)
23568 #define CCM_GPR_SHARED13_m7_sinc2_ipg_stop_SHIFT (20U)
23569 /*! m7_sinc2_ipg_stop - m7_sinc2_ipg_stop */
23570 #define CCM_GPR_SHARED13_m7_sinc2_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sinc2_ipg_stop_MASK)
23571 
23572 #define CCM_GPR_SHARED13_m7_sinc3_ipg_stop_MASK  (0x200000U)
23573 #define CCM_GPR_SHARED13_m7_sinc3_ipg_stop_SHIFT (21U)
23574 /*! m7_sinc3_ipg_stop - m7_sinc3_ipg_stop */
23575 #define CCM_GPR_SHARED13_m7_sinc3_ipg_stop(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sinc3_ipg_stop_MASK)
23576 
23577 #define CCM_GPR_SHARED13_m7_sai1_ipg_stop_MASK   (0x400000U)
23578 #define CCM_GPR_SHARED13_m7_sai1_ipg_stop_SHIFT  (22U)
23579 /*! m7_sai1_ipg_stop - m7_sai1_ipg_stop */
23580 #define CCM_GPR_SHARED13_m7_sai1_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sai1_ipg_stop_MASK)
23581 
23582 #define CCM_GPR_SHARED13_m7_sai2_ipg_stop_MASK   (0x800000U)
23583 #define CCM_GPR_SHARED13_m7_sai2_ipg_stop_SHIFT  (23U)
23584 /*! m7_sai2_ipg_stop - m7_sai2_ipg_stop */
23585 #define CCM_GPR_SHARED13_m7_sai2_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sai2_ipg_stop_MASK)
23586 
23587 #define CCM_GPR_SHARED13_m7_sai3_ipg_stop_MASK   (0x1000000U)
23588 #define CCM_GPR_SHARED13_m7_sai3_ipg_stop_SHIFT  (24U)
23589 /*! m7_sai3_ipg_stop - m7_sai3_ipg_stop */
23590 #define CCM_GPR_SHARED13_m7_sai3_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sai3_ipg_stop_MASK)
23591 
23592 #define CCM_GPR_SHARED13_m7_sai4_ipg_stop_MASK   (0x2000000U)
23593 #define CCM_GPR_SHARED13_m7_sai4_ipg_stop_SHIFT  (25U)
23594 /*! m7_sai4_ipg_stop - m7_sai4_ipg_stop */
23595 #define CCM_GPR_SHARED13_m7_sai4_ipg_stop(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_sai4_ipg_stop_MASK)
23596 
23597 #define CCM_GPR_SHARED13_m7_mic_ipg_stop_MASK    (0x4000000U)
23598 #define CCM_GPR_SHARED13_m7_mic_ipg_stop_SHIFT   (26U)
23599 /*! m7_mic_ipg_stop - m7_mic_ipg_stop */
23600 #define CCM_GPR_SHARED13_m7_mic_ipg_stop(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_m7_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_m7_mic_ipg_stop_MASK)
23601 /*! @} */
23602 
23603 /*! @name GPR_SHARED13_SET - General Purpose Register */
23604 /*! @{ */
23605 
23606 #define CCM_GPR_SHARED13_SET_m7_lpuart6_ipg_stop_MASK (0x1U)
23607 #define CCM_GPR_SHARED13_SET_m7_lpuart6_ipg_stop_SHIFT (0U)
23608 /*! m7_lpuart6_ipg_stop - m7_lpuart6_ipg_stop */
23609 #define CCM_GPR_SHARED13_SET_m7_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart6_ipg_stop_MASK)
23610 
23611 #define CCM_GPR_SHARED13_SET_m7_lpuart7_ipg_stop_MASK (0x2U)
23612 #define CCM_GPR_SHARED13_SET_m7_lpuart7_ipg_stop_SHIFT (1U)
23613 /*! m7_lpuart7_ipg_stop - m7_lpuart7_ipg_stop */
23614 #define CCM_GPR_SHARED13_SET_m7_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart7_ipg_stop_MASK)
23615 
23616 #define CCM_GPR_SHARED13_SET_m7_lpuart8_ipg_stop_MASK (0x4U)
23617 #define CCM_GPR_SHARED13_SET_m7_lpuart8_ipg_stop_SHIFT (2U)
23618 /*! m7_lpuart8_ipg_stop - m7_lpuart8_ipg_stop */
23619 #define CCM_GPR_SHARED13_SET_m7_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart8_ipg_stop_MASK)
23620 
23621 #define CCM_GPR_SHARED13_SET_m7_lpuart9_ipg_stop_MASK (0x8U)
23622 #define CCM_GPR_SHARED13_SET_m7_lpuart9_ipg_stop_SHIFT (3U)
23623 /*! m7_lpuart9_ipg_stop - m7_lpuart9_ipg_stop */
23624 #define CCM_GPR_SHARED13_SET_m7_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart9_ipg_stop_MASK)
23625 
23626 #define CCM_GPR_SHARED13_SET_m7_lpuart10_ipg_stop_MASK (0x10U)
23627 #define CCM_GPR_SHARED13_SET_m7_lpuart10_ipg_stop_SHIFT (4U)
23628 /*! m7_lpuart10_ipg_stop - m7_lpuart10_ipg_stop */
23629 #define CCM_GPR_SHARED13_SET_m7_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart10_ipg_stop_MASK)
23630 
23631 #define CCM_GPR_SHARED13_SET_m7_lpuart11_ipg_stop_MASK (0x20U)
23632 #define CCM_GPR_SHARED13_SET_m7_lpuart11_ipg_stop_SHIFT (5U)
23633 /*! m7_lpuart11_ipg_stop - m7_lpuart11_ipg_stop */
23634 #define CCM_GPR_SHARED13_SET_m7_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart11_ipg_stop_MASK)
23635 
23636 #define CCM_GPR_SHARED13_SET_m7_lpuart12_ipg_stop_MASK (0x40U)
23637 #define CCM_GPR_SHARED13_SET_m7_lpuart12_ipg_stop_SHIFT (6U)
23638 /*! m7_lpuart12_ipg_stop - m7_lpuart12_ipg_stop */
23639 #define CCM_GPR_SHARED13_SET_m7_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpuart12_ipg_stop_MASK)
23640 
23641 #define CCM_GPR_SHARED13_SET_m7_lpi2c1_ipg_stop_MASK (0x80U)
23642 #define CCM_GPR_SHARED13_SET_m7_lpi2c1_ipg_stop_SHIFT (7U)
23643 /*! m7_lpi2c1_ipg_stop - m7_lpi2c1_ipg_stop */
23644 #define CCM_GPR_SHARED13_SET_m7_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c1_ipg_stop_MASK)
23645 
23646 #define CCM_GPR_SHARED13_SET_m7_lpi2c2_ipg_stop_MASK (0x100U)
23647 #define CCM_GPR_SHARED13_SET_m7_lpi2c2_ipg_stop_SHIFT (8U)
23648 /*! m7_lpi2c2_ipg_stop - m7_lpi2c2_ipg_stop */
23649 #define CCM_GPR_SHARED13_SET_m7_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c2_ipg_stop_MASK)
23650 
23651 #define CCM_GPR_SHARED13_SET_m7_lpi2c3_ipg_stop_MASK (0x200U)
23652 #define CCM_GPR_SHARED13_SET_m7_lpi2c3_ipg_stop_SHIFT (9U)
23653 /*! m7_lpi2c3_ipg_stop - m7_lpi2c3_ipg_stop */
23654 #define CCM_GPR_SHARED13_SET_m7_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c3_ipg_stop_MASK)
23655 
23656 #define CCM_GPR_SHARED13_SET_m7_lpi2c4_ipg_stop_MASK (0x400U)
23657 #define CCM_GPR_SHARED13_SET_m7_lpi2c4_ipg_stop_SHIFT (10U)
23658 /*! m7_lpi2c4_ipg_stop - m7_lpi2c4_ipg_stop */
23659 #define CCM_GPR_SHARED13_SET_m7_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c4_ipg_stop_MASK)
23660 
23661 #define CCM_GPR_SHARED13_SET_m7_lpi2c5_ipg_stop_MASK (0x800U)
23662 #define CCM_GPR_SHARED13_SET_m7_lpi2c5_ipg_stop_SHIFT (11U)
23663 /*! m7_lpi2c5_ipg_stop - m7_lpi2c5_ipg_stop */
23664 #define CCM_GPR_SHARED13_SET_m7_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c5_ipg_stop_MASK)
23665 
23666 #define CCM_GPR_SHARED13_SET_m7_lpi2c6_ipg_stop_MASK (0x1000U)
23667 #define CCM_GPR_SHARED13_SET_m7_lpi2c6_ipg_stop_SHIFT (12U)
23668 /*! m7_lpi2c6_ipg_stop - m7_lpi2c6_ipg_stop */
23669 #define CCM_GPR_SHARED13_SET_m7_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpi2c6_ipg_stop_MASK)
23670 
23671 #define CCM_GPR_SHARED13_SET_m7_lpspi1_ipg_stop_MASK (0x2000U)
23672 #define CCM_GPR_SHARED13_SET_m7_lpspi1_ipg_stop_SHIFT (13U)
23673 /*! m7_lpspi1_ipg_stop - m7_lpspi1_ipg_stop */
23674 #define CCM_GPR_SHARED13_SET_m7_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi1_ipg_stop_MASK)
23675 
23676 #define CCM_GPR_SHARED13_SET_m7_lpspi2_ipg_stop_MASK (0x4000U)
23677 #define CCM_GPR_SHARED13_SET_m7_lpspi2_ipg_stop_SHIFT (14U)
23678 /*! m7_lpspi2_ipg_stop - m7_lpspi2_ipg_stop */
23679 #define CCM_GPR_SHARED13_SET_m7_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi2_ipg_stop_MASK)
23680 
23681 #define CCM_GPR_SHARED13_SET_m7_lpspi3_ipg_stop_MASK (0x8000U)
23682 #define CCM_GPR_SHARED13_SET_m7_lpspi3_ipg_stop_SHIFT (15U)
23683 /*! m7_lpspi3_ipg_stop - m7_lpspi3_ipg_stop */
23684 #define CCM_GPR_SHARED13_SET_m7_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi3_ipg_stop_MASK)
23685 
23686 #define CCM_GPR_SHARED13_SET_m7_lpspi4_ipg_stop_MASK (0x10000U)
23687 #define CCM_GPR_SHARED13_SET_m7_lpspi4_ipg_stop_SHIFT (16U)
23688 /*! m7_lpspi4_ipg_stop - m7_lpspi4_ipg_stop */
23689 #define CCM_GPR_SHARED13_SET_m7_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi4_ipg_stop_MASK)
23690 
23691 #define CCM_GPR_SHARED13_SET_m7_lpspi5_ipg_stop_MASK (0x20000U)
23692 #define CCM_GPR_SHARED13_SET_m7_lpspi5_ipg_stop_SHIFT (17U)
23693 /*! m7_lpspi5_ipg_stop - m7_lpspi5_ipg_stop */
23694 #define CCM_GPR_SHARED13_SET_m7_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi5_ipg_stop_MASK)
23695 
23696 #define CCM_GPR_SHARED13_SET_m7_lpspi6_ipg_stop_MASK (0x40000U)
23697 #define CCM_GPR_SHARED13_SET_m7_lpspi6_ipg_stop_SHIFT (18U)
23698 /*! m7_lpspi6_ipg_stop - m7_lpspi6_ipg_stop */
23699 #define CCM_GPR_SHARED13_SET_m7_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_lpspi6_ipg_stop_MASK)
23700 
23701 #define CCM_GPR_SHARED13_SET_m7_sinc1_ipg_stop_MASK (0x80000U)
23702 #define CCM_GPR_SHARED13_SET_m7_sinc1_ipg_stop_SHIFT (19U)
23703 /*! m7_sinc1_ipg_stop - m7_sinc1_ipg_stop */
23704 #define CCM_GPR_SHARED13_SET_m7_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sinc1_ipg_stop_MASK)
23705 
23706 #define CCM_GPR_SHARED13_SET_m7_sinc2_ipg_stop_MASK (0x100000U)
23707 #define CCM_GPR_SHARED13_SET_m7_sinc2_ipg_stop_SHIFT (20U)
23708 /*! m7_sinc2_ipg_stop - m7_sinc2_ipg_stop */
23709 #define CCM_GPR_SHARED13_SET_m7_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sinc2_ipg_stop_MASK)
23710 
23711 #define CCM_GPR_SHARED13_SET_m7_sinc3_ipg_stop_MASK (0x200000U)
23712 #define CCM_GPR_SHARED13_SET_m7_sinc3_ipg_stop_SHIFT (21U)
23713 /*! m7_sinc3_ipg_stop - m7_sinc3_ipg_stop */
23714 #define CCM_GPR_SHARED13_SET_m7_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sinc3_ipg_stop_MASK)
23715 
23716 #define CCM_GPR_SHARED13_SET_m7_sai1_ipg_stop_MASK (0x400000U)
23717 #define CCM_GPR_SHARED13_SET_m7_sai1_ipg_stop_SHIFT (22U)
23718 /*! m7_sai1_ipg_stop - m7_sai1_ipg_stop */
23719 #define CCM_GPR_SHARED13_SET_m7_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sai1_ipg_stop_MASK)
23720 
23721 #define CCM_GPR_SHARED13_SET_m7_sai2_ipg_stop_MASK (0x800000U)
23722 #define CCM_GPR_SHARED13_SET_m7_sai2_ipg_stop_SHIFT (23U)
23723 /*! m7_sai2_ipg_stop - m7_sai2_ipg_stop */
23724 #define CCM_GPR_SHARED13_SET_m7_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sai2_ipg_stop_MASK)
23725 
23726 #define CCM_GPR_SHARED13_SET_m7_sai3_ipg_stop_MASK (0x1000000U)
23727 #define CCM_GPR_SHARED13_SET_m7_sai3_ipg_stop_SHIFT (24U)
23728 /*! m7_sai3_ipg_stop - m7_sai3_ipg_stop */
23729 #define CCM_GPR_SHARED13_SET_m7_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sai3_ipg_stop_MASK)
23730 
23731 #define CCM_GPR_SHARED13_SET_m7_sai4_ipg_stop_MASK (0x2000000U)
23732 #define CCM_GPR_SHARED13_SET_m7_sai4_ipg_stop_SHIFT (25U)
23733 /*! m7_sai4_ipg_stop - m7_sai4_ipg_stop */
23734 #define CCM_GPR_SHARED13_SET_m7_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_sai4_ipg_stop_MASK)
23735 
23736 #define CCM_GPR_SHARED13_SET_m7_mic_ipg_stop_MASK (0x4000000U)
23737 #define CCM_GPR_SHARED13_SET_m7_mic_ipg_stop_SHIFT (26U)
23738 /*! m7_mic_ipg_stop - m7_mic_ipg_stop */
23739 #define CCM_GPR_SHARED13_SET_m7_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_SET_m7_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_SET_m7_mic_ipg_stop_MASK)
23740 /*! @} */
23741 
23742 /*! @name GPR_SHARED13_CLR - General Purpose Register */
23743 /*! @{ */
23744 
23745 #define CCM_GPR_SHARED13_CLR_m7_lpuart6_ipg_stop_MASK (0x1U)
23746 #define CCM_GPR_SHARED13_CLR_m7_lpuart6_ipg_stop_SHIFT (0U)
23747 /*! m7_lpuart6_ipg_stop - m7_lpuart6_ipg_stop */
23748 #define CCM_GPR_SHARED13_CLR_m7_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart6_ipg_stop_MASK)
23749 
23750 #define CCM_GPR_SHARED13_CLR_m7_lpuart7_ipg_stop_MASK (0x2U)
23751 #define CCM_GPR_SHARED13_CLR_m7_lpuart7_ipg_stop_SHIFT (1U)
23752 /*! m7_lpuart7_ipg_stop - m7_lpuart7_ipg_stop */
23753 #define CCM_GPR_SHARED13_CLR_m7_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart7_ipg_stop_MASK)
23754 
23755 #define CCM_GPR_SHARED13_CLR_m7_lpuart8_ipg_stop_MASK (0x4U)
23756 #define CCM_GPR_SHARED13_CLR_m7_lpuart8_ipg_stop_SHIFT (2U)
23757 /*! m7_lpuart8_ipg_stop - m7_lpuart8_ipg_stop */
23758 #define CCM_GPR_SHARED13_CLR_m7_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart8_ipg_stop_MASK)
23759 
23760 #define CCM_GPR_SHARED13_CLR_m7_lpuart9_ipg_stop_MASK (0x8U)
23761 #define CCM_GPR_SHARED13_CLR_m7_lpuart9_ipg_stop_SHIFT (3U)
23762 /*! m7_lpuart9_ipg_stop - m7_lpuart9_ipg_stop */
23763 #define CCM_GPR_SHARED13_CLR_m7_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart9_ipg_stop_MASK)
23764 
23765 #define CCM_GPR_SHARED13_CLR_m7_lpuart10_ipg_stop_MASK (0x10U)
23766 #define CCM_GPR_SHARED13_CLR_m7_lpuart10_ipg_stop_SHIFT (4U)
23767 /*! m7_lpuart10_ipg_stop - m7_lpuart10_ipg_stop */
23768 #define CCM_GPR_SHARED13_CLR_m7_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart10_ipg_stop_MASK)
23769 
23770 #define CCM_GPR_SHARED13_CLR_m7_lpuart11_ipg_stop_MASK (0x20U)
23771 #define CCM_GPR_SHARED13_CLR_m7_lpuart11_ipg_stop_SHIFT (5U)
23772 /*! m7_lpuart11_ipg_stop - m7_lpuart11_ipg_stop */
23773 #define CCM_GPR_SHARED13_CLR_m7_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart11_ipg_stop_MASK)
23774 
23775 #define CCM_GPR_SHARED13_CLR_m7_lpuart12_ipg_stop_MASK (0x40U)
23776 #define CCM_GPR_SHARED13_CLR_m7_lpuart12_ipg_stop_SHIFT (6U)
23777 /*! m7_lpuart12_ipg_stop - m7_lpuart12_ipg_stop */
23778 #define CCM_GPR_SHARED13_CLR_m7_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpuart12_ipg_stop_MASK)
23779 
23780 #define CCM_GPR_SHARED13_CLR_m7_lpi2c1_ipg_stop_MASK (0x80U)
23781 #define CCM_GPR_SHARED13_CLR_m7_lpi2c1_ipg_stop_SHIFT (7U)
23782 /*! m7_lpi2c1_ipg_stop - m7_lpi2c1_ipg_stop */
23783 #define CCM_GPR_SHARED13_CLR_m7_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c1_ipg_stop_MASK)
23784 
23785 #define CCM_GPR_SHARED13_CLR_m7_lpi2c2_ipg_stop_MASK (0x100U)
23786 #define CCM_GPR_SHARED13_CLR_m7_lpi2c2_ipg_stop_SHIFT (8U)
23787 /*! m7_lpi2c2_ipg_stop - m7_lpi2c2_ipg_stop */
23788 #define CCM_GPR_SHARED13_CLR_m7_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c2_ipg_stop_MASK)
23789 
23790 #define CCM_GPR_SHARED13_CLR_m7_lpi2c3_ipg_stop_MASK (0x200U)
23791 #define CCM_GPR_SHARED13_CLR_m7_lpi2c3_ipg_stop_SHIFT (9U)
23792 /*! m7_lpi2c3_ipg_stop - m7_lpi2c3_ipg_stop */
23793 #define CCM_GPR_SHARED13_CLR_m7_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c3_ipg_stop_MASK)
23794 
23795 #define CCM_GPR_SHARED13_CLR_m7_lpi2c4_ipg_stop_MASK (0x400U)
23796 #define CCM_GPR_SHARED13_CLR_m7_lpi2c4_ipg_stop_SHIFT (10U)
23797 /*! m7_lpi2c4_ipg_stop - m7_lpi2c4_ipg_stop */
23798 #define CCM_GPR_SHARED13_CLR_m7_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c4_ipg_stop_MASK)
23799 
23800 #define CCM_GPR_SHARED13_CLR_m7_lpi2c5_ipg_stop_MASK (0x800U)
23801 #define CCM_GPR_SHARED13_CLR_m7_lpi2c5_ipg_stop_SHIFT (11U)
23802 /*! m7_lpi2c5_ipg_stop - m7_lpi2c5_ipg_stop */
23803 #define CCM_GPR_SHARED13_CLR_m7_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c5_ipg_stop_MASK)
23804 
23805 #define CCM_GPR_SHARED13_CLR_m7_lpi2c6_ipg_stop_MASK (0x1000U)
23806 #define CCM_GPR_SHARED13_CLR_m7_lpi2c6_ipg_stop_SHIFT (12U)
23807 /*! m7_lpi2c6_ipg_stop - m7_lpi2c6_ipg_stop */
23808 #define CCM_GPR_SHARED13_CLR_m7_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpi2c6_ipg_stop_MASK)
23809 
23810 #define CCM_GPR_SHARED13_CLR_m7_lpspi1_ipg_stop_MASK (0x2000U)
23811 #define CCM_GPR_SHARED13_CLR_m7_lpspi1_ipg_stop_SHIFT (13U)
23812 /*! m7_lpspi1_ipg_stop - m7_lpspi1_ipg_stop */
23813 #define CCM_GPR_SHARED13_CLR_m7_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi1_ipg_stop_MASK)
23814 
23815 #define CCM_GPR_SHARED13_CLR_m7_lpspi2_ipg_stop_MASK (0x4000U)
23816 #define CCM_GPR_SHARED13_CLR_m7_lpspi2_ipg_stop_SHIFT (14U)
23817 /*! m7_lpspi2_ipg_stop - m7_lpspi2_ipg_stop */
23818 #define CCM_GPR_SHARED13_CLR_m7_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi2_ipg_stop_MASK)
23819 
23820 #define CCM_GPR_SHARED13_CLR_m7_lpspi3_ipg_stop_MASK (0x8000U)
23821 #define CCM_GPR_SHARED13_CLR_m7_lpspi3_ipg_stop_SHIFT (15U)
23822 /*! m7_lpspi3_ipg_stop - m7_lpspi3_ipg_stop */
23823 #define CCM_GPR_SHARED13_CLR_m7_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi3_ipg_stop_MASK)
23824 
23825 #define CCM_GPR_SHARED13_CLR_m7_lpspi4_ipg_stop_MASK (0x10000U)
23826 #define CCM_GPR_SHARED13_CLR_m7_lpspi4_ipg_stop_SHIFT (16U)
23827 /*! m7_lpspi4_ipg_stop - m7_lpspi4_ipg_stop */
23828 #define CCM_GPR_SHARED13_CLR_m7_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi4_ipg_stop_MASK)
23829 
23830 #define CCM_GPR_SHARED13_CLR_m7_lpspi5_ipg_stop_MASK (0x20000U)
23831 #define CCM_GPR_SHARED13_CLR_m7_lpspi5_ipg_stop_SHIFT (17U)
23832 /*! m7_lpspi5_ipg_stop - m7_lpspi5_ipg_stop */
23833 #define CCM_GPR_SHARED13_CLR_m7_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi5_ipg_stop_MASK)
23834 
23835 #define CCM_GPR_SHARED13_CLR_m7_lpspi6_ipg_stop_MASK (0x40000U)
23836 #define CCM_GPR_SHARED13_CLR_m7_lpspi6_ipg_stop_SHIFT (18U)
23837 /*! m7_lpspi6_ipg_stop - m7_lpspi6_ipg_stop */
23838 #define CCM_GPR_SHARED13_CLR_m7_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_lpspi6_ipg_stop_MASK)
23839 
23840 #define CCM_GPR_SHARED13_CLR_m7_sinc1_ipg_stop_MASK (0x80000U)
23841 #define CCM_GPR_SHARED13_CLR_m7_sinc1_ipg_stop_SHIFT (19U)
23842 /*! m7_sinc1_ipg_stop - m7_sinc1_ipg_stop */
23843 #define CCM_GPR_SHARED13_CLR_m7_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sinc1_ipg_stop_MASK)
23844 
23845 #define CCM_GPR_SHARED13_CLR_m7_sinc2_ipg_stop_MASK (0x100000U)
23846 #define CCM_GPR_SHARED13_CLR_m7_sinc2_ipg_stop_SHIFT (20U)
23847 /*! m7_sinc2_ipg_stop - m7_sinc2_ipg_stop */
23848 #define CCM_GPR_SHARED13_CLR_m7_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sinc2_ipg_stop_MASK)
23849 
23850 #define CCM_GPR_SHARED13_CLR_m7_sinc3_ipg_stop_MASK (0x200000U)
23851 #define CCM_GPR_SHARED13_CLR_m7_sinc3_ipg_stop_SHIFT (21U)
23852 /*! m7_sinc3_ipg_stop - m7_sinc3_ipg_stop */
23853 #define CCM_GPR_SHARED13_CLR_m7_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sinc3_ipg_stop_MASK)
23854 
23855 #define CCM_GPR_SHARED13_CLR_m7_sai1_ipg_stop_MASK (0x400000U)
23856 #define CCM_GPR_SHARED13_CLR_m7_sai1_ipg_stop_SHIFT (22U)
23857 /*! m7_sai1_ipg_stop - m7_sai1_ipg_stop */
23858 #define CCM_GPR_SHARED13_CLR_m7_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sai1_ipg_stop_MASK)
23859 
23860 #define CCM_GPR_SHARED13_CLR_m7_sai2_ipg_stop_MASK (0x800000U)
23861 #define CCM_GPR_SHARED13_CLR_m7_sai2_ipg_stop_SHIFT (23U)
23862 /*! m7_sai2_ipg_stop - m7_sai2_ipg_stop */
23863 #define CCM_GPR_SHARED13_CLR_m7_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sai2_ipg_stop_MASK)
23864 
23865 #define CCM_GPR_SHARED13_CLR_m7_sai3_ipg_stop_MASK (0x1000000U)
23866 #define CCM_GPR_SHARED13_CLR_m7_sai3_ipg_stop_SHIFT (24U)
23867 /*! m7_sai3_ipg_stop - m7_sai3_ipg_stop */
23868 #define CCM_GPR_SHARED13_CLR_m7_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sai3_ipg_stop_MASK)
23869 
23870 #define CCM_GPR_SHARED13_CLR_m7_sai4_ipg_stop_MASK (0x2000000U)
23871 #define CCM_GPR_SHARED13_CLR_m7_sai4_ipg_stop_SHIFT (25U)
23872 /*! m7_sai4_ipg_stop - m7_sai4_ipg_stop */
23873 #define CCM_GPR_SHARED13_CLR_m7_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_sai4_ipg_stop_MASK)
23874 
23875 #define CCM_GPR_SHARED13_CLR_m7_mic_ipg_stop_MASK (0x4000000U)
23876 #define CCM_GPR_SHARED13_CLR_m7_mic_ipg_stop_SHIFT (26U)
23877 /*! m7_mic_ipg_stop - m7_mic_ipg_stop */
23878 #define CCM_GPR_SHARED13_CLR_m7_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_CLR_m7_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_CLR_m7_mic_ipg_stop_MASK)
23879 /*! @} */
23880 
23881 /*! @name GPR_SHARED13_TOG - General Purpose Register */
23882 /*! @{ */
23883 
23884 #define CCM_GPR_SHARED13_TOG_m7_lpuart6_ipg_stop_MASK (0x1U)
23885 #define CCM_GPR_SHARED13_TOG_m7_lpuart6_ipg_stop_SHIFT (0U)
23886 /*! m7_lpuart6_ipg_stop - m7_lpuart6_ipg_stop */
23887 #define CCM_GPR_SHARED13_TOG_m7_lpuart6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart6_ipg_stop_MASK)
23888 
23889 #define CCM_GPR_SHARED13_TOG_m7_lpuart7_ipg_stop_MASK (0x2U)
23890 #define CCM_GPR_SHARED13_TOG_m7_lpuart7_ipg_stop_SHIFT (1U)
23891 /*! m7_lpuart7_ipg_stop - m7_lpuart7_ipg_stop */
23892 #define CCM_GPR_SHARED13_TOG_m7_lpuart7_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart7_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart7_ipg_stop_MASK)
23893 
23894 #define CCM_GPR_SHARED13_TOG_m7_lpuart8_ipg_stop_MASK (0x4U)
23895 #define CCM_GPR_SHARED13_TOG_m7_lpuart8_ipg_stop_SHIFT (2U)
23896 /*! m7_lpuart8_ipg_stop - m7_lpuart8_ipg_stop */
23897 #define CCM_GPR_SHARED13_TOG_m7_lpuart8_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart8_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart8_ipg_stop_MASK)
23898 
23899 #define CCM_GPR_SHARED13_TOG_m7_lpuart9_ipg_stop_MASK (0x8U)
23900 #define CCM_GPR_SHARED13_TOG_m7_lpuart9_ipg_stop_SHIFT (3U)
23901 /*! m7_lpuart9_ipg_stop - m7_lpuart9_ipg_stop */
23902 #define CCM_GPR_SHARED13_TOG_m7_lpuart9_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart9_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart9_ipg_stop_MASK)
23903 
23904 #define CCM_GPR_SHARED13_TOG_m7_lpuart10_ipg_stop_MASK (0x10U)
23905 #define CCM_GPR_SHARED13_TOG_m7_lpuart10_ipg_stop_SHIFT (4U)
23906 /*! m7_lpuart10_ipg_stop - m7_lpuart10_ipg_stop */
23907 #define CCM_GPR_SHARED13_TOG_m7_lpuart10_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart10_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart10_ipg_stop_MASK)
23908 
23909 #define CCM_GPR_SHARED13_TOG_m7_lpuart11_ipg_stop_MASK (0x20U)
23910 #define CCM_GPR_SHARED13_TOG_m7_lpuart11_ipg_stop_SHIFT (5U)
23911 /*! m7_lpuart11_ipg_stop - m7_lpuart11_ipg_stop */
23912 #define CCM_GPR_SHARED13_TOG_m7_lpuart11_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart11_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart11_ipg_stop_MASK)
23913 
23914 #define CCM_GPR_SHARED13_TOG_m7_lpuart12_ipg_stop_MASK (0x40U)
23915 #define CCM_GPR_SHARED13_TOG_m7_lpuart12_ipg_stop_SHIFT (6U)
23916 /*! m7_lpuart12_ipg_stop - m7_lpuart12_ipg_stop */
23917 #define CCM_GPR_SHARED13_TOG_m7_lpuart12_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpuart12_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpuart12_ipg_stop_MASK)
23918 
23919 #define CCM_GPR_SHARED13_TOG_m7_lpi2c1_ipg_stop_MASK (0x80U)
23920 #define CCM_GPR_SHARED13_TOG_m7_lpi2c1_ipg_stop_SHIFT (7U)
23921 /*! m7_lpi2c1_ipg_stop - m7_lpi2c1_ipg_stop */
23922 #define CCM_GPR_SHARED13_TOG_m7_lpi2c1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c1_ipg_stop_MASK)
23923 
23924 #define CCM_GPR_SHARED13_TOG_m7_lpi2c2_ipg_stop_MASK (0x100U)
23925 #define CCM_GPR_SHARED13_TOG_m7_lpi2c2_ipg_stop_SHIFT (8U)
23926 /*! m7_lpi2c2_ipg_stop - m7_lpi2c2_ipg_stop */
23927 #define CCM_GPR_SHARED13_TOG_m7_lpi2c2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c2_ipg_stop_MASK)
23928 
23929 #define CCM_GPR_SHARED13_TOG_m7_lpi2c3_ipg_stop_MASK (0x200U)
23930 #define CCM_GPR_SHARED13_TOG_m7_lpi2c3_ipg_stop_SHIFT (9U)
23931 /*! m7_lpi2c3_ipg_stop - m7_lpi2c3_ipg_stop */
23932 #define CCM_GPR_SHARED13_TOG_m7_lpi2c3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c3_ipg_stop_MASK)
23933 
23934 #define CCM_GPR_SHARED13_TOG_m7_lpi2c4_ipg_stop_MASK (0x400U)
23935 #define CCM_GPR_SHARED13_TOG_m7_lpi2c4_ipg_stop_SHIFT (10U)
23936 /*! m7_lpi2c4_ipg_stop - m7_lpi2c4_ipg_stop */
23937 #define CCM_GPR_SHARED13_TOG_m7_lpi2c4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c4_ipg_stop_MASK)
23938 
23939 #define CCM_GPR_SHARED13_TOG_m7_lpi2c5_ipg_stop_MASK (0x800U)
23940 #define CCM_GPR_SHARED13_TOG_m7_lpi2c5_ipg_stop_SHIFT (11U)
23941 /*! m7_lpi2c5_ipg_stop - m7_lpi2c5_ipg_stop */
23942 #define CCM_GPR_SHARED13_TOG_m7_lpi2c5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c5_ipg_stop_MASK)
23943 
23944 #define CCM_GPR_SHARED13_TOG_m7_lpi2c6_ipg_stop_MASK (0x1000U)
23945 #define CCM_GPR_SHARED13_TOG_m7_lpi2c6_ipg_stop_SHIFT (12U)
23946 /*! m7_lpi2c6_ipg_stop - m7_lpi2c6_ipg_stop */
23947 #define CCM_GPR_SHARED13_TOG_m7_lpi2c6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpi2c6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpi2c6_ipg_stop_MASK)
23948 
23949 #define CCM_GPR_SHARED13_TOG_m7_lpspi1_ipg_stop_MASK (0x2000U)
23950 #define CCM_GPR_SHARED13_TOG_m7_lpspi1_ipg_stop_SHIFT (13U)
23951 /*! m7_lpspi1_ipg_stop - m7_lpspi1_ipg_stop */
23952 #define CCM_GPR_SHARED13_TOG_m7_lpspi1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi1_ipg_stop_MASK)
23953 
23954 #define CCM_GPR_SHARED13_TOG_m7_lpspi2_ipg_stop_MASK (0x4000U)
23955 #define CCM_GPR_SHARED13_TOG_m7_lpspi2_ipg_stop_SHIFT (14U)
23956 /*! m7_lpspi2_ipg_stop - m7_lpspi2_ipg_stop */
23957 #define CCM_GPR_SHARED13_TOG_m7_lpspi2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi2_ipg_stop_MASK)
23958 
23959 #define CCM_GPR_SHARED13_TOG_m7_lpspi3_ipg_stop_MASK (0x8000U)
23960 #define CCM_GPR_SHARED13_TOG_m7_lpspi3_ipg_stop_SHIFT (15U)
23961 /*! m7_lpspi3_ipg_stop - m7_lpspi3_ipg_stop */
23962 #define CCM_GPR_SHARED13_TOG_m7_lpspi3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi3_ipg_stop_MASK)
23963 
23964 #define CCM_GPR_SHARED13_TOG_m7_lpspi4_ipg_stop_MASK (0x10000U)
23965 #define CCM_GPR_SHARED13_TOG_m7_lpspi4_ipg_stop_SHIFT (16U)
23966 /*! m7_lpspi4_ipg_stop - m7_lpspi4_ipg_stop */
23967 #define CCM_GPR_SHARED13_TOG_m7_lpspi4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi4_ipg_stop_MASK)
23968 
23969 #define CCM_GPR_SHARED13_TOG_m7_lpspi5_ipg_stop_MASK (0x20000U)
23970 #define CCM_GPR_SHARED13_TOG_m7_lpspi5_ipg_stop_SHIFT (17U)
23971 /*! m7_lpspi5_ipg_stop - m7_lpspi5_ipg_stop */
23972 #define CCM_GPR_SHARED13_TOG_m7_lpspi5_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi5_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi5_ipg_stop_MASK)
23973 
23974 #define CCM_GPR_SHARED13_TOG_m7_lpspi6_ipg_stop_MASK (0x40000U)
23975 #define CCM_GPR_SHARED13_TOG_m7_lpspi6_ipg_stop_SHIFT (18U)
23976 /*! m7_lpspi6_ipg_stop - m7_lpspi6_ipg_stop */
23977 #define CCM_GPR_SHARED13_TOG_m7_lpspi6_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_lpspi6_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_lpspi6_ipg_stop_MASK)
23978 
23979 #define CCM_GPR_SHARED13_TOG_m7_sinc1_ipg_stop_MASK (0x80000U)
23980 #define CCM_GPR_SHARED13_TOG_m7_sinc1_ipg_stop_SHIFT (19U)
23981 /*! m7_sinc1_ipg_stop - m7_sinc1_ipg_stop */
23982 #define CCM_GPR_SHARED13_TOG_m7_sinc1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sinc1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sinc1_ipg_stop_MASK)
23983 
23984 #define CCM_GPR_SHARED13_TOG_m7_sinc2_ipg_stop_MASK (0x100000U)
23985 #define CCM_GPR_SHARED13_TOG_m7_sinc2_ipg_stop_SHIFT (20U)
23986 /*! m7_sinc2_ipg_stop - m7_sinc2_ipg_stop */
23987 #define CCM_GPR_SHARED13_TOG_m7_sinc2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sinc2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sinc2_ipg_stop_MASK)
23988 
23989 #define CCM_GPR_SHARED13_TOG_m7_sinc3_ipg_stop_MASK (0x200000U)
23990 #define CCM_GPR_SHARED13_TOG_m7_sinc3_ipg_stop_SHIFT (21U)
23991 /*! m7_sinc3_ipg_stop - m7_sinc3_ipg_stop */
23992 #define CCM_GPR_SHARED13_TOG_m7_sinc3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sinc3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sinc3_ipg_stop_MASK)
23993 
23994 #define CCM_GPR_SHARED13_TOG_m7_sai1_ipg_stop_MASK (0x400000U)
23995 #define CCM_GPR_SHARED13_TOG_m7_sai1_ipg_stop_SHIFT (22U)
23996 /*! m7_sai1_ipg_stop - m7_sai1_ipg_stop */
23997 #define CCM_GPR_SHARED13_TOG_m7_sai1_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sai1_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sai1_ipg_stop_MASK)
23998 
23999 #define CCM_GPR_SHARED13_TOG_m7_sai2_ipg_stop_MASK (0x800000U)
24000 #define CCM_GPR_SHARED13_TOG_m7_sai2_ipg_stop_SHIFT (23U)
24001 /*! m7_sai2_ipg_stop - m7_sai2_ipg_stop */
24002 #define CCM_GPR_SHARED13_TOG_m7_sai2_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sai2_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sai2_ipg_stop_MASK)
24003 
24004 #define CCM_GPR_SHARED13_TOG_m7_sai3_ipg_stop_MASK (0x1000000U)
24005 #define CCM_GPR_SHARED13_TOG_m7_sai3_ipg_stop_SHIFT (24U)
24006 /*! m7_sai3_ipg_stop - m7_sai3_ipg_stop */
24007 #define CCM_GPR_SHARED13_TOG_m7_sai3_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sai3_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sai3_ipg_stop_MASK)
24008 
24009 #define CCM_GPR_SHARED13_TOG_m7_sai4_ipg_stop_MASK (0x2000000U)
24010 #define CCM_GPR_SHARED13_TOG_m7_sai4_ipg_stop_SHIFT (25U)
24011 /*! m7_sai4_ipg_stop - m7_sai4_ipg_stop */
24012 #define CCM_GPR_SHARED13_TOG_m7_sai4_ipg_stop(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_sai4_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_sai4_ipg_stop_MASK)
24013 
24014 #define CCM_GPR_SHARED13_TOG_m7_mic_ipg_stop_MASK (0x4000000U)
24015 #define CCM_GPR_SHARED13_TOG_m7_mic_ipg_stop_SHIFT (26U)
24016 /*! m7_mic_ipg_stop - m7_mic_ipg_stop */
24017 #define CCM_GPR_SHARED13_TOG_m7_mic_ipg_stop(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_TOG_m7_mic_ipg_stop_SHIFT)) & CCM_GPR_SHARED13_TOG_m7_mic_ipg_stop_MASK)
24018 /*! @} */
24019 
24020 /*! @name GPR_SHARED13_AUTHEN - GPR access control */
24021 /*! @{ */
24022 
24023 #define CCM_GPR_SHARED13_AUTHEN_TZ_USER_MASK     (0x100U)
24024 #define CCM_GPR_SHARED13_AUTHEN_TZ_USER_SHIFT    (8U)
24025 /*! TZ_USER - User access permission
24026  *  0b1..Registers of shared GPR slice can be changed in user mode.
24027  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
24028  */
24029 #define CCM_GPR_SHARED13_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TZ_USER_MASK)
24030 
24031 #define CCM_GPR_SHARED13_AUTHEN_TZ_NS_MASK       (0x200U)
24032 #define CCM_GPR_SHARED13_AUTHEN_TZ_NS_SHIFT      (9U)
24033 /*! TZ_NS - Non-secure access permission
24034  *  0b0..Cannot be changed in Non-secure mode.
24035  *  0b1..Can be changed in Non-secure mode.
24036  */
24037 #define CCM_GPR_SHARED13_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TZ_NS_MASK)
24038 
24039 #define CCM_GPR_SHARED13_AUTHEN_LOCK_TZ_MASK     (0x800U)
24040 #define CCM_GPR_SHARED13_AUTHEN_LOCK_TZ_SHIFT    (11U)
24041 /*! LOCK_TZ - Lock TrustZone settings
24042  *  0b0..TrustZone settings is not locked.
24043  *  0b1..TrustZone settings is locked.
24044  */
24045 #define CCM_GPR_SHARED13_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_LOCK_TZ_MASK)
24046 
24047 #define CCM_GPR_SHARED13_AUTHEN_LOCK_LIST_MASK   (0x8000U)
24048 #define CCM_GPR_SHARED13_AUTHEN_LOCK_LIST_SHIFT  (15U)
24049 /*! LOCK_LIST - Lock white list
24050  *  0b0..Whitelist is not locked.
24051  *  0b1..Whitelist is locked.
24052  */
24053 #define CCM_GPR_SHARED13_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_LOCK_LIST_MASK)
24054 
24055 #define CCM_GPR_SHARED13_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
24056 #define CCM_GPR_SHARED13_AUTHEN_WHITE_LIST_SHIFT (16U)
24057 /*! WHITE_LIST - Whitelist settings */
24058 #define CCM_GPR_SHARED13_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_WHITE_LIST_MASK)
24059 /*! @} */
24060 
24061 /*! @name GPR_SHARED13_AUTHEN_SET - GPR access control */
24062 /*! @{ */
24063 
24064 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_USER_MASK (0x100U)
24065 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_USER_SHIFT (8U)
24066 /*! TZ_USER - User access permission */
24067 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_SET_TZ_USER_MASK)
24068 
24069 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_NS_MASK   (0x200U)
24070 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_NS_SHIFT  (9U)
24071 /*! TZ_NS - Non-secure access permission */
24072 #define CCM_GPR_SHARED13_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_SET_TZ_NS_MASK)
24073 
24074 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
24075 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
24076 /*! LOCK_TZ - Lock TrustZone settings */
24077 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_SET_LOCK_TZ_MASK)
24078 
24079 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
24080 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
24081 /*! LOCK_LIST - Lock white list */
24082 #define CCM_GPR_SHARED13_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_SET_LOCK_LIST_MASK)
24083 
24084 #define CCM_GPR_SHARED13_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
24085 #define CCM_GPR_SHARED13_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
24086 /*! WHITE_LIST - Whitelist settings */
24087 #define CCM_GPR_SHARED13_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_SET_WHITE_LIST_MASK)
24088 /*! @} */
24089 
24090 /*! @name GPR_SHARED13_AUTHEN_CLR - GPR access control */
24091 /*! @{ */
24092 
24093 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_USER_MASK (0x100U)
24094 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_USER_SHIFT (8U)
24095 /*! TZ_USER - User access permission */
24096 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_CLR_TZ_USER_MASK)
24097 
24098 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
24099 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
24100 /*! TZ_NS - Non-secure access permission */
24101 #define CCM_GPR_SHARED13_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_CLR_TZ_NS_MASK)
24102 
24103 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
24104 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
24105 /*! LOCK_TZ - Lock TrustZone settings */
24106 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_TZ_MASK)
24107 
24108 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
24109 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
24110 /*! LOCK_LIST - Lock white list */
24111 #define CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_CLR_LOCK_LIST_MASK)
24112 
24113 #define CCM_GPR_SHARED13_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
24114 #define CCM_GPR_SHARED13_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
24115 /*! WHITE_LIST - Whitelist settings */
24116 #define CCM_GPR_SHARED13_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_CLR_WHITE_LIST_MASK)
24117 /*! @} */
24118 
24119 /*! @name GPR_SHARED13_AUTHEN_TOG - GPR access control */
24120 /*! @{ */
24121 
24122 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_USER_MASK (0x100U)
24123 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_USER_SHIFT (8U)
24124 /*! TZ_USER - User access permission */
24125 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TOG_TZ_USER_MASK)
24126 
24127 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
24128 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
24129 /*! TZ_NS - Non-secure access permission */
24130 #define CCM_GPR_SHARED13_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TOG_TZ_NS_MASK)
24131 
24132 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
24133 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
24134 /*! LOCK_TZ - Lock TrustZone settings */
24135 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_TZ_MASK)
24136 
24137 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
24138 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
24139 /*! LOCK_LIST - Lock white list */
24140 #define CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TOG_LOCK_LIST_MASK)
24141 
24142 #define CCM_GPR_SHARED13_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
24143 #define CCM_GPR_SHARED13_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
24144 /*! WHITE_LIST - Whitelist settings */
24145 #define CCM_GPR_SHARED13_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED13_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED13_AUTHEN_TOG_WHITE_LIST_MASK)
24146 /*! @} */
24147 
24148 /*! @name GPR_SHARED14 - General Purpose Register */
24149 /*! @{ */
24150 
24151 #define CCM_GPR_SHARED14_m7_adc1_ipg_doze_MASK   (0x1U)
24152 #define CCM_GPR_SHARED14_m7_adc1_ipg_doze_SHIFT  (0U)
24153 /*! m7_adc1_ipg_doze - m7_adc1_ipg_doze */
24154 #define CCM_GPR_SHARED14_m7_adc1_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_adc1_ipg_doze_MASK)
24155 
24156 #define CCM_GPR_SHARED14_m7_adc2_ipg_doze_MASK   (0x2U)
24157 #define CCM_GPR_SHARED14_m7_adc2_ipg_doze_SHIFT  (1U)
24158 /*! m7_adc2_ipg_doze - m7_adc2_ipg_doze */
24159 #define CCM_GPR_SHARED14_m7_adc2_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_adc2_ipg_doze_MASK)
24160 
24161 #define CCM_GPR_SHARED14_m7_flexspi1_ipg_doze_MASK (0x4U)
24162 #define CCM_GPR_SHARED14_m7_flexspi1_ipg_doze_SHIFT (2U)
24163 /*! m7_flexspi1_ipg_doze - m7_flexspi1_ipg_doze */
24164 #define CCM_GPR_SHARED14_m7_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_flexspi1_ipg_doze_MASK)
24165 
24166 #define CCM_GPR_SHARED14_m7_flexspi2_ipg_doze_MASK (0x8U)
24167 #define CCM_GPR_SHARED14_m7_flexspi2_ipg_doze_SHIFT (3U)
24168 /*! m7_flexspi2_ipg_doze - m7_flexspi2_ipg_doze */
24169 #define CCM_GPR_SHARED14_m7_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_flexspi2_ipg_doze_MASK)
24170 
24171 #define CCM_GPR_SHARED14_m7_flexio1_ipg_doze_MASK (0x10U)
24172 #define CCM_GPR_SHARED14_m7_flexio1_ipg_doze_SHIFT (4U)
24173 /*! m7_flexio1_ipg_doze - m7_flexio1_ipg_doze */
24174 #define CCM_GPR_SHARED14_m7_flexio1_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_flexio1_ipg_doze_MASK)
24175 
24176 #define CCM_GPR_SHARED14_m7_flexio2_ipg_doze_MASK (0x20U)
24177 #define CCM_GPR_SHARED14_m7_flexio2_ipg_doze_SHIFT (5U)
24178 /*! m7_flexio2_ipg_doze - m7_flexio2_ipg_doze */
24179 #define CCM_GPR_SHARED14_m7_flexio2_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_flexio2_ipg_doze_MASK)
24180 
24181 #define CCM_GPR_SHARED14_m7_lpit1_ipg_doze_MASK  (0x40U)
24182 #define CCM_GPR_SHARED14_m7_lpit1_ipg_doze_SHIFT (6U)
24183 /*! m7_lpit1_ipg_doze - m7_lpit1_ipg_doze */
24184 #define CCM_GPR_SHARED14_m7_lpit1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpit1_ipg_doze_MASK)
24185 
24186 #define CCM_GPR_SHARED14_m7_lpit2_ipg_doze_MASK  (0x80U)
24187 #define CCM_GPR_SHARED14_m7_lpit2_ipg_doze_SHIFT (7U)
24188 /*! m7_lpit2_ipg_doze - m7_lpit2_ipg_doze */
24189 #define CCM_GPR_SHARED14_m7_lpit2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpit2_ipg_doze_MASK)
24190 
24191 #define CCM_GPR_SHARED14_m7_lpit3_ipg_doze_MASK  (0x100U)
24192 #define CCM_GPR_SHARED14_m7_lpit3_ipg_doze_SHIFT (8U)
24193 /*! m7_lpit3_ipg_doze - m7_lpit3_ipg_doze */
24194 #define CCM_GPR_SHARED14_m7_lpit3_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpit3_ipg_doze_MASK)
24195 
24196 #define CCM_GPR_SHARED14_m7_tpm1_ipg_doze_MASK   (0x200U)
24197 #define CCM_GPR_SHARED14_m7_tpm1_ipg_doze_SHIFT  (9U)
24198 /*! m7_tpm1_ipg_doze - m7_tpm1_ipg_doze */
24199 #define CCM_GPR_SHARED14_m7_tpm1_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm1_ipg_doze_MASK)
24200 
24201 #define CCM_GPR_SHARED14_m7_tpm2_ipg_doze_MASK   (0x400U)
24202 #define CCM_GPR_SHARED14_m7_tpm2_ipg_doze_SHIFT  (10U)
24203 /*! m7_tpm2_ipg_doze - m7_tpm2_ipg_doze */
24204 #define CCM_GPR_SHARED14_m7_tpm2_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm2_ipg_doze_MASK)
24205 
24206 #define CCM_GPR_SHARED14_m7_tpm3_ipg_doze_MASK   (0x800U)
24207 #define CCM_GPR_SHARED14_m7_tpm3_ipg_doze_SHIFT  (11U)
24208 /*! m7_tpm3_ipg_doze - m7_tpm3_ipg_doze */
24209 #define CCM_GPR_SHARED14_m7_tpm3_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm3_ipg_doze_MASK)
24210 
24211 #define CCM_GPR_SHARED14_m7_tpm4_ipg_doze_MASK   (0x1000U)
24212 #define CCM_GPR_SHARED14_m7_tpm4_ipg_doze_SHIFT  (12U)
24213 /*! m7_tpm4_ipg_doze - m7_tpm4_ipg_doze */
24214 #define CCM_GPR_SHARED14_m7_tpm4_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm4_ipg_doze_MASK)
24215 
24216 #define CCM_GPR_SHARED14_m7_tpm5_ipg_doze_MASK   (0x2000U)
24217 #define CCM_GPR_SHARED14_m7_tpm5_ipg_doze_SHIFT  (13U)
24218 /*! m7_tpm5_ipg_doze - m7_tpm5_ipg_doze */
24219 #define CCM_GPR_SHARED14_m7_tpm5_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm5_ipg_doze_MASK)
24220 
24221 #define CCM_GPR_SHARED14_m7_tpm6_ipg_doze_MASK   (0x4000U)
24222 #define CCM_GPR_SHARED14_m7_tpm6_ipg_doze_SHIFT  (14U)
24223 /*! m7_tpm6_ipg_doze - m7_tpm6_ipg_doze */
24224 #define CCM_GPR_SHARED14_m7_tpm6_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_tpm6_ipg_doze_MASK)
24225 
24226 #define CCM_GPR_SHARED14_m7_gpt1_ipg_doze_MASK   (0x8000U)
24227 #define CCM_GPR_SHARED14_m7_gpt1_ipg_doze_SHIFT  (15U)
24228 /*! m7_gpt1_ipg_doze - m7_gpt1_ipg_doze */
24229 #define CCM_GPR_SHARED14_m7_gpt1_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_gpt1_ipg_doze_MASK)
24230 
24231 #define CCM_GPR_SHARED14_m7_gpt2_ipg_doze_MASK   (0x10000U)
24232 #define CCM_GPR_SHARED14_m7_gpt2_ipg_doze_SHIFT  (16U)
24233 /*! m7_gpt2_ipg_doze - m7_gpt2_ipg_doze */
24234 #define CCM_GPR_SHARED14_m7_gpt2_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_gpt2_ipg_doze_MASK)
24235 
24236 #define CCM_GPR_SHARED14_m7_can1_ipg_doze_MASK   (0x20000U)
24237 #define CCM_GPR_SHARED14_m7_can1_ipg_doze_SHIFT  (17U)
24238 /*! m7_can1_ipg_doze - m7_can1_ipg_doze */
24239 #define CCM_GPR_SHARED14_m7_can1_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_can1_ipg_doze_MASK)
24240 
24241 #define CCM_GPR_SHARED14_m7_can2_ipg_doze_MASK   (0x40000U)
24242 #define CCM_GPR_SHARED14_m7_can2_ipg_doze_SHIFT  (18U)
24243 /*! m7_can2_ipg_doze - m7_can2_ipg_doze */
24244 #define CCM_GPR_SHARED14_m7_can2_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_can2_ipg_doze_MASK)
24245 
24246 #define CCM_GPR_SHARED14_m7_can3_ipg_doze_MASK   (0x80000U)
24247 #define CCM_GPR_SHARED14_m7_can3_ipg_doze_SHIFT  (19U)
24248 /*! m7_can3_ipg_doze - m7_can3_ipg_doze */
24249 #define CCM_GPR_SHARED14_m7_can3_ipg_doze(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_can3_ipg_doze_MASK)
24250 
24251 #define CCM_GPR_SHARED14_m7_lpuart1_ipg_doze_MASK (0x100000U)
24252 #define CCM_GPR_SHARED14_m7_lpuart1_ipg_doze_SHIFT (20U)
24253 /*! m7_lpuart1_ipg_doze - m7_lpuart1_ipg_doze */
24254 #define CCM_GPR_SHARED14_m7_lpuart1_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart1_ipg_doze_MASK)
24255 
24256 #define CCM_GPR_SHARED14_m7_lpuart2_ipg_doze_MASK (0x200000U)
24257 #define CCM_GPR_SHARED14_m7_lpuart2_ipg_doze_SHIFT (21U)
24258 /*! m7_lpuart2_ipg_doze - m7_lpuart2_ipg_doze */
24259 #define CCM_GPR_SHARED14_m7_lpuart2_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart2_ipg_doze_MASK)
24260 
24261 #define CCM_GPR_SHARED14_m7_lpuart3_ipg_doze_MASK (0x400000U)
24262 #define CCM_GPR_SHARED14_m7_lpuart3_ipg_doze_SHIFT (22U)
24263 /*! m7_lpuart3_ipg_doze - m7_lpuart3_ipg_doze */
24264 #define CCM_GPR_SHARED14_m7_lpuart3_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart3_ipg_doze_MASK)
24265 
24266 #define CCM_GPR_SHARED14_m7_lpuart4_ipg_doze_MASK (0x800000U)
24267 #define CCM_GPR_SHARED14_m7_lpuart4_ipg_doze_SHIFT (23U)
24268 /*! m7_lpuart4_ipg_doze - m7_lpuart4_ipg_doze */
24269 #define CCM_GPR_SHARED14_m7_lpuart4_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart4_ipg_doze_MASK)
24270 
24271 #define CCM_GPR_SHARED14_m7_lpuart5_ipg_doze_MASK (0x1000000U)
24272 #define CCM_GPR_SHARED14_m7_lpuart5_ipg_doze_SHIFT (24U)
24273 /*! m7_lpuart5_ipg_doze - m7_lpuart5_ipg_doze */
24274 #define CCM_GPR_SHARED14_m7_lpuart5_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart5_ipg_doze_MASK)
24275 
24276 #define CCM_GPR_SHARED14_m7_lpuart6_ipg_doze_MASK (0x2000000U)
24277 #define CCM_GPR_SHARED14_m7_lpuart6_ipg_doze_SHIFT (25U)
24278 /*! m7_lpuart6_ipg_doze - m7_lpuart6_ipg_doze */
24279 #define CCM_GPR_SHARED14_m7_lpuart6_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart6_ipg_doze_MASK)
24280 
24281 #define CCM_GPR_SHARED14_m7_lpuart7_ipg_doze_MASK (0x4000000U)
24282 #define CCM_GPR_SHARED14_m7_lpuart7_ipg_doze_SHIFT (26U)
24283 /*! m7_lpuart7_ipg_doze - m7_lpuart7_ipg_doze */
24284 #define CCM_GPR_SHARED14_m7_lpuart7_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart7_ipg_doze_MASK)
24285 
24286 #define CCM_GPR_SHARED14_m7_lpuart8_ipg_doze_MASK (0x8000000U)
24287 #define CCM_GPR_SHARED14_m7_lpuart8_ipg_doze_SHIFT (27U)
24288 /*! m7_lpuart8_ipg_doze - m7_lpuart8_ipg_doze */
24289 #define CCM_GPR_SHARED14_m7_lpuart8_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart8_ipg_doze_MASK)
24290 
24291 #define CCM_GPR_SHARED14_m7_lpuart9_ipg_doze_MASK (0x10000000U)
24292 #define CCM_GPR_SHARED14_m7_lpuart9_ipg_doze_SHIFT (28U)
24293 /*! m7_lpuart9_ipg_doze - m7_lpuart9_ipg_doze */
24294 #define CCM_GPR_SHARED14_m7_lpuart9_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart9_ipg_doze_MASK)
24295 
24296 #define CCM_GPR_SHARED14_m7_lpuart10_ipg_doze_MASK (0x20000000U)
24297 #define CCM_GPR_SHARED14_m7_lpuart10_ipg_doze_SHIFT (29U)
24298 /*! m7_lpuart10_ipg_doze - m7_lpuart10_ipg_doze */
24299 #define CCM_GPR_SHARED14_m7_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart10_ipg_doze_MASK)
24300 
24301 #define CCM_GPR_SHARED14_m7_lpuart11_ipg_doze_MASK (0x40000000U)
24302 #define CCM_GPR_SHARED14_m7_lpuart11_ipg_doze_SHIFT (30U)
24303 /*! m7_lpuart11_ipg_doze - m7_lpuart11_ipg_doze */
24304 #define CCM_GPR_SHARED14_m7_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart11_ipg_doze_MASK)
24305 
24306 #define CCM_GPR_SHARED14_m7_lpuart12_ipg_doze_MASK (0x80000000U)
24307 #define CCM_GPR_SHARED14_m7_lpuart12_ipg_doze_SHIFT (31U)
24308 /*! m7_lpuart12_ipg_doze - m7_lpuart12_ipg_doze */
24309 #define CCM_GPR_SHARED14_m7_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_m7_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_m7_lpuart12_ipg_doze_MASK)
24310 /*! @} */
24311 
24312 /*! @name GPR_SHARED14_SET - General Purpose Register */
24313 /*! @{ */
24314 
24315 #define CCM_GPR_SHARED14_SET_m7_adc1_ipg_doze_MASK (0x1U)
24316 #define CCM_GPR_SHARED14_SET_m7_adc1_ipg_doze_SHIFT (0U)
24317 /*! m7_adc1_ipg_doze - m7_adc1_ipg_doze */
24318 #define CCM_GPR_SHARED14_SET_m7_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_adc1_ipg_doze_MASK)
24319 
24320 #define CCM_GPR_SHARED14_SET_m7_adc2_ipg_doze_MASK (0x2U)
24321 #define CCM_GPR_SHARED14_SET_m7_adc2_ipg_doze_SHIFT (1U)
24322 /*! m7_adc2_ipg_doze - m7_adc2_ipg_doze */
24323 #define CCM_GPR_SHARED14_SET_m7_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_adc2_ipg_doze_MASK)
24324 
24325 #define CCM_GPR_SHARED14_SET_m7_flexspi1_ipg_doze_MASK (0x4U)
24326 #define CCM_GPR_SHARED14_SET_m7_flexspi1_ipg_doze_SHIFT (2U)
24327 /*! m7_flexspi1_ipg_doze - m7_flexspi1_ipg_doze */
24328 #define CCM_GPR_SHARED14_SET_m7_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_flexspi1_ipg_doze_MASK)
24329 
24330 #define CCM_GPR_SHARED14_SET_m7_flexspi2_ipg_doze_MASK (0x8U)
24331 #define CCM_GPR_SHARED14_SET_m7_flexspi2_ipg_doze_SHIFT (3U)
24332 /*! m7_flexspi2_ipg_doze - m7_flexspi2_ipg_doze */
24333 #define CCM_GPR_SHARED14_SET_m7_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_flexspi2_ipg_doze_MASK)
24334 
24335 #define CCM_GPR_SHARED14_SET_m7_flexio1_ipg_doze_MASK (0x10U)
24336 #define CCM_GPR_SHARED14_SET_m7_flexio1_ipg_doze_SHIFT (4U)
24337 /*! m7_flexio1_ipg_doze - m7_flexio1_ipg_doze */
24338 #define CCM_GPR_SHARED14_SET_m7_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_flexio1_ipg_doze_MASK)
24339 
24340 #define CCM_GPR_SHARED14_SET_m7_flexio2_ipg_doze_MASK (0x20U)
24341 #define CCM_GPR_SHARED14_SET_m7_flexio2_ipg_doze_SHIFT (5U)
24342 /*! m7_flexio2_ipg_doze - m7_flexio2_ipg_doze */
24343 #define CCM_GPR_SHARED14_SET_m7_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_flexio2_ipg_doze_MASK)
24344 
24345 #define CCM_GPR_SHARED14_SET_m7_lpit1_ipg_doze_MASK (0x40U)
24346 #define CCM_GPR_SHARED14_SET_m7_lpit1_ipg_doze_SHIFT (6U)
24347 /*! m7_lpit1_ipg_doze - m7_lpit1_ipg_doze */
24348 #define CCM_GPR_SHARED14_SET_m7_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpit1_ipg_doze_MASK)
24349 
24350 #define CCM_GPR_SHARED14_SET_m7_lpit2_ipg_doze_MASK (0x80U)
24351 #define CCM_GPR_SHARED14_SET_m7_lpit2_ipg_doze_SHIFT (7U)
24352 /*! m7_lpit2_ipg_doze - m7_lpit2_ipg_doze */
24353 #define CCM_GPR_SHARED14_SET_m7_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpit2_ipg_doze_MASK)
24354 
24355 #define CCM_GPR_SHARED14_SET_m7_lpit3_ipg_doze_MASK (0x100U)
24356 #define CCM_GPR_SHARED14_SET_m7_lpit3_ipg_doze_SHIFT (8U)
24357 /*! m7_lpit3_ipg_doze - m7_lpit3_ipg_doze */
24358 #define CCM_GPR_SHARED14_SET_m7_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpit3_ipg_doze_MASK)
24359 
24360 #define CCM_GPR_SHARED14_SET_m7_tpm1_ipg_doze_MASK (0x200U)
24361 #define CCM_GPR_SHARED14_SET_m7_tpm1_ipg_doze_SHIFT (9U)
24362 /*! m7_tpm1_ipg_doze - m7_tpm1_ipg_doze */
24363 #define CCM_GPR_SHARED14_SET_m7_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm1_ipg_doze_MASK)
24364 
24365 #define CCM_GPR_SHARED14_SET_m7_tpm2_ipg_doze_MASK (0x400U)
24366 #define CCM_GPR_SHARED14_SET_m7_tpm2_ipg_doze_SHIFT (10U)
24367 /*! m7_tpm2_ipg_doze - m7_tpm2_ipg_doze */
24368 #define CCM_GPR_SHARED14_SET_m7_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm2_ipg_doze_MASK)
24369 
24370 #define CCM_GPR_SHARED14_SET_m7_tpm3_ipg_doze_MASK (0x800U)
24371 #define CCM_GPR_SHARED14_SET_m7_tpm3_ipg_doze_SHIFT (11U)
24372 /*! m7_tpm3_ipg_doze - m7_tpm3_ipg_doze */
24373 #define CCM_GPR_SHARED14_SET_m7_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm3_ipg_doze_MASK)
24374 
24375 #define CCM_GPR_SHARED14_SET_m7_tpm4_ipg_doze_MASK (0x1000U)
24376 #define CCM_GPR_SHARED14_SET_m7_tpm4_ipg_doze_SHIFT (12U)
24377 /*! m7_tpm4_ipg_doze - m7_tpm4_ipg_doze */
24378 #define CCM_GPR_SHARED14_SET_m7_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm4_ipg_doze_MASK)
24379 
24380 #define CCM_GPR_SHARED14_SET_m7_tpm5_ipg_doze_MASK (0x2000U)
24381 #define CCM_GPR_SHARED14_SET_m7_tpm5_ipg_doze_SHIFT (13U)
24382 /*! m7_tpm5_ipg_doze - m7_tpm5_ipg_doze */
24383 #define CCM_GPR_SHARED14_SET_m7_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm5_ipg_doze_MASK)
24384 
24385 #define CCM_GPR_SHARED14_SET_m7_tpm6_ipg_doze_MASK (0x4000U)
24386 #define CCM_GPR_SHARED14_SET_m7_tpm6_ipg_doze_SHIFT (14U)
24387 /*! m7_tpm6_ipg_doze - m7_tpm6_ipg_doze */
24388 #define CCM_GPR_SHARED14_SET_m7_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_tpm6_ipg_doze_MASK)
24389 
24390 #define CCM_GPR_SHARED14_SET_m7_gpt1_ipg_doze_MASK (0x8000U)
24391 #define CCM_GPR_SHARED14_SET_m7_gpt1_ipg_doze_SHIFT (15U)
24392 /*! m7_gpt1_ipg_doze - m7_gpt1_ipg_doze */
24393 #define CCM_GPR_SHARED14_SET_m7_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_gpt1_ipg_doze_MASK)
24394 
24395 #define CCM_GPR_SHARED14_SET_m7_gpt2_ipg_doze_MASK (0x10000U)
24396 #define CCM_GPR_SHARED14_SET_m7_gpt2_ipg_doze_SHIFT (16U)
24397 /*! m7_gpt2_ipg_doze - m7_gpt2_ipg_doze */
24398 #define CCM_GPR_SHARED14_SET_m7_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_gpt2_ipg_doze_MASK)
24399 
24400 #define CCM_GPR_SHARED14_SET_m7_can1_ipg_doze_MASK (0x20000U)
24401 #define CCM_GPR_SHARED14_SET_m7_can1_ipg_doze_SHIFT (17U)
24402 /*! m7_can1_ipg_doze - m7_can1_ipg_doze */
24403 #define CCM_GPR_SHARED14_SET_m7_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_can1_ipg_doze_MASK)
24404 
24405 #define CCM_GPR_SHARED14_SET_m7_can2_ipg_doze_MASK (0x40000U)
24406 #define CCM_GPR_SHARED14_SET_m7_can2_ipg_doze_SHIFT (18U)
24407 /*! m7_can2_ipg_doze - m7_can2_ipg_doze */
24408 #define CCM_GPR_SHARED14_SET_m7_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_can2_ipg_doze_MASK)
24409 
24410 #define CCM_GPR_SHARED14_SET_m7_can3_ipg_doze_MASK (0x80000U)
24411 #define CCM_GPR_SHARED14_SET_m7_can3_ipg_doze_SHIFT (19U)
24412 /*! m7_can3_ipg_doze - m7_can3_ipg_doze */
24413 #define CCM_GPR_SHARED14_SET_m7_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_can3_ipg_doze_MASK)
24414 
24415 #define CCM_GPR_SHARED14_SET_m7_lpuart1_ipg_doze_MASK (0x100000U)
24416 #define CCM_GPR_SHARED14_SET_m7_lpuart1_ipg_doze_SHIFT (20U)
24417 /*! m7_lpuart1_ipg_doze - m7_lpuart1_ipg_doze */
24418 #define CCM_GPR_SHARED14_SET_m7_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart1_ipg_doze_MASK)
24419 
24420 #define CCM_GPR_SHARED14_SET_m7_lpuart2_ipg_doze_MASK (0x200000U)
24421 #define CCM_GPR_SHARED14_SET_m7_lpuart2_ipg_doze_SHIFT (21U)
24422 /*! m7_lpuart2_ipg_doze - m7_lpuart2_ipg_doze */
24423 #define CCM_GPR_SHARED14_SET_m7_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart2_ipg_doze_MASK)
24424 
24425 #define CCM_GPR_SHARED14_SET_m7_lpuart3_ipg_doze_MASK (0x400000U)
24426 #define CCM_GPR_SHARED14_SET_m7_lpuart3_ipg_doze_SHIFT (22U)
24427 /*! m7_lpuart3_ipg_doze - m7_lpuart3_ipg_doze */
24428 #define CCM_GPR_SHARED14_SET_m7_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart3_ipg_doze_MASK)
24429 
24430 #define CCM_GPR_SHARED14_SET_m7_lpuart4_ipg_doze_MASK (0x800000U)
24431 #define CCM_GPR_SHARED14_SET_m7_lpuart4_ipg_doze_SHIFT (23U)
24432 /*! m7_lpuart4_ipg_doze - m7_lpuart4_ipg_doze */
24433 #define CCM_GPR_SHARED14_SET_m7_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart4_ipg_doze_MASK)
24434 
24435 #define CCM_GPR_SHARED14_SET_m7_lpuart5_ipg_doze_MASK (0x1000000U)
24436 #define CCM_GPR_SHARED14_SET_m7_lpuart5_ipg_doze_SHIFT (24U)
24437 /*! m7_lpuart5_ipg_doze - m7_lpuart5_ipg_doze */
24438 #define CCM_GPR_SHARED14_SET_m7_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart5_ipg_doze_MASK)
24439 
24440 #define CCM_GPR_SHARED14_SET_m7_lpuart6_ipg_doze_MASK (0x2000000U)
24441 #define CCM_GPR_SHARED14_SET_m7_lpuart6_ipg_doze_SHIFT (25U)
24442 /*! m7_lpuart6_ipg_doze - m7_lpuart6_ipg_doze */
24443 #define CCM_GPR_SHARED14_SET_m7_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart6_ipg_doze_MASK)
24444 
24445 #define CCM_GPR_SHARED14_SET_m7_lpuart7_ipg_doze_MASK (0x4000000U)
24446 #define CCM_GPR_SHARED14_SET_m7_lpuart7_ipg_doze_SHIFT (26U)
24447 /*! m7_lpuart7_ipg_doze - m7_lpuart7_ipg_doze */
24448 #define CCM_GPR_SHARED14_SET_m7_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart7_ipg_doze_MASK)
24449 
24450 #define CCM_GPR_SHARED14_SET_m7_lpuart8_ipg_doze_MASK (0x8000000U)
24451 #define CCM_GPR_SHARED14_SET_m7_lpuart8_ipg_doze_SHIFT (27U)
24452 /*! m7_lpuart8_ipg_doze - m7_lpuart8_ipg_doze */
24453 #define CCM_GPR_SHARED14_SET_m7_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart8_ipg_doze_MASK)
24454 
24455 #define CCM_GPR_SHARED14_SET_m7_lpuart9_ipg_doze_MASK (0x10000000U)
24456 #define CCM_GPR_SHARED14_SET_m7_lpuart9_ipg_doze_SHIFT (28U)
24457 /*! m7_lpuart9_ipg_doze - m7_lpuart9_ipg_doze */
24458 #define CCM_GPR_SHARED14_SET_m7_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart9_ipg_doze_MASK)
24459 
24460 #define CCM_GPR_SHARED14_SET_m7_lpuart10_ipg_doze_MASK (0x20000000U)
24461 #define CCM_GPR_SHARED14_SET_m7_lpuart10_ipg_doze_SHIFT (29U)
24462 /*! m7_lpuart10_ipg_doze - m7_lpuart10_ipg_doze */
24463 #define CCM_GPR_SHARED14_SET_m7_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart10_ipg_doze_MASK)
24464 
24465 #define CCM_GPR_SHARED14_SET_m7_lpuart11_ipg_doze_MASK (0x40000000U)
24466 #define CCM_GPR_SHARED14_SET_m7_lpuart11_ipg_doze_SHIFT (30U)
24467 /*! m7_lpuart11_ipg_doze - m7_lpuart11_ipg_doze */
24468 #define CCM_GPR_SHARED14_SET_m7_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart11_ipg_doze_MASK)
24469 
24470 #define CCM_GPR_SHARED14_SET_m7_lpuart12_ipg_doze_MASK (0x80000000U)
24471 #define CCM_GPR_SHARED14_SET_m7_lpuart12_ipg_doze_SHIFT (31U)
24472 /*! m7_lpuart12_ipg_doze - m7_lpuart12_ipg_doze */
24473 #define CCM_GPR_SHARED14_SET_m7_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_SET_m7_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_SET_m7_lpuart12_ipg_doze_MASK)
24474 /*! @} */
24475 
24476 /*! @name GPR_SHARED14_CLR - General Purpose Register */
24477 /*! @{ */
24478 
24479 #define CCM_GPR_SHARED14_CLR_m7_adc1_ipg_doze_MASK (0x1U)
24480 #define CCM_GPR_SHARED14_CLR_m7_adc1_ipg_doze_SHIFT (0U)
24481 /*! m7_adc1_ipg_doze - m7_adc1_ipg_doze */
24482 #define CCM_GPR_SHARED14_CLR_m7_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_adc1_ipg_doze_MASK)
24483 
24484 #define CCM_GPR_SHARED14_CLR_m7_adc2_ipg_doze_MASK (0x2U)
24485 #define CCM_GPR_SHARED14_CLR_m7_adc2_ipg_doze_SHIFT (1U)
24486 /*! m7_adc2_ipg_doze - m7_adc2_ipg_doze */
24487 #define CCM_GPR_SHARED14_CLR_m7_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_adc2_ipg_doze_MASK)
24488 
24489 #define CCM_GPR_SHARED14_CLR_m7_flexspi1_ipg_doze_MASK (0x4U)
24490 #define CCM_GPR_SHARED14_CLR_m7_flexspi1_ipg_doze_SHIFT (2U)
24491 /*! m7_flexspi1_ipg_doze - m7_flexspi1_ipg_doze */
24492 #define CCM_GPR_SHARED14_CLR_m7_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_flexspi1_ipg_doze_MASK)
24493 
24494 #define CCM_GPR_SHARED14_CLR_m7_flexspi2_ipg_doze_MASK (0x8U)
24495 #define CCM_GPR_SHARED14_CLR_m7_flexspi2_ipg_doze_SHIFT (3U)
24496 /*! m7_flexspi2_ipg_doze - m7_flexspi2_ipg_doze */
24497 #define CCM_GPR_SHARED14_CLR_m7_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_flexspi2_ipg_doze_MASK)
24498 
24499 #define CCM_GPR_SHARED14_CLR_m7_flexio1_ipg_doze_MASK (0x10U)
24500 #define CCM_GPR_SHARED14_CLR_m7_flexio1_ipg_doze_SHIFT (4U)
24501 /*! m7_flexio1_ipg_doze - m7_flexio1_ipg_doze */
24502 #define CCM_GPR_SHARED14_CLR_m7_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_flexio1_ipg_doze_MASK)
24503 
24504 #define CCM_GPR_SHARED14_CLR_m7_flexio2_ipg_doze_MASK (0x20U)
24505 #define CCM_GPR_SHARED14_CLR_m7_flexio2_ipg_doze_SHIFT (5U)
24506 /*! m7_flexio2_ipg_doze - m7_flexio2_ipg_doze */
24507 #define CCM_GPR_SHARED14_CLR_m7_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_flexio2_ipg_doze_MASK)
24508 
24509 #define CCM_GPR_SHARED14_CLR_m7_lpit1_ipg_doze_MASK (0x40U)
24510 #define CCM_GPR_SHARED14_CLR_m7_lpit1_ipg_doze_SHIFT (6U)
24511 /*! m7_lpit1_ipg_doze - m7_lpit1_ipg_doze */
24512 #define CCM_GPR_SHARED14_CLR_m7_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpit1_ipg_doze_MASK)
24513 
24514 #define CCM_GPR_SHARED14_CLR_m7_lpit2_ipg_doze_MASK (0x80U)
24515 #define CCM_GPR_SHARED14_CLR_m7_lpit2_ipg_doze_SHIFT (7U)
24516 /*! m7_lpit2_ipg_doze - m7_lpit2_ipg_doze */
24517 #define CCM_GPR_SHARED14_CLR_m7_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpit2_ipg_doze_MASK)
24518 
24519 #define CCM_GPR_SHARED14_CLR_m7_lpit3_ipg_doze_MASK (0x100U)
24520 #define CCM_GPR_SHARED14_CLR_m7_lpit3_ipg_doze_SHIFT (8U)
24521 /*! m7_lpit3_ipg_doze - m7_lpit3_ipg_doze */
24522 #define CCM_GPR_SHARED14_CLR_m7_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpit3_ipg_doze_MASK)
24523 
24524 #define CCM_GPR_SHARED14_CLR_m7_tpm1_ipg_doze_MASK (0x200U)
24525 #define CCM_GPR_SHARED14_CLR_m7_tpm1_ipg_doze_SHIFT (9U)
24526 /*! m7_tpm1_ipg_doze - m7_tpm1_ipg_doze */
24527 #define CCM_GPR_SHARED14_CLR_m7_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm1_ipg_doze_MASK)
24528 
24529 #define CCM_GPR_SHARED14_CLR_m7_tpm2_ipg_doze_MASK (0x400U)
24530 #define CCM_GPR_SHARED14_CLR_m7_tpm2_ipg_doze_SHIFT (10U)
24531 /*! m7_tpm2_ipg_doze - m7_tpm2_ipg_doze */
24532 #define CCM_GPR_SHARED14_CLR_m7_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm2_ipg_doze_MASK)
24533 
24534 #define CCM_GPR_SHARED14_CLR_m7_tpm3_ipg_doze_MASK (0x800U)
24535 #define CCM_GPR_SHARED14_CLR_m7_tpm3_ipg_doze_SHIFT (11U)
24536 /*! m7_tpm3_ipg_doze - m7_tpm3_ipg_doze */
24537 #define CCM_GPR_SHARED14_CLR_m7_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm3_ipg_doze_MASK)
24538 
24539 #define CCM_GPR_SHARED14_CLR_m7_tpm4_ipg_doze_MASK (0x1000U)
24540 #define CCM_GPR_SHARED14_CLR_m7_tpm4_ipg_doze_SHIFT (12U)
24541 /*! m7_tpm4_ipg_doze - m7_tpm4_ipg_doze */
24542 #define CCM_GPR_SHARED14_CLR_m7_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm4_ipg_doze_MASK)
24543 
24544 #define CCM_GPR_SHARED14_CLR_m7_tpm5_ipg_doze_MASK (0x2000U)
24545 #define CCM_GPR_SHARED14_CLR_m7_tpm5_ipg_doze_SHIFT (13U)
24546 /*! m7_tpm5_ipg_doze - m7_tpm5_ipg_doze */
24547 #define CCM_GPR_SHARED14_CLR_m7_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm5_ipg_doze_MASK)
24548 
24549 #define CCM_GPR_SHARED14_CLR_m7_tpm6_ipg_doze_MASK (0x4000U)
24550 #define CCM_GPR_SHARED14_CLR_m7_tpm6_ipg_doze_SHIFT (14U)
24551 /*! m7_tpm6_ipg_doze - m7_tpm6_ipg_doze */
24552 #define CCM_GPR_SHARED14_CLR_m7_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_tpm6_ipg_doze_MASK)
24553 
24554 #define CCM_GPR_SHARED14_CLR_m7_gpt1_ipg_doze_MASK (0x8000U)
24555 #define CCM_GPR_SHARED14_CLR_m7_gpt1_ipg_doze_SHIFT (15U)
24556 /*! m7_gpt1_ipg_doze - m7_gpt1_ipg_doze */
24557 #define CCM_GPR_SHARED14_CLR_m7_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_gpt1_ipg_doze_MASK)
24558 
24559 #define CCM_GPR_SHARED14_CLR_m7_gpt2_ipg_doze_MASK (0x10000U)
24560 #define CCM_GPR_SHARED14_CLR_m7_gpt2_ipg_doze_SHIFT (16U)
24561 /*! m7_gpt2_ipg_doze - m7_gpt2_ipg_doze */
24562 #define CCM_GPR_SHARED14_CLR_m7_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_gpt2_ipg_doze_MASK)
24563 
24564 #define CCM_GPR_SHARED14_CLR_m7_can1_ipg_doze_MASK (0x20000U)
24565 #define CCM_GPR_SHARED14_CLR_m7_can1_ipg_doze_SHIFT (17U)
24566 /*! m7_can1_ipg_doze - m7_can1_ipg_doze */
24567 #define CCM_GPR_SHARED14_CLR_m7_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_can1_ipg_doze_MASK)
24568 
24569 #define CCM_GPR_SHARED14_CLR_m7_can2_ipg_doze_MASK (0x40000U)
24570 #define CCM_GPR_SHARED14_CLR_m7_can2_ipg_doze_SHIFT (18U)
24571 /*! m7_can2_ipg_doze - m7_can2_ipg_doze */
24572 #define CCM_GPR_SHARED14_CLR_m7_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_can2_ipg_doze_MASK)
24573 
24574 #define CCM_GPR_SHARED14_CLR_m7_can3_ipg_doze_MASK (0x80000U)
24575 #define CCM_GPR_SHARED14_CLR_m7_can3_ipg_doze_SHIFT (19U)
24576 /*! m7_can3_ipg_doze - m7_can3_ipg_doze */
24577 #define CCM_GPR_SHARED14_CLR_m7_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_can3_ipg_doze_MASK)
24578 
24579 #define CCM_GPR_SHARED14_CLR_m7_lpuart1_ipg_doze_MASK (0x100000U)
24580 #define CCM_GPR_SHARED14_CLR_m7_lpuart1_ipg_doze_SHIFT (20U)
24581 /*! m7_lpuart1_ipg_doze - m7_lpuart1_ipg_doze */
24582 #define CCM_GPR_SHARED14_CLR_m7_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart1_ipg_doze_MASK)
24583 
24584 #define CCM_GPR_SHARED14_CLR_m7_lpuart2_ipg_doze_MASK (0x200000U)
24585 #define CCM_GPR_SHARED14_CLR_m7_lpuart2_ipg_doze_SHIFT (21U)
24586 /*! m7_lpuart2_ipg_doze - m7_lpuart2_ipg_doze */
24587 #define CCM_GPR_SHARED14_CLR_m7_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart2_ipg_doze_MASK)
24588 
24589 #define CCM_GPR_SHARED14_CLR_m7_lpuart3_ipg_doze_MASK (0x400000U)
24590 #define CCM_GPR_SHARED14_CLR_m7_lpuart3_ipg_doze_SHIFT (22U)
24591 /*! m7_lpuart3_ipg_doze - m7_lpuart3_ipg_doze */
24592 #define CCM_GPR_SHARED14_CLR_m7_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart3_ipg_doze_MASK)
24593 
24594 #define CCM_GPR_SHARED14_CLR_m7_lpuart4_ipg_doze_MASK (0x800000U)
24595 #define CCM_GPR_SHARED14_CLR_m7_lpuart4_ipg_doze_SHIFT (23U)
24596 /*! m7_lpuart4_ipg_doze - m7_lpuart4_ipg_doze */
24597 #define CCM_GPR_SHARED14_CLR_m7_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart4_ipg_doze_MASK)
24598 
24599 #define CCM_GPR_SHARED14_CLR_m7_lpuart5_ipg_doze_MASK (0x1000000U)
24600 #define CCM_GPR_SHARED14_CLR_m7_lpuart5_ipg_doze_SHIFT (24U)
24601 /*! m7_lpuart5_ipg_doze - m7_lpuart5_ipg_doze */
24602 #define CCM_GPR_SHARED14_CLR_m7_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart5_ipg_doze_MASK)
24603 
24604 #define CCM_GPR_SHARED14_CLR_m7_lpuart6_ipg_doze_MASK (0x2000000U)
24605 #define CCM_GPR_SHARED14_CLR_m7_lpuart6_ipg_doze_SHIFT (25U)
24606 /*! m7_lpuart6_ipg_doze - m7_lpuart6_ipg_doze */
24607 #define CCM_GPR_SHARED14_CLR_m7_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart6_ipg_doze_MASK)
24608 
24609 #define CCM_GPR_SHARED14_CLR_m7_lpuart7_ipg_doze_MASK (0x4000000U)
24610 #define CCM_GPR_SHARED14_CLR_m7_lpuart7_ipg_doze_SHIFT (26U)
24611 /*! m7_lpuart7_ipg_doze - m7_lpuart7_ipg_doze */
24612 #define CCM_GPR_SHARED14_CLR_m7_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart7_ipg_doze_MASK)
24613 
24614 #define CCM_GPR_SHARED14_CLR_m7_lpuart8_ipg_doze_MASK (0x8000000U)
24615 #define CCM_GPR_SHARED14_CLR_m7_lpuart8_ipg_doze_SHIFT (27U)
24616 /*! m7_lpuart8_ipg_doze - m7_lpuart8_ipg_doze */
24617 #define CCM_GPR_SHARED14_CLR_m7_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart8_ipg_doze_MASK)
24618 
24619 #define CCM_GPR_SHARED14_CLR_m7_lpuart9_ipg_doze_MASK (0x10000000U)
24620 #define CCM_GPR_SHARED14_CLR_m7_lpuart9_ipg_doze_SHIFT (28U)
24621 /*! m7_lpuart9_ipg_doze - m7_lpuart9_ipg_doze */
24622 #define CCM_GPR_SHARED14_CLR_m7_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart9_ipg_doze_MASK)
24623 
24624 #define CCM_GPR_SHARED14_CLR_m7_lpuart10_ipg_doze_MASK (0x20000000U)
24625 #define CCM_GPR_SHARED14_CLR_m7_lpuart10_ipg_doze_SHIFT (29U)
24626 /*! m7_lpuart10_ipg_doze - m7_lpuart10_ipg_doze */
24627 #define CCM_GPR_SHARED14_CLR_m7_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart10_ipg_doze_MASK)
24628 
24629 #define CCM_GPR_SHARED14_CLR_m7_lpuart11_ipg_doze_MASK (0x40000000U)
24630 #define CCM_GPR_SHARED14_CLR_m7_lpuart11_ipg_doze_SHIFT (30U)
24631 /*! m7_lpuart11_ipg_doze - m7_lpuart11_ipg_doze */
24632 #define CCM_GPR_SHARED14_CLR_m7_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart11_ipg_doze_MASK)
24633 
24634 #define CCM_GPR_SHARED14_CLR_m7_lpuart12_ipg_doze_MASK (0x80000000U)
24635 #define CCM_GPR_SHARED14_CLR_m7_lpuart12_ipg_doze_SHIFT (31U)
24636 /*! m7_lpuart12_ipg_doze - m7_lpuart12_ipg_doze */
24637 #define CCM_GPR_SHARED14_CLR_m7_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_CLR_m7_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_CLR_m7_lpuart12_ipg_doze_MASK)
24638 /*! @} */
24639 
24640 /*! @name GPR_SHARED14_TOG - General Purpose Register */
24641 /*! @{ */
24642 
24643 #define CCM_GPR_SHARED14_TOG_m7_adc1_ipg_doze_MASK (0x1U)
24644 #define CCM_GPR_SHARED14_TOG_m7_adc1_ipg_doze_SHIFT (0U)
24645 /*! m7_adc1_ipg_doze - m7_adc1_ipg_doze */
24646 #define CCM_GPR_SHARED14_TOG_m7_adc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_adc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_adc1_ipg_doze_MASK)
24647 
24648 #define CCM_GPR_SHARED14_TOG_m7_adc2_ipg_doze_MASK (0x2U)
24649 #define CCM_GPR_SHARED14_TOG_m7_adc2_ipg_doze_SHIFT (1U)
24650 /*! m7_adc2_ipg_doze - m7_adc2_ipg_doze */
24651 #define CCM_GPR_SHARED14_TOG_m7_adc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_adc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_adc2_ipg_doze_MASK)
24652 
24653 #define CCM_GPR_SHARED14_TOG_m7_flexspi1_ipg_doze_MASK (0x4U)
24654 #define CCM_GPR_SHARED14_TOG_m7_flexspi1_ipg_doze_SHIFT (2U)
24655 /*! m7_flexspi1_ipg_doze - m7_flexspi1_ipg_doze */
24656 #define CCM_GPR_SHARED14_TOG_m7_flexspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_flexspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_flexspi1_ipg_doze_MASK)
24657 
24658 #define CCM_GPR_SHARED14_TOG_m7_flexspi2_ipg_doze_MASK (0x8U)
24659 #define CCM_GPR_SHARED14_TOG_m7_flexspi2_ipg_doze_SHIFT (3U)
24660 /*! m7_flexspi2_ipg_doze - m7_flexspi2_ipg_doze */
24661 #define CCM_GPR_SHARED14_TOG_m7_flexspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_flexspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_flexspi2_ipg_doze_MASK)
24662 
24663 #define CCM_GPR_SHARED14_TOG_m7_flexio1_ipg_doze_MASK (0x10U)
24664 #define CCM_GPR_SHARED14_TOG_m7_flexio1_ipg_doze_SHIFT (4U)
24665 /*! m7_flexio1_ipg_doze - m7_flexio1_ipg_doze */
24666 #define CCM_GPR_SHARED14_TOG_m7_flexio1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_flexio1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_flexio1_ipg_doze_MASK)
24667 
24668 #define CCM_GPR_SHARED14_TOG_m7_flexio2_ipg_doze_MASK (0x20U)
24669 #define CCM_GPR_SHARED14_TOG_m7_flexio2_ipg_doze_SHIFT (5U)
24670 /*! m7_flexio2_ipg_doze - m7_flexio2_ipg_doze */
24671 #define CCM_GPR_SHARED14_TOG_m7_flexio2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_flexio2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_flexio2_ipg_doze_MASK)
24672 
24673 #define CCM_GPR_SHARED14_TOG_m7_lpit1_ipg_doze_MASK (0x40U)
24674 #define CCM_GPR_SHARED14_TOG_m7_lpit1_ipg_doze_SHIFT (6U)
24675 /*! m7_lpit1_ipg_doze - m7_lpit1_ipg_doze */
24676 #define CCM_GPR_SHARED14_TOG_m7_lpit1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpit1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpit1_ipg_doze_MASK)
24677 
24678 #define CCM_GPR_SHARED14_TOG_m7_lpit2_ipg_doze_MASK (0x80U)
24679 #define CCM_GPR_SHARED14_TOG_m7_lpit2_ipg_doze_SHIFT (7U)
24680 /*! m7_lpit2_ipg_doze - m7_lpit2_ipg_doze */
24681 #define CCM_GPR_SHARED14_TOG_m7_lpit2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpit2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpit2_ipg_doze_MASK)
24682 
24683 #define CCM_GPR_SHARED14_TOG_m7_lpit3_ipg_doze_MASK (0x100U)
24684 #define CCM_GPR_SHARED14_TOG_m7_lpit3_ipg_doze_SHIFT (8U)
24685 /*! m7_lpit3_ipg_doze - m7_lpit3_ipg_doze */
24686 #define CCM_GPR_SHARED14_TOG_m7_lpit3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpit3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpit3_ipg_doze_MASK)
24687 
24688 #define CCM_GPR_SHARED14_TOG_m7_tpm1_ipg_doze_MASK (0x200U)
24689 #define CCM_GPR_SHARED14_TOG_m7_tpm1_ipg_doze_SHIFT (9U)
24690 /*! m7_tpm1_ipg_doze - m7_tpm1_ipg_doze */
24691 #define CCM_GPR_SHARED14_TOG_m7_tpm1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm1_ipg_doze_MASK)
24692 
24693 #define CCM_GPR_SHARED14_TOG_m7_tpm2_ipg_doze_MASK (0x400U)
24694 #define CCM_GPR_SHARED14_TOG_m7_tpm2_ipg_doze_SHIFT (10U)
24695 /*! m7_tpm2_ipg_doze - m7_tpm2_ipg_doze */
24696 #define CCM_GPR_SHARED14_TOG_m7_tpm2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm2_ipg_doze_MASK)
24697 
24698 #define CCM_GPR_SHARED14_TOG_m7_tpm3_ipg_doze_MASK (0x800U)
24699 #define CCM_GPR_SHARED14_TOG_m7_tpm3_ipg_doze_SHIFT (11U)
24700 /*! m7_tpm3_ipg_doze - m7_tpm3_ipg_doze */
24701 #define CCM_GPR_SHARED14_TOG_m7_tpm3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm3_ipg_doze_MASK)
24702 
24703 #define CCM_GPR_SHARED14_TOG_m7_tpm4_ipg_doze_MASK (0x1000U)
24704 #define CCM_GPR_SHARED14_TOG_m7_tpm4_ipg_doze_SHIFT (12U)
24705 /*! m7_tpm4_ipg_doze - m7_tpm4_ipg_doze */
24706 #define CCM_GPR_SHARED14_TOG_m7_tpm4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm4_ipg_doze_MASK)
24707 
24708 #define CCM_GPR_SHARED14_TOG_m7_tpm5_ipg_doze_MASK (0x2000U)
24709 #define CCM_GPR_SHARED14_TOG_m7_tpm5_ipg_doze_SHIFT (13U)
24710 /*! m7_tpm5_ipg_doze - m7_tpm5_ipg_doze */
24711 #define CCM_GPR_SHARED14_TOG_m7_tpm5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm5_ipg_doze_MASK)
24712 
24713 #define CCM_GPR_SHARED14_TOG_m7_tpm6_ipg_doze_MASK (0x4000U)
24714 #define CCM_GPR_SHARED14_TOG_m7_tpm6_ipg_doze_SHIFT (14U)
24715 /*! m7_tpm6_ipg_doze - m7_tpm6_ipg_doze */
24716 #define CCM_GPR_SHARED14_TOG_m7_tpm6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_tpm6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_tpm6_ipg_doze_MASK)
24717 
24718 #define CCM_GPR_SHARED14_TOG_m7_gpt1_ipg_doze_MASK (0x8000U)
24719 #define CCM_GPR_SHARED14_TOG_m7_gpt1_ipg_doze_SHIFT (15U)
24720 /*! m7_gpt1_ipg_doze - m7_gpt1_ipg_doze */
24721 #define CCM_GPR_SHARED14_TOG_m7_gpt1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_gpt1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_gpt1_ipg_doze_MASK)
24722 
24723 #define CCM_GPR_SHARED14_TOG_m7_gpt2_ipg_doze_MASK (0x10000U)
24724 #define CCM_GPR_SHARED14_TOG_m7_gpt2_ipg_doze_SHIFT (16U)
24725 /*! m7_gpt2_ipg_doze - m7_gpt2_ipg_doze */
24726 #define CCM_GPR_SHARED14_TOG_m7_gpt2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_gpt2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_gpt2_ipg_doze_MASK)
24727 
24728 #define CCM_GPR_SHARED14_TOG_m7_can1_ipg_doze_MASK (0x20000U)
24729 #define CCM_GPR_SHARED14_TOG_m7_can1_ipg_doze_SHIFT (17U)
24730 /*! m7_can1_ipg_doze - m7_can1_ipg_doze */
24731 #define CCM_GPR_SHARED14_TOG_m7_can1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_can1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_can1_ipg_doze_MASK)
24732 
24733 #define CCM_GPR_SHARED14_TOG_m7_can2_ipg_doze_MASK (0x40000U)
24734 #define CCM_GPR_SHARED14_TOG_m7_can2_ipg_doze_SHIFT (18U)
24735 /*! m7_can2_ipg_doze - m7_can2_ipg_doze */
24736 #define CCM_GPR_SHARED14_TOG_m7_can2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_can2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_can2_ipg_doze_MASK)
24737 
24738 #define CCM_GPR_SHARED14_TOG_m7_can3_ipg_doze_MASK (0x80000U)
24739 #define CCM_GPR_SHARED14_TOG_m7_can3_ipg_doze_SHIFT (19U)
24740 /*! m7_can3_ipg_doze - m7_can3_ipg_doze */
24741 #define CCM_GPR_SHARED14_TOG_m7_can3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_can3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_can3_ipg_doze_MASK)
24742 
24743 #define CCM_GPR_SHARED14_TOG_m7_lpuart1_ipg_doze_MASK (0x100000U)
24744 #define CCM_GPR_SHARED14_TOG_m7_lpuart1_ipg_doze_SHIFT (20U)
24745 /*! m7_lpuart1_ipg_doze - m7_lpuart1_ipg_doze */
24746 #define CCM_GPR_SHARED14_TOG_m7_lpuart1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart1_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart1_ipg_doze_MASK)
24747 
24748 #define CCM_GPR_SHARED14_TOG_m7_lpuart2_ipg_doze_MASK (0x200000U)
24749 #define CCM_GPR_SHARED14_TOG_m7_lpuart2_ipg_doze_SHIFT (21U)
24750 /*! m7_lpuart2_ipg_doze - m7_lpuart2_ipg_doze */
24751 #define CCM_GPR_SHARED14_TOG_m7_lpuart2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart2_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart2_ipg_doze_MASK)
24752 
24753 #define CCM_GPR_SHARED14_TOG_m7_lpuart3_ipg_doze_MASK (0x400000U)
24754 #define CCM_GPR_SHARED14_TOG_m7_lpuart3_ipg_doze_SHIFT (22U)
24755 /*! m7_lpuart3_ipg_doze - m7_lpuart3_ipg_doze */
24756 #define CCM_GPR_SHARED14_TOG_m7_lpuart3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart3_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart3_ipg_doze_MASK)
24757 
24758 #define CCM_GPR_SHARED14_TOG_m7_lpuart4_ipg_doze_MASK (0x800000U)
24759 #define CCM_GPR_SHARED14_TOG_m7_lpuart4_ipg_doze_SHIFT (23U)
24760 /*! m7_lpuart4_ipg_doze - m7_lpuart4_ipg_doze */
24761 #define CCM_GPR_SHARED14_TOG_m7_lpuart4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart4_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart4_ipg_doze_MASK)
24762 
24763 #define CCM_GPR_SHARED14_TOG_m7_lpuart5_ipg_doze_MASK (0x1000000U)
24764 #define CCM_GPR_SHARED14_TOG_m7_lpuart5_ipg_doze_SHIFT (24U)
24765 /*! m7_lpuart5_ipg_doze - m7_lpuart5_ipg_doze */
24766 #define CCM_GPR_SHARED14_TOG_m7_lpuart5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart5_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart5_ipg_doze_MASK)
24767 
24768 #define CCM_GPR_SHARED14_TOG_m7_lpuart6_ipg_doze_MASK (0x2000000U)
24769 #define CCM_GPR_SHARED14_TOG_m7_lpuart6_ipg_doze_SHIFT (25U)
24770 /*! m7_lpuart6_ipg_doze - m7_lpuart6_ipg_doze */
24771 #define CCM_GPR_SHARED14_TOG_m7_lpuart6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart6_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart6_ipg_doze_MASK)
24772 
24773 #define CCM_GPR_SHARED14_TOG_m7_lpuart7_ipg_doze_MASK (0x4000000U)
24774 #define CCM_GPR_SHARED14_TOG_m7_lpuart7_ipg_doze_SHIFT (26U)
24775 /*! m7_lpuart7_ipg_doze - m7_lpuart7_ipg_doze */
24776 #define CCM_GPR_SHARED14_TOG_m7_lpuart7_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart7_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart7_ipg_doze_MASK)
24777 
24778 #define CCM_GPR_SHARED14_TOG_m7_lpuart8_ipg_doze_MASK (0x8000000U)
24779 #define CCM_GPR_SHARED14_TOG_m7_lpuart8_ipg_doze_SHIFT (27U)
24780 /*! m7_lpuart8_ipg_doze - m7_lpuart8_ipg_doze */
24781 #define CCM_GPR_SHARED14_TOG_m7_lpuart8_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart8_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart8_ipg_doze_MASK)
24782 
24783 #define CCM_GPR_SHARED14_TOG_m7_lpuart9_ipg_doze_MASK (0x10000000U)
24784 #define CCM_GPR_SHARED14_TOG_m7_lpuart9_ipg_doze_SHIFT (28U)
24785 /*! m7_lpuart9_ipg_doze - m7_lpuart9_ipg_doze */
24786 #define CCM_GPR_SHARED14_TOG_m7_lpuart9_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart9_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart9_ipg_doze_MASK)
24787 
24788 #define CCM_GPR_SHARED14_TOG_m7_lpuart10_ipg_doze_MASK (0x20000000U)
24789 #define CCM_GPR_SHARED14_TOG_m7_lpuart10_ipg_doze_SHIFT (29U)
24790 /*! m7_lpuart10_ipg_doze - m7_lpuart10_ipg_doze */
24791 #define CCM_GPR_SHARED14_TOG_m7_lpuart10_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart10_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart10_ipg_doze_MASK)
24792 
24793 #define CCM_GPR_SHARED14_TOG_m7_lpuart11_ipg_doze_MASK (0x40000000U)
24794 #define CCM_GPR_SHARED14_TOG_m7_lpuart11_ipg_doze_SHIFT (30U)
24795 /*! m7_lpuart11_ipg_doze - m7_lpuart11_ipg_doze */
24796 #define CCM_GPR_SHARED14_TOG_m7_lpuart11_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart11_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart11_ipg_doze_MASK)
24797 
24798 #define CCM_GPR_SHARED14_TOG_m7_lpuart12_ipg_doze_MASK (0x80000000U)
24799 #define CCM_GPR_SHARED14_TOG_m7_lpuart12_ipg_doze_SHIFT (31U)
24800 /*! m7_lpuart12_ipg_doze - m7_lpuart12_ipg_doze */
24801 #define CCM_GPR_SHARED14_TOG_m7_lpuart12_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_TOG_m7_lpuart12_ipg_doze_SHIFT)) & CCM_GPR_SHARED14_TOG_m7_lpuart12_ipg_doze_MASK)
24802 /*! @} */
24803 
24804 /*! @name GPR_SHARED14_AUTHEN - GPR access control */
24805 /*! @{ */
24806 
24807 #define CCM_GPR_SHARED14_AUTHEN_TZ_USER_MASK     (0x100U)
24808 #define CCM_GPR_SHARED14_AUTHEN_TZ_USER_SHIFT    (8U)
24809 /*! TZ_USER - User access permission
24810  *  0b1..Registers of shared GPR slice can be changed in user mode.
24811  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
24812  */
24813 #define CCM_GPR_SHARED14_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TZ_USER_MASK)
24814 
24815 #define CCM_GPR_SHARED14_AUTHEN_TZ_NS_MASK       (0x200U)
24816 #define CCM_GPR_SHARED14_AUTHEN_TZ_NS_SHIFT      (9U)
24817 /*! TZ_NS - Non-secure access permission
24818  *  0b0..Cannot be changed in Non-secure mode.
24819  *  0b1..Can be changed in Non-secure mode.
24820  */
24821 #define CCM_GPR_SHARED14_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TZ_NS_MASK)
24822 
24823 #define CCM_GPR_SHARED14_AUTHEN_LOCK_TZ_MASK     (0x800U)
24824 #define CCM_GPR_SHARED14_AUTHEN_LOCK_TZ_SHIFT    (11U)
24825 /*! LOCK_TZ - Lock TrustZone settings
24826  *  0b0..TrustZone settings is not locked.
24827  *  0b1..TrustZone settings is locked.
24828  */
24829 #define CCM_GPR_SHARED14_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_LOCK_TZ_MASK)
24830 
24831 #define CCM_GPR_SHARED14_AUTHEN_LOCK_LIST_MASK   (0x8000U)
24832 #define CCM_GPR_SHARED14_AUTHEN_LOCK_LIST_SHIFT  (15U)
24833 /*! LOCK_LIST - Lock white list
24834  *  0b0..Whitelist is not locked.
24835  *  0b1..Whitelist is locked.
24836  */
24837 #define CCM_GPR_SHARED14_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_LOCK_LIST_MASK)
24838 
24839 #define CCM_GPR_SHARED14_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
24840 #define CCM_GPR_SHARED14_AUTHEN_WHITE_LIST_SHIFT (16U)
24841 /*! WHITE_LIST - Whitelist settings */
24842 #define CCM_GPR_SHARED14_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_WHITE_LIST_MASK)
24843 /*! @} */
24844 
24845 /*! @name GPR_SHARED14_AUTHEN_SET - GPR access control */
24846 /*! @{ */
24847 
24848 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_USER_MASK (0x100U)
24849 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_USER_SHIFT (8U)
24850 /*! TZ_USER - User access permission */
24851 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_SET_TZ_USER_MASK)
24852 
24853 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_NS_MASK   (0x200U)
24854 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_NS_SHIFT  (9U)
24855 /*! TZ_NS - Non-secure access permission */
24856 #define CCM_GPR_SHARED14_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_SET_TZ_NS_MASK)
24857 
24858 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
24859 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
24860 /*! LOCK_TZ - Lock TrustZone settings */
24861 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_SET_LOCK_TZ_MASK)
24862 
24863 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
24864 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
24865 /*! LOCK_LIST - Lock white list */
24866 #define CCM_GPR_SHARED14_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_SET_LOCK_LIST_MASK)
24867 
24868 #define CCM_GPR_SHARED14_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
24869 #define CCM_GPR_SHARED14_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
24870 /*! WHITE_LIST - Whitelist settings */
24871 #define CCM_GPR_SHARED14_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_SET_WHITE_LIST_MASK)
24872 /*! @} */
24873 
24874 /*! @name GPR_SHARED14_AUTHEN_CLR - GPR access control */
24875 /*! @{ */
24876 
24877 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_USER_MASK (0x100U)
24878 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_USER_SHIFT (8U)
24879 /*! TZ_USER - User access permission */
24880 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_CLR_TZ_USER_MASK)
24881 
24882 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
24883 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
24884 /*! TZ_NS - Non-secure access permission */
24885 #define CCM_GPR_SHARED14_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_CLR_TZ_NS_MASK)
24886 
24887 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
24888 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
24889 /*! LOCK_TZ - Lock TrustZone settings */
24890 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_TZ_MASK)
24891 
24892 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
24893 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
24894 /*! LOCK_LIST - Lock white list */
24895 #define CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_CLR_LOCK_LIST_MASK)
24896 
24897 #define CCM_GPR_SHARED14_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
24898 #define CCM_GPR_SHARED14_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
24899 /*! WHITE_LIST - Whitelist settings */
24900 #define CCM_GPR_SHARED14_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_CLR_WHITE_LIST_MASK)
24901 /*! @} */
24902 
24903 /*! @name GPR_SHARED14_AUTHEN_TOG - GPR access control */
24904 /*! @{ */
24905 
24906 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_USER_MASK (0x100U)
24907 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_USER_SHIFT (8U)
24908 /*! TZ_USER - User access permission */
24909 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TOG_TZ_USER_MASK)
24910 
24911 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
24912 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
24913 /*! TZ_NS - Non-secure access permission */
24914 #define CCM_GPR_SHARED14_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TOG_TZ_NS_MASK)
24915 
24916 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
24917 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
24918 /*! LOCK_TZ - Lock TrustZone settings */
24919 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_TZ_MASK)
24920 
24921 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
24922 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
24923 /*! LOCK_LIST - Lock white list */
24924 #define CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TOG_LOCK_LIST_MASK)
24925 
24926 #define CCM_GPR_SHARED14_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
24927 #define CCM_GPR_SHARED14_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
24928 /*! WHITE_LIST - Whitelist settings */
24929 #define CCM_GPR_SHARED14_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED14_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED14_AUTHEN_TOG_WHITE_LIST_MASK)
24930 /*! @} */
24931 
24932 /*! @name GPR_SHARED15 - General Purpose Register */
24933 /*! @{ */
24934 
24935 #define CCM_GPR_SHARED15_m7_lpi2c1_ipg_doze_MASK (0x1U)
24936 #define CCM_GPR_SHARED15_m7_lpi2c1_ipg_doze_SHIFT (0U)
24937 /*! m7_lpi2c1_ipg_doze - m7_lpi2c1_ipg_doze */
24938 #define CCM_GPR_SHARED15_m7_lpi2c1_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c1_ipg_doze_MASK)
24939 
24940 #define CCM_GPR_SHARED15_m7_lpi2c2_ipg_doze_MASK (0x2U)
24941 #define CCM_GPR_SHARED15_m7_lpi2c2_ipg_doze_SHIFT (1U)
24942 /*! m7_lpi2c2_ipg_doze - m7_lpi2c2_ipg_doze */
24943 #define CCM_GPR_SHARED15_m7_lpi2c2_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c2_ipg_doze_MASK)
24944 
24945 #define CCM_GPR_SHARED15_m7_lpi2c3_ipg_doze_MASK (0x4U)
24946 #define CCM_GPR_SHARED15_m7_lpi2c3_ipg_doze_SHIFT (2U)
24947 /*! m7_lpi2c3_ipg_doze - m7_lpi2c3_ipg_doze */
24948 #define CCM_GPR_SHARED15_m7_lpi2c3_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c3_ipg_doze_MASK)
24949 
24950 #define CCM_GPR_SHARED15_m7_lpi2c4_ipg_doze_MASK (0x8U)
24951 #define CCM_GPR_SHARED15_m7_lpi2c4_ipg_doze_SHIFT (3U)
24952 /*! m7_lpi2c4_ipg_doze - m7_lpi2c4_ipg_doze */
24953 #define CCM_GPR_SHARED15_m7_lpi2c4_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c4_ipg_doze_MASK)
24954 
24955 #define CCM_GPR_SHARED15_m7_lpi2c5_ipg_doze_MASK (0x10U)
24956 #define CCM_GPR_SHARED15_m7_lpi2c5_ipg_doze_SHIFT (4U)
24957 /*! m7_lpi2c5_ipg_doze - m7_lpi2c5_ipg_doze */
24958 #define CCM_GPR_SHARED15_m7_lpi2c5_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c5_ipg_doze_MASK)
24959 
24960 #define CCM_GPR_SHARED15_m7_lpi2c6_ipg_doze_MASK (0x20U)
24961 #define CCM_GPR_SHARED15_m7_lpi2c6_ipg_doze_SHIFT (5U)
24962 /*! m7_lpi2c6_ipg_doze - m7_lpi2c6_ipg_doze */
24963 #define CCM_GPR_SHARED15_m7_lpi2c6_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpi2c6_ipg_doze_MASK)
24964 
24965 #define CCM_GPR_SHARED15_m7_lpspi1_ipg_doze_MASK (0x40U)
24966 #define CCM_GPR_SHARED15_m7_lpspi1_ipg_doze_SHIFT (6U)
24967 /*! m7_lpspi1_ipg_doze - m7_lpspi1_ipg_doze */
24968 #define CCM_GPR_SHARED15_m7_lpspi1_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi1_ipg_doze_MASK)
24969 
24970 #define CCM_GPR_SHARED15_m7_lpspi2_ipg_doze_MASK (0x80U)
24971 #define CCM_GPR_SHARED15_m7_lpspi2_ipg_doze_SHIFT (7U)
24972 /*! m7_lpspi2_ipg_doze - m7_lpspi2_ipg_doze */
24973 #define CCM_GPR_SHARED15_m7_lpspi2_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi2_ipg_doze_MASK)
24974 
24975 #define CCM_GPR_SHARED15_m7_lpspi3_ipg_doze_MASK (0x100U)
24976 #define CCM_GPR_SHARED15_m7_lpspi3_ipg_doze_SHIFT (8U)
24977 /*! m7_lpspi3_ipg_doze - m7_lpspi3_ipg_doze */
24978 #define CCM_GPR_SHARED15_m7_lpspi3_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi3_ipg_doze_MASK)
24979 
24980 #define CCM_GPR_SHARED15_m7_lpspi4_ipg_doze_MASK (0x200U)
24981 #define CCM_GPR_SHARED15_m7_lpspi4_ipg_doze_SHIFT (9U)
24982 /*! m7_lpspi4_ipg_doze - m7_lpspi4_ipg_doze */
24983 #define CCM_GPR_SHARED15_m7_lpspi4_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi4_ipg_doze_MASK)
24984 
24985 #define CCM_GPR_SHARED15_m7_lpspi5_ipg_doze_MASK (0x400U)
24986 #define CCM_GPR_SHARED15_m7_lpspi5_ipg_doze_SHIFT (10U)
24987 /*! m7_lpspi5_ipg_doze - m7_lpspi5_ipg_doze */
24988 #define CCM_GPR_SHARED15_m7_lpspi5_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi5_ipg_doze_MASK)
24989 
24990 #define CCM_GPR_SHARED15_m7_lpspi6_ipg_doze_MASK (0x800U)
24991 #define CCM_GPR_SHARED15_m7_lpspi6_ipg_doze_SHIFT (11U)
24992 /*! m7_lpspi6_ipg_doze - m7_lpspi6_ipg_doze */
24993 #define CCM_GPR_SHARED15_m7_lpspi6_ipg_doze(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_lpspi6_ipg_doze_MASK)
24994 
24995 #define CCM_GPR_SHARED15_m7_sinc1_ipg_doze_MASK  (0x1000U)
24996 #define CCM_GPR_SHARED15_m7_sinc1_ipg_doze_SHIFT (12U)
24997 /*! m7_sinc1_ipg_doze - m7_sinc1_ipg_doze */
24998 #define CCM_GPR_SHARED15_m7_sinc1_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_sinc1_ipg_doze_MASK)
24999 
25000 #define CCM_GPR_SHARED15_m7_sinc2_ipg_doze_MASK  (0x2000U)
25001 #define CCM_GPR_SHARED15_m7_sinc2_ipg_doze_SHIFT (13U)
25002 /*! m7_sinc2_ipg_doze - m7_sinc2_ipg_doze */
25003 #define CCM_GPR_SHARED15_m7_sinc2_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_sinc2_ipg_doze_MASK)
25004 
25005 #define CCM_GPR_SHARED15_m7_sinc3_ipg_doze_MASK  (0x4000U)
25006 #define CCM_GPR_SHARED15_m7_sinc3_ipg_doze_SHIFT (14U)
25007 /*! m7_sinc3_ipg_doze - m7_sinc3_ipg_doze */
25008 #define CCM_GPR_SHARED15_m7_sinc3_ipg_doze(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_sinc3_ipg_doze_MASK)
25009 
25010 #define CCM_GPR_SHARED15_m7_mic_ipg_doze_MASK    (0x8000U)
25011 #define CCM_GPR_SHARED15_m7_mic_ipg_doze_SHIFT   (15U)
25012 /*! m7_mic_ipg_doze - m7_mic_ipg_doze */
25013 #define CCM_GPR_SHARED15_m7_mic_ipg_doze(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_m7_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_m7_mic_ipg_doze_MASK)
25014 /*! @} */
25015 
25016 /*! @name GPR_SHARED15_SET - General Purpose Register */
25017 /*! @{ */
25018 
25019 #define CCM_GPR_SHARED15_SET_m7_lpi2c1_ipg_doze_MASK (0x1U)
25020 #define CCM_GPR_SHARED15_SET_m7_lpi2c1_ipg_doze_SHIFT (0U)
25021 /*! m7_lpi2c1_ipg_doze - m7_lpi2c1_ipg_doze */
25022 #define CCM_GPR_SHARED15_SET_m7_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c1_ipg_doze_MASK)
25023 
25024 #define CCM_GPR_SHARED15_SET_m7_lpi2c2_ipg_doze_MASK (0x2U)
25025 #define CCM_GPR_SHARED15_SET_m7_lpi2c2_ipg_doze_SHIFT (1U)
25026 /*! m7_lpi2c2_ipg_doze - m7_lpi2c2_ipg_doze */
25027 #define CCM_GPR_SHARED15_SET_m7_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c2_ipg_doze_MASK)
25028 
25029 #define CCM_GPR_SHARED15_SET_m7_lpi2c3_ipg_doze_MASK (0x4U)
25030 #define CCM_GPR_SHARED15_SET_m7_lpi2c3_ipg_doze_SHIFT (2U)
25031 /*! m7_lpi2c3_ipg_doze - m7_lpi2c3_ipg_doze */
25032 #define CCM_GPR_SHARED15_SET_m7_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c3_ipg_doze_MASK)
25033 
25034 #define CCM_GPR_SHARED15_SET_m7_lpi2c4_ipg_doze_MASK (0x8U)
25035 #define CCM_GPR_SHARED15_SET_m7_lpi2c4_ipg_doze_SHIFT (3U)
25036 /*! m7_lpi2c4_ipg_doze - m7_lpi2c4_ipg_doze */
25037 #define CCM_GPR_SHARED15_SET_m7_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c4_ipg_doze_MASK)
25038 
25039 #define CCM_GPR_SHARED15_SET_m7_lpi2c5_ipg_doze_MASK (0x10U)
25040 #define CCM_GPR_SHARED15_SET_m7_lpi2c5_ipg_doze_SHIFT (4U)
25041 /*! m7_lpi2c5_ipg_doze - m7_lpi2c5_ipg_doze */
25042 #define CCM_GPR_SHARED15_SET_m7_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c5_ipg_doze_MASK)
25043 
25044 #define CCM_GPR_SHARED15_SET_m7_lpi2c6_ipg_doze_MASK (0x20U)
25045 #define CCM_GPR_SHARED15_SET_m7_lpi2c6_ipg_doze_SHIFT (5U)
25046 /*! m7_lpi2c6_ipg_doze - m7_lpi2c6_ipg_doze */
25047 #define CCM_GPR_SHARED15_SET_m7_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpi2c6_ipg_doze_MASK)
25048 
25049 #define CCM_GPR_SHARED15_SET_m7_lpspi1_ipg_doze_MASK (0x40U)
25050 #define CCM_GPR_SHARED15_SET_m7_lpspi1_ipg_doze_SHIFT (6U)
25051 /*! m7_lpspi1_ipg_doze - m7_lpspi1_ipg_doze */
25052 #define CCM_GPR_SHARED15_SET_m7_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi1_ipg_doze_MASK)
25053 
25054 #define CCM_GPR_SHARED15_SET_m7_lpspi2_ipg_doze_MASK (0x80U)
25055 #define CCM_GPR_SHARED15_SET_m7_lpspi2_ipg_doze_SHIFT (7U)
25056 /*! m7_lpspi2_ipg_doze - m7_lpspi2_ipg_doze */
25057 #define CCM_GPR_SHARED15_SET_m7_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi2_ipg_doze_MASK)
25058 
25059 #define CCM_GPR_SHARED15_SET_m7_lpspi3_ipg_doze_MASK (0x100U)
25060 #define CCM_GPR_SHARED15_SET_m7_lpspi3_ipg_doze_SHIFT (8U)
25061 /*! m7_lpspi3_ipg_doze - m7_lpspi3_ipg_doze */
25062 #define CCM_GPR_SHARED15_SET_m7_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi3_ipg_doze_MASK)
25063 
25064 #define CCM_GPR_SHARED15_SET_m7_lpspi4_ipg_doze_MASK (0x200U)
25065 #define CCM_GPR_SHARED15_SET_m7_lpspi4_ipg_doze_SHIFT (9U)
25066 /*! m7_lpspi4_ipg_doze - m7_lpspi4_ipg_doze */
25067 #define CCM_GPR_SHARED15_SET_m7_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi4_ipg_doze_MASK)
25068 
25069 #define CCM_GPR_SHARED15_SET_m7_lpspi5_ipg_doze_MASK (0x400U)
25070 #define CCM_GPR_SHARED15_SET_m7_lpspi5_ipg_doze_SHIFT (10U)
25071 /*! m7_lpspi5_ipg_doze - m7_lpspi5_ipg_doze */
25072 #define CCM_GPR_SHARED15_SET_m7_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi5_ipg_doze_MASK)
25073 
25074 #define CCM_GPR_SHARED15_SET_m7_lpspi6_ipg_doze_MASK (0x800U)
25075 #define CCM_GPR_SHARED15_SET_m7_lpspi6_ipg_doze_SHIFT (11U)
25076 /*! m7_lpspi6_ipg_doze - m7_lpspi6_ipg_doze */
25077 #define CCM_GPR_SHARED15_SET_m7_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_lpspi6_ipg_doze_MASK)
25078 
25079 #define CCM_GPR_SHARED15_SET_m7_sinc1_ipg_doze_MASK (0x1000U)
25080 #define CCM_GPR_SHARED15_SET_m7_sinc1_ipg_doze_SHIFT (12U)
25081 /*! m7_sinc1_ipg_doze - m7_sinc1_ipg_doze */
25082 #define CCM_GPR_SHARED15_SET_m7_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_sinc1_ipg_doze_MASK)
25083 
25084 #define CCM_GPR_SHARED15_SET_m7_sinc2_ipg_doze_MASK (0x2000U)
25085 #define CCM_GPR_SHARED15_SET_m7_sinc2_ipg_doze_SHIFT (13U)
25086 /*! m7_sinc2_ipg_doze - m7_sinc2_ipg_doze */
25087 #define CCM_GPR_SHARED15_SET_m7_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_sinc2_ipg_doze_MASK)
25088 
25089 #define CCM_GPR_SHARED15_SET_m7_sinc3_ipg_doze_MASK (0x4000U)
25090 #define CCM_GPR_SHARED15_SET_m7_sinc3_ipg_doze_SHIFT (14U)
25091 /*! m7_sinc3_ipg_doze - m7_sinc3_ipg_doze */
25092 #define CCM_GPR_SHARED15_SET_m7_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_sinc3_ipg_doze_MASK)
25093 
25094 #define CCM_GPR_SHARED15_SET_m7_mic_ipg_doze_MASK (0x8000U)
25095 #define CCM_GPR_SHARED15_SET_m7_mic_ipg_doze_SHIFT (15U)
25096 /*! m7_mic_ipg_doze - m7_mic_ipg_doze */
25097 #define CCM_GPR_SHARED15_SET_m7_mic_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_SET_m7_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_SET_m7_mic_ipg_doze_MASK)
25098 /*! @} */
25099 
25100 /*! @name GPR_SHARED15_CLR - General Purpose Register */
25101 /*! @{ */
25102 
25103 #define CCM_GPR_SHARED15_CLR_m7_lpi2c1_ipg_doze_MASK (0x1U)
25104 #define CCM_GPR_SHARED15_CLR_m7_lpi2c1_ipg_doze_SHIFT (0U)
25105 /*! m7_lpi2c1_ipg_doze - m7_lpi2c1_ipg_doze */
25106 #define CCM_GPR_SHARED15_CLR_m7_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c1_ipg_doze_MASK)
25107 
25108 #define CCM_GPR_SHARED15_CLR_m7_lpi2c2_ipg_doze_MASK (0x2U)
25109 #define CCM_GPR_SHARED15_CLR_m7_lpi2c2_ipg_doze_SHIFT (1U)
25110 /*! m7_lpi2c2_ipg_doze - m7_lpi2c2_ipg_doze */
25111 #define CCM_GPR_SHARED15_CLR_m7_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c2_ipg_doze_MASK)
25112 
25113 #define CCM_GPR_SHARED15_CLR_m7_lpi2c3_ipg_doze_MASK (0x4U)
25114 #define CCM_GPR_SHARED15_CLR_m7_lpi2c3_ipg_doze_SHIFT (2U)
25115 /*! m7_lpi2c3_ipg_doze - m7_lpi2c3_ipg_doze */
25116 #define CCM_GPR_SHARED15_CLR_m7_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c3_ipg_doze_MASK)
25117 
25118 #define CCM_GPR_SHARED15_CLR_m7_lpi2c4_ipg_doze_MASK (0x8U)
25119 #define CCM_GPR_SHARED15_CLR_m7_lpi2c4_ipg_doze_SHIFT (3U)
25120 /*! m7_lpi2c4_ipg_doze - m7_lpi2c4_ipg_doze */
25121 #define CCM_GPR_SHARED15_CLR_m7_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c4_ipg_doze_MASK)
25122 
25123 #define CCM_GPR_SHARED15_CLR_m7_lpi2c5_ipg_doze_MASK (0x10U)
25124 #define CCM_GPR_SHARED15_CLR_m7_lpi2c5_ipg_doze_SHIFT (4U)
25125 /*! m7_lpi2c5_ipg_doze - m7_lpi2c5_ipg_doze */
25126 #define CCM_GPR_SHARED15_CLR_m7_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c5_ipg_doze_MASK)
25127 
25128 #define CCM_GPR_SHARED15_CLR_m7_lpi2c6_ipg_doze_MASK (0x20U)
25129 #define CCM_GPR_SHARED15_CLR_m7_lpi2c6_ipg_doze_SHIFT (5U)
25130 /*! m7_lpi2c6_ipg_doze - m7_lpi2c6_ipg_doze */
25131 #define CCM_GPR_SHARED15_CLR_m7_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpi2c6_ipg_doze_MASK)
25132 
25133 #define CCM_GPR_SHARED15_CLR_m7_lpspi1_ipg_doze_MASK (0x40U)
25134 #define CCM_GPR_SHARED15_CLR_m7_lpspi1_ipg_doze_SHIFT (6U)
25135 /*! m7_lpspi1_ipg_doze - m7_lpspi1_ipg_doze */
25136 #define CCM_GPR_SHARED15_CLR_m7_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi1_ipg_doze_MASK)
25137 
25138 #define CCM_GPR_SHARED15_CLR_m7_lpspi2_ipg_doze_MASK (0x80U)
25139 #define CCM_GPR_SHARED15_CLR_m7_lpspi2_ipg_doze_SHIFT (7U)
25140 /*! m7_lpspi2_ipg_doze - m7_lpspi2_ipg_doze */
25141 #define CCM_GPR_SHARED15_CLR_m7_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi2_ipg_doze_MASK)
25142 
25143 #define CCM_GPR_SHARED15_CLR_m7_lpspi3_ipg_doze_MASK (0x100U)
25144 #define CCM_GPR_SHARED15_CLR_m7_lpspi3_ipg_doze_SHIFT (8U)
25145 /*! m7_lpspi3_ipg_doze - m7_lpspi3_ipg_doze */
25146 #define CCM_GPR_SHARED15_CLR_m7_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi3_ipg_doze_MASK)
25147 
25148 #define CCM_GPR_SHARED15_CLR_m7_lpspi4_ipg_doze_MASK (0x200U)
25149 #define CCM_GPR_SHARED15_CLR_m7_lpspi4_ipg_doze_SHIFT (9U)
25150 /*! m7_lpspi4_ipg_doze - m7_lpspi4_ipg_doze */
25151 #define CCM_GPR_SHARED15_CLR_m7_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi4_ipg_doze_MASK)
25152 
25153 #define CCM_GPR_SHARED15_CLR_m7_lpspi5_ipg_doze_MASK (0x400U)
25154 #define CCM_GPR_SHARED15_CLR_m7_lpspi5_ipg_doze_SHIFT (10U)
25155 /*! m7_lpspi5_ipg_doze - m7_lpspi5_ipg_doze */
25156 #define CCM_GPR_SHARED15_CLR_m7_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi5_ipg_doze_MASK)
25157 
25158 #define CCM_GPR_SHARED15_CLR_m7_lpspi6_ipg_doze_MASK (0x800U)
25159 #define CCM_GPR_SHARED15_CLR_m7_lpspi6_ipg_doze_SHIFT (11U)
25160 /*! m7_lpspi6_ipg_doze - m7_lpspi6_ipg_doze */
25161 #define CCM_GPR_SHARED15_CLR_m7_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_lpspi6_ipg_doze_MASK)
25162 
25163 #define CCM_GPR_SHARED15_CLR_m7_sinc1_ipg_doze_MASK (0x1000U)
25164 #define CCM_GPR_SHARED15_CLR_m7_sinc1_ipg_doze_SHIFT (12U)
25165 /*! m7_sinc1_ipg_doze - m7_sinc1_ipg_doze */
25166 #define CCM_GPR_SHARED15_CLR_m7_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_sinc1_ipg_doze_MASK)
25167 
25168 #define CCM_GPR_SHARED15_CLR_m7_sinc2_ipg_doze_MASK (0x2000U)
25169 #define CCM_GPR_SHARED15_CLR_m7_sinc2_ipg_doze_SHIFT (13U)
25170 /*! m7_sinc2_ipg_doze - m7_sinc2_ipg_doze */
25171 #define CCM_GPR_SHARED15_CLR_m7_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_sinc2_ipg_doze_MASK)
25172 
25173 #define CCM_GPR_SHARED15_CLR_m7_sinc3_ipg_doze_MASK (0x4000U)
25174 #define CCM_GPR_SHARED15_CLR_m7_sinc3_ipg_doze_SHIFT (14U)
25175 /*! m7_sinc3_ipg_doze - m7_sinc3_ipg_doze */
25176 #define CCM_GPR_SHARED15_CLR_m7_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_sinc3_ipg_doze_MASK)
25177 
25178 #define CCM_GPR_SHARED15_CLR_m7_mic_ipg_doze_MASK (0x8000U)
25179 #define CCM_GPR_SHARED15_CLR_m7_mic_ipg_doze_SHIFT (15U)
25180 /*! m7_mic_ipg_doze - m7_mic_ipg_doze */
25181 #define CCM_GPR_SHARED15_CLR_m7_mic_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_CLR_m7_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_CLR_m7_mic_ipg_doze_MASK)
25182 /*! @} */
25183 
25184 /*! @name GPR_SHARED15_TOG - General Purpose Register */
25185 /*! @{ */
25186 
25187 #define CCM_GPR_SHARED15_TOG_m7_lpi2c1_ipg_doze_MASK (0x1U)
25188 #define CCM_GPR_SHARED15_TOG_m7_lpi2c1_ipg_doze_SHIFT (0U)
25189 /*! m7_lpi2c1_ipg_doze - m7_lpi2c1_ipg_doze */
25190 #define CCM_GPR_SHARED15_TOG_m7_lpi2c1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c1_ipg_doze_MASK)
25191 
25192 #define CCM_GPR_SHARED15_TOG_m7_lpi2c2_ipg_doze_MASK (0x2U)
25193 #define CCM_GPR_SHARED15_TOG_m7_lpi2c2_ipg_doze_SHIFT (1U)
25194 /*! m7_lpi2c2_ipg_doze - m7_lpi2c2_ipg_doze */
25195 #define CCM_GPR_SHARED15_TOG_m7_lpi2c2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c2_ipg_doze_MASK)
25196 
25197 #define CCM_GPR_SHARED15_TOG_m7_lpi2c3_ipg_doze_MASK (0x4U)
25198 #define CCM_GPR_SHARED15_TOG_m7_lpi2c3_ipg_doze_SHIFT (2U)
25199 /*! m7_lpi2c3_ipg_doze - m7_lpi2c3_ipg_doze */
25200 #define CCM_GPR_SHARED15_TOG_m7_lpi2c3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c3_ipg_doze_MASK)
25201 
25202 #define CCM_GPR_SHARED15_TOG_m7_lpi2c4_ipg_doze_MASK (0x8U)
25203 #define CCM_GPR_SHARED15_TOG_m7_lpi2c4_ipg_doze_SHIFT (3U)
25204 /*! m7_lpi2c4_ipg_doze - m7_lpi2c4_ipg_doze */
25205 #define CCM_GPR_SHARED15_TOG_m7_lpi2c4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c4_ipg_doze_MASK)
25206 
25207 #define CCM_GPR_SHARED15_TOG_m7_lpi2c5_ipg_doze_MASK (0x10U)
25208 #define CCM_GPR_SHARED15_TOG_m7_lpi2c5_ipg_doze_SHIFT (4U)
25209 /*! m7_lpi2c5_ipg_doze - m7_lpi2c5_ipg_doze */
25210 #define CCM_GPR_SHARED15_TOG_m7_lpi2c5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c5_ipg_doze_MASK)
25211 
25212 #define CCM_GPR_SHARED15_TOG_m7_lpi2c6_ipg_doze_MASK (0x20U)
25213 #define CCM_GPR_SHARED15_TOG_m7_lpi2c6_ipg_doze_SHIFT (5U)
25214 /*! m7_lpi2c6_ipg_doze - m7_lpi2c6_ipg_doze */
25215 #define CCM_GPR_SHARED15_TOG_m7_lpi2c6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpi2c6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpi2c6_ipg_doze_MASK)
25216 
25217 #define CCM_GPR_SHARED15_TOG_m7_lpspi1_ipg_doze_MASK (0x40U)
25218 #define CCM_GPR_SHARED15_TOG_m7_lpspi1_ipg_doze_SHIFT (6U)
25219 /*! m7_lpspi1_ipg_doze - m7_lpspi1_ipg_doze */
25220 #define CCM_GPR_SHARED15_TOG_m7_lpspi1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi1_ipg_doze_MASK)
25221 
25222 #define CCM_GPR_SHARED15_TOG_m7_lpspi2_ipg_doze_MASK (0x80U)
25223 #define CCM_GPR_SHARED15_TOG_m7_lpspi2_ipg_doze_SHIFT (7U)
25224 /*! m7_lpspi2_ipg_doze - m7_lpspi2_ipg_doze */
25225 #define CCM_GPR_SHARED15_TOG_m7_lpspi2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi2_ipg_doze_MASK)
25226 
25227 #define CCM_GPR_SHARED15_TOG_m7_lpspi3_ipg_doze_MASK (0x100U)
25228 #define CCM_GPR_SHARED15_TOG_m7_lpspi3_ipg_doze_SHIFT (8U)
25229 /*! m7_lpspi3_ipg_doze - m7_lpspi3_ipg_doze */
25230 #define CCM_GPR_SHARED15_TOG_m7_lpspi3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi3_ipg_doze_MASK)
25231 
25232 #define CCM_GPR_SHARED15_TOG_m7_lpspi4_ipg_doze_MASK (0x200U)
25233 #define CCM_GPR_SHARED15_TOG_m7_lpspi4_ipg_doze_SHIFT (9U)
25234 /*! m7_lpspi4_ipg_doze - m7_lpspi4_ipg_doze */
25235 #define CCM_GPR_SHARED15_TOG_m7_lpspi4_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi4_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi4_ipg_doze_MASK)
25236 
25237 #define CCM_GPR_SHARED15_TOG_m7_lpspi5_ipg_doze_MASK (0x400U)
25238 #define CCM_GPR_SHARED15_TOG_m7_lpspi5_ipg_doze_SHIFT (10U)
25239 /*! m7_lpspi5_ipg_doze - m7_lpspi5_ipg_doze */
25240 #define CCM_GPR_SHARED15_TOG_m7_lpspi5_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi5_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi5_ipg_doze_MASK)
25241 
25242 #define CCM_GPR_SHARED15_TOG_m7_lpspi6_ipg_doze_MASK (0x800U)
25243 #define CCM_GPR_SHARED15_TOG_m7_lpspi6_ipg_doze_SHIFT (11U)
25244 /*! m7_lpspi6_ipg_doze - m7_lpspi6_ipg_doze */
25245 #define CCM_GPR_SHARED15_TOG_m7_lpspi6_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_lpspi6_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_lpspi6_ipg_doze_MASK)
25246 
25247 #define CCM_GPR_SHARED15_TOG_m7_sinc1_ipg_doze_MASK (0x1000U)
25248 #define CCM_GPR_SHARED15_TOG_m7_sinc1_ipg_doze_SHIFT (12U)
25249 /*! m7_sinc1_ipg_doze - m7_sinc1_ipg_doze */
25250 #define CCM_GPR_SHARED15_TOG_m7_sinc1_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_sinc1_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_sinc1_ipg_doze_MASK)
25251 
25252 #define CCM_GPR_SHARED15_TOG_m7_sinc2_ipg_doze_MASK (0x2000U)
25253 #define CCM_GPR_SHARED15_TOG_m7_sinc2_ipg_doze_SHIFT (13U)
25254 /*! m7_sinc2_ipg_doze - m7_sinc2_ipg_doze */
25255 #define CCM_GPR_SHARED15_TOG_m7_sinc2_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_sinc2_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_sinc2_ipg_doze_MASK)
25256 
25257 #define CCM_GPR_SHARED15_TOG_m7_sinc3_ipg_doze_MASK (0x4000U)
25258 #define CCM_GPR_SHARED15_TOG_m7_sinc3_ipg_doze_SHIFT (14U)
25259 /*! m7_sinc3_ipg_doze - m7_sinc3_ipg_doze */
25260 #define CCM_GPR_SHARED15_TOG_m7_sinc3_ipg_doze(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_sinc3_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_sinc3_ipg_doze_MASK)
25261 
25262 #define CCM_GPR_SHARED15_TOG_m7_mic_ipg_doze_MASK (0x8000U)
25263 #define CCM_GPR_SHARED15_TOG_m7_mic_ipg_doze_SHIFT (15U)
25264 /*! m7_mic_ipg_doze - m7_mic_ipg_doze */
25265 #define CCM_GPR_SHARED15_TOG_m7_mic_ipg_doze(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_TOG_m7_mic_ipg_doze_SHIFT)) & CCM_GPR_SHARED15_TOG_m7_mic_ipg_doze_MASK)
25266 /*! @} */
25267 
25268 /*! @name GPR_SHARED15_AUTHEN - GPR access control */
25269 /*! @{ */
25270 
25271 #define CCM_GPR_SHARED15_AUTHEN_TZ_USER_MASK     (0x100U)
25272 #define CCM_GPR_SHARED15_AUTHEN_TZ_USER_SHIFT    (8U)
25273 /*! TZ_USER - User access permission
25274  *  0b1..Registers of shared GPR slice can be changed in user mode.
25275  *  0b0..Registers of shared GPR slice cannot be changed in user mode.
25276  */
25277 #define CCM_GPR_SHARED15_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TZ_USER_MASK)
25278 
25279 #define CCM_GPR_SHARED15_AUTHEN_TZ_NS_MASK       (0x200U)
25280 #define CCM_GPR_SHARED15_AUTHEN_TZ_NS_SHIFT      (9U)
25281 /*! TZ_NS - Non-secure access permission
25282  *  0b0..Cannot be changed in Non-secure mode.
25283  *  0b1..Can be changed in Non-secure mode.
25284  */
25285 #define CCM_GPR_SHARED15_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TZ_NS_MASK)
25286 
25287 #define CCM_GPR_SHARED15_AUTHEN_LOCK_TZ_MASK     (0x800U)
25288 #define CCM_GPR_SHARED15_AUTHEN_LOCK_TZ_SHIFT    (11U)
25289 /*! LOCK_TZ - Lock TrustZone settings
25290  *  0b0..TrustZone settings is not locked.
25291  *  0b1..TrustZone settings is locked.
25292  */
25293 #define CCM_GPR_SHARED15_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_LOCK_TZ_MASK)
25294 
25295 #define CCM_GPR_SHARED15_AUTHEN_LOCK_LIST_MASK   (0x8000U)
25296 #define CCM_GPR_SHARED15_AUTHEN_LOCK_LIST_SHIFT  (15U)
25297 /*! LOCK_LIST - Lock white list
25298  *  0b0..Whitelist is not locked.
25299  *  0b1..Whitelist is locked.
25300  */
25301 #define CCM_GPR_SHARED15_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_LOCK_LIST_MASK)
25302 
25303 #define CCM_GPR_SHARED15_AUTHEN_WHITE_LIST_MASK  (0xFFFF0000U)
25304 #define CCM_GPR_SHARED15_AUTHEN_WHITE_LIST_SHIFT (16U)
25305 /*! WHITE_LIST - Whitelist settings */
25306 #define CCM_GPR_SHARED15_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_WHITE_LIST_MASK)
25307 /*! @} */
25308 
25309 /*! @name GPR_SHARED15_AUTHEN_SET - GPR access control */
25310 /*! @{ */
25311 
25312 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_USER_MASK (0x100U)
25313 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_USER_SHIFT (8U)
25314 /*! TZ_USER - User access permission */
25315 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_SET_TZ_USER_MASK)
25316 
25317 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_NS_MASK   (0x200U)
25318 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_NS_SHIFT  (9U)
25319 /*! TZ_NS - Non-secure access permission */
25320 #define CCM_GPR_SHARED15_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_SET_TZ_NS_MASK)
25321 
25322 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_TZ_MASK (0x800U)
25323 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
25324 /*! LOCK_TZ - Lock TrustZone settings */
25325 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_SET_LOCK_TZ_MASK)
25326 
25327 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
25328 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
25329 /*! LOCK_LIST - Lock white list */
25330 #define CCM_GPR_SHARED15_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_SET_LOCK_LIST_MASK)
25331 
25332 #define CCM_GPR_SHARED15_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
25333 #define CCM_GPR_SHARED15_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
25334 /*! WHITE_LIST - Whitelist settings */
25335 #define CCM_GPR_SHARED15_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_SET_WHITE_LIST_MASK)
25336 /*! @} */
25337 
25338 /*! @name GPR_SHARED15_AUTHEN_CLR - GPR access control */
25339 /*! @{ */
25340 
25341 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_USER_MASK (0x100U)
25342 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_USER_SHIFT (8U)
25343 /*! TZ_USER - User access permission */
25344 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_CLR_TZ_USER_MASK)
25345 
25346 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_NS_MASK   (0x200U)
25347 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_NS_SHIFT  (9U)
25348 /*! TZ_NS - Non-secure access permission */
25349 #define CCM_GPR_SHARED15_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_CLR_TZ_NS_MASK)
25350 
25351 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_TZ_MASK (0x800U)
25352 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
25353 /*! LOCK_TZ - Lock TrustZone settings */
25354 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_TZ_MASK)
25355 
25356 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
25357 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
25358 /*! LOCK_LIST - Lock white list */
25359 #define CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_CLR_LOCK_LIST_MASK)
25360 
25361 #define CCM_GPR_SHARED15_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
25362 #define CCM_GPR_SHARED15_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
25363 /*! WHITE_LIST - Whitelist settings */
25364 #define CCM_GPR_SHARED15_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_CLR_WHITE_LIST_MASK)
25365 /*! @} */
25366 
25367 /*! @name GPR_SHARED15_AUTHEN_TOG - GPR access control */
25368 /*! @{ */
25369 
25370 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_USER_MASK (0x100U)
25371 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_USER_SHIFT (8U)
25372 /*! TZ_USER - User access permission */
25373 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TOG_TZ_USER_MASK)
25374 
25375 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_NS_MASK   (0x200U)
25376 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_NS_SHIFT  (9U)
25377 /*! TZ_NS - Non-secure access permission */
25378 #define CCM_GPR_SHARED15_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TOG_TZ_NS_MASK)
25379 
25380 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_TZ_MASK (0x800U)
25381 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
25382 /*! LOCK_TZ - Lock TrustZone settings */
25383 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_TZ_MASK)
25384 
25385 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
25386 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
25387 /*! LOCK_LIST - Lock white list */
25388 #define CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TOG_LOCK_LIST_MASK)
25389 
25390 #define CCM_GPR_SHARED15_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
25391 #define CCM_GPR_SHARED15_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
25392 /*! WHITE_LIST - Whitelist settings */
25393 #define CCM_GPR_SHARED15_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED15_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED15_AUTHEN_TOG_WHITE_LIST_MASK)
25394 /*! @} */
25395 
25396 /*! @name GPR_SHARED_STATUS - General purpose status register for CM33..General purpose status register for CM7 */
25397 /*! @{ */
25398 
25399 #define CCM_GPR_SHARED_STATUS_GPR_STATUS_MASK    (0xFFFFFFFFU)
25400 #define CCM_GPR_SHARED_STATUS_GPR_STATUS_SHIFT   (0U)
25401 /*! GPR_STATUS - Acknowledge indicators for low power handshake */
25402 #define CCM_GPR_SHARED_STATUS_GPR_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_STATUS_GPR_STATUS_SHIFT)) & CCM_GPR_SHARED_STATUS_GPR_STATUS_MASK)
25403 /*! @} */
25404 
25405 /* The count of CCM_GPR_SHARED_STATUS */
25406 #define CCM_GPR_SHARED_STATUS_COUNT              (8U)
25407 
25408 /*! @name GPR_PRIVATE - General purpose register */
25409 /*! @{ */
25410 
25411 #define CCM_GPR_PRIVATE_GPR_MASK                 (0xFFFFFFFFU)
25412 #define CCM_GPR_PRIVATE_GPR_SHIFT                (0U)
25413 /*! GPR - GP register */
25414 #define CCM_GPR_PRIVATE_GPR(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_GPR_SHIFT)) & CCM_GPR_PRIVATE_GPR_MASK)
25415 /*! @} */
25416 
25417 /* The count of CCM_GPR_PRIVATE */
25418 #define CCM_GPR_PRIVATE_COUNT                    (4U)
25419 
25420 /*! @name GPR_PRIVATE_SET - General purpose register */
25421 /*! @{ */
25422 
25423 #define CCM_GPR_PRIVATE_SET_GPR_MASK             (0xFFFFFFFFU)
25424 #define CCM_GPR_PRIVATE_SET_GPR_SHIFT            (0U)
25425 /*! GPR - GP register */
25426 #define CCM_GPR_PRIVATE_SET_GPR(x)               (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE_SET_GPR_MASK)
25427 /*! @} */
25428 
25429 /* The count of CCM_GPR_PRIVATE_SET */
25430 #define CCM_GPR_PRIVATE_SET_COUNT                (4U)
25431 
25432 /*! @name GPR_PRIVATE_CLR - General purpose register */
25433 /*! @{ */
25434 
25435 #define CCM_GPR_PRIVATE_CLR_GPR_MASK             (0xFFFFFFFFU)
25436 #define CCM_GPR_PRIVATE_CLR_GPR_SHIFT            (0U)
25437 /*! GPR - GP register */
25438 #define CCM_GPR_PRIVATE_CLR_GPR(x)               (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE_CLR_GPR_MASK)
25439 /*! @} */
25440 
25441 /* The count of CCM_GPR_PRIVATE_CLR */
25442 #define CCM_GPR_PRIVATE_CLR_COUNT                (4U)
25443 
25444 /*! @name GPR_PRIVATE_TOG - General purpose register */
25445 /*! @{ */
25446 
25447 #define CCM_GPR_PRIVATE_TOG_GPR_MASK             (0xFFFFFFFFU)
25448 #define CCM_GPR_PRIVATE_TOG_GPR_SHIFT            (0U)
25449 /*! GPR - GP register */
25450 #define CCM_GPR_PRIVATE_TOG_GPR(x)               (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE_TOG_GPR_MASK)
25451 /*! @} */
25452 
25453 /* The count of CCM_GPR_PRIVATE_TOG */
25454 #define CCM_GPR_PRIVATE_TOG_COUNT                (4U)
25455 
25456 /*! @name GPR_PRIVATE_AUTHEN - GPR access control */
25457 /*! @{ */
25458 
25459 #define CCM_GPR_PRIVATE_AUTHEN_TZ_USER_MASK      (0x100U)
25460 #define CCM_GPR_PRIVATE_AUTHEN_TZ_USER_SHIFT     (8U)
25461 /*! TZ_USER - User access permission
25462  *  0b1..Registers of private GPR can be changed in user mode.
25463  *  0b0..Registers of private GPR cannot be changed in user mode.
25464  */
25465 #define CCM_GPR_PRIVATE_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TZ_USER_MASK)
25466 
25467 #define CCM_GPR_PRIVATE_AUTHEN_TZ_NS_MASK        (0x200U)
25468 #define CCM_GPR_PRIVATE_AUTHEN_TZ_NS_SHIFT       (9U)
25469 /*! TZ_NS - Non-secure access permission
25470  *  0b0..Cannot be changed in Non-secure mode.
25471  *  0b1..Can be changed in Non-secure mode.
25472  */
25473 #define CCM_GPR_PRIVATE_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TZ_NS_MASK)
25474 
25475 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_MASK      (0x800U)
25476 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_SHIFT     (11U)
25477 /*! LOCK_TZ - Lock TrustZone settings
25478  *  0b0..TrustZone settings is not locked.
25479  *  0b1..TrustZone settings is locked.
25480  */
25481 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_MASK)
25482 
25483 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_MASK    (0x8000U)
25484 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_SHIFT   (15U)
25485 /*! LOCK_LIST - Lock white list
25486  *  0b0..Whitelist is not locked.
25487  *  0b1..Whitelist is locked.
25488  */
25489 #define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_MASK)
25490 
25491 #define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_MASK   (0xFFFF0000U)
25492 #define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_SHIFT  (16U)
25493 /*! WHITE_LIST - Whitelist settings */
25494 #define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_MASK)
25495 /*! @} */
25496 
25497 /* The count of CCM_GPR_PRIVATE_AUTHEN */
25498 #define CCM_GPR_PRIVATE_AUTHEN_COUNT             (4U)
25499 
25500 /*! @name GPR_PRIVATE_AUTHEN_SET - GPR access control */
25501 /*! @{ */
25502 
25503 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_MASK  (0x100U)
25504 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_SHIFT (8U)
25505 /*! TZ_USER - User access permission */
25506 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_MASK)
25507 
25508 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_MASK    (0x200U)
25509 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_SHIFT   (9U)
25510 /*! TZ_NS - Non-secure access permission */
25511 #define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_MASK)
25512 
25513 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_MASK  (0x800U)
25514 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_SHIFT (11U)
25515 /*! LOCK_TZ - Lock TrustZone settings */
25516 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_MASK)
25517 
25518 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_MASK (0x8000U)
25519 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_SHIFT (15U)
25520 /*! LOCK_LIST - Lock white list */
25521 #define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_MASK)
25522 
25523 #define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_MASK (0xFFFF0000U)
25524 #define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_SHIFT (16U)
25525 /*! WHITE_LIST - Whitelist settings */
25526 #define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_MASK)
25527 /*! @} */
25528 
25529 /* The count of CCM_GPR_PRIVATE_AUTHEN_SET */
25530 #define CCM_GPR_PRIVATE_AUTHEN_SET_COUNT         (4U)
25531 
25532 /*! @name GPR_PRIVATE_AUTHEN_CLR - GPR access control */
25533 /*! @{ */
25534 
25535 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_MASK  (0x100U)
25536 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_SHIFT (8U)
25537 /*! TZ_USER - User access permission */
25538 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_MASK)
25539 
25540 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_MASK    (0x200U)
25541 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_SHIFT   (9U)
25542 /*! TZ_NS - Non-secure access permission */
25543 #define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_MASK)
25544 
25545 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_MASK  (0x800U)
25546 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_SHIFT (11U)
25547 /*! LOCK_TZ - Lock TrustZone settings */
25548 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_MASK)
25549 
25550 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_MASK (0x8000U)
25551 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_SHIFT (15U)
25552 /*! LOCK_LIST - Lock white list */
25553 #define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_MASK)
25554 
25555 #define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_MASK (0xFFFF0000U)
25556 #define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_SHIFT (16U)
25557 /*! WHITE_LIST - Whitelist settings */
25558 #define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_MASK)
25559 /*! @} */
25560 
25561 /* The count of CCM_GPR_PRIVATE_AUTHEN_CLR */
25562 #define CCM_GPR_PRIVATE_AUTHEN_CLR_COUNT         (4U)
25563 
25564 /*! @name GPR_PRIVATE_AUTHEN_TOG - GPR access control */
25565 /*! @{ */
25566 
25567 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_MASK  (0x100U)
25568 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_SHIFT (8U)
25569 /*! TZ_USER - User access permission */
25570 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_MASK)
25571 
25572 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_MASK    (0x200U)
25573 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_SHIFT   (9U)
25574 /*! TZ_NS - Non-secure access permission */
25575 #define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_MASK)
25576 
25577 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_MASK  (0x800U)
25578 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_SHIFT (11U)
25579 /*! LOCK_TZ - Lock TrustZone settings */
25580 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_MASK)
25581 
25582 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_MASK (0x8000U)
25583 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_SHIFT (15U)
25584 /*! LOCK_LIST - Lock white list */
25585 #define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_MASK)
25586 
25587 #define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_MASK (0xFFFF0000U)
25588 #define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_SHIFT (16U)
25589 /*! WHITE_LIST - Whitelist settings */
25590 #define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_MASK)
25591 /*! @} */
25592 
25593 /* The count of CCM_GPR_PRIVATE_AUTHEN_TOG */
25594 #define CCM_GPR_PRIVATE_AUTHEN_TOG_COUNT         (4U)
25595 
25596 /*! @name OSCPLL_DIRECT - Clock source direct control */
25597 /*! @{ */
25598 
25599 #define CCM_OSCPLL_DIRECT_ON_MASK                (0x1U)
25600 #define CCM_OSCPLL_DIRECT_ON_SHIFT               (0U)
25601 /*! ON - Turn on clock source
25602  *  0b0..Clock source is OFF.
25603  *  0b1..Clock source is ON.
25604  */
25605 #define CCM_OSCPLL_DIRECT_ON(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
25606 /*! @} */
25607 
25608 /* The count of CCM_OSCPLL_DIRECT */
25609 #define CCM_OSCPLL_DIRECT_COUNT                  (25U)
25610 
25611 /*! @name OSCPLL_LPM0 - Clock source low power mode setting */
25612 /*! @{ */
25613 
25614 #define CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK      (0x7U)
25615 #define CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT     (0U)
25616 /*! LPM_SETTING_D0 - Clock Source LPM in DOMAIN0
25617  *  0b000..Clock Source will be OFF in any CPU mode.
25618  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25619  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25620  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25621  */
25622 #define CCM_OSCPLL_LPM0_LPM_SETTING_D0(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK)
25623 
25624 #define CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK      (0x70U)
25625 #define CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT     (4U)
25626 /*! LPM_SETTING_D1 - Clock Source LPM in DOMAIN1
25627  *  0b000..Clock Source will be OFF in any CPU mode.
25628  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25629  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25630  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25631  */
25632 #define CCM_OSCPLL_LPM0_LPM_SETTING_D1(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK)
25633 
25634 #define CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK      (0x700U)
25635 #define CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT     (8U)
25636 /*! LPM_SETTING_D2 - Clock Source LPM in DOMAIN2
25637  *  0b000..Clock Source will be OFF in any CPU mode.
25638  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25639  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25640  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25641  */
25642 #define CCM_OSCPLL_LPM0_LPM_SETTING_D2(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK)
25643 
25644 #define CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK      (0x7000U)
25645 #define CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT     (12U)
25646 /*! LPM_SETTING_D3 - Clock Source LPM in DOMAIN3
25647  *  0b000..Clock Source will be OFF in any CPU mode.
25648  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25649  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25650  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25651  */
25652 #define CCM_OSCPLL_LPM0_LPM_SETTING_D3(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK)
25653 
25654 #define CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK      (0x70000U)
25655 #define CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT     (16U)
25656 /*! LPM_SETTING_D4 - Clock Source LPM in DOMAIN4
25657  *  0b000..Clock Source will be OFF in any CPU mode.
25658  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25659  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25660  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25661  */
25662 #define CCM_OSCPLL_LPM0_LPM_SETTING_D4(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK)
25663 
25664 #define CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK      (0x700000U)
25665 #define CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT     (20U)
25666 /*! LPM_SETTING_D5 - Clock Source LPM in DOMAIN5
25667  *  0b000..Clock Source will be OFF in any CPU mode.
25668  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25669  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25670  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25671  */
25672 #define CCM_OSCPLL_LPM0_LPM_SETTING_D5(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK)
25673 
25674 #define CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK      (0x7000000U)
25675 #define CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT     (24U)
25676 /*! LPM_SETTING_D6 - Clock Source LPM in DOMAIN6
25677  *  0b000..Clock Source will be OFF in any CPU mode.
25678  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25679  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25680  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25681  */
25682 #define CCM_OSCPLL_LPM0_LPM_SETTING_D6(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK)
25683 
25684 #define CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK      (0x70000000U)
25685 #define CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT     (28U)
25686 /*! LPM_SETTING_D7 - Clock Source LPM in DOMAIN7
25687  *  0b000..Clock Source will be OFF in any CPU mode.
25688  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25689  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25690  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25691  */
25692 #define CCM_OSCPLL_LPM0_LPM_SETTING_D7(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK)
25693 /*! @} */
25694 
25695 /* The count of CCM_OSCPLL_LPM0 */
25696 #define CCM_OSCPLL_LPM0_COUNT                    (25U)
25697 
25698 /*! @name OSCPLL_LPM1 - clock source low power mode setting */
25699 /*! @{ */
25700 
25701 #define CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK      (0x7U)
25702 #define CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT     (0U)
25703 /*! LPM_SETTING_D8 - Clock Source LPM in DOMAIN8
25704  *  0b000..Clock Source will be OFF in any CPU mode.
25705  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25706  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25707  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25708  */
25709 #define CCM_OSCPLL_LPM1_LPM_SETTING_D8(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK)
25710 
25711 #define CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK      (0x70U)
25712 #define CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT     (4U)
25713 /*! LPM_SETTING_D9 - Clock Source LPM in DOMAIN9
25714  *  0b000..Clock Source will be OFF in any CPU mode.
25715  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25716  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25717  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25718  */
25719 #define CCM_OSCPLL_LPM1_LPM_SETTING_D9(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK)
25720 
25721 #define CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK     (0x700U)
25722 #define CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT    (8U)
25723 /*! LPM_SETTING_D10 - Clock Source LPM in DOMAIN10
25724  *  0b000..Clock Source will be OFF in any CPU mode.
25725  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25726  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25727  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25728  */
25729 #define CCM_OSCPLL_LPM1_LPM_SETTING_D10(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK)
25730 
25731 #define CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK     (0x7000U)
25732 #define CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT    (12U)
25733 /*! LPM_SETTING_D11 - Clock Source LPM in DOMAIN11
25734  *  0b000..Clock Source will be OFF in any CPU mode.
25735  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25736  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25737  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25738  */
25739 #define CCM_OSCPLL_LPM1_LPM_SETTING_D11(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK)
25740 
25741 #define CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK     (0x70000U)
25742 #define CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT    (16U)
25743 /*! LPM_SETTING_D12 - Clock Source LPM in DOMAIN12
25744  *  0b000..Clock Source will be OFF in any CPU mode.
25745  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25746  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25747  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25748  */
25749 #define CCM_OSCPLL_LPM1_LPM_SETTING_D12(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK)
25750 
25751 #define CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK     (0x700000U)
25752 #define CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT    (20U)
25753 /*! LPM_SETTING_D13 - Clock Source LPM in DOMAIN13
25754  *  0b000..Clock Source will be OFF in any CPU mode.
25755  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25756  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25757  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25758  */
25759 #define CCM_OSCPLL_LPM1_LPM_SETTING_D13(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK)
25760 
25761 #define CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK     (0x7000000U)
25762 #define CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT    (24U)
25763 /*! LPM_SETTING_D14 - Clock Source LPM in DOMAIN14
25764  *  0b000..Clock Source will be OFF in any CPU mode.
25765  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25766  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25767  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25768  */
25769 #define CCM_OSCPLL_LPM1_LPM_SETTING_D14(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK)
25770 
25771 #define CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK     (0x70000000U)
25772 #define CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT    (28U)
25773 /*! LPM_SETTING_D15 - Clock Source LPM in DOMAIN15
25774  *  0b000..Clock Source will be OFF in any CPU mode.
25775  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25776  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25777  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25778  */
25779 #define CCM_OSCPLL_LPM1_LPM_SETTING_D15(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK)
25780 /*! @} */
25781 
25782 /* The count of CCM_OSCPLL_LPM1 */
25783 #define CCM_OSCPLL_LPM1_COUNT                    (25U)
25784 
25785 /*! @name OSCPLL_LPM_CUR - LPM setting of current CPU domain */
25786 /*! @{ */
25787 
25788 #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK  (0x7U)
25789 #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U)
25790 /*! LPM_SETTING_CUR - LPM settings value for current CPU domain that is reading this register.
25791  *  0b000..Clock Source will be OFF in any CPU mode.
25792  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25793  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25794  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25795  */
25796 #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK)
25797 /*! @} */
25798 
25799 /* The count of CCM_OSCPLL_LPM_CUR */
25800 #define CCM_OSCPLL_LPM_CUR_COUNT                 (25U)
25801 
25802 /*! @name OSCPLL_STATUS0 - Clock source working status */
25803 /*! @{ */
25804 
25805 #define CCM_OSCPLL_STATUS0_ON_MASK               (0x1U)
25806 #define CCM_OSCPLL_STATUS0_ON_SHIFT              (0U)
25807 /*! ON - Clock source current state
25808  *  0b0..Clock source is OFF.
25809  *  0b1..Clock source is ON.
25810  */
25811 #define CCM_OSCPLL_STATUS0_ON(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
25812 
25813 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK     (0x10U)
25814 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT    (4U)
25815 /*! STATUS_EARLY - Clock source active
25816  *  0b0..Clock source is not active
25817  *  0b1..Clock source is active
25818  */
25819 #define CCM_OSCPLL_STATUS0_STATUS_EARLY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
25820 
25821 #define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK      (0x20U)
25822 #define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT     (5U)
25823 /*! STATUS_LATE - Clock source ready
25824  *  0b0..Clock source is not ready to use
25825  *  0b1..Clock source is ready to use
25826  */
25827 #define CCM_OSCPLL_STATUS0_STATUS_LATE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
25828 
25829 #define CCM_OSCPLL_STATUS0_IN_USE_MASK           (0x1000U)
25830 #define CCM_OSCPLL_STATUS0_IN_USE_SHIFT          (12U)
25831 /*! IN_USE - This Clock Source is being used or not.
25832  *  0b0..Clock Source is not being used.
25833  *  0b1..Clock Source is being used.
25834  */
25835 #define CCM_OSCPLL_STATUS0_IN_USE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
25836 /*! @} */
25837 
25838 /* The count of CCM_OSCPLL_STATUS0 */
25839 #define CCM_OSCPLL_STATUS0_COUNT                 (25U)
25840 
25841 /*! @name OSCPLL_STATUS1 - Clock source domain status */
25842 /*! @{ */
25843 
25844 #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK    (0xFFFFU)
25845 #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT   (0U)
25846 /*! DOMAIN_ACTIVE - Domain active */
25847 #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK)
25848 
25849 #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK    (0xFFFF0000U)
25850 #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT   (16U)
25851 /*! DOMAIN_ENABLE - Domain enable */
25852 #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK)
25853 /*! @} */
25854 
25855 /* The count of CCM_OSCPLL_STATUS1 */
25856 #define CCM_OSCPLL_STATUS1_COUNT                 (25U)
25857 
25858 /*! @name OSCPLL_AUTHEN - Clock Source access control */
25859 /*! @{ */
25860 
25861 #define CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK       (0x4U)
25862 #define CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT      (2U)
25863 /*! CPULPM_MODE - CPULPM mode enable
25864  *  0b0..Disable CPULPM mode.
25865  *  0b1..Enable CPULPM mode.
25866  */
25867 #define CCM_OSCPLL_AUTHEN_CPULPM_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK)
25868 
25869 #define CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK         (0x8U)
25870 #define CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT        (3U)
25871 /*! AUTO_CTRL - Auto mode enable
25872  *  0b0..Disable Auto mode
25873  *  0b1..Enable Auto mode
25874  */
25875 #define CCM_OSCPLL_AUTHEN_AUTO_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT)) & CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK)
25876 
25877 #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK           (0x100U)
25878 #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT          (8U)
25879 /*! TZ_USER - User access permission
25880  *  0b1..Clock Source settings can be changed in user mode.
25881  *  0b0..Clock Source settings cannot be changed in user mode.
25882  */
25883 #define CCM_OSCPLL_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
25884 
25885 #define CCM_OSCPLL_AUTHEN_TZ_NS_MASK             (0x200U)
25886 #define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT            (9U)
25887 /*! TZ_NS - Non-secure access permission
25888  *  0b0..Cannot be changed in Non-secure mode.
25889  *  0b1..Can be changed in Non-secure mode.
25890  */
25891 #define CCM_OSCPLL_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
25892 
25893 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK           (0x800U)
25894 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT          (11U)
25895 /*! LOCK_TZ - Lock TrustZone settings
25896  *  0b0..TrustZone settings is not locked.
25897  *  0b1..TrustZone settings is locked.
25898  */
25899 #define CCM_OSCPLL_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
25900 
25901 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK         (0x8000U)
25902 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT        (15U)
25903 /*! LOCK_LIST - Lock white list
25904  *  0b0..Whitelist is not locked.
25905  *  0b1..Whitelist is locked.
25906  */
25907 #define CCM_OSCPLL_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
25908 
25909 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK        (0xFFFF0000U)
25910 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT       (16U)
25911 /*! WHITE_LIST - Whitelist */
25912 #define CCM_OSCPLL_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
25913 /*! @} */
25914 
25915 /* The count of CCM_OSCPLL_AUTHEN */
25916 #define CCM_OSCPLL_AUTHEN_COUNT                  (25U)
25917 
25918 /*! @name LPCG_DIRECT - LPCG direct control */
25919 /*! @{ */
25920 
25921 #define CCM_LPCG_DIRECT_ON_MASK                  (0x1U)
25922 #define CCM_LPCG_DIRECT_ON_SHIFT                 (0U)
25923 /*! ON - Turn on LPCG
25924  *  0b0..LPCG is OFF.
25925  *  0b1..LPCG is ON.
25926  */
25927 #define CCM_LPCG_DIRECT_ON(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
25928 
25929 #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK (0x4U)
25930 #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT (2U)
25931 /*! CLKOFF_ACK_TIMEOUT_EN - Clock off handshake timeout enable
25932  *  0b0..disable
25933  *  0b1..enable
25934  */
25935 #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT)) & CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK)
25936 /*! @} */
25937 
25938 /* The count of CCM_LPCG_DIRECT */
25939 #define CCM_LPCG_DIRECT_COUNT                    (149U)
25940 
25941 /*! @name LPCG_LPM0 - Clock source low power mode setting */
25942 /*! @{ */
25943 
25944 #define CCM_LPCG_LPM0_LPM_SETTING_D0_MASK        (0x7U)
25945 #define CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT       (0U)
25946 /*! LPM_SETTING_D0 - Clock Source LPM in DOMAIN0
25947  *  0b000..Clock Source will be OFF in any CPU mode.
25948  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25949  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25950  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25951  */
25952 #define CCM_LPCG_LPM0_LPM_SETTING_D0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D0_MASK)
25953 
25954 #define CCM_LPCG_LPM0_LPM_SETTING_D1_MASK        (0x70U)
25955 #define CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT       (4U)
25956 /*! LPM_SETTING_D1 - Clock Source LPM in DOMAIN1
25957  *  0b000..Clock Source will be OFF in any CPU mode.
25958  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25959  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25960  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25961  */
25962 #define CCM_LPCG_LPM0_LPM_SETTING_D1(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D1_MASK)
25963 
25964 #define CCM_LPCG_LPM0_LPM_SETTING_D2_MASK        (0x700U)
25965 #define CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT       (8U)
25966 /*! LPM_SETTING_D2 - Clock Source LPM in DOMAIN2
25967  *  0b000..Clock Source will be OFF in any CPU mode.
25968  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25969  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25970  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25971  */
25972 #define CCM_LPCG_LPM0_LPM_SETTING_D2(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D2_MASK)
25973 
25974 #define CCM_LPCG_LPM0_LPM_SETTING_D3_MASK        (0x7000U)
25975 #define CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT       (12U)
25976 /*! LPM_SETTING_D3 - Clock Source LPM in DOMAIN3
25977  *  0b000..Clock Source will be OFF in any CPU mode.
25978  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25979  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25980  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25981  */
25982 #define CCM_LPCG_LPM0_LPM_SETTING_D3(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D3_MASK)
25983 
25984 #define CCM_LPCG_LPM0_LPM_SETTING_D4_MASK        (0x70000U)
25985 #define CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT       (16U)
25986 /*! LPM_SETTING_D4 - Clock Source LPM in DOMAIN4
25987  *  0b000..Clock Source will be OFF in any CPU mode.
25988  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25989  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
25990  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
25991  */
25992 #define CCM_LPCG_LPM0_LPM_SETTING_D4(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D4_MASK)
25993 
25994 #define CCM_LPCG_LPM0_LPM_SETTING_D5_MASK        (0x700000U)
25995 #define CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT       (20U)
25996 /*! LPM_SETTING_D5 - Clock Source LPM in DOMAIN5
25997  *  0b000..Clock Source will be OFF in any CPU mode.
25998  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
25999  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26000  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26001  */
26002 #define CCM_LPCG_LPM0_LPM_SETTING_D5(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D5_MASK)
26003 
26004 #define CCM_LPCG_LPM0_LPM_SETTING_D6_MASK        (0x7000000U)
26005 #define CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT       (24U)
26006 /*! LPM_SETTING_D6 - Clock Source LPM in DOMAIN6
26007  *  0b000..Clock Source will be OFF in any CPU mode.
26008  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26009  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26010  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26011  */
26012 #define CCM_LPCG_LPM0_LPM_SETTING_D6(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D6_MASK)
26013 
26014 #define CCM_LPCG_LPM0_LPM_SETTING_D7_MASK        (0x70000000U)
26015 #define CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT       (28U)
26016 /*! LPM_SETTING_D7 - Clock Source LPM in DOMAIN7
26017  *  0b000..Clock Source will be OFF in any CPU mode.
26018  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26019  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26020  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26021  */
26022 #define CCM_LPCG_LPM0_LPM_SETTING_D7(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D7_MASK)
26023 /*! @} */
26024 
26025 /* The count of CCM_LPCG_LPM0 */
26026 #define CCM_LPCG_LPM0_COUNT                      (149U)
26027 
26028 /*! @name LPCG_LPM1 - clock source low power mode setting */
26029 /*! @{ */
26030 
26031 #define CCM_LPCG_LPM1_LPM_SETTING_D8_MASK        (0x7U)
26032 #define CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT       (0U)
26033 /*! LPM_SETTING_D8 - Clock Source LPM in DOMAIN8
26034  *  0b000..Clock Source will be OFF in any CPU mode.
26035  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26036  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26037  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26038  */
26039 #define CCM_LPCG_LPM1_LPM_SETTING_D8(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D8_MASK)
26040 
26041 #define CCM_LPCG_LPM1_LPM_SETTING_D9_MASK        (0x70U)
26042 #define CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT       (4U)
26043 /*! LPM_SETTING_D9 - Clock Source LPM in DOMAIN9
26044  *  0b000..Clock Source will be OFF in any CPU mode.
26045  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26046  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26047  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26048  */
26049 #define CCM_LPCG_LPM1_LPM_SETTING_D9(x)          (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D9_MASK)
26050 
26051 #define CCM_LPCG_LPM1_LPM_SETTING_D10_MASK       (0x700U)
26052 #define CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT      (8U)
26053 /*! LPM_SETTING_D10 - Clock Source LPM in DOMAIN10
26054  *  0b000..Clock Source will be OFF in any CPU mode.
26055  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26056  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26057  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26058  */
26059 #define CCM_LPCG_LPM1_LPM_SETTING_D10(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D10_MASK)
26060 
26061 #define CCM_LPCG_LPM1_LPM_SETTING_D11_MASK       (0x7000U)
26062 #define CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT      (12U)
26063 /*! LPM_SETTING_D11 - Clock Source LPM in DOMAIN11
26064  *  0b000..Clock Source will be OFF in any CPU mode.
26065  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26066  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26067  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26068  */
26069 #define CCM_LPCG_LPM1_LPM_SETTING_D11(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D11_MASK)
26070 
26071 #define CCM_LPCG_LPM1_LPM_SETTING_D12_MASK       (0x70000U)
26072 #define CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT      (16U)
26073 /*! LPM_SETTING_D12 - Clock Source LPM in DOMAIN12
26074  *  0b000..Clock Source will be OFF in any CPU mode.
26075  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26076  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26077  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26078  */
26079 #define CCM_LPCG_LPM1_LPM_SETTING_D12(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D12_MASK)
26080 
26081 #define CCM_LPCG_LPM1_LPM_SETTING_D13_MASK       (0x700000U)
26082 #define CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT      (20U)
26083 /*! LPM_SETTING_D13 - Clock Source LPM in DOMAIN13
26084  *  0b000..Clock Source will be OFF in any CPU mode.
26085  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26086  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26087  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26088  */
26089 #define CCM_LPCG_LPM1_LPM_SETTING_D13(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D13_MASK)
26090 
26091 #define CCM_LPCG_LPM1_LPM_SETTING_D14_MASK       (0x7000000U)
26092 #define CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT      (24U)
26093 /*! LPM_SETTING_D14 - Clock Source LPM in DOMAIN14
26094  *  0b000..Clock Source will be OFF in any CPU mode.
26095  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26096  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26097  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26098  */
26099 #define CCM_LPCG_LPM1_LPM_SETTING_D14(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D14_MASK)
26100 
26101 #define CCM_LPCG_LPM1_LPM_SETTING_D15_MASK       (0x70000000U)
26102 #define CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT      (28U)
26103 /*! LPM_SETTING_D15 - Clock Source LPM in DOMAIN15
26104  *  0b000..Clock Source will be OFF in any CPU mode.
26105  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26106  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26107  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26108  */
26109 #define CCM_LPCG_LPM1_LPM_SETTING_D15(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D15_MASK)
26110 /*! @} */
26111 
26112 /* The count of CCM_LPCG_LPM1 */
26113 #define CCM_LPCG_LPM1_COUNT                      (149U)
26114 
26115 /*! @name LPCG_LPM_CUR - LPM setting of current CPU domain */
26116 /*! @{ */
26117 
26118 #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK    (0x7U)
26119 #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT   (0U)
26120 /*! LPM_SETTING_CUR - LPM settings value for current CPU domain that is reading this register.
26121  *  0b000..Clock Source will be OFF in any CPU mode.
26122  *  0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
26123  *  0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
26124  *  0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
26125  */
26126 #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK)
26127 /*! @} */
26128 
26129 /* The count of CCM_LPCG_LPM_CUR */
26130 #define CCM_LPCG_LPM_CUR_COUNT                   (149U)
26131 
26132 /*! @name LPCG_STATUS0 - LPCG working status */
26133 /*! @{ */
26134 
26135 #define CCM_LPCG_STATUS0_ON_MASK                 (0x1U)
26136 #define CCM_LPCG_STATUS0_ON_SHIFT                (0U)
26137 /*! ON - LPCG work status
26138  *  0b0..LPCG is OFF.
26139  *  0b1..LPCG is ON.
26140  */
26141 #define CCM_LPCG_STATUS0_ON(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
26142 /*! @} */
26143 
26144 /* The count of CCM_LPCG_STATUS0 */
26145 #define CCM_LPCG_STATUS0_COUNT                   (149U)
26146 
26147 /*! @name LPCG_STATUS1 - LPCG domain status */
26148 /*! @{ */
26149 
26150 #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK      (0xFFFFU)
26151 #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT     (0U)
26152 /*! DOMAIN_ACTIVE - Domain active */
26153 #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK)
26154 
26155 #define CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK      (0xFFFF0000U)
26156 #define CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT     (16U)
26157 /*! DOMAIN_ENABLE - Domain enable */
26158 #define CCM_LPCG_STATUS1_DOMAIN_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK)
26159 /*! @} */
26160 
26161 /* The count of CCM_LPCG_STATUS1 */
26162 #define CCM_LPCG_STATUS1_COUNT                   (149U)
26163 
26164 /*! @name LPCG_AUTHEN - LPCG access control */
26165 /*! @{ */
26166 
26167 #define CCM_LPCG_AUTHEN_CPULPM_MODE_MASK         (0x4U)
26168 #define CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT        (2U)
26169 /*! CPULPM_MODE - CPULPM mode enable
26170  *  0b0..Disable CPULPM mode, this LPCG is in Direct Control mode.
26171  *  0b1..Enable CPULPM mode, this LPCG is in CPULPM mode.
26172  */
26173 #define CCM_LPCG_AUTHEN_CPULPM_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MODE_MASK)
26174 
26175 #define CCM_LPCG_AUTHEN_ACK_MODE_MASK            (0x10U)
26176 #define CCM_LPCG_AUTHEN_ACK_MODE_SHIFT           (4U)
26177 /*! ACK_MODE - CPULPM mode enable
26178  *  0b0..Disable ACK mode.
26179  *  0b1..Enable ACK mode.
26180  */
26181 #define CCM_LPCG_AUTHEN_ACK_MODE(x)              (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_ACK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_ACK_MODE_MASK)
26182 
26183 #define CCM_LPCG_AUTHEN_TZ_USER_MASK             (0x100U)
26184 #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT            (8U)
26185 /*! TZ_USER - User access permission
26186  *  0b1..LPCG settings can be changed in user mode.
26187  *  0b0..LPCG settings cannot be changed in user mode.
26188  */
26189 #define CCM_LPCG_AUTHEN_TZ_USER(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
26190 
26191 #define CCM_LPCG_AUTHEN_TZ_NS_MASK               (0x200U)
26192 #define CCM_LPCG_AUTHEN_TZ_NS_SHIFT              (9U)
26193 /*! TZ_NS - Non-secure access permission
26194  *  0b0..Cannot be changed in Non-secure mode.
26195  *  0b1..Can be changed in Non-secure mode.
26196  */
26197 #define CCM_LPCG_AUTHEN_TZ_NS(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
26198 
26199 #define CCM_LPCG_AUTHEN_LOCK_TZ_MASK             (0x800U)
26200 #define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT            (11U)
26201 /*! LOCK_TZ - Lock TrustZone settings
26202  *  0b0..TrustZone settings is not locked.
26203  *  0b1..TrustZone settings is locked.
26204  */
26205 #define CCM_LPCG_AUTHEN_LOCK_TZ(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
26206 
26207 #define CCM_LPCG_AUTHEN_LOCK_LIST_MASK           (0x8000U)
26208 #define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT          (15U)
26209 /*! LOCK_LIST - Lock white list
26210  *  0b0..Whitelist is not locked.
26211  *  0b1..Whitelist is locked.
26212  */
26213 #define CCM_LPCG_AUTHEN_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
26214 
26215 #define CCM_LPCG_AUTHEN_WHITE_LIST_MASK          (0xFFFF0000U)
26216 #define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT         (16U)
26217 /*! WHITE_LIST - Whitelist */
26218 #define CCM_LPCG_AUTHEN_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
26219 /*! @} */
26220 
26221 /* The count of CCM_LPCG_AUTHEN */
26222 #define CCM_LPCG_AUTHEN_COUNT                    (149U)
26223 
26224 
26225 /*!
26226  * @}
26227  */ /* end of group CCM_Register_Masks */
26228 
26229 
26230 /* CCM - Peripheral instance base addresses */
26231 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
26232   /** Peripheral CCM base address */
26233   #define CCM_BASE                                 (0x54450000u)
26234   /** Peripheral CCM base address */
26235   #define CCM_BASE_NS                              (0x44450000u)
26236   /** Peripheral CCM base pointer */
26237   #define CCM                                      ((CCM_Type *)CCM_BASE)
26238   /** Peripheral CCM base pointer */
26239   #define CCM_NS                                   ((CCM_Type *)CCM_BASE_NS)
26240   /** Array initializer of CCM peripheral base addresses */
26241   #define CCM_BASE_ADDRS                           { CCM_BASE }
26242   /** Array initializer of CCM peripheral base pointers */
26243   #define CCM_BASE_PTRS                            { CCM }
26244   /** Array initializer of CCM peripheral base addresses */
26245   #define CCM_BASE_ADDRS_NS                        { CCM_BASE_NS }
26246   /** Array initializer of CCM peripheral base pointers */
26247   #define CCM_BASE_PTRS_NS                         { CCM_NS }
26248 #else
26249   /** Peripheral CCM base address */
26250   #define CCM_BASE                                 (0x44450000u)
26251   /** Peripheral CCM base pointer */
26252   #define CCM                                      ((CCM_Type *)CCM_BASE)
26253   /** Array initializer of CCM peripheral base addresses */
26254   #define CCM_BASE_ADDRS                           { CCM_BASE }
26255   /** Array initializer of CCM peripheral base pointers */
26256   #define CCM_BASE_PTRS                            { CCM }
26257 #endif
26258 
26259 /*!
26260  * @}
26261  */ /* end of group CCM_Peripheral_Access_Layer */
26262 
26263 
26264 /* ----------------------------------------------------------------------------
26265    -- CMP Peripheral Access Layer
26266    ---------------------------------------------------------------------------- */
26267 
26268 /*!
26269  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
26270  * @{
26271  */
26272 
26273 /** CMP - Register Layout Typedef */
26274 typedef struct {
26275   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
26276   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
26277   __IO uint32_t C0;                                /**< CMP Control 0, offset: 0x8 */
26278   __IO uint32_t C1;                                /**< CMP Control 1, offset: 0xC */
26279   __IO uint32_t C2;                                /**< CMP Control 2, offset: 0x10 */
26280   __IO uint32_t C3;                                /**< CMP Control 3, offset: 0x14 */
26281 } CMP_Type;
26282 
26283 /* ----------------------------------------------------------------------------
26284    -- CMP Register Masks
26285    ---------------------------------------------------------------------------- */
26286 
26287 /*!
26288  * @addtogroup CMP_Register_Masks CMP Register Masks
26289  * @{
26290  */
26291 
26292 /*! @name VERID - Version ID Register */
26293 /*! @{ */
26294 
26295 #define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
26296 #define CMP_VERID_FEATURE_SHIFT                  (0U)
26297 /*! FEATURE - Feature Specification Number */
26298 #define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
26299 
26300 #define CMP_VERID_MINOR_MASK                     (0xFF0000U)
26301 #define CMP_VERID_MINOR_SHIFT                    (16U)
26302 /*! MINOR - Minor Version Number */
26303 #define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
26304 
26305 #define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
26306 #define CMP_VERID_MAJOR_SHIFT                    (24U)
26307 /*! MAJOR - Major Version Number */
26308 #define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
26309 /*! @} */
26310 
26311 /*! @name PARAM - Parameter Register */
26312 /*! @{ */
26313 
26314 #define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
26315 #define CMP_PARAM_PARAM_SHIFT                    (0U)
26316 /*! PARAM - Parameters */
26317 #define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
26318 /*! @} */
26319 
26320 /*! @name C0 - CMP Control 0 */
26321 /*! @{ */
26322 
26323 #define CMP_C0_FILTER_CNT_MASK                   (0x70U)
26324 #define CMP_C0_FILTER_CNT_SHIFT                  (4U)
26325 /*! FILTER_CNT - Filter Sample Count
26326  *  0b000..Filter is disabled (if C0[SE] = 1, then COUT is a logic zero (this is not a legal state, and is not
26327  *         recommended); if C0[SE] = 0, COUT = COUTA)
26328  *  0b001..One consecutive sample (comparator output is simply sampled)
26329  *  0b010..Two consecutive samples
26330  *  0b011..Three consecutive samples
26331  *  0b100..Four consecutive samples
26332  *  0b101..Five consecutive samples
26333  *  0b110..Six consecutive samples
26334  *  0b111..Seven consecutive samples
26335  */
26336 #define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
26337 
26338 #define CMP_C0_EN_MASK                           (0x100U)
26339 #define CMP_C0_EN_SHIFT                          (8U)
26340 /*! EN - Analog Comparator Module Enable
26341  *  0b0..Disable
26342  *  0b1..Enable
26343  */
26344 #define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
26345 
26346 #define CMP_C0_OPE_MASK                          (0x200U)
26347 #define CMP_C0_OPE_SHIFT                         (9U)
26348 /*! OPE - Comparator Output Pin Enable
26349  *  0b0..Disable
26350  *  0b1..Enable
26351  */
26352 #define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
26353 
26354 #define CMP_C0_COS_MASK                          (0x400U)
26355 #define CMP_C0_COS_SHIFT                         (10U)
26356 /*! COS - Comparator Output Select
26357  *  0b0..COUT
26358  *  0b1..COUTA
26359  */
26360 #define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
26361 
26362 #define CMP_C0_INVT_MASK                         (0x800U)
26363 #define CMP_C0_INVT_SHIFT                        (11U)
26364 /*! INVT - Comparator Invert
26365  *  0b0..Do not invert
26366  *  0b1..Invert
26367  */
26368 #define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
26369 
26370 #define CMP_C0_PMODE_MASK                        (0x1000U)
26371 #define CMP_C0_PMODE_SHIFT                       (12U)
26372 /*! PMODE - Power Mode Select
26373  *  0b0..Low-speed (LS)
26374  *  0b1..High-speed (HS)
26375  */
26376 #define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
26377 
26378 #define CMP_C0_WE_MASK                           (0x4000U)
26379 #define CMP_C0_WE_SHIFT                          (14U)
26380 /*! WE - Windowing Enable
26381  *  0b0..Disable
26382  *  0b1..Enable
26383  */
26384 #define CMP_C0_WE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
26385 
26386 #define CMP_C0_SE_MASK                           (0x8000U)
26387 #define CMP_C0_SE_SHIFT                          (15U)
26388 /*! SE - Sample Enable
26389  *  0b0..Disable
26390  *  0b1..Enable
26391  */
26392 #define CMP_C0_SE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
26393 
26394 #define CMP_C0_FPR_MASK                          (0xFF0000U)
26395 #define CMP_C0_FPR_SHIFT                         (16U)
26396 /*! FPR - Filter Sample Period */
26397 #define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
26398 
26399 #define CMP_C0_COUT_MASK                         (0x1000000U)
26400 #define CMP_C0_COUT_SHIFT                        (24U)
26401 /*! COUT - Analog Comparator Output */
26402 #define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
26403 
26404 #define CMP_C0_CFF_MASK                          (0x2000000U)
26405 #define CMP_C0_CFF_SHIFT                         (25U)
26406 /*! CFF - Analog Comparator Flag Falling
26407  *  0b0..Not detected
26408  *  0b1..Detected
26409  *  0b0..No effect
26410  *  0b1..Clear the flag
26411  */
26412 #define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
26413 
26414 #define CMP_C0_CFR_MASK                          (0x4000000U)
26415 #define CMP_C0_CFR_SHIFT                         (26U)
26416 /*! CFR - Analog Comparator Flag Rising
26417  *  0b0..Not detected
26418  *  0b1..Detected
26419  *  0b0..No effect
26420  *  0b1..Clear the flag
26421  */
26422 #define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
26423 
26424 #define CMP_C0_IEF_MASK                          (0x8000000U)
26425 #define CMP_C0_IEF_SHIFT                         (27U)
26426 /*! IEF - Comparator Interrupt Enable Falling
26427  *  0b0..Disable
26428  *  0b1..Enable
26429  */
26430 #define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
26431 
26432 #define CMP_C0_IER_MASK                          (0x10000000U)
26433 #define CMP_C0_IER_SHIFT                         (28U)
26434 /*! IER - Comparator Interrupt Enable Rising
26435  *  0b0..Disable
26436  *  0b1..Enable
26437  */
26438 #define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
26439 
26440 #define CMP_C0_DMAEN_MASK                        (0x40000000U)
26441 #define CMP_C0_DMAEN_SHIFT                       (30U)
26442 /*! DMAEN - DMA Enable
26443  *  0b0..Disable
26444  *  0b1..Enable
26445  */
26446 #define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
26447 
26448 #define CMP_C0_LINKEN_MASK                       (0x80000000U)
26449 #define CMP_C0_LINKEN_SHIFT                      (31U)
26450 /*! LINKEN - CMP to DAC Link Enable
26451  *  0b0..Disable
26452  *  0b1..Enable
26453  */
26454 #define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
26455 /*! @} */
26456 
26457 /*! @name C1 - CMP Control 1 */
26458 /*! @{ */
26459 
26460 #define CMP_C1_VOSEL_MASK                        (0xFFU)
26461 #define CMP_C1_VOSEL_SHIFT                       (0U)
26462 /*! VOSEL - DAC Output Voltage Select */
26463 #define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
26464 
26465 #define CMP_C1_DMODE_MASK                        (0x100U)
26466 #define CMP_C1_DMODE_SHIFT                       (8U)
26467 /*! DMODE - DAC Mode Select
26468  *  0b0..Low-Speed and Low-Power mode
26469  *  0b1..High-Speed and High-Power mode
26470  */
26471 #define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
26472 
26473 #define CMP_C1_VRSEL_MASK                        (0x200U)
26474 #define CMP_C1_VRSEL_SHIFT                       (9U)
26475 /*! VRSEL - Supply Voltage Reference Source Select
26476  *  0b0..Vin1
26477  *  0b1..Vin2
26478  */
26479 #define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
26480 
26481 #define CMP_C1_DACEN_MASK                        (0x400U)
26482 #define CMP_C1_DACEN_SHIFT                       (10U)
26483 /*! DACEN - DAC Enable
26484  *  0b0..Disable
26485  *  0b1..Enable
26486  */
26487 #define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
26488 
26489 #define CMP_C1_CHN0_MASK                         (0x10000U)
26490 #define CMP_C1_CHN0_SHIFT                        (16U)
26491 /*! CHN0 - Channel 0 Input Enable
26492  *  0b0..Disable
26493  *  0b1..Enable
26494  */
26495 #define CMP_C1_CHN0(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
26496 
26497 #define CMP_C1_CHN1_MASK                         (0x20000U)
26498 #define CMP_C1_CHN1_SHIFT                        (17U)
26499 /*! CHN1 - Channel 1 Input Enable
26500  *  0b0..Disable
26501  *  0b1..Enable
26502  */
26503 #define CMP_C1_CHN1(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
26504 
26505 #define CMP_C1_CHN2_MASK                         (0x40000U)
26506 #define CMP_C1_CHN2_SHIFT                        (18U)
26507 /*! CHN2 - Channel 2 Input Enable
26508  *  0b0..Disable
26509  *  0b1..Enable
26510  */
26511 #define CMP_C1_CHN2(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
26512 
26513 #define CMP_C1_CHN3_MASK                         (0x80000U)
26514 #define CMP_C1_CHN3_SHIFT                        (19U)
26515 /*! CHN3 - Channel 3 Input Enable
26516  *  0b0..Disable
26517  *  0b1..Enable
26518  */
26519 #define CMP_C1_CHN3(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
26520 
26521 #define CMP_C1_CHN4_MASK                         (0x100000U)
26522 #define CMP_C1_CHN4_SHIFT                        (20U)
26523 /*! CHN4 - Channel 4 Input Enable
26524  *  0b0..Disable
26525  *  0b1..Enable
26526  */
26527 #define CMP_C1_CHN4(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
26528 
26529 #define CMP_C1_CHN5_MASK                         (0x200000U)
26530 #define CMP_C1_CHN5_SHIFT                        (21U)
26531 /*! CHN5 - Channel 5 Input Enable
26532  *  0b0..Disable
26533  *  0b1..Enable
26534  */
26535 #define CMP_C1_CHN5(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
26536 
26537 #define CMP_C1_MSEL_MASK                         (0x7000000U)
26538 #define CMP_C1_MSEL_SHIFT                        (24U)
26539 /*! MSEL - Minus Input MUX Control
26540  *  0b000..Internal negative input 0 for minus channel (internal minus input)
26541  *  0b001..External input 1 for minus channel (reference input 0)
26542  *  0b010..External input 2 for minus channel (reference input 1)
26543  *  0b011..External input 3 for minus channel (reference input 2)
26544  *  0b100..External input 4 for minus channel (reference input 3)
26545  *  0b101..Reserved
26546  *  0b110..Reserved
26547  *  0b111..Internal 8-bit DAC output
26548  */
26549 #define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
26550 
26551 #define CMP_C1_PSEL_MASK                         (0x70000000U)
26552 #define CMP_C1_PSEL_SHIFT                        (28U)
26553 /*! PSEL - Plus Input MUX Control
26554  *  0b000..Internal positive input 0 for plus channel (internal plus input)
26555  *  0b001..External input 1 for plus Channel (reference input 0)
26556  *  0b010..External input 2 for plus channel (reference input 1)
26557  *  0b011..External input 3 for plus channel (reference input 2)
26558  *  0b100..External input 4 for plus channel (reference input 3)
26559  *  0b101..Reserved
26560  *  0b110..Reserved
26561  *  0b111..Internal 8-bit DAC output
26562  */
26563 #define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
26564 /*! @} */
26565 
26566 /*! @name C2 - CMP Control 2 */
26567 /*! @{ */
26568 
26569 #define CMP_C2_ACOn_MASK                         (0x3FU)
26570 #define CMP_C2_ACOn_SHIFT                        (0U)
26571 /*! ACOn - ACOn */
26572 #define CMP_C2_ACOn(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
26573 
26574 #define CMP_C2_INITMOD_MASK                      (0x3F00U)
26575 #define CMP_C2_INITMOD_SHIFT                     (8U)
26576 /*! INITMOD - Comparator and DAC Initialization Delay Modulus */
26577 #define CMP_C2_INITMOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
26578 
26579 #define CMP_C2_NSAM_MASK                         (0xC000U)
26580 #define CMP_C2_NSAM_SHIFT                        (14U)
26581 /*! NSAM - Number of Sample Clocks
26582  *  0b00..As soon as the active channel is scanned in one round-robin clock
26583  *  0b01..After one round-robin clock cycle
26584  *  0b10..After two round-robin clock cycles
26585  *  0b11..After three round-robin clock cycles
26586  */
26587 #define CMP_C2_NSAM(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
26588 
26589 #define CMP_C2_CH0F_MASK                         (0x10000U)
26590 #define CMP_C2_CH0F_SHIFT                        (16U)
26591 /*! CH0F - External Channel 0 Input Changed Flag */
26592 #define CMP_C2_CH0F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
26593 
26594 #define CMP_C2_CH1F_MASK                         (0x20000U)
26595 #define CMP_C2_CH1F_SHIFT                        (17U)
26596 /*! CH1F - External Channel 1 Input Changed Flag */
26597 #define CMP_C2_CH1F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
26598 
26599 #define CMP_C2_CH2F_MASK                         (0x40000U)
26600 #define CMP_C2_CH2F_SHIFT                        (18U)
26601 /*! CH2F - External Channel 2 Input Changed Flag */
26602 #define CMP_C2_CH2F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
26603 
26604 #define CMP_C2_CH3F_MASK                         (0x80000U)
26605 #define CMP_C2_CH3F_SHIFT                        (19U)
26606 /*! CH3F - External Channel 3 Input Changed Flag */
26607 #define CMP_C2_CH3F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
26608 
26609 #define CMP_C2_CH4F_MASK                         (0x100000U)
26610 #define CMP_C2_CH4F_SHIFT                        (20U)
26611 /*! CH4F - External Channel 4 Input Changed Flag */
26612 #define CMP_C2_CH4F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
26613 
26614 #define CMP_C2_CH5F_MASK                         (0x200000U)
26615 #define CMP_C2_CH5F_SHIFT                        (21U)
26616 /*! CH5F - External Channel 5 Input Changed Flag */
26617 #define CMP_C2_CH5F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
26618 
26619 #define CMP_C2_FXMXCH_MASK                       (0xE000000U)
26620 #define CMP_C2_FXMXCH_SHIFT                      (25U)
26621 /*! FXMXCH - Fixed Channel Select
26622  *  0b000..External reference input 0
26623  *  0b001..External reference input 1
26624  *  0b010..External reference input 2
26625  *  0b011..External reference input 3
26626  *  0b100..External reference input 4
26627  *  0b101..External reference input 5
26628  *  0b110..Reserved
26629  *  0b111..8-bit DAC
26630  */
26631 #define CMP_C2_FXMXCH(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
26632 
26633 #define CMP_C2_FXMP_MASK                         (0x20000000U)
26634 #define CMP_C2_FXMP_SHIFT                        (29U)
26635 /*! FXMP - Fixed MUX Port
26636  *  0b0..Fix plus port
26637  *  0b1..Fix minus port
26638  */
26639 #define CMP_C2_FXMP(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
26640 
26641 #define CMP_C2_RRIE_MASK                         (0x40000000U)
26642 #define CMP_C2_RRIE_SHIFT                        (30U)
26643 /*! RRIE - Round-Robin Interrupt Enable
26644  *  0b0..Disable
26645  *  0b1..Enable
26646  */
26647 #define CMP_C2_RRIE(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
26648 /*! @} */
26649 
26650 /*! @name C3 - CMP Control 3 */
26651 /*! @{ */
26652 
26653 #define CMP_C3_ACPH2TC_MASK                      (0x70U)
26654 #define CMP_C3_ACPH2TC_SHIFT                     (4U)
26655 /*! ACPH2TC - Analog Comparator Phase 2 Timing Control
26656  *  0b000..Phase 2 active time in one sampling period equals to T
26657  *  0b001..Phase 2 active time in one sampling period equals to 2 * T
26658  *  0b010..Phase 2 active time in one sampling period equals to 4 * T
26659  *  0b011..Phase 2 active time in one sampling period equals to 8 * T
26660  *  0b100..Phase 2 active time in one sampling period equals to 16 * T
26661  *  0b101..Phase 2 active time in one sampling period equals to 32 * T
26662  *  0b110..Phase 2 active time in one sampling period equals to 64 * T
26663  *  0b111..Phase 2 active time in one sampling period equals to 16 * T
26664  */
26665 #define CMP_C3_ACPH2TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
26666 
26667 #define CMP_C3_ACPH1TC_MASK                      (0x700U)
26668 #define CMP_C3_ACPH1TC_SHIFT                     (8U)
26669 /*! ACPH1TC - Analog Comparator Phase 1 Timing Control
26670  *  0b000..Phase 1 active time in one sampling period equals to T
26671  *  0b001..Phase 1 active time in one sampling period equals to 2 * T
26672  *  0b010..Phase 1 active time in one sampling period equals to 4 * T
26673  *  0b011..Phase 1 active time in one sampling period equals to 8 * T
26674  *  0b100..Phase 1 active time in one sampling period equals to T
26675  *  0b101..Phase 1 active time in one sampling period equals to T
26676  *  0b110..Phase 1 active time in one sampling period equals to T
26677  *  0b111..Phase 1 active time in one sampling period equals to 0
26678  */
26679 #define CMP_C3_ACPH1TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
26680 
26681 #define CMP_C3_ACSAT_MASK                        (0x7000U)
26682 #define CMP_C3_ACSAT_SHIFT                       (12U)
26683 /*! ACSAT - Analog Comparator Sampling Time Control
26684  *  0b000..The sampling time equals to T
26685  *  0b001..The sampling time equals to 2 * T
26686  *  0b010..The sampling time equals to 4 * T
26687  *  0b011..The sampling time equals to 8 * T
26688  *  0b100..The sampling time equals to 16 * T
26689  *  0b101..The sampling time equals to 32 * T
26690  *  0b110..The sampling time equals to 64 * T
26691  *  0b111..The sampling time equals to 256 * T
26692  */
26693 #define CMP_C3_ACSAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
26694 
26695 #define CMP_C3_DMCS_MASK                         (0x10000U)
26696 #define CMP_C3_DMCS_SHIFT                        (16U)
26697 /*! DMCS - Discrete Mode Clock Select
26698  *  0b0..Slow clock is selected for the timing generation.
26699  *  0b1..Fast clock is selected for the timing generation.
26700  */
26701 #define CMP_C3_DMCS(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
26702 
26703 #define CMP_C3_RDIVE_MASK                        (0x100000U)
26704 #define CMP_C3_RDIVE_SHIFT                       (20U)
26705 /*! RDIVE - Resistor Divider Enable
26706  *  0b0..Disable even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 to 1.8v.
26707  *  0b1..Enable because the inputs are above 1.8v.
26708  */
26709 #define CMP_C3_RDIVE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
26710 
26711 #define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
26712 #define CMP_C3_NCHCTEN_SHIFT                     (24U)
26713 /*! NCHCTEN - Negative Channel Continuous Mode Enable
26714  *  0b0..in Discrete Mode and special timing needs to be configured.
26715  *  0b1..in Continuous Mode and no special timing is required.
26716  */
26717 #define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
26718 
26719 #define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
26720 #define CMP_C3_PCHCTEN_SHIFT                     (28U)
26721 /*! PCHCTEN - Positive Channel Continuous Mode Enable
26722  *  0b0..in Discrete Mode and special timing needs to be configured
26723  *  0b1..in Continuous Mode and no special timing is required
26724  */
26725 #define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
26726 /*! @} */
26727 
26728 
26729 /*!
26730  * @}
26731  */ /* end of group CMP_Register_Masks */
26732 
26733 
26734 /* CMP - Peripheral instance base addresses */
26735 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
26736   /** Peripheral CMP1 base address */
26737   #define CMP1_BASE                                (0x52DC0000u)
26738   /** Peripheral CMP1 base address */
26739   #define CMP1_BASE_NS                             (0x42DC0000u)
26740   /** Peripheral CMP1 base pointer */
26741   #define CMP1                                     ((CMP_Type *)CMP1_BASE)
26742   /** Peripheral CMP1 base pointer */
26743   #define CMP1_NS                                  ((CMP_Type *)CMP1_BASE_NS)
26744   /** Peripheral CMP2 base address */
26745   #define CMP2_BASE                                (0x52DD0000u)
26746   /** Peripheral CMP2 base address */
26747   #define CMP2_BASE_NS                             (0x42DD0000u)
26748   /** Peripheral CMP2 base pointer */
26749   #define CMP2                                     ((CMP_Type *)CMP2_BASE)
26750   /** Peripheral CMP2 base pointer */
26751   #define CMP2_NS                                  ((CMP_Type *)CMP2_BASE_NS)
26752   /** Peripheral CMP3 base address */
26753   #define CMP3_BASE                                (0x52DE0000u)
26754   /** Peripheral CMP3 base address */
26755   #define CMP3_BASE_NS                             (0x42DE0000u)
26756   /** Peripheral CMP3 base pointer */
26757   #define CMP3                                     ((CMP_Type *)CMP3_BASE)
26758   /** Peripheral CMP3 base pointer */
26759   #define CMP3_NS                                  ((CMP_Type *)CMP3_BASE_NS)
26760   /** Peripheral CMP4 base address */
26761   #define CMP4_BASE                                (0x52DF0000u)
26762   /** Peripheral CMP4 base address */
26763   #define CMP4_BASE_NS                             (0x42DF0000u)
26764   /** Peripheral CMP4 base pointer */
26765   #define CMP4                                     ((CMP_Type *)CMP4_BASE)
26766   /** Peripheral CMP4 base pointer */
26767   #define CMP4_NS                                  ((CMP_Type *)CMP4_BASE_NS)
26768   /** Array initializer of CMP peripheral base addresses */
26769   #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
26770   /** Array initializer of CMP peripheral base pointers */
26771   #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
26772   /** Array initializer of CMP peripheral base addresses */
26773   #define CMP_BASE_ADDRS_NS                        { 0u, CMP1_BASE_NS, CMP2_BASE_NS, CMP3_BASE_NS, CMP4_BASE_NS }
26774   /** Array initializer of CMP peripheral base pointers */
26775   #define CMP_BASE_PTRS_NS                         { (CMP_Type *)0u, CMP1_NS, CMP2_NS, CMP3_NS, CMP4_NS }
26776 #else
26777   /** Peripheral CMP1 base address */
26778   #define CMP1_BASE                                (0x42DC0000u)
26779   /** Peripheral CMP1 base pointer */
26780   #define CMP1                                     ((CMP_Type *)CMP1_BASE)
26781   /** Peripheral CMP2 base address */
26782   #define CMP2_BASE                                (0x42DD0000u)
26783   /** Peripheral CMP2 base pointer */
26784   #define CMP2                                     ((CMP_Type *)CMP2_BASE)
26785   /** Peripheral CMP3 base address */
26786   #define CMP3_BASE                                (0x42DE0000u)
26787   /** Peripheral CMP3 base pointer */
26788   #define CMP3                                     ((CMP_Type *)CMP3_BASE)
26789   /** Peripheral CMP4 base address */
26790   #define CMP4_BASE                                (0x42DF0000u)
26791   /** Peripheral CMP4 base pointer */
26792   #define CMP4                                     ((CMP_Type *)CMP4_BASE)
26793   /** Array initializer of CMP peripheral base addresses */
26794   #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
26795   /** Array initializer of CMP peripheral base pointers */
26796   #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
26797 #endif
26798 /** Interrupt vectors for the CMP peripheral type */
26799 #define CMP_IRQS                                 { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
26800 
26801 /*!
26802  * @}
26803  */ /* end of group CMP_Peripheral_Access_Layer */
26804 
26805 
26806 /* ----------------------------------------------------------------------------
26807    -- DAC Peripheral Access Layer
26808    ---------------------------------------------------------------------------- */
26809 
26810 /*!
26811  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
26812  * @{
26813  */
26814 
26815 /** DAC - Register Layout Typedef */
26816 typedef struct {
26817   __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
26818   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
26819   __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
26820   __IO uint32_t CR;                                /**< DAC Status and Control Register, offset: 0xC */
26821   __I  uint32_t PTR;                               /**< DAC FIFO Pointer Register, offset: 0x10 */
26822   __IO uint32_t CR2;                               /**< DAC Status and Control Register 2, offset: 0x14 */
26823 } DAC_Type;
26824 
26825 /* ----------------------------------------------------------------------------
26826    -- DAC Register Masks
26827    ---------------------------------------------------------------------------- */
26828 
26829 /*!
26830  * @addtogroup DAC_Register_Masks DAC Register Masks
26831  * @{
26832  */
26833 
26834 /*! @name VERID - Version Identifier Register */
26835 /*! @{ */
26836 
26837 #define DAC_VERID_FEATURE_MASK                   (0xFFFFU)
26838 #define DAC_VERID_FEATURE_SHIFT                  (0U)
26839 /*! FEATURE - Feature Identification Number
26840  *  0b0000000000000000..Standard feature set
26841  *  0b0000000000000001..C40 feature set
26842  *  0b0000000000000010..5V DAC feature set
26843  *  0b0000000000000100..ADC BIST feature set
26844  */
26845 #define DAC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
26846 
26847 #define DAC_VERID_MINOR_MASK                     (0xFF0000U)
26848 #define DAC_VERID_MINOR_SHIFT                    (16U)
26849 /*! MINOR - Minor version number */
26850 #define DAC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
26851 
26852 #define DAC_VERID_MAJOR_MASK                     (0xFF000000U)
26853 #define DAC_VERID_MAJOR_SHIFT                    (24U)
26854 /*! MAJOR - Major version number */
26855 #define DAC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
26856 /*! @} */
26857 
26858 /*! @name PARAM - Parameter Register */
26859 /*! @{ */
26860 
26861 #define DAC_PARAM_FIFOSZ_MASK                    (0x7U)
26862 #define DAC_PARAM_FIFOSZ_SHIFT                   (0U)
26863 /*! FIFOSZ - FIFO size
26864  *  0b000..FIFO depth is 2
26865  *  0b001..FIFO depth is 4
26866  *  0b010..FIFO depth is 8
26867  *  0b011..FIFO depth is 16
26868  *  0b100..FIFO depth is 32
26869  *  0b101..FIFO depth is 64
26870  *  0b110..FIFO depth is 128
26871  *  0b111..FIFO depth is 256
26872  */
26873 #define DAC_PARAM_FIFOSZ(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
26874 /*! @} */
26875 
26876 /*! @name DATA - DAC Data Register */
26877 /*! @{ */
26878 
26879 #define DAC_DATA_DATA0_MASK                      (0xFFFU)
26880 #define DAC_DATA_DATA0_SHIFT                     (0U)
26881 /*! DATA0 - FIFO DATA0 */
26882 #define DAC_DATA_DATA0(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
26883 /*! @} */
26884 
26885 /*! @name CR - DAC Status and Control Register */
26886 /*! @{ */
26887 
26888 #define DAC_CR_FULLF_MASK                        (0x1U)
26889 #define DAC_CR_FULLF_SHIFT                       (0U)
26890 /*! FULLF - Full Flag
26891  *  0b0..FIFO is not full.
26892  *  0b1..FIFO is full.
26893  */
26894 #define DAC_CR_FULLF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
26895 
26896 #define DAC_CR_NEMPTF_MASK                       (0x2U)
26897 #define DAC_CR_NEMPTF_SHIFT                      (1U)
26898 /*! NEMPTF - Nearly Empty Flag
26899  *  0b0..More than one data is available in the FIFO.
26900  *  0b1..One data is available in the FIFO.
26901  */
26902 #define DAC_CR_NEMPTF(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
26903 
26904 #define DAC_CR_WMF_MASK                          (0x4U)
26905 #define DAC_CR_WMF_SHIFT                         (2U)
26906 /*! WMF - FIFO Watermark Status Flag
26907  *  0b0..The DAC buffer read pointer has not reached the watermark level.
26908  *  0b1..The DAC buffer read pointer has reached the watermark level.
26909  */
26910 #define DAC_CR_WMF(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
26911 
26912 #define DAC_CR_UDFF_MASK                         (0x8U)
26913 #define DAC_CR_UDFF_SHIFT                        (3U)
26914 /*! UDFF - Underflow Flag
26915  *  0b0..No underflow has occurred since the last time the flag was cleared.
26916  *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
26917  */
26918 #define DAC_CR_UDFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
26919 
26920 #define DAC_CR_OVFF_MASK                         (0x10U)
26921 #define DAC_CR_OVFF_SHIFT                        (4U)
26922 /*! OVFF - Overflow Flag
26923  *  0b0..No overflow has occurred since the last time the flag was cleared.
26924  *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
26925  */
26926 #define DAC_CR_OVFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
26927 
26928 #define DAC_CR_FULLIE_MASK                       (0x100U)
26929 #define DAC_CR_FULLIE_SHIFT                      (8U)
26930 /*! FULLIE - Full Interrupt Enable
26931  *  0b0..FIFO Full interrupt is disabled.
26932  *  0b1..FIFO Full interrupt is enabled.
26933  */
26934 #define DAC_CR_FULLIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
26935 
26936 #define DAC_CR_EMPTIE_MASK                       (0x200U)
26937 #define DAC_CR_EMPTIE_SHIFT                      (9U)
26938 /*! EMPTIE - Nearly Empty Interrupt Enable
26939  *  0b0..FIFO Nearly Empty interrupt is disabled.
26940  *  0b1..FIFO Nearly Empty interrupt is enabled.
26941  */
26942 #define DAC_CR_EMPTIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
26943 
26944 #define DAC_CR_WTMIE_MASK                        (0x400U)
26945 #define DAC_CR_WTMIE_SHIFT                       (10U)
26946 /*! WTMIE - Watermark Interrupt Enable
26947  *  0b0..Watermark interrupt is disabled.
26948  *  0b1..Watermark interrupt is enabled.
26949  */
26950 #define DAC_CR_WTMIE(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
26951 
26952 #define DAC_CR_SWTRG_MASK                        (0x1000U)
26953 #define DAC_CR_SWTRG_SHIFT                       (12U)
26954 /*! SWTRG - DAC Software Trigger
26955  *  0b0..The DAC soft trigger is not valid.
26956  *  0b1..The DAC soft trigger is valid.
26957  */
26958 #define DAC_CR_SWTRG(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
26959 
26960 #define DAC_CR_TRGSEL_MASK                       (0x2000U)
26961 #define DAC_CR_TRGSEL_SHIFT                      (13U)
26962 /*! TRGSEL - DAC Trigger Select
26963  *  0b0..The DAC hardware trigger is selected.
26964  *  0b1..The DAC software trigger is selected.
26965  */
26966 #define DAC_CR_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
26967 
26968 #define DAC_CR_DACRFS_MASK                       (0x4000U)
26969 #define DAC_CR_DACRFS_SHIFT                      (14U)
26970 /*! DACRFS - DAC Reference Select
26971  *  0b0..The DAC selects DACREF_1 as the reference voltage.
26972  *  0b1..The DAC selects DACREF_2 as the reference voltage.
26973  */
26974 #define DAC_CR_DACRFS(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
26975 
26976 #define DAC_CR_DACEN_MASK                        (0x8000U)
26977 #define DAC_CR_DACEN_SHIFT                       (15U)
26978 /*! DACEN - DAC Enable
26979  *  0b0..The DAC system is disabled.
26980  *  0b1..The DAC system is enabled.
26981  */
26982 #define DAC_CR_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
26983 
26984 #define DAC_CR_FIFOEN_MASK                       (0x10000U)
26985 #define DAC_CR_FIFOEN_SHIFT                      (16U)
26986 /*! FIFOEN - FIFO Enable
26987  *  0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
26988  *  0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
26989  */
26990 #define DAC_CR_FIFOEN(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
26991 
26992 #define DAC_CR_SWMD_MASK                         (0x20000U)
26993 #define DAC_CR_SWMD_SHIFT                        (17U)
26994 /*! SWMD - DAC FIFO Mode Select
26995  *  0b0..Normal mode
26996  *  0b1..Swing back mode
26997  */
26998 #define DAC_CR_SWMD(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
26999 
27000 #define DAC_CR_UVIE_MASK                         (0x40000U)
27001 #define DAC_CR_UVIE_SHIFT                        (18U)
27002 /*! UVIE - Underflow and overflow interrupt enable
27003  *  0b0..Underflow and overflow interrupt is disabled.
27004  *  0b1..Underflow and overflow interrupt is enabled.
27005  */
27006 #define DAC_CR_UVIE(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
27007 
27008 #define DAC_CR_FIFORST_MASK                      (0x200000U)
27009 #define DAC_CR_FIFORST_SHIFT                     (21U)
27010 /*! FIFORST - FIFO Reset
27011  *  0b0..No effect
27012  *  0b1..FIFO reset
27013  */
27014 #define DAC_CR_FIFORST(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
27015 
27016 #define DAC_CR_SWRST_MASK                        (0x400000U)
27017 #define DAC_CR_SWRST_SHIFT                       (22U)
27018 /*! SWRST - Software reset */
27019 #define DAC_CR_SWRST(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
27020 
27021 #define DAC_CR_DMAEN_MASK                        (0x800000U)
27022 #define DAC_CR_DMAEN_SHIFT                       (23U)
27023 /*! DMAEN - DMA Enable Select
27024  *  0b0..DMA is disabled.
27025  *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
27026  *       interrupts will not be presented on this module at the same time.
27027  */
27028 #define DAC_CR_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
27029 
27030 #define DAC_CR_WML_MASK                          (0xFF000000U)
27031 #define DAC_CR_WML_SHIFT                         (24U)
27032 /*! WML - Watermark Level Select */
27033 #define DAC_CR_WML(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
27034 /*! @} */
27035 
27036 /*! @name PTR - DAC FIFO Pointer Register */
27037 /*! @{ */
27038 
27039 #define DAC_PTR_DACWFP_MASK                      (0xFFU)
27040 #define DAC_PTR_DACWFP_SHIFT                     (0U)
27041 /*! DACWFP - DACWFP */
27042 #define DAC_PTR_DACWFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
27043 
27044 #define DAC_PTR_DACRFP_MASK                      (0xFF0000U)
27045 #define DAC_PTR_DACRFP_SHIFT                     (16U)
27046 /*! DACRFP - DACRFP */
27047 #define DAC_PTR_DACRFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
27048 /*! @} */
27049 
27050 /*! @name CR2 - DAC Status and Control Register 2 */
27051 /*! @{ */
27052 
27053 #define DAC_CR2_BFEN_MASK                        (0x1U)
27054 #define DAC_CR2_BFEN_SHIFT                       (0U)
27055 /*! BFEN - Buffer Enable
27056  *  0b0..Opamp is not used as buffer
27057  *  0b1..Opamp is used as buffer
27058  */
27059 #define DAC_CR2_BFEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
27060 
27061 #define DAC_CR2_OEN_MASK                         (0x2U)
27062 #define DAC_CR2_OEN_SHIFT                        (1U)
27063 /*! OEN - Optional Enable
27064  *  0b0..Output buffer is not bypassed
27065  *  0b1..Output buffer is bypassed
27066  */
27067 #define DAC_CR2_OEN(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
27068 
27069 #define DAC_CR2_BFMS_MASK                        (0x4U)
27070 #define DAC_CR2_BFMS_SHIFT                       (2U)
27071 /*! BFMS - Buffer Middle Speed Select
27072  *  0b0..Buffer middle speed not selected
27073  *  0b1..Buffer middle speed selected
27074  */
27075 #define DAC_CR2_BFMS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
27076 
27077 #define DAC_CR2_BFHS_MASK                        (0x8U)
27078 #define DAC_CR2_BFHS_SHIFT                       (3U)
27079 /*! BFHS - Buffer High Speed Select
27080  *  0b0..Buffer high speed not selected
27081  *  0b1..Buffer high speed selected
27082  */
27083 #define DAC_CR2_BFHS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
27084 
27085 #define DAC_CR2_IREF2_MASK                       (0x10U)
27086 #define DAC_CR2_IREF2_SHIFT                      (4U)
27087 /*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
27088  *  0b0..Internal PTAT Current Reference not selected
27089  *  0b1..Internal PTAT Current Reference selected
27090  */
27091 #define DAC_CR2_IREF2(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
27092 
27093 #define DAC_CR2_IREF1_MASK                       (0x20U)
27094 #define DAC_CR2_IREF1_SHIFT                      (5U)
27095 /*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
27096  *  0b0..Internal ZTC Current Reference not selected
27097  *  0b1..Internal ZTC Current Reference selected
27098  */
27099 #define DAC_CR2_IREF1(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
27100 
27101 #define DAC_CR2_IREF_MASK                        (0x40U)
27102 #define DAC_CR2_IREF_SHIFT                       (6U)
27103 /*! IREF - Internal Current Reference Select
27104  *  0b0..Internal Current Reference not selected
27105  *  0b1..Internal Current Reference selected
27106  */
27107 #define DAC_CR2_IREF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
27108 /*! @} */
27109 
27110 
27111 /*!
27112  * @}
27113  */ /* end of group DAC_Register_Masks */
27114 
27115 
27116 /* DAC - Peripheral instance base addresses */
27117 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
27118   /** Peripheral DAC base address */
27119   #define DAC_BASE                                 (0x52E20000u)
27120   /** Peripheral DAC base address */
27121   #define DAC_BASE_NS                              (0x42E20000u)
27122   /** Peripheral DAC base pointer */
27123   #define DAC                                      ((DAC_Type *)DAC_BASE)
27124   /** Peripheral DAC base pointer */
27125   #define DAC_NS                                   ((DAC_Type *)DAC_BASE_NS)
27126   /** Array initializer of DAC peripheral base addresses */
27127   #define DAC_BASE_ADDRS                           { DAC_BASE }
27128   /** Array initializer of DAC peripheral base pointers */
27129   #define DAC_BASE_PTRS                            { DAC }
27130   /** Array initializer of DAC peripheral base addresses */
27131   #define DAC_BASE_ADDRS_NS                        { DAC_BASE_NS }
27132   /** Array initializer of DAC peripheral base pointers */
27133   #define DAC_BASE_PTRS_NS                         { DAC_NS }
27134 #else
27135   /** Peripheral DAC base address */
27136   #define DAC_BASE                                 (0x42E20000u)
27137   /** Peripheral DAC base pointer */
27138   #define DAC                                      ((DAC_Type *)DAC_BASE)
27139   /** Array initializer of DAC peripheral base addresses */
27140   #define DAC_BASE_ADDRS                           { DAC_BASE }
27141   /** Array initializer of DAC peripheral base pointers */
27142   #define DAC_BASE_PTRS                            { DAC }
27143 #endif
27144 /** Interrupt vectors for the DAC peripheral type */
27145 #define DAC_IRQS                                 { DAC_IRQn }
27146 
27147 /*!
27148  * @}
27149  */ /* end of group DAC_Peripheral_Access_Layer */
27150 
27151 
27152 /* ----------------------------------------------------------------------------
27153    -- DCDC Peripheral Access Layer
27154    ---------------------------------------------------------------------------- */
27155 
27156 /*!
27157  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
27158  * @{
27159  */
27160 
27161 /** DCDC - Register Layout Typedef */
27162 typedef struct {
27163   __IO uint32_t REG0;                              /**< DCDC Register 0, offset: 0x0 */
27164   __IO uint32_t REG1;                              /**< DCDC Register 1, offset: 0x4 */
27165   __IO uint32_t REG2;                              /**< DCDC Register 2, offset: 0x8 */
27166   __IO uint32_t REG3;                              /**< DCDC Register 3, offset: 0xC */
27167   __IO uint32_t CTRL0;                             /**< DCDC Control Register 0, offset: 0x10 */
27168   __IO uint32_t OK_CNT;                            /**< OK CNT, offset: 0x14 */
27169   __IO uint32_t CURRENT_TRG;                       /**< CURRENT TARGET VALUE for DCDC ANALOG, offset: 0x18 */
27170   __IO uint32_t FILTER_CNT;                        /**< FILTER CNT, offset: 0x1C */
27171   __IO uint32_t TRG_0_AUTHEN;                      /**< TRG_0 Authentication Control, offset: 0x20 */
27172   __IO uint32_t TRG_SW_0;                          /**< Target SW Control for CORE 0, offset: 0x24 */
27173   __IO uint32_t TRG_GPC_0;                         /**< Target GPC Control for CORE 0, offset: 0x28 */
27174        uint8_t RESERVED_0[4];
27175   __IO uint32_t TRG_1_AUTHEN;                      /**< TRG_1 Authentication Control, offset: 0x30 */
27176   __IO uint32_t TRG_SW_1;                          /**< Target SW Control for CORE 1, offset: 0x34 */
27177   __IO uint32_t TRG_GPC_1;                         /**< Target GPC Control for CORE 1, offset: 0x38 */
27178 } DCDC_Type;
27179 
27180 /* ----------------------------------------------------------------------------
27181    -- DCDC Register Masks
27182    ---------------------------------------------------------------------------- */
27183 
27184 /*!
27185  * @addtogroup DCDC_Register_Masks DCDC Register Masks
27186  * @{
27187  */
27188 
27189 /*! @name REG0 - DCDC Register 0 */
27190 /*! @{ */
27191 
27192 #define DCDC_REG0_PWD_ZCD_MASK                   (0x1U)
27193 #define DCDC_REG0_PWD_ZCD_SHIFT                  (0U)
27194 /*! PWD_ZCD - Power Down Zero Cross Detection
27195  *  0b0..Zero cross detection function powered up
27196  *  0b1..Zero cross detection function powered down
27197  */
27198 #define DCDC_REG0_PWD_ZCD(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
27199 
27200 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
27201 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT  (1U)
27202 /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
27203  *  0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically
27204  *  0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
27205  */
27206 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
27207 
27208 #define DCDC_REG0_SEL_CLK_MASK                   (0x4U)
27209 #define DCDC_REG0_SEL_CLK_SHIFT                  (2U)
27210 /*! SEL_CLK - Select Clock
27211  *  0b0..DCDC uses internal ring oscillator
27212  *  0b1..DCDC uses 24M xtal
27213  */
27214 #define DCDC_REG0_SEL_CLK(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
27215 
27216 #define DCDC_REG0_PWD_OSC_INT_MASK               (0x8U)
27217 #define DCDC_REG0_PWD_OSC_INT_SHIFT              (3U)
27218 /*! PWD_OSC_INT - Power down internal osc
27219  *  0b0..Internal oscillator powered up
27220  *  0b1..Internal oscillator powered down
27221  */
27222 #define DCDC_REG0_PWD_OSC_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
27223 
27224 #define DCDC_REG0_PWD_OVERCUR_DET_MASK           (0x100U)
27225 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT          (8U)
27226 /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
27227  *  0b0..Overcurrent detection comparator is enabled
27228  *  0b1..Overcurrent detection comparator is disabled
27229  */
27230 #define DCDC_REG0_PWD_OVERCUR_DET(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
27231 
27232 #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK          (0x600U)
27233 #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT         (9U)
27234 /*! OVERCUR_TRIG_ADJ - Overcurrent Trigger Adjust
27235  *  0b00..In Run Mode, 1.5 A. In LP Mode, 150 mA
27236  *  0b01..In Run Mode, 1.5 A. In LP Mode, 130 mA
27237  *  0b10..In Run Mode, 2 A. In LP Mode, 150 mA
27238  *  0b11..In Run Mode, 2 A. In LP Mode, 130 mA
27239  */
27240 #define DCDC_REG0_OVERCUR_TRIG_ADJ(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
27241 
27242 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK       (0x800U)
27243 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT      (11U)
27244 /*! PWD_CMP_DCDC_IN_DET
27245  *  0b0..Low voltage detection comparator is enabled
27246  *  0b1..Low voltage detection comparator is disabled
27247  */
27248 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
27249 
27250 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK       (0x10000U)
27251 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT      (16U)
27252 /*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8
27253  *  0b0..Overvoltage detection comparator for the VDD1P8 output is enabled
27254  *  0b1..Overvoltage detection comparator for the VDD1P8 output is disabled
27255  */
27256 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
27257 
27258 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK       (0x20000U)
27259 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT      (17U)
27260 /*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0
27261  *  0b0..Overvoltage detection comparator for the VDD1P0 output is enabled
27262  *  0b1..Overvoltage detection comparator for the VDD1P0 output is disabled
27263  */
27264 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
27265 
27266 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
27267 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
27268 /*! PWD_CMP_OFFSET - power down the out-of-range detection comparator
27269  *  0b0..Out-of-range comparator powered up
27270  *  0b1..Out-of-range comparator powered down
27271  */
27272 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
27273 
27274 #define DCDC_REG0_XTALOK_DISABLE_MASK            (0x8000000U)
27275 #define DCDC_REG0_XTALOK_DISABLE_SHIFT           (27U)
27276 /*! XTALOK_DISABLE - Disable xtalok detection circuit
27277  *  0b0..Enable xtalok detection circuit
27278  *  0b1..Disable xtalok detection circuit and always outputs OK signal "1"
27279  */
27280 #define DCDC_REG0_XTALOK_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
27281 
27282 #define DCDC_REG0_XTAL_24M_OK_MASK               (0x20000000U)
27283 #define DCDC_REG0_XTAL_24M_OK_SHIFT              (29U)
27284 /*! XTAL_24M_OK - 24M XTAL OK
27285  *  0b0..DCDC uses internal ring OSC
27286  *  0b1..DCDC uses xtal 24M
27287  */
27288 #define DCDC_REG0_XTAL_24M_OK(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
27289 
27290 #define DCDC_REG0_STS_DC_OK_MASK                 (0x80000000U)
27291 #define DCDC_REG0_STS_DC_OK_SHIFT                (31U)
27292 /*! STS_DC_OK - DCDC Output OK
27293  *  0b0..DCDC is settling
27294  *  0b1..DCDC already settled
27295  */
27296 #define DCDC_REG0_STS_DC_OK(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
27297 /*! @} */
27298 
27299 /*! @name REG1 - DCDC Register 1 */
27300 /*! @{ */
27301 
27302 #define DCDC_REG1_RLOAD_REG_EN_MASK              (0x10U)
27303 #define DCDC_REG1_RLOAD_REG_EN_SHIFT             (4U)
27304 /*! RLOAD_REG_EN - Resistor Load of Regulator Enable
27305  *  0b0..Resistor load disconnected
27306  *  0b1..Resistor load connected
27307  */
27308 #define DCDC_REG1_RLOAD_REG_EN(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_MASK)
27309 
27310 #define DCDC_REG1_VBG_TRIM_MASK                  (0x7C0U)
27311 #define DCDC_REG1_VBG_TRIM_SHIFT                 (6U)
27312 #define DCDC_REG1_VBG_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
27313 
27314 #define DCDC_REG1_NEGLIMIT_IN_MASK               (0xFE000U)
27315 #define DCDC_REG1_NEGLIMIT_IN_SHIFT              (13U)
27316 #define DCDC_REG1_NEGLIMIT_IN(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_NEGLIMIT_IN_SHIFT)) & DCDC_REG1_NEGLIMIT_IN_MASK)
27317 
27318 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK    (0x8000000U)
27319 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
27320 /*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection
27321  *  0b0..Disable increase the threshold detection for common mode analog comparators.
27322  *  0b1..Enable increase the threshold detection for common mode analog comparators.
27323  */
27324 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
27325 
27326 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK    (0x10000000U)
27327 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
27328 /*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection
27329  *  0b0..Disable increase the threshold detection for differential mode analog comparators.
27330  *  0b1..Enable increase the threshold detection for differential mode analog comparators.
27331  */
27332 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
27333 
27334 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK       (0x20000000U)
27335 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT      (29U)
27336 /*! LOOPCTRL_EN_CM_HYST
27337  *  0b0..Disable hysteresis in switching converter common mode analog comparators
27338  *  0b1..Enable hysteresis in switching converter common mode analog comparators
27339  */
27340 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
27341 
27342 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK       (0x40000000U)
27343 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT      (30U)
27344 /*! LOOPCTRL_EN_DF_HYST
27345  *  0b0..Disable hysteresis in switching converter differential mode analog comparators
27346  *  0b1..Enable hysteresis in switching converter differential mode analog comparators
27347  */
27348 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
27349 /*! @} */
27350 
27351 /*! @name REG2 - DCDC Register 2 */
27352 /*! @{ */
27353 
27354 #define DCDC_REG2_LOOPCTRL_DC_C_MASK             (0x3U)
27355 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT            (0U)
27356 #define DCDC_REG2_LOOPCTRL_DC_C(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
27357 
27358 #define DCDC_REG2_LOOPCTRL_DC_R_MASK             (0x3CU)
27359 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT            (2U)
27360 #define DCDC_REG2_LOOPCTRL_DC_R(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
27361 
27362 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK            (0x1C0U)
27363 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT           (6U)
27364 #define DCDC_REG2_LOOPCTRL_DC_FF(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
27365 
27366 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK       (0xE00U)
27367 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT      (9U)
27368 /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale */
27369 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
27370 
27371 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK    (0x1000U)
27372 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
27373 /*! LOOPCTRL_RCSCALE_THRSH
27374  *  0b0..Disable increasing the threshold detection function.
27375  *  0b1..Enable increasing the threshold detection function.
27376  */
27377 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
27378 
27379 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK        (0x2000U)
27380 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT       (13U)
27381 /*! LOOPCTRL_HYST_SIGN
27382  *  0b0..Disable the invert function.
27383  *  0b1..Enable the invert function.
27384  */
27385 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
27386 
27387 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK     (0x8000U)
27388 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT    (15U)
27389 /*! BATTMONITOR_EN_BATADJ
27390  *  0b0..Disable the improvement function.
27391  *  0b1..Enable the improvement function.
27392  */
27393 #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
27394 
27395 #define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK      (0x3FF0000U)
27396 #define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT     (16U)
27397 #define DCDC_REG2_BATTMONITOR_BATT_VAL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
27398 
27399 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK       (0x40000000U)
27400 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT      (30U)
27401 /*! LOOPCTRL_TOGGLE_DIF
27402  *  0b0..Disable supply stepping to change.
27403  *  0b1..Enable supply stepping to change.
27404  */
27405 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
27406 /*! @} */
27407 
27408 /*! @name REG3 - DCDC Register 3 */
27409 /*! @{ */
27410 
27411 #define DCDC_REG3_IN_BROWNOUT_WARN_MASK          (0x200U)
27412 #define DCDC_REG3_IN_BROWNOUT_WARN_SHIFT         (9U)
27413 /*! IN_BROWNOUT_WARN
27414  *  0b0..The voltage on DCDC_IN raises up to 2.8V.
27415  *  0b1..The voltage on DCDC_IN is lower than 2.8V. Once this bit sets, the bit must be cleared by software write
27416  *       one clear action while the voltage on DCDC_IN raises up to 2.8V. Writing "0" to this bit has no effect.
27417  *       Writing "1" to this bit has no effect while it's "0".
27418  */
27419 #define DCDC_REG3_IN_BROWNOUT_WARN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_WARN_SHIFT)) & DCDC_REG3_IN_BROWNOUT_WARN_MASK)
27420 
27421 #define DCDC_REG3_ENABLE_FF_MASK                 (0x40000U)
27422 #define DCDC_REG3_ENABLE_FF_SHIFT                (18U)
27423 /*! ENABLE_FF
27424  *  0b0..Enable the FF function.
27425  *  0b1..Disable the FF function.
27426  */
27427 #define DCDC_REG3_ENABLE_FF(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
27428 
27429 #define DCDC_REG3_DISABLE_PULSE_SKIP_MASK        (0x80000U)
27430 #define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT       (19U)
27431 /*! DISABLE_PULSE_SKIP - Disable Pulse Skip */
27432 #define DCDC_REG3_DISABLE_PULSE_SKIP(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
27433 
27434 #define DCDC_REG3_DISABLE_IDLE_SKIP_MASK         (0x100000U)
27435 #define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT        (20U)
27436 /*! DISABLE_IDLE_SKIP
27437  *  0b0..Enable the idle skip function.
27438  *  0b1..Disable the idle skip function.
27439  */
27440 #define DCDC_REG3_DISABLE_IDLE_SKIP(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
27441 
27442 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_MASK       (0x200000U)
27443 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_SHIFT      (21U)
27444 /*! DOUBLE_IBIAS_CMP_LP
27445  *  0b0..Disable the function.
27446  *  0b1..Enable the function.
27447  */
27448 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_MASK)
27449 
27450 #define DCDC_REG3_REG_FBK_SEL_MASK               (0xC00000U)
27451 #define DCDC_REG3_REG_FBK_SEL_SHIFT              (22U)
27452 #define DCDC_REG3_REG_FBK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
27453 
27454 #define DCDC_REG3_MINPWR_HALF_FETS_MASK          (0x4000000U)
27455 #define DCDC_REG3_MINPWR_HALF_FETS_SHIFT         (26U)
27456 /*! MINPWR_HALF_FETS
27457  *  0b0..Donot use half switch FET.
27458  *  0b1..Use half switch FET.
27459  */
27460 #define DCDC_REG3_MINPWR_HALF_FETS(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
27461 
27462 #define DCDC_REG3_MISC_DELAY_TIMING_MASK         (0x8000000U)
27463 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT        (27U)
27464 /*! MISC_DELAY_TIMING - Miscellaneous Delay Timing
27465  *  0b0..Disable the function.
27466  *  0b1..Enable the function.
27467  */
27468 #define DCDC_REG3_MISC_DELAY_TIMING(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
27469 
27470 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
27471 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT  (29U)
27472 /*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0
27473  *  0b0..Enable stepping for VDD1P0
27474  *  0b1..Disable stepping for VDD1P0
27475  */
27476 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
27477 /*! @} */
27478 
27479 /*! @name CTRL0 - DCDC Control Register 0 */
27480 /*! @{ */
27481 
27482 #define DCDC_CTRL0_ENABLE_OK_CNT_MASK            (0x20U)
27483 #define DCDC_CTRL0_ENABLE_OK_CNT_SHIFT           (5U)
27484 /*! ENABLE_OK_CNT - Enable internal count for DCDC_OK timeout
27485  *  0b0..Wait DCDC_OK for ACK
27486  *  0b1..Enable internal count for DCDC_OK timeout
27487  */
27488 #define DCDC_CTRL0_ENABLE_OK_CNT(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_OK_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_OK_CNT_MASK)
27489 
27490 #define DCDC_CTRL0_TRIM_HOLD_MASK                (0x40U)
27491 #define DCDC_CTRL0_TRIM_HOLD_SHIFT               (6U)
27492 /*! TRIM_HOLD - Hold trim input
27493  *  0b0..Sample trim value from FUSE or value from REG1[VBG_TRIM] depending on FUSE select bit.
27494  *  0b1..Use value from REG1[VBG_TRIM] as trim value.
27495  */
27496 #define DCDC_CTRL0_TRIM_HOLD(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
27497 
27498 #define DCDC_CTRL0_IN_BROWNOUT_WARN_EN_MASK      (0x200U)
27499 #define DCDC_CTRL0_IN_BROWNOUT_WARN_EN_SHIFT     (9U)
27500 /*! IN_BROWNOUT_WARN_EN - IN_BROWNOUT_WARN_EN
27501  *  0b0..Disable IN_BROWNOUT_WARN int flag bit output to CORE as an interrupt resource.
27502  *  0b1..Enable IN_BROWNOUT_WARN int flag bit output to CORE as an interrupt resource.
27503  */
27504 #define DCDC_CTRL0_IN_BROWNOUT_WARN_EN(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_IN_BROWNOUT_WARN_EN_SHIFT)) & DCDC_CTRL0_IN_BROWNOUT_WARN_EN_MASK)
27505 
27506 #define DCDC_CTRL0_DEBUG_BITS_MASK               (0x7FF80000U)
27507 #define DCDC_CTRL0_DEBUG_BITS_SHIFT              (19U)
27508 #define DCDC_CTRL0_DEBUG_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
27509 
27510 #define DCDC_CTRL0_TRG_GPC_EN_MASK               (0x80000000U)
27511 #define DCDC_CTRL0_TRG_GPC_EN_SHIFT              (31U)
27512 /*! TRG_GPC_EN - TRG_GPC_EN: used to enable TRG_GPC_* value or not.
27513  *  0b0..No matter there is GPC stby request or not, value in TRG_SW_* register will always be used as DCDC analog target value.
27514  *  0b1..When there is a GPC stby request, value in TRG_GPC_* register will be used as DCDC analog target value instead of TRG_SW_*'s
27515  */
27516 #define DCDC_CTRL0_TRG_GPC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRG_GPC_EN_SHIFT)) & DCDC_CTRL0_TRG_GPC_EN_MASK)
27517 /*! @} */
27518 
27519 /*! @name OK_CNT - OK CNT */
27520 /*! @{ */
27521 
27522 #define DCDC_OK_CNT_OK_COUNT_MASK                (0xFFFFFFFFU)
27523 #define DCDC_OK_CNT_OK_COUNT_SHIFT               (0U)
27524 /*! OK_COUNT - OK_COUNT */
27525 #define DCDC_OK_CNT_OK_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_OK_CNT_OK_COUNT_SHIFT)) & DCDC_OK_CNT_OK_COUNT_MASK)
27526 /*! @} */
27527 
27528 /*! @name CURRENT_TRG - CURRENT TARGET VALUE for DCDC ANALOG */
27529 /*! @{ */
27530 
27531 #define DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_MASK     (0x1FU)
27532 #define DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_SHIFT    (0U)
27533 #define DCDC_CURRENT_TRG_VDD1P0CTRL_TRG(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_MASK)
27534 
27535 #define DCDC_CURRENT_TRG_VDD1P8CTRL_TRG_MASK     (0x1F00U)
27536 #define DCDC_CURRENT_TRG_VDD1P8CTRL_TRG_SHIFT    (8U)
27537 #define DCDC_CURRENT_TRG_VDD1P8CTRL_TRG(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CURRENT_TRG_VDD1P8CTRL_TRG_MASK)
27538 
27539 #define DCDC_CURRENT_TRG_DCDC_UPDATING_MASK      (0x8000U)
27540 #define DCDC_CURRENT_TRG_DCDC_UPDATING_SHIFT     (15U)
27541 /*! DCDC_UPDATING
27542  *  0b0..Last DCDC change has been done. New value can be written to TRG register to trigger a new change of DCDC voltage.
27543  *  0b1..Last DCDC change is still not done. New value should not be written to TRG register to trigger a new change of DCDC voltage.
27544  */
27545 #define DCDC_CURRENT_TRG_DCDC_UPDATING(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_DCDC_UPDATING_SHIFT)) & DCDC_CURRENT_TRG_DCDC_UPDATING_MASK)
27546 
27547 #define DCDC_CURRENT_TRG_VDD1P0CTRL_LP_TRG_MASK  (0x1F0000U)
27548 #define DCDC_CURRENT_TRG_VDD1P0CTRL_LP_TRG_SHIFT (16U)
27549 #define DCDC_CURRENT_TRG_VDD1P0CTRL_LP_TRG(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_VDD1P0CTRL_LP_TRG_SHIFT)) & DCDC_CURRENT_TRG_VDD1P0CTRL_LP_TRG_MASK)
27550 
27551 #define DCDC_CURRENT_TRG_LP_EN_1P0_MASK          (0x80000000U)
27552 #define DCDC_CURRENT_TRG_LP_EN_1P0_SHIFT         (31U)
27553 /*! LP_EN_1P0 - This value comes from the smaller one between TRG_SW_0 and TRG_SW_1. This bit only
27554  *    controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG
27555  *  0b0..DCDC 1P0 works in run mode. Its output voltage is controlled by VDD1P0CTRL_TRG.
27556  *  0b1..DCDC 1P0 works in low power mode. Its output voltage is controlled by VDD1P0CTRL_LP_TRG and its output current is less than 50mA.
27557  */
27558 #define DCDC_CURRENT_TRG_LP_EN_1P0(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CURRENT_TRG_LP_EN_1P0_SHIFT)) & DCDC_CURRENT_TRG_LP_EN_1P0_MASK)
27559 /*! @} */
27560 
27561 /*! @name FILTER_CNT - FILTER CNT */
27562 /*! @{ */
27563 
27564 #define DCDC_FILTER_CNT_FILTER_CNT_CFG_MASK      (0xFFFFFFFFU)
27565 #define DCDC_FILTER_CNT_FILTER_CNT_CFG_SHIFT     (0U)
27566 /*! FILTER_CNT_CFG - FILTER_CNT_CFG */
27567 #define DCDC_FILTER_CNT_FILTER_CNT_CFG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_FILTER_CNT_FILTER_CNT_CFG_SHIFT)) & DCDC_FILTER_CNT_FILTER_CNT_CFG_MASK)
27568 /*! @} */
27569 
27570 /*! @name TRG_0_AUTHEN - TRG_0 Authentication Control */
27571 /*! @{ */
27572 
27573 #define DCDC_TRG_0_AUTHEN_TZ_USER_MASK           (0x100U)
27574 #define DCDC_TRG_0_AUTHEN_TZ_USER_SHIFT          (8U)
27575 /*! TZ_USER - Allow user mode write
27576  *  0b0..TRG_0 registers can only be written in privilege mode.
27577  *  0b1..TRG_0 registers can be written either in privilege mode or user mode.
27578  */
27579 #define DCDC_TRG_0_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_0_AUTHEN_TZ_USER_SHIFT)) & DCDC_TRG_0_AUTHEN_TZ_USER_MASK)
27580 
27581 #define DCDC_TRG_0_AUTHEN_TZ_NS_MASK             (0x200U)
27582 #define DCDC_TRG_0_AUTHEN_TZ_NS_SHIFT            (9U)
27583 /*! TZ_NS - Allow non-secure mode access
27584  *  0b0..TRG_0 registers can only be written in secure mode.
27585  *  0b1..TRG_0 registers can be written either in secure mode or non-secure mode.
27586  */
27587 #define DCDC_TRG_0_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_0_AUTHEN_TZ_NS_SHIFT)) & DCDC_TRG_0_AUTHEN_TZ_NS_MASK)
27588 
27589 #define DCDC_TRG_0_AUTHEN_LOCK_TZ_MASK           (0x800U)
27590 #define DCDC_TRG_0_AUTHEN_LOCK_TZ_SHIFT          (11U)
27591 /*! LOCK_TZ - Lock TZ_NS and TZ_USER
27592  *  0b0..TZ_NS and TZ_USER value can be changed.
27593  *  0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed.
27594  */
27595 #define DCDC_TRG_0_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_0_AUTHEN_LOCK_TZ_SHIFT)) & DCDC_TRG_0_AUTHEN_LOCK_TZ_MASK)
27596 
27597 #define DCDC_TRG_0_AUTHEN_LOCK_LIST_MASK         (0x8000U)
27598 #define DCDC_TRG_0_AUTHEN_LOCK_LIST_SHIFT        (15U)
27599 /*! LOCK_LIST - White list lock
27600  *  0b0..WHITE_LIST value can be changed.
27601  *  0b1..LOCK_LIST and WHITE_LIST value cannot be changed.
27602  */
27603 #define DCDC_TRG_0_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_0_AUTHEN_LOCK_LIST_SHIFT)) & DCDC_TRG_0_AUTHEN_LOCK_LIST_MASK)
27604 
27605 #define DCDC_TRG_0_AUTHEN_WHITE_LIST_MASK        (0xFFFF0000U)
27606 #define DCDC_TRG_0_AUTHEN_WHITE_LIST_SHIFT       (16U)
27607 /*! WHITE_LIST - Domain ID white list
27608  *  0b0000000000000001..Core with domain ID=0 can write TRG_0 registers.
27609  *  0b0000000000000010..Core with domain ID=1 can write TRG_0 registers.
27610  *  0b0000000000000100..Core with domain ID=2 can write TRG_0 registers.
27611  *  0b0000000000001000..Core with domain ID=3 can write TRG_0 registers.
27612  *  0b0000000000010000..Core with domain ID=4 can write TRG_0 registers.
27613  *  0b0000000000100000..Core with domain ID=5 can write TRG_0 registers.
27614  *  0b0000000001000000..Core with domain ID=6 can write TRG_0 registers.
27615  *  0b0000000010000000..Core with domain ID=7 can write TRG_0 registers.
27616  *  0b0000000100000000..Core with domain ID=8 can write TRG_0 registers.
27617  *  0b0000001000000000..Core with domain ID=9 can write TRG_0 registers.
27618  *  0b0000010000000000..Core with domain ID=10 can write TRG_0 registers.
27619  *  0b0000100000000000..Core with domain ID=11 can write TRG_0 registers.
27620  *  0b0001000000000000..Core with domain ID=12 can write TRG_0 registers.
27621  *  0b0010000000000000..Core with domain ID=13 can write TRG_0 registers.
27622  *  0b0100000000000000..Core with domain ID=14 can write TRG_0 registers.
27623  *  0b1000000000000000..Core with domain ID=15 can write TRG_0 registers.
27624  */
27625 #define DCDC_TRG_0_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_0_AUTHEN_WHITE_LIST_SHIFT)) & DCDC_TRG_0_AUTHEN_WHITE_LIST_MASK)
27626 /*! @} */
27627 
27628 /*! @name TRG_SW_0 - Target SW Control for CORE 0 */
27629 /*! @{ */
27630 
27631 #define DCDC_TRG_SW_0_VDD1P0CTRL_TRG_MASK        (0x1FU)
27632 #define DCDC_TRG_SW_0_VDD1P0CTRL_TRG_SHIFT       (0U)
27633 #define DCDC_TRG_SW_0_VDD1P0CTRL_TRG(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_0_VDD1P0CTRL_TRG_SHIFT)) & DCDC_TRG_SW_0_VDD1P0CTRL_TRG_MASK)
27634 
27635 #define DCDC_TRG_SW_0_VDD1P8CTRL_TRG_MASK        (0x1F00U)
27636 #define DCDC_TRG_SW_0_VDD1P8CTRL_TRG_SHIFT       (8U)
27637 #define DCDC_TRG_SW_0_VDD1P8CTRL_TRG(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_0_VDD1P8CTRL_TRG_SHIFT)) & DCDC_TRG_SW_0_VDD1P8CTRL_TRG_MASK)
27638 
27639 #define DCDC_TRG_SW_0_VDD1P0CTRL_LP_TRG_MASK     (0x1F0000U)
27640 #define DCDC_TRG_SW_0_VDD1P0CTRL_LP_TRG_SHIFT    (16U)
27641 #define DCDC_TRG_SW_0_VDD1P0CTRL_LP_TRG(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_0_VDD1P0CTRL_LP_TRG_SHIFT)) & DCDC_TRG_SW_0_VDD1P0CTRL_LP_TRG_MASK)
27642 
27643 #define DCDC_TRG_SW_0_LP_EN_1P0_MASK             (0x80000000U)
27644 #define DCDC_TRG_SW_0_LP_EN_1P0_SHIFT            (31U)
27645 /*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */
27646 #define DCDC_TRG_SW_0_LP_EN_1P0(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_0_LP_EN_1P0_SHIFT)) & DCDC_TRG_SW_0_LP_EN_1P0_MASK)
27647 /*! @} */
27648 
27649 /*! @name TRG_GPC_0 - Target GPC Control for CORE 0 */
27650 /*! @{ */
27651 
27652 #define DCDC_TRG_GPC_0_VDD1P0CTRL_TRG_MASK       (0x1FU)
27653 #define DCDC_TRG_GPC_0_VDD1P0CTRL_TRG_SHIFT      (0U)
27654 #define DCDC_TRG_GPC_0_VDD1P0CTRL_TRG(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_0_VDD1P0CTRL_TRG_SHIFT)) & DCDC_TRG_GPC_0_VDD1P0CTRL_TRG_MASK)
27655 
27656 #define DCDC_TRG_GPC_0_VDD1P8CTRL_TRG_MASK       (0x1F00U)
27657 #define DCDC_TRG_GPC_0_VDD1P8CTRL_TRG_SHIFT      (8U)
27658 #define DCDC_TRG_GPC_0_VDD1P8CTRL_TRG(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_0_VDD1P8CTRL_TRG_SHIFT)) & DCDC_TRG_GPC_0_VDD1P8CTRL_TRG_MASK)
27659 
27660 #define DCDC_TRG_GPC_0_VDD1P0CTRL_LP_TRG_MASK    (0x1F0000U)
27661 #define DCDC_TRG_GPC_0_VDD1P0CTRL_LP_TRG_SHIFT   (16U)
27662 #define DCDC_TRG_GPC_0_VDD1P0CTRL_LP_TRG(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_0_VDD1P0CTRL_LP_TRG_SHIFT)) & DCDC_TRG_GPC_0_VDD1P0CTRL_LP_TRG_MASK)
27663 
27664 #define DCDC_TRG_GPC_0_LP_EN_1P0_MASK            (0x80000000U)
27665 #define DCDC_TRG_GPC_0_LP_EN_1P0_SHIFT           (31U)
27666 /*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */
27667 #define DCDC_TRG_GPC_0_LP_EN_1P0(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_0_LP_EN_1P0_SHIFT)) & DCDC_TRG_GPC_0_LP_EN_1P0_MASK)
27668 /*! @} */
27669 
27670 /*! @name TRG_1_AUTHEN - TRG_1 Authentication Control */
27671 /*! @{ */
27672 
27673 #define DCDC_TRG_1_AUTHEN_TZ_USER_MASK           (0x100U)
27674 #define DCDC_TRG_1_AUTHEN_TZ_USER_SHIFT          (8U)
27675 /*! TZ_USER - Allow user mode write
27676  *  0b0..TRG_1 registers can only be written in privilege mode.
27677  *  0b1..TRG_1 registers can be written either in privilege mode or user mode.
27678  */
27679 #define DCDC_TRG_1_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_1_AUTHEN_TZ_USER_SHIFT)) & DCDC_TRG_1_AUTHEN_TZ_USER_MASK)
27680 
27681 #define DCDC_TRG_1_AUTHEN_TZ_NS_MASK             (0x200U)
27682 #define DCDC_TRG_1_AUTHEN_TZ_NS_SHIFT            (9U)
27683 /*! TZ_NS - Allow non-secure mode access
27684  *  0b0..TRG_1 registers can only be written in secure mode.
27685  *  0b1..TRG_1 registers can be written either in secure mode or non-secure mode.
27686  */
27687 #define DCDC_TRG_1_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_1_AUTHEN_TZ_NS_SHIFT)) & DCDC_TRG_1_AUTHEN_TZ_NS_MASK)
27688 
27689 #define DCDC_TRG_1_AUTHEN_LOCK_TZ_MASK           (0x800U)
27690 #define DCDC_TRG_1_AUTHEN_LOCK_TZ_SHIFT          (11U)
27691 /*! LOCK_TZ - Lock TZ_NS and TZ_USER
27692  *  0b0..TZ_NS and TZ_USER value can be changed.
27693  *  0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed.
27694  */
27695 #define DCDC_TRG_1_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_1_AUTHEN_LOCK_TZ_SHIFT)) & DCDC_TRG_1_AUTHEN_LOCK_TZ_MASK)
27696 
27697 #define DCDC_TRG_1_AUTHEN_LOCK_LIST_MASK         (0x8000U)
27698 #define DCDC_TRG_1_AUTHEN_LOCK_LIST_SHIFT        (15U)
27699 /*! LOCK_LIST - White list lock
27700  *  0b0..WHITE_LIST value can be changed.
27701  *  0b1..LOCK_LIST and WHITE_LIST value cannot be changed.
27702  */
27703 #define DCDC_TRG_1_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_1_AUTHEN_LOCK_LIST_SHIFT)) & DCDC_TRG_1_AUTHEN_LOCK_LIST_MASK)
27704 
27705 #define DCDC_TRG_1_AUTHEN_WHITE_LIST_MASK        (0xFFFF0000U)
27706 #define DCDC_TRG_1_AUTHEN_WHITE_LIST_SHIFT       (16U)
27707 /*! WHITE_LIST - Domain ID white list
27708  *  0b0000000000000001..Core with domain ID=0 can write TRG_1 registers.
27709  *  0b0000000000000010..Core with domain ID=1 can write TRG_1 registers.
27710  *  0b0000000000000100..Core with domain ID=2 can write TRG_1 registers.
27711  *  0b0000000000001000..Core with domain ID=3 can write TRG_1 registers.
27712  *  0b0000000000010000..Core with domain ID=4 can write TRG_1 registers.
27713  *  0b0000000000100000..Core with domain ID=5 can write TRG_1 registers.
27714  *  0b0000000001000000..Core with domain ID=6 can write TRG_1 registers.
27715  *  0b0000000010000000..Core with domain ID=7 can write TRG_1 registers.
27716  *  0b0000000100000000..Core with domain ID=8 can write TRG_1 registers.
27717  *  0b0000001000000000..Core with domain ID=9 can write TRG_1 registers.
27718  *  0b0000010000000000..Core with domain ID=10 can write TRG_1 registers.
27719  *  0b0000100000000000..Core with domain ID=11 can write TRG_1 registers.
27720  *  0b0001000000000000..Core with domain ID=12 can write TRG_1 registers.
27721  *  0b0010000000000000..Core with domain ID=13 can write TRG_1 registers.
27722  *  0b0100000000000000..Core with domain ID=14 can write TRG_1 registers.
27723  *  0b1000000000000000..Core with domain ID=15 can write TRG_1 registers.
27724  */
27725 #define DCDC_TRG_1_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_1_AUTHEN_WHITE_LIST_SHIFT)) & DCDC_TRG_1_AUTHEN_WHITE_LIST_MASK)
27726 /*! @} */
27727 
27728 /*! @name TRG_SW_1 - Target SW Control for CORE 1 */
27729 /*! @{ */
27730 
27731 #define DCDC_TRG_SW_1_VDD1P0CTRL_TRG_MASK        (0x1FU)
27732 #define DCDC_TRG_SW_1_VDD1P0CTRL_TRG_SHIFT       (0U)
27733 #define DCDC_TRG_SW_1_VDD1P0CTRL_TRG(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_TRG_SW_1_VDD1P0CTRL_TRG_MASK)
27734 
27735 #define DCDC_TRG_SW_1_VDD1P8CTRL_TRG_MASK        (0x1F00U)
27736 #define DCDC_TRG_SW_1_VDD1P8CTRL_TRG_SHIFT       (8U)
27737 #define DCDC_TRG_SW_1_VDD1P8CTRL_TRG(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_TRG_SW_1_VDD1P8CTRL_TRG_MASK)
27738 
27739 #define DCDC_TRG_SW_1_VDD1P0CTRL_LP_TRG_MASK     (0x1F0000U)
27740 #define DCDC_TRG_SW_1_VDD1P0CTRL_LP_TRG_SHIFT    (16U)
27741 #define DCDC_TRG_SW_1_VDD1P0CTRL_LP_TRG(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_1_VDD1P0CTRL_LP_TRG_SHIFT)) & DCDC_TRG_SW_1_VDD1P0CTRL_LP_TRG_MASK)
27742 
27743 #define DCDC_TRG_SW_1_LP_EN_1P0_MASK             (0x80000000U)
27744 #define DCDC_TRG_SW_1_LP_EN_1P0_SHIFT            (31U)
27745 /*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */
27746 #define DCDC_TRG_SW_1_LP_EN_1P0(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_SW_1_LP_EN_1P0_SHIFT)) & DCDC_TRG_SW_1_LP_EN_1P0_MASK)
27747 /*! @} */
27748 
27749 /*! @name TRG_GPC_1 - Target GPC Control for CORE 1 */
27750 /*! @{ */
27751 
27752 #define DCDC_TRG_GPC_1_VDD1P0CTRL_TRG_MASK       (0x1FU)
27753 #define DCDC_TRG_GPC_1_VDD1P0CTRL_TRG_SHIFT      (0U)
27754 #define DCDC_TRG_GPC_1_VDD1P0CTRL_TRG(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_TRG_GPC_1_VDD1P0CTRL_TRG_MASK)
27755 
27756 #define DCDC_TRG_GPC_1_VDD1P8CTRL_TRG_MASK       (0x1F00U)
27757 #define DCDC_TRG_GPC_1_VDD1P8CTRL_TRG_SHIFT      (8U)
27758 #define DCDC_TRG_GPC_1_VDD1P8CTRL_TRG(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_TRG_GPC_1_VDD1P8CTRL_TRG_MASK)
27759 
27760 #define DCDC_TRG_GPC_1_VDD1P0CTRL_LP_TRG_MASK    (0x1F0000U)
27761 #define DCDC_TRG_GPC_1_VDD1P0CTRL_LP_TRG_SHIFT   (16U)
27762 #define DCDC_TRG_GPC_1_VDD1P0CTRL_LP_TRG(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_1_VDD1P0CTRL_LP_TRG_SHIFT)) & DCDC_TRG_GPC_1_VDD1P0CTRL_LP_TRG_MASK)
27763 
27764 #define DCDC_TRG_GPC_1_LP_EN_1P0_MASK            (0x80000000U)
27765 #define DCDC_TRG_GPC_1_LP_EN_1P0_SHIFT           (31U)
27766 /*! LP_EN_1P0 - LP_EN_1P0 only controls 1P0. 1P8 is always controlled by VDD1P8CTRL_TRG */
27767 #define DCDC_TRG_GPC_1_LP_EN_1P0(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_TRG_GPC_1_LP_EN_1P0_SHIFT)) & DCDC_TRG_GPC_1_LP_EN_1P0_MASK)
27768 /*! @} */
27769 
27770 
27771 /*!
27772  * @}
27773  */ /* end of group DCDC_Register_Masks */
27774 
27775 
27776 /* DCDC - Peripheral instance base addresses */
27777 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
27778   /** Peripheral DCDC base address */
27779   #define DCDC_BASE                                (0x54520000u)
27780   /** Peripheral DCDC base address */
27781   #define DCDC_BASE_NS                             (0x44520000u)
27782   /** Peripheral DCDC base pointer */
27783   #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
27784   /** Peripheral DCDC base pointer */
27785   #define DCDC_NS                                  ((DCDC_Type *)DCDC_BASE_NS)
27786   /** Array initializer of DCDC peripheral base addresses */
27787   #define DCDC_BASE_ADDRS                          { DCDC_BASE }
27788   /** Array initializer of DCDC peripheral base pointers */
27789   #define DCDC_BASE_PTRS                           { DCDC }
27790   /** Array initializer of DCDC peripheral base addresses */
27791   #define DCDC_BASE_ADDRS_NS                       { DCDC_BASE_NS }
27792   /** Array initializer of DCDC peripheral base pointers */
27793   #define DCDC_BASE_PTRS_NS                        { DCDC_NS }
27794 #else
27795   /** Peripheral DCDC base address */
27796   #define DCDC_BASE                                (0x44520000u)
27797   /** Peripheral DCDC base pointer */
27798   #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
27799   /** Array initializer of DCDC peripheral base addresses */
27800   #define DCDC_BASE_ADDRS                          { DCDC_BASE }
27801   /** Array initializer of DCDC peripheral base pointers */
27802   #define DCDC_BASE_PTRS                           { DCDC }
27803 #endif
27804 /** Interrupt vectors for the DCDC peripheral type */
27805 #define DCDC_IRQS                                { DCDC_IRQn }
27806 
27807 /*!
27808  * @}
27809  */ /* end of group DCDC_Peripheral_Access_Layer */
27810 
27811 
27812 /* ----------------------------------------------------------------------------
27813    -- DMA Peripheral Access Layer
27814    ---------------------------------------------------------------------------- */
27815 
27816 /*!
27817  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
27818  * @{
27819  */
27820 
27821 /** DMA - Register Layout Typedef */
27822 typedef struct {
27823   __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
27824   __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
27825   __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
27826   __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
27827        uint8_t RESERVED_0[240];
27828   __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
27829        uint8_t RESERVED_1[65152];
27830   struct {                                         /* offset: 0x10000, array step: 0x10000 */
27831     __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
27832     __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
27833     __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
27834     __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
27835     __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
27836     __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
27837          uint8_t RESERVED_0[8];
27838     __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x10020, array step: 0x10000 */
27839     __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x10000 */
27840     __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x10000 */
27841     union {                                          /* offset: 0x10028, array step: 0x10000 */
27842       __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
27843       __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
27844     };
27845     __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x10000 */
27846     __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x10030, array step: 0x10000 */
27847     __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x10000 */
27848     union {                                          /* offset: 0x10036, array step: 0x10000 */
27849       __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x10000 */
27850       __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x10000 */
27851     };
27852     __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x10000 */
27853     __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x1003C, array step: 0x10000 */
27854     union {                                          /* offset: 0x1003E, array step: 0x10000 */
27855       __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x10000 */
27856       __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x10000 */
27857     };
27858          uint8_t RESERVED_1[65472];
27859   } CH[32];
27860 } DMA_Type;
27861 
27862 /* ----------------------------------------------------------------------------
27863    -- DMA Register Masks
27864    ---------------------------------------------------------------------------- */
27865 
27866 /*!
27867  * @addtogroup DMA_Register_Masks DMA Register Masks
27868  * @{
27869  */
27870 
27871 /*! @name MP_CSR - Management Page Control */
27872 /*! @{ */
27873 
27874 #define DMA_MP_CSR_EDBG_MASK                     (0x2U)
27875 #define DMA_MP_CSR_EDBG_SHIFT                    (1U)
27876 /*! EDBG - Enable Debug
27877  *  0b0..Debug mode disabled
27878  *  0b1..Debug mode is enabled.
27879  */
27880 #define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
27881 
27882 #define DMA_MP_CSR_ERCA_MASK                     (0x4U)
27883 #define DMA_MP_CSR_ERCA_SHIFT                    (2U)
27884 /*! ERCA - Enable Round Robin Channel Arbitration
27885  *  0b0..Round-robin channel arbitration disabled
27886  *  0b1..Round-robin channel arbitration enabled
27887  */
27888 #define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
27889 
27890 #define DMA_MP_CSR_HAE_MASK                      (0x10U)
27891 #define DMA_MP_CSR_HAE_SHIFT                     (4U)
27892 /*! HAE - Halt After Error
27893  *  0b0..Normal operation
27894  *  0b1..Any error causes the HALT field to be set to 1
27895  */
27896 #define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
27897 
27898 #define DMA_MP_CSR_HALT_MASK                     (0x20U)
27899 #define DMA_MP_CSR_HALT_SHIFT                    (5U)
27900 /*! HALT - Halt DMA Operations
27901  *  0b0..Normal operation
27902  *  0b1..Stall the start of any new channels
27903  */
27904 #define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
27905 
27906 #define DMA_MP_CSR_GCLC_MASK                     (0x40U)
27907 #define DMA_MP_CSR_GCLC_SHIFT                    (6U)
27908 /*! GCLC - Global Channel Linking Control
27909  *  0b0..Channel linking disabled for all channels
27910  *  0b1..Channel linking available and controlled by each channel's link settings
27911  */
27912 #define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
27913 
27914 #define DMA_MP_CSR_GMRC_MASK                     (0x80U)
27915 #define DMA_MP_CSR_GMRC_SHIFT                    (7U)
27916 /*! GMRC - Global Master ID Replication Control
27917  *  0b0..Master ID replication disabled for all channels
27918  *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
27919  */
27920 #define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
27921 
27922 #define DMA_MP_CSR_ECX_MASK                      (0x100U)
27923 #define DMA_MP_CSR_ECX_SHIFT                     (8U)
27924 /*! ECX - Cancel Transfer With Error
27925  *  0b0..Normal operation
27926  *  0b1..Cancel the remaining data transfer
27927  */
27928 #define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
27929 
27930 #define DMA_MP_CSR_CX_MASK                       (0x200U)
27931 #define DMA_MP_CSR_CX_SHIFT                      (9U)
27932 /*! CX - Cancel Transfer
27933  *  0b0..Normal operation
27934  *  0b1..Cancel the remaining data transfer
27935  */
27936 #define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
27937 
27938 #define DMA_MP_CSR_ACTIVE_ID_MASK                (0x1F000000U)
27939 #define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
27940 /*! ACTIVE_ID - Active Channel ID */
27941 #define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
27942 
27943 #define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
27944 #define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
27945 /*! ACTIVE - DMA Active Status
27946  *  0b0..eDMA is idle
27947  *  0b1..eDMA is executing a channel
27948  */
27949 #define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
27950 /*! @} */
27951 
27952 /*! @name MP_ES - Management Page Error Status */
27953 /*! @{ */
27954 
27955 #define DMA_MP_ES_DBE_MASK                       (0x1U)
27956 #define DMA_MP_ES_DBE_SHIFT                      (0U)
27957 /*! DBE - Destination Bus Error
27958  *  0b0..No destination bus error
27959  *  0b1..Last recorded error was a bus error on a destination write
27960  */
27961 #define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
27962 
27963 #define DMA_MP_ES_SBE_MASK                       (0x2U)
27964 #define DMA_MP_ES_SBE_SHIFT                      (1U)
27965 /*! SBE - Source Bus Error
27966  *  0b0..No source bus error
27967  *  0b1..Last recorded error was a bus error on a source read
27968  */
27969 #define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
27970 
27971 #define DMA_MP_ES_SGE_MASK                       (0x4U)
27972 #define DMA_MP_ES_SGE_SHIFT                      (2U)
27973 /*! SGE - Scatter/Gather Configuration Error
27974  *  0b0..No scatter/gather configuration error
27975  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
27976  */
27977 #define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
27978 
27979 #define DMA_MP_ES_NCE_MASK                       (0x8U)
27980 #define DMA_MP_ES_NCE_SHIFT                      (3U)
27981 /*! NCE - NBYTES/CITER Configuration Error
27982  *  0b0..No NBYTES/CITER configuration error
27983  *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
27984  */
27985 #define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
27986 
27987 #define DMA_MP_ES_DOE_MASK                       (0x10U)
27988 #define DMA_MP_ES_DOE_SHIFT                      (4U)
27989 /*! DOE - Destination Offset Error
27990  *  0b0..No destination offset configuration error
27991  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
27992  */
27993 #define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
27994 
27995 #define DMA_MP_ES_DAE_MASK                       (0x20U)
27996 #define DMA_MP_ES_DAE_SHIFT                      (5U)
27997 /*! DAE - Destination Address Error
27998  *  0b0..No destination address configuration error
27999  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
28000  */
28001 #define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
28002 
28003 #define DMA_MP_ES_SOE_MASK                       (0x40U)
28004 #define DMA_MP_ES_SOE_SHIFT                      (6U)
28005 /*! SOE - Source Offset Error
28006  *  0b0..No source offset configuration error
28007  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
28008  */
28009 #define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
28010 
28011 #define DMA_MP_ES_SAE_MASK                       (0x80U)
28012 #define DMA_MP_ES_SAE_SHIFT                      (7U)
28013 /*! SAE - Source Address Error
28014  *  0b0..No source address configuration error
28015  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
28016  */
28017 #define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
28018 
28019 #define DMA_MP_ES_ECX_MASK                       (0x100U)
28020 #define DMA_MP_ES_ECX_SHIFT                      (8U)
28021 /*! ECX - Transfer Canceled
28022  *  0b0..No canceled transfers
28023  *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
28024  */
28025 #define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
28026 
28027 #define DMA_MP_ES_ERRCHN_MASK                    (0x1F000000U)
28028 #define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
28029 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
28030 #define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
28031 
28032 #define DMA_MP_ES_VLD_MASK                       (0x80000000U)
28033 #define DMA_MP_ES_VLD_SHIFT                      (31U)
28034 /*! VLD - Valid
28035  *  0b0..No CHn_ES[ERR] fields are set to 1
28036  *  0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared
28037  */
28038 #define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
28039 /*! @} */
28040 
28041 /*! @name MP_INT - Management Page Interrupt Request Status */
28042 /*! @{ */
28043 
28044 #define DMA_MP_INT_INT_MASK                      (0xFFFFFFFFU)
28045 #define DMA_MP_INT_INT_SHIFT                     (0U)
28046 /*! INT - Interrupt Request Status */
28047 #define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
28048 /*! @} */
28049 
28050 /*! @name MP_HRS - Management Page Hardware Request Status */
28051 /*! @{ */
28052 
28053 #define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
28054 #define DMA_MP_HRS_HRS_SHIFT                     (0U)
28055 /*! HRS - Hardware Request Status */
28056 #define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
28057 /*! @} */
28058 
28059 /*! @name CH_GRPRI - Channel Arbitration Group */
28060 /*! @{ */
28061 
28062 #define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
28063 #define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
28064 /*! GRPRI - Arbitration Group For Channel n */
28065 #define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
28066 /*! @} */
28067 
28068 /* The count of DMA_CH_GRPRI */
28069 #define DMA_CH_GRPRI_COUNT                       (32U)
28070 
28071 /*! @name CH_CSR - Channel Control and Status */
28072 /*! @{ */
28073 
28074 #define DMA_CH_CSR_ERQ_MASK                      (0x1U)
28075 #define DMA_CH_CSR_ERQ_SHIFT                     (0U)
28076 /*! ERQ - Enable DMA Request
28077  *  0b0..DMA hardware request signal for corresponding channel disabled
28078  *  0b1..DMA hardware request signal for corresponding channel enabled
28079  */
28080 #define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
28081 
28082 #define DMA_CH_CSR_EARQ_MASK                     (0x2U)
28083 #define DMA_CH_CSR_EARQ_SHIFT                    (1U)
28084 /*! EARQ - Enable Asynchronous DMA Request
28085  *  0b0..Disable asynchronous DMA request for the channel
28086  *  0b1..Enable asynchronous DMA request for the channel
28087  */
28088 #define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
28089 
28090 #define DMA_CH_CSR_EEI_MASK                      (0x4U)
28091 #define DMA_CH_CSR_EEI_SHIFT                     (2U)
28092 /*! EEI - Enable Error Interrupt
28093  *  0b0..Error signal for corresponding channel does not generate error interrupt
28094  *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
28095  */
28096 #define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
28097 
28098 #define DMA_CH_CSR_EBW_MASK                      (0x8U)
28099 #define DMA_CH_CSR_EBW_SHIFT                     (3U)
28100 /*! EBW - Enable Buffered Writes
28101  *  0b0..Buffered writes on system bus disabled
28102  *  0b1..Buffered writes on system bus enabled
28103  */
28104 #define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
28105 
28106 #define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
28107 #define DMA_CH_CSR_DONE_SHIFT                    (30U)
28108 /*! DONE - Channel Done */
28109 #define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
28110 
28111 #define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
28112 #define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
28113 /*! ACTIVE - Channel Active */
28114 #define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
28115 /*! @} */
28116 
28117 /* The count of DMA_CH_CSR */
28118 #define DMA_CH_CSR_COUNT                         (32U)
28119 
28120 /*! @name CH_ES - Channel Error Status */
28121 /*! @{ */
28122 
28123 #define DMA_CH_ES_DBE_MASK                       (0x1U)
28124 #define DMA_CH_ES_DBE_SHIFT                      (0U)
28125 /*! DBE - Destination Bus Error
28126  *  0b0..No destination bus error
28127  *  0b1..Last recorded error was bus error on destination write
28128  */
28129 #define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
28130 
28131 #define DMA_CH_ES_SBE_MASK                       (0x2U)
28132 #define DMA_CH_ES_SBE_SHIFT                      (1U)
28133 /*! SBE - Source Bus Error
28134  *  0b0..No source bus error
28135  *  0b1..Last recorded error was bus error on source read
28136  */
28137 #define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
28138 
28139 #define DMA_CH_ES_SGE_MASK                       (0x4U)
28140 #define DMA_CH_ES_SGE_SHIFT                      (2U)
28141 /*! SGE - Scatter/Gather Configuration Error
28142  *  0b0..No scatter/gather configuration error
28143  *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
28144  */
28145 #define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
28146 
28147 #define DMA_CH_ES_NCE_MASK                       (0x8U)
28148 #define DMA_CH_ES_NCE_SHIFT                      (3U)
28149 /*! NCE - NBYTES/CITER Configuration Error
28150  *  0b0..No NBYTES/CITER configuration error
28151  *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
28152  */
28153 #define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
28154 
28155 #define DMA_CH_ES_DOE_MASK                       (0x10U)
28156 #define DMA_CH_ES_DOE_SHIFT                      (4U)
28157 /*! DOE - Destination Offset Error
28158  *  0b0..No destination offset configuration error
28159  *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
28160  */
28161 #define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
28162 
28163 #define DMA_CH_ES_DAE_MASK                       (0x20U)
28164 #define DMA_CH_ES_DAE_SHIFT                      (5U)
28165 /*! DAE - Destination Address Error
28166  *  0b0..No destination address configuration error
28167  *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
28168  */
28169 #define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
28170 
28171 #define DMA_CH_ES_SOE_MASK                       (0x40U)
28172 #define DMA_CH_ES_SOE_SHIFT                      (6U)
28173 /*! SOE - Source Offset Error
28174  *  0b0..No source offset configuration error
28175  *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
28176  */
28177 #define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
28178 
28179 #define DMA_CH_ES_SAE_MASK                       (0x80U)
28180 #define DMA_CH_ES_SAE_SHIFT                      (7U)
28181 /*! SAE - Source Address Error
28182  *  0b0..No source address configuration error
28183  *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
28184  */
28185 #define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
28186 
28187 #define DMA_CH_ES_ERR_MASK                       (0x80000000U)
28188 #define DMA_CH_ES_ERR_SHIFT                      (31U)
28189 /*! ERR - Error In Channel
28190  *  0b0..An error in this channel has not occurred
28191  *  0b1..An error in this channel has occurred
28192  */
28193 #define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
28194 /*! @} */
28195 
28196 /* The count of DMA_CH_ES */
28197 #define DMA_CH_ES_COUNT                          (32U)
28198 
28199 /*! @name CH_INT - Channel Interrupt Status */
28200 /*! @{ */
28201 
28202 #define DMA_CH_INT_INT_MASK                      (0x1U)
28203 #define DMA_CH_INT_INT_SHIFT                     (0U)
28204 /*! INT - Interrupt Request
28205  *  0b0..Interrupt request for corresponding channel cleared
28206  *  0b1..Interrupt request for corresponding channel active
28207  */
28208 #define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
28209 /*! @} */
28210 
28211 /* The count of DMA_CH_INT */
28212 #define DMA_CH_INT_COUNT                         (32U)
28213 
28214 /*! @name CH_SBR - Channel System Bus */
28215 /*! @{ */
28216 
28217 #define DMA_CH_SBR_MID_MASK                      (0xFU)
28218 #define DMA_CH_SBR_MID_SHIFT                     (0U)
28219 /*! MID - Master ID */
28220 #define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
28221 
28222 #define DMA_CH_SBR_SEC_MASK                      (0x4000U)
28223 #define DMA_CH_SBR_SEC_SHIFT                     (14U)
28224 /*! SEC - Security Level
28225  *  0b0..Nonsecure protection level for DMA transfers
28226  *  0b1..Secure protection level for DMA transfers
28227  */
28228 #define DMA_CH_SBR_SEC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK)
28229 
28230 #define DMA_CH_SBR_PAL_MASK                      (0x8000U)
28231 #define DMA_CH_SBR_PAL_SHIFT                     (15U)
28232 /*! PAL - Privileged Access Level
28233  *  0b0..User protection level for DMA transfers
28234  *  0b1..Privileged protection level for DMA transfers
28235  */
28236 #define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
28237 
28238 #define DMA_CH_SBR_EMI_MASK                      (0x10000U)
28239 #define DMA_CH_SBR_EMI_SHIFT                     (16U)
28240 /*! EMI - Enable Master ID Replication
28241  *  0b0..Master ID replication is disabled
28242  *  0b1..Master ID replication is enabled
28243  */
28244 #define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
28245 
28246 #define DMA_CH_SBR_ATTR_MASK                     (0x7E0000U)
28247 #define DMA_CH_SBR_ATTR_SHIFT                    (17U)
28248 /*! ATTR - Attribute Output */
28249 #define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
28250 /*! @} */
28251 
28252 /* The count of DMA_CH_SBR */
28253 #define DMA_CH_SBR_COUNT                         (32U)
28254 
28255 /*! @name CH_PRI - Channel Priority */
28256 /*! @{ */
28257 
28258 #define DMA_CH_PRI_APL_MASK                      (0x7U)
28259 #define DMA_CH_PRI_APL_SHIFT                     (0U)
28260 /*! APL - Arbitration Priority Level */
28261 #define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
28262 
28263 #define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
28264 #define DMA_CH_PRI_DPA_SHIFT                     (30U)
28265 /*! DPA - Disable Preempt Ability
28266  *  0b0..Channel can suspend a lower-priority channel
28267  *  0b1..Channel cannot suspend any other channel, regardless of channel priority
28268  */
28269 #define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
28270 
28271 #define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
28272 #define DMA_CH_PRI_ECP_SHIFT                     (31U)
28273 /*! ECP - Enable Channel Preemption
28274  *  0b0..Channel cannot be suspended by a higher-priority channel's service request
28275  *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
28276  */
28277 #define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
28278 /*! @} */
28279 
28280 /* The count of DMA_CH_PRI */
28281 #define DMA_CH_PRI_COUNT                         (32U)
28282 
28283 /*! @name CH_MUX - Channel Multiplexor Configuration */
28284 /*! @{ */
28285 
28286 #define DMA_CH_MUX_SRC_MASK                      (0x3FU)
28287 #define DMA_CH_MUX_SRC_SHIFT                     (0U)
28288 /*! SRC - Service Request Source */
28289 #define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
28290 /*! @} */
28291 
28292 /* The count of DMA_CH_MUX */
28293 #define DMA_CH_MUX_COUNT                         (32U)
28294 
28295 /*! @name TCD_SADDR - TCD Source Address */
28296 /*! @{ */
28297 
28298 #define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
28299 #define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
28300 /*! SADDR - Source Address */
28301 #define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
28302 /*! @} */
28303 
28304 /* The count of DMA_TCD_SADDR */
28305 #define DMA_TCD_SADDR_COUNT                      (32U)
28306 
28307 /*! @name TCD_SOFF - TCD Signed Source Address Offset */
28308 /*! @{ */
28309 
28310 #define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
28311 #define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
28312 /*! SOFF - Source Address Signed Offset */
28313 #define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
28314 /*! @} */
28315 
28316 /* The count of DMA_TCD_SOFF */
28317 #define DMA_TCD_SOFF_COUNT                       (32U)
28318 
28319 /*! @name TCD_ATTR - TCD Transfer Attributes */
28320 /*! @{ */
28321 
28322 #define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
28323 #define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
28324 /*! DSIZE - Destination Data Transfer Size */
28325 #define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
28326 
28327 #define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
28328 #define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
28329 /*! DMOD - Destination Address Modulo */
28330 #define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
28331 
28332 #define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
28333 #define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
28334 /*! SSIZE - Source Data Transfer Size
28335  *  0b000..8-bit
28336  *  0b001..16-bit
28337  *  0b010..32-bit
28338  *  0b011..64-bit
28339  *  0b100..16-byte
28340  *  0b101..32-byte
28341  *  0b110..64-byte
28342  *  0b111..
28343  */
28344 #define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
28345 
28346 #define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
28347 #define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
28348 /*! SMOD - Source Address Modulo
28349  *  0b00000..Source address modulo feature disabled
28350  *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
28351  */
28352 #define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
28353 /*! @} */
28354 
28355 /* The count of DMA_TCD_ATTR */
28356 #define DMA_TCD_ATTR_COUNT                       (32U)
28357 
28358 /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
28359 /*! @{ */
28360 
28361 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
28362 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
28363 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
28364 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
28365 
28366 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
28367 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
28368 /*! DMLOE - Destination Minor Loop Offset Enable
28369  *  0b0..Minor loop offset not applied to DADDR
28370  *  0b1..Minor loop offset applied to DADDR
28371  */
28372 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
28373 
28374 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
28375 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
28376 /*! SMLOE - Source Minor Loop Offset Enable
28377  *  0b0..Minor loop offset not applied to SADDR
28378  *  0b1..Minor loop offset applied to SADDR
28379  */
28380 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
28381 /*! @} */
28382 
28383 /* The count of DMA_TCD_NBYTES_MLOFFNO */
28384 #define DMA_TCD_NBYTES_MLOFFNO_COUNT             (32U)
28385 
28386 /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
28387 /*! @{ */
28388 
28389 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
28390 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
28391 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
28392 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
28393 
28394 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
28395 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
28396 /*! MLOFF - Minor Loop Offset */
28397 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
28398 
28399 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
28400 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
28401 /*! DMLOE - Destination Minor Loop Offset Enable
28402  *  0b0..Minor loop offset not applied to DADDR
28403  *  0b1..Minor loop offset applied to DADDR
28404  */
28405 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
28406 
28407 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
28408 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
28409 /*! SMLOE - Source Minor Loop Offset Enable
28410  *  0b0..Minor loop offset not applied to SADDR
28411  *  0b1..Minor loop offset applied to SADDR
28412  */
28413 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
28414 /*! @} */
28415 
28416 /* The count of DMA_TCD_NBYTES_MLOFFYES */
28417 #define DMA_TCD_NBYTES_MLOFFYES_COUNT            (32U)
28418 
28419 /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
28420 /*! @{ */
28421 
28422 #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
28423 #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
28424 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
28425 #define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
28426 /*! @} */
28427 
28428 /* The count of DMA_TCD_SLAST_SDA */
28429 #define DMA_TCD_SLAST_SDA_COUNT                  (32U)
28430 
28431 /*! @name TCD_DADDR - TCD Destination Address */
28432 /*! @{ */
28433 
28434 #define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
28435 #define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
28436 /*! DADDR - Destination Address */
28437 #define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
28438 /*! @} */
28439 
28440 /* The count of DMA_TCD_DADDR */
28441 #define DMA_TCD_DADDR_COUNT                      (32U)
28442 
28443 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */
28444 /*! @{ */
28445 
28446 #define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
28447 #define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
28448 /*! DOFF - Destination Address Signed Offset */
28449 #define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
28450 /*! @} */
28451 
28452 /* The count of DMA_TCD_DOFF */
28453 #define DMA_TCD_DOFF_COUNT                       (32U)
28454 
28455 /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
28456 /*! @{ */
28457 
28458 #define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
28459 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
28460 /*! CITER - Current Major Iteration Count */
28461 #define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
28462 
28463 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
28464 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
28465 /*! ELINK - Enable Link
28466  *  0b0..Channel-to-channel linking disabled
28467  *  0b1..Channel-to-channel linking enabled
28468  */
28469 #define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
28470 /*! @} */
28471 
28472 /* The count of DMA_TCD_CITER_ELINKNO */
28473 #define DMA_TCD_CITER_ELINKNO_COUNT              (32U)
28474 
28475 /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
28476 /*! @{ */
28477 
28478 #define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
28479 #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
28480 /*! CITER - Current Major Iteration Count */
28481 #define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
28482 
28483 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x3E00U)
28484 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
28485 /*! LINKCH - Minor Loop Link Channel Number */
28486 #define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
28487 
28488 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
28489 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
28490 /*! ELINK - Enable Link
28491  *  0b0..Channel-to-channel linking disabled
28492  *  0b1..Channel-to-channel linking enabled
28493  */
28494 #define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
28495 /*! @} */
28496 
28497 /* The count of DMA_TCD_CITER_ELINKYES */
28498 #define DMA_TCD_CITER_ELINKYES_COUNT             (32U)
28499 
28500 /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
28501 /*! @{ */
28502 
28503 #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
28504 #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
28505 /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
28506 #define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
28507 /*! @} */
28508 
28509 /* The count of DMA_TCD_DLAST_SGA */
28510 #define DMA_TCD_DLAST_SGA_COUNT                  (32U)
28511 
28512 /*! @name TCD_CSR - TCD Control and Status */
28513 /*! @{ */
28514 
28515 #define DMA_TCD_CSR_START_MASK                   (0x1U)
28516 #define DMA_TCD_CSR_START_SHIFT                  (0U)
28517 /*! START - Channel Start
28518  *  0b0..Channel not explicitly started
28519  *  0b1..Channel explicitly started via a software-initiated service request
28520  */
28521 #define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
28522 
28523 #define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
28524 #define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
28525 /*! INTMAJOR - Enable Interrupt If Major count complete
28526  *  0b0..End-of-major loop interrupt disabled
28527  *  0b1..End-of-major loop interrupt enabled
28528  */
28529 #define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
28530 
28531 #define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
28532 #define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
28533 /*! INTHALF - Enable Interrupt If Major Counter Half-complete
28534  *  0b0..Halfway point interrupt disabled
28535  *  0b1..Halfway point interrupt enabled
28536  */
28537 #define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
28538 
28539 #define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
28540 #define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
28541 /*! DREQ - Disable Request
28542  *  0b0..No operation
28543  *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
28544  */
28545 #define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
28546 
28547 #define DMA_TCD_CSR_ESG_MASK                     (0x10U)
28548 #define DMA_TCD_CSR_ESG_SHIFT                    (4U)
28549 /*! ESG - Enable Scatter/Gather Processing
28550  *  0b0..Current channel's TCD is normal format
28551  *  0b1..Current channel's TCD specifies scatter/gather format.
28552  */
28553 #define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
28554 
28555 #define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
28556 #define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
28557 /*! MAJORELINK - Enable Link When Major Loop Complete
28558  *  0b0..Channel-to-channel linking disabled
28559  *  0b1..Channel-to-channel linking enabled
28560  */
28561 #define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
28562 
28563 #define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
28564 #define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
28565 /*! EEOP - Enable End-Of-Packet Processing
28566  *  0b0..End-of-packet operation disabled
28567  *  0b1..End-of-packet hardware input signal enabled
28568  */
28569 #define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
28570 
28571 #define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
28572 #define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
28573 /*! ESDA - Enable Store Destination Address
28574  *  0b0..Ability to store destination address to system memory disabled
28575  *  0b1..Ability to store destination address to system memory enabled
28576  */
28577 #define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
28578 
28579 #define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x1F00U)
28580 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
28581 /*! MAJORLINKCH - Major Loop Link Channel Number */
28582 #define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
28583 
28584 #define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
28585 #define DMA_TCD_CSR_BWC_SHIFT                    (14U)
28586 /*! BWC - Bandwidth Control
28587  *  0b00..No eDMA engine stalls
28588  *  0b01..
28589  *  0b10..eDMA engine stalls for 4 cycles after each R/W
28590  *  0b11..eDMA engine stalls for 8 cycles after each R/W
28591  */
28592 #define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
28593 /*! @} */
28594 
28595 /* The count of DMA_TCD_CSR */
28596 #define DMA_TCD_CSR_COUNT                        (32U)
28597 
28598 /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
28599 /*! @{ */
28600 
28601 #define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
28602 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
28603 /*! BITER - Starting Major Iteration Count */
28604 #define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
28605 
28606 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
28607 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
28608 /*! ELINK - Enables Link
28609  *  0b0..Channel-to-channel linking disabled
28610  *  0b1..Channel-to-channel linking enabled
28611  */
28612 #define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
28613 /*! @} */
28614 
28615 /* The count of DMA_TCD_BITER_ELINKNO */
28616 #define DMA_TCD_BITER_ELINKNO_COUNT              (32U)
28617 
28618 /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
28619 /*! @{ */
28620 
28621 #define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
28622 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
28623 /*! BITER - Starting Major Iteration Count */
28624 #define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
28625 
28626 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x3E00U)
28627 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
28628 /*! LINKCH - Link Channel Number */
28629 #define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
28630 
28631 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
28632 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
28633 /*! ELINK - Enable Link
28634  *  0b0..Channel-to-channel linking disabled
28635  *  0b1..Channel-to-channel linking enabled
28636  */
28637 #define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
28638 /*! @} */
28639 
28640 /* The count of DMA_TCD_BITER_ELINKYES */
28641 #define DMA_TCD_BITER_ELINKYES_COUNT             (32U)
28642 
28643 
28644 /*!
28645  * @}
28646  */ /* end of group DMA_Register_Masks */
28647 
28648 
28649 /* DMA - Peripheral instance base addresses */
28650 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
28651   /** Peripheral DMA3 base address */
28652   #define DMA3_BASE                                (0x54000000u)
28653   /** Peripheral DMA3 base address */
28654   #define DMA3_BASE_NS                             (0x44000000u)
28655   /** Peripheral DMA3 base pointer */
28656   #define DMA3                                     ((DMA_Type *)DMA3_BASE)
28657   /** Peripheral DMA3 base pointer */
28658   #define DMA3_NS                                  ((DMA_Type *)DMA3_BASE_NS)
28659   /** Array initializer of DMA peripheral base addresses */
28660   #define DMA_BASE_ADDRS                           { DMA3_BASE }
28661   /** Array initializer of DMA peripheral base pointers */
28662   #define DMA_BASE_PTRS                            { DMA3 }
28663   /** Array initializer of DMA peripheral base addresses */
28664   #define DMA_BASE_ADDRS_NS                        { DMA3_BASE_NS }
28665   /** Array initializer of DMA peripheral base pointers */
28666   #define DMA_BASE_PTRS_NS                         { DMA3_NS }
28667 #else
28668   /** Peripheral DMA3 base address */
28669   #define DMA3_BASE                                (0x44000000u)
28670   /** Peripheral DMA3 base pointer */
28671   #define DMA3                                     ((DMA_Type *)DMA3_BASE)
28672   /** Array initializer of DMA peripheral base addresses */
28673   #define DMA_BASE_ADDRS                           { DMA3_BASE }
28674   /** Array initializer of DMA peripheral base pointers */
28675   #define DMA_BASE_PTRS                            { DMA3 }
28676 #endif
28677 /** Interrupt vectors for the DMA peripheral type */
28678 #define DMA_IRQS                                 { { DMA3_CH0_IRQn, DMA3_CH1_IRQn, DMA3_CH2_IRQn, DMA3_CH3_IRQn, DMA3_CH4_IRQn, DMA3_CH5_IRQn, DMA3_CH6_IRQn, DMA3_CH7_IRQn, DMA3_CH8_IRQn, DMA3_CH9_IRQn, DMA3_CH10_IRQn, DMA3_CH11_IRQn, DMA3_CH12_IRQn, DMA3_CH13_IRQn, DMA3_CH14_IRQn, DMA3_CH15_IRQn, DMA3_CH16_IRQn, DMA3_CH17_IRQn, DMA3_CH18_IRQn, DMA3_CH19_IRQn, DMA3_CH20_IRQn, DMA3_CH21_IRQn, DMA3_CH22_IRQn, DMA3_CH23_IRQn, DMA3_CH24_IRQn, DMA3_CH25_IRQn, DMA3_CH26_IRQn, DMA3_CH27_IRQn, DMA3_CH28_IRQn, DMA3_CH29_IRQn, DMA3_CH30_IRQn, DMA3_CH31_IRQn } }
28679 #define DMA_ERROR_IRQS                           { { DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn, DMA_ERROR_IRQn } }
28680 
28681 /*!
28682  * @}
28683  */ /* end of group DMA_Peripheral_Access_Layer */
28684 
28685 
28686 /* ----------------------------------------------------------------------------
28687    -- DMA4 Peripheral Access Layer
28688    ---------------------------------------------------------------------------- */
28689 
28690 /*!
28691  * @addtogroup DMA4_Peripheral_Access_Layer DMA4 Peripheral Access Layer
28692  * @{
28693  */
28694 
28695 /** DMA4 - Register Layout Typedef */
28696 typedef struct {
28697   __IO uint32_t MP_CSR;                            /**< Management Page Control Register, offset: 0x0 */
28698   __I  uint32_t MP_ES;                             /**< Management Page Error Status Register, offset: 0x4 */
28699   __I  uint32_t MP_INT_LOW;                        /**< Management Page Interrupt Request Status Register - Low, offset: 0x8 */
28700   __I  uint32_t MP_INT_HIGH;                       /**< Management Page Interrupt Request Status Register- High, offset: 0xC */
28701   __I  uint32_t MP_HRS_LOW;                        /**< Management Page Hardware Request Status Register - Low, offset: 0x10 */
28702   __I  uint32_t MP_HRS_HIGH;                       /**< Management Page Hardware Request Status Register - High, offset: 0x14 */
28703        uint8_t RESERVED_0[232];
28704   __IO uint32_t CH_GRPRI[64];                      /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */
28705        uint8_t RESERVED_1[65024];
28706   struct {                                         /* offset: 0x10000, array step: 0x8000 */
28707     __IO uint32_t CH_CSR;                            /**< Channel Control and Status Register, array offset: 0x10000, array step: 0x8000 */
28708     __IO uint32_t CH_ES;                             /**< Channel Error Status Register, array offset: 0x10004, array step: 0x8000 */
28709     __IO uint32_t CH_INT;                            /**< Channel Interrupt Status Register, array offset: 0x10008, array step: 0x8000 */
28710     __IO uint32_t CH_SBR;                            /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x8000 */
28711     __IO uint32_t CH_PRI;                            /**< Channel Priority Register, array offset: 0x10010, array step: 0x8000 */
28712     __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x8000 */
28713     __IO uint16_t CH_MATTR;                          /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
28714          uint8_t RESERVED_0[6];
28715     __IO uint32_t SADDR;                             /**< TCD Source Address Register, array offset: 0x10020, array step: 0x8000 */
28716     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset Register, array offset: 0x10024, array step: 0x8000 */
28717     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes Register, array offset: 0x10026, array step: 0x8000 */
28718     union {                                          /* offset: 0x10028, array step: 0x8000 */
28719       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x10028, array step: 0x8000 */
28720       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x10028, array step: 0x8000 */
28721     };
28722     __IO uint32_t SLAST_SDA;                         /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x1002C, array step: 0x8000 */
28723     __IO uint32_t DADDR;                             /**< TCD Destination Address Register, array offset: 0x10030, array step: 0x8000 */
28724     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset Register, array offset: 0x10034, array step: 0x8000 */
28725     union {                                          /* offset: 0x10036, array step: 0x8000 */
28726       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x10036, array step: 0x8000 */
28727       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x10036, array step: 0x8000 */
28728     };
28729     __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x10038, array step: 0x8000 */
28730     __IO uint16_t CSR;                               /**< TCD Control and Status Register, array offset: 0x1003C, array step: 0x8000 */
28731     union {                                          /* offset: 0x1003E, array step: 0x8000 */
28732       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x1003E, array step: 0x8000 */
28733       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x1003E, array step: 0x8000 */
28734     };
28735          uint8_t RESERVED_1[32704];
28736   } TCD[64];
28737 } DMA4_Type;
28738 
28739 /* ----------------------------------------------------------------------------
28740    -- DMA4 Register Masks
28741    ---------------------------------------------------------------------------- */
28742 
28743 /*!
28744  * @addtogroup DMA4_Register_Masks DMA4 Register Masks
28745  * @{
28746  */
28747 
28748 /*! @name MP_CSR - Management Page Control Register */
28749 /*! @{ */
28750 
28751 #define DMA4_MP_CSR_EDBG_MASK                    (0x2U)
28752 #define DMA4_MP_CSR_EDBG_SHIFT                   (1U)
28753 /*! EDBG - Enable Debug
28754  *  0b0..Debug mode is disabled.
28755  *  0b1..Debug mode is enabled.
28756  */
28757 #define DMA4_MP_CSR_EDBG(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_EDBG_SHIFT)) & DMA4_MP_CSR_EDBG_MASK)
28758 
28759 #define DMA4_MP_CSR_ERCA_MASK                    (0x4U)
28760 #define DMA4_MP_CSR_ERCA_SHIFT                   (2U)
28761 /*! ERCA - Enable Round Robin Channel Arbitration
28762  *  0b0..Round robin channel arbitration is disabled.
28763  *  0b1..Round robin channel arbitration is enabled.
28764  */
28765 #define DMA4_MP_CSR_ERCA(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_ERCA_SHIFT)) & DMA4_MP_CSR_ERCA_MASK)
28766 
28767 #define DMA4_MP_CSR_HAE_MASK                     (0x10U)
28768 #define DMA4_MP_CSR_HAE_SHIFT                    (4U)
28769 /*! HAE - Halt After Error
28770  *  0b0..Normal operation
28771  *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
28772  */
28773 #define DMA4_MP_CSR_HAE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_HAE_SHIFT)) & DMA4_MP_CSR_HAE_MASK)
28774 
28775 #define DMA4_MP_CSR_HALT_MASK                    (0x20U)
28776 #define DMA4_MP_CSR_HALT_SHIFT                   (5U)
28777 /*! HALT - Halt DMA Operations
28778  *  0b0..Normal operation
28779  *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
28780  */
28781 #define DMA4_MP_CSR_HALT(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_HALT_SHIFT)) & DMA4_MP_CSR_HALT_MASK)
28782 
28783 #define DMA4_MP_CSR_GCLC_MASK                    (0x40U)
28784 #define DMA4_MP_CSR_GCLC_SHIFT                   (6U)
28785 /*! GCLC - Global Channel Linking Control
28786  *  0b0..Channel linking is disabled for all channels.
28787  *  0b1..Channel linking is available and controlled by each channel's link settings.
28788  */
28789 #define DMA4_MP_CSR_GCLC(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_GCLC_SHIFT)) & DMA4_MP_CSR_GCLC_MASK)
28790 
28791 #define DMA4_MP_CSR_GMRC_MASK                    (0x80U)
28792 #define DMA4_MP_CSR_GMRC_SHIFT                   (7U)
28793 /*! GMRC - Global Master ID Replication Control
28794  *  0b0..Master ID replication is disabled for all channels.
28795  *  0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting.
28796  */
28797 #define DMA4_MP_CSR_GMRC(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_GMRC_SHIFT)) & DMA4_MP_CSR_GMRC_MASK)
28798 
28799 #define DMA4_MP_CSR_VER_MASK                     (0xFF0000U)
28800 #define DMA4_MP_CSR_VER_SHIFT                    (16U)
28801 /*! VER - eDMA version */
28802 #define DMA4_MP_CSR_VER(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_VER_SHIFT)) & DMA4_MP_CSR_VER_MASK)
28803 
28804 #define DMA4_MP_CSR_ACTIVE_ID_MASK               (0x3F000000U)
28805 #define DMA4_MP_CSR_ACTIVE_ID_SHIFT              (24U)
28806 /*! ACTIVE_ID - Active channel ID */
28807 #define DMA4_MP_CSR_ACTIVE_ID(x)                 (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_ACTIVE_ID_SHIFT)) & DMA4_MP_CSR_ACTIVE_ID_MASK)
28808 
28809 #define DMA4_MP_CSR_ACTIVE_MASK                  (0x80000000U)
28810 #define DMA4_MP_CSR_ACTIVE_SHIFT                 (31U)
28811 /*! ACTIVE - DMA Active Status
28812  *  0b0..eDMA is idle.
28813  *  0b1..eDMA is executing a channel.
28814  */
28815 #define DMA4_MP_CSR_ACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << DMA4_MP_CSR_ACTIVE_SHIFT)) & DMA4_MP_CSR_ACTIVE_MASK)
28816 /*! @} */
28817 
28818 /*! @name MP_ES - Management Page Error Status Register */
28819 /*! @{ */
28820 
28821 #define DMA4_MP_ES_DBE_MASK                      (0x1U)
28822 #define DMA4_MP_ES_DBE_SHIFT                     (0U)
28823 /*! DBE - Destination Bus Error
28824  *  0b0..No destination bus error
28825  *  0b1..The last recorded error was a bus error on a destination write
28826  */
28827 #define DMA4_MP_ES_DBE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_DBE_SHIFT)) & DMA4_MP_ES_DBE_MASK)
28828 
28829 #define DMA4_MP_ES_SBE_MASK                      (0x2U)
28830 #define DMA4_MP_ES_SBE_SHIFT                     (1U)
28831 /*! SBE - Source Bus Error
28832  *  0b0..No source bus error
28833  *  0b1..The last recorded error was a bus error on a source read
28834  */
28835 #define DMA4_MP_ES_SBE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_SBE_SHIFT)) & DMA4_MP_ES_SBE_MASK)
28836 
28837 #define DMA4_MP_ES_SGE_MASK                      (0x4U)
28838 #define DMA4_MP_ES_SGE_SHIFT                     (2U)
28839 /*! SGE - Scatter/Gather Configuration Error
28840  *  0b0..No scatter/gather configuration error
28841  *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
28842  *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
28843  *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
28844  */
28845 #define DMA4_MP_ES_SGE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_SGE_SHIFT)) & DMA4_MP_ES_SGE_MASK)
28846 
28847 #define DMA4_MP_ES_NCE_MASK                      (0x8U)
28848 #define DMA4_MP_ES_NCE_SHIFT                     (3U)
28849 /*! NCE - NBYTES/CITER Configuration Error
28850  *  0b0..No NBYTES/CITER configuration error
28851  *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
28852  */
28853 #define DMA4_MP_ES_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_NCE_SHIFT)) & DMA4_MP_ES_NCE_MASK)
28854 
28855 #define DMA4_MP_ES_DOE_MASK                      (0x10U)
28856 #define DMA4_MP_ES_DOE_SHIFT                     (4U)
28857 /*! DOE - Destination Offset Error
28858  *  0b0..No destination offset configuration error
28859  *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
28860  */
28861 #define DMA4_MP_ES_DOE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_DOE_SHIFT)) & DMA4_MP_ES_DOE_MASK)
28862 
28863 #define DMA4_MP_ES_DAE_MASK                      (0x20U)
28864 #define DMA4_MP_ES_DAE_SHIFT                     (5U)
28865 /*! DAE - Destination Address Error
28866  *  0b0..No destination address configuration error
28867  *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
28868  */
28869 #define DMA4_MP_ES_DAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_DAE_SHIFT)) & DMA4_MP_ES_DAE_MASK)
28870 
28871 #define DMA4_MP_ES_SOE_MASK                      (0x40U)
28872 #define DMA4_MP_ES_SOE_SHIFT                     (6U)
28873 /*! SOE - Source Offset Error
28874  *  0b0..No source offset configuration error
28875  *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
28876  */
28877 #define DMA4_MP_ES_SOE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_SOE_SHIFT)) & DMA4_MP_ES_SOE_MASK)
28878 
28879 #define DMA4_MP_ES_SAE_MASK                      (0x80U)
28880 #define DMA4_MP_ES_SAE_SHIFT                     (7U)
28881 /*! SAE - Source Address Error
28882  *  0b0..No source address configuration error.
28883  *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
28884  */
28885 #define DMA4_MP_ES_SAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_SAE_SHIFT)) & DMA4_MP_ES_SAE_MASK)
28886 
28887 #define DMA4_MP_ES_ECX_MASK                      (0x100U)
28888 #define DMA4_MP_ES_ECX_SHIFT                     (8U)
28889 /*! ECX - Transfer Canceled
28890  *  0b0..No canceled transfers
28891  *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input.
28892  */
28893 #define DMA4_MP_ES_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_ECX_SHIFT)) & DMA4_MP_ES_ECX_MASK)
28894 
28895 #define DMA4_MP_ES_ERRCHN_MASK                   (0x3F000000U)
28896 #define DMA4_MP_ES_ERRCHN_SHIFT                  (24U)
28897 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
28898 #define DMA4_MP_ES_ERRCHN(x)                     (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_ERRCHN_SHIFT)) & DMA4_MP_ES_ERRCHN_MASK)
28899 
28900 #define DMA4_MP_ES_VLD_MASK                      (0x80000000U)
28901 #define DMA4_MP_ES_VLD_SHIFT                     (31U)
28902 /*! VLD - Valid
28903  *  0b0..No ERR bits are set.
28904  *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
28905  */
28906 #define DMA4_MP_ES_VLD(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_MP_ES_VLD_SHIFT)) & DMA4_MP_ES_VLD_MASK)
28907 /*! @} */
28908 
28909 /*! @name MP_INT_LOW - Management Page Interrupt Request Status Register - Low */
28910 /*! @{ */
28911 
28912 #define DMA4_MP_INT_LOW_INT_MASK                 (0xFFFFFFFFU)
28913 #define DMA4_MP_INT_LOW_INT_SHIFT                (0U)
28914 /*! INT - Interrupt Request Status for channels 31 - 0 */
28915 #define DMA4_MP_INT_LOW_INT(x)                   (((uint32_t)(((uint32_t)(x)) << DMA4_MP_INT_LOW_INT_SHIFT)) & DMA4_MP_INT_LOW_INT_MASK)
28916 /*! @} */
28917 
28918 /*! @name MP_INT_HIGH - Management Page Interrupt Request Status Register- High */
28919 /*! @{ */
28920 
28921 #define DMA4_MP_INT_HIGH_INT_MASK                (0xFFFFFFFFU)
28922 #define DMA4_MP_INT_HIGH_INT_SHIFT               (0U)
28923 /*! INT - Interrupt Request Status for channels 63-32 */
28924 #define DMA4_MP_INT_HIGH_INT(x)                  (((uint32_t)(((uint32_t)(x)) << DMA4_MP_INT_HIGH_INT_SHIFT)) & DMA4_MP_INT_HIGH_INT_MASK)
28925 /*! @} */
28926 
28927 /*! @name MP_HRS_LOW - Management Page Hardware Request Status Register - Low */
28928 /*! @{ */
28929 
28930 #define DMA4_MP_HRS_LOW_HRS_MASK                 (0xFFFFFFFFU)
28931 #define DMA4_MP_HRS_LOW_HRS_SHIFT                (0U)
28932 /*! HRS - Hardware Request Status for channels 31 - 0
28933  *  0b00000000000000000000000000000000..A hardware service request for the channel is not present
28934  *  0b00000000000000000000000000000001..A hardware service request for channel 0 is present
28935  */
28936 #define DMA4_MP_HRS_LOW_HRS(x)                   (((uint32_t)(((uint32_t)(x)) << DMA4_MP_HRS_LOW_HRS_SHIFT)) & DMA4_MP_HRS_LOW_HRS_MASK)
28937 /*! @} */
28938 
28939 /*! @name MP_HRS_HIGH - Management Page Hardware Request Status Register - High */
28940 /*! @{ */
28941 
28942 #define DMA4_MP_HRS_HIGH_HRS_MASK                (0xFFFFFFFFU)
28943 #define DMA4_MP_HRS_HIGH_HRS_SHIFT               (0U)
28944 /*! HRS - Hardware Request Status for channels 63-32
28945  *  0b00000000000000000000000000000000..A hardware service request for the channel is not present
28946  *  0b00000000000000000000000000000001..A hardware service request for channel 0 is present
28947  */
28948 #define DMA4_MP_HRS_HIGH_HRS(x)                  (((uint32_t)(((uint32_t)(x)) << DMA4_MP_HRS_HIGH_HRS_SHIFT)) & DMA4_MP_HRS_HIGH_HRS_MASK)
28949 /*! @} */
28950 
28951 /*! @name CH_GRPRI - Channel Arbitration Group Register */
28952 /*! @{ */
28953 
28954 #define DMA4_CH_GRPRI_GRPRI_MASK                 (0x3FU)
28955 #define DMA4_CH_GRPRI_GRPRI_SHIFT                (0U)
28956 /*! GRPRI - Arbitration group per channel. */
28957 #define DMA4_CH_GRPRI_GRPRI(x)                   (((uint32_t)(((uint32_t)(x)) << DMA4_CH_GRPRI_GRPRI_SHIFT)) & DMA4_CH_GRPRI_GRPRI_MASK)
28958 /*! @} */
28959 
28960 /* The count of DMA4_CH_GRPRI */
28961 #define DMA4_CH_GRPRI_COUNT                      (64U)
28962 
28963 /*! @name CH_CSR - Channel Control and Status Register */
28964 /*! @{ */
28965 
28966 #define DMA4_CH_CSR_ERQ_MASK                     (0x1U)
28967 #define DMA4_CH_CSR_ERQ_SHIFT                    (0U)
28968 /*! ERQ - Enable DMA Request
28969  *  0b0..The DMA hardware request signal for the corresponding channel is disabled.
28970  *  0b1..The DMA hardware request signal for the corresponding channel is enabled.
28971  */
28972 #define DMA4_CH_CSR_ERQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_ERQ_SHIFT)) & DMA4_CH_CSR_ERQ_MASK)
28973 
28974 #define DMA4_CH_CSR_EARQ_MASK                    (0x2U)
28975 #define DMA4_CH_CSR_EARQ_SHIFT                   (1U)
28976 /*! EARQ - Enable Asynchronous DMA Request
28977  *  0b0..Disable asynchronous DMA request for the channel.
28978  *  0b1..Enable asynchronous DMA request for the channel.
28979  */
28980 #define DMA4_CH_CSR_EARQ(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_EARQ_SHIFT)) & DMA4_CH_CSR_EARQ_MASK)
28981 
28982 #define DMA4_CH_CSR_EEI_MASK                     (0x4U)
28983 #define DMA4_CH_CSR_EEI_SHIFT                    (2U)
28984 /*! EEI - Enable Error Interrupt
28985  *  0b0..The error signal for corresponding channel does not generate an error interrupt
28986  *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
28987  */
28988 #define DMA4_CH_CSR_EEI(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_EEI_SHIFT)) & DMA4_CH_CSR_EEI_MASK)
28989 
28990 #define DMA4_CH_CSR_SWAP_MASK                    (0xF000U)
28991 #define DMA4_CH_CSR_SWAP_SHIFT                   (12U)
28992 /*! SWAP - Swap size
28993  *  0b0000..disabled
28994  *  0b0001..read with 8-bit swap
28995  *  0b0010..read with 16-bit swap
28996  *  0b0011..read with 32-bit swap
28997  *  0b0100-0b1000..reserved
28998  *  0b1001..write with 8-bit swap
28999  *  0b1010..write with 16-bit swap
29000  *  0b1011..write with 32-bit swap
29001  *  0b1100-0b1111..reserved
29002  */
29003 #define DMA4_CH_CSR_SWAP(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_SWAP_SHIFT)) & DMA4_CH_CSR_SWAP_MASK)
29004 
29005 #define DMA4_CH_CSR_SIGNEXT_MASK                 (0x3F0000U)
29006 #define DMA4_CH_CSR_SIGNEXT_SHIFT                (16U)
29007 /*! SIGNEXT - Sign Extension
29008  *  0b000000..disabled
29009  *  0b000001..A non-zero value specifying the sign extend bit position
29010  */
29011 #define DMA4_CH_CSR_SIGNEXT(x)                   (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_SIGNEXT_SHIFT)) & DMA4_CH_CSR_SIGNEXT_MASK)
29012 
29013 #define DMA4_CH_CSR_DONE_MASK                    (0x40000000U)
29014 #define DMA4_CH_CSR_DONE_SHIFT                   (30U)
29015 /*! DONE - Channel Done */
29016 #define DMA4_CH_CSR_DONE(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_DONE_SHIFT)) & DMA4_CH_CSR_DONE_MASK)
29017 
29018 #define DMA4_CH_CSR_ACTIVE_MASK                  (0x80000000U)
29019 #define DMA4_CH_CSR_ACTIVE_SHIFT                 (31U)
29020 /*! ACTIVE - Channel Active */
29021 #define DMA4_CH_CSR_ACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << DMA4_CH_CSR_ACTIVE_SHIFT)) & DMA4_CH_CSR_ACTIVE_MASK)
29022 /*! @} */
29023 
29024 /* The count of DMA4_CH_CSR */
29025 #define DMA4_CH_CSR_COUNT                        (64U)
29026 
29027 /*! @name CH_ES - Channel Error Status Register */
29028 /*! @{ */
29029 
29030 #define DMA4_CH_ES_DBE_MASK                      (0x1U)
29031 #define DMA4_CH_ES_DBE_SHIFT                     (0U)
29032 /*! DBE - Destination Bus Error
29033  *  0b0..No destination bus error
29034  *  0b1..The last recorded error was a bus error on a destination write
29035  */
29036 #define DMA4_CH_ES_DBE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_DBE_SHIFT)) & DMA4_CH_ES_DBE_MASK)
29037 
29038 #define DMA4_CH_ES_SBE_MASK                      (0x2U)
29039 #define DMA4_CH_ES_SBE_SHIFT                     (1U)
29040 /*! SBE - Source Bus Error
29041  *  0b0..No source bus error
29042  *  0b1..The last recorded error was a bus error on a source read
29043  */
29044 #define DMA4_CH_ES_SBE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_SBE_SHIFT)) & DMA4_CH_ES_SBE_MASK)
29045 
29046 #define DMA4_CH_ES_SGE_MASK                      (0x4U)
29047 #define DMA4_CH_ES_SGE_SHIFT                     (2U)
29048 /*! SGE - Scatter/Gather Configuration Error
29049  *  0b0..No scatter/gather configuration error
29050  *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
29051  *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
29052  *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
29053  */
29054 #define DMA4_CH_ES_SGE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_SGE_SHIFT)) & DMA4_CH_ES_SGE_MASK)
29055 
29056 #define DMA4_CH_ES_NCE_MASK                      (0x8U)
29057 #define DMA4_CH_ES_NCE_SHIFT                     (3U)
29058 /*! NCE - NBYTES/CITER Configuration Error
29059  *  0b0..No NBYTES/CITER configuration error
29060  *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
29061  *       TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
29062  *       or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
29063  */
29064 #define DMA4_CH_ES_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_NCE_SHIFT)) & DMA4_CH_ES_NCE_MASK)
29065 
29066 #define DMA4_CH_ES_DOE_MASK                      (0x10U)
29067 #define DMA4_CH_ES_DOE_SHIFT                     (4U)
29068 /*! DOE - Destination Offset Error
29069  *  0b0..No destination offset configuration error
29070  *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
29071  */
29072 #define DMA4_CH_ES_DOE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_DOE_SHIFT)) & DMA4_CH_ES_DOE_MASK)
29073 
29074 #define DMA4_CH_ES_DAE_MASK                      (0x20U)
29075 #define DMA4_CH_ES_DAE_SHIFT                     (5U)
29076 /*! DAE - Destination Address Error
29077  *  0b0..No destination address configuration error
29078  *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
29079  */
29080 #define DMA4_CH_ES_DAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_DAE_SHIFT)) & DMA4_CH_ES_DAE_MASK)
29081 
29082 #define DMA4_CH_ES_SOE_MASK                      (0x40U)
29083 #define DMA4_CH_ES_SOE_SHIFT                     (6U)
29084 /*! SOE - Source Offset Error
29085  *  0b0..No source offset configuration error
29086  *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
29087  */
29088 #define DMA4_CH_ES_SOE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_SOE_SHIFT)) & DMA4_CH_ES_SOE_MASK)
29089 
29090 #define DMA4_CH_ES_SAE_MASK                      (0x80U)
29091 #define DMA4_CH_ES_SAE_SHIFT                     (7U)
29092 /*! SAE - Source Address Error
29093  *  0b0..No source address configuration error.
29094  *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
29095  */
29096 #define DMA4_CH_ES_SAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_SAE_SHIFT)) & DMA4_CH_ES_SAE_MASK)
29097 
29098 #define DMA4_CH_ES_ERR_MASK                      (0x80000000U)
29099 #define DMA4_CH_ES_ERR_SHIFT                     (31U)
29100 /*! ERR - Error In Channel
29101  *  0b0..An error in this channel has not occurred
29102  *  0b1..An error in this channel has occurred
29103  */
29104 #define DMA4_CH_ES_ERR(x)                        (((uint32_t)(((uint32_t)(x)) << DMA4_CH_ES_ERR_SHIFT)) & DMA4_CH_ES_ERR_MASK)
29105 /*! @} */
29106 
29107 /* The count of DMA4_CH_ES */
29108 #define DMA4_CH_ES_COUNT                         (64U)
29109 
29110 /*! @name CH_INT - Channel Interrupt Status Register */
29111 /*! @{ */
29112 
29113 #define DMA4_CH_INT_INT_MASK                     (0x1U)
29114 #define DMA4_CH_INT_INT_SHIFT                    (0U)
29115 /*! INT - Interrupt Request
29116  *  0b0..The interrupt request for corresponding channel is cleared
29117  *  0b1..The interrupt request for corresponding channel is active
29118  */
29119 #define DMA4_CH_INT_INT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_INT_INT_SHIFT)) & DMA4_CH_INT_INT_MASK)
29120 /*! @} */
29121 
29122 /* The count of DMA4_CH_INT */
29123 #define DMA4_CH_INT_COUNT                        (64U)
29124 
29125 /*! @name CH_SBR - Channel System Bus Register */
29126 /*! @{ */
29127 
29128 #define DMA4_CH_SBR_MID_MASK                     (0xFU)
29129 #define DMA4_CH_SBR_MID_SHIFT                    (0U)
29130 /*! MID - Master ID */
29131 #define DMA4_CH_SBR_MID(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_MID_SHIFT)) & DMA4_CH_SBR_MID_MASK)
29132 
29133 #define DMA4_CH_SBR_INSTR_MASK                   (0x2000U)
29134 #define DMA4_CH_SBR_INSTR_SHIFT                  (13U)
29135 /*! INSTR - Instruction/Data Access
29136  *  0b0..Data access for DMA transfers
29137  *  0b1..Instruction access for DMA transfers
29138  */
29139 #define DMA4_CH_SBR_INSTR(x)                     (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_INSTR_SHIFT)) & DMA4_CH_SBR_INSTR_MASK)
29140 
29141 #define DMA4_CH_SBR_SEC_MASK                     (0x4000U)
29142 #define DMA4_CH_SBR_SEC_SHIFT                    (14U)
29143 /*! SEC - Security Level
29144  *  0b0..Nonsecure protection level for DMA transfers
29145  *  0b1..Secure protection level for DMA transfers
29146  */
29147 #define DMA4_CH_SBR_SEC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_SEC_SHIFT)) & DMA4_CH_SBR_SEC_MASK)
29148 
29149 #define DMA4_CH_SBR_PAL_MASK                     (0x8000U)
29150 #define DMA4_CH_SBR_PAL_SHIFT                    (15U)
29151 /*! PAL - Privileged Access Level
29152  *  0b0..User protection level for DMA transfers
29153  *  0b1..Privileged protection level for DMA transfers
29154  */
29155 #define DMA4_CH_SBR_PAL(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_PAL_SHIFT)) & DMA4_CH_SBR_PAL_MASK)
29156 
29157 #define DMA4_CH_SBR_EMI_MASK                     (0x10000U)
29158 #define DMA4_CH_SBR_EMI_SHIFT                    (16U)
29159 /*! EMI - Enable Master ID replication
29160  *  0b0..Master ID replication is disabled
29161  *  0b1..Master ID replication is enabled
29162  */
29163 #define DMA4_CH_SBR_EMI(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_EMI_SHIFT)) & DMA4_CH_SBR_EMI_MASK)
29164 
29165 #define DMA4_CH_SBR_ATTR_MASK                    (0x7E0000U)
29166 #define DMA4_CH_SBR_ATTR_SHIFT                   (17U)
29167 /*! ATTR - Attribute Output */
29168 #define DMA4_CH_SBR_ATTR(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_CH_SBR_ATTR_SHIFT)) & DMA4_CH_SBR_ATTR_MASK)
29169 /*! @} */
29170 
29171 /* The count of DMA4_CH_SBR */
29172 #define DMA4_CH_SBR_COUNT                        (64U)
29173 
29174 /*! @name CH_PRI - Channel Priority Register */
29175 /*! @{ */
29176 
29177 #define DMA4_CH_PRI_APL_MASK                     (0x7U)
29178 #define DMA4_CH_PRI_APL_SHIFT                    (0U)
29179 /*! APL - Arbitration Priority Level */
29180 #define DMA4_CH_PRI_APL(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_PRI_APL_SHIFT)) & DMA4_CH_PRI_APL_MASK)
29181 
29182 #define DMA4_CH_PRI_DPA_MASK                     (0x40000000U)
29183 #define DMA4_CH_PRI_DPA_SHIFT                    (30U)
29184 /*! DPA - Disable Preempt Ability.
29185  *  0b0..The channel can suspend a lower priority channel.
29186  *  0b1..The channel cannot suspend any other channel, regardless of channel priority.
29187  */
29188 #define DMA4_CH_PRI_DPA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_PRI_DPA_SHIFT)) & DMA4_CH_PRI_DPA_MASK)
29189 
29190 #define DMA4_CH_PRI_ECP_MASK                     (0x80000000U)
29191 #define DMA4_CH_PRI_ECP_SHIFT                    (31U)
29192 /*! ECP - Enable Channel Preemption.
29193  *  0b0..The channel cannot be suspended by a higher priority channel's service request.
29194  *  0b1..The channel can be temporarily suspended by the service request of a higher priority channel.
29195  */
29196 #define DMA4_CH_PRI_ECP(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_PRI_ECP_SHIFT)) & DMA4_CH_PRI_ECP_MASK)
29197 /*! @} */
29198 
29199 /* The count of DMA4_CH_PRI */
29200 #define DMA4_CH_PRI_COUNT                        (64U)
29201 
29202 /*! @name CH_MUX - Channel Multiplexor Configuration */
29203 /*! @{ */
29204 
29205 #define DMA4_CH_MUX_SRC_MASK                     (0xFFU)
29206 #define DMA4_CH_MUX_SRC_SHIFT                    (0U)
29207 /*! SRC - Service Request Source */
29208 #define DMA4_CH_MUX_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA4_CH_MUX_SRC_SHIFT)) & DMA4_CH_MUX_SRC_MASK)
29209 /*! @} */
29210 
29211 /* The count of DMA4_CH_MUX */
29212 #define DMA4_CH_MUX_COUNT                        (64U)
29213 
29214 /*! @name CH_MATTR - Memory Attributes Register */
29215 /*! @{ */
29216 
29217 #define DMA4_CH_MATTR_RCACHE_MASK                (0xFU)
29218 #define DMA4_CH_MATTR_RCACHE_SHIFT               (0U)
29219 /*! RCACHE - Read Cache Attributes */
29220 #define DMA4_CH_MATTR_RCACHE(x)                  (((uint16_t)(((uint16_t)(x)) << DMA4_CH_MATTR_RCACHE_SHIFT)) & DMA4_CH_MATTR_RCACHE_MASK)
29221 
29222 #define DMA4_CH_MATTR_WCACHE_MASK                (0xF0U)
29223 #define DMA4_CH_MATTR_WCACHE_SHIFT               (4U)
29224 /*! WCACHE - Write Cache Attributes */
29225 #define DMA4_CH_MATTR_WCACHE(x)                  (((uint16_t)(((uint16_t)(x)) << DMA4_CH_MATTR_WCACHE_SHIFT)) & DMA4_CH_MATTR_WCACHE_MASK)
29226 /*! @} */
29227 
29228 /* The count of DMA4_CH_MATTR */
29229 #define DMA4_CH_MATTR_COUNT                      (64U)
29230 
29231 /*! @name SADDR - TCD Source Address Register */
29232 /*! @{ */
29233 
29234 #define DMA4_SADDR_SADDR_MASK                    (0xFFFFFFFFU)
29235 #define DMA4_SADDR_SADDR_SHIFT                   (0U)
29236 /*! SADDR - Source Address */
29237 #define DMA4_SADDR_SADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_SADDR_SADDR_SHIFT)) & DMA4_SADDR_SADDR_MASK)
29238 /*! @} */
29239 
29240 /* The count of DMA4_SADDR */
29241 #define DMA4_SADDR_COUNT                         (64U)
29242 
29243 /*! @name SOFF - TCD Signed Source Address Offset Register */
29244 /*! @{ */
29245 
29246 #define DMA4_SOFF_SOFF_MASK                      (0xFFFFU)
29247 #define DMA4_SOFF_SOFF_SHIFT                     (0U)
29248 /*! SOFF - Source address signed offset */
29249 #define DMA4_SOFF_SOFF(x)                        (((uint16_t)(((uint16_t)(x)) << DMA4_SOFF_SOFF_SHIFT)) & DMA4_SOFF_SOFF_MASK)
29250 /*! @} */
29251 
29252 /* The count of DMA4_SOFF */
29253 #define DMA4_SOFF_COUNT                          (64U)
29254 
29255 /*! @name ATTR - TCD Transfer Attributes Register */
29256 /*! @{ */
29257 
29258 #define DMA4_ATTR_DSIZE_MASK                     (0x7U)
29259 #define DMA4_ATTR_DSIZE_SHIFT                    (0U)
29260 /*! DSIZE - Destination data transfer size
29261  *  0b000..8-bit
29262  *  0b001..16-bit
29263  *  0b010..32-bit
29264  *  0b011..64-bit
29265  *  0b100..16-byte
29266  *  0b101..32-byte
29267  *  0b110..64-byte
29268  *  0b111..128-byte
29269  */
29270 #define DMA4_ATTR_DSIZE(x)                       (((uint16_t)(((uint16_t)(x)) << DMA4_ATTR_DSIZE_SHIFT)) & DMA4_ATTR_DSIZE_MASK)
29271 
29272 #define DMA4_ATTR_DMOD_MASK                      (0xF8U)
29273 #define DMA4_ATTR_DMOD_SHIFT                     (3U)
29274 /*! DMOD - Destination address modulo */
29275 #define DMA4_ATTR_DMOD(x)                        (((uint16_t)(((uint16_t)(x)) << DMA4_ATTR_DMOD_SHIFT)) & DMA4_ATTR_DMOD_MASK)
29276 
29277 #define DMA4_ATTR_SSIZE_MASK                     (0x700U)
29278 #define DMA4_ATTR_SSIZE_SHIFT                    (8U)
29279 /*! SSIZE - Source data transfer size
29280  *  0b000..8-bit
29281  *  0b001..16-bit
29282  *  0b010..32-bit
29283  *  0b011..64-bit
29284  *  0b100..16-byte
29285  *  0b101..32-byte
29286  *  0b110..64-byte
29287  *  0b111..128-byte
29288  */
29289 #define DMA4_ATTR_SSIZE(x)                       (((uint16_t)(((uint16_t)(x)) << DMA4_ATTR_SSIZE_SHIFT)) & DMA4_ATTR_SSIZE_MASK)
29290 
29291 #define DMA4_ATTR_SMOD_MASK                      (0xF800U)
29292 #define DMA4_ATTR_SMOD_SHIFT                     (11U)
29293 /*! SMOD - Source address modulo
29294  *  0b00000..Source address modulo feature is disabled
29295  *  0b00001..Source address modulo feature is enabled for any non-zero value [1-31]
29296  */
29297 #define DMA4_ATTR_SMOD(x)                        (((uint16_t)(((uint16_t)(x)) << DMA4_ATTR_SMOD_SHIFT)) & DMA4_ATTR_SMOD_MASK)
29298 /*! @} */
29299 
29300 /* The count of DMA4_ATTR */
29301 #define DMA4_ATTR_COUNT                          (64U)
29302 
29303 /*! @name NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */
29304 /*! @{ */
29305 
29306 #define DMA4_NBYTES_MLOFFNO_NBYTES_MASK          (0x3FFFFFFFU)
29307 #define DMA4_NBYTES_MLOFFNO_NBYTES_SHIFT         (0U)
29308 /*! NBYTES - Number of Bytes to transfer per service request */
29309 #define DMA4_NBYTES_MLOFFNO_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA4_NBYTES_MLOFFNO_NBYTES_MASK)
29310 
29311 #define DMA4_NBYTES_MLOFFNO_DMLOE_MASK           (0x40000000U)
29312 #define DMA4_NBYTES_MLOFFNO_DMLOE_SHIFT          (30U)
29313 /*! DMLOE - Destination Minor Loop Offset Enable
29314  *  0b0..The minor loop offset is not applied to the DADDR
29315  *  0b1..The minor loop offset is applied to the DADDR
29316  */
29317 #define DMA4_NBYTES_MLOFFNO_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA4_NBYTES_MLOFFNO_DMLOE_MASK)
29318 
29319 #define DMA4_NBYTES_MLOFFNO_SMLOE_MASK           (0x80000000U)
29320 #define DMA4_NBYTES_MLOFFNO_SMLOE_SHIFT          (31U)
29321 /*! SMLOE - Source Minor Loop Offset Enable
29322  *  0b0..The minor loop offset is not applied to the SADDR
29323  *  0b1..The minor loop offset is applied to the SADDR
29324  */
29325 #define DMA4_NBYTES_MLOFFNO_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA4_NBYTES_MLOFFNO_SMLOE_MASK)
29326 /*! @} */
29327 
29328 /* The count of DMA4_NBYTES_MLOFFNO */
29329 #define DMA4_NBYTES_MLOFFNO_COUNT                (64U)
29330 
29331 /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */
29332 /*! @{ */
29333 
29334 #define DMA4_NBYTES_MLOFFYES_NBYTES_MASK         (0x3FFU)
29335 #define DMA4_NBYTES_MLOFFYES_NBYTES_SHIFT        (0U)
29336 /*! NBYTES - Number of Bytes to transfer per service request */
29337 #define DMA4_NBYTES_MLOFFYES_NBYTES(x)           (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA4_NBYTES_MLOFFYES_NBYTES_MASK)
29338 
29339 #define DMA4_NBYTES_MLOFFYES_MLOFF_MASK          (0x3FFFFC00U)
29340 #define DMA4_NBYTES_MLOFFYES_MLOFF_SHIFT         (10U)
29341 /*! MLOFF - Minor Loop Offset */
29342 #define DMA4_NBYTES_MLOFFYES_MLOFF(x)            (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA4_NBYTES_MLOFFYES_MLOFF_MASK)
29343 
29344 #define DMA4_NBYTES_MLOFFYES_DMLOE_MASK          (0x40000000U)
29345 #define DMA4_NBYTES_MLOFFYES_DMLOE_SHIFT         (30U)
29346 /*! DMLOE - Destination Minor Loop Offset Enable
29347  *  0b0..The minor loop offset is not applied to the DADDR
29348  *  0b1..The minor loop offset is applied to the DADDR
29349  */
29350 #define DMA4_NBYTES_MLOFFYES_DMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA4_NBYTES_MLOFFYES_DMLOE_MASK)
29351 
29352 #define DMA4_NBYTES_MLOFFYES_SMLOE_MASK          (0x80000000U)
29353 #define DMA4_NBYTES_MLOFFYES_SMLOE_SHIFT         (31U)
29354 /*! SMLOE - Source Minor Loop Offset Enable
29355  *  0b0..The minor loop offset is not applied to the SADDR
29356  *  0b1..The minor loop offset is applied to the SADDR
29357  */
29358 #define DMA4_NBYTES_MLOFFYES_SMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA4_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA4_NBYTES_MLOFFYES_SMLOE_MASK)
29359 /*! @} */
29360 
29361 /* The count of DMA4_NBYTES_MLOFFYES */
29362 #define DMA4_NBYTES_MLOFFYES_COUNT               (64U)
29363 
29364 /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */
29365 /*! @{ */
29366 
29367 #define DMA4_SLAST_SDA_SLAST_SDA_MASK            (0xFFFFFFFFU)
29368 #define DMA4_SLAST_SDA_SLAST_SDA_SHIFT           (0U)
29369 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
29370 #define DMA4_SLAST_SDA_SLAST_SDA(x)              (((uint32_t)(((uint32_t)(x)) << DMA4_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA4_SLAST_SDA_SLAST_SDA_MASK)
29371 /*! @} */
29372 
29373 /* The count of DMA4_SLAST_SDA */
29374 #define DMA4_SLAST_SDA_COUNT                     (64U)
29375 
29376 /*! @name DADDR - TCD Destination Address Register */
29377 /*! @{ */
29378 
29379 #define DMA4_DADDR_DADDR_MASK                    (0xFFFFFFFFU)
29380 #define DMA4_DADDR_DADDR_SHIFT                   (0U)
29381 /*! DADDR - Destination Address */
29382 #define DMA4_DADDR_DADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DMA4_DADDR_DADDR_SHIFT)) & DMA4_DADDR_DADDR_MASK)
29383 /*! @} */
29384 
29385 /* The count of DMA4_DADDR */
29386 #define DMA4_DADDR_COUNT                         (64U)
29387 
29388 /*! @name DOFF - TCD Signed Destination Address Offset Register */
29389 /*! @{ */
29390 
29391 #define DMA4_DOFF_DOFF_MASK                      (0xFFFFU)
29392 #define DMA4_DOFF_DOFF_SHIFT                     (0U)
29393 /*! DOFF - Destination Address Signed Offset */
29394 #define DMA4_DOFF_DOFF(x)                        (((uint16_t)(((uint16_t)(x)) << DMA4_DOFF_DOFF_SHIFT)) & DMA4_DOFF_DOFF_MASK)
29395 /*! @} */
29396 
29397 /* The count of DMA4_DOFF */
29398 #define DMA4_DOFF_COUNT                          (64U)
29399 
29400 /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */
29401 /*! @{ */
29402 
29403 #define DMA4_CITER_ELINKNO_CITER_MASK            (0x7FFFU)
29404 #define DMA4_CITER_ELINKNO_CITER_SHIFT           (0U)
29405 /*! CITER - Current Major Iteration Count */
29406 #define DMA4_CITER_ELINKNO_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA4_CITER_ELINKNO_CITER_SHIFT)) & DMA4_CITER_ELINKNO_CITER_MASK)
29407 
29408 #define DMA4_CITER_ELINKNO_ELINK_MASK            (0x8000U)
29409 #define DMA4_CITER_ELINKNO_ELINK_SHIFT           (15U)
29410 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
29411  *  0b0..The channel-to-channel linking is disabled
29412  *  0b1..The channel-to-channel linking is enabled
29413  */
29414 #define DMA4_CITER_ELINKNO_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA4_CITER_ELINKNO_ELINK_SHIFT)) & DMA4_CITER_ELINKNO_ELINK_MASK)
29415 /*! @} */
29416 
29417 /* The count of DMA4_CITER_ELINKNO */
29418 #define DMA4_CITER_ELINKNO_COUNT                 (64U)
29419 
29420 /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */
29421 /*! @{ */
29422 
29423 #define DMA4_CITER_ELINKYES_CITER_MASK           (0x1FFU)
29424 #define DMA4_CITER_ELINKYES_CITER_SHIFT          (0U)
29425 /*! CITER - Current Major Iteration Count */
29426 #define DMA4_CITER_ELINKYES_CITER(x)             (((uint16_t)(((uint16_t)(x)) << DMA4_CITER_ELINKYES_CITER_SHIFT)) & DMA4_CITER_ELINKYES_CITER_MASK)
29427 
29428 #define DMA4_CITER_ELINKYES_LINKCH_MASK          (0x7E00U)
29429 #define DMA4_CITER_ELINKYES_LINKCH_SHIFT         (9U)
29430 /*! LINKCH - Minor Loop Link Channel Number */
29431 #define DMA4_CITER_ELINKYES_LINKCH(x)            (((uint16_t)(((uint16_t)(x)) << DMA4_CITER_ELINKYES_LINKCH_SHIFT)) & DMA4_CITER_ELINKYES_LINKCH_MASK)
29432 
29433 #define DMA4_CITER_ELINKYES_ELINK_MASK           (0x8000U)
29434 #define DMA4_CITER_ELINKYES_ELINK_SHIFT          (15U)
29435 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
29436  *  0b0..The channel-to-channel linking is disabled
29437  *  0b1..The channel-to-channel linking is enabled
29438  */
29439 #define DMA4_CITER_ELINKYES_ELINK(x)             (((uint16_t)(((uint16_t)(x)) << DMA4_CITER_ELINKYES_ELINK_SHIFT)) & DMA4_CITER_ELINKYES_ELINK_MASK)
29440 /*! @} */
29441 
29442 /* The count of DMA4_CITER_ELINKYES */
29443 #define DMA4_CITER_ELINKYES_COUNT                (64U)
29444 
29445 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */
29446 /*! @{ */
29447 
29448 #define DMA4_DLAST_SGA_DLAST_SGA_MASK            (0xFFFFFFFFU)
29449 #define DMA4_DLAST_SGA_DLAST_SGA_SHIFT           (0U)
29450 /*! DLAST_SGA - Final Destination Address Adjustment / Scatter Gather Address */
29451 #define DMA4_DLAST_SGA_DLAST_SGA(x)              (((uint32_t)(((uint32_t)(x)) << DMA4_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA4_DLAST_SGA_DLAST_SGA_MASK)
29452 /*! @} */
29453 
29454 /* The count of DMA4_DLAST_SGA */
29455 #define DMA4_DLAST_SGA_COUNT                     (64U)
29456 
29457 /*! @name CSR - TCD Control and Status Register */
29458 /*! @{ */
29459 
29460 #define DMA4_CSR_START_MASK                      (0x1U)
29461 #define DMA4_CSR_START_SHIFT                     (0U)
29462 /*! START - Channel Start
29463  *  0b0..The channel is not explicitly started.
29464  *  0b1..The channel is explicitly started via a software initiated service request.
29465  */
29466 #define DMA4_CSR_START(x)                        (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_START_SHIFT)) & DMA4_CSR_START_MASK)
29467 
29468 #define DMA4_CSR_INTMAJOR_MASK                   (0x2U)
29469 #define DMA4_CSR_INTMAJOR_SHIFT                  (1U)
29470 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
29471  *  0b0..The end-of-major loop interrupt is disabled.
29472  *  0b1..The end-of-major loop interrupt is enabled.
29473  */
29474 #define DMA4_CSR_INTMAJOR(x)                     (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_INTMAJOR_SHIFT)) & DMA4_CSR_INTMAJOR_MASK)
29475 
29476 #define DMA4_CSR_INTHALF_MASK                    (0x4U)
29477 #define DMA4_CSR_INTHALF_SHIFT                   (2U)
29478 /*! INTHALF - Enable an interrupt when major counter is half complete.
29479  *  0b0..The half-point interrupt is disabled.
29480  *  0b1..The half-point interrupt is enabled.
29481  */
29482 #define DMA4_CSR_INTHALF(x)                      (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_INTHALF_SHIFT)) & DMA4_CSR_INTHALF_MASK)
29483 
29484 #define DMA4_CSR_DREQ_MASK                       (0x8U)
29485 #define DMA4_CSR_DREQ_SHIFT                      (3U)
29486 /*! DREQ - Disable request
29487  *  0b0..No operation
29488  *  0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests.
29489  */
29490 #define DMA4_CSR_DREQ(x)                         (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_DREQ_SHIFT)) & DMA4_CSR_DREQ_MASK)
29491 
29492 #define DMA4_CSR_ESG_MASK                        (0x10U)
29493 #define DMA4_CSR_ESG_SHIFT                       (4U)
29494 /*! ESG - Enable Scatter/Gather processing
29495  *  0b0..The current channel's TCD is normal format.
29496  *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
29497  *       to the next TCD to be loaded into this channel after the major loop completes its execution.
29498  */
29499 #define DMA4_CSR_ESG(x)                          (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_ESG_SHIFT)) & DMA4_CSR_ESG_MASK)
29500 
29501 #define DMA4_CSR_MAJORELINK_MASK                 (0x20U)
29502 #define DMA4_CSR_MAJORELINK_SHIFT                (5U)
29503 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
29504  *  0b0..The channel-to-channel linking is disabled.
29505  *  0b1..The channel-to-channel linking is enabled.
29506  */
29507 #define DMA4_CSR_MAJORELINK(x)                   (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_MAJORELINK_SHIFT)) & DMA4_CSR_MAJORELINK_MASK)
29508 
29509 #define DMA4_CSR_EEOP_MASK                       (0x40U)
29510 #define DMA4_CSR_EEOP_SHIFT                      (6U)
29511 /*! EEOP - Enable end-of-packet processing
29512  *  0b0..The end-of-packet operation is disabled.
29513  *  0b1..The end-of-packet hardware input signal is enabled.
29514  */
29515 #define DMA4_CSR_EEOP(x)                         (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_EEOP_SHIFT)) & DMA4_CSR_EEOP_MASK)
29516 
29517 #define DMA4_CSR_ESDA_MASK                       (0x80U)
29518 #define DMA4_CSR_ESDA_SHIFT                      (7U)
29519 /*! ESDA - Enable store destination address
29520  *  0b0..The store destination address to system memory operation is disabled.
29521  *  0b1..The store destination address to system memory operation is enabled.
29522  */
29523 #define DMA4_CSR_ESDA(x)                         (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_ESDA_SHIFT)) & DMA4_CSR_ESDA_MASK)
29524 
29525 #define DMA4_CSR_MAJORLINKCH_MASK                (0x3F00U)
29526 #define DMA4_CSR_MAJORLINKCH_SHIFT               (8U)
29527 /*! MAJORLINKCH - Major loop link channel number */
29528 #define DMA4_CSR_MAJORLINKCH(x)                  (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_MAJORLINKCH_SHIFT)) & DMA4_CSR_MAJORLINKCH_MASK)
29529 
29530 #define DMA4_CSR_TMC_MASK                        (0xC000U)
29531 #define DMA4_CSR_TMC_SHIFT                       (14U)
29532 /*! TMC - Transfer Mode Control
29533  *  0b00..Read/Write
29534  *  0b01..Read Only
29535  *  0b10..Write Only
29536  *  0b11..Reserved
29537  */
29538 #define DMA4_CSR_TMC(x)                          (((uint16_t)(((uint16_t)(x)) << DMA4_CSR_TMC_SHIFT)) & DMA4_CSR_TMC_MASK)
29539 /*! @} */
29540 
29541 /* The count of DMA4_CSR */
29542 #define DMA4_CSR_COUNT                           (64U)
29543 
29544 /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */
29545 /*! @{ */
29546 
29547 #define DMA4_BITER_ELINKNO_BITER_MASK            (0x7FFFU)
29548 #define DMA4_BITER_ELINKNO_BITER_SHIFT           (0U)
29549 /*! BITER - Starting Major Iteration Count */
29550 #define DMA4_BITER_ELINKNO_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA4_BITER_ELINKNO_BITER_SHIFT)) & DMA4_BITER_ELINKNO_BITER_MASK)
29551 
29552 #define DMA4_BITER_ELINKNO_ELINK_MASK            (0x8000U)
29553 #define DMA4_BITER_ELINKNO_ELINK_SHIFT           (15U)
29554 /*! ELINK - Enables channel-to-channel linking on minor loop complete
29555  *  0b0..The channel-to-channel linking is disabled
29556  *  0b1..The channel-to-channel linking is enabled
29557  */
29558 #define DMA4_BITER_ELINKNO_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA4_BITER_ELINKNO_ELINK_SHIFT)) & DMA4_BITER_ELINKNO_ELINK_MASK)
29559 /*! @} */
29560 
29561 /* The count of DMA4_BITER_ELINKNO */
29562 #define DMA4_BITER_ELINKNO_COUNT                 (64U)
29563 
29564 /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */
29565 /*! @{ */
29566 
29567 #define DMA4_BITER_ELINKYES_BITER_MASK           (0x1FFU)
29568 #define DMA4_BITER_ELINKYES_BITER_SHIFT          (0U)
29569 /*! BITER - Starting major iteration count */
29570 #define DMA4_BITER_ELINKYES_BITER(x)             (((uint16_t)(((uint16_t)(x)) << DMA4_BITER_ELINKYES_BITER_SHIFT)) & DMA4_BITER_ELINKYES_BITER_MASK)
29571 
29572 #define DMA4_BITER_ELINKYES_LINKCH_MASK          (0x7E00U)
29573 #define DMA4_BITER_ELINKYES_LINKCH_SHIFT         (9U)
29574 /*! LINKCH - Link Channel Number */
29575 #define DMA4_BITER_ELINKYES_LINKCH(x)            (((uint16_t)(((uint16_t)(x)) << DMA4_BITER_ELINKYES_LINKCH_SHIFT)) & DMA4_BITER_ELINKYES_LINKCH_MASK)
29576 
29577 #define DMA4_BITER_ELINKYES_ELINK_MASK           (0x8000U)
29578 #define DMA4_BITER_ELINKYES_ELINK_SHIFT          (15U)
29579 /*! ELINK - Enables channel-to-channel linking on minor loop complete
29580  *  0b0..The channel-to-channel linking is disabled
29581  *  0b1..The channel-to-channel linking is enabled
29582  */
29583 #define DMA4_BITER_ELINKYES_ELINK(x)             (((uint16_t)(((uint16_t)(x)) << DMA4_BITER_ELINKYES_ELINK_SHIFT)) & DMA4_BITER_ELINKYES_ELINK_MASK)
29584 /*! @} */
29585 
29586 /* The count of DMA4_BITER_ELINKYES */
29587 #define DMA4_BITER_ELINKYES_COUNT                (64U)
29588 
29589 
29590 /*!
29591  * @}
29592  */ /* end of group DMA4_Register_Masks */
29593 
29594 
29595 /* DMA4 - Peripheral instance base addresses */
29596 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
29597   /** Peripheral DMA4 base address */
29598   #define DMA4_BASE                                (0x52000000u)
29599   /** Peripheral DMA4 base address */
29600   #define DMA4_BASE_NS                             (0x42000000u)
29601   /** Peripheral DMA4 base pointer */
29602   #define DMA4                                     ((DMA4_Type *)DMA4_BASE)
29603   /** Peripheral DMA4 base pointer */
29604   #define DMA4_NS                                  ((DMA4_Type *)DMA4_BASE_NS)
29605   /** Array initializer of DMA4 peripheral base addresses */
29606   #define DMA4_BASE_ADDRS                          { DMA4_BASE }
29607   /** Array initializer of DMA4 peripheral base pointers */
29608   #define DMA4_BASE_PTRS                           { DMA4 }
29609   /** Array initializer of DMA4 peripheral base addresses */
29610   #define DMA4_BASE_ADDRS_NS                       { DMA4_BASE_NS }
29611   /** Array initializer of DMA4 peripheral base pointers */
29612   #define DMA4_BASE_PTRS_NS                        { DMA4_NS }
29613 #else
29614   /** Peripheral DMA4 base address */
29615   #define DMA4_BASE                                (0x42000000u)
29616   /** Peripheral DMA4 base pointer */
29617   #define DMA4                                     ((DMA4_Type *)DMA4_BASE)
29618   /** Array initializer of DMA4 peripheral base addresses */
29619   #define DMA4_BASE_ADDRS                          { DMA4_BASE }
29620   /** Array initializer of DMA4 peripheral base pointers */
29621   #define DMA4_BASE_PTRS                           { DMA4 }
29622 #endif
29623 /** Interrupt vectors for the DMA4 peripheral type */
29624 #define DMA4_IRQS                                { { DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH0_CH1_CH32_CH33_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH2_CH3_CH34_CH35_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH4_CH5_CH36_CH37_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH6_CH7_CH38_CH39_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH8_CH9_CH40_CH41_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH10_CH11_CH42_CH43_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH12_CH13_CH44_CH45_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH14_CH15_CH46_CH47_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH16_CH17_CH48_CH49_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH18_CH19_CH50_CH51_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH20_CH21_CH52_CH53_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH22_CH23_CH54_CH55_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH24_CH25_CH56_CH57_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH26_CH27_CH58_CH59_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH28_CH29_CH60_CH61_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn, DMA4_CH30_CH31_CH62_CH63_IRQn } }
29625 #define DMA4_ERROR_IRQS                          { { DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn, DMA4_ERROR_IRQn } }
29626 
29627 /*!
29628  * @}
29629  */ /* end of group DMA4_Peripheral_Access_Layer */
29630 
29631 
29632 /* ----------------------------------------------------------------------------
29633    -- ECAT Peripheral Access Layer
29634    ---------------------------------------------------------------------------- */
29635 
29636 /*!
29637  * @addtogroup ECAT_Peripheral_Access_Layer ECAT Peripheral Access Layer
29638  * @{
29639  */
29640 
29641 /** ECAT - Register Layout Typedef */
29642 typedef struct {
29643   __I  uint8_t TYPE;                               /**< Type, offset: 0x0 */
29644   __I  uint8_t REVISION;                           /**< Revision, offset: 0x1 */
29645   __I  uint16_t BUILD;                             /**< Build, offset: 0x2 */
29646   __I  uint8_t FMMUS_SUPPORTED;                    /**< FMMUs supported, offset: 0x4 */
29647   __I  uint8_t SYNCMANAGERS_SUPPORTED;             /**< SyncManagers supported, offset: 0x5 */
29648   __I  uint8_t RAM_SIZE;                           /**< RAM Size, offset: 0x6 */
29649   __I  uint8_t PORT_DESCRIPTOR;                    /**< Port configuration, offset: 0x7 */
29650   __I  uint16_t ESC_FEATURES_SUPPORTED;            /**< Register ESC Features supported, offset: 0x8 */
29651        uint8_t RESERVED_0[6];
29652   union {                                          /* offset: 0x10 */
29653     __IO uint16_t CONFIGURED_STATION_ADDRESS;        /**< Configured Station Address, offset: 0x10 */
29654     __I  uint16_t CONFIGURED_STATION_ADDRESS_PDI;    /**< Configured Station Address, offset: 0x10 */
29655   };
29656   union {                                          /* offset: 0x12 */
29657     __I  uint16_t CONFIGURED_STATION_ALIAS;          /**< Configured Station Alias, offset: 0x12 */
29658     __IO uint16_t CONFIGURED_STATION_ALIAS_PDI;      /**< Configured Station Alias, offset: 0x12 */
29659   };
29660        uint8_t RESERVED_1[12];
29661   union {                                          /* offset: 0x20 */
29662     __IO uint8_t REGISTER_WRITE_ENABLE;              /**< Register Write Enable, offset: 0x20 */
29663     __I  uint8_t REGISTER_WRITE_ENABLE_PDI;          /**< Register Write Enable, offset: 0x20 */
29664   };
29665   union {                                          /* offset: 0x21 */
29666     __IO uint8_t REGISTER_WRITE_PROTECTION;          /**< Register Write Protection, offset: 0x21 */
29667     __I  uint8_t REGISTER_WRITE_PROTECTION_PDI;      /**< Register Write Protection, offset: 0x21 */
29668   };
29669        uint8_t RESERVED_2[14];
29670   union {                                          /* offset: 0x30 */
29671     __IO uint8_t ESC_WRITE_ENABLE;                   /**< ESC Write Enable, offset: 0x30 */
29672     __I  uint8_t ESC_WRITE_ENABLE_PDI;               /**< ESC Write Enable, offset: 0x30 */
29673   };
29674   union {                                          /* offset: 0x31 */
29675     __IO uint8_t ESC_WRITE_PROTECTION;               /**< ESC Write Protection, offset: 0x31 */
29676     __I  uint8_t ESC_WRITE_PROTECTION_PDI;           /**< ESC Write Protection, offset: 0x31 */
29677   };
29678        uint8_t RESERVED_3[14];
29679   union {                                          /* offset: 0x40 */
29680     __IO uint8_t ESC_RESET_ECAT_WRITE;               /**< ESC Reset ECAT WRITE, offset: 0x40 */
29681     __I  uint8_t ESC_RESET_ECAT_WRITE_PDI;           /**< ESC Reset ECAT WRITE, offset: 0x40 */
29682   };
29683   union {                                          /* offset: 0x41 */
29684     __I  uint8_t ESC_RESET_PDI_WRITE;                /**< ESC Reset PDI WRITE, offset: 0x41 */
29685     __IO uint8_t ESC_RESET_PDI_WRITE_PDI;            /**< ESC Reset PDI WRITE, offset: 0x41 */
29686   };
29687        uint8_t RESERVED_4[190];
29688   union {                                          /* offset: 0x100 */
29689     __IO uint32_t ESC_DL_CONTROL;                    /**< ESC DL Control, offset: 0x100 */
29690     __I  uint32_t ESC_DL_CONTROL_PDI;                /**< ESC DL Control, offset: 0x100 */
29691   };
29692        uint8_t RESERVED_5[4];
29693   union {                                          /* offset: 0x108 */
29694     __IO uint16_t PHYSICAL_READ_WRITE_OFFSET;        /**< Physical Read Write Offset, offset: 0x108 */
29695     __I  uint16_t PHYSICAL_READ_WRITE_OFFSET_PDI;    /**< Physical Read Write Offset, offset: 0x108 */
29696   };
29697        uint8_t RESERVED_6[6];
29698   __I  uint16_t ESC_DL_STATUS;                     /**< ESC DL Status, offset: 0x110 */
29699        uint8_t RESERVED_7[14];
29700   union {                                          /* offset: 0x120 */
29701     __IO uint16_t AL_CONTROL;                        /**< AL Control, offset: 0x120 */
29702     __I  uint16_t AL_CONTROL_PDI;                    /**< AL Control, offset: 0x120 */
29703   };
29704        uint8_t RESERVED_8[14];
29705   union {                                          /* offset: 0x130 */
29706     __I  uint16_t AL_STATUS;                         /**< AL Status, offset: 0x130 */
29707     __IO uint16_t AL_STATUS_PDI;                     /**< AL Status, offset: 0x130 */
29708   };
29709        uint8_t RESERVED_9[2];
29710   union {                                          /* offset: 0x134 */
29711     __I  uint16_t AL_STATUS_CODE;                    /**< AL Status Code, offset: 0x134 */
29712     __IO uint16_t AL_STATUS_CODE_PDI;                /**< AL Status Code, offset: 0x134 */
29713   };
29714        uint8_t RESERVED_10[2];
29715   __IO uint8_t RUN_LED_OVERRIDE;                   /**< RUN LED Override, offset: 0x138 */
29716   __IO uint8_t ERR_LED_OVERRIDE;                   /**< ERR LED Override, offset: 0x139 */
29717        uint8_t RESERVED_11[6];
29718   __I  uint8_t PDI_CONTROL;                        /**< PDI Control, offset: 0x140 */
29719   __I  uint8_t ESC_CONFIGURATION;                  /**< ESC Configuration, offset: 0x141 */
29720        uint8_t RESERVED_12[12];
29721   __I  uint16_t PDI_INFORMATION;                   /**< PDI Information, offset: 0x14E */
29722   __I  uint8_t PDI_ON_CHIP_BUS_CONFIGURATION;      /**< Register PDI On-chip bus configuration, offset: 0x150 */
29723   __I  uint8_t SYNC_LATCH_1_AND_0_PDI_CONFIGURATION; /**< PDI Configuration Sync Latch 1 and 0 PDI Configuration, offset: 0x151 */
29724   __I  uint16_t PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION; /**< Register PDI On-chip bus extended configuration., offset: 0x152 */
29725        uint8_t RESERVED_13[172];
29726   union {                                          /* offset: 0x200 */
29727     __IO uint16_t ECAT_EVENT_MASK;                   /**< ECAT Event Mask, offset: 0x200 */
29728     __I  uint16_t ECAT_EVENT_MASK_PDI;               /**< ECAT Event Mask, offset: 0x200 */
29729   };
29730        uint8_t RESERVED_14[2];
29731   union {                                          /* offset: 0x204 */
29732     __I  uint32_t PDI_AL_EVENT_MASK;                 /**< PDI AL Event Mask, offset: 0x204 */
29733     __IO uint32_t PDI_AL_EVENT_MASK_PDI;             /**< PDI AL Event Mask, offset: 0x204 */
29734   };
29735        uint8_t RESERVED_15[8];
29736   __I  uint16_t ECAT_EVENT_REQUEST;                /**< ECAT Event Request, offset: 0x210 */
29737        uint8_t RESERVED_16[14];
29738   __I  uint32_t AL_EVENT_REQUEST;                  /**< AL Event request, offset: 0x220 */
29739        uint8_t RESERVED_17[220];
29740   union {                                          /* offset: 0x300, array step: 0x2 */
29741     __IO uint16_t RX_ERROR_COUNTER_PORT[2];          /**< RX Error Counter, array offset: 0x300, array step: 0x2 */
29742     __I  uint16_t RX_ERROR_COUNTER_PORT_PDI[2];      /**< RX Error Counter, array offset: 0x300, array step: 0x2 */
29743   };
29744        uint8_t RESERVED_18[4];
29745   union {                                          /* offset: 0x308, array step: 0x1 */
29746     __IO uint8_t FORWARDED_RX_ERROR_COUNTER_PORT[2];   /**< Forwarded RX Error Counter, array offset: 0x308, array step: 0x1 */
29747     __I  uint8_t FORWARDED_RX_ERROR_COUNTER_PORT_PDI[2];   /**< Forwarded RX Error Counter, array offset: 0x308, array step: 0x1 */
29748   };
29749        uint8_t RESERVED_19[2];
29750   union {                                          /* offset: 0x30C */
29751     __IO uint8_t ECAT_PROCESSING_UNIT_ERROR_COUNTER;   /**< ECAT Processing Unit Error Counter, offset: 0x30C */
29752     __I  uint8_t ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI;   /**< ECAT Processing Unit Error Counter, offset: 0x30C */
29753   };
29754   union {                                          /* offset: 0x30D */
29755     __IO uint8_t PDI_ERROR_COUNTER;                  /**< PDI Error counter, offset: 0x30D */
29756     __I  uint8_t PDI_ERROR_COUNTER_PDI;              /**< PDI Error counter, offset: 0x30D */
29757   };
29758   __I  uint8_t ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER; /**< ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_PDI_ERROR_CODE., offset: 0x30E */
29759        uint8_t RESERVED_20[1];
29760   union {                                          /* offset: 0x310, array step: 0x1 */
29761     __IO uint8_t LOST_LINK_COUNTER_PORT[2];          /**< Lost Link Counter, array offset: 0x310, array step: 0x1 */
29762     __I  uint8_t LOST_LINK_COUNTER_PORT_PDI[2];      /**< Lost Link Counter, array offset: 0x310, array step: 0x1 */
29763   };
29764        uint8_t RESERVED_21[238];
29765   union {                                          /* offset: 0x400 */
29766     __IO uint16_t WATCHDOG_DIVIDER;                  /**< Watchdog Divider, offset: 0x400 */
29767     __I  uint16_t WATCHDOG_DIVIDER_PDI;              /**< Watchdog Divider, offset: 0x400 */
29768   };
29769        uint8_t RESERVED_22[14];
29770   union {                                          /* offset: 0x410 */
29771     __IO uint16_t WATCHDOG_TIME_PDI;                 /**< Register Watchdog Time PDI, offset: 0x410 */
29772     __I  uint16_t WATCHDOG_TIME_PDI_PDI;             /**< Register Watchdog Time PDI, offset: 0x410 */
29773   };
29774        uint8_t RESERVED_23[14];
29775   union {                                          /* offset: 0x420 */
29776     __IO uint16_t WATCHDOG_TIME_PROCESS_DATA;        /**< Regsister Watchdog Time Process Data, offset: 0x420 */
29777     __I  uint16_t WATCHDOG_TIME_PROCESS_DATA_PDI;    /**< Regsister Watchdog Time Process Data, offset: 0x420 */
29778   };
29779        uint8_t RESERVED_24[30];
29780   __I  uint16_t WATCHDOG_STATUS_PROCESS_DATA;      /**< Watchdog Status Process Data, offset: 0x440 */
29781   union {                                          /* offset: 0x442 */
29782     __IO uint8_t WATCHDOG_COUNTER_PROCESS_DATA;      /**< Watchdog Counter Process Data, offset: 0x442 */
29783     __I  uint8_t WATCHDOG_COUNTER_PROCESS_DATA_PDI;   /**< Watchdog Counter Process Data, offset: 0x442 */
29784   };
29785   union {                                          /* offset: 0x443 */
29786     __IO uint8_t WATCHDOG_COUNTER_PDI;               /**< Watchdog Counter PDI, offset: 0x443 */
29787     __I  uint8_t WATCHDOG_COUNTER_PDI_PDI;           /**< Watchdog Counter PDI, offset: 0x443 */
29788   };
29789        uint8_t RESERVED_25[188];
29790   union {                                          /* offset: 0x500 */
29791     __IO uint8_t EEPROM_CONFIGURATION;               /**< EEPROM Configuration, offset: 0x500 */
29792     __I  uint8_t EEPROM_CONFIGURATION_PDI;           /**< EEPROM Configuration, offset: 0x500 */
29793   };
29794   union {                                          /* offset: 0x501 */
29795     __I  uint8_t REGISTER_EEPROM_PDI_ACCESS_STATE;   /**< EEPROM PDI Access State, offset: 0x501 */
29796     __IO uint8_t REGISTER_EEPROM_PDI_ACCESS_STATE_PDI;   /**< EEPROM PDI Access State, offset: 0x501 */
29797   };
29798   union {                                          /* offset: 0x502 */
29799     __IO uint16_t EEPROM_CONTROL_STATUS;             /**< Register EEPROM Control/Status, offset: 0x502 */
29800     __IO uint16_t EEPROM_CONTROL_STATUS_PDI;         /**< Register EEPROM Control/Status, offset: 0x502 */
29801   };
29802   __IO uint32_t EEPROM_ADDRESS;                    /**< EEPROM Address, offset: 0x504 */
29803   __IO uint64_t EEPROM_DATA;                       /**< EEPROM Data, offset: 0x508 */
29804   union {                                          /* offset: 0x510 */
29805     __IO uint16_t MII_MANAGEMENT_CONTROL_OR_STATUS;   /**< MII Management Control/Status, offset: 0x510 */
29806     __IO uint16_t MII_MANAGEMENT_CONTROL_OR_STATUS_PDI;   /**< MII Management Control/Status, offset: 0x510 */
29807   };
29808   __IO uint8_t PHY_ADDRESS;                        /**< PHY Address, offset: 0x512 */
29809   __IO uint8_t PHY_REGISTER_ADDRESS;               /**< PHY Register Address, offset: 0x513 */
29810   __IO uint16_t PHY_DATA;                          /**< PHY Data, offset: 0x514 */
29811   union {                                          /* offset: 0x516 */
29812     __IO uint8_t MII_MANAGEMENT_ECAT_ACCESS_STATE;   /**< MII Management ECAT Access State, offset: 0x516 */
29813     __I  uint8_t MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI;   /**< MII Management ECAT Access State, offset: 0x516 */
29814   };
29815   union {                                          /* offset: 0x517 */
29816     __IO uint8_t MII_MANAGEMENT_PDI_ACCESS_STATE;    /**< MII Management PDI Access State, offset: 0x517 */
29817     __IO uint8_t MII_MANAGEMENT_PDI_ACCESS_STATE_PDI;   /**< MII Management PDI Access State, offset: 0x517 */
29818   };
29819   __IO uint8_t PHY_PORT_STATUS[2];                 /**< PHY Port, array offset: 0x518, array step: 0x1 */
29820        uint8_t RESERVED_26[230];
29821   struct {                                         /* offset: 0x600, array step: 0x10 */
29822     union {                                          /* offset: 0x600, array step: 0x10 */
29823       __IO uint32_t LOGICAL_START_ADDRESS;             /**< Register Logical Start address FMMU, array offset: 0x600, array step: 0x10 */
29824       __I  uint32_t LOGICAL_START_ADDRESS_PDI;         /**< Register Logical Start address FMMU, array offset: 0x600, array step: 0x10 */
29825     };
29826     union {                                          /* offset: 0x604, array step: 0x10 */
29827       __IO uint16_t LENGTH;                            /**< Register Length FMMU, array offset: 0x604, array step: 0x10 */
29828       __I  uint16_t LENGTH_PDI;                        /**< Register Length FMMU, array offset: 0x604, array step: 0x10 */
29829     };
29830     union {                                          /* offset: 0x606, array step: 0x10 */
29831       __IO uint8_t LOGICAL_START_BIT;                  /**< Register Start bit FMMU y in logical address space, array offset: 0x606, array step: 0x10 */
29832       __I  uint8_t LOGICAL_START_BIT_PDI;              /**< Register Start bit FMMU y in logical address space, array offset: 0x606, array step: 0x10 */
29833     };
29834     union {                                          /* offset: 0x607, array step: 0x10 */
29835       __IO uint8_t LOGICAL_STOP_BIT;                   /**< Register Stop bit FMMU y in logical address space, array offset: 0x607, array step: 0x10 */
29836       __I  uint8_t LOGICAL_STOP_BIT_PDI;               /**< Register Stop bit FMMU y in logical address space, array offset: 0x607, array step: 0x10 */
29837     };
29838     union {                                          /* offset: 0x608, array step: 0x10 */
29839       __IO uint16_t PHYSICAL_START_ADDRESS;            /**< Register Physical Start address FMMU, array offset: 0x608, array step: 0x10 */
29840       __I  uint16_t PHYSICAL_START_ADDRESS_PDI;        /**< Register Physical Start address FMMU, array offset: 0x608, array step: 0x10 */
29841     };
29842     union {                                          /* offset: 0x60A, array step: 0x10 */
29843       __IO uint8_t PHYSICAL_START_BIT;                 /**< Register Physical Start bit FMMU, array offset: 0x60A, array step: 0x10 */
29844       __I  uint8_t PHYSICAL_START_BIT_PDI;             /**< Register Physical Start bit FMMU, array offset: 0x60A, array step: 0x10 */
29845     };
29846     union {                                          /* offset: 0x60B, array step: 0x10 */
29847       __IO uint8_t TYPE;                               /**< Register Type FMMU y, array offset: 0x60B, array step: 0x10 */
29848       __I  uint8_t TYPE_PDI;                           /**< Register Type FMMU y, array offset: 0x60B, array step: 0x10 */
29849     };
29850     union {                                          /* offset: 0x60C, array step: 0x10 */
29851       __IO uint8_t ACTIVATE;                           /**< Register Activate FMMU, array offset: 0x60C, array step: 0x10 */
29852       __I  uint8_t ACTIVATE_PDI;                       /**< Register Activate FMMU, array offset: 0x60C, array step: 0x10 */
29853     };
29854          uint8_t RESERVED_0[3];
29855   } FMMU[8];
29856        uint8_t RESERVED_27[384];
29857   struct {                                         /* offset: 0x800, array step: 0x8 */
29858     union {                                          /* offset: 0x800, array step: 0x8 */
29859       __IO uint16_t PHYSICAL_START_ADDRESS;            /**< Register physical Start Address SyncManager, array offset: 0x800, array step: 0x8 */
29860       __I  uint16_t PHYSICAL_START_ADDRESS_PDI;        /**< Register physical Start Address SyncManager, array offset: 0x800, array step: 0x8 */
29861     };
29862     union {                                          /* offset: 0x802, array step: 0x8 */
29863       __IO uint16_t LENGTH;                            /**< Register Length SyncManager, array offset: 0x802, array step: 0x8 */
29864       __I  uint16_t LENGTH_PDI;                        /**< Register Length SyncManager, array offset: 0x802, array step: 0x8 */
29865     };
29866     union {                                          /* offset: 0x804, array step: 0x8 */
29867       __IO uint8_t CONTROL_REGISTER;                   /**< Register Control Register SyncManager, array offset: 0x804, array step: 0x8 */
29868       __I  uint8_t CONTROL_REGISTER_PDI;               /**< Register Control Register SyncManager, array offset: 0x804, array step: 0x8 */
29869     };
29870     __I  uint8_t STATUS;                             /**< Register Status Register SyncManager, array offset: 0x805, array step: 0x8 */
29871     union {                                          /* offset: 0x806, array step: 0x8 */
29872       __IO uint8_t ACTIVATE;                           /**< Register Activate SyncManager, array offset: 0x806, array step: 0x8 */
29873       __I  uint8_t ACTIVATE_PDI;                       /**< Register Activate SyncManager, array offset: 0x806, array step: 0x8 */
29874     };
29875     union {                                          /* offset: 0x807, array step: 0x8 */
29876       __I  uint8_t PDI_CONTROL;                        /**< Register PDI Control SyncManager, array offset: 0x807, array step: 0x8 */
29877       __IO uint8_t PDI_CONTROL_PDI;                    /**< Register PDI Control SyncManager, array offset: 0x807, array step: 0x8 */
29878     };
29879   } SYNCMANAGER[16];
29880        uint8_t RESERVED_28[128];
29881   union {                                          /* offset: 0x900 */
29882     __IO uint32_t RECEIVE_TIMES;                     /**< Distributed Clocks Receive Times, offset: 0x900 */
29883     __I  uint32_t RECEIVE_TIMES_PDI;                 /**< Distributed Clocks Receive Times, offset: 0x900 */
29884   };
29885   __I  uint32_t RECEIVE_TIME_PORT_1;               /**< Distributed Clocks Receive Time Port 1, offset: 0x904 */
29886        uint8_t RESERVED_29[8];
29887   union {                                          /* offset: 0x910 */
29888     __IO uint64_t SYSTEM_TIME;                       /**< Register System Time, offset: 0x910 */
29889     __IO uint64_t SYSTEM_TIME_PDI;                   /**< Register System Time, offset: 0x910 */
29890   };
29891   __I  uint64_t RECEIVE_TIME_ECAT_PROCESSING_UNIT; /**< Distributed Clocks Register Receive Time ECAT Processing Unit, offset: 0x918 */
29892   __IO uint64_t SYSTEM_TIME_OFFSET;                /**< Register System Time Offset, offset: 0x920 */
29893   __IO uint32_t SYSTEM_TIME_DELAY;                 /**< Register System Time Delay, offset: 0x928 */
29894   __I  uint32_t SYSTEM_TIME_DIFFERENCE;            /**< Register System Time Difference, offset: 0x92C */
29895   __IO uint16_t SPEED_COUNTER_START;               /**< Register Speed Counter Start, offset: 0x930 */
29896   __I  uint16_t SPEED_COUNTER_DIFF;                /**< Register Speed Counter Diff, offset: 0x932 */
29897   __IO uint8_t SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH; /**< Register System Time Difference Filter Depth, offset: 0x934 */
29898   __IO uint8_t SPEED_COUNTER_FILTER_DEPTH;         /**< Register Speed Counter Filter Depth, offset: 0x935 */
29899        uint8_t RESERVED_30[74];
29900   union {                                          /* offset: 0x980 */
29901     __IO uint8_t CYCLIC_UNIT_CONTROL;                /**< Register Cyclic Unit Control, offset: 0x980 */
29902     __I  uint8_t CYCLIC_UNIT_CONTROL_PDI;            /**< Register Cyclic Unit Control, offset: 0x980 */
29903   };
29904   __IO uint8_t UNIT_ACTIVATION_REGISTER;           /**< Register Activation register, offset: 0x981 */
29905   __I  uint16_t UNI_PULSE_LENGTH_OF_SYNCSIGNALS;   /**< Register Pulse Length of SyncSignals, offset: 0x982 */
29906   __I  uint8_t UNIT_ACTIVATION_STATUS;             /**< Register Activation Status, offset: 0x984 */
29907        uint8_t RESERVED_31[9];
29908   __I  uint8_t UNIT_SYNC0_STATUS;                  /**< Register SYNC0 Status, offset: 0x98E */
29909   __I  uint8_t UNIT_SYNC1_STATUS;                  /**< Register SYNC1 Status, offset: 0x98F */
29910   __IO uint64_t UNIT_START_TIME_CYCLIC_OPERATION;  /**< Register Start Time Cyclic Operation, offset: 0x990 */
29911   __I  uint64_t UNIT_NEXT_SYNC1_PULSE;             /**< Register Next SYNC1 Pulse, offset: 0x998 */
29912   __IO uint32_t UNIT_SYNC0_CYCLE_TIME;             /**< Register SYNC0 Cycle Time, offset: 0x9A0 */
29913   __IO uint32_t UNIT_SYNC1_CYCLE_TIME;             /**< Register SYNC1 Cycle Time, offset: 0x9A4 */
29914   __IO uint8_t LATCH0_CONTROL;                     /**< Register Latch0 Control, offset: 0x9A8 */
29915   __IO uint8_t LATCH1_CONTROL;                     /**< Register Latch1 Control, offset: 0x9A9 */
29916        uint8_t RESERVED_32[4];
29917   __I  uint8_t LATCH0_STATUS;                      /**< Register Latch0 Status, offset: 0x9AE */
29918   __I  uint8_t LATCH1_STATUS;                      /**< Register Latch1 Status, offset: 0x9AF */
29919   __I  uint64_t LATCH0_TIME_POSITIVE_EDGE;         /**< Register Latch0 Time Positive Edge, offset: 0x9B0 */
29920   __I  uint64_t LATCH0_TIME_NEGATIVE_EDGE;         /**< Register Latch0 Time Negative Edge, offset: 0x9B8 */
29921   __I  uint64_t LATCH1_TIME_POSITIVE_EDGE;         /**< Register Latch1 Time Positive Edge, offset: 0x9C0 */
29922   __I  uint64_t LATCH1_TIME_NEGATIVE_EDGE;         /**< Register Latch1 Time Negative Edge, offset: 0x9C8 */
29923        uint8_t RESERVED_33[32];
29924   __I  uint32_t ETHERCAT_BUFFER_CHANGE_EVENT_TIME; /**< Register EtherCAT Buffer Change Event Time, offset: 0x9F0 */
29925        uint8_t RESERVED_34[4];
29926   __I  uint32_t PDI_BUFFER_START_EVENT_TIME;       /**< Register PDI Buffer Start Event Time, offset: 0x9F8 */
29927   __I  uint32_t PDI_BUFFER_CHANGE_EVENT_TIME;      /**< Register PDI Buffer Change Event Time, offset: 0x9FC */
29928        uint8_t RESERVED_35[1024];
29929   __I  uint64_t PRODUCT_ID_IP_CORE;                /**< Register Product ID IP Core, offset: 0xE00 */
29930   __I  uint64_t VENDOR_ID_IP_CORE;                 /**< Register Vendor ID IP Core, offset: 0xE08 */
29931        uint8_t RESERVED_36[256];
29932   __IO uint16_t GENERAL_PURPOSE_OUTPUTS;           /**< Register General Purpose Outputs, offset: 0xF10 */
29933        uint8_t RESERVED_37[6];
29934   __I  uint16_t GENERAL_PURPOSE_INPUTS;            /**< Register General Purpose Inputs, offset: 0xF18 */
29935 } ECAT_Type;
29936 
29937 /* ----------------------------------------------------------------------------
29938    -- ECAT Register Masks
29939    ---------------------------------------------------------------------------- */
29940 
29941 /*!
29942  * @addtogroup ECAT_Register_Masks ECAT Register Masks
29943  * @{
29944  */
29945 
29946 /*! @name TYPE - Type */
29947 /*! @{ */
29948 
29949 #define ECAT_TYPE_BF0_MASK                       (0xFFU)
29950 #define ECAT_TYPE_BF0_SHIFT                      (0U)
29951 /*! BF0 - Type of EtherCAT controller */
29952 #define ECAT_TYPE_BF0(x)                         (((uint8_t)(((uint8_t)(x)) << ECAT_TYPE_BF0_SHIFT)) & ECAT_TYPE_BF0_MASK)
29953 /*! @} */
29954 
29955 /*! @name REVISION - Revision */
29956 /*! @{ */
29957 
29958 #define ECAT_REVISION_BF0_MASK                   (0xFFU)
29959 #define ECAT_REVISION_BF0_SHIFT                  (0U)
29960 /*! BF0 - Revision of EtherCAT controller. */
29961 #define ECAT_REVISION_BF0(x)                     (((uint8_t)(((uint8_t)(x)) << ECAT_REVISION_BF0_SHIFT)) & ECAT_REVISION_BF0_MASK)
29962 /*! @} */
29963 
29964 /*! @name BUILD - Build */
29965 /*! @{ */
29966 
29967 #define ECAT_BUILD_BF0_MASK                      (0xFFFFU)
29968 #define ECAT_BUILD_BF0_SHIFT                     (0U)
29969 /*! BF0 - Build of EtherCAT controller */
29970 #define ECAT_BUILD_BF0(x)                        (((uint16_t)(((uint16_t)(x)) << ECAT_BUILD_BF0_SHIFT)) & ECAT_BUILD_BF0_MASK)
29971 /*! @} */
29972 
29973 /*! @name FMMUS_SUPPORTED - FMMUs supported */
29974 /*! @{ */
29975 
29976 #define ECAT_FMMUS_SUPPORTED_BF0_MASK            (0xFFU)
29977 #define ECAT_FMMUS_SUPPORTED_BF0_SHIFT           (0U)
29978 /*! BF0 - Number of supported FMMU channels (or entities) */
29979 #define ECAT_FMMUS_SUPPORTED_BF0(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_FMMUS_SUPPORTED_BF0_SHIFT)) & ECAT_FMMUS_SUPPORTED_BF0_MASK)
29980 /*! @} */
29981 
29982 /*! @name SYNCMANAGERS_SUPPORTED - SyncManagers supported */
29983 /*! @{ */
29984 
29985 #define ECAT_SYNCMANAGERS_SUPPORTED_BF0_MASK     (0xFFU)
29986 #define ECAT_SYNCMANAGERS_SUPPORTED_BF0_SHIFT    (0U)
29987 /*! BF0 - Number of supported SyncManager channels (or entities) */
29988 #define ECAT_SYNCMANAGERS_SUPPORTED_BF0(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGERS_SUPPORTED_BF0_SHIFT)) & ECAT_SYNCMANAGERS_SUPPORTED_BF0_MASK)
29989 /*! @} */
29990 
29991 /*! @name RAM_SIZE - RAM Size */
29992 /*! @{ */
29993 
29994 #define ECAT_RAM_SIZE_BF0_MASK                   (0xFFU)
29995 #define ECAT_RAM_SIZE_BF0_SHIFT                  (0U)
29996 /*! BF0 - Process Data RAM size supported in KByte */
29997 #define ECAT_RAM_SIZE_BF0(x)                     (((uint8_t)(((uint8_t)(x)) << ECAT_RAM_SIZE_BF0_SHIFT)) & ECAT_RAM_SIZE_BF0_MASK)
29998 /*! @} */
29999 
30000 /*! @name PORT_DESCRIPTOR - Port configuration */
30001 /*! @{ */
30002 
30003 #define ECAT_PORT_DESCRIPTOR_BF0_MASK            (0x3U)
30004 #define ECAT_PORT_DESCRIPTOR_BF0_SHIFT           (0U)
30005 /*! BF0 - Port 0 */
30006 #define ECAT_PORT_DESCRIPTOR_BF0(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PORT_DESCRIPTOR_BF0_SHIFT)) & ECAT_PORT_DESCRIPTOR_BF0_MASK)
30007 
30008 #define ECAT_PORT_DESCRIPTOR_BF2_MASK            (0xCU)
30009 #define ECAT_PORT_DESCRIPTOR_BF2_SHIFT           (2U)
30010 /*! BF2 - Port 1 */
30011 #define ECAT_PORT_DESCRIPTOR_BF2(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PORT_DESCRIPTOR_BF2_SHIFT)) & ECAT_PORT_DESCRIPTOR_BF2_MASK)
30012 
30013 #define ECAT_PORT_DESCRIPTOR_BF4_MASK            (0x30U)
30014 #define ECAT_PORT_DESCRIPTOR_BF4_SHIFT           (4U)
30015 /*! BF4 - Reserved */
30016 #define ECAT_PORT_DESCRIPTOR_BF4(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PORT_DESCRIPTOR_BF4_SHIFT)) & ECAT_PORT_DESCRIPTOR_BF4_MASK)
30017 
30018 #define ECAT_PORT_DESCRIPTOR_BF6_MASK            (0xC0U)
30019 #define ECAT_PORT_DESCRIPTOR_BF6_SHIFT           (6U)
30020 /*! BF6 - Reserved */
30021 #define ECAT_PORT_DESCRIPTOR_BF6(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PORT_DESCRIPTOR_BF6_SHIFT)) & ECAT_PORT_DESCRIPTOR_BF6_MASK)
30022 /*! @} */
30023 
30024 /*! @name ESC_FEATURES_SUPPORTED - Register ESC Features supported */
30025 /*! @{ */
30026 
30027 #define ECAT_ESC_FEATURES_SUPPORTED_BF0_MASK     (0x1U)
30028 #define ECAT_ESC_FEATURES_SUPPORTED_BF0_SHIFT    (0U)
30029 /*! BF0 - FMMU Operation:
30030  *  0b0..Bit oriented
30031  *  0b1..Byte oriented
30032  */
30033 #define ECAT_ESC_FEATURES_SUPPORTED_BF0(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF0_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF0_MASK)
30034 
30035 #define ECAT_ESC_FEATURES_SUPPORTED_BF1_MASK     (0x2U)
30036 #define ECAT_ESC_FEATURES_SUPPORTED_BF1_SHIFT    (1U)
30037 /*! BF1 - Unused register access:
30038  *  0b0..allowed
30039  *  0b1..not supported
30040  */
30041 #define ECAT_ESC_FEATURES_SUPPORTED_BF1(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF1_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF1_MASK)
30042 
30043 #define ECAT_ESC_FEATURES_SUPPORTED_BF2_MASK     (0x4U)
30044 #define ECAT_ESC_FEATURES_SUPPORTED_BF2_SHIFT    (2U)
30045 /*! BF2 - Distributed Clocks:
30046  *  0b0..Not available
30047  *  0b1..Available
30048  */
30049 #define ECAT_ESC_FEATURES_SUPPORTED_BF2(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF2_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF2_MASK)
30050 
30051 #define ECAT_ESC_FEATURES_SUPPORTED_BF3_MASK     (0x8U)
30052 #define ECAT_ESC_FEATURES_SUPPORTED_BF3_SHIFT    (3U)
30053 /*! BF3 - Distributed Clocks (width):
30054  *  0b0..32 bit
30055  *  0b1..64 bit
30056  */
30057 #define ECAT_ESC_FEATURES_SUPPORTED_BF3(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF3_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF3_MASK)
30058 
30059 #define ECAT_ESC_FEATURES_SUPPORTED_BF6_MASK     (0x40U)
30060 #define ECAT_ESC_FEATURES_SUPPORTED_BF6_SHIFT    (6U)
30061 /*! BF6 - Enhanced Link Detection MII:
30062  *  0b0..Not available
30063  *  0b1..Available
30064  */
30065 #define ECAT_ESC_FEATURES_SUPPORTED_BF6(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF6_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF6_MASK)
30066 
30067 #define ECAT_ESC_FEATURES_SUPPORTED_BF7_MASK     (0x80U)
30068 #define ECAT_ESC_FEATURES_SUPPORTED_BF7_SHIFT    (7U)
30069 /*! BF7 - Separate Handling of FCS Errors:
30070  *  0b0..Not supported
30071  *  0b1..Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter
30072  */
30073 #define ECAT_ESC_FEATURES_SUPPORTED_BF7(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF7_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF7_MASK)
30074 
30075 #define ECAT_ESC_FEATURES_SUPPORTED_BF8_MASK     (0x100U)
30076 #define ECAT_ESC_FEATURES_SUPPORTED_BF8_SHIFT    (8U)
30077 /*! BF8 - Enhanced DC SYNC Activation
30078  *  0b0..Not available
30079  *  0b1..Available
30080  */
30081 #define ECAT_ESC_FEATURES_SUPPORTED_BF8(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF8_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF8_MASK)
30082 
30083 #define ECAT_ESC_FEATURES_SUPPORTED_BF9_MASK     (0x200U)
30084 #define ECAT_ESC_FEATURES_SUPPORTED_BF9_SHIFT    (9U)
30085 /*! BF9 - EtherCAT LRW command support:
30086  *  0b0..Supported
30087  *  0b1..Not supported
30088  */
30089 #define ECAT_ESC_FEATURES_SUPPORTED_BF9(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF9_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF9_MASK)
30090 
30091 #define ECAT_ESC_FEATURES_SUPPORTED_BF10_MASK    (0x400U)
30092 #define ECAT_ESC_FEATURES_SUPPORTED_BF10_SHIFT   (10U)
30093 /*! BF10 - EtherCAT read/write command support (BRW, APRW, FPRW):
30094  *  0b0..Supported
30095  *  0b1..Not supported
30096  */
30097 #define ECAT_ESC_FEATURES_SUPPORTED_BF10(x)      (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF10_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF10_MASK)
30098 
30099 #define ECAT_ESC_FEATURES_SUPPORTED_BF11_MASK    (0x800U)
30100 #define ECAT_ESC_FEATURES_SUPPORTED_BF11_SHIFT   (11U)
30101 /*! BF11 - Fixed FMMU/SyncManager configuration
30102  *  0b0..Variable configuration
30103  *  0b1..Fixed configuration (refer to documentation of supporting ESCs)
30104  */
30105 #define ECAT_ESC_FEATURES_SUPPORTED_BF11(x)      (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF11_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF11_MASK)
30106 
30107 #define ECAT_ESC_FEATURES_SUPPORTED_BF12_MASK    (0xF000U)
30108 #define ECAT_ESC_FEATURES_SUPPORTED_BF12_SHIFT   (12U)
30109 /*! BF12 - Reserved */
30110 #define ECAT_ESC_FEATURES_SUPPORTED_BF12(x)      (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_FEATURES_SUPPORTED_BF12_SHIFT)) & ECAT_ESC_FEATURES_SUPPORTED_BF12_MASK)
30111 /*! @} */
30112 
30113 /*! @name CONFIGURED_STATION_ADDRESS - Configured Station Address */
30114 /*! @{ */
30115 
30116 #define ECAT_CONFIGURED_STATION_ADDRESS_BF0_MASK (0xFFFFU)
30117 #define ECAT_CONFIGURED_STATION_ADDRESS_BF0_SHIFT (0U)
30118 /*! BF0 - Address used for node addressing (FPRD/FPWR/FPRW/FRMW commands). */
30119 #define ECAT_CONFIGURED_STATION_ADDRESS_BF0(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_CONFIGURED_STATION_ADDRESS_BF0_SHIFT)) & ECAT_CONFIGURED_STATION_ADDRESS_BF0_MASK)
30120 /*! @} */
30121 
30122 /*! @name CONFIGURED_STATION_ADDRESS_PDI - Configured Station Address */
30123 /*! @{ */
30124 
30125 #define ECAT_CONFIGURED_STATION_ADDRESS_PDI_BF0_MASK (0xFFFFU)
30126 #define ECAT_CONFIGURED_STATION_ADDRESS_PDI_BF0_SHIFT (0U)
30127 /*! BF0 - Address used for node addressing (FPRD/FPWR/FPRW/FRMW commands). */
30128 #define ECAT_CONFIGURED_STATION_ADDRESS_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_CONFIGURED_STATION_ADDRESS_PDI_BF0_SHIFT)) & ECAT_CONFIGURED_STATION_ADDRESS_PDI_BF0_MASK)
30129 /*! @} */
30130 
30131 /*! @name CONFIGURED_STATION_ALIAS - Configured Station Alias */
30132 /*! @{ */
30133 
30134 #define ECAT_CONFIGURED_STATION_ALIAS_BF0_MASK   (0xFFFFU)
30135 #define ECAT_CONFIGURED_STATION_ALIAS_BF0_SHIFT  (0U)
30136 /*! BF0 - Alias Address used for node addressing (FPRD/FPWR/FPRW/FRMW commands). */
30137 #define ECAT_CONFIGURED_STATION_ALIAS_BF0(x)     (((uint16_t)(((uint16_t)(x)) << ECAT_CONFIGURED_STATION_ALIAS_BF0_SHIFT)) & ECAT_CONFIGURED_STATION_ALIAS_BF0_MASK)
30138 /*! @} */
30139 
30140 /*! @name CONFIGURED_STATION_ALIAS_PDI - Configured Station Alias */
30141 /*! @{ */
30142 
30143 #define ECAT_CONFIGURED_STATION_ALIAS_PDI_BF0_MASK (0xFFFFU)
30144 #define ECAT_CONFIGURED_STATION_ALIAS_PDI_BF0_SHIFT (0U)
30145 /*! BF0 - Alias Address used for node addressing (FPRD/FPWR/FPRW/FRMW commands). */
30146 #define ECAT_CONFIGURED_STATION_ALIAS_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_CONFIGURED_STATION_ALIAS_PDI_BF0_SHIFT)) & ECAT_CONFIGURED_STATION_ALIAS_PDI_BF0_MASK)
30147 /*! @} */
30148 
30149 /*! @name REGISTER_WRITE_ENABLE - Register Write Enable */
30150 /*! @{ */
30151 
30152 #define ECAT_REGISTER_WRITE_ENABLE_BF0_MASK      (0x1U)
30153 #define ECAT_REGISTER_WRITE_ENABLE_BF0_SHIFT     (0U)
30154 /*! BF0 - Register Write Enable. */
30155 #define ECAT_REGISTER_WRITE_ENABLE_BF0(x)        (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_ENABLE_BF0_SHIFT)) & ECAT_REGISTER_WRITE_ENABLE_BF0_MASK)
30156 
30157 #define ECAT_REGISTER_WRITE_ENABLE_BF1_MASK      (0xFEU)
30158 #define ECAT_REGISTER_WRITE_ENABLE_BF1_SHIFT     (1U)
30159 /*! BF1 - Reserved, write 0 */
30160 #define ECAT_REGISTER_WRITE_ENABLE_BF1(x)        (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_ENABLE_BF1_SHIFT)) & ECAT_REGISTER_WRITE_ENABLE_BF1_MASK)
30161 /*! @} */
30162 
30163 /*! @name REGISTER_WRITE_ENABLE_PDI - Register Write Enable */
30164 /*! @{ */
30165 
30166 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF0_MASK  (0x1U)
30167 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF0_SHIFT (0U)
30168 /*! BF0 - Register Write Enable. */
30169 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF0(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_ENABLE_PDI_BF0_SHIFT)) & ECAT_REGISTER_WRITE_ENABLE_PDI_BF0_MASK)
30170 
30171 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF1_MASK  (0xFEU)
30172 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF1_SHIFT (1U)
30173 /*! BF1 - Reserved, write 0 */
30174 #define ECAT_REGISTER_WRITE_ENABLE_PDI_BF1(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_ENABLE_PDI_BF1_SHIFT)) & ECAT_REGISTER_WRITE_ENABLE_PDI_BF1_MASK)
30175 /*! @} */
30176 
30177 /*! @name REGISTER_WRITE_PROTECTION - Register Write Protection */
30178 /*! @{ */
30179 
30180 #define ECAT_REGISTER_WRITE_PROTECTION_BF0_MASK  (0x1U)
30181 #define ECAT_REGISTER_WRITE_PROTECTION_BF0_SHIFT (0U)
30182 /*! BF0 - Register write protection.
30183  *  0b0..Protection disabled
30184  *  0b1..Protection enabled
30185  */
30186 #define ECAT_REGISTER_WRITE_PROTECTION_BF0(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_PROTECTION_BF0_SHIFT)) & ECAT_REGISTER_WRITE_PROTECTION_BF0_MASK)
30187 
30188 #define ECAT_REGISTER_WRITE_PROTECTION_BF1_MASK  (0xFEU)
30189 #define ECAT_REGISTER_WRITE_PROTECTION_BF1_SHIFT (1U)
30190 /*! BF1 - Reserved, write 0 */
30191 #define ECAT_REGISTER_WRITE_PROTECTION_BF1(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_PROTECTION_BF1_SHIFT)) & ECAT_REGISTER_WRITE_PROTECTION_BF1_MASK)
30192 /*! @} */
30193 
30194 /*! @name REGISTER_WRITE_PROTECTION_PDI - Register Write Protection */
30195 /*! @{ */
30196 
30197 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF0_MASK (0x1U)
30198 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF0_SHIFT (0U)
30199 /*! BF0 - Register write protection.
30200  *  0b0..Protection disabled
30201  *  0b1..Protection enabled
30202  */
30203 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_PROTECTION_PDI_BF0_SHIFT)) & ECAT_REGISTER_WRITE_PROTECTION_PDI_BF0_MASK)
30204 
30205 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF1_MASK (0xFEU)
30206 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF1_SHIFT (1U)
30207 /*! BF1 - Reserved, write 0 */
30208 #define ECAT_REGISTER_WRITE_PROTECTION_PDI_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_WRITE_PROTECTION_PDI_BF1_SHIFT)) & ECAT_REGISTER_WRITE_PROTECTION_PDI_BF1_MASK)
30209 /*! @} */
30210 
30211 /*! @name ESC_WRITE_ENABLE - ESC Write Enable */
30212 /*! @{ */
30213 
30214 #define ECAT_ESC_WRITE_ENABLE_BF0_MASK           (0x1U)
30215 #define ECAT_ESC_WRITE_ENABLE_BF0_SHIFT          (0U)
30216 /*! BF0 - ESC Write Enable */
30217 #define ECAT_ESC_WRITE_ENABLE_BF0(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_ENABLE_BF0_SHIFT)) & ECAT_ESC_WRITE_ENABLE_BF0_MASK)
30218 
30219 #define ECAT_ESC_WRITE_ENABLE_BF1_MASK           (0xFEU)
30220 #define ECAT_ESC_WRITE_ENABLE_BF1_SHIFT          (1U)
30221 /*! BF1 - Reserved, write 0 */
30222 #define ECAT_ESC_WRITE_ENABLE_BF1(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_ENABLE_BF1_SHIFT)) & ECAT_ESC_WRITE_ENABLE_BF1_MASK)
30223 /*! @} */
30224 
30225 /*! @name ESC_WRITE_ENABLE_PDI - ESC Write Enable */
30226 /*! @{ */
30227 
30228 #define ECAT_ESC_WRITE_ENABLE_PDI_BF0_MASK       (0x1U)
30229 #define ECAT_ESC_WRITE_ENABLE_PDI_BF0_SHIFT      (0U)
30230 /*! BF0 - ESC Write Enable */
30231 #define ECAT_ESC_WRITE_ENABLE_PDI_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_ENABLE_PDI_BF0_SHIFT)) & ECAT_ESC_WRITE_ENABLE_PDI_BF0_MASK)
30232 
30233 #define ECAT_ESC_WRITE_ENABLE_PDI_BF1_MASK       (0xFEU)
30234 #define ECAT_ESC_WRITE_ENABLE_PDI_BF1_SHIFT      (1U)
30235 /*! BF1 - Reserved, write 0 */
30236 #define ECAT_ESC_WRITE_ENABLE_PDI_BF1(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_ENABLE_PDI_BF1_SHIFT)) & ECAT_ESC_WRITE_ENABLE_PDI_BF1_MASK)
30237 /*! @} */
30238 
30239 /*! @name ESC_WRITE_PROTECTION - ESC Write Protection */
30240 /*! @{ */
30241 
30242 #define ECAT_ESC_WRITE_PROTECTION_BF0_MASK       (0x1U)
30243 #define ECAT_ESC_WRITE_PROTECTION_BF0_SHIFT      (0U)
30244 /*! BF0 - Write protect:
30245  *  0b0..Protection disabled
30246  *  0b1..Protection enabled
30247  */
30248 #define ECAT_ESC_WRITE_PROTECTION_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_PROTECTION_BF0_SHIFT)) & ECAT_ESC_WRITE_PROTECTION_BF0_MASK)
30249 
30250 #define ECAT_ESC_WRITE_PROTECTION_BF1_MASK       (0xFEU)
30251 #define ECAT_ESC_WRITE_PROTECTION_BF1_SHIFT      (1U)
30252 /*! BF1 - Reserved, write 0 */
30253 #define ECAT_ESC_WRITE_PROTECTION_BF1(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_PROTECTION_BF1_SHIFT)) & ECAT_ESC_WRITE_PROTECTION_BF1_MASK)
30254 /*! @} */
30255 
30256 /*! @name ESC_WRITE_PROTECTION_PDI - ESC Write Protection */
30257 /*! @{ */
30258 
30259 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF0_MASK   (0x1U)
30260 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF0_SHIFT  (0U)
30261 /*! BF0 - Write protect:
30262  *  0b0..Protection disabled
30263  *  0b1..Protection enabled
30264  */
30265 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_PROTECTION_PDI_BF0_SHIFT)) & ECAT_ESC_WRITE_PROTECTION_PDI_BF0_MASK)
30266 
30267 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF1_MASK   (0xFEU)
30268 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF1_SHIFT  (1U)
30269 /*! BF1 - Reserved, write 0 */
30270 #define ECAT_ESC_WRITE_PROTECTION_PDI_BF1(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_WRITE_PROTECTION_PDI_BF1_SHIFT)) & ECAT_ESC_WRITE_PROTECTION_PDI_BF1_MASK)
30271 /*! @} */
30272 
30273 /*! @name ESC_RESET_ECAT_WRITE - ESC Reset ECAT WRITE */
30274 /*! @{ */
30275 
30276 #define ECAT_ESC_RESET_ECAT_WRITE_BF0_MASK       (0xFFU)
30277 #define ECAT_ESC_RESET_ECAT_WRITE_BF0_SHIFT      (0U)
30278 /*! BF0 - A reset is asserted after writing 0x52 ('R'), 0x45 ('E') and 0x53 ('S') in this register with 3 consecutive frames. */
30279 #define ECAT_ESC_RESET_ECAT_WRITE_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_RESET_ECAT_WRITE_BF0_SHIFT)) & ECAT_ESC_RESET_ECAT_WRITE_BF0_MASK)
30280 /*! @} */
30281 
30282 /*! @name ESC_RESET_ECAT_WRITE_PDI - ESC Reset ECAT WRITE */
30283 /*! @{ */
30284 
30285 #define ECAT_ESC_RESET_ECAT_WRITE_PDI_BF0_MASK   (0xFFU)
30286 #define ECAT_ESC_RESET_ECAT_WRITE_PDI_BF0_SHIFT  (0U)
30287 /*! BF0 - A reset is asserted after writing 0x52 ('R'), 0x45 ('E') and 0x53 ('S') in this register with 3 consecutive frames. */
30288 #define ECAT_ESC_RESET_ECAT_WRITE_PDI_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_RESET_ECAT_WRITE_PDI_BF0_SHIFT)) & ECAT_ESC_RESET_ECAT_WRITE_PDI_BF0_MASK)
30289 /*! @} */
30290 
30291 /*! @name ESC_RESET_PDI_WRITE - ESC Reset PDI WRITE */
30292 /*! @{ */
30293 
30294 #define ECAT_ESC_RESET_PDI_WRITE_BF0_MASK        (0xFFU)
30295 #define ECAT_ESC_RESET_PDI_WRITE_BF0_SHIFT       (0U)
30296 /*! BF0 - A reset is asserted after writing 0x52 ('R'), 0x45 ('E') and 0x53 ('S') in this register with 3 consecutive commands. */
30297 #define ECAT_ESC_RESET_PDI_WRITE_BF0(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_RESET_PDI_WRITE_BF0_SHIFT)) & ECAT_ESC_RESET_PDI_WRITE_BF0_MASK)
30298 /*! @} */
30299 
30300 /*! @name ESC_RESET_PDI_WRITE_PDI - ESC Reset PDI WRITE */
30301 /*! @{ */
30302 
30303 #define ECAT_ESC_RESET_PDI_WRITE_PDI_BF0_MASK    (0xFFU)
30304 #define ECAT_ESC_RESET_PDI_WRITE_PDI_BF0_SHIFT   (0U)
30305 /*! BF0 - A reset is asserted after writing 0x52 ('R'), 0x45 ('E') and 0x53 ('S') in this register with 3 consecutive commands. */
30306 #define ECAT_ESC_RESET_PDI_WRITE_PDI_BF0(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_RESET_PDI_WRITE_PDI_BF0_SHIFT)) & ECAT_ESC_RESET_PDI_WRITE_PDI_BF0_MASK)
30307 /*! @} */
30308 
30309 /*! @name ESC_DL_CONTROL - ESC DL Control */
30310 /*! @{ */
30311 
30312 #define ECAT_ESC_DL_CONTROL_BF0_MASK             (0x1U)
30313 #define ECAT_ESC_DL_CONTROL_BF0_SHIFT            (0U)
30314 /*! BF0 - Forwarding Rule
30315  *  0b0..EtherCAT frames are processed, non-EtherCAT frames are forwarded without processing or modification.
30316  *  0b1..EtherCAT frames are processed, non-EtherCAT frames are destroyed.
30317  */
30318 #define ECAT_ESC_DL_CONTROL_BF0(x)               (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF0_SHIFT)) & ECAT_ESC_DL_CONTROL_BF0_MASK)
30319 
30320 #define ECAT_ESC_DL_CONTROL_BF1_MASK             (0x2U)
30321 #define ECAT_ESC_DL_CONTROL_BF1_SHIFT            (1U)
30322 /*! BF1 - Temporary use of settings in 0x0100:0x0103[8:15]:
30323  *  0b0..permanent use
30324  *  0b1..use for about 1 second, then revert to previous settings
30325  */
30326 #define ECAT_ESC_DL_CONTROL_BF1(x)               (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF1_SHIFT)) & ECAT_ESC_DL_CONTROL_BF1_MASK)
30327 
30328 #define ECAT_ESC_DL_CONTROL_BF2_MASK             (0xFCU)
30329 #define ECAT_ESC_DL_CONTROL_BF2_SHIFT            (2U)
30330 /*! BF2 - Reserved, Write 0 */
30331 #define ECAT_ESC_DL_CONTROL_BF2(x)               (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF2_SHIFT)) & ECAT_ESC_DL_CONTROL_BF2_MASK)
30332 
30333 #define ECAT_ESC_DL_CONTROL_BF8_MASK             (0x300U)
30334 #define ECAT_ESC_DL_CONTROL_BF8_SHIFT            (8U)
30335 /*! BF8 - Loop Port 0:
30336  *  0b00..Auto
30337  *  0b01..Auto Close
30338  *  0b10..Open
30339  *  0b11..Closed
30340  */
30341 #define ECAT_ESC_DL_CONTROL_BF8(x)               (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF8_SHIFT)) & ECAT_ESC_DL_CONTROL_BF8_MASK)
30342 
30343 #define ECAT_ESC_DL_CONTROL_BF10_MASK            (0xC00U)
30344 #define ECAT_ESC_DL_CONTROL_BF10_SHIFT           (10U)
30345 /*! BF10 - Loop Port 1:
30346  *  0b00..Auto
30347  *  0b01..Auto Close
30348  *  0b10..Open
30349  *  0b11..Closed
30350  */
30351 #define ECAT_ESC_DL_CONTROL_BF10(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF10_SHIFT)) & ECAT_ESC_DL_CONTROL_BF10_MASK)
30352 
30353 #define ECAT_ESC_DL_CONTROL_BF12_MASK            (0x3000U)
30354 #define ECAT_ESC_DL_CONTROL_BF12_SHIFT           (12U)
30355 /*! BF12 - Reserved */
30356 #define ECAT_ESC_DL_CONTROL_BF12(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF12_SHIFT)) & ECAT_ESC_DL_CONTROL_BF12_MASK)
30357 
30358 #define ECAT_ESC_DL_CONTROL_BF14_MASK            (0xC000U)
30359 #define ECAT_ESC_DL_CONTROL_BF14_SHIFT           (14U)
30360 /*! BF14 - Reserved */
30361 #define ECAT_ESC_DL_CONTROL_BF14(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF14_SHIFT)) & ECAT_ESC_DL_CONTROL_BF14_MASK)
30362 
30363 #define ECAT_ESC_DL_CONTROL_BF16_MASK            (0x70000U)
30364 #define ECAT_ESC_DL_CONTROL_BF16_SHIFT           (16U)
30365 /*! BF16 - RX FIFO Size (ESC delays start of forwarding until FIFO is at least half full). */
30366 #define ECAT_ESC_DL_CONTROL_BF16(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF16_SHIFT)) & ECAT_ESC_DL_CONTROL_BF16_MASK)
30367 
30368 #define ECAT_ESC_DL_CONTROL_BF20_MASK            (0x300000U)
30369 #define ECAT_ESC_DL_CONTROL_BF20_SHIFT           (20U)
30370 /*! BF20 - Reserved, write 0 */
30371 #define ECAT_ESC_DL_CONTROL_BF20(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF20_SHIFT)) & ECAT_ESC_DL_CONTROL_BF20_MASK)
30372 
30373 #define ECAT_ESC_DL_CONTROL_BF23_MASK            (0x800000U)
30374 #define ECAT_ESC_DL_CONTROL_BF23_SHIFT           (23U)
30375 /*! BF23 - Reserved, write 0 */
30376 #define ECAT_ESC_DL_CONTROL_BF23(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF23_SHIFT)) & ECAT_ESC_DL_CONTROL_BF23_MASK)
30377 
30378 #define ECAT_ESC_DL_CONTROL_BF24_MASK            (0x1000000U)
30379 #define ECAT_ESC_DL_CONTROL_BF24_SHIFT           (24U)
30380 /*! BF24 - Station alias:
30381  *  0b0..Ignore Station Alias
30382  *  0b1..Alias can be used for all configured address command types (FPRD, FPWR, ...)
30383  */
30384 #define ECAT_ESC_DL_CONTROL_BF24(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF24_SHIFT)) & ECAT_ESC_DL_CONTROL_BF24_MASK)
30385 
30386 #define ECAT_ESC_DL_CONTROL_BF25_MASK            (0xFE000000U)
30387 #define ECAT_ESC_DL_CONTROL_BF25_SHIFT           (25U)
30388 /*! BF25 - Reserved, write 0 */
30389 #define ECAT_ESC_DL_CONTROL_BF25(x)              (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_BF25_SHIFT)) & ECAT_ESC_DL_CONTROL_BF25_MASK)
30390 /*! @} */
30391 
30392 /*! @name ESC_DL_CONTROL_PDI - ESC DL Control */
30393 /*! @{ */
30394 
30395 #define ECAT_ESC_DL_CONTROL_PDI_BF0_MASK         (0x1U)
30396 #define ECAT_ESC_DL_CONTROL_PDI_BF0_SHIFT        (0U)
30397 /*! BF0 - Forwarding Rule
30398  *  0b0..EtherCAT frames are processed, non-EtherCAT frames are forwarded without processing or modification.
30399  *  0b1..EtherCAT frames are processed, non-EtherCAT frames are destroyed.
30400  */
30401 #define ECAT_ESC_DL_CONTROL_PDI_BF0(x)           (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF0_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF0_MASK)
30402 
30403 #define ECAT_ESC_DL_CONTROL_PDI_BF1_MASK         (0x2U)
30404 #define ECAT_ESC_DL_CONTROL_PDI_BF1_SHIFT        (1U)
30405 /*! BF1 - Temporary use of settings in 0x0100:0x0103[8:15]:
30406  *  0b0..permanent use
30407  *  0b1..use for about 1 second, then revert to previous settings
30408  */
30409 #define ECAT_ESC_DL_CONTROL_PDI_BF1(x)           (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF1_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF1_MASK)
30410 
30411 #define ECAT_ESC_DL_CONTROL_PDI_BF2_MASK         (0xFCU)
30412 #define ECAT_ESC_DL_CONTROL_PDI_BF2_SHIFT        (2U)
30413 /*! BF2 - Reserved, Write 0 */
30414 #define ECAT_ESC_DL_CONTROL_PDI_BF2(x)           (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF2_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF2_MASK)
30415 
30416 #define ECAT_ESC_DL_CONTROL_PDI_BF8_MASK         (0x300U)
30417 #define ECAT_ESC_DL_CONTROL_PDI_BF8_SHIFT        (8U)
30418 /*! BF8 - Loop Port 0:
30419  *  0b00..Auto
30420  *  0b01..Auto Close
30421  *  0b10..Open
30422  *  0b11..Closed
30423  */
30424 #define ECAT_ESC_DL_CONTROL_PDI_BF8(x)           (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF8_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF8_MASK)
30425 
30426 #define ECAT_ESC_DL_CONTROL_PDI_BF10_MASK        (0xC00U)
30427 #define ECAT_ESC_DL_CONTROL_PDI_BF10_SHIFT       (10U)
30428 /*! BF10 - Loop Port 1:
30429  *  0b00..Auto
30430  *  0b01..Auto Close
30431  *  0b10..Open
30432  *  0b11..Closed
30433  */
30434 #define ECAT_ESC_DL_CONTROL_PDI_BF10(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF10_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF10_MASK)
30435 
30436 #define ECAT_ESC_DL_CONTROL_PDI_BF12_MASK        (0x3000U)
30437 #define ECAT_ESC_DL_CONTROL_PDI_BF12_SHIFT       (12U)
30438 /*! BF12 - Reserved */
30439 #define ECAT_ESC_DL_CONTROL_PDI_BF12(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF12_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF12_MASK)
30440 
30441 #define ECAT_ESC_DL_CONTROL_PDI_BF14_MASK        (0xC000U)
30442 #define ECAT_ESC_DL_CONTROL_PDI_BF14_SHIFT       (14U)
30443 /*! BF14 - Reserved */
30444 #define ECAT_ESC_DL_CONTROL_PDI_BF14(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF14_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF14_MASK)
30445 
30446 #define ECAT_ESC_DL_CONTROL_PDI_BF16_MASK        (0x70000U)
30447 #define ECAT_ESC_DL_CONTROL_PDI_BF16_SHIFT       (16U)
30448 /*! BF16 - RX FIFO Size (ESC delays start of forwarding until FIFO is at least half full). */
30449 #define ECAT_ESC_DL_CONTROL_PDI_BF16(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF16_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF16_MASK)
30450 
30451 #define ECAT_ESC_DL_CONTROL_PDI_BF20_MASK        (0x300000U)
30452 #define ECAT_ESC_DL_CONTROL_PDI_BF20_SHIFT       (20U)
30453 /*! BF20 - Reserved, write 0 */
30454 #define ECAT_ESC_DL_CONTROL_PDI_BF20(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF20_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF20_MASK)
30455 
30456 #define ECAT_ESC_DL_CONTROL_PDI_BF23_MASK        (0x800000U)
30457 #define ECAT_ESC_DL_CONTROL_PDI_BF23_SHIFT       (23U)
30458 /*! BF23 - Reserved, write 0 */
30459 #define ECAT_ESC_DL_CONTROL_PDI_BF23(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF23_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF23_MASK)
30460 
30461 #define ECAT_ESC_DL_CONTROL_PDI_BF24_MASK        (0x1000000U)
30462 #define ECAT_ESC_DL_CONTROL_PDI_BF24_SHIFT       (24U)
30463 /*! BF24 - Station alias:
30464  *  0b0..Ignore Station Alias
30465  *  0b1..Alias can be used for all configured address command types (FPRD, FPWR, ...)
30466  */
30467 #define ECAT_ESC_DL_CONTROL_PDI_BF24(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF24_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF24_MASK)
30468 
30469 #define ECAT_ESC_DL_CONTROL_PDI_BF25_MASK        (0xFE000000U)
30470 #define ECAT_ESC_DL_CONTROL_PDI_BF25_SHIFT       (25U)
30471 /*! BF25 - Reserved, write 0 */
30472 #define ECAT_ESC_DL_CONTROL_PDI_BF25(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_ESC_DL_CONTROL_PDI_BF25_SHIFT)) & ECAT_ESC_DL_CONTROL_PDI_BF25_MASK)
30473 /*! @} */
30474 
30475 /*! @name PHYSICAL_READ_WRITE_OFFSET - Physical Read Write Offset */
30476 /*! @{ */
30477 
30478 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_BF0_MASK (0xFFFFU)
30479 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_BF0_SHIFT (0U)
30480 /*! BF0 - This register is used for ReadWrite commands in Device Addressing mode (FPRW, APRW, BRW). */
30481 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_BF0(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_PHYSICAL_READ_WRITE_OFFSET_BF0_SHIFT)) & ECAT_PHYSICAL_READ_WRITE_OFFSET_BF0_MASK)
30482 /*! @} */
30483 
30484 /*! @name PHYSICAL_READ_WRITE_OFFSET_PDI - Physical Read Write Offset */
30485 /*! @{ */
30486 
30487 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_PDI_BF0_MASK (0xFFFFU)
30488 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_PDI_BF0_SHIFT (0U)
30489 /*! BF0 - This register is used for ReadWrite commands in Device Addressing mode (FPRW, APRW, BRW). */
30490 #define ECAT_PHYSICAL_READ_WRITE_OFFSET_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_PHYSICAL_READ_WRITE_OFFSET_PDI_BF0_SHIFT)) & ECAT_PHYSICAL_READ_WRITE_OFFSET_PDI_BF0_MASK)
30491 /*! @} */
30492 
30493 /*! @name ESC_DL_STATUS - ESC DL Status */
30494 /*! @{ */
30495 
30496 #define ECAT_ESC_DL_STATUS_BF0_MASK              (0x1U)
30497 #define ECAT_ESC_DL_STATUS_BF0_SHIFT             (0U)
30498 /*! BF0 - Register ESC DL Status
30499  *  0b0..PDI operational/EEPROM loaded correctly:
30500  *  0b1..EEPROM loaded correctly, PDI operational (access to Process Data RAM)
30501  */
30502 #define ECAT_ESC_DL_STATUS_BF0(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF0_SHIFT)) & ECAT_ESC_DL_STATUS_BF0_MASK)
30503 
30504 #define ECAT_ESC_DL_STATUS_BF1_MASK              (0x2U)
30505 #define ECAT_ESC_DL_STATUS_BF1_SHIFT             (1U)
30506 /*! BF1 - PDI Watchdog Status:
30507  *  0b0..Watchdog expired
30508  *  0b1..Watchdog reloaded
30509  */
30510 #define ECAT_ESC_DL_STATUS_BF1(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF1_SHIFT)) & ECAT_ESC_DL_STATUS_BF1_MASK)
30511 
30512 #define ECAT_ESC_DL_STATUS_BF2_MASK              (0x4U)
30513 #define ECAT_ESC_DL_STATUS_BF2_SHIFT             (2U)
30514 /*! BF2 - Enhanced Link detection:
30515  *  0b0..Deactivated for all ports
30516  *  0b1..Activated for at least one port
30517  */
30518 #define ECAT_ESC_DL_STATUS_BF2(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF2_SHIFT)) & ECAT_ESC_DL_STATUS_BF2_MASK)
30519 
30520 #define ECAT_ESC_DL_STATUS_BF3_MASK              (0x8U)
30521 #define ECAT_ESC_DL_STATUS_BF3_SHIFT             (3U)
30522 /*! BF3 - Reserved */
30523 #define ECAT_ESC_DL_STATUS_BF3(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF3_SHIFT)) & ECAT_ESC_DL_STATUS_BF3_MASK)
30524 
30525 #define ECAT_ESC_DL_STATUS_BF4_MASK              (0x10U)
30526 #define ECAT_ESC_DL_STATUS_BF4_SHIFT             (4U)
30527 /*! BF4 - Physical link on Port 0:
30528  *  0b0..No link
30529  *  0b1..Link detected
30530  */
30531 #define ECAT_ESC_DL_STATUS_BF4(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF4_SHIFT)) & ECAT_ESC_DL_STATUS_BF4_MASK)
30532 
30533 #define ECAT_ESC_DL_STATUS_BF5_MASK              (0x20U)
30534 #define ECAT_ESC_DL_STATUS_BF5_SHIFT             (5U)
30535 /*! BF5 - Physical link on Port 1:
30536  *  0b0..No link
30537  *  0b1..Link detected
30538  */
30539 #define ECAT_ESC_DL_STATUS_BF5(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF5_SHIFT)) & ECAT_ESC_DL_STATUS_BF5_MASK)
30540 
30541 #define ECAT_ESC_DL_STATUS_BF6_MASK              (0x40U)
30542 #define ECAT_ESC_DL_STATUS_BF6_SHIFT             (6U)
30543 /*! BF6 - Reserved */
30544 #define ECAT_ESC_DL_STATUS_BF6(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF6_SHIFT)) & ECAT_ESC_DL_STATUS_BF6_MASK)
30545 
30546 #define ECAT_ESC_DL_STATUS_BF7_MASK              (0x80U)
30547 #define ECAT_ESC_DL_STATUS_BF7_SHIFT             (7U)
30548 /*! BF7 - Reserved */
30549 #define ECAT_ESC_DL_STATUS_BF7(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF7_SHIFT)) & ECAT_ESC_DL_STATUS_BF7_MASK)
30550 
30551 #define ECAT_ESC_DL_STATUS_BF8_MASK              (0x100U)
30552 #define ECAT_ESC_DL_STATUS_BF8_SHIFT             (8U)
30553 /*! BF8 - Loop Port 0:
30554  *  0b0..Open
30555  *  0b1..Closed
30556  */
30557 #define ECAT_ESC_DL_STATUS_BF8(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF8_SHIFT)) & ECAT_ESC_DL_STATUS_BF8_MASK)
30558 
30559 #define ECAT_ESC_DL_STATUS_BF9_MASK              (0x200U)
30560 #define ECAT_ESC_DL_STATUS_BF9_SHIFT             (9U)
30561 /*! BF9 - Communication on Port 0:
30562  *  0b0..No stable communication
30563  *  0b1..Communication established
30564  */
30565 #define ECAT_ESC_DL_STATUS_BF9(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF9_SHIFT)) & ECAT_ESC_DL_STATUS_BF9_MASK)
30566 
30567 #define ECAT_ESC_DL_STATUS_BF10_MASK             (0x400U)
30568 #define ECAT_ESC_DL_STATUS_BF10_SHIFT            (10U)
30569 /*! BF10 - Loop Port 1
30570  *  0b0..Open
30571  *  0b1..Closed
30572  */
30573 #define ECAT_ESC_DL_STATUS_BF10(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF10_SHIFT)) & ECAT_ESC_DL_STATUS_BF10_MASK)
30574 
30575 #define ECAT_ESC_DL_STATUS_BF11_MASK             (0x800U)
30576 #define ECAT_ESC_DL_STATUS_BF11_SHIFT            (11U)
30577 /*! BF11 - Communication on Port 1:
30578  *  0b0..No stable communication
30579  *  0b1..Communication established
30580  */
30581 #define ECAT_ESC_DL_STATUS_BF11(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF11_SHIFT)) & ECAT_ESC_DL_STATUS_BF11_MASK)
30582 
30583 #define ECAT_ESC_DL_STATUS_BF12_MASK             (0x1000U)
30584 #define ECAT_ESC_DL_STATUS_BF12_SHIFT            (12U)
30585 /*! BF12 - Reserved */
30586 #define ECAT_ESC_DL_STATUS_BF12(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF12_SHIFT)) & ECAT_ESC_DL_STATUS_BF12_MASK)
30587 
30588 #define ECAT_ESC_DL_STATUS_BF13_MASK             (0x2000U)
30589 #define ECAT_ESC_DL_STATUS_BF13_SHIFT            (13U)
30590 /*! BF13 - Reserved */
30591 #define ECAT_ESC_DL_STATUS_BF13(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF13_SHIFT)) & ECAT_ESC_DL_STATUS_BF13_MASK)
30592 
30593 #define ECAT_ESC_DL_STATUS_BF14_MASK             (0x4000U)
30594 #define ECAT_ESC_DL_STATUS_BF14_SHIFT            (14U)
30595 /*! BF14 - Reserved */
30596 #define ECAT_ESC_DL_STATUS_BF14(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF14_SHIFT)) & ECAT_ESC_DL_STATUS_BF14_MASK)
30597 
30598 #define ECAT_ESC_DL_STATUS_BF15_MASK             (0x8000U)
30599 #define ECAT_ESC_DL_STATUS_BF15_SHIFT            (15U)
30600 /*! BF15 - Reserved */
30601 #define ECAT_ESC_DL_STATUS_BF15(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_ESC_DL_STATUS_BF15_SHIFT)) & ECAT_ESC_DL_STATUS_BF15_MASK)
30602 /*! @} */
30603 
30604 /*! @name AL_CONTROL - AL Control */
30605 /*! @{ */
30606 
30607 #define ECAT_AL_CONTROL_BF0_MASK                 (0xFU)
30608 #define ECAT_AL_CONTROL_BF0_SHIFT                (0U)
30609 /*! BF0 - Initiate State Transition of the Device State Machine: */
30610 #define ECAT_AL_CONTROL_BF0(x)                   (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_BF0_SHIFT)) & ECAT_AL_CONTROL_BF0_MASK)
30611 
30612 #define ECAT_AL_CONTROL_BF4_MASK                 (0x10U)
30613 #define ECAT_AL_CONTROL_BF4_SHIFT                (4U)
30614 /*! BF4 - Error Ind Ack
30615  *  0b0..No Ack of Error Ind in AL status register
30616  *  0b1..Ack of Error Ind in AL status register
30617  */
30618 #define ECAT_AL_CONTROL_BF4(x)                   (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_BF4_SHIFT)) & ECAT_AL_CONTROL_BF4_MASK)
30619 
30620 #define ECAT_AL_CONTROL_BF5_MASK                 (0x20U)
30621 #define ECAT_AL_CONTROL_BF5_SHIFT                (5U)
30622 /*! BF5 - Device Identification:
30623  *  0b0..No request
30624  *  0b1..Device Identification request
30625  */
30626 #define ECAT_AL_CONTROL_BF5(x)                   (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_BF5_SHIFT)) & ECAT_AL_CONTROL_BF5_MASK)
30627 
30628 #define ECAT_AL_CONTROL_BF6_MASK                 (0xFFC0U)
30629 #define ECAT_AL_CONTROL_BF6_SHIFT                (6U)
30630 /*! BF6 - Reserved, write 0 */
30631 #define ECAT_AL_CONTROL_BF6(x)                   (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_BF6_SHIFT)) & ECAT_AL_CONTROL_BF6_MASK)
30632 /*! @} */
30633 
30634 /*! @name AL_CONTROL_PDI - AL Control */
30635 /*! @{ */
30636 
30637 #define ECAT_AL_CONTROL_PDI_BF0_MASK             (0xFU)
30638 #define ECAT_AL_CONTROL_PDI_BF0_SHIFT            (0U)
30639 /*! BF0 - Initiate State Transition of the Device State Machine: */
30640 #define ECAT_AL_CONTROL_PDI_BF0(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_PDI_BF0_SHIFT)) & ECAT_AL_CONTROL_PDI_BF0_MASK)
30641 
30642 #define ECAT_AL_CONTROL_PDI_BF4_MASK             (0x10U)
30643 #define ECAT_AL_CONTROL_PDI_BF4_SHIFT            (4U)
30644 /*! BF4 - Error Ind Ack
30645  *  0b0..No Ack of Error Ind in AL status register
30646  *  0b1..Ack of Error Ind in AL status register
30647  */
30648 #define ECAT_AL_CONTROL_PDI_BF4(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_PDI_BF4_SHIFT)) & ECAT_AL_CONTROL_PDI_BF4_MASK)
30649 
30650 #define ECAT_AL_CONTROL_PDI_BF5_MASK             (0x20U)
30651 #define ECAT_AL_CONTROL_PDI_BF5_SHIFT            (5U)
30652 /*! BF5 - Device Identification:
30653  *  0b0..No request
30654  *  0b1..Device Identification request
30655  */
30656 #define ECAT_AL_CONTROL_PDI_BF5(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_PDI_BF5_SHIFT)) & ECAT_AL_CONTROL_PDI_BF5_MASK)
30657 
30658 #define ECAT_AL_CONTROL_PDI_BF6_MASK             (0xFFC0U)
30659 #define ECAT_AL_CONTROL_PDI_BF6_SHIFT            (6U)
30660 /*! BF6 - Reserved, write 0 */
30661 #define ECAT_AL_CONTROL_PDI_BF6(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_AL_CONTROL_PDI_BF6_SHIFT)) & ECAT_AL_CONTROL_PDI_BF6_MASK)
30662 /*! @} */
30663 
30664 /*! @name AL_STATUS - AL Status */
30665 /*! @{ */
30666 
30667 #define ECAT_AL_STATUS_BF0_MASK                  (0xFU)
30668 #define ECAT_AL_STATUS_BF0_SHIFT                 (0U)
30669 /*! BF0 - Actual State of the Device State Machine: */
30670 #define ECAT_AL_STATUS_BF0(x)                    (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_BF0_SHIFT)) & ECAT_AL_STATUS_BF0_MASK)
30671 
30672 #define ECAT_AL_STATUS_BF4_MASK                  (0x10U)
30673 #define ECAT_AL_STATUS_BF4_SHIFT                 (4U)
30674 /*! BF4 - Error Ind:
30675  *  0b0..Device is in State as requested or Flag cleared by command
30676  *  0b1..Device has not entered requested State or changed State as result of a local action
30677  */
30678 #define ECAT_AL_STATUS_BF4(x)                    (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_BF4_SHIFT)) & ECAT_AL_STATUS_BF4_MASK)
30679 
30680 #define ECAT_AL_STATUS_BF5_MASK                  (0x20U)
30681 #define ECAT_AL_STATUS_BF5_SHIFT                 (5U)
30682 /*! BF5 - Device Identification:
30683  *  0b0..Device Identification not valid
30684  *  0b1..Device Identification loaded
30685  */
30686 #define ECAT_AL_STATUS_BF5(x)                    (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_BF5_SHIFT)) & ECAT_AL_STATUS_BF5_MASK)
30687 
30688 #define ECAT_AL_STATUS_BF6_MASK                  (0xFFC0U)
30689 #define ECAT_AL_STATUS_BF6_SHIFT                 (6U)
30690 /*! BF6 - Reserved, write 0 */
30691 #define ECAT_AL_STATUS_BF6(x)                    (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_BF6_SHIFT)) & ECAT_AL_STATUS_BF6_MASK)
30692 /*! @} */
30693 
30694 /*! @name AL_STATUS_PDI - AL Status */
30695 /*! @{ */
30696 
30697 #define ECAT_AL_STATUS_PDI_BF0_MASK              (0xFU)
30698 #define ECAT_AL_STATUS_PDI_BF0_SHIFT             (0U)
30699 /*! BF0 - Actual State of the Device State Machine: */
30700 #define ECAT_AL_STATUS_PDI_BF0(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_PDI_BF0_SHIFT)) & ECAT_AL_STATUS_PDI_BF0_MASK)
30701 
30702 #define ECAT_AL_STATUS_PDI_BF4_MASK              (0x10U)
30703 #define ECAT_AL_STATUS_PDI_BF4_SHIFT             (4U)
30704 /*! BF4 - Error Ind:
30705  *  0b0..Device is in State as requested or Flag cleared by command
30706  *  0b1..Device has not entered requested State or changed State as result of a local action
30707  */
30708 #define ECAT_AL_STATUS_PDI_BF4(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_PDI_BF4_SHIFT)) & ECAT_AL_STATUS_PDI_BF4_MASK)
30709 
30710 #define ECAT_AL_STATUS_PDI_BF5_MASK              (0x20U)
30711 #define ECAT_AL_STATUS_PDI_BF5_SHIFT             (5U)
30712 /*! BF5 - Device Identification:
30713  *  0b0..Device Identification not valid
30714  *  0b1..Device Identification loaded
30715  */
30716 #define ECAT_AL_STATUS_PDI_BF5(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_PDI_BF5_SHIFT)) & ECAT_AL_STATUS_PDI_BF5_MASK)
30717 
30718 #define ECAT_AL_STATUS_PDI_BF6_MASK              (0xFFC0U)
30719 #define ECAT_AL_STATUS_PDI_BF6_SHIFT             (6U)
30720 /*! BF6 - Reserved, write 0 */
30721 #define ECAT_AL_STATUS_PDI_BF6(x)                (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_PDI_BF6_SHIFT)) & ECAT_AL_STATUS_PDI_BF6_MASK)
30722 /*! @} */
30723 
30724 /*! @name AL_STATUS_CODE - AL Status Code */
30725 /*! @{ */
30726 
30727 #define ECAT_AL_STATUS_CODE_BF0_MASK             (0xFFFFU)
30728 #define ECAT_AL_STATUS_CODE_BF0_SHIFT            (0U)
30729 /*! BF0 - AL Status Code */
30730 #define ECAT_AL_STATUS_CODE_BF0(x)               (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_CODE_BF0_SHIFT)) & ECAT_AL_STATUS_CODE_BF0_MASK)
30731 /*! @} */
30732 
30733 /*! @name AL_STATUS_CODE_PDI - AL Status Code */
30734 /*! @{ */
30735 
30736 #define ECAT_AL_STATUS_CODE_PDI_BF0_MASK         (0xFFFFU)
30737 #define ECAT_AL_STATUS_CODE_PDI_BF0_SHIFT        (0U)
30738 /*! BF0 - AL Status Code */
30739 #define ECAT_AL_STATUS_CODE_PDI_BF0(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_AL_STATUS_CODE_PDI_BF0_SHIFT)) & ECAT_AL_STATUS_CODE_PDI_BF0_MASK)
30740 /*! @} */
30741 
30742 /*! @name RUN_LED_OVERRIDE - RUN LED Override */
30743 /*! @{ */
30744 
30745 #define ECAT_RUN_LED_OVERRIDE_BF0_MASK           (0xFU)
30746 #define ECAT_RUN_LED_OVERRIDE_BF0_SHIFT          (0U)
30747 /*! BF0 - LED code and AL Status */
30748 #define ECAT_RUN_LED_OVERRIDE_BF0(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_RUN_LED_OVERRIDE_BF0_SHIFT)) & ECAT_RUN_LED_OVERRIDE_BF0_MASK)
30749 
30750 #define ECAT_RUN_LED_OVERRIDE_BF4_MASK           (0x10U)
30751 #define ECAT_RUN_LED_OVERRIDE_BF4_SHIFT          (4U)
30752 /*! BF4 - Enable Override:
30753  *  0b0..Override disabled
30754  *  0b1..Override enabled
30755  */
30756 #define ECAT_RUN_LED_OVERRIDE_BF4(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_RUN_LED_OVERRIDE_BF4_SHIFT)) & ECAT_RUN_LED_OVERRIDE_BF4_MASK)
30757 
30758 #define ECAT_RUN_LED_OVERRIDE_BF5_MASK           (0xE0U)
30759 #define ECAT_RUN_LED_OVERRIDE_BF5_SHIFT          (5U)
30760 /*! BF5 - Reserved, write 0 */
30761 #define ECAT_RUN_LED_OVERRIDE_BF5(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_RUN_LED_OVERRIDE_BF5_SHIFT)) & ECAT_RUN_LED_OVERRIDE_BF5_MASK)
30762 /*! @} */
30763 
30764 /*! @name ERR_LED_OVERRIDE - ERR LED Override */
30765 /*! @{ */
30766 
30767 #define ECAT_ERR_LED_OVERRIDE_BF0_MASK           (0xFU)
30768 #define ECAT_ERR_LED_OVERRIDE_BF0_SHIFT          (0U)
30769 /*! BF0 - LED code */
30770 #define ECAT_ERR_LED_OVERRIDE_BF0(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_ERR_LED_OVERRIDE_BF0_SHIFT)) & ECAT_ERR_LED_OVERRIDE_BF0_MASK)
30771 
30772 #define ECAT_ERR_LED_OVERRIDE_BF4_MASK           (0x10U)
30773 #define ECAT_ERR_LED_OVERRIDE_BF4_SHIFT          (4U)
30774 /*! BF4 - Enable Override:
30775  *  0b0..Override disabled
30776  *  0b1..Override enabled
30777  */
30778 #define ECAT_ERR_LED_OVERRIDE_BF4(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_ERR_LED_OVERRIDE_BF4_SHIFT)) & ECAT_ERR_LED_OVERRIDE_BF4_MASK)
30779 
30780 #define ECAT_ERR_LED_OVERRIDE_BF5_MASK           (0xE0U)
30781 #define ECAT_ERR_LED_OVERRIDE_BF5_SHIFT          (5U)
30782 /*! BF5 - Reserved, write 0 */
30783 #define ECAT_ERR_LED_OVERRIDE_BF5(x)             (((uint8_t)(((uint8_t)(x)) << ECAT_ERR_LED_OVERRIDE_BF5_SHIFT)) & ECAT_ERR_LED_OVERRIDE_BF5_MASK)
30784 /*! @} */
30785 
30786 /*! @name PDI_CONTROL - PDI Control */
30787 /*! @{ */
30788 
30789 #define ECAT_PDI_CONTROL_BF0_MASK                (0xFFU)
30790 #define ECAT_PDI_CONTROL_BF0_SHIFT               (0U)
30791 /*! BF0 - Process data interface:
30792  *  0b00000000..Interface deactivated (no PDI)
30793  *  0b00000001..4 Digital Input
30794  *  0b00000010..4 Digital Output
30795  *  0b00000011..2 Digital Input and 2 Digital Output
30796  *  0b00000100..Digital I/O
30797  *  0b00000101..SPI Slave
30798  *  0b00000110..Oversampling I/O
30799  *  0b00000111..Reserved
30800  *  0b00001000..16 Bit asynchronous Microcontroller interface
30801  *  0b00001001..8 Bit asynchronous Microcontroller interface
30802  *  0b00001010..16 Bit synchronous Microcontroller interface
30803  *  0b00001011..8 Bit synchronous Microcontroller interface
30804  *  0b00010000..32 Digital Input and 0 Digital Output
30805  *  0b00010001..24 Digital Input and 8 Digital Output
30806  *  0b00010010..16 Digital Input and 16 Digital Output
30807  *  0b00010011..8 Digital Input and 24 Digital Output
30808  *  0b00010100..0 Digital Input and 32 Digital Output
30809  *  0b10000000..On-chip bus.
30810  */
30811 #define ECAT_PDI_CONTROL_BF0(x)                  (((uint8_t)(((uint8_t)(x)) << ECAT_PDI_CONTROL_BF0_SHIFT)) & ECAT_PDI_CONTROL_BF0_MASK)
30812 /*! @} */
30813 
30814 /*! @name ESC_CONFIGURATION - ESC Configuration */
30815 /*! @{ */
30816 
30817 #define ECAT_ESC_CONFIGURATION_BF0_MASK          (0x1U)
30818 #define ECAT_ESC_CONFIGURATION_BF0_SHIFT         (0U)
30819 /*! BF0 - Device emulation (control of AL status):
30820  *  0b0..AL status register has to be set by PDI
30821  *  0b1..AL status register will be set to value written to AL control register
30822  */
30823 #define ECAT_ESC_CONFIGURATION_BF0(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF0_SHIFT)) & ECAT_ESC_CONFIGURATION_BF0_MASK)
30824 
30825 #define ECAT_ESC_CONFIGURATION_BF1_MASK          (0x2U)
30826 #define ECAT_ESC_CONFIGURATION_BF1_SHIFT         (1U)
30827 /*! BF1 - Enhanced Link detection all ports:
30828  *  0b0..disabled (if bits [7:4]=0)
30829  *  0b1..enabled at all ports (overrides bits [7:4])
30830  */
30831 #define ECAT_ESC_CONFIGURATION_BF1(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF1_SHIFT)) & ECAT_ESC_CONFIGURATION_BF1_MASK)
30832 
30833 #define ECAT_ESC_CONFIGURATION_BF2_MASK          (0x4U)
30834 #define ECAT_ESC_CONFIGURATION_BF2_SHIFT         (2U)
30835 /*! BF2 - Distributed Clocks SYNC Out Unit:
30836  *  0b0..disabled (power saving)
30837  *  0b1..enabled
30838  */
30839 #define ECAT_ESC_CONFIGURATION_BF2(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF2_SHIFT)) & ECAT_ESC_CONFIGURATION_BF2_MASK)
30840 
30841 #define ECAT_ESC_CONFIGURATION_BF3_MASK          (0x8U)
30842 #define ECAT_ESC_CONFIGURATION_BF3_SHIFT         (3U)
30843 /*! BF3 - Distributed Clocks Latch In Unit:
30844  *  0b0..disabled (power saving)
30845  *  0b1..enabled
30846  */
30847 #define ECAT_ESC_CONFIGURATION_BF3(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF3_SHIFT)) & ECAT_ESC_CONFIGURATION_BF3_MASK)
30848 
30849 #define ECAT_ESC_CONFIGURATION_BF4_MASK          (0x10U)
30850 #define ECAT_ESC_CONFIGURATION_BF4_SHIFT         (4U)
30851 /*! BF4 - Enhanced Link port 0:
30852  *  0b0..disabled (if bit 1=0)
30853  *  0b1..enabled
30854  */
30855 #define ECAT_ESC_CONFIGURATION_BF4(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF4_SHIFT)) & ECAT_ESC_CONFIGURATION_BF4_MASK)
30856 
30857 #define ECAT_ESC_CONFIGURATION_BF5_MASK          (0x20U)
30858 #define ECAT_ESC_CONFIGURATION_BF5_SHIFT         (5U)
30859 /*! BF5 - Enhanced Link port 1:
30860  *  0b0..disabled (if bit 1=0)
30861  *  0b1..enabled
30862  */
30863 #define ECAT_ESC_CONFIGURATION_BF5(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF5_SHIFT)) & ECAT_ESC_CONFIGURATION_BF5_MASK)
30864 
30865 #define ECAT_ESC_CONFIGURATION_BF6_MASK          (0x40U)
30866 #define ECAT_ESC_CONFIGURATION_BF6_SHIFT         (6U)
30867 /*! BF6 - Reserved */
30868 #define ECAT_ESC_CONFIGURATION_BF6(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF6_SHIFT)) & ECAT_ESC_CONFIGURATION_BF6_MASK)
30869 
30870 #define ECAT_ESC_CONFIGURATION_BF7_MASK          (0x80U)
30871 #define ECAT_ESC_CONFIGURATION_BF7_SHIFT         (7U)
30872 /*! BF7 - Reserved */
30873 #define ECAT_ESC_CONFIGURATION_BF7(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_ESC_CONFIGURATION_BF7_SHIFT)) & ECAT_ESC_CONFIGURATION_BF7_MASK)
30874 /*! @} */
30875 
30876 /*! @name PDI_INFORMATION - PDI Information */
30877 /*! @{ */
30878 
30879 #define ECAT_PDI_INFORMATION_BF0_MASK            (0x1U)
30880 #define ECAT_PDI_INFORMATION_BF0_SHIFT           (0U)
30881 /*! BF0 - PDI function
30882  *  0b0..Disabled
30883  *  0b1..Enabled
30884  */
30885 #define ECAT_PDI_INFORMATION_BF0(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_INFORMATION_BF0_SHIFT)) & ECAT_PDI_INFORMATION_BF0_MASK)
30886 
30887 #define ECAT_PDI_INFORMATION_BF1_MASK            (0x2U)
30888 #define ECAT_PDI_INFORMATION_BF1_SHIFT           (1U)
30889 /*! BF1 - ESC configuration area loaded from EEPROM:
30890  *  0b0..not loaded
30891  *  0b1..loaded
30892  */
30893 #define ECAT_PDI_INFORMATION_BF1(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_INFORMATION_BF1_SHIFT)) & ECAT_PDI_INFORMATION_BF1_MASK)
30894 
30895 #define ECAT_PDI_INFORMATION_BF2_MASK            (0x4U)
30896 #define ECAT_PDI_INFORMATION_BF2_SHIFT           (2U)
30897 /*! BF2 - PDI active:
30898  *  0b0..PDI not active
30899  *  0b1..PDI active
30900  */
30901 #define ECAT_PDI_INFORMATION_BF2(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_INFORMATION_BF2_SHIFT)) & ECAT_PDI_INFORMATION_BF2_MASK)
30902 
30903 #define ECAT_PDI_INFORMATION_BF3_MASK            (0x8U)
30904 #define ECAT_PDI_INFORMATION_BF3_SHIFT           (3U)
30905 /*! BF3 - PDI configuration invalid:
30906  *  0b0..PDI configuration ok
30907  *  0b1..PDI configuration invalid
30908  */
30909 #define ECAT_PDI_INFORMATION_BF3(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_INFORMATION_BF3_SHIFT)) & ECAT_PDI_INFORMATION_BF3_MASK)
30910 
30911 #define ECAT_PDI_INFORMATION_BF4_MASK            (0xFFF0U)
30912 #define ECAT_PDI_INFORMATION_BF4_SHIFT           (4U)
30913 /*! BF4 - Reserved */
30914 #define ECAT_PDI_INFORMATION_BF4(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_INFORMATION_BF4_SHIFT)) & ECAT_PDI_INFORMATION_BF4_MASK)
30915 /*! @} */
30916 
30917 /*! @name PDI_ON_CHIP_BUS_CONFIGURATION - Register PDI On-chip bus configuration */
30918 /*! @{ */
30919 
30920 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF0_MASK (0x1FU)
30921 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF0_SHIFT (0U)
30922 /*! BF0 - On-chip bus clock:
30923  *  0b00000..asynchronous
30924  *  0b00001-0b11111..synchronous multiplication factor (N * 25 MHz)
30925  */
30926 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF0_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF0_MASK)
30927 
30928 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF5_MASK (0xE0U)
30929 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF5_SHIFT (5U)
30930 /*! BF5 - On-chip bus
30931  *  0b000..Intel® Avalon®
30932  *  0b001..AXI® 010: Xilinx® PLB v4.6
30933  *  0b100..Xilinx OPB
30934  */
30935 #define ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF5(x) (((uint8_t)(((uint8_t)(x)) << ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF5_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_CONFIGURATION_BF5_MASK)
30936 /*! @} */
30937 
30938 /*! @name SYNC_LATCH_1_AND_0_PDI_CONFIGURATION - PDI Configuration Sync Latch 1 and 0 PDI Configuration */
30939 /*! @{ */
30940 
30941 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF0_MASK (0x3U)
30942 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF0_SHIFT (0U)
30943 /*! BF0 - SYNC0 output driver/polarity:
30944  *  0b00..Push-Pull active low
30945  *  0b01..Open Drain (active low)
30946  *  0b10..Push-Pull active high
30947  *  0b11..Open Source (active high)
30948  */
30949 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF0_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF0_MASK)
30950 
30951 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF2_MASK (0x4U)
30952 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF2_SHIFT (2U)
30953 /*! BF2 - SYNC0/LATCH0 configuration*:
30954  *  0b0..LATCH0 Input
30955  *  0b1..SYNC0 Output
30956  */
30957 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF2_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF2_MASK)
30958 
30959 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF3_MASK (0x8U)
30960 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF3_SHIFT (3U)
30961 /*! BF3 - SYNC0 mapped to AL Event Request register 0x0220[2]:
30962  *  0b0..Disabled
30963  *  0b1..Enabled
30964  */
30965 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF3(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF3_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF3_MASK)
30966 
30967 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF4_MASK (0x30U)
30968 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF4_SHIFT (4U)
30969 /*! BF4 - SYNC1 output driver/polarity:
30970  *  0b00..Push-Pull active low
30971  *  0b01..Open Drain (active low)
30972  *  0b10..Push-Pull active high
30973  *  0b11..Open Source (active high)
30974  */
30975 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF4(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF4_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF4_MASK)
30976 
30977 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF6_MASK (0x40U)
30978 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF6_SHIFT (6U)
30979 /*! BF6 - SYNC1/LATCH1 configuration*
30980  *  0b0..LATCH1 input
30981  *  0b1..SYNC1 output
30982  */
30983 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF6(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF6_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF6_MASK)
30984 
30985 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF7_MASK (0x80U)
30986 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF7_SHIFT (7U)
30987 /*! BF7 - SYNC1 mapped to AL Event Request register 0x0220[3]:
30988  *  0b0..Disabled
30989  *  0b1..Enabled
30990  */
30991 #define ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF7(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF7_SHIFT)) & ECAT_SYNC_LATCH_1_AND_0_PDI_CONFIGURATION_BF7_MASK)
30992 /*! @} */
30993 
30994 /*! @name PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION - Register PDI On-chip bus extended configuration. */
30995 /*! @{ */
30996 
30997 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF0_MASK (0x3U)
30998 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF0_SHIFT (0U)
30999 /*! BF0 - Read prefetch size (in cycles of PDI width):
31000  *  0b00..4 cycles
31001  *  0b01..1 cycle (typical)
31002  *  0b10..2 cycles
31003  *  0b11..Reserved
31004  */
31005 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF0_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF0_MASK)
31006 
31007 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF2_MASK (0xFCU)
31008 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF2_SHIFT (2U)
31009 /*! BF2 - Reserved */
31010 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF2(x) (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF2_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF2_MASK)
31011 
31012 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF8_MASK (0x700U)
31013 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF8_SHIFT (8U)
31014 /*! BF8 - On-chip bus sub-type for AXI:
31015  *  0b000..AXI3
31016  *  0b001..AXI4
31017  *  0b010..AXI4 LITE
31018  */
31019 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF8(x) (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF8_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF8_MASK)
31020 
31021 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF11_MASK (0xF800U)
31022 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF11_SHIFT (11U)
31023 /*! BF11 - Reserved */
31024 #define ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF11(x) (((uint16_t)(((uint16_t)(x)) << ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF11_SHIFT)) & ECAT_PDI_ON_CHIP_BUS_EXTENDED_CONFIGURATION_BF11_MASK)
31025 /*! @} */
31026 
31027 /*! @name ECAT_EVENT_MASK - ECAT Event Mask */
31028 /*! @{ */
31029 
31030 #define ECAT_ECAT_EVENT_MASK_BF0_MASK            (0xFFFFU)
31031 #define ECAT_ECAT_EVENT_MASK_BF0_SHIFT           (0U)
31032 /*! BF0 - ECAT Event masking of the ECAT Event Request Events for mapping into ECAT event field of EtherCAT frames:
31033  *  0b0000000000000000..Corresponding ECAT Event Request register bit is not mapped
31034  *  0b0000000000000001..Corresponding ECAT Event Request register bit is mapped
31035  */
31036 #define ECAT_ECAT_EVENT_MASK_BF0(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_MASK_BF0_SHIFT)) & ECAT_ECAT_EVENT_MASK_BF0_MASK)
31037 /*! @} */
31038 
31039 /*! @name ECAT_EVENT_MASK_PDI - ECAT Event Mask */
31040 /*! @{ */
31041 
31042 #define ECAT_ECAT_EVENT_MASK_PDI_BF0_MASK        (0xFFFFU)
31043 #define ECAT_ECAT_EVENT_MASK_PDI_BF0_SHIFT       (0U)
31044 /*! BF0 - ECAT Event masking of the ECAT Event Request Events for mapping into ECAT event field of EtherCAT frames:
31045  *  0b0000000000000000..Corresponding ECAT Event Request register bit is not mapped
31046  *  0b0000000000000001..Corresponding ECAT Event Request register bit is mapped
31047  */
31048 #define ECAT_ECAT_EVENT_MASK_PDI_BF0(x)          (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_MASK_PDI_BF0_SHIFT)) & ECAT_ECAT_EVENT_MASK_PDI_BF0_MASK)
31049 /*! @} */
31050 
31051 /*! @name PDI_AL_EVENT_MASK - PDI AL Event Mask */
31052 /*! @{ */
31053 
31054 #define ECAT_PDI_AL_EVENT_MASK_BF0_MASK          (0xFFFFFFFFU)
31055 #define ECAT_PDI_AL_EVENT_MASK_BF0_SHIFT         (0U)
31056 /*! BF0 - AL Event masking of the AL Event Request register Events for mapping to PDI IRQ signal:
31057  *  0b00000000000000000000000000000000..Corresponding AL Event Request register bit is not mapped
31058  *  0b00000000000000000000000000000001..Corresponding AL Event Request register bit is mapped
31059  */
31060 #define ECAT_PDI_AL_EVENT_MASK_BF0(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_PDI_AL_EVENT_MASK_BF0_SHIFT)) & ECAT_PDI_AL_EVENT_MASK_BF0_MASK)
31061 /*! @} */
31062 
31063 /*! @name PDI_AL_EVENT_MASK_PDI - PDI AL Event Mask */
31064 /*! @{ */
31065 
31066 #define ECAT_PDI_AL_EVENT_MASK_PDI_BF0_MASK      (0xFFFFFFFFU)
31067 #define ECAT_PDI_AL_EVENT_MASK_PDI_BF0_SHIFT     (0U)
31068 /*! BF0 - AL Event masking of the AL Event Request register Events for mapping to PDI IRQ signal:
31069  *  0b00000000000000000000000000000000..Corresponding AL Event Request register bit is not mapped
31070  *  0b00000000000000000000000000000001..Corresponding AL Event Request register bit is mapped
31071  */
31072 #define ECAT_PDI_AL_EVENT_MASK_PDI_BF0(x)        (((uint32_t)(((uint32_t)(x)) << ECAT_PDI_AL_EVENT_MASK_PDI_BF0_SHIFT)) & ECAT_PDI_AL_EVENT_MASK_PDI_BF0_MASK)
31073 /*! @} */
31074 
31075 /*! @name ECAT_EVENT_REQUEST - ECAT Event Request */
31076 /*! @{ */
31077 
31078 #define ECAT_ECAT_EVENT_REQUEST_BF0_MASK         (0x1U)
31079 #define ECAT_ECAT_EVENT_REQUEST_BF0_SHIFT        (0U)
31080 /*! BF0 - DC Latch event:
31081  *  0b0..No change on DC Latch Inputs
31082  *  0b1..At least one change on DC Latch Inputs
31083  */
31084 #define ECAT_ECAT_EVENT_REQUEST_BF0(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF0_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF0_MASK)
31085 
31086 #define ECAT_ECAT_EVENT_REQUEST_BF1_MASK         (0x2U)
31087 #define ECAT_ECAT_EVENT_REQUEST_BF1_SHIFT        (1U)
31088 /*! BF1 - Reserved */
31089 #define ECAT_ECAT_EVENT_REQUEST_BF1(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF1_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF1_MASK)
31090 
31091 #define ECAT_ECAT_EVENT_REQUEST_BF2_MASK         (0x4U)
31092 #define ECAT_ECAT_EVENT_REQUEST_BF2_SHIFT        (2U)
31093 /*! BF2 - DL Status event:
31094  *  0b0..No change in DL Status
31095  *  0b1..DL Status change
31096  */
31097 #define ECAT_ECAT_EVENT_REQUEST_BF2(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF2_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF2_MASK)
31098 
31099 #define ECAT_ECAT_EVENT_REQUEST_BF3_MASK         (0x8U)
31100 #define ECAT_ECAT_EVENT_REQUEST_BF3_SHIFT        (3U)
31101 /*! BF3 - AL Status event:
31102  *  0b0..No change in AL Status
31103  *  0b1..AL Status change
31104  */
31105 #define ECAT_ECAT_EVENT_REQUEST_BF3(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF3_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF3_MASK)
31106 
31107 #define ECAT_ECAT_EVENT_REQUEST_BF4_MASK         (0x10U)
31108 #define ECAT_ECAT_EVENT_REQUEST_BF4_SHIFT        (4U)
31109 /*! BF4 - Mirrors values of each SyncManager Status:
31110  *  0b0..No Sync Channel 0 event
31111  *  0b1..Sync Channel 0 event pending
31112  */
31113 #define ECAT_ECAT_EVENT_REQUEST_BF4(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF4_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF4_MASK)
31114 
31115 #define ECAT_ECAT_EVENT_REQUEST_BF5_MASK         (0x20U)
31116 #define ECAT_ECAT_EVENT_REQUEST_BF5_SHIFT        (5U)
31117 /*! BF5 - Mirrors values of each SyncManager Status:
31118  *  0b0..No Sync Channel 1 event
31119  *  0b1..Sync Channel 1 event pending
31120  */
31121 #define ECAT_ECAT_EVENT_REQUEST_BF5(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF5_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF5_MASK)
31122 
31123 #define ECAT_ECAT_EVENT_REQUEST_BF6_MASK         (0x40U)
31124 #define ECAT_ECAT_EVENT_REQUEST_BF6_SHIFT        (6U)
31125 /*! BF6 - Mirrors values of each SyncManager Status:
31126  *  0b0..No Sync Channel 2 event
31127  *  0b1..Sync Channel 2 event pending
31128  */
31129 #define ECAT_ECAT_EVENT_REQUEST_BF6(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF6_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF6_MASK)
31130 
31131 #define ECAT_ECAT_EVENT_REQUEST_BF7_MASK         (0x80U)
31132 #define ECAT_ECAT_EVENT_REQUEST_BF7_SHIFT        (7U)
31133 /*! BF7 - Mirrors values of each SyncManager Status:
31134  *  0b0..No Sync Channel 3 event
31135  *  0b1..Sync Channel 3 event pending
31136  */
31137 #define ECAT_ECAT_EVENT_REQUEST_BF7(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF7_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF7_MASK)
31138 
31139 #define ECAT_ECAT_EVENT_REQUEST_BF8_MASK         (0x100U)
31140 #define ECAT_ECAT_EVENT_REQUEST_BF8_SHIFT        (8U)
31141 /*! BF8 - Mirrors values of each SyncManager Status:
31142  *  0b0..No Sync Channel 4 event
31143  *  0b1..Sync Channel 4 event pending
31144  */
31145 #define ECAT_ECAT_EVENT_REQUEST_BF8(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF8_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF8_MASK)
31146 
31147 #define ECAT_ECAT_EVENT_REQUEST_BF9_MASK         (0x200U)
31148 #define ECAT_ECAT_EVENT_REQUEST_BF9_SHIFT        (9U)
31149 /*! BF9 - Mirrors values of each SyncManager Status:
31150  *  0b0..No Sync Channel 5 event
31151  *  0b1..Sync Channel 5 event pending
31152  */
31153 #define ECAT_ECAT_EVENT_REQUEST_BF9(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF9_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF9_MASK)
31154 
31155 #define ECAT_ECAT_EVENT_REQUEST_BF10_MASK        (0x400U)
31156 #define ECAT_ECAT_EVENT_REQUEST_BF10_SHIFT       (10U)
31157 /*! BF10 - Mirrors values of each SyncManager Status:
31158  *  0b0..No Sync Channel 6 event
31159  *  0b1..Sync Channel 6 event pending
31160  */
31161 #define ECAT_ECAT_EVENT_REQUEST_BF10(x)          (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF10_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF10_MASK)
31162 
31163 #define ECAT_ECAT_EVENT_REQUEST_BF11_MASK        (0x800U)
31164 #define ECAT_ECAT_EVENT_REQUEST_BF11_SHIFT       (11U)
31165 /*! BF11 - Mirrors values of each SyncManager Status:
31166  *  0b0..No Sync Channel 7 event
31167  *  0b1..Sync Channel 7 event pending
31168  */
31169 #define ECAT_ECAT_EVENT_REQUEST_BF11(x)          (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF11_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF11_MASK)
31170 
31171 #define ECAT_ECAT_EVENT_REQUEST_BF12_MASK        (0xF000U)
31172 #define ECAT_ECAT_EVENT_REQUEST_BF12_SHIFT       (12U)
31173 /*! BF12 - Reserved */
31174 #define ECAT_ECAT_EVENT_REQUEST_BF12(x)          (((uint16_t)(((uint16_t)(x)) << ECAT_ECAT_EVENT_REQUEST_BF12_SHIFT)) & ECAT_ECAT_EVENT_REQUEST_BF12_MASK)
31175 /*! @} */
31176 
31177 /*! @name AL_EVENT_REQUEST - AL Event request */
31178 /*! @{ */
31179 
31180 #define ECAT_AL_EVENT_REQUEST_BF0_MASK           (0x1U)
31181 #define ECAT_AL_EVENT_REQUEST_BF0_SHIFT          (0U)
31182 /*! BF0 - AL Control event:
31183  *  0b0..No AL Control Register change
31184  *  0b1..AL Control Register has been written3
31185  */
31186 #define ECAT_AL_EVENT_REQUEST_BF0(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF0_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF0_MASK)
31187 
31188 #define ECAT_AL_EVENT_REQUEST_BF1_MASK           (0x2U)
31189 #define ECAT_AL_EVENT_REQUEST_BF1_SHIFT          (1U)
31190 /*! BF1 - DC Latch event:
31191  *  0b0..No change on DC Latch Inputs
31192  *  0b1..At least one change on DC Latch Inputs
31193  */
31194 #define ECAT_AL_EVENT_REQUEST_BF1(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF1_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF1_MASK)
31195 
31196 #define ECAT_AL_EVENT_REQUEST_BF2_MASK           (0x4U)
31197 #define ECAT_AL_EVENT_REQUEST_BF2_SHIFT          (2U)
31198 /*! BF2 - State of DC SYNC0 (if register 0x0151[3]=1): */
31199 #define ECAT_AL_EVENT_REQUEST_BF2(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF2_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF2_MASK)
31200 
31201 #define ECAT_AL_EVENT_REQUEST_BF3_MASK           (0x8U)
31202 #define ECAT_AL_EVENT_REQUEST_BF3_SHIFT          (3U)
31203 /*! BF3 - State of DC SYNC1 (if register 0x0151[7]=1): */
31204 #define ECAT_AL_EVENT_REQUEST_BF3(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF3_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF3_MASK)
31205 
31206 #define ECAT_AL_EVENT_REQUEST_BF4_MASK           (0x10U)
31207 #define ECAT_AL_EVENT_REQUEST_BF4_SHIFT          (4U)
31208 /*! BF4 - SyncManager activation register (SyncManager register offset 0x6) changed:
31209  *  0b0..No change in any SyncManager
31210  *  0b1..At least one SyncManager changed
31211  */
31212 #define ECAT_AL_EVENT_REQUEST_BF4(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF4_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF4_MASK)
31213 
31214 #define ECAT_AL_EVENT_REQUEST_BF5_MASK           (0x20U)
31215 #define ECAT_AL_EVENT_REQUEST_BF5_SHIFT          (5U)
31216 /*! BF5 - EEPROM Emulation:
31217  *  0b0..No command pending
31218  *  0b1..EEPROM command pending
31219  */
31220 #define ECAT_AL_EVENT_REQUEST_BF5(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF5_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF5_MASK)
31221 
31222 #define ECAT_AL_EVENT_REQUEST_BF6_MASK           (0x40U)
31223 #define ECAT_AL_EVENT_REQUEST_BF6_SHIFT          (6U)
31224 /*! BF6 - Watchdog Process Data:
31225  *  0b0..Has not expired
31226  *  0b1..Has expired
31227  */
31228 #define ECAT_AL_EVENT_REQUEST_BF6(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF6_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF6_MASK)
31229 
31230 #define ECAT_AL_EVENT_REQUEST_BF7_MASK           (0x80U)
31231 #define ECAT_AL_EVENT_REQUEST_BF7_SHIFT          (7U)
31232 /*! BF7 - Reserved */
31233 #define ECAT_AL_EVENT_REQUEST_BF7(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF7_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF7_MASK)
31234 
31235 #define ECAT_AL_EVENT_REQUEST_BF8_MASK           (0x100U)
31236 #define ECAT_AL_EVENT_REQUEST_BF8_SHIFT          (8U)
31237 /*! BF8 - SyncManager interrupts (SyncManager register offset 0x5, bit [0] or [1]):
31238  *  0b0..No SyncManager 0 interrupt
31239  *  0b1..SyncManager 0 interrupt pending
31240  */
31241 #define ECAT_AL_EVENT_REQUEST_BF8(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF8_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF8_MASK)
31242 
31243 #define ECAT_AL_EVENT_REQUEST_BF9_MASK           (0x200U)
31244 #define ECAT_AL_EVENT_REQUEST_BF9_SHIFT          (9U)
31245 /*! BF9 - Bit field access for ECAT: r/-
31246  *  0b0..No SyncManager 1 interrupt
31247  *  0b1..SyncManager 1 interrupt pending
31248  */
31249 #define ECAT_AL_EVENT_REQUEST_BF9(x)             (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF9_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF9_MASK)
31250 
31251 #define ECAT_AL_EVENT_REQUEST_BF10_MASK          (0x400U)
31252 #define ECAT_AL_EVENT_REQUEST_BF10_SHIFT         (10U)
31253 /*! BF10 - Bit field access for ECAT: r/-
31254  *  0b0..No SyncManager2 interrupt
31255  *  0b1..SyncManager 2 interrupt pending
31256  */
31257 #define ECAT_AL_EVENT_REQUEST_BF10(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF10_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF10_MASK)
31258 
31259 #define ECAT_AL_EVENT_REQUEST_BF11_MASK          (0x800U)
31260 #define ECAT_AL_EVENT_REQUEST_BF11_SHIFT         (11U)
31261 /*! BF11 - Bit field access for ECAT: r/-
31262  *  0b0..No SyncManager 3 interrupt
31263  *  0b1..SyncManager 3 interrupt pending
31264  */
31265 #define ECAT_AL_EVENT_REQUEST_BF11(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF11_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF11_MASK)
31266 
31267 #define ECAT_AL_EVENT_REQUEST_BF12_MASK          (0x1000U)
31268 #define ECAT_AL_EVENT_REQUEST_BF12_SHIFT         (12U)
31269 /*! BF12 - Bit field access for ECAT: r/-
31270  *  0b0..No SyncManager4 interrupt
31271  *  0b1..SyncManager 4 interrupt pending
31272  */
31273 #define ECAT_AL_EVENT_REQUEST_BF12(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF12_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF12_MASK)
31274 
31275 #define ECAT_AL_EVENT_REQUEST_BF13_MASK          (0x2000U)
31276 #define ECAT_AL_EVENT_REQUEST_BF13_SHIFT         (13U)
31277 /*! BF13 - Bit field access for ECAT: r/-
31278  *  0b0..No SyncManager 5 interrupt
31279  *  0b1..SyncManager 5 interrupt pending
31280  */
31281 #define ECAT_AL_EVENT_REQUEST_BF13(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF13_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF13_MASK)
31282 
31283 #define ECAT_AL_EVENT_REQUEST_BF14_MASK          (0x4000U)
31284 #define ECAT_AL_EVENT_REQUEST_BF14_SHIFT         (14U)
31285 /*! BF14 - Bit field access for ECAT: r/-
31286  *  0b0..No SyncManager 6 interrupt
31287  *  0b1..SyncManager6 interrupt pending
31288  */
31289 #define ECAT_AL_EVENT_REQUEST_BF14(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF14_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF14_MASK)
31290 
31291 #define ECAT_AL_EVENT_REQUEST_BF15_MASK          (0x8000U)
31292 #define ECAT_AL_EVENT_REQUEST_BF15_SHIFT         (15U)
31293 /*! BF15 - Bit field access for ECAT: r/-
31294  *  0b0..No SyncManager 7 interrupt
31295  *  0b1..SyncManager 7 interrupt pending
31296  */
31297 #define ECAT_AL_EVENT_REQUEST_BF15(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF15_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF15_MASK)
31298 
31299 #define ECAT_AL_EVENT_REQUEST_BF16_MASK          (0xFFFF0000U)
31300 #define ECAT_AL_EVENT_REQUEST_BF16_SHIFT         (16U)
31301 /*! BF16 - Reserved */
31302 #define ECAT_AL_EVENT_REQUEST_BF16(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_AL_EVENT_REQUEST_BF16_SHIFT)) & ECAT_AL_EVENT_REQUEST_BF16_MASK)
31303 /*! @} */
31304 
31305 /*! @name RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT - RX Error Counter */
31306 /*! @{ */
31307 
31308 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF0_MASK (0xFFU)
31309 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF0_SHIFT (0U)
31310 /*! BF0 - Invalid frame counter of Port y (counting is stopped when 0xFF is reached). */
31311 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF0_SHIFT)) & ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF0_MASK)
31312 
31313 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF8_MASK (0xFF00U)
31314 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF8_SHIFT (8U)
31315 /*! BF8 - RX Error counter of Port y (counting is stopped when 0xFF is reached). */
31316 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF8(x) (((uint16_t)(((uint16_t)(x)) << ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF8_SHIFT)) & ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_BF8_MASK)
31317 /*! @} */
31318 
31319 /* The count of ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT */
31320 #define ECAT_RX_ERROR_COUNT_E                    (2U)
31321 
31322 /*! @name RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI - RX Error Counter */
31323 /*! @{ */
31324 
31325 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF0_MASK (0xFFU)
31326 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF0_SHIFT (0U)
31327 /*! BF0 - Invalid frame counter of Port y (counting is stopped when 0xFF is reached). */
31328 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF0_SHIFT)) & ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF0_MASK)
31329 
31330 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF8_MASK (0xFF00U)
31331 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF8_SHIFT (8U)
31332 /*! BF8 - RX Error counter of Port y (counting is stopped when 0xFF is reached). */
31333 #define ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF8(x) (((uint16_t)(((uint16_t)(x)) << ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF8_SHIFT)) & ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI_BF8_MASK)
31334 /*! @} */
31335 
31336 /* The count of ECAT_RX_ERROR_CNTR_RX_ERROR_COUNTER_PORT_PDI */
31337 #define ECAT_RX_ERROR_COUNT_P                    (2U)
31338 
31339 /*! @name FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT - Forwarded RX Error Counter */
31340 /*! @{ */
31341 
31342 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_BF0_MASK (0xFFU)
31343 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_BF0_SHIFT (0U)
31344 /*! BF0 - Forwarded error counter of Port y (counting is stopped when 0xFF is reached). */
31345 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_BF0_SHIFT)) & ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_BF0_MASK)
31346 /*! @} */
31347 
31348 /* The count of ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT */
31349 #define ECAT_FORWARDED_RX_ERROR_COUNT_E          (2U)
31350 
31351 /*! @name FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI - Forwarded RX Error Counter */
31352 /*! @{ */
31353 
31354 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI_BF0_MASK (0xFFU)
31355 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI_BF0_SHIFT (0U)
31356 /*! BF0 - Forwarded error counter of Port y (counting is stopped when 0xFF is reached). */
31357 #define ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI_BF0_SHIFT)) & ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI_BF0_MASK)
31358 /*! @} */
31359 
31360 /* The count of ECAT_FORWARDED_RX_ERROR_CNTR_FORWARDED_RX_ERROR_COUNTER_PORT_PDI */
31361 #define ECAT_FORWARDED_RX_ERROR_COUNT_P          (2U)
31362 
31363 /*! @name ECAT_PROCESSING_UNIT_ERROR_COUNTER - ECAT Processing Unit Error Counter */
31364 /*! @{ */
31365 
31366 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_BF0_MASK (0xFFU)
31367 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_BF0_SHIFT (0U)
31368 /*! BF0 - ECAT Processing Unit error counter (counting is stopped when 0xFF is reached). Counts
31369  *    errors of frames passing the Processing Unit.
31370  */
31371 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_BF0_SHIFT)) & ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_BF0_MASK)
31372 /*! @} */
31373 
31374 /*! @name ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI - ECAT Processing Unit Error Counter */
31375 /*! @{ */
31376 
31377 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI_BF0_MASK (0xFFU)
31378 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI_BF0_SHIFT (0U)
31379 /*! BF0 - ECAT Processing Unit error counter (counting is stopped when 0xFF is reached). Counts
31380  *    errors of frames passing the Processing Unit.
31381  */
31382 #define ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI_BF0_SHIFT)) & ECAT_ECAT_PROCESSING_UNIT_ERROR_COUNTER_PDI_BF0_MASK)
31383 /*! @} */
31384 
31385 /*! @name PDI_ERROR_COUNTER - PDI Error counter */
31386 /*! @{ */
31387 
31388 #define ECAT_PDI_ERROR_COUNTER_BF0_MASK          (0xFFU)
31389 #define ECAT_PDI_ERROR_COUNTER_BF0_SHIFT         (0U)
31390 /*! BF0 - PDI Error counter (counting is stopped when 0xFF is reached). Counts if a PDI access has an interface error. */
31391 #define ECAT_PDI_ERROR_COUNTER_BF0(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_PDI_ERROR_COUNTER_BF0_SHIFT)) & ECAT_PDI_ERROR_COUNTER_BF0_MASK)
31392 /*! @} */
31393 
31394 /*! @name PDI_ERROR_COUNTER_PDI - PDI Error counter */
31395 /*! @{ */
31396 
31397 #define ECAT_PDI_ERROR_COUNTER_PDI_BF0_MASK      (0xFFU)
31398 #define ECAT_PDI_ERROR_COUNTER_PDI_BF0_SHIFT     (0U)
31399 /*! BF0 - PDI Error counter (counting is stopped when 0xFF is reached). Counts if a PDI access has an interface error. */
31400 #define ECAT_PDI_ERROR_COUNTER_PDI_BF0(x)        (((uint8_t)(((uint8_t)(x)) << ECAT_PDI_ERROR_COUNTER_PDI_BF0_SHIFT)) & ECAT_PDI_ERROR_COUNTER_PDI_BF0_MASK)
31401 /*! @} */
31402 
31403 /*! @name ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER - ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_PDI_ERROR_CODE. */
31404 /*! @{ */
31405 
31406 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF0_MASK (0x1U)
31407 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF0_SHIFT (0U)
31408 /*! BF0 - Busy violation during read access
31409  *  0b0..no error
31410  *  0b1..error detected
31411  */
31412 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF0_SHIFT)) & ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF0_MASK)
31413 
31414 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF1_MASK (0x2U)
31415 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF1_SHIFT (1U)
31416 /*! BF1 - Busy violation during write access
31417  *  0b0..no error
31418  *  0b1..error detected
31419  */
31420 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF1_SHIFT)) & ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF1_MASK)
31421 
31422 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF2_MASK (0x4U)
31423 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF2_SHIFT (2U)
31424 /*! BF2 - Addressing error for a read access (odd address without BHE)
31425  *  0b0..no error
31426  *  0b1..error detected
31427  */
31428 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF2_SHIFT)) & ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF2_MASK)
31429 
31430 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF3_MASK (0x8U)
31431 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF3_SHIFT (3U)
31432 /*! BF3 - Addressing error for a write access (odd address without BHE)
31433  *  0b0..no error
31434  *  0b1..error detected
31435  */
31436 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF3(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF3_SHIFT)) & ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF3_MASK)
31437 
31438 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF4_MASK (0xF0U)
31439 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF4_SHIFT (4U)
31440 /*! BF4 - reserved */
31441 #define ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF4(x) (((uint8_t)(((uint8_t)(x)) << ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF4_SHIFT)) & ECAT_ASYNCHRONOUS_SYNCHRONOUS_MICROCONTROLLER_BF4_MASK)
31442 /*! @} */
31443 
31444 /*! @name LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT - Lost Link Counter */
31445 /*! @{ */
31446 
31447 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_BF0_MASK (0xFFU)
31448 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_BF0_SHIFT (0U)
31449 /*! BF0 - Lost Link counter of Port y (counting is stopped when 0xff is reached). */
31450 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_BF0_SHIFT)) & ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_BF0_MASK)
31451 /*! @} */
31452 
31453 /* The count of ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT */
31454 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_COUNT (2U)
31455 
31456 /*! @name LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI - Lost Link Counter */
31457 /*! @{ */
31458 
31459 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_BF0_MASK (0xFFU)
31460 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_BF0_SHIFT (0U)
31461 /*! BF0 - Lost Link counter of Port y (counting is stopped when 0xff is reached). */
31462 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_BF0_SHIFT)) & ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_BF0_MASK)
31463 /*! @} */
31464 
31465 /* The count of ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI */
31466 #define ECAT_LOST_LINK_CNTR_LOST_LINK_COUNTER_PORT_PDI_COUNT (2U)
31467 
31468 /*! @name WATCHDOG_DIVIDER - Watchdog Divider */
31469 /*! @{ */
31470 
31471 #define ECAT_WATCHDOG_DIVIDER_BF0_MASK           (0xFFFFU)
31472 #define ECAT_WATCHDOG_DIVIDER_BF0_SHIFT          (0U)
31473 /*! BF0 - Watchdog divider: Number of 25 MHz tics (minus 2) that represent the basic watchdog
31474  *    increment. (Default value is 100us = 2498)
31475  */
31476 #define ECAT_WATCHDOG_DIVIDER_BF0(x)             (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_DIVIDER_BF0_SHIFT)) & ECAT_WATCHDOG_DIVIDER_BF0_MASK)
31477 /*! @} */
31478 
31479 /*! @name WATCHDOG_DIVIDER_PDI - Watchdog Divider */
31480 /*! @{ */
31481 
31482 #define ECAT_WATCHDOG_DIVIDER_PDI_BF0_MASK       (0xFFFFU)
31483 #define ECAT_WATCHDOG_DIVIDER_PDI_BF0_SHIFT      (0U)
31484 /*! BF0 - Watchdog divider: Number of 25 MHz tics (minus 2) that represent the basic watchdog
31485  *    increment. (Default value is 100us = 2498)
31486  */
31487 #define ECAT_WATCHDOG_DIVIDER_PDI_BF0(x)         (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_DIVIDER_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_DIVIDER_PDI_BF0_MASK)
31488 /*! @} */
31489 
31490 /*! @name WATCHDOG_TIME_PDI - Register Watchdog Time PDI */
31491 /*! @{ */
31492 
31493 #define ECAT_WATCHDOG_TIME_PDI_BF0_MASK          (0xFFFFU)
31494 #define ECAT_WATCHDOG_TIME_PDI_BF0_SHIFT         (0U)
31495 /*! BF0 - Watchdog Time PDI: number or basic watchdog increments (Default value with Watchdog divider 100us means 100ms Watchdog) */
31496 #define ECAT_WATCHDOG_TIME_PDI_BF0(x)            (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_TIME_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_TIME_PDI_BF0_MASK)
31497 /*! @} */
31498 
31499 /*! @name WATCHDOG_TIME_PDI_PDI - Register Watchdog Time PDI */
31500 /*! @{ */
31501 
31502 #define ECAT_WATCHDOG_TIME_PDI_PDI_BF0_MASK      (0xFFFFU)
31503 #define ECAT_WATCHDOG_TIME_PDI_PDI_BF0_SHIFT     (0U)
31504 /*! BF0 - Watchdog Time PDI: number or basic watchdog increments (Default value with Watchdog divider 100us means 100ms Watchdog) */
31505 #define ECAT_WATCHDOG_TIME_PDI_PDI_BF0(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_TIME_PDI_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_TIME_PDI_PDI_BF0_MASK)
31506 /*! @} */
31507 
31508 /*! @name WATCHDOG_TIME_PROCESS_DATA - Regsister Watchdog Time Process Data */
31509 /*! @{ */
31510 
31511 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_BF0_MASK (0xFFFFU)
31512 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_BF0_SHIFT (0U)
31513 /*! BF0 - Watchdog Time Process Data */
31514 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_BF0(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_TIME_PROCESS_DATA_BF0_SHIFT)) & ECAT_WATCHDOG_TIME_PROCESS_DATA_BF0_MASK)
31515 /*! @} */
31516 
31517 /*! @name WATCHDOG_TIME_PROCESS_DATA_PDI - Regsister Watchdog Time Process Data */
31518 /*! @{ */
31519 
31520 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_PDI_BF0_MASK (0xFFFFU)
31521 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_PDI_BF0_SHIFT (0U)
31522 /*! BF0 - Watchdog Time Process Data */
31523 #define ECAT_WATCHDOG_TIME_PROCESS_DATA_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_TIME_PROCESS_DATA_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_TIME_PROCESS_DATA_PDI_BF0_MASK)
31524 /*! @} */
31525 
31526 /*! @name WATCHDOG_STATUS_PROCESS_DATA - Watchdog Status Process Data */
31527 /*! @{ */
31528 
31529 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF0_MASK (0x1U)
31530 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF0_SHIFT (0U)
31531 /*! BF0 - Watchdog Status of Process Data (triggered by SyncManagers)
31532  *  0b0..Watchdog Process Data expired
31533  *  0b1..Watchdog Process Data is active or disabled
31534  */
31535 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF0_SHIFT)) & ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF0_MASK)
31536 
31537 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF1_MASK (0xFFFEU)
31538 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF1_SHIFT (1U)
31539 /*! BF1 - Reserved */
31540 #define ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF1(x) (((uint16_t)(((uint16_t)(x)) << ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF1_SHIFT)) & ECAT_WATCHDOG_STATUS_PROCESS_DATA_BF1_MASK)
31541 /*! @} */
31542 
31543 /*! @name WATCHDOG_COUNTER_PROCESS_DATA - Watchdog Counter Process Data */
31544 /*! @{ */
31545 
31546 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_BF0_MASK (0xFFU)
31547 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_BF0_SHIFT (0U)
31548 /*! BF0 - Watchdog Counter Process Data (counting is stopped when 0xFF is reached). Counts if Process Data Watchdog expires. */
31549 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_WATCHDOG_COUNTER_PROCESS_DATA_BF0_SHIFT)) & ECAT_WATCHDOG_COUNTER_PROCESS_DATA_BF0_MASK)
31550 /*! @} */
31551 
31552 /*! @name WATCHDOG_COUNTER_PROCESS_DATA_PDI - Watchdog Counter Process Data */
31553 /*! @{ */
31554 
31555 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_PDI_BF0_MASK (0xFFU)
31556 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_PDI_BF0_SHIFT (0U)
31557 /*! BF0 - Watchdog Counter Process Data (counting is stopped when 0xFF is reached). Counts if Process Data Watchdog expires. */
31558 #define ECAT_WATCHDOG_COUNTER_PROCESS_DATA_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_WATCHDOG_COUNTER_PROCESS_DATA_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_COUNTER_PROCESS_DATA_PDI_BF0_MASK)
31559 /*! @} */
31560 
31561 /*! @name WATCHDOG_COUNTER_PDI - Watchdog Counter PDI */
31562 /*! @{ */
31563 
31564 #define ECAT_WATCHDOG_COUNTER_PDI_BF0_MASK       (0xFFU)
31565 #define ECAT_WATCHDOG_COUNTER_PDI_BF0_SHIFT      (0U)
31566 /*! BF0 - Watchdog PDI counter (counting is stopped when 0xFF is reached). */
31567 #define ECAT_WATCHDOG_COUNTER_PDI_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_WATCHDOG_COUNTER_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_COUNTER_PDI_BF0_MASK)
31568 /*! @} */
31569 
31570 /*! @name WATCHDOG_COUNTER_PDI_PDI - Watchdog Counter PDI */
31571 /*! @{ */
31572 
31573 #define ECAT_WATCHDOG_COUNTER_PDI_PDI_BF0_MASK   (0xFFU)
31574 #define ECAT_WATCHDOG_COUNTER_PDI_PDI_BF0_SHIFT  (0U)
31575 /*! BF0 - Watchdog PDI counter (counting is stopped when 0xFF is reached). */
31576 #define ECAT_WATCHDOG_COUNTER_PDI_PDI_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_WATCHDOG_COUNTER_PDI_PDI_BF0_SHIFT)) & ECAT_WATCHDOG_COUNTER_PDI_PDI_BF0_MASK)
31577 /*! @} */
31578 
31579 /*! @name EEPROM_CONFIGURATION - EEPROM Configuration */
31580 /*! @{ */
31581 
31582 #define ECAT_EEPROM_CONFIGURATION_BF0_MASK       (0x1U)
31583 #define ECAT_EEPROM_CONFIGURATION_BF0_SHIFT      (0U)
31584 /*! BF0 - EEPROM control is offered to PDI
31585  *  0b0..no
31586  *  0b1..yes (PDI has EEPROM control)
31587  */
31588 #define ECAT_EEPROM_CONFIGURATION_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_BF0_SHIFT)) & ECAT_EEPROM_CONFIGURATION_BF0_MASK)
31589 
31590 #define ECAT_EEPROM_CONFIGURATION_BF1_MASK       (0x2U)
31591 #define ECAT_EEPROM_CONFIGURATION_BF1_SHIFT      (1U)
31592 /*! BF1 - Force ECAT access
31593  *  0b0..Do not change Bit 0x0501[0]
31594  *  0b1..Reset Bit 0x0501[0] to 0
31595  */
31596 #define ECAT_EEPROM_CONFIGURATION_BF1(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_BF1_SHIFT)) & ECAT_EEPROM_CONFIGURATION_BF1_MASK)
31597 
31598 #define ECAT_EEPROM_CONFIGURATION_BF2_MASK       (0xFCU)
31599 #define ECAT_EEPROM_CONFIGURATION_BF2_SHIFT      (2U)
31600 /*! BF2 - Reserved, write 0 */
31601 #define ECAT_EEPROM_CONFIGURATION_BF2(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_BF2_SHIFT)) & ECAT_EEPROM_CONFIGURATION_BF2_MASK)
31602 /*! @} */
31603 
31604 /*! @name EEPROM_CONFIGURATION_PDI - EEPROM Configuration */
31605 /*! @{ */
31606 
31607 #define ECAT_EEPROM_CONFIGURATION_PDI_BF0_MASK   (0x1U)
31608 #define ECAT_EEPROM_CONFIGURATION_PDI_BF0_SHIFT  (0U)
31609 /*! BF0 - EEPROM control is offered to PDI
31610  *  0b0..no
31611  *  0b1..yes (PDI has EEPROM control)
31612  */
31613 #define ECAT_EEPROM_CONFIGURATION_PDI_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_PDI_BF0_SHIFT)) & ECAT_EEPROM_CONFIGURATION_PDI_BF0_MASK)
31614 
31615 #define ECAT_EEPROM_CONFIGURATION_PDI_BF1_MASK   (0x2U)
31616 #define ECAT_EEPROM_CONFIGURATION_PDI_BF1_SHIFT  (1U)
31617 /*! BF1 - Force ECAT access
31618  *  0b0..Do not change Bit 0x0501[0]
31619  *  0b1..Reset Bit 0x0501[0] to 0
31620  */
31621 #define ECAT_EEPROM_CONFIGURATION_PDI_BF1(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_PDI_BF1_SHIFT)) & ECAT_EEPROM_CONFIGURATION_PDI_BF1_MASK)
31622 
31623 #define ECAT_EEPROM_CONFIGURATION_PDI_BF2_MASK   (0xFCU)
31624 #define ECAT_EEPROM_CONFIGURATION_PDI_BF2_SHIFT  (2U)
31625 /*! BF2 - Reserved, write 0 */
31626 #define ECAT_EEPROM_CONFIGURATION_PDI_BF2(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_EEPROM_CONFIGURATION_PDI_BF2_SHIFT)) & ECAT_EEPROM_CONFIGURATION_PDI_BF2_MASK)
31627 /*! @} */
31628 
31629 /*! @name REGISTER_EEPROM_PDI_ACCESS_STATE - EEPROM PDI Access State */
31630 /*! @{ */
31631 
31632 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF0_MASK (0x1U)
31633 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF0_SHIFT (0U)
31634 /*! BF0 - Access to EEPROM:
31635  *  0b0..PDI releases EEPROM access
31636  *  0b1..PDI takes EEPROM access (PDI has EEPROM control)
31637  */
31638 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF0_SHIFT)) & ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF0_MASK)
31639 
31640 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF1_MASK (0xFEU)
31641 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF1_SHIFT (1U)
31642 /*! BF1 - Reserved, write 0 */
31643 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF1_SHIFT)) & ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_BF1_MASK)
31644 /*! @} */
31645 
31646 /*! @name REGISTER_EEPROM_PDI_ACCESS_STATE_PDI - EEPROM PDI Access State */
31647 /*! @{ */
31648 
31649 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF0_MASK (0x1U)
31650 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF0_SHIFT (0U)
31651 /*! BF0 - Access to EEPROM:
31652  *  0b0..PDI releases EEPROM access
31653  *  0b1..PDI takes EEPROM access (PDI has EEPROM control)
31654  */
31655 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF0_SHIFT)) & ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF0_MASK)
31656 
31657 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF1_MASK (0xFEU)
31658 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF1_SHIFT (1U)
31659 /*! BF1 - Reserved, write 0 */
31660 #define ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF1_SHIFT)) & ECAT_REGISTER_EEPROM_PDI_ACCESS_STATE_PDI_BF1_MASK)
31661 /*! @} */
31662 
31663 /*! @name EEPROM_CONTROL_STATUS - Register EEPROM Control/Status */
31664 /*! @{ */
31665 
31666 #define ECAT_EEPROM_CONTROL_STATUS_BF0_MASK      (0x1U)
31667 #define ECAT_EEPROM_CONTROL_STATUS_BF0_SHIFT     (0U)
31668 /*! BF0 - ECAT write enable2
31669  *  0b0..Write requests are disabled
31670  *  0b1..Write requests are enabled
31671  */
31672 #define ECAT_EEPROM_CONTROL_STATUS_BF0(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF0_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF0_MASK)
31673 
31674 #define ECAT_EEPROM_CONTROL_STATUS_BF1_MASK      (0x1EU)
31675 #define ECAT_EEPROM_CONTROL_STATUS_BF1_SHIFT     (1U)
31676 /*! BF1 - Reserved, write 0 */
31677 #define ECAT_EEPROM_CONTROL_STATUS_BF1(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF1_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF1_MASK)
31678 
31679 #define ECAT_EEPROM_CONTROL_STATUS_BF5_MASK      (0x20U)
31680 #define ECAT_EEPROM_CONTROL_STATUS_BF5_SHIFT     (5U)
31681 /*! BF5 - EEPROM emulation:
31682  *  0b0..Normal operation (I2C interface used)
31683  *  0b1..PDI emulates EEPROM (I2C not used)
31684  */
31685 #define ECAT_EEPROM_CONTROL_STATUS_BF5(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF5_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF5_MASK)
31686 
31687 #define ECAT_EEPROM_CONTROL_STATUS_BF6_MASK      (0x40U)
31688 #define ECAT_EEPROM_CONTROL_STATUS_BF6_SHIFT     (6U)
31689 /*! BF6 - Supported number of EEPROM read bytes:
31690  *  0b0..4 Bytes
31691  *  0b1..8 Bytes
31692  */
31693 #define ECAT_EEPROM_CONTROL_STATUS_BF6(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF6_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF6_MASK)
31694 
31695 #define ECAT_EEPROM_CONTROL_STATUS_BF7_MASK      (0x80U)
31696 #define ECAT_EEPROM_CONTROL_STATUS_BF7_SHIFT     (7U)
31697 /*! BF7 - Selected EEPROM Algorithm:
31698  *  0b0..1 address byte (1Kbit to 16Kbit EEPROMs)
31699  *  0b1..2 address bytes (32Kbit to 4 Mbit EEPROMs)
31700  */
31701 #define ECAT_EEPROM_CONTROL_STATUS_BF7(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF7_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF7_MASK)
31702 
31703 #define ECAT_EEPROM_CONTROL_STATUS_BF8_MASK      (0x700U)
31704 #define ECAT_EEPROM_CONTROL_STATUS_BF8_SHIFT     (8U)
31705 /*! BF8 - Command register
31706  *  0b000..No command/EEPROM idle (clear error bits)
31707  *  0b001..Read
31708  *  0b010..Write
31709  *  0b100..Reload
31710  */
31711 #define ECAT_EEPROM_CONTROL_STATUS_BF8(x)        (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF8_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF8_MASK)
31712 
31713 #define ECAT_EEPROM_CONTROL_STATUS_BF11_MASK     (0x800U)
31714 #define ECAT_EEPROM_CONTROL_STATUS_BF11_SHIFT    (11U)
31715 /*! BF11 - Checksum Error in ESC Configuration Area:
31716  *  0b0..Checksum ok
31717  *  0b1..Checksum error
31718  */
31719 #define ECAT_EEPROM_CONTROL_STATUS_BF11(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF11_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF11_MASK)
31720 
31721 #define ECAT_EEPROM_CONTROL_STATUS_BF12_MASK     (0x1000U)
31722 #define ECAT_EEPROM_CONTROL_STATUS_BF12_SHIFT    (12U)
31723 /*! BF12 - EEPROM loading status:
31724  *  0b0..EEPROM loaded, device information ok
31725  *  0b1..EEPROM not loaded, device information not available (EEPROM loading in progress or finished with a failure)
31726  */
31727 #define ECAT_EEPROM_CONTROL_STATUS_BF12(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF12_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF12_MASK)
31728 
31729 #define ECAT_EEPROM_CONTROL_STATUS_BF13_MASK     (0x2000U)
31730 #define ECAT_EEPROM_CONTROL_STATUS_BF13_SHIFT    (13U)
31731 /*! BF13 - Error Acknowledge/Command3:
31732  *  0b0..No error
31733  *  0b1..Missing EEPROM acknowledge or invalid command
31734  */
31735 #define ECAT_EEPROM_CONTROL_STATUS_BF13(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF13_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF13_MASK)
31736 
31737 #define ECAT_EEPROM_CONTROL_STATUS_BF14_MASK     (0x4000U)
31738 #define ECAT_EEPROM_CONTROL_STATUS_BF14_SHIFT    (14U)
31739 /*! BF14 - Error Write Enable3:
31740  *  0b0..No error
31741  *  0b1..Write Command without Write enable
31742  */
31743 #define ECAT_EEPROM_CONTROL_STATUS_BF14(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF14_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF14_MASK)
31744 
31745 #define ECAT_EEPROM_CONTROL_STATUS_BF15_MASK     (0x8000U)
31746 #define ECAT_EEPROM_CONTROL_STATUS_BF15_SHIFT    (15U)
31747 /*! BF15 - Busy:
31748  *  0b0..EEPROM Interface is idle
31749  *  0b1..EEPROM Interface is busy
31750  */
31751 #define ECAT_EEPROM_CONTROL_STATUS_BF15(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_BF15_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_BF15_MASK)
31752 /*! @} */
31753 
31754 /*! @name EEPROM_CONTROL_STATUS_PDI - Register EEPROM Control/Status */
31755 /*! @{ */
31756 
31757 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF0_MASK  (0x1U)
31758 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF0_SHIFT (0U)
31759 /*! BF0 - ECAT write enable2
31760  *  0b0..Write requests are disabled
31761  *  0b1..Write requests are enabled
31762  */
31763 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF0(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF0_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF0_MASK)
31764 
31765 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF1_MASK  (0x1EU)
31766 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF1_SHIFT (1U)
31767 /*! BF1 - Reserved, write 0 */
31768 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF1(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF1_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF1_MASK)
31769 
31770 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF5_MASK  (0x20U)
31771 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF5_SHIFT (5U)
31772 /*! BF5 - EEPROM emulation:
31773  *  0b0..Normal operation (I2C interface used)
31774  *  0b1..PDI emulates EEPROM (I2C not used)
31775  */
31776 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF5(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF5_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF5_MASK)
31777 
31778 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF6_MASK  (0x40U)
31779 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF6_SHIFT (6U)
31780 /*! BF6 - Supported number of EEPROM read bytes:
31781  *  0b0..4 Bytes
31782  *  0b1..8 Bytes
31783  */
31784 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF6(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF6_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF6_MASK)
31785 
31786 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF7_MASK  (0x80U)
31787 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF7_SHIFT (7U)
31788 /*! BF7 - Selected EEPROM Algorithm:
31789  *  0b0..1 address byte (1Kbit to 16Kbit EEPROMs)
31790  *  0b1..2 address bytes (32Kbit to 4 Mbit EEPROMs)
31791  */
31792 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF7(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF7_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF7_MASK)
31793 
31794 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF8_MASK  (0x700U)
31795 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF8_SHIFT (8U)
31796 /*! BF8 - Command register
31797  *  0b000..No command/EEPROM idle (clear error bits)
31798  *  0b001..Read
31799  *  0b010..Write
31800  *  0b100..Reload
31801  */
31802 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF8(x)    (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF8_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF8_MASK)
31803 
31804 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF11_MASK (0x800U)
31805 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF11_SHIFT (11U)
31806 /*! BF11 - Checksum Error in ESC Configuration Area:
31807  *  0b0..Checksum ok
31808  *  0b1..Checksum error
31809  */
31810 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF11(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF11_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF11_MASK)
31811 
31812 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF12_MASK (0x1000U)
31813 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF12_SHIFT (12U)
31814 /*! BF12 - EEPROM loading status:
31815  *  0b0..EEPROM loaded, device information ok
31816  *  0b1..EEPROM not loaded, device information not available (EEPROM loading in progress or finished with a failure)
31817  */
31818 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF12(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF12_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF12_MASK)
31819 
31820 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF13_MASK (0x2000U)
31821 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF13_SHIFT (13U)
31822 /*! BF13 - Error Acknowledge/Command3:
31823  *  0b0..No error
31824  *  0b1..Missing EEPROM acknowledge or invalid command
31825  */
31826 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF13(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF13_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF13_MASK)
31827 
31828 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF14_MASK (0x4000U)
31829 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF14_SHIFT (14U)
31830 /*! BF14 - Error Write Enable3:
31831  *  0b0..No error
31832  *  0b1..Write Command without Write enable
31833  */
31834 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF14(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF14_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF14_MASK)
31835 
31836 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF15_MASK (0x8000U)
31837 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF15_SHIFT (15U)
31838 /*! BF15 - Busy:
31839  *  0b0..EEPROM Interface is idle
31840  *  0b1..EEPROM Interface is busy
31841  */
31842 #define ECAT_EEPROM_CONTROL_STATUS_PDI_BF15(x)   (((uint16_t)(((uint16_t)(x)) << ECAT_EEPROM_CONTROL_STATUS_PDI_BF15_SHIFT)) & ECAT_EEPROM_CONTROL_STATUS_PDI_BF15_MASK)
31843 /*! @} */
31844 
31845 /*! @name EEPROM_ADDRESS - EEPROM Address */
31846 /*! @{ */
31847 
31848 #define ECAT_EEPROM_ADDRESS_BF0_MASK             (0xFFFFFFFFU)
31849 #define ECAT_EEPROM_ADDRESS_BF0_SHIFT            (0U)
31850 /*! BF0 - EEPROM Address */
31851 #define ECAT_EEPROM_ADDRESS_BF0(x)               (((uint32_t)(((uint32_t)(x)) << ECAT_EEPROM_ADDRESS_BF0_SHIFT)) & ECAT_EEPROM_ADDRESS_BF0_MASK)
31852 /*! @} */
31853 
31854 /*! @name EEPROM_DATA - EEPROM Data */
31855 /*! @{ */
31856 
31857 #define ECAT_EEPROM_DATA_BF0_MASK                (0xFFFFU)
31858 #define ECAT_EEPROM_DATA_BF0_SHIFT               (0U)
31859 /*! BF0 - EEPROM Write data (data to be written to EEPROM) or EEPROM Read data (data read from EEPROM,. lower bytes) */
31860 #define ECAT_EEPROM_DATA_BF0(x)                  (((uint64_t)(((uint64_t)(x)) << ECAT_EEPROM_DATA_BF0_SHIFT)) & ECAT_EEPROM_DATA_BF0_MASK)
31861 
31862 #define ECAT_EEPROM_DATA_BF16_MASK               (0xFFFFFFFFFFFF0000U)
31863 #define ECAT_EEPROM_DATA_BF16_SHIFT              (16U)
31864 /*! BF16 - EEPROM Read data (data read from EEPROM, higher bytes) */
31865 #define ECAT_EEPROM_DATA_BF16(x)                 (((uint64_t)(((uint64_t)(x)) << ECAT_EEPROM_DATA_BF16_SHIFT)) & ECAT_EEPROM_DATA_BF16_MASK)
31866 /*! @} */
31867 
31868 /*! @name MII_MANAGEMENT_CONTROL_OR_STATUS - MII Management Control/Status */
31869 /*! @{ */
31870 
31871 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF0_MASK (0x1U)
31872 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF0_SHIFT (0U)
31873 /*! BF0 - Write enable*:
31874  *  0b0..Write disabled
31875  *  0b1..Write enabled
31876  */
31877 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF0_MASK)
31878 
31879 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF1_MASK (0x2U)
31880 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF1_SHIFT (1U)
31881 /*! BF1 - Management Interface can be controlled by PDI (registers 0x0516-0x0517):
31882  *  0b0..Only ECAT control
31883  *  0b1..PDI control possible
31884  */
31885 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF1(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF1_MASK)
31886 
31887 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF2_MASK (0x4U)
31888 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF2_SHIFT (2U)
31889 /*! BF2 - MI link detection and configuration:
31890  *  0b0..Disabled for all ports
31891  *  0b1..Enabled for at least one MII port, refer to PHY Port Status (0x0518 ff.) for details
31892  */
31893 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF2(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF2_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF2_MASK)
31894 
31895 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF3_MASK (0xF8U)
31896 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF3_SHIFT (3U)
31897 /*! BF3 - PHY address of port 0 */
31898 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF3(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF3_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF3_MASK)
31899 
31900 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8_MASK (0x300U)
31901 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8_SHIFT (8U)
31902 /*! BF8 - Command register*:
31903  *  0b00..No command/MI idle (clear error bits)
31904  *  0b01..Read
31905  *  0b10..Write
31906  *  0b11..Reserved/invalid command (do not issue)
31907  */
31908 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF8_MASK)
31909 
31910 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF10_MASK (0x1C00U)
31911 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF10_SHIFT (10U)
31912 /*! BF10 - Reserved, write 0 */
31913 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF10(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF10_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF10_MASK)
31914 
31915 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_MASK (0x2000U)
31916 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_SHIFT (13U)
31917 /*! BF13 - Read error:
31918  *  0b0..No read error
31919  *  0b1..Read error occurred (PHY or register not available)
31920  */
31921 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF13_MASK)
31922 
31923 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_MASK (0x4000U)
31924 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_SHIFT (14U)
31925 /*! BF14 - Command error:
31926  *  0b0..Last Command was successful
31927  *  0b1..Invalid command or write command without Write Enable
31928  */
31929 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF14_MASK)
31930 
31931 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK (0x8000U)
31932 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_SHIFT (15U)
31933 /*! BF15 - Busy:
31934  *  0b0..MII Management Interface is idle
31935  *  0b1..MII Management Interface is busy
31936  */
31937 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_BF15_MASK)
31938 /*! @} */
31939 
31940 /*! @name MII_MANAGEMENT_CONTROL_OR_STATUS_PDI - MII Management Control/Status */
31941 /*! @{ */
31942 
31943 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF0_MASK (0x1U)
31944 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF0_SHIFT (0U)
31945 /*! BF0 - Write enable*:
31946  *  0b0..Write disabled
31947  *  0b1..Write enabled
31948  */
31949 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF0_MASK)
31950 
31951 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF1_MASK (0x2U)
31952 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF1_SHIFT (1U)
31953 /*! BF1 - Management Interface can be controlled by PDI (registers 0x0516-0x0517):
31954  *  0b0..Only ECAT control
31955  *  0b1..PDI control possible
31956  */
31957 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF1(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF1_MASK)
31958 
31959 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF2_MASK (0x4U)
31960 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF2_SHIFT (2U)
31961 /*! BF2 - MI link detection and configuration:
31962  *  0b0..Disabled for all ports
31963  *  0b1..Enabled for at least one MII port, refer to PHY Port Status (0x0518 ff.) for details
31964  */
31965 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF2(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF2_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF2_MASK)
31966 
31967 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF3_MASK (0xF8U)
31968 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF3_SHIFT (3U)
31969 /*! BF3 - PHY address of port 0 */
31970 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF3(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF3_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF3_MASK)
31971 
31972 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF8_MASK (0x300U)
31973 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF8_SHIFT (8U)
31974 /*! BF8 - Command register*:
31975  *  0b00..No command/MI idle (clear error bits)
31976  *  0b01..Read
31977  *  0b10..Write
31978  *  0b11..Reserved/invalid command (do not issue)
31979  */
31980 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF8(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF8_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF8_MASK)
31981 
31982 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF10_MASK (0x1C00U)
31983 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF10_SHIFT (10U)
31984 /*! BF10 - Reserved, write 0 */
31985 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF10(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF10_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF10_MASK)
31986 
31987 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF13_MASK (0x2000U)
31988 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF13_SHIFT (13U)
31989 /*! BF13 - Read error:
31990  *  0b0..No read error
31991  *  0b1..Read error occurred (PHY or register not available)
31992  */
31993 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF13(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF13_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF13_MASK)
31994 
31995 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF14_MASK (0x4000U)
31996 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF14_SHIFT (14U)
31997 /*! BF14 - Command error:
31998  *  0b0..Last Command was successful
31999  *  0b1..Invalid command or write command without Write Enable
32000  */
32001 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF14(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF14_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF14_MASK)
32002 
32003 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF15_MASK (0x8000U)
32004 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF15_SHIFT (15U)
32005 /*! BF15 - Busy:
32006  *  0b0..MII Management Interface is idle
32007  *  0b1..MII Management Interface is busy
32008  */
32009 #define ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF15(x) (((uint16_t)(((uint16_t)(x)) << ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF15_SHIFT)) & ECAT_MII_MANAGEMENT_CONTROL_OR_STATUS_PDI_BF15_MASK)
32010 /*! @} */
32011 
32012 /*! @name PHY_ADDRESS - PHY Address */
32013 /*! @{ */
32014 
32015 #define ECAT_PHY_ADDRESS_BF0_MASK                (0x1FU)
32016 #define ECAT_PHY_ADDRESS_BF0_SHIFT               (0U)
32017 /*! BF0 - PHY Address */
32018 #define ECAT_PHY_ADDRESS_BF0(x)                  (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_ADDRESS_BF0_SHIFT)) & ECAT_PHY_ADDRESS_BF0_MASK)
32019 
32020 #define ECAT_PHY_ADDRESS_BF5_MASK                (0x60U)
32021 #define ECAT_PHY_ADDRESS_BF5_SHIFT               (5U)
32022 /*! BF5 - Reserved, write 0 */
32023 #define ECAT_PHY_ADDRESS_BF5(x)                  (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_ADDRESS_BF5_SHIFT)) & ECAT_PHY_ADDRESS_BF5_MASK)
32024 
32025 #define ECAT_PHY_ADDRESS_BF7_MASK                (0x80U)
32026 #define ECAT_PHY_ADDRESS_BF7_SHIFT               (7U)
32027 /*! BF7 - Show configured PHY address of port 0-3 in register 0x0510[7:3]. This is used if the PHY addresses are not consecutive.
32028  *  0b0..Register 0x0510[7:3] shows PHY address of port 0 (this is also the PHY address offset, if the PHY addresses are consecutive)
32029  *  0b1..Register 0x0510[7:3] shows PHY address of port 0x0512[4:0] (valid values 0-3)
32030  */
32031 #define ECAT_PHY_ADDRESS_BF7(x)                  (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_ADDRESS_BF7_SHIFT)) & ECAT_PHY_ADDRESS_BF7_MASK)
32032 /*! @} */
32033 
32034 /*! @name PHY_REGISTER_ADDRESS - PHY Register Address */
32035 /*! @{ */
32036 
32037 #define ECAT_PHY_REGISTER_ADDRESS_BF0_MASK       (0x1FU)
32038 #define ECAT_PHY_REGISTER_ADDRESS_BF0_SHIFT      (0U)
32039 /*! BF0 - Address of PHY Register that shall be read/written */
32040 #define ECAT_PHY_REGISTER_ADDRESS_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_REGISTER_ADDRESS_BF0_SHIFT)) & ECAT_PHY_REGISTER_ADDRESS_BF0_MASK)
32041 
32042 #define ECAT_PHY_REGISTER_ADDRESS_BF5_MASK       (0xE0U)
32043 #define ECAT_PHY_REGISTER_ADDRESS_BF5_SHIFT      (5U)
32044 /*! BF5 - Reserved, write 0 */
32045 #define ECAT_PHY_REGISTER_ADDRESS_BF5(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_REGISTER_ADDRESS_BF5_SHIFT)) & ECAT_PHY_REGISTER_ADDRESS_BF5_MASK)
32046 /*! @} */
32047 
32048 /*! @name PHY_DATA - PHY Data */
32049 /*! @{ */
32050 
32051 #define ECAT_PHY_DATA_BF0_MASK                   (0xFFFFU)
32052 #define ECAT_PHY_DATA_BF0_SHIFT                  (0U)
32053 /*! BF0 - PHY Read/Write Data */
32054 #define ECAT_PHY_DATA_BF0(x)                     (((uint16_t)(((uint16_t)(x)) << ECAT_PHY_DATA_BF0_SHIFT)) & ECAT_PHY_DATA_BF0_MASK)
32055 /*! @} */
32056 
32057 /*! @name MII_MANAGEMENT_ECAT_ACCESS_STATE - MII Management ECAT Access State */
32058 /*! @{ */
32059 
32060 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF0_MASK (0x1U)
32061 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF0_SHIFT (0U)
32062 /*! BF0 - Access to MII management:
32063  *  0b0..ECAT enables PDI takeover of MII management interface
32064  *  0b1..ECAT claims exclusive access to MII management interface
32065  */
32066 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF0_MASK)
32067 
32068 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF1_MASK (0xFEU)
32069 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF1_SHIFT (1U)
32070 /*! BF1 - Reserved, write 0 */
32071 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_BF1_MASK)
32072 /*! @} */
32073 
32074 /*! @name MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI - MII Management ECAT Access State */
32075 /*! @{ */
32076 
32077 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF0_MASK (0x1U)
32078 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF0_SHIFT (0U)
32079 /*! BF0 - Access to MII management:
32080  *  0b0..ECAT enables PDI takeover of MII management interface
32081  *  0b1..ECAT claims exclusive access to MII management interface
32082  */
32083 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF0_MASK)
32084 
32085 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF1_MASK (0xFEU)
32086 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF1_SHIFT (1U)
32087 /*! BF1 - Reserved, write 0 */
32088 #define ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_ECAT_ACCESS_STATE_PDI_BF1_MASK)
32089 /*! @} */
32090 
32091 /*! @name MII_MANAGEMENT_PDI_ACCESS_STATE - MII Management PDI Access State */
32092 /*! @{ */
32093 
32094 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_MASK (0x1U)
32095 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_SHIFT (0U)
32096 /*! BF0 - Access to MII management:
32097  *  0b0..ECAT has access to MII management
32098  *  0b1..PDI has access to MII management
32099  */
32100 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF0_MASK)
32101 
32102 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF1_MASK (0x2U)
32103 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF1_SHIFT (1U)
32104 /*! BF1 - Force PDI Access State:
32105  *  0b0..Do not change Bit 0x0517[0]
32106  *  0b1..Reset Bit 0x0517[0] to 0
32107  */
32108 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF1_MASK)
32109 
32110 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF2_MASK (0xFCU)
32111 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF2_SHIFT (2U)
32112 /*! BF2 - Reserved, write 0 */
32113 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF2_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_BF2_MASK)
32114 /*! @} */
32115 
32116 /*! @name MII_MANAGEMENT_PDI_ACCESS_STATE_PDI - MII Management PDI Access State */
32117 /*! @{ */
32118 
32119 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF0_MASK (0x1U)
32120 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF0_SHIFT (0U)
32121 /*! BF0 - Access to MII management:
32122  *  0b0..ECAT has access to MII management
32123  *  0b1..PDI has access to MII management
32124  */
32125 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF0_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF0_MASK)
32126 
32127 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF1_MASK (0x2U)
32128 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF1_SHIFT (1U)
32129 /*! BF1 - Force PDI Access State:
32130  *  0b0..Do not change Bit 0x0517[0]
32131  *  0b1..Reset Bit 0x0517[0] to 0
32132  */
32133 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF1(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF1_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF1_MASK)
32134 
32135 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF2_MASK (0xFCU)
32136 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF2_SHIFT (2U)
32137 /*! BF2 - Reserved, write 0 */
32138 #define ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF2_SHIFT)) & ECAT_MII_MANAGEMENT_PDI_ACCESS_STATE_PDI_BF2_MASK)
32139 /*! @} */
32140 
32141 /*! @name PHY_PORT_STATUS - PHY Port */
32142 /*! @{ */
32143 
32144 #define ECAT_PHY_PORT_STATUS_BF0_MASK            (0x1U)
32145 #define ECAT_PHY_PORT_STATUS_BF0_SHIFT           (0U)
32146 /*! BF0 - Physical link status (PHY status register 1.2):
32147  *  0b0..No physical link
32148  *  0b1..Physical link detected
32149  */
32150 #define ECAT_PHY_PORT_STATUS_BF0(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF0_SHIFT)) & ECAT_PHY_PORT_STATUS_BF0_MASK)
32151 
32152 #define ECAT_PHY_PORT_STATUS_BF1_MASK            (0x2U)
32153 #define ECAT_PHY_PORT_STATUS_BF1_SHIFT           (1U)
32154 /*! BF1 - Link status (100 Mbit/s, Full Duplex, Auto negotiation):
32155  *  0b0..No link
32156  *  0b1..Link detected
32157  */
32158 #define ECAT_PHY_PORT_STATUS_BF1(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF1_SHIFT)) & ECAT_PHY_PORT_STATUS_BF1_MASK)
32159 
32160 #define ECAT_PHY_PORT_STATUS_BF2_MASK            (0x4U)
32161 #define ECAT_PHY_PORT_STATUS_BF2_SHIFT           (2U)
32162 /*! BF2 - Link status error:
32163  *  0b0..No error
32164  *  0b1..Link error, link inhibited
32165  */
32166 #define ECAT_PHY_PORT_STATUS_BF2(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF2_SHIFT)) & ECAT_PHY_PORT_STATUS_BF2_MASK)
32167 
32168 #define ECAT_PHY_PORT_STATUS_BF3_MASK            (0x8U)
32169 #define ECAT_PHY_PORT_STATUS_BF3_SHIFT           (3U)
32170 /*! BF3 - Read error:
32171  *  0b0..No read error occurred
32172  *  0b1..A read error has occurred
32173  */
32174 #define ECAT_PHY_PORT_STATUS_BF3(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF3_SHIFT)) & ECAT_PHY_PORT_STATUS_BF3_MASK)
32175 
32176 #define ECAT_PHY_PORT_STATUS_BF4_MASK            (0x10U)
32177 #define ECAT_PHY_PORT_STATUS_BF4_SHIFT           (4U)
32178 /*! BF4 - Link partner error:
32179  *  0b0..No error detected
32180  *  0b1..Link partner error
32181  */
32182 #define ECAT_PHY_PORT_STATUS_BF4(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF4_SHIFT)) & ECAT_PHY_PORT_STATUS_BF4_MASK)
32183 
32184 #define ECAT_PHY_PORT_STATUS_BF5_MASK            (0x20U)
32185 #define ECAT_PHY_PORT_STATUS_BF5_SHIFT           (5U)
32186 /*! BF5 - PHY configuration updated
32187  *  0b0..No update
32188  *  0b1..PHY configuration was updated
32189  */
32190 #define ECAT_PHY_PORT_STATUS_BF5(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF5_SHIFT)) & ECAT_PHY_PORT_STATUS_BF5_MASK)
32191 
32192 #define ECAT_PHY_PORT_STATUS_BF6_MASK            (0xC0U)
32193 #define ECAT_PHY_PORT_STATUS_BF6_SHIFT           (6U)
32194 /*! BF6 - Reserved */
32195 #define ECAT_PHY_PORT_STATUS_BF6(x)              (((uint8_t)(((uint8_t)(x)) << ECAT_PHY_PORT_STATUS_BF6_SHIFT)) & ECAT_PHY_PORT_STATUS_BF6_MASK)
32196 /*! @} */
32197 
32198 /* The count of ECAT_PHY_PORT_STATUS */
32199 #define ECAT_PHY_PORT_STATUS_COUNT               (2U)
32200 
32201 /*! @name FMMU_LOGICAL_START_ADDRESS - Register Logical Start address FMMU */
32202 /*! @{ */
32203 
32204 #define ECAT_FMMU_LOGICAL_START_ADDRESS_BF0_MASK (0xFFFFFFFFU)
32205 #define ECAT_FMMU_LOGICAL_START_ADDRESS_BF0_SHIFT (0U)
32206 /*! BF0 - Logical start address within the EtherCAT Address Space. */
32207 #define ECAT_FMMU_LOGICAL_START_ADDRESS_BF0(x)   (((uint32_t)(((uint32_t)(x)) << ECAT_FMMU_LOGICAL_START_ADDRESS_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_START_ADDRESS_BF0_MASK)
32208 /*! @} */
32209 
32210 /* The count of ECAT_FMMU_LOGICAL_START_ADDRESS */
32211 #define ECAT_FMMU_LOGICAL_START_ADDRESS_COUNT    (8U)
32212 
32213 /*! @name FMMU_LOGICAL_START_ADDRESS_PDI - Register Logical Start address FMMU */
32214 /*! @{ */
32215 
32216 #define ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_BF0_MASK (0xFFFFFFFFU)
32217 #define ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_BF0_SHIFT (0U)
32218 /*! BF0 - Logical start address within the EtherCAT Address Space. */
32219 #define ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_BF0(x) (((uint32_t)(((uint32_t)(x)) << ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_BF0_MASK)
32220 /*! @} */
32221 
32222 /* The count of ECAT_FMMU_LOGICAL_START_ADDRESS_PDI */
32223 #define ECAT_FMMU_LOGICAL_START_ADDRESS_PDI_COUNT (8U)
32224 
32225 /*! @name FMMU_LENGTH - Register Length FMMU */
32226 /*! @{ */
32227 
32228 #define ECAT_FMMU_LENGTH_BF0_MASK                (0xFFFFU)
32229 #define ECAT_FMMU_LENGTH_BF0_SHIFT               (0U)
32230 /*! BF0 - Offset from the first logical FMMU byte to the last FMMU byte + 1 */
32231 #define ECAT_FMMU_LENGTH_BF0(x)                  (((uint16_t)(((uint16_t)(x)) << ECAT_FMMU_LENGTH_BF0_SHIFT)) & ECAT_FMMU_LENGTH_BF0_MASK)
32232 /*! @} */
32233 
32234 /* The count of ECAT_FMMU_LENGTH */
32235 #define ECAT_FMMU_LENGTH_COUNT                   (8U)
32236 
32237 /*! @name FMMU_LENGTH_PDI - Register Length FMMU */
32238 /*! @{ */
32239 
32240 #define ECAT_FMMU_LENGTH_PDI_BF0_MASK            (0xFFFFU)
32241 #define ECAT_FMMU_LENGTH_PDI_BF0_SHIFT           (0U)
32242 /*! BF0 - Offset from the first logical FMMU byte to the last FMMU byte + 1 */
32243 #define ECAT_FMMU_LENGTH_PDI_BF0(x)              (((uint16_t)(((uint16_t)(x)) << ECAT_FMMU_LENGTH_PDI_BF0_SHIFT)) & ECAT_FMMU_LENGTH_PDI_BF0_MASK)
32244 /*! @} */
32245 
32246 /* The count of ECAT_FMMU_LENGTH_PDI */
32247 #define ECAT_FMMU_LENGTH_PDI_COUNT               (8U)
32248 
32249 /*! @name FMMU_LOGICAL_START_BIT - Register Start bit FMMU y in logical address space */
32250 /*! @{ */
32251 
32252 #define ECAT_FMMU_LOGICAL_START_BIT_BF0_MASK     (0x7U)
32253 #define ECAT_FMMU_LOGICAL_START_BIT_BF0_SHIFT    (0U)
32254 /*! BF0 - Logical starting bit that shall be mapped (bits are counted from least significant bit 0 to most significant bit 7) */
32255 #define ECAT_FMMU_LOGICAL_START_BIT_BF0(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_START_BIT_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_START_BIT_BF0_MASK)
32256 
32257 #define ECAT_FMMU_LOGICAL_START_BIT_BF3_MASK     (0xF8U)
32258 #define ECAT_FMMU_LOGICAL_START_BIT_BF3_SHIFT    (3U)
32259 /*! BF3 - Reserved, write 0 */
32260 #define ECAT_FMMU_LOGICAL_START_BIT_BF3(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_START_BIT_BF3_SHIFT)) & ECAT_FMMU_LOGICAL_START_BIT_BF3_MASK)
32261 /*! @} */
32262 
32263 /* The count of ECAT_FMMU_LOGICAL_START_BIT */
32264 #define ECAT_FMMU_LOGICAL_START_BIT_COUNT        (8U)
32265 
32266 /*! @name FMMU_LOGICAL_START_BIT_PDI - Register Start bit FMMU y in logical address space */
32267 /*! @{ */
32268 
32269 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF0_MASK (0x7U)
32270 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF0_SHIFT (0U)
32271 /*! BF0 - Logical starting bit that shall be mapped (bits are counted from least significant bit 0 to most significant bit 7) */
32272 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF0(x)   (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_START_BIT_PDI_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_START_BIT_PDI_BF0_MASK)
32273 
32274 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF3_MASK (0xF8U)
32275 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF3_SHIFT (3U)
32276 /*! BF3 - Reserved, write 0 */
32277 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_BF3(x)   (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_START_BIT_PDI_BF3_SHIFT)) & ECAT_FMMU_LOGICAL_START_BIT_PDI_BF3_MASK)
32278 /*! @} */
32279 
32280 /* The count of ECAT_FMMU_LOGICAL_START_BIT_PDI */
32281 #define ECAT_FMMU_LOGICAL_START_BIT_PDI_COUNT    (8U)
32282 
32283 /*! @name FMMU_LOGICAL_STOP_BIT - Register Stop bit FMMU y in logical address space */
32284 /*! @{ */
32285 
32286 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF0_MASK      (0x7U)
32287 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF0_SHIFT     (0U)
32288 /*! BF0 - Last logical bit that shall be mapped (bits are counted from least significant bit 0 to most significant bit 7) */
32289 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF0(x)        (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_STOP_BIT_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_STOP_BIT_BF0_MASK)
32290 
32291 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF3_MASK      (0xF8U)
32292 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF3_SHIFT     (3U)
32293 /*! BF3 - Reserved, write 0 */
32294 #define ECAT_FMMU_LOGICAL_STOP_BIT_BF3(x)        (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_STOP_BIT_BF3_SHIFT)) & ECAT_FMMU_LOGICAL_STOP_BIT_BF3_MASK)
32295 /*! @} */
32296 
32297 /* The count of ECAT_FMMU_LOGICAL_STOP_BIT */
32298 #define ECAT_FMMU_LOGICAL_STOP_BIT_COUNT         (8U)
32299 
32300 /*! @name FMMU_LOGICAL_STOP_BIT_PDI - Register Stop bit FMMU y in logical address space */
32301 /*! @{ */
32302 
32303 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF0_MASK  (0x7U)
32304 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF0_SHIFT (0U)
32305 /*! BF0 - Last logical bit that shall be mapped (bits are counted from least significant bit 0 to most significant bit 7) */
32306 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF0(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF0_SHIFT)) & ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF0_MASK)
32307 
32308 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF3_MASK  (0xF8U)
32309 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF3_SHIFT (3U)
32310 /*! BF3 - Reserved, write 0 */
32311 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF3(x)    (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF3_SHIFT)) & ECAT_FMMU_LOGICAL_STOP_BIT_PDI_BF3_MASK)
32312 /*! @} */
32313 
32314 /* The count of ECAT_FMMU_LOGICAL_STOP_BIT_PDI */
32315 #define ECAT_FMMU_LOGICAL_STOP_BIT_PDI_COUNT     (8U)
32316 
32317 /*! @name FMMU_PHYSICAL_START_ADDRESS - Register Physical Start address FMMU */
32318 /*! @{ */
32319 
32320 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_BF0_MASK (0xFFFFU)
32321 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_BF0_SHIFT (0U)
32322 /*! BF0 - Physical Start Address (mapped to logical Start address) */
32323 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_BF0(x)  (((uint16_t)(((uint16_t)(x)) << ECAT_FMMU_PHYSICAL_START_ADDRESS_BF0_SHIFT)) & ECAT_FMMU_PHYSICAL_START_ADDRESS_BF0_MASK)
32324 /*! @} */
32325 
32326 /* The count of ECAT_FMMU_PHYSICAL_START_ADDRESS */
32327 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_COUNT   (8U)
32328 
32329 /*! @name FMMU_PHYSICAL_START_ADDRESS_PDI - Register Physical Start address FMMU */
32330 /*! @{ */
32331 
32332 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_BF0_MASK (0xFFFFU)
32333 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_BF0_SHIFT (0U)
32334 /*! BF0 - Physical Start Address (mapped to logical Start address) */
32335 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_BF0_SHIFT)) & ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_BF0_MASK)
32336 /*! @} */
32337 
32338 /* The count of ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI */
32339 #define ECAT_FMMU_PHYSICAL_START_ADDRESS_PDI_COUNT (8U)
32340 
32341 /*! @name FMMU_PHYSICAL_START_BIT - Register Physical Start bit FMMU */
32342 /*! @{ */
32343 
32344 #define ECAT_FMMU_PHYSICAL_START_BIT_BF0_MASK    (0x7U)
32345 #define ECAT_FMMU_PHYSICAL_START_BIT_BF0_SHIFT   (0U)
32346 /*! BF0 - Physical starting bit as target of logical start bit mapping (bits are counted from least
32347  *    significant bit 0 to most significant bit 7)
32348  */
32349 #define ECAT_FMMU_PHYSICAL_START_BIT_BF0(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_PHYSICAL_START_BIT_BF0_SHIFT)) & ECAT_FMMU_PHYSICAL_START_BIT_BF0_MASK)
32350 
32351 #define ECAT_FMMU_PHYSICAL_START_BIT_BF3_MASK    (0xF8U)
32352 #define ECAT_FMMU_PHYSICAL_START_BIT_BF3_SHIFT   (3U)
32353 /*! BF3 - Reserved, write 0 */
32354 #define ECAT_FMMU_PHYSICAL_START_BIT_BF3(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_PHYSICAL_START_BIT_BF3_SHIFT)) & ECAT_FMMU_PHYSICAL_START_BIT_BF3_MASK)
32355 /*! @} */
32356 
32357 /* The count of ECAT_FMMU_PHYSICAL_START_BIT */
32358 #define ECAT_FMMU_PHYSICAL_START_BIT_COUNT       (8U)
32359 
32360 /*! @name FMMU_PHYSICAL_START_BIT_PDI - Register Physical Start bit FMMU */
32361 /*! @{ */
32362 
32363 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF0_MASK (0x7U)
32364 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF0_SHIFT (0U)
32365 /*! BF0 - Physical starting bit as target of logical start bit mapping (bits are counted from least
32366  *    significant bit 0 to most significant bit 7)
32367  */
32368 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF0(x)  (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF0_SHIFT)) & ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF0_MASK)
32369 
32370 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF3_MASK (0xF8U)
32371 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF3_SHIFT (3U)
32372 /*! BF3 - Reserved, write 0 */
32373 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF3(x)  (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF3_SHIFT)) & ECAT_FMMU_PHYSICAL_START_BIT_PDI_BF3_MASK)
32374 /*! @} */
32375 
32376 /* The count of ECAT_FMMU_PHYSICAL_START_BIT_PDI */
32377 #define ECAT_FMMU_PHYSICAL_START_BIT_PDI_COUNT   (8U)
32378 
32379 /*! @name FMMU_TYPE - Register Type FMMU y */
32380 /*! @{ */
32381 
32382 #define ECAT_FMMU_TYPE_BF0_MASK                  (0x1U)
32383 #define ECAT_FMMU_TYPE_BF0_SHIFT                 (0U)
32384 /*! BF0 - Bit field access for ECAT: r/w
32385  *  0b0..Ignore mapping for read accesses
32386  *  0b1..Use mapping for read accesses
32387  */
32388 #define ECAT_FMMU_TYPE_BF0(x)                    (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_BF0_SHIFT)) & ECAT_FMMU_TYPE_BF0_MASK)
32389 
32390 #define ECAT_FMMU_TYPE_BF1_MASK                  (0x2U)
32391 #define ECAT_FMMU_TYPE_BF1_SHIFT                 (1U)
32392 /*! BF1 - Bit field access for ECAT: r/w
32393  *  0b0..Ignore mapping for write accesses
32394  *  0b1..Use mapping for write accesses
32395  */
32396 #define ECAT_FMMU_TYPE_BF1(x)                    (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_BF1_SHIFT)) & ECAT_FMMU_TYPE_BF1_MASK)
32397 
32398 #define ECAT_FMMU_TYPE_BF2_MASK                  (0xFCU)
32399 #define ECAT_FMMU_TYPE_BF2_SHIFT                 (2U)
32400 /*! BF2 - Reserved, write 0 */
32401 #define ECAT_FMMU_TYPE_BF2(x)                    (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_BF2_SHIFT)) & ECAT_FMMU_TYPE_BF2_MASK)
32402 /*! @} */
32403 
32404 /* The count of ECAT_FMMU_TYPE */
32405 #define ECAT_FMMU_TYPE_COUNT                     (8U)
32406 
32407 /*! @name FMMU_TYPE_PDI - Register Type FMMU y */
32408 /*! @{ */
32409 
32410 #define ECAT_FMMU_TYPE_PDI_BF0_MASK              (0x1U)
32411 #define ECAT_FMMU_TYPE_PDI_BF0_SHIFT             (0U)
32412 /*! BF0
32413  *  0b0..Ignore mapping for read accesses
32414  *  0b1..Use mapping for read accesses
32415  */
32416 #define ECAT_FMMU_TYPE_PDI_BF0(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_PDI_BF0_SHIFT)) & ECAT_FMMU_TYPE_PDI_BF0_MASK)
32417 
32418 #define ECAT_FMMU_TYPE_PDI_BF1_MASK              (0x2U)
32419 #define ECAT_FMMU_TYPE_PDI_BF1_SHIFT             (1U)
32420 /*! BF1
32421  *  0b0..Ignore mapping for write accesses
32422  *  0b1..Use mapping for write accesses
32423  */
32424 #define ECAT_FMMU_TYPE_PDI_BF1(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_PDI_BF1_SHIFT)) & ECAT_FMMU_TYPE_PDI_BF1_MASK)
32425 
32426 #define ECAT_FMMU_TYPE_PDI_BF2_MASK              (0xFCU)
32427 #define ECAT_FMMU_TYPE_PDI_BF2_SHIFT             (2U)
32428 /*! BF2 - Reserved, write 0 */
32429 #define ECAT_FMMU_TYPE_PDI_BF2(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_TYPE_PDI_BF2_SHIFT)) & ECAT_FMMU_TYPE_PDI_BF2_MASK)
32430 /*! @} */
32431 
32432 /* The count of ECAT_FMMU_TYPE_PDI */
32433 #define ECAT_FMMU_TYPE_PDI_COUNT                 (8U)
32434 
32435 /*! @name FMMU_ACTIVATE - Register Activate FMMU */
32436 /*! @{ */
32437 
32438 #define ECAT_FMMU_ACTIVATE_BF0_MASK              (0x1U)
32439 #define ECAT_FMMU_ACTIVATE_BF0_SHIFT             (0U)
32440 /*! BF0 - Bit field access for ECAT: r/w
32441  *  0b0..FMMU deactivated
32442  *  0b1..FMMU activated. FMMU checks logically addressed blocks to be mapped according to configured mapping
32443  */
32444 #define ECAT_FMMU_ACTIVATE_BF0(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_ACTIVATE_BF0_SHIFT)) & ECAT_FMMU_ACTIVATE_BF0_MASK)
32445 
32446 #define ECAT_FMMU_ACTIVATE_BF1_MASK              (0xFEU)
32447 #define ECAT_FMMU_ACTIVATE_BF1_SHIFT             (1U)
32448 /*! BF1 - Reserved, write 0 */
32449 #define ECAT_FMMU_ACTIVATE_BF1(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_ACTIVATE_BF1_SHIFT)) & ECAT_FMMU_ACTIVATE_BF1_MASK)
32450 /*! @} */
32451 
32452 /* The count of ECAT_FMMU_ACTIVATE */
32453 #define ECAT_FMMU_ACTIVATE_COUNT                 (8U)
32454 
32455 /*! @name FMMU_ACTIVATE_PDI - Register Activate FMMU */
32456 /*! @{ */
32457 
32458 #define ECAT_FMMU_ACTIVATE_PDI_BF0_MASK          (0x1U)
32459 #define ECAT_FMMU_ACTIVATE_PDI_BF0_SHIFT         (0U)
32460 /*! BF0
32461  *  0b0..FMMU deactivated
32462  *  0b1..FMMU activated. FMMU checks logically addressed blocks to be mapped according to configured mapping
32463  */
32464 #define ECAT_FMMU_ACTIVATE_PDI_BF0(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_ACTIVATE_PDI_BF0_SHIFT)) & ECAT_FMMU_ACTIVATE_PDI_BF0_MASK)
32465 
32466 #define ECAT_FMMU_ACTIVATE_PDI_BF1_MASK          (0xFEU)
32467 #define ECAT_FMMU_ACTIVATE_PDI_BF1_SHIFT         (1U)
32468 /*! BF1 - Reserved, write 0 */
32469 #define ECAT_FMMU_ACTIVATE_PDI_BF1(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_FMMU_ACTIVATE_PDI_BF1_SHIFT)) & ECAT_FMMU_ACTIVATE_PDI_BF1_MASK)
32470 /*! @} */
32471 
32472 /* The count of ECAT_FMMU_ACTIVATE_PDI */
32473 #define ECAT_FMMU_ACTIVATE_PDI_COUNT             (8U)
32474 
32475 /*! @name SYNCMANAGER_PHYSICAL_START_ADDRESS - Register physical Start Address SyncManager */
32476 /*! @{ */
32477 
32478 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_BF0_MASK (0xFFFFU)
32479 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_BF0_SHIFT (0U)
32480 /*! BF0 - First byte that will be handled by SyncManager */
32481 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_BF0_SHIFT)) & ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_BF0_MASK)
32482 /*! @} */
32483 
32484 /* The count of ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS */
32485 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_COUNT (16U)
32486 
32487 /*! @name SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI - Register physical Start Address SyncManager */
32488 /*! @{ */
32489 
32490 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_BF0_MASK (0xFFFFU)
32491 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_BF0_SHIFT (0U)
32492 /*! BF0 - First byte that will be handled by SyncManager */
32493 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_BF0_SHIFT)) & ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_BF0_MASK)
32494 /*! @} */
32495 
32496 /* The count of ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI */
32497 #define ECAT_SYNCMANAGER_PHYSICAL_START_ADDRESS_PDI_COUNT (16U)
32498 
32499 /*! @name SYNCMANAGER_LENGTH - Register Length SyncManager */
32500 /*! @{ */
32501 
32502 #define ECAT_SYNCMANAGER_LENGTH_BF0_MASK         (0xFFFFU)
32503 #define ECAT_SYNCMANAGER_LENGTH_BF0_SHIFT        (0U)
32504 /*! BF0 - Number of bytes assigned to SyncManager (shall be greater than 1 */
32505 #define ECAT_SYNCMANAGER_LENGTH_BF0(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_SYNCMANAGER_LENGTH_BF0_SHIFT)) & ECAT_SYNCMANAGER_LENGTH_BF0_MASK)
32506 /*! @} */
32507 
32508 /* The count of ECAT_SYNCMANAGER_LENGTH */
32509 #define ECAT_SYNCMANAGER_LENGTH_COUNT            (16U)
32510 
32511 /*! @name SYNCMANAGER_LENGTH_PDI - Register Length SyncManager */
32512 /*! @{ */
32513 
32514 #define ECAT_SYNCMANAGER_LENGTH_PDI_BF0_MASK     (0xFFFFU)
32515 #define ECAT_SYNCMANAGER_LENGTH_PDI_BF0_SHIFT    (0U)
32516 /*! BF0 - Number of bytes assigned to SyncManager (shall be greater than 1 */
32517 #define ECAT_SYNCMANAGER_LENGTH_PDI_BF0(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_SYNCMANAGER_LENGTH_PDI_BF0_SHIFT)) & ECAT_SYNCMANAGER_LENGTH_PDI_BF0_MASK)
32518 /*! @} */
32519 
32520 /* The count of ECAT_SYNCMANAGER_LENGTH_PDI */
32521 #define ECAT_SYNCMANAGER_LENGTH_PDI_COUNT        (16U)
32522 
32523 /*! @name SYNCMANAGER_CONTROL_REGISTER - Register Control Register SyncManager */
32524 /*! @{ */
32525 
32526 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF0_MASK (0x3U)
32527 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF0_SHIFT (0U)
32528 /*! BF0 - Operation Mode:
32529  *  0b00..Buffered (3 buffer mode)
32530  *  0b01..Reserved
32531  *  0b10..Mailbox (Single buffer mode)
32532  *  0b11..Reserved
32533  */
32534 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF0_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF0_MASK)
32535 
32536 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF2_MASK (0xCU)
32537 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF2_SHIFT (2U)
32538 /*! BF2 - Direction:
32539  *  0b00..Read: ECAT read access, PDI write access.
32540  *  0b01..Write: ECAT write access, PDI read access.
32541  *  0b10..Reserved
32542  *  0b11..Reserved
32543  */
32544 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF2_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF2_MASK)
32545 
32546 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF4_MASK (0x10U)
32547 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF4_SHIFT (4U)
32548 /*! BF4 - Interrupt in ECAT Event Request Register:
32549  *  0b0..Disabled
32550  *  0b1..Enabled
32551  */
32552 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF4(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF4_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF4_MASK)
32553 
32554 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF5_MASK (0x20U)
32555 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF5_SHIFT (5U)
32556 /*! BF5 - Interrupt in AL Event Request Register:
32557  *  0b0..Disabled
32558  *  0b1..Enabled
32559  */
32560 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF5(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF5_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF5_MASK)
32561 
32562 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF6_MASK (0x40U)
32563 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF6_SHIFT (6U)
32564 /*! BF6 - Watchdog Trigger Enable:
32565  *  0b0..Disabled
32566  *  0b1..Enabled
32567  */
32568 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF6(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF6_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF6_MASK)
32569 
32570 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF7_MASK (0x80U)
32571 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF7_SHIFT (7U)
32572 /*! BF7 - Reserved, write 0 */
32573 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_BF7(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_BF7_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_BF7_MASK)
32574 /*! @} */
32575 
32576 /* The count of ECAT_SYNCMANAGER_CONTROL_REGISTER */
32577 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_COUNT  (16U)
32578 
32579 /*! @name SYNCMANAGER_CONTROL_REGISTER_PDI - Register Control Register SyncManager */
32580 /*! @{ */
32581 
32582 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF0_MASK (0x3U)
32583 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF0_SHIFT (0U)
32584 /*! BF0 - Operation Mode:
32585  *  0b00..Buffered (3 buffer mode)
32586  *  0b01..Reserved
32587  *  0b10..Mailbox (Single buffer mode)
32588  *  0b11..Reserved
32589  */
32590 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF0_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF0_MASK)
32591 
32592 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF2_MASK (0xCU)
32593 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF2_SHIFT (2U)
32594 /*! BF2 - Direction:
32595  *  0b00..Read: ECAT read access, PDI write access.
32596  *  0b01..Write: ECAT write access, PDI read access.
32597  *  0b10..Reserved
32598  *  0b11..Reserved
32599  */
32600 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF2(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF2_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF2_MASK)
32601 
32602 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF4_MASK (0x10U)
32603 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF4_SHIFT (4U)
32604 /*! BF4 - Interrupt in ECAT Event Request Register:
32605  *  0b0..Disabled
32606  *  0b1..Enabled
32607  */
32608 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF4(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF4_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF4_MASK)
32609 
32610 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF5_MASK (0x20U)
32611 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF5_SHIFT (5U)
32612 /*! BF5 - Interrupt in AL Event Request Register:
32613  *  0b0..Disabled
32614  *  0b1..Enabled
32615  */
32616 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF5(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF5_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF5_MASK)
32617 
32618 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF6_MASK (0x40U)
32619 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF6_SHIFT (6U)
32620 /*! BF6 - Watchdog Trigger Enable:
32621  *  0b0..Disabled
32622  *  0b1..Enabled
32623  */
32624 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF6(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF6_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF6_MASK)
32625 
32626 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF7_MASK (0x80U)
32627 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF7_SHIFT (7U)
32628 /*! BF7 - Reserved, write 0 */
32629 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF7(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF7_SHIFT)) & ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_BF7_MASK)
32630 /*! @} */
32631 
32632 /* The count of ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI */
32633 #define ECAT_SYNCMANAGER_CONTROL_REGISTER_PDI_COUNT (16U)
32634 
32635 /*! @name SYNCMANAGER_STATUS - Register Status Register SyncManager */
32636 /*! @{ */
32637 
32638 #define ECAT_SYNCMANAGER_STATUS_BF0_MASK         (0x1U)
32639 #define ECAT_SYNCMANAGER_STATUS_BF0_SHIFT        (0U)
32640 /*! BF0 - Interrupt Write:
32641  *  0b1..Interrupt after buffer was completely and successfully written
32642  *  0b0..Interrupt cleared after first byte of buffer was read
32643  */
32644 #define ECAT_SYNCMANAGER_STATUS_BF0(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF0_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF0_MASK)
32645 
32646 #define ECAT_SYNCMANAGER_STATUS_BF1_MASK         (0x2U)
32647 #define ECAT_SYNCMANAGER_STATUS_BF1_SHIFT        (1U)
32648 /*! BF1 - Interrupt Read:
32649  *  0b1..Interrupt after buffer was completely and successfully read
32650  *  0b0..Interrupt cleared after first byte of buffer was written
32651  */
32652 #define ECAT_SYNCMANAGER_STATUS_BF1(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF1_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF1_MASK)
32653 
32654 #define ECAT_SYNCMANAGER_STATUS_BF2_MASK         (0x4U)
32655 #define ECAT_SYNCMANAGER_STATUS_BF2_SHIFT        (2U)
32656 /*! BF2 - Reserved */
32657 #define ECAT_SYNCMANAGER_STATUS_BF2(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF2_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF2_MASK)
32658 
32659 #define ECAT_SYNCMANAGER_STATUS_BF3_MASK         (0x8U)
32660 #define ECAT_SYNCMANAGER_STATUS_BF3_SHIFT        (3U)
32661 /*! BF3 - Mailbox mode: mailbox status:
32662  *  0b0..Mailbox empty
32663  *  0b1..Mailbox full
32664  */
32665 #define ECAT_SYNCMANAGER_STATUS_BF3(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF3_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF3_MASK)
32666 
32667 #define ECAT_SYNCMANAGER_STATUS_BF4_MASK         (0x30U)
32668 #define ECAT_SYNCMANAGER_STATUS_BF4_SHIFT        (4U)
32669 /*! BF4 - Buffered mode: buffer status (last written buffer):
32670  *  0b00..1st buffer
32671  *  0b01..2nd buffer
32672  *  0b10..3rd buffer
32673  *  0b11..(no buffer written)
32674  */
32675 #define ECAT_SYNCMANAGER_STATUS_BF4(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF4_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF4_MASK)
32676 
32677 #define ECAT_SYNCMANAGER_STATUS_BF6_MASK         (0x40U)
32678 #define ECAT_SYNCMANAGER_STATUS_BF6_SHIFT        (6U)
32679 /*! BF6 - Read buffer in use (opened) */
32680 #define ECAT_SYNCMANAGER_STATUS_BF6(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF6_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF6_MASK)
32681 
32682 #define ECAT_SYNCMANAGER_STATUS_BF7_MASK         (0x80U)
32683 #define ECAT_SYNCMANAGER_STATUS_BF7_SHIFT        (7U)
32684 /*! BF7 - Write buffer in use (opened) */
32685 #define ECAT_SYNCMANAGER_STATUS_BF7(x)           (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_STATUS_BF7_SHIFT)) & ECAT_SYNCMANAGER_STATUS_BF7_MASK)
32686 /*! @} */
32687 
32688 /* The count of ECAT_SYNCMANAGER_STATUS */
32689 #define ECAT_SYNCMANAGER_STATUS_COUNT            (16U)
32690 
32691 /*! @name SYNCMANAGER_ACTIVATE - Register Activate SyncManager */
32692 /*! @{ */
32693 
32694 #define ECAT_SYNCMANAGER_ACTIVATE_BF0_MASK       (0x1U)
32695 #define ECAT_SYNCMANAGER_ACTIVATE_BF0_SHIFT      (0U)
32696 /*! BF0 - SyncManager Enable/Disable:
32697  *  0b0..Disable: Access to Memory without SyncManager control
32698  *  0b1..Enable: SyncManager is active and controls Memory area set in configuration
32699  */
32700 #define ECAT_SYNCMANAGER_ACTIVATE_BF0(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_BF0_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_BF0_MASK)
32701 
32702 #define ECAT_SYNCMANAGER_ACTIVATE_BF1_MASK       (0x2U)
32703 #define ECAT_SYNCMANAGER_ACTIVATE_BF1_SHIFT      (1U)
32704 /*! BF1 - Repeat Request: */
32705 #define ECAT_SYNCMANAGER_ACTIVATE_BF1(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_BF1_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_BF1_MASK)
32706 
32707 #define ECAT_SYNCMANAGER_ACTIVATE_BF2_MASK       (0x3CU)
32708 #define ECAT_SYNCMANAGER_ACTIVATE_BF2_SHIFT      (2U)
32709 /*! BF2 - Reserved, write 0 */
32710 #define ECAT_SYNCMANAGER_ACTIVATE_BF2(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_BF2_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_BF2_MASK)
32711 
32712 #define ECAT_SYNCMANAGER_ACTIVATE_BF6_MASK       (0x40U)
32713 #define ECAT_SYNCMANAGER_ACTIVATE_BF6_SHIFT      (6U)
32714 /*! BF6 - Latch Event ECAT:
32715  *  0b0..No
32716  *  0b1..Generate Latch event when EtherCAT master issues a buffer exchange
32717  */
32718 #define ECAT_SYNCMANAGER_ACTIVATE_BF6(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_BF6_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_BF6_MASK)
32719 
32720 #define ECAT_SYNCMANAGER_ACTIVATE_BF7_MASK       (0x80U)
32721 #define ECAT_SYNCMANAGER_ACTIVATE_BF7_SHIFT      (7U)
32722 /*! BF7 - Latch Event PDI:
32723  *  0b0..No
32724  *  0b1..Generate Latch events when PDI issues a buffer exchange or when PDI accesses buffer start address
32725  */
32726 #define ECAT_SYNCMANAGER_ACTIVATE_BF7(x)         (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_BF7_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_BF7_MASK)
32727 /*! @} */
32728 
32729 /* The count of ECAT_SYNCMANAGER_ACTIVATE */
32730 #define ECAT_SYNCMANAGER_ACTIVATE_COUNT          (16U)
32731 
32732 /*! @name SYNCMANAGER_ACTIVATE_PDI - Register Activate SyncManager */
32733 /*! @{ */
32734 
32735 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF0_MASK   (0x1U)
32736 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF0_SHIFT  (0U)
32737 /*! BF0 - SyncManager Enable/Disable:
32738  *  0b0..Disable: Access to Memory without SyncManager control
32739  *  0b1..Enable: SyncManager is active and controls Memory area set in configuration
32740  */
32741 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_PDI_BF0_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_PDI_BF0_MASK)
32742 
32743 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF1_MASK   (0x2U)
32744 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF1_SHIFT  (1U)
32745 /*! BF1 - Repeat Request: */
32746 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF1(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_PDI_BF1_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_PDI_BF1_MASK)
32747 
32748 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF2_MASK   (0x3CU)
32749 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF2_SHIFT  (2U)
32750 /*! BF2 - Reserved, write 0 */
32751 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF2(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_PDI_BF2_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_PDI_BF2_MASK)
32752 
32753 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF6_MASK   (0x40U)
32754 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF6_SHIFT  (6U)
32755 /*! BF6 - Latch Event ECAT:
32756  *  0b0..No
32757  *  0b1..Generate Latch event when EtherCAT master issues a buffer exchange
32758  */
32759 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF6(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_PDI_BF6_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_PDI_BF6_MASK)
32760 
32761 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF7_MASK   (0x80U)
32762 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF7_SHIFT  (7U)
32763 /*! BF7 - Latch Event PDI:
32764  *  0b0..No
32765  *  0b1..Generate Latch events when PDI issues a buffer exchange or when PDI accesses buffer start address
32766  */
32767 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_BF7(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_ACTIVATE_PDI_BF7_SHIFT)) & ECAT_SYNCMANAGER_ACTIVATE_PDI_BF7_MASK)
32768 /*! @} */
32769 
32770 /* The count of ECAT_SYNCMANAGER_ACTIVATE_PDI */
32771 #define ECAT_SYNCMANAGER_ACTIVATE_PDI_COUNT      (16U)
32772 
32773 /*! @name SYNCMANAGER_PDI_CONTROL - Register PDI Control SyncManager */
32774 /*! @{ */
32775 
32776 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF0_MASK    (0x1U)
32777 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF0_SHIFT   (0U)
32778 /*! BF0 - Deactivate SyncManager: */
32779 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF0(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_BF0_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_BF0_MASK)
32780 
32781 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF1_MASK    (0x2U)
32782 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF1_SHIFT   (1U)
32783 /*! BF1 - Repeat Ack: */
32784 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF1(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_BF1_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_BF1_MASK)
32785 
32786 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF2_MASK    (0xFCU)
32787 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF2_SHIFT   (2U)
32788 /*! BF2 - Reserved, write 0 */
32789 #define ECAT_SYNCMANAGER_PDI_CONTROL_BF2(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_BF2_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_BF2_MASK)
32790 /*! @} */
32791 
32792 /* The count of ECAT_SYNCMANAGER_PDI_CONTROL */
32793 #define ECAT_SYNCMANAGER_PDI_CONTROL_COUNT       (16U)
32794 
32795 /*! @name SYNCMANAGER_PDI_CONTROL_PDI - Register PDI Control SyncManager */
32796 /*! @{ */
32797 
32798 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF0_MASK (0x1U)
32799 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF0_SHIFT (0U)
32800 /*! BF0 - Deactivate SyncManager: */
32801 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF0(x)  (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF0_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF0_MASK)
32802 
32803 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF1_MASK (0x2U)
32804 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF1_SHIFT (1U)
32805 /*! BF1 - Repeat Ack: */
32806 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF1(x)  (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF1_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF1_MASK)
32807 
32808 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF2_MASK (0xFCU)
32809 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF2_SHIFT (2U)
32810 /*! BF2 - Reserved, write 0 */
32811 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF2(x)  (((uint8_t)(((uint8_t)(x)) << ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF2_SHIFT)) & ECAT_SYNCMANAGER_PDI_CONTROL_PDI_BF2_MASK)
32812 /*! @} */
32813 
32814 /* The count of ECAT_SYNCMANAGER_PDI_CONTROL_PDI */
32815 #define ECAT_SYNCMANAGER_PDI_CONTROL_PDI_COUNT   (16U)
32816 
32817 /*! @name RECEIVE_TIMES - Distributed Clocks Receive Times */
32818 /*! @{ */
32819 
32820 #define ECAT_RECEIVE_TIMES_BF0_MASK              (0xFFU)
32821 #define ECAT_RECEIVE_TIMES_BF0_SHIFT             (0U)
32822 /*! BF0 - Write */
32823 #define ECAT_RECEIVE_TIMES_BF0(x)                (((uint32_t)(((uint32_t)(x)) << ECAT_RECEIVE_TIMES_BF0_SHIFT)) & ECAT_RECEIVE_TIMES_BF0_MASK)
32824 
32825 #define ECAT_RECEIVE_TIMES_BF8_MASK              (0xFFFFFF00U)
32826 #define ECAT_RECEIVE_TIMES_BF8_SHIFT             (8U)
32827 /*! BF8 - Local time at the beginning of the last receive frame containing a write access to register 0x0900. */
32828 #define ECAT_RECEIVE_TIMES_BF8(x)                (((uint32_t)(((uint32_t)(x)) << ECAT_RECEIVE_TIMES_BF8_SHIFT)) & ECAT_RECEIVE_TIMES_BF8_MASK)
32829 /*! @} */
32830 
32831 /*! @name RECEIVE_TIMES_PDI - Distributed Clocks Receive Times */
32832 /*! @{ */
32833 
32834 #define ECAT_RECEIVE_TIMES_PDI_BF0_MASK          (0xFFU)
32835 #define ECAT_RECEIVE_TIMES_PDI_BF0_SHIFT         (0U)
32836 /*! BF0 - Write */
32837 #define ECAT_RECEIVE_TIMES_PDI_BF0(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_RECEIVE_TIMES_PDI_BF0_SHIFT)) & ECAT_RECEIVE_TIMES_PDI_BF0_MASK)
32838 
32839 #define ECAT_RECEIVE_TIMES_PDI_BF8_MASK          (0xFFFFFF00U)
32840 #define ECAT_RECEIVE_TIMES_PDI_BF8_SHIFT         (8U)
32841 /*! BF8 - Local time at the beginning of the last receive frame containing a write access to register 0x0900. */
32842 #define ECAT_RECEIVE_TIMES_PDI_BF8(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_RECEIVE_TIMES_PDI_BF8_SHIFT)) & ECAT_RECEIVE_TIMES_PDI_BF8_MASK)
32843 /*! @} */
32844 
32845 /*! @name RECEIVE_TIME_PORT_1 - Distributed Clocks Receive Time Port 1 */
32846 /*! @{ */
32847 
32848 #define ECAT_RECEIVE_TIME_PORT_1_BF0_MASK        (0xFFFFFFFFU)
32849 #define ECAT_RECEIVE_TIME_PORT_1_BF0_SHIFT       (0U)
32850 /*! BF0 - Local time at the beginning of a frame (start first bit of preamble) received at port 1
32851  *    containing a BWR or FPWR to register 0x0900.
32852  */
32853 #define ECAT_RECEIVE_TIME_PORT_1_BF0(x)          (((uint32_t)(((uint32_t)(x)) << ECAT_RECEIVE_TIME_PORT_1_BF0_SHIFT)) & ECAT_RECEIVE_TIME_PORT_1_BF0_MASK)
32854 /*! @} */
32855 
32856 /*! @name SYSTEM_TIME - Register System Time */
32857 /*! @{ */
32858 
32859 #define ECAT_SYSTEM_TIME_BF0ECAT_MASK            (0xFFFFFFFFFFFFFFFFU)
32860 #define ECAT_SYSTEM_TIME_BF0ECAT_SHIFT           (0U)
32861 /*! BF0ECAT - ECAT read access */
32862 #define ECAT_SYSTEM_TIME_BF0ECAT(x)              (((uint64_t)(((uint64_t)(x)) << ECAT_SYSTEM_TIME_BF0ECAT_SHIFT)) & ECAT_SYSTEM_TIME_BF0ECAT_MASK)
32863 /*! @} */
32864 
32865 /*! @name SYSTEM_TIME_PDI - Register System Time */
32866 /*! @{ */
32867 
32868 #define ECAT_SYSTEM_TIME_PDI_BF0ECAT_MASK        (0xFFFFFFFFFFFFFFFFU)
32869 #define ECAT_SYSTEM_TIME_PDI_BF0ECAT_SHIFT       (0U)
32870 /*! BF0ECAT - PDI read access */
32871 #define ECAT_SYSTEM_TIME_PDI_BF0ECAT(x)          (((uint64_t)(((uint64_t)(x)) << ECAT_SYSTEM_TIME_PDI_BF0ECAT_SHIFT)) & ECAT_SYSTEM_TIME_PDI_BF0ECAT_MASK)
32872 /*! @} */
32873 
32874 /*! @name RECEIVE_TIME_ECAT_PROCESSING_UNIT - Distributed Clocks Register Receive Time ECAT Processing Unit */
32875 /*! @{ */
32876 
32877 #define ECAT_RECEIVE_TIME_ECAT_PROCESSING_UNIT_BF0_MASK (0xFFFFFFFFFFFFFFFFU)
32878 #define ECAT_RECEIVE_TIME_ECAT_PROCESSING_UNIT_BF0_SHIFT (0U)
32879 /*! BF0 - Local time at the beginning of a frame (start first bit of preamble) received at the ECAT
32880  *    Processing Unit containing a write access to register 0x0900
32881  */
32882 #define ECAT_RECEIVE_TIME_ECAT_PROCESSING_UNIT_BF0(x) (((uint64_t)(((uint64_t)(x)) << ECAT_RECEIVE_TIME_ECAT_PROCESSING_UNIT_BF0_SHIFT)) & ECAT_RECEIVE_TIME_ECAT_PROCESSING_UNIT_BF0_MASK)
32883 /*! @} */
32884 
32885 /*! @name SYSTEM_TIME_OFFSET - Register System Time Offset */
32886 /*! @{ */
32887 
32888 #define ECAT_SYSTEM_TIME_OFFSET_BF0_MASK         (0xFFFFFFFFFFFFFFFFU)
32889 #define ECAT_SYSTEM_TIME_OFFSET_BF0_SHIFT        (0U)
32890 /*! BF0 - Difference between local time and System Time. Offset is added to the local time. */
32891 #define ECAT_SYSTEM_TIME_OFFSET_BF0(x)           (((uint64_t)(((uint64_t)(x)) << ECAT_SYSTEM_TIME_OFFSET_BF0_SHIFT)) & ECAT_SYSTEM_TIME_OFFSET_BF0_MASK)
32892 /*! @} */
32893 
32894 /*! @name SYSTEM_TIME_DELAY - Register System Time Delay */
32895 /*! @{ */
32896 
32897 #define ECAT_SYSTEM_TIME_DELAY_BF0_MASK          (0xFFFFFFFFU)
32898 #define ECAT_SYSTEM_TIME_DELAY_BF0_SHIFT         (0U)
32899 /*! BF0 - Delay between Reference Clock and the eCAT */
32900 #define ECAT_SYSTEM_TIME_DELAY_BF0(x)            (((uint32_t)(((uint32_t)(x)) << ECAT_SYSTEM_TIME_DELAY_BF0_SHIFT)) & ECAT_SYSTEM_TIME_DELAY_BF0_MASK)
32901 /*! @} */
32902 
32903 /*! @name SYSTEM_TIME_DIFFERENCE - Register System Time Difference */
32904 /*! @{ */
32905 
32906 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF0_MASK     (0x7FFFFFFFU)
32907 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF0_SHIFT    (0U)
32908 /*! BF0 - Mean difference between local copy of system Time and received System Time values */
32909 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF0(x)       (((uint32_t)(((uint32_t)(x)) << ECAT_SYSTEM_TIME_DIFFERENCE_BF0_SHIFT)) & ECAT_SYSTEM_TIME_DIFFERENCE_BF0_MASK)
32910 
32911 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF31_MASK    (0x80000000U)
32912 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF31_SHIFT   (31U)
32913 /*! BF31 - Bit field access for ECAT: r/-
32914  *  0b0..Local copy of System Time less than received System Time
32915  *  0b1..Local copy of System Time greater than or equal to received System Time
32916  */
32917 #define ECAT_SYSTEM_TIME_DIFFERENCE_BF31(x)      (((uint32_t)(((uint32_t)(x)) << ECAT_SYSTEM_TIME_DIFFERENCE_BF31_SHIFT)) & ECAT_SYSTEM_TIME_DIFFERENCE_BF31_MASK)
32918 /*! @} */
32919 
32920 /*! @name SPEED_COUNTER_START - Register Speed Counter Start */
32921 /*! @{ */
32922 
32923 #define ECAT_SPEED_COUNTER_START_BF0_MASK        (0x7FFFU)
32924 #define ECAT_SPEED_COUNTER_START_BF0_SHIFT       (0U)
32925 /*! BF0 - Bandwidth for adjustment of local copy of system Time (larger values -> smaller bandwidth and smoother adjustment) */
32926 #define ECAT_SPEED_COUNTER_START_BF0(x)          (((uint16_t)(((uint16_t)(x)) << ECAT_SPEED_COUNTER_START_BF0_SHIFT)) & ECAT_SPEED_COUNTER_START_BF0_MASK)
32927 
32928 #define ECAT_SPEED_COUNTER_START_BF15_MASK       (0x8000U)
32929 #define ECAT_SPEED_COUNTER_START_BF15_SHIFT      (15U)
32930 /*! BF15 - Reserved, write 0 */
32931 #define ECAT_SPEED_COUNTER_START_BF15(x)         (((uint16_t)(((uint16_t)(x)) << ECAT_SPEED_COUNTER_START_BF15_SHIFT)) & ECAT_SPEED_COUNTER_START_BF15_MASK)
32932 /*! @} */
32933 
32934 /*! @name SPEED_COUNTER_DIFF - Register Speed Counter Diff */
32935 /*! @{ */
32936 
32937 #define ECAT_SPEED_COUNTER_DIFF_BF0_MASK         (0xFFFFU)
32938 #define ECAT_SPEED_COUNTER_DIFF_BF0_SHIFT        (0U)
32939 /*! BF0 - Representation of the deviation between local clock period and Reference Clock's clock
32940  *    period (representation: two's complement)
32941  */
32942 #define ECAT_SPEED_COUNTER_DIFF_BF0(x)           (((uint16_t)(((uint16_t)(x)) << ECAT_SPEED_COUNTER_DIFF_BF0_SHIFT)) & ECAT_SPEED_COUNTER_DIFF_BF0_MASK)
32943 /*! @} */
32944 
32945 /*! @name SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH - Register System Time Difference Filter Depth */
32946 /*! @{ */
32947 
32948 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF0_MASK (0xFU)
32949 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF0_SHIFT (0U)
32950 /*! BF0 - Filter depth for averaging the received System Time deviation */
32951 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF0(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF0_SHIFT)) & ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF0_MASK)
32952 
32953 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF4_MASK (0xF0U)
32954 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF4_SHIFT (4U)
32955 /*! BF4 - Reserved, write 0 */
32956 #define ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF4(x) (((uint8_t)(((uint8_t)(x)) << ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF4_SHIFT)) & ECAT_SYSTEM_TIME_DIFFERENCE_FILTER_DEPTH_BF4_MASK)
32957 /*! @} */
32958 
32959 /*! @name SPEED_COUNTER_FILTER_DEPTH - Register Speed Counter Filter Depth */
32960 /*! @{ */
32961 
32962 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF0_MASK (0xFU)
32963 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF0_SHIFT (0U)
32964 /*! BF0 - Filter depth for averaging the clock period deviation */
32965 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF0(x)   (((uint8_t)(((uint8_t)(x)) << ECAT_SPEED_COUNTER_FILTER_DEPTH_BF0_SHIFT)) & ECAT_SPEED_COUNTER_FILTER_DEPTH_BF0_MASK)
32966 
32967 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF4_MASK (0xF0U)
32968 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF4_SHIFT (4U)
32969 /*! BF4 - Reserved, write 0 */
32970 #define ECAT_SPEED_COUNTER_FILTER_DEPTH_BF4(x)   (((uint8_t)(((uint8_t)(x)) << ECAT_SPEED_COUNTER_FILTER_DEPTH_BF4_SHIFT)) & ECAT_SPEED_COUNTER_FILTER_DEPTH_BF4_MASK)
32971 /*! @} */
32972 
32973 /*! @name CYCLIC_UNIT_CONTROL - Register Cyclic Unit Control */
32974 /*! @{ */
32975 
32976 #define ECAT_CYCLIC_UNIT_CONTROL_BF0_MASK        (0x1U)
32977 #define ECAT_CYCLIC_UNIT_CONTROL_BF0_SHIFT       (0U)
32978 /*! BF0 - SYNC out unit control:
32979  *  0b0..ECAT-controlled
32980  *  0b1..PDI-controlled
32981  */
32982 #define ECAT_CYCLIC_UNIT_CONTROL_BF0(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_BF0_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_BF0_MASK)
32983 
32984 #define ECAT_CYCLIC_UNIT_CONTROL_BF1_MASK        (0xEU)
32985 #define ECAT_CYCLIC_UNIT_CONTROL_BF1_SHIFT       (1U)
32986 /*! BF1 - Reserved, write 0 */
32987 #define ECAT_CYCLIC_UNIT_CONTROL_BF1(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_BF1_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_BF1_MASK)
32988 
32989 #define ECAT_CYCLIC_UNIT_CONTROL_BF4_MASK        (0x10U)
32990 #define ECAT_CYCLIC_UNIT_CONTROL_BF4_SHIFT       (4U)
32991 /*! BF4 - Latch In unit 0:
32992  *  0b0..ECAT-controlled
32993  *  0b1..PDI-controlled
32994  */
32995 #define ECAT_CYCLIC_UNIT_CONTROL_BF4(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_BF4_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_BF4_MASK)
32996 
32997 #define ECAT_CYCLIC_UNIT_CONTROL_BF5_MASK        (0x20U)
32998 #define ECAT_CYCLIC_UNIT_CONTROL_BF5_SHIFT       (5U)
32999 /*! BF5 - Latch In unit 1:
33000  *  0b0..ECAT-controlled
33001  *  0b1..PDI-controlled
33002  */
33003 #define ECAT_CYCLIC_UNIT_CONTROL_BF5(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_BF5_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_BF5_MASK)
33004 
33005 #define ECAT_CYCLIC_UNIT_CONTROL_BF6_MASK        (0xC0U)
33006 #define ECAT_CYCLIC_UNIT_CONTROL_BF6_SHIFT       (6U)
33007 /*! BF6 - Reserved, write 0 */
33008 #define ECAT_CYCLIC_UNIT_CONTROL_BF6(x)          (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_BF6_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_BF6_MASK)
33009 /*! @} */
33010 
33011 /*! @name CYCLIC_UNIT_CONTROL_PDI - Register Cyclic Unit Control */
33012 /*! @{ */
33013 
33014 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF0_MASK    (0x1U)
33015 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF0_SHIFT   (0U)
33016 /*! BF0 - SYNC out unit control:
33017  *  0b0..ECAT-controlled
33018  *  0b1..PDI-controlled
33019  */
33020 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF0(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_PDI_BF0_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_PDI_BF0_MASK)
33021 
33022 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF1_MASK    (0xEU)
33023 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF1_SHIFT   (1U)
33024 /*! BF1 - Reserved, write 0 */
33025 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF1(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_PDI_BF1_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_PDI_BF1_MASK)
33026 
33027 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF4_MASK    (0x10U)
33028 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF4_SHIFT   (4U)
33029 /*! BF4 - Latch In unit 0:
33030  *  0b0..ECAT-controlled
33031  *  0b1..PDI-controlled
33032  */
33033 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF4(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_PDI_BF4_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_PDI_BF4_MASK)
33034 
33035 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF5_MASK    (0x20U)
33036 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF5_SHIFT   (5U)
33037 /*! BF5 - Latch In unit 1:
33038  *  0b0..ECAT-controlled
33039  *  0b1..PDI-controlled
33040  */
33041 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF5(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_PDI_BF5_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_PDI_BF5_MASK)
33042 
33043 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF6_MASK    (0xC0U)
33044 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF6_SHIFT   (6U)
33045 /*! BF6 - Reserved, write 0 */
33046 #define ECAT_CYCLIC_UNIT_CONTROL_PDI_BF6(x)      (((uint8_t)(((uint8_t)(x)) << ECAT_CYCLIC_UNIT_CONTROL_PDI_BF6_SHIFT)) & ECAT_CYCLIC_UNIT_CONTROL_PDI_BF6_MASK)
33047 /*! @} */
33048 
33049 /*! @name UNIT_ACTIVATION_REGISTER - Register Activation register */
33050 /*! @{ */
33051 
33052 #define ECAT_UNIT_ACTIVATION_REGISTER_BF0_MASK   (0x1U)
33053 #define ECAT_UNIT_ACTIVATION_REGISTER_BF0_SHIFT  (0U)
33054 /*! BF0 - Sync Out Unit activation:
33055  *  0b0..Deactivated
33056  *  0b1..Activated
33057  */
33058 #define ECAT_UNIT_ACTIVATION_REGISTER_BF0(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF0_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF0_MASK)
33059 
33060 #define ECAT_UNIT_ACTIVATION_REGISTER_BF1_MASK   (0x2U)
33061 #define ECAT_UNIT_ACTIVATION_REGISTER_BF1_SHIFT  (1U)
33062 /*! BF1 - SYNC0 generation:
33063  *  0b0..Deactivated
33064  *  0b1..SYNC0 pulse is generated
33065  */
33066 #define ECAT_UNIT_ACTIVATION_REGISTER_BF1(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF1_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF1_MASK)
33067 
33068 #define ECAT_UNIT_ACTIVATION_REGISTER_BF2_MASK   (0x4U)
33069 #define ECAT_UNIT_ACTIVATION_REGISTER_BF2_SHIFT  (2U)
33070 /*! BF2 - SYNC1 generation:
33071  *  0b0..Deactivated
33072  *  0b1..SYNC1 pulse is generated
33073  */
33074 #define ECAT_UNIT_ACTIVATION_REGISTER_BF2(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF2_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF2_MASK)
33075 
33076 #define ECAT_UNIT_ACTIVATION_REGISTER_BF3_MASK   (0x8U)
33077 #define ECAT_UNIT_ACTIVATION_REGISTER_BF3_SHIFT  (3U)
33078 /*! BF3 - Auto-activation by writing Start Time Cyclic Operation (0x0990:0x0997):
33079  *  0b0..Disabled
33080  *  0b1..Auto-activation enabled. 0x0981[0] is set automatically after Start Time is written
33081  */
33082 #define ECAT_UNIT_ACTIVATION_REGISTER_BF3(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF3_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF3_MASK)
33083 
33084 #define ECAT_UNIT_ACTIVATION_REGISTER_BF4_MASK   (0x10U)
33085 #define ECAT_UNIT_ACTIVATION_REGISTER_BF4_SHIFT  (4U)
33086 /*! BF4 - Extension of Start Time Cyclic Operation (0x0990:0x0993):
33087  *  0b0..No extension
33088  *  0b1..Extend 32 bit written Start Time to 64 bit
33089  */
33090 #define ECAT_UNIT_ACTIVATION_REGISTER_BF4(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF4_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF4_MASK)
33091 
33092 #define ECAT_UNIT_ACTIVATION_REGISTER_BF5_MASK   (0x20U)
33093 #define ECAT_UNIT_ACTIVATION_REGISTER_BF5_SHIFT  (5U)
33094 /*! BF5 - Start Time plausibility check:
33095  *  0b0..Disabled. SyncSignal generation if Start Time is reached.
33096  *  0b1..Immediate SyncSignal generation if Start Time is outside near future (see 0x0981[6])
33097  */
33098 #define ECAT_UNIT_ACTIVATION_REGISTER_BF5(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF5_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF5_MASK)
33099 
33100 #define ECAT_UNIT_ACTIVATION_REGISTER_BF6_MASK   (0x40U)
33101 #define ECAT_UNIT_ACTIVATION_REGISTER_BF6_SHIFT  (6U)
33102 /*! BF6 - Near future configuration (approx.):
33103  *  0b0..1/2 DC width future (2^31ns or 2^63ns)
33104  *  0b1..~2.1 sec. future (2^31ns)
33105  */
33106 #define ECAT_UNIT_ACTIVATION_REGISTER_BF6(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF6_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF6_MASK)
33107 
33108 #define ECAT_UNIT_ACTIVATION_REGISTER_BF7_MASK   (0x80U)
33109 #define ECAT_UNIT_ACTIVATION_REGISTER_BF7_SHIFT  (7U)
33110 /*! BF7 - SyncSignal debug pulse (Vasily bit):
33111  *  0b0..Deactivated
33112  *  0b1..Immediately generate one ping only on SYNC0-1 according to 0x0981[2:1] for debugging.
33113  */
33114 #define ECAT_UNIT_ACTIVATION_REGISTER_BF7(x)     (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_REGISTER_BF7_SHIFT)) & ECAT_UNIT_ACTIVATION_REGISTER_BF7_MASK)
33115 /*! @} */
33116 
33117 /*! @name UNI_PULSE_LENGTH_OF_SYNCSIGNALS - Register Pulse Length of SyncSignals */
33118 /*! @{ */
33119 
33120 #define ECAT_UNI_PULSE_LENGTH_OF_SYNCSIGNALS_BF0_MASK (0xFFFFU)
33121 #define ECAT_UNI_PULSE_LENGTH_OF_SYNCSIGNALS_BF0_SHIFT (0U)
33122 /*! BF0 - Pulse length of SyncSignals (in Units of 10ns)
33123  *  0b0000000000000000..Acknowledge mode: SyncSignal will be cleared by reading SYNC[1:0] Status register
33124  */
33125 #define ECAT_UNI_PULSE_LENGTH_OF_SYNCSIGNALS_BF0(x) (((uint16_t)(((uint16_t)(x)) << ECAT_UNI_PULSE_LENGTH_OF_SYNCSIGNALS_BF0_SHIFT)) & ECAT_UNI_PULSE_LENGTH_OF_SYNCSIGNALS_BF0_MASK)
33126 /*! @} */
33127 
33128 /*! @name UNIT_ACTIVATION_STATUS - Register Activation Status */
33129 /*! @{ */
33130 
33131 #define ECAT_UNIT_ACTIVATION_STATUS_BF0_MASK     (0x1U)
33132 #define ECAT_UNIT_ACTIVATION_STATUS_BF0_SHIFT    (0U)
33133 /*! BF0 - SYNC0 activation state:
33134  *  0b0..First SYNC0 pulse is not pending
33135  *  0b1..First SYNC0 pulse is pending
33136  */
33137 #define ECAT_UNIT_ACTIVATION_STATUS_BF0(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_STATUS_BF0_SHIFT)) & ECAT_UNIT_ACTIVATION_STATUS_BF0_MASK)
33138 
33139 #define ECAT_UNIT_ACTIVATION_STATUS_BF1_MASK     (0x2U)
33140 #define ECAT_UNIT_ACTIVATION_STATUS_BF1_SHIFT    (1U)
33141 /*! BF1 - SYNC1 activation state:
33142  *  0b0..First SYNC1 pulse is not pending
33143  *  0b1..First SYNC1 pulse is pending
33144  */
33145 #define ECAT_UNIT_ACTIVATION_STATUS_BF1(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_STATUS_BF1_SHIFT)) & ECAT_UNIT_ACTIVATION_STATUS_BF1_MASK)
33146 
33147 #define ECAT_UNIT_ACTIVATION_STATUS_BF2_MASK     (0x4U)
33148 #define ECAT_UNIT_ACTIVATION_STATUS_BF2_SHIFT    (2U)
33149 /*! BF2 - Start Time Cyclic Operation (0x0990:0x0997) plausibility check result when Sync Out Unit was activated:
33150  *  0b0..Start Time was within near future
33151  *  0b1..Start Time was out of near future (0x0981[6])
33152  */
33153 #define ECAT_UNIT_ACTIVATION_STATUS_BF2(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_STATUS_BF2_SHIFT)) & ECAT_UNIT_ACTIVATION_STATUS_BF2_MASK)
33154 
33155 #define ECAT_UNIT_ACTIVATION_STATUS_BF3_MASK     (0xF8U)
33156 #define ECAT_UNIT_ACTIVATION_STATUS_BF3_SHIFT    (3U)
33157 /*! BF3 - Reserved */
33158 #define ECAT_UNIT_ACTIVATION_STATUS_BF3(x)       (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_ACTIVATION_STATUS_BF3_SHIFT)) & ECAT_UNIT_ACTIVATION_STATUS_BF3_MASK)
33159 /*! @} */
33160 
33161 /*! @name UNIT_SYNC0_STATUS - Register SYNC0 Status */
33162 /*! @{ */
33163 
33164 #define ECAT_UNIT_SYNC0_STATUS_BF0_MASK          (0x1U)
33165 #define ECAT_UNIT_SYNC0_STATUS_BF0_SHIFT         (0U)
33166 /*! BF0 - SYNC0 state for Acknowledge mode. */
33167 #define ECAT_UNIT_SYNC0_STATUS_BF0(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_SYNC0_STATUS_BF0_SHIFT)) & ECAT_UNIT_SYNC0_STATUS_BF0_MASK)
33168 
33169 #define ECAT_UNIT_SYNC0_STATUS_BF1_MASK          (0xFEU)
33170 #define ECAT_UNIT_SYNC0_STATUS_BF1_SHIFT         (1U)
33171 /*! BF1 - Reserved */
33172 #define ECAT_UNIT_SYNC0_STATUS_BF1(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_SYNC0_STATUS_BF1_SHIFT)) & ECAT_UNIT_SYNC0_STATUS_BF1_MASK)
33173 /*! @} */
33174 
33175 /*! @name UNIT_SYNC1_STATUS - Register SYNC1 Status */
33176 /*! @{ */
33177 
33178 #define ECAT_UNIT_SYNC1_STATUS_BF0_MASK          (0x1U)
33179 #define ECAT_UNIT_SYNC1_STATUS_BF0_SHIFT         (0U)
33180 /*! BF0 - SYNC1 state for Acknowledge mode. */
33181 #define ECAT_UNIT_SYNC1_STATUS_BF0(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_SYNC1_STATUS_BF0_SHIFT)) & ECAT_UNIT_SYNC1_STATUS_BF0_MASK)
33182 
33183 #define ECAT_UNIT_SYNC1_STATUS_BF1_MASK          (0xFEU)
33184 #define ECAT_UNIT_SYNC1_STATUS_BF1_SHIFT         (1U)
33185 /*! BF1 - Reserved */
33186 #define ECAT_UNIT_SYNC1_STATUS_BF1(x)            (((uint8_t)(((uint8_t)(x)) << ECAT_UNIT_SYNC1_STATUS_BF1_SHIFT)) & ECAT_UNIT_SYNC1_STATUS_BF1_MASK)
33187 /*! @} */
33188 
33189 /*! @name UNIT_START_TIME_CYCLIC_OPERATION - Register Start Time Cyclic Operation */
33190 /*! @{ */
33191 
33192 #define ECAT_UNIT_START_TIME_CYCLIC_OPERATION_BF0_MASK (0xFFFFFFFFFFFFFFFFU)
33193 #define ECAT_UNIT_START_TIME_CYCLIC_OPERATION_BF0_SHIFT (0U)
33194 /*! BF0 - Write: Start time (System time) of cyclic operation in ns */
33195 #define ECAT_UNIT_START_TIME_CYCLIC_OPERATION_BF0(x) (((uint64_t)(((uint64_t)(x)) << ECAT_UNIT_START_TIME_CYCLIC_OPERATION_BF0_SHIFT)) & ECAT_UNIT_START_TIME_CYCLIC_OPERATION_BF0_MASK)
33196 /*! @} */
33197 
33198 /*! @name UNIT_NEXT_SYNC1_PULSE - Register Next SYNC1 Pulse */
33199 /*! @{ */
33200 
33201 #define ECAT_UNIT_NEXT_SYNC1_PULSE_BF0_MASK      (0xFFFFFFFFFFFFFFFFU)
33202 #define ECAT_UNIT_NEXT_SYNC1_PULSE_BF0_SHIFT     (0U)
33203 /*! BF0 - System time of next SYNC1 pulse in ns */
33204 #define ECAT_UNIT_NEXT_SYNC1_PULSE_BF0(x)        (((uint64_t)(((uint64_t)(x)) << ECAT_UNIT_NEXT_SYNC1_PULSE_BF0_SHIFT)) & ECAT_UNIT_NEXT_SYNC1_PULSE_BF0_MASK)
33205 /*! @} */
33206 
33207 /*! @name UNIT_SYNC0_CYCLE_TIME - Register SYNC0 Cycle Time */
33208 /*! @{ */
33209 
33210 #define ECAT_UNIT_SYNC0_CYCLE_TIME_BF0_MASK      (0xFFFFFFFFU)
33211 #define ECAT_UNIT_SYNC0_CYCLE_TIME_BF0_SHIFT     (0U)
33212 /*! BF0 - Time between two consecutive SYNC0 pulses in ns.
33213  *  0b00000000000000000000000000000000..Single shot mode, generate only one SYNC0 pulse.
33214  */
33215 #define ECAT_UNIT_SYNC0_CYCLE_TIME_BF0(x)        (((uint32_t)(((uint32_t)(x)) << ECAT_UNIT_SYNC0_CYCLE_TIME_BF0_SHIFT)) & ECAT_UNIT_SYNC0_CYCLE_TIME_BF0_MASK)
33216 /*! @} */
33217 
33218 /*! @name UNIT_SYNC1_CYCLE_TIME - Register SYNC1 Cycle Time */
33219 /*! @{ */
33220 
33221 #define ECAT_UNIT_SYNC1_CYCLE_TIME_BF0_MASK      (0xFFFFFFFFU)
33222 #define ECAT_UNIT_SYNC1_CYCLE_TIME_BF0_SHIFT     (0U)
33223 /*! BF0 - Time between SYNC0 pulse and SYNC1 pulse in ns */
33224 #define ECAT_UNIT_SYNC1_CYCLE_TIME_BF0(x)        (((uint32_t)(((uint32_t)(x)) << ECAT_UNIT_SYNC1_CYCLE_TIME_BF0_SHIFT)) & ECAT_UNIT_SYNC1_CYCLE_TIME_BF0_MASK)
33225 /*! @} */
33226 
33227 /*! @name LATCH0_CONTROL - Register Latch0 Control */
33228 /*! @{ */
33229 
33230 #define ECAT_LATCH0_CONTROL_BF0_MASK             (0x1U)
33231 #define ECAT_LATCH0_CONTROL_BF0_SHIFT            (0U)
33232 /*! BF0 - Latch0 positive edge:
33233  *  0b0..Continuous Latch active
33234  *  0b1..Single event (only first event active)
33235  */
33236 #define ECAT_LATCH0_CONTROL_BF0(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_CONTROL_BF0_SHIFT)) & ECAT_LATCH0_CONTROL_BF0_MASK)
33237 
33238 #define ECAT_LATCH0_CONTROL_BF1_MASK             (0x2U)
33239 #define ECAT_LATCH0_CONTROL_BF1_SHIFT            (1U)
33240 /*! BF1 - Latch0 negative edge:
33241  *  0b0..Continuous Latch active
33242  *  0b1..Single event (only first event active)
33243  */
33244 #define ECAT_LATCH0_CONTROL_BF1(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_CONTROL_BF1_SHIFT)) & ECAT_LATCH0_CONTROL_BF1_MASK)
33245 
33246 #define ECAT_LATCH0_CONTROL_BF2_MASK             (0xFCU)
33247 #define ECAT_LATCH0_CONTROL_BF2_SHIFT            (2U)
33248 /*! BF2 - Reserved, write 0 */
33249 #define ECAT_LATCH0_CONTROL_BF2(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_CONTROL_BF2_SHIFT)) & ECAT_LATCH0_CONTROL_BF2_MASK)
33250 /*! @} */
33251 
33252 /*! @name LATCH1_CONTROL - Register Latch1 Control */
33253 /*! @{ */
33254 
33255 #define ECAT_LATCH1_CONTROL_BF0_MASK             (0x1U)
33256 #define ECAT_LATCH1_CONTROL_BF0_SHIFT            (0U)
33257 /*! BF0 - Latch1 positive edge:
33258  *  0b0..Continuous Latch active
33259  *  0b1..Single event (only first event active)
33260  */
33261 #define ECAT_LATCH1_CONTROL_BF0(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_CONTROL_BF0_SHIFT)) & ECAT_LATCH1_CONTROL_BF0_MASK)
33262 
33263 #define ECAT_LATCH1_CONTROL_BF1_MASK             (0x2U)
33264 #define ECAT_LATCH1_CONTROL_BF1_SHIFT            (1U)
33265 /*! BF1 - Latch1 negative edge:
33266  *  0b0..Continuous Latch active
33267  *  0b1..Single event (only first event active)
33268  */
33269 #define ECAT_LATCH1_CONTROL_BF1(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_CONTROL_BF1_SHIFT)) & ECAT_LATCH1_CONTROL_BF1_MASK)
33270 
33271 #define ECAT_LATCH1_CONTROL_BF2_MASK             (0xFCU)
33272 #define ECAT_LATCH1_CONTROL_BF2_SHIFT            (2U)
33273 /*! BF2 - Reserved, write 0 */
33274 #define ECAT_LATCH1_CONTROL_BF2(x)               (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_CONTROL_BF2_SHIFT)) & ECAT_LATCH1_CONTROL_BF2_MASK)
33275 /*! @} */
33276 
33277 /*! @name LATCH0_STATUS - Register Latch0 Status */
33278 /*! @{ */
33279 
33280 #define ECAT_LATCH0_STATUS_BF0_MASK              (0x1U)
33281 #define ECAT_LATCH0_STATUS_BF0_SHIFT             (0U)
33282 /*! BF0 - Event Latch0 positive edge.
33283  *  0b0..Positive edge not detected or continuous mode
33284  *  0b1..Positive edge detected in single event mode only.
33285  */
33286 #define ECAT_LATCH0_STATUS_BF0(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_STATUS_BF0_SHIFT)) & ECAT_LATCH0_STATUS_BF0_MASK)
33287 
33288 #define ECAT_LATCH0_STATUS_BF1_MASK              (0x2U)
33289 #define ECAT_LATCH0_STATUS_BF1_SHIFT             (1U)
33290 /*! BF1 - Event Latch0 negative edge.
33291  *  0b0..Negative edge not detected or continuous mode
33292  *  0b1..Negative edge detected in single event mode only
33293  */
33294 #define ECAT_LATCH0_STATUS_BF1(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_STATUS_BF1_SHIFT)) & ECAT_LATCH0_STATUS_BF1_MASK)
33295 
33296 #define ECAT_LATCH0_STATUS_BF2_MASK              (0x4U)
33297 #define ECAT_LATCH0_STATUS_BF2_SHIFT             (2U)
33298 /*! BF2 - Latch0 pin state */
33299 #define ECAT_LATCH0_STATUS_BF2(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_STATUS_BF2_SHIFT)) & ECAT_LATCH0_STATUS_BF2_MASK)
33300 
33301 #define ECAT_LATCH0_STATUS_BF3_MASK              (0xF8U)
33302 #define ECAT_LATCH0_STATUS_BF3_SHIFT             (3U)
33303 /*! BF3 - Reserved */
33304 #define ECAT_LATCH0_STATUS_BF3(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH0_STATUS_BF3_SHIFT)) & ECAT_LATCH0_STATUS_BF3_MASK)
33305 /*! @} */
33306 
33307 /*! @name LATCH1_STATUS - Register Latch1 Status */
33308 /*! @{ */
33309 
33310 #define ECAT_LATCH1_STATUS_BF0_MASK              (0x1U)
33311 #define ECAT_LATCH1_STATUS_BF0_SHIFT             (0U)
33312 /*! BF0 - Event Latch1 positive edge.
33313  *  0b0..Positive edge not detected or continuous mode
33314  *  0b1..Positive edge detected in single event mode only.
33315  */
33316 #define ECAT_LATCH1_STATUS_BF0(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_STATUS_BF0_SHIFT)) & ECAT_LATCH1_STATUS_BF0_MASK)
33317 
33318 #define ECAT_LATCH1_STATUS_BF1_MASK              (0x2U)
33319 #define ECAT_LATCH1_STATUS_BF1_SHIFT             (1U)
33320 /*! BF1 - Event Latch1 negative edge.
33321  *  0b0..Negative edge not detected or continuous mode
33322  *  0b1..Negative edge detected in single event mode only.
33323  */
33324 #define ECAT_LATCH1_STATUS_BF1(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_STATUS_BF1_SHIFT)) & ECAT_LATCH1_STATUS_BF1_MASK)
33325 
33326 #define ECAT_LATCH1_STATUS_BF2_MASK              (0x4U)
33327 #define ECAT_LATCH1_STATUS_BF2_SHIFT             (2U)
33328 /*! BF2 - Latch1 pin state */
33329 #define ECAT_LATCH1_STATUS_BF2(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_STATUS_BF2_SHIFT)) & ECAT_LATCH1_STATUS_BF2_MASK)
33330 
33331 #define ECAT_LATCH1_STATUS_BF3_MASK              (0xF8U)
33332 #define ECAT_LATCH1_STATUS_BF3_SHIFT             (3U)
33333 /*! BF3 - Reserved */
33334 #define ECAT_LATCH1_STATUS_BF3(x)                (((uint8_t)(((uint8_t)(x)) << ECAT_LATCH1_STATUS_BF3_SHIFT)) & ECAT_LATCH1_STATUS_BF3_MASK)
33335 /*! @} */
33336 
33337 /*! @name LATCH0_TIME_POSITIVE_EDGE - Register Latch0 Time Positive Edge */
33338 /*! @{ */
33339 
33340 #define ECAT_LATCH0_TIME_POSITIVE_EDGE_BF0_MASK  (0xFFFFFFFFFFFFFFFFU)
33341 #define ECAT_LATCH0_TIME_POSITIVE_EDGE_BF0_SHIFT (0U)
33342 /*! BF0 - System time at the positive edge of the Latch0 signal. */
33343 #define ECAT_LATCH0_TIME_POSITIVE_EDGE_BF0(x)    (((uint64_t)(((uint64_t)(x)) << ECAT_LATCH0_TIME_POSITIVE_EDGE_BF0_SHIFT)) & ECAT_LATCH0_TIME_POSITIVE_EDGE_BF0_MASK)
33344 /*! @} */
33345 
33346 /*! @name LATCH0_TIME_NEGATIVE_EDGE - Register Latch0 Time Negative Edge */
33347 /*! @{ */
33348 
33349 #define ECAT_LATCH0_TIME_NEGATIVE_EDGE_BF0_MASK  (0xFFFFFFFFFFFFFFFFU)
33350 #define ECAT_LATCH0_TIME_NEGATIVE_EDGE_BF0_SHIFT (0U)
33351 /*! BF0 - System time at the negative edge of the Latch0 signal. */
33352 #define ECAT_LATCH0_TIME_NEGATIVE_EDGE_BF0(x)    (((uint64_t)(((uint64_t)(x)) << ECAT_LATCH0_TIME_NEGATIVE_EDGE_BF0_SHIFT)) & ECAT_LATCH0_TIME_NEGATIVE_EDGE_BF0_MASK)
33353 /*! @} */
33354 
33355 /*! @name LATCH1_TIME_POSITIVE_EDGE - Register Latch1 Time Positive Edge */
33356 /*! @{ */
33357 
33358 #define ECAT_LATCH1_TIME_POSITIVE_EDGE_BF0_MASK  (0xFFFFFFFFFFFFFFFFU)
33359 #define ECAT_LATCH1_TIME_POSITIVE_EDGE_BF0_SHIFT (0U)
33360 /*! BF0 - System time at the positive edge of the Latch1 signal. */
33361 #define ECAT_LATCH1_TIME_POSITIVE_EDGE_BF0(x)    (((uint64_t)(((uint64_t)(x)) << ECAT_LATCH1_TIME_POSITIVE_EDGE_BF0_SHIFT)) & ECAT_LATCH1_TIME_POSITIVE_EDGE_BF0_MASK)
33362 /*! @} */
33363 
33364 /*! @name LATCH1_TIME_NEGATIVE_EDGE - Register Latch1 Time Negative Edge */
33365 /*! @{ */
33366 
33367 #define ECAT_LATCH1_TIME_NEGATIVE_EDGE_BF0_MASK  (0xFFFFFFFFFFFFFFFFU)
33368 #define ECAT_LATCH1_TIME_NEGATIVE_EDGE_BF0_SHIFT (0U)
33369 /*! BF0 - System time at the negative edge of the Latch1 signal. */
33370 #define ECAT_LATCH1_TIME_NEGATIVE_EDGE_BF0(x)    (((uint64_t)(((uint64_t)(x)) << ECAT_LATCH1_TIME_NEGATIVE_EDGE_BF0_SHIFT)) & ECAT_LATCH1_TIME_NEGATIVE_EDGE_BF0_MASK)
33371 /*! @} */
33372 
33373 /*! @name ETHERCAT_BUFFER_CHANGE_EVENT_TIME - Register EtherCAT Buffer Change Event Time */
33374 /*! @{ */
33375 
33376 #define ECAT_ETHERCAT_BUFFER_CHANGE_EVENT_TIME_BF0_MASK (0xFFFFFFFFU)
33377 #define ECAT_ETHERCAT_BUFFER_CHANGE_EVENT_TIME_BF0_SHIFT (0U)
33378 /*! BF0 - Local time at the beginning of the frame which causes at least one SyncManager to assert an ECAT event */
33379 #define ECAT_ETHERCAT_BUFFER_CHANGE_EVENT_TIME_BF0(x) (((uint32_t)(((uint32_t)(x)) << ECAT_ETHERCAT_BUFFER_CHANGE_EVENT_TIME_BF0_SHIFT)) & ECAT_ETHERCAT_BUFFER_CHANGE_EVENT_TIME_BF0_MASK)
33380 /*! @} */
33381 
33382 /*! @name PDI_BUFFER_START_EVENT_TIME - Register PDI Buffer Start Event Time */
33383 /*! @{ */
33384 
33385 #define ECAT_PDI_BUFFER_START_EVENT_TIME_BF0_MASK (0xFFFFFFFFU)
33386 #define ECAT_PDI_BUFFER_START_EVENT_TIME_BF0_SHIFT (0U)
33387 /*! BF0 - Local time when at least one SyncManager asserts a PDI buffer start event */
33388 #define ECAT_PDI_BUFFER_START_EVENT_TIME_BF0(x)  (((uint32_t)(((uint32_t)(x)) << ECAT_PDI_BUFFER_START_EVENT_TIME_BF0_SHIFT)) & ECAT_PDI_BUFFER_START_EVENT_TIME_BF0_MASK)
33389 /*! @} */
33390 
33391 /*! @name PDI_BUFFER_CHANGE_EVENT_TIME - Register PDI Buffer Change Event Time */
33392 /*! @{ */
33393 
33394 #define ECAT_PDI_BUFFER_CHANGE_EVENT_TIME_BF0_MASK (0xFFFFFFFFU)
33395 #define ECAT_PDI_BUFFER_CHANGE_EVENT_TIME_BF0_SHIFT (0U)
33396 /*! BF0 - Local time when at least one SyncManager asserts a PDI buffer change event */
33397 #define ECAT_PDI_BUFFER_CHANGE_EVENT_TIME_BF0(x) (((uint32_t)(((uint32_t)(x)) << ECAT_PDI_BUFFER_CHANGE_EVENT_TIME_BF0_SHIFT)) & ECAT_PDI_BUFFER_CHANGE_EVENT_TIME_BF0_MASK)
33398 /*! @} */
33399 
33400 /*! @name PRODUCT_ID_IP_CORE - Register Product ID IP Core */
33401 /*! @{ */
33402 
33403 #define ECAT_PRODUCT_ID_IP_CORE_BF0_MASK         (0xFFFFFFFFFFFFFFFFU)
33404 #define ECAT_PRODUCT_ID_IP_CORE_BF0_SHIFT        (0U)
33405 /*! BF0 - Product ID */
33406 #define ECAT_PRODUCT_ID_IP_CORE_BF0(x)           (((uint64_t)(((uint64_t)(x)) << ECAT_PRODUCT_ID_IP_CORE_BF0_SHIFT)) & ECAT_PRODUCT_ID_IP_CORE_BF0_MASK)
33407 /*! @} */
33408 
33409 /*! @name VENDOR_ID_IP_CORE - Register Vendor ID IP Core */
33410 /*! @{ */
33411 
33412 #define ECAT_VENDOR_ID_IP_CORE_BF0_MASK          (0xFFFFFFFFU)
33413 #define ECAT_VENDOR_ID_IP_CORE_BF0_SHIFT         (0U)
33414 /*! BF0 - Vendor ID */
33415 #define ECAT_VENDOR_ID_IP_CORE_BF0(x)            (((uint64_t)(((uint64_t)(x)) << ECAT_VENDOR_ID_IP_CORE_BF0_SHIFT)) & ECAT_VENDOR_ID_IP_CORE_BF0_MASK)
33416 
33417 #define ECAT_VENDOR_ID_IP_CORE_BF32_MASK         (0xFFFFFFFF00000000U)
33418 #define ECAT_VENDOR_ID_IP_CORE_BF32_SHIFT        (32U)
33419 /*! BF32 - Reserved */
33420 #define ECAT_VENDOR_ID_IP_CORE_BF32(x)           (((uint64_t)(((uint64_t)(x)) << ECAT_VENDOR_ID_IP_CORE_BF32_SHIFT)) & ECAT_VENDOR_ID_IP_CORE_BF32_MASK)
33421 /*! @} */
33422 
33423 /*! @name GENERAL_PURPOSE_OUTPUTS - Register General Purpose Outputs */
33424 /*! @{ */
33425 
33426 #define ECAT_GENERAL_PURPOSE_OUTPUTS_BF0_MASK    (0xFFFFU)
33427 #define ECAT_GENERAL_PURPOSE_OUTPUTS_BF0_SHIFT   (0U)
33428 /*! BF0 - General Purpose Output Data */
33429 #define ECAT_GENERAL_PURPOSE_OUTPUTS_BF0(x)      (((uint16_t)(((uint16_t)(x)) << ECAT_GENERAL_PURPOSE_OUTPUTS_BF0_SHIFT)) & ECAT_GENERAL_PURPOSE_OUTPUTS_BF0_MASK)
33430 /*! @} */
33431 
33432 /*! @name GENERAL_PURPOSE_INPUTS - Register General Purpose Inputs */
33433 /*! @{ */
33434 
33435 #define ECAT_GENERAL_PURPOSE_INPUTS_BF0_MASK     (0xFFFFU)
33436 #define ECAT_GENERAL_PURPOSE_INPUTS_BF0_SHIFT    (0U)
33437 /*! BF0 - General Purpose Input Data */
33438 #define ECAT_GENERAL_PURPOSE_INPUTS_BF0(x)       (((uint16_t)(((uint16_t)(x)) << ECAT_GENERAL_PURPOSE_INPUTS_BF0_SHIFT)) & ECAT_GENERAL_PURPOSE_INPUTS_BF0_MASK)
33439 /*! @} */
33440 
33441 
33442 /*!
33443  * @}
33444  */ /* end of group ECAT_Register_Masks */
33445 
33446 
33447 /* ECAT - Peripheral instance base addresses */
33448 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
33449   /** Peripheral ECAT base address */
33450   #define ECAT_BASE                                (0x52A80000u)
33451   /** Peripheral ECAT base address */
33452   #define ECAT_BASE_NS                             (0x42A80000u)
33453   /** Peripheral ECAT base pointer */
33454   #define ECAT                                     ((ECAT_Type *)ECAT_BASE)
33455   /** Peripheral ECAT base pointer */
33456   #define ECAT_NS                                  ((ECAT_Type *)ECAT_BASE_NS)
33457   /** Array initializer of ECAT peripheral base addresses */
33458   #define ECAT_BASE_ADDRS                          { ECAT_BASE }
33459   /** Array initializer of ECAT peripheral base pointers */
33460   #define ECAT_BASE_PTRS                           { ECAT }
33461   /** Array initializer of ECAT peripheral base addresses */
33462   #define ECAT_BASE_ADDRS_NS                       { ECAT_BASE_NS }
33463   /** Array initializer of ECAT peripheral base pointers */
33464   #define ECAT_BASE_PTRS_NS                        { ECAT_NS }
33465 #else
33466   /** Peripheral ECAT base address */
33467   #define ECAT_BASE                                (0x42A80000u)
33468   /** Peripheral ECAT base pointer */
33469   #define ECAT                                     ((ECAT_Type *)ECAT_BASE)
33470   /** Array initializer of ECAT peripheral base addresses */
33471   #define ECAT_BASE_ADDRS                          { ECAT_BASE }
33472   /** Array initializer of ECAT peripheral base pointers */
33473   #define ECAT_BASE_PTRS                           { ECAT }
33474 #endif
33475 
33476 /*!
33477  * @}
33478  */ /* end of group ECAT_Peripheral_Access_Layer */
33479 
33480 
33481 /* ----------------------------------------------------------------------------
33482    -- EIM Peripheral Access Layer
33483    ---------------------------------------------------------------------------- */
33484 
33485 /*!
33486  * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
33487  * @{
33488  */
33489 
33490 /** EIM - Register Layout Typedef */
33491 typedef struct {
33492   __IO uint32_t EIMCR;                             /**< Error Injection Module Configuration Register, offset: 0x0 */
33493   __IO uint32_t EICHEN;                            /**< Error Injection Channel Enable register, offset: 0x4 */
33494        uint8_t RESERVED_0[248];
33495   __IO uint32_t EICHD0_WORD0;                      /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */
33496   __IO uint32_t EICHD0_WORD1;                      /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */
33497   __IO uint32_t EICHD0_WORD2;                      /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */
33498        uint8_t RESERVED_1[52];
33499   __IO uint32_t EICHD1_WORD0;                      /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */
33500   __IO uint32_t EICHD1_WORD1;                      /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */
33501   __IO uint32_t EICHD1_WORD2;                      /**< Error Injection Channel Descriptor 1, Word2, offset: 0x148 */
33502   __IO uint32_t EICHD1_WORD3;                      /**< Error Injection Channel Descriptor 1, Word3, offset: 0x14C */
33503   __IO uint32_t EICHD1_WORD4;                      /**< Error Injection Channel Descriptor 1, Word4, offset: 0x150 */
33504        uint8_t RESERVED_2[44];
33505   __IO uint32_t EICHD2_WORD0;                      /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */
33506   __IO uint32_t EICHD2_WORD1;                      /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */
33507   __IO uint32_t EICHD2_WORD2;                      /**< Error Injection Channel Descriptor 2, Word2, offset: 0x188 */
33508   __IO uint32_t EICHD2_WORD3;                      /**< Error Injection Channel Descriptor 2, Word3, offset: 0x18C */
33509   __IO uint32_t EICHD2_WORD4;                      /**< Error Injection Channel Descriptor 2, Word4, offset: 0x190 */
33510        uint8_t RESERVED_3[44];
33511   __IO uint32_t EICHD3_WORD0;                      /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */
33512   __IO uint32_t EICHD3_WORD1;                      /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */
33513   __IO uint32_t EICHD3_WORD2;                      /**< Error Injection Channel Descriptor 3, Word2, offset: 0x1C8 */
33514   __IO uint32_t EICHD3_WORD3;                      /**< Error Injection Channel Descriptor 3, Word3, offset: 0x1CC */
33515   __IO uint32_t EICHD3_WORD4;                      /**< Error Injection Channel Descriptor 3, Word4, offset: 0x1D0 */
33516        uint8_t RESERVED_4[44];
33517   __IO uint32_t EICHD4_WORD0;                      /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */
33518   __IO uint32_t EICHD4_WORD1;                      /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */
33519   __IO uint32_t EICHD4_WORD2;                      /**< Error Injection Channel Descriptor 4, Word2, offset: 0x208 */
33520   __IO uint32_t EICHD4_WORD3;                      /**< Error Injection Channel Descriptor 4, Word3, offset: 0x20C */
33521   __IO uint32_t EICHD4_WORD4;                      /**< Error Injection Channel Descriptor 4, Word4, offset: 0x210 */
33522 } EIM_Type;
33523 
33524 /* ----------------------------------------------------------------------------
33525    -- EIM Register Masks
33526    ---------------------------------------------------------------------------- */
33527 
33528 /*!
33529  * @addtogroup EIM_Register_Masks EIM Register Masks
33530  * @{
33531  */
33532 
33533 /*! @name EIMCR - Error Injection Module Configuration Register */
33534 /*! @{ */
33535 
33536 #define EIM_EIMCR_GEIEN_MASK                     (0x1U)
33537 #define EIM_EIMCR_GEIEN_SHIFT                    (0U)
33538 /*! GEIEN - Global Error Injection Enable
33539  *  0b0..Disabled
33540  *  0b1..Enabled
33541  */
33542 #define EIM_EIMCR_GEIEN(x)                       (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK)
33543 /*! @} */
33544 
33545 /*! @name EICHEN - Error Injection Channel Enable register */
33546 /*! @{ */
33547 
33548 #define EIM_EICHEN_EICH4EN_MASK                  (0x8000000U)
33549 #define EIM_EICHEN_EICH4EN_SHIFT                 (27U)
33550 /*! EICH4EN - Error Injection Channel 4 Enable
33551  *  0b0..Error injection is disabled on Error Injection Channel 4
33552  *  0b1..Error injection is enabled on Error Injection Channel 4
33553  */
33554 #define EIM_EICHEN_EICH4EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK)
33555 
33556 #define EIM_EICHEN_EICH3EN_MASK                  (0x10000000U)
33557 #define EIM_EICHEN_EICH3EN_SHIFT                 (28U)
33558 /*! EICH3EN - Error Injection Channel 3 Enable
33559  *  0b0..Error injection is disabled on Error Injection Channel 3
33560  *  0b1..Error injection is enabled on Error Injection Channel 3
33561  */
33562 #define EIM_EICHEN_EICH3EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK)
33563 
33564 #define EIM_EICHEN_EICH2EN_MASK                  (0x20000000U)
33565 #define EIM_EICHEN_EICH2EN_SHIFT                 (29U)
33566 /*! EICH2EN - Error Injection Channel 2 Enable
33567  *  0b0..Error injection is disabled on Error Injection Channel 2
33568  *  0b1..Error injection is enabled on Error Injection Channel 2
33569  */
33570 #define EIM_EICHEN_EICH2EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK)
33571 
33572 #define EIM_EICHEN_EICH1EN_MASK                  (0x40000000U)
33573 #define EIM_EICHEN_EICH1EN_SHIFT                 (30U)
33574 /*! EICH1EN - Error Injection Channel 1 Enable
33575  *  0b0..Error injection is disabled on Error Injection Channel 1
33576  *  0b1..Error injection is enabled on Error Injection Channel 1
33577  */
33578 #define EIM_EICHEN_EICH1EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK)
33579 
33580 #define EIM_EICHEN_EICH0EN_MASK                  (0x80000000U)
33581 #define EIM_EICHEN_EICH0EN_SHIFT                 (31U)
33582 /*! EICH0EN - Error Injection Channel 0 Enable
33583  *  0b0..Error injection is disabled on Error Injection Channel 0
33584  *  0b1..Error injection is enabled on Error Injection Channel 0
33585  */
33586 #define EIM_EICHEN_EICH0EN(x)                    (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK)
33587 /*! @} */
33588 
33589 /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */
33590 /*! @{ */
33591 
33592 #define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK        (0xFFFC0000U)
33593 #define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT       (18U)
33594 /*! CHKBIT_MASK - Checkbit Mask */
33595 #define EIM_EICHD0_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK)
33596 /*! @} */
33597 
33598 /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */
33599 /*! @{ */
33600 
33601 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK      (0xFFFU)
33602 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT     (0U)
33603 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
33604 #define EIM_EICHD0_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK)
33605 /*! @} */
33606 
33607 /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */
33608 /*! @{ */
33609 
33610 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK      (0xFFFFFFFFU)
33611 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT     (0U)
33612 /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */
33613 #define EIM_EICHD0_WORD2_B4_7DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK)
33614 /*! @} */
33615 
33616 /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */
33617 /*! @{ */
33618 
33619 #define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK        (0xFFFF0000U)
33620 #define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT       (16U)
33621 /*! CHKBIT_MASK - Checkbit Mask */
33622 #define EIM_EICHD1_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK)
33623 /*! @} */
33624 
33625 /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */
33626 /*! @{ */
33627 
33628 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
33629 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT     (0U)
33630 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
33631 #define EIM_EICHD1_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK)
33632 /*! @} */
33633 
33634 /*! @name EICHD1_WORD2 - Error Injection Channel Descriptor 1, Word2 */
33635 /*! @{ */
33636 
33637 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK      (0xFFFFFFFFU)
33638 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT     (0U)
33639 /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */
33640 #define EIM_EICHD1_WORD2_B4_7DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK)
33641 /*! @} */
33642 
33643 /*! @name EICHD1_WORD3 - Error Injection Channel Descriptor 1, Word3 */
33644 /*! @{ */
33645 
33646 #define EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK     (0xFFFFFFFFU)
33647 #define EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT    (0U)
33648 /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */
33649 #define EIM_EICHD1_WORD3_B8_11DATA_MASK(x)       (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK)
33650 /*! @} */
33651 
33652 /*! @name EICHD1_WORD4 - Error Injection Channel Descriptor 1, Word4 */
33653 /*! @{ */
33654 
33655 #define EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK    (0xFFFFFFFFU)
33656 #define EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT   (0U)
33657 /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */
33658 #define EIM_EICHD1_WORD4_B12_15DATA_MASK(x)      (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK)
33659 /*! @} */
33660 
33661 /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */
33662 /*! @{ */
33663 
33664 #define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK        (0xFFFFFFF0U)
33665 #define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT       (4U)
33666 /*! CHKBIT_MASK - Checkbit Mask */
33667 #define EIM_EICHD2_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK)
33668 /*! @} */
33669 
33670 /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */
33671 /*! @{ */
33672 
33673 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK      (0xFFU)
33674 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT     (0U)
33675 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
33676 #define EIM_EICHD2_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK)
33677 /*! @} */
33678 
33679 /*! @name EICHD2_WORD2 - Error Injection Channel Descriptor 2, Word2 */
33680 /*! @{ */
33681 
33682 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK      (0xFFFFFFFFU)
33683 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT     (0U)
33684 /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */
33685 #define EIM_EICHD2_WORD2_B4_7DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK)
33686 /*! @} */
33687 
33688 /*! @name EICHD2_WORD3 - Error Injection Channel Descriptor 2, Word3 */
33689 /*! @{ */
33690 
33691 #define EIM_EICHD2_WORD3_B8_11DATA_MASK_MASK     (0xFFFFFFFFU)
33692 #define EIM_EICHD2_WORD3_B8_11DATA_MASK_SHIFT    (0U)
33693 /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */
33694 #define EIM_EICHD2_WORD3_B8_11DATA_MASK(x)       (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD2_WORD3_B8_11DATA_MASK_MASK)
33695 /*! @} */
33696 
33697 /*! @name EICHD2_WORD4 - Error Injection Channel Descriptor 2, Word4 */
33698 /*! @{ */
33699 
33700 #define EIM_EICHD2_WORD4_B12_15DATA_MASK_MASK    (0xFFFFFFFFU)
33701 #define EIM_EICHD2_WORD4_B12_15DATA_MASK_SHIFT   (0U)
33702 /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */
33703 #define EIM_EICHD2_WORD4_B12_15DATA_MASK(x)      (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD2_WORD4_B12_15DATA_MASK_MASK)
33704 /*! @} */
33705 
33706 /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */
33707 /*! @{ */
33708 
33709 #define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK        (0xFFFFFFF0U)
33710 #define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT       (4U)
33711 /*! CHKBIT_MASK - Checkbit Mask */
33712 #define EIM_EICHD3_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK)
33713 /*! @} */
33714 
33715 /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */
33716 /*! @{ */
33717 
33718 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
33719 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT     (0U)
33720 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
33721 #define EIM_EICHD3_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK)
33722 /*! @} */
33723 
33724 /*! @name EICHD3_WORD2 - Error Injection Channel Descriptor 3, Word2 */
33725 /*! @{ */
33726 
33727 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK      (0xFFFFFFFFU)
33728 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT     (0U)
33729 /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */
33730 #define EIM_EICHD3_WORD2_B4_7DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK)
33731 /*! @} */
33732 
33733 /*! @name EICHD3_WORD3 - Error Injection Channel Descriptor 3, Word3 */
33734 /*! @{ */
33735 
33736 #define EIM_EICHD3_WORD3_B8_11DATA_MASK_MASK     (0xFFFFFFFFU)
33737 #define EIM_EICHD3_WORD3_B8_11DATA_MASK_SHIFT    (0U)
33738 /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */
33739 #define EIM_EICHD3_WORD3_B8_11DATA_MASK(x)       (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD3_WORD3_B8_11DATA_MASK_MASK)
33740 /*! @} */
33741 
33742 /*! @name EICHD3_WORD4 - Error Injection Channel Descriptor 3, Word4 */
33743 /*! @{ */
33744 
33745 #define EIM_EICHD3_WORD4_B12_15DATA_MASK_MASK    (0xFFFFFFFFU)
33746 #define EIM_EICHD3_WORD4_B12_15DATA_MASK_SHIFT   (0U)
33747 /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */
33748 #define EIM_EICHD3_WORD4_B12_15DATA_MASK(x)      (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD3_WORD4_B12_15DATA_MASK_MASK)
33749 /*! @} */
33750 
33751 /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */
33752 /*! @{ */
33753 
33754 #define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK        (0xFFFFFFF0U)
33755 #define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT       (4U)
33756 /*! CHKBIT_MASK - Checkbit Mask */
33757 #define EIM_EICHD4_WORD0_CHKBIT_MASK(x)          (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK)
33758 /*! @} */
33759 
33760 /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */
33761 /*! @{ */
33762 
33763 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK      (0xFFFFFFFFU)
33764 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT     (0U)
33765 /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */
33766 #define EIM_EICHD4_WORD1_B0_3DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK)
33767 /*! @} */
33768 
33769 /*! @name EICHD4_WORD2 - Error Injection Channel Descriptor 4, Word2 */
33770 /*! @{ */
33771 
33772 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK      (0xFFFFFFFFU)
33773 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT     (0U)
33774 /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */
33775 #define EIM_EICHD4_WORD2_B4_7DATA_MASK(x)        (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK)
33776 /*! @} */
33777 
33778 /*! @name EICHD4_WORD3 - Error Injection Channel Descriptor 4, Word3 */
33779 /*! @{ */
33780 
33781 #define EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK     (0xFFFFFFFFU)
33782 #define EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT    (0U)
33783 /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */
33784 #define EIM_EICHD4_WORD3_B8_11DATA_MASK(x)       (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK)
33785 /*! @} */
33786 
33787 /*! @name EICHD4_WORD4 - Error Injection Channel Descriptor 4, Word4 */
33788 /*! @{ */
33789 
33790 #define EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK    (0xFFFFFFFFU)
33791 #define EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT   (0U)
33792 /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */
33793 #define EIM_EICHD4_WORD4_B12_15DATA_MASK(x)      (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK)
33794 /*! @} */
33795 
33796 
33797 /*!
33798  * @}
33799  */ /* end of group EIM_Register_Masks */
33800 
33801 
33802 /* EIM - Peripheral instance base addresses */
33803 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
33804   /** Peripheral EIM base address */
33805   #define EIM_BASE                                 (0x5B860000u)
33806   /** Peripheral EIM base address */
33807   #define EIM_BASE_NS                              (0x4B860000u)
33808   /** Peripheral EIM base pointer */
33809   #define EIM                                      ((EIM_Type *)EIM_BASE)
33810   /** Peripheral EIM base pointer */
33811   #define EIM_NS                                   ((EIM_Type *)EIM_BASE_NS)
33812   /** Array initializer of EIM peripheral base addresses */
33813   #define EIM_BASE_ADDRS                           { EIM_BASE }
33814   /** Array initializer of EIM peripheral base pointers */
33815   #define EIM_BASE_PTRS                            { EIM }
33816   /** Array initializer of EIM peripheral base addresses */
33817   #define EIM_BASE_ADDRS_NS                        { EIM_BASE_NS }
33818   /** Array initializer of EIM peripheral base pointers */
33819   #define EIM_BASE_PTRS_NS                         { EIM_NS }
33820 #else
33821   /** Peripheral EIM base address */
33822   #define EIM_BASE                                 (0x4B860000u)
33823   /** Peripheral EIM base pointer */
33824   #define EIM                                      ((EIM_Type *)EIM_BASE)
33825   /** Array initializer of EIM peripheral base addresses */
33826   #define EIM_BASE_ADDRS                           { EIM_BASE }
33827   /** Array initializer of EIM peripheral base pointers */
33828   #define EIM_BASE_PTRS                            { EIM }
33829 #endif
33830 
33831 /*!
33832  * @}
33833  */ /* end of group EIM_Peripheral_Access_Layer */
33834 
33835 
33836 /* ----------------------------------------------------------------------------
33837    -- ENETC_GLOBAL Peripheral Access Layer
33838    ---------------------------------------------------------------------------- */
33839 
33840 /*!
33841  * @addtogroup ENETC_GLOBAL_Peripheral_Access_Layer ENETC_GLOBAL Peripheral Access Layer
33842  * @{
33843  */
33844 
33845 /** ENETC_GLOBAL - Register Layout Typedef */
33846 typedef struct {
33847   __I  uint32_t SMCAPR;                            /**< Shared memory capability register, offset: 0x0 */
33848   __I  uint32_t SMDTR;                             /**< Shared memory depletion threshold register, offset: 0x4 */
33849   __I  uint32_t SMACR;                             /**< Shared memory available count register, offset: 0x8 */
33850        uint8_t RESERVED_0[4];
33851   __I  uint32_t SMCLWMR;                           /**< Shared memory count low watermark register, offset: 0x10 */
33852   __I  uint32_t SMBUCR;                            /**< Shared memory buffer unassigned count register, offset: 0x14 */
33853   __I  uint32_t SMBUCHWMR;                         /**< Shared memory buffer unassigned count high watermark register, offset: 0x18 */
33854   __I  uint32_t SMLCR;                             /**< Shared memory loss count register, offset: 0x1C */
33855   __I  uint32_t HBTCAPR;                           /**< Hash bucket table capability register, offset: 0x20 */
33856   __I  uint32_t HBTOR0;                            /**< Hash bucket table operational register 0, offset: 0x24 */
33857        uint8_t RESERVED_1[4];
33858   __I  uint32_t HBTOR2;                            /**< Hash bucket table operational register 2, offset: 0x2C */
33859        uint8_t RESERVED_2[16];
33860   __I  uint32_t SMERBCAPR;                         /**< Shared memory ENETC receive buffer capability register, offset: 0x40 */
33861   __I  uint32_t SMERBOR0;                          /**< Shared memory ENETC receive buffer operational register 0, offset: 0x44 */
33862   __I  uint32_t SMERBOR1;                          /**< Shared memory ENETC receive buffer operational 1, offset: 0x48 */
33863        uint8_t RESERVED_3[180];
33864   struct {                                         /* offset: 0x100, array step: 0x8 */
33865     __I  uint32_t PCEOR;                             /**< PCE 0 operational register, array offset: 0x100, array step: 0x8 */
33866     __I  uint32_t RFEOR;                             /**< Replication Forwarding Engine 0 operational register, array offset: 0x104, array step: 0x8 */
33867   } PCE_SL[1];
33868        uint8_t RESERVED_4[92];
33869   __I  uint32_t NETCCLKR;                          /**< NETC clock register, offset: 0x164 */
33870        uint8_t RESERVED_5[152];
33871   struct {                                         /* offset: 0x200, array step: 0x28 */
33872     __I  uint32_t HTACAPR;                           /**< HTA 0 capability register, array offset: 0x200, array step: 0x28 */
33873     __I  uint32_t HTARFCOR;                          /**< HTA 0 receive frame count operational register, array offset: 0x204, array step: 0x28 */
33874     __I  uint32_t HTAHPBCOR;                         /**< HTA 0 high priority byte count operational register, array offset: 0x208, array step: 0x28 */
33875     __I  uint32_t HTALPBCOR;                         /**< HTA 0 low priority byte count operational register, array offset: 0x20C, array step: 0x28 */
33876          uint8_t RESERVED_0[20];
33877     __I  uint32_t HTATFCOR;                          /**< HTA 0 transmit frame count operational register, array offset: 0x224, array step: 0x28 */
33878   } HTA_LOOP[1];
33879        uint8_t RESERVED_6[216];
33880   struct {                                         /* offset: 0x300, array step: 0x10 */
33881     __IO uint32_t RCSBRLAR;                          /**< Root complex 0 system bus read latency average register, array offset: 0x300, array step: 0x10 */
33882     __I  uint32_t RCSBRLHWMR;                        /**< Root complex 0 system bus read latency high watermark register, array offset: 0x304, array step: 0x10 */
33883     __IO uint32_t RCSBWLAR;                          /**< Root complex 0 system bus write latency average register, array offset: 0x308, array step: 0x10 */
33884     __I  uint32_t RCSBWLHWMR;                        /**< Root complex 0 system bus write latency high watermark register, array offset: 0x30C, array step: 0x10 */
33885   } ARRAY_NUM_RC[1];
33886        uint8_t RESERVED_7[2280];
33887   __I  uint32_t IPBRR0;                            /**< IP block revision register 0, offset: 0xBF8 */
33888   __I  uint32_t IPBRR1;                            /**< IP block revision register 1, offset: 0xBFC */
33889        uint8_t RESERVED_8[256];
33890   __I  uint32_t FBLPR[2];                          /**< Function boot loader parameter register 0..Function boot loader parameter register 1, array offset: 0xD00, array step: 0x4 */
33891        uint8_t RESERVED_9[280];
33892   union {                                          /* offset: 0xE20 */
33893     struct {                                         /* offset: 0xE20 */
33894       __IO uint32_t EMDIOUFSBECR;                      /**< EMDIO uncorrectable fatal system bus error configuration register, offset: 0xE20, available only on: EMDIO_GLOBAL (missing on ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL, TMR0_GLOBAL) */
33895       __IO uint32_t EMDIOUFSBESR;                      /**< EMDIO uncorrectable fatal system bus error status register, offset: 0xE24, available only on: EMDIO_GLOBAL (missing on ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL, TMR0_GLOBAL) */
33896     } EMDIO;
33897     struct {                                         /* offset: 0xE20 */
33898       __IO uint32_t TUFSBECR;                          /**< Timer uncorrectable fatal system bus error configuration register, offset: 0xE20, available only on: TMR0_GLOBAL (missing on EMDIO_GLOBAL, ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL) */
33899       __IO uint32_t TUFSBESR;                          /**< Timer uncorrectable fatal system bus error status register, offset: 0xE24, available only on: TMR0_GLOBAL (missing on EMDIO_GLOBAL, ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL) */
33900     } TIMER;
33901   };
33902 } ENETC_GLOBAL_Type;
33903 
33904 /* ----------------------------------------------------------------------------
33905    -- ENETC_GLOBAL Register Masks
33906    ---------------------------------------------------------------------------- */
33907 
33908 /*!
33909  * @addtogroup ENETC_GLOBAL_Register_Masks ENETC_GLOBAL Register Masks
33910  * @{
33911  */
33912 
33913 /*! @name SMCAPR - Shared memory capability register */
33914 /*! @{ */
33915 
33916 #define ENETC_GLOBAL_SMCAPR_NUM_WORDS_MASK       (0xFFFFFFU)
33917 #define ENETC_GLOBAL_SMCAPR_NUM_WORDS_SHIFT      (0U)
33918 #define ENETC_GLOBAL_SMCAPR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMCAPR_NUM_WORDS_SHIFT)) & ENETC_GLOBAL_SMCAPR_NUM_WORDS_MASK)
33919 /*! @} */
33920 
33921 /*! @name SMDTR - Shared memory depletion threshold register */
33922 /*! @{ */
33923 
33924 #define ENETC_GLOBAL_SMDTR_THRESH_MASK           (0xFFFFFFU)
33925 #define ENETC_GLOBAL_SMDTR_THRESH_SHIFT          (0U)
33926 #define ENETC_GLOBAL_SMDTR_THRESH(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMDTR_THRESH_SHIFT)) & ENETC_GLOBAL_SMDTR_THRESH_MASK)
33927 /*! @} */
33928 
33929 /*! @name SMACR - Shared memory available count register */
33930 /*! @{ */
33931 
33932 #define ENETC_GLOBAL_SMACR_COUNT_MASK            (0xFFFFFFU)
33933 #define ENETC_GLOBAL_SMACR_COUNT_SHIFT           (0U)
33934 #define ENETC_GLOBAL_SMACR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMACR_COUNT_SHIFT)) & ENETC_GLOBAL_SMACR_COUNT_MASK)
33935 /*! @} */
33936 
33937 /*! @name SMCLWMR - Shared memory count low watermark register */
33938 /*! @{ */
33939 
33940 #define ENETC_GLOBAL_SMCLWMR_WATERMARK_MASK      (0xFFFFFFU)
33941 #define ENETC_GLOBAL_SMCLWMR_WATERMARK_SHIFT     (0U)
33942 #define ENETC_GLOBAL_SMCLWMR_WATERMARK(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMCLWMR_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMCLWMR_WATERMARK_MASK)
33943 /*! @} */
33944 
33945 /*! @name SMBUCR - Shared memory buffer unassigned count register */
33946 /*! @{ */
33947 
33948 #define ENETC_GLOBAL_SMBUCR_COUNT_MASK           (0xFFFFFFU)
33949 #define ENETC_GLOBAL_SMBUCR_COUNT_SHIFT          (0U)
33950 #define ENETC_GLOBAL_SMBUCR_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMBUCR_COUNT_SHIFT)) & ENETC_GLOBAL_SMBUCR_COUNT_MASK)
33951 /*! @} */
33952 
33953 /*! @name SMBUCHWMR - Shared memory buffer unassigned count high watermark register */
33954 /*! @{ */
33955 
33956 #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK_MASK    (0xFFFFFFU)
33957 #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT   (0U)
33958 #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMBUCHWMR_WATERMARK_MASK)
33959 /*! @} */
33960 
33961 /*! @name SMLCR - Shared memory loss count register */
33962 /*! @{ */
33963 
33964 #define ENETC_GLOBAL_SMLCR_COUNT_MASK            (0xFFFFFFU)
33965 #define ENETC_GLOBAL_SMLCR_COUNT_SHIFT           (0U)
33966 #define ENETC_GLOBAL_SMLCR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_COUNT_SHIFT)) & ENETC_GLOBAL_SMLCR_COUNT_MASK)
33967 
33968 #define ENETC_GLOBAL_SMLCR_IFLC_MASK             (0x40000000U)
33969 #define ENETC_GLOBAL_SMLCR_IFLC_SHIFT            (30U)
33970 #define ENETC_GLOBAL_SMLCR_IFLC(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_IFLC_SHIFT)) & ENETC_GLOBAL_SMLCR_IFLC_MASK)
33971 
33972 #define ENETC_GLOBAL_SMLCR_IFDC_MASK             (0x80000000U)
33973 #define ENETC_GLOBAL_SMLCR_IFDC_SHIFT            (31U)
33974 #define ENETC_GLOBAL_SMLCR_IFDC(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_IFDC_SHIFT)) & ENETC_GLOBAL_SMLCR_IFDC_MASK)
33975 /*! @} */
33976 
33977 /*! @name HBTCAPR - Hash bucket table capability register */
33978 /*! @{ */
33979 
33980 #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK    (0xFFFFU)
33981 #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT   (0U)
33982 #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK)
33983 
33984 #define ENETC_GLOBAL_HBTCAPR_MAX_COL_MASK        (0x7000000U)
33985 #define ENETC_GLOBAL_HBTCAPR_MAX_COL_SHIFT       (24U)
33986 #define ENETC_GLOBAL_HBTCAPR_MAX_COL(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_MAX_COL_SHIFT)) & ENETC_GLOBAL_HBTCAPR_MAX_COL_MASK)
33987 
33988 #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS_MASK     (0xF0000000U)
33989 #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT    (28U)
33990 #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT)) & ENETC_GLOBAL_HBTCAPR_MAX_VISITS_MASK)
33991 /*! @} */
33992 
33993 /*! @name HBTOR0 - Hash bucket table operational register 0 */
33994 /*! @{ */
33995 
33996 #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_MASK     (0xFFFFU)
33997 #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT    (0U)
33998 #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_MASK)
33999 
34000 #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_MASK     (0xFFFF0000U)
34001 #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT    (16U)
34002 #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_MASK)
34003 /*! @} */
34004 
34005 /*! @name HBTOR2 - Hash bucket table operational register 2 */
34006 /*! @{ */
34007 
34008 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK   (0xFFU)
34009 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT  (0U)
34010 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT)) & ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK)
34011 
34012 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_MASK     (0xFF00U)
34013 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT    (8U)
34014 #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT)) & ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_MASK)
34015 
34016 #define ENETC_GLOBAL_HBTOR2_HWM_COL_MASK         (0xF0000U)
34017 #define ENETC_GLOBAL_HBTOR2_HWM_COL_SHIFT        (16U)
34018 #define ENETC_GLOBAL_HBTOR2_HWM_COL(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_HWM_COL_SHIFT)) & ENETC_GLOBAL_HBTOR2_HWM_COL_MASK)
34019 /*! @} */
34020 
34021 /*! @name SMERBCAPR - Shared memory ENETC receive buffer capability register */
34022 /*! @{ */
34023 
34024 #define ENETC_GLOBAL_SMERBCAPR_THRESH_MASK       (0xFFFFFFU)
34025 #define ENETC_GLOBAL_SMERBCAPR_THRESH_SHIFT      (0U)
34026 #define ENETC_GLOBAL_SMERBCAPR_THRESH(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_THRESH_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_THRESH_MASK)
34027 
34028 #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_MASK    (0x30000000U)
34029 #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT   (28U)
34030 #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_MASK)
34031 
34032 #define ENETC_GLOBAL_SMERBCAPR_MLOC_MASK         (0xC0000000U)
34033 #define ENETC_GLOBAL_SMERBCAPR_MLOC_SHIFT        (30U)
34034 #define ENETC_GLOBAL_SMERBCAPR_MLOC(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_MLOC_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_MLOC_MASK)
34035 /*! @} */
34036 
34037 /*! @name SMERBOR0 - Shared memory ENETC receive buffer operational register 0 */
34038 /*! @{ */
34039 
34040 #define ENETC_GLOBAL_SMERBOR0_AMOUNT_MASK        (0xFFFFFFU)
34041 #define ENETC_GLOBAL_SMERBOR0_AMOUNT_SHIFT       (0U)
34042 #define ENETC_GLOBAL_SMERBOR0_AMOUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBOR0_AMOUNT_SHIFT)) & ENETC_GLOBAL_SMERBOR0_AMOUNT_MASK)
34043 /*! @} */
34044 
34045 /*! @name SMERBOR1 - Shared memory ENETC receive buffer operational 1 */
34046 /*! @{ */
34047 
34048 #define ENETC_GLOBAL_SMERBOR1_WATERMARK_MASK     (0xFFFFFFU)
34049 #define ENETC_GLOBAL_SMERBOR1_WATERMARK_SHIFT    (0U)
34050 #define ENETC_GLOBAL_SMERBOR1_WATERMARK(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBOR1_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMERBOR1_WATERMARK_MASK)
34051 /*! @} */
34052 
34053 /*! @name PCEOR - PCE 0 operational register */
34054 /*! @{ */
34055 
34056 #define ENETC_GLOBAL_PCEOR_NUM_FRAMES_MASK       (0x3FU)
34057 #define ENETC_GLOBAL_PCEOR_NUM_FRAMES_SHIFT      (0U)
34058 #define ENETC_GLOBAL_PCEOR_NUM_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_NUM_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_NUM_FRAMES_MASK)
34059 
34060 #define ENETC_GLOBAL_PCEOR_HWM_FRAMES_MASK       (0x3F00U)
34061 #define ENETC_GLOBAL_PCEOR_HWM_FRAMES_SHIFT      (8U)
34062 #define ENETC_GLOBAL_PCEOR_HWM_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_HWM_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_HWM_FRAMES_MASK)
34063 
34064 #define ENETC_GLOBAL_PCEOR_MAX_FRAMES_MASK       (0x3F0000U)
34065 #define ENETC_GLOBAL_PCEOR_MAX_FRAMES_SHIFT      (16U)
34066 #define ENETC_GLOBAL_PCEOR_MAX_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_MAX_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_MAX_FRAMES_MASK)
34067 /*! @} */
34068 
34069 /* The count of ENETC_GLOBAL_PCEOR */
34070 #define ENETC_GLOBAL_PCEOR_COUNT                 (1U)
34071 
34072 /*! @name RFEOR - Replication Forwarding Engine 0 operational register */
34073 /*! @{ */
34074 
34075 #define ENETC_GLOBAL_RFEOR_NUM_FRAMES_MASK       (0x3FU)
34076 #define ENETC_GLOBAL_RFEOR_NUM_FRAMES_SHIFT      (0U)
34077 #define ENETC_GLOBAL_RFEOR_NUM_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_NUM_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_NUM_FRAMES_MASK)
34078 
34079 #define ENETC_GLOBAL_RFEOR_HWM_FRAMES_MASK       (0x3F00U)
34080 #define ENETC_GLOBAL_RFEOR_HWM_FRAMES_SHIFT      (8U)
34081 #define ENETC_GLOBAL_RFEOR_HWM_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_HWM_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_HWM_FRAMES_MASK)
34082 
34083 #define ENETC_GLOBAL_RFEOR_MAX_FRAMES_MASK       (0x3F0000U)
34084 #define ENETC_GLOBAL_RFEOR_MAX_FRAMES_SHIFT      (16U)
34085 #define ENETC_GLOBAL_RFEOR_MAX_FRAMES(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_MAX_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_MAX_FRAMES_MASK)
34086 /*! @} */
34087 
34088 /* The count of ENETC_GLOBAL_RFEOR */
34089 #define ENETC_GLOBAL_RFEOR_COUNT                 (1U)
34090 
34091 /*! @name NETCCLKR - NETC clock register */
34092 /*! @{ */
34093 
34094 #define ENETC_GLOBAL_NETCCLKR_FREQ_MASK          (0x7FFU)
34095 #define ENETC_GLOBAL_NETCCLKR_FREQ_SHIFT         (0U)
34096 /*! FREQ - Frequency */
34097 #define ENETC_GLOBAL_NETCCLKR_FREQ(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_NETCCLKR_FREQ_SHIFT)) & ENETC_GLOBAL_NETCCLKR_FREQ_MASK)
34098 /*! @} */
34099 
34100 /*! @name HTACAPR - HTA 0 capability register */
34101 /*! @{ */
34102 
34103 #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK  (0xFFU)
34104 #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT (0U)
34105 #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT)) & ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK)
34106 
34107 #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK  (0xFF00U)
34108 #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT (8U)
34109 #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT)) & ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK)
34110 /*! @} */
34111 
34112 /* The count of ENETC_GLOBAL_HTACAPR */
34113 #define ENETC_GLOBAL_HTACAPR_COUNT               (1U)
34114 
34115 /*! @name HTARFCOR - HTA 0 receive frame count operational register */
34116 /*! @{ */
34117 
34118 #define ENETC_GLOBAL_HTARFCOR_HP_COUNT_MASK      (0xFFU)
34119 #define ENETC_GLOBAL_HTARFCOR_HP_COUNT_SHIFT     (0U)
34120 #define ENETC_GLOBAL_HTARFCOR_HP_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTARFCOR_HP_COUNT_MASK)
34121 
34122 #define ENETC_GLOBAL_HTARFCOR_HP_HWM_MASK        (0xFF00U)
34123 #define ENETC_GLOBAL_HTARFCOR_HP_HWM_SHIFT       (8U)
34124 #define ENETC_GLOBAL_HTARFCOR_HP_HWM(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_HP_HWM_SHIFT)) & ENETC_GLOBAL_HTARFCOR_HP_HWM_MASK)
34125 
34126 #define ENETC_GLOBAL_HTARFCOR_LP_COUNT_MASK      (0xFF0000U)
34127 #define ENETC_GLOBAL_HTARFCOR_LP_COUNT_SHIFT     (16U)
34128 #define ENETC_GLOBAL_HTARFCOR_LP_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTARFCOR_LP_COUNT_MASK)
34129 
34130 #define ENETC_GLOBAL_HTARFCOR_LP_HWM_MASK        (0xFF000000U)
34131 #define ENETC_GLOBAL_HTARFCOR_LP_HWM_SHIFT       (24U)
34132 #define ENETC_GLOBAL_HTARFCOR_LP_HWM(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_LP_HWM_SHIFT)) & ENETC_GLOBAL_HTARFCOR_LP_HWM_MASK)
34133 /*! @} */
34134 
34135 /* The count of ENETC_GLOBAL_HTARFCOR */
34136 #define ENETC_GLOBAL_HTARFCOR_COUNT              (1U)
34137 
34138 /*! @name HTAHPBCOR - HTA 0 high priority byte count operational register */
34139 /*! @{ */
34140 
34141 #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_MASK     (0xFFFFU)
34142 #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT    (0U)
34143 #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_MASK)
34144 
34145 #define ENETC_GLOBAL_HTAHPBCOR_HWM_MASK          (0xFFFF0000U)
34146 #define ENETC_GLOBAL_HTAHPBCOR_HWM_SHIFT         (16U)
34147 #define ENETC_GLOBAL_HTAHPBCOR_HWM(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTAHPBCOR_HWM_SHIFT)) & ENETC_GLOBAL_HTAHPBCOR_HWM_MASK)
34148 /*! @} */
34149 
34150 /* The count of ENETC_GLOBAL_HTAHPBCOR */
34151 #define ENETC_GLOBAL_HTAHPBCOR_COUNT             (1U)
34152 
34153 /*! @name HTALPBCOR - HTA 0 low priority byte count operational register */
34154 /*! @{ */
34155 
34156 #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT_MASK     (0xFFFFU)
34157 #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT    (0U)
34158 #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTALPBCOR_LP_COUNT_MASK)
34159 
34160 #define ENETC_GLOBAL_HTALPBCOR_HWM_MASK          (0xFFFF0000U)
34161 #define ENETC_GLOBAL_HTALPBCOR_HWM_SHIFT         (16U)
34162 #define ENETC_GLOBAL_HTALPBCOR_HWM(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTALPBCOR_HWM_SHIFT)) & ENETC_GLOBAL_HTALPBCOR_HWM_MASK)
34163 /*! @} */
34164 
34165 /* The count of ENETC_GLOBAL_HTALPBCOR */
34166 #define ENETC_GLOBAL_HTALPBCOR_COUNT             (1U)
34167 
34168 /*! @name HTATFCOR - HTA 0 transmit frame count operational register */
34169 /*! @{ */
34170 
34171 #define ENETC_GLOBAL_HTATFCOR_HP_COUNT_MASK      (0xFFU)
34172 #define ENETC_GLOBAL_HTATFCOR_HP_COUNT_SHIFT     (0U)
34173 #define ENETC_GLOBAL_HTATFCOR_HP_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTATFCOR_HP_COUNT_MASK)
34174 
34175 #define ENETC_GLOBAL_HTATFCOR_HP_HWM_MASK        (0xFF00U)
34176 #define ENETC_GLOBAL_HTATFCOR_HP_HWM_SHIFT       (8U)
34177 #define ENETC_GLOBAL_HTATFCOR_HP_HWM(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_HP_HWM_SHIFT)) & ENETC_GLOBAL_HTATFCOR_HP_HWM_MASK)
34178 
34179 #define ENETC_GLOBAL_HTATFCOR_LP_COUNT_MASK      (0xFF0000U)
34180 #define ENETC_GLOBAL_HTATFCOR_LP_COUNT_SHIFT     (16U)
34181 #define ENETC_GLOBAL_HTATFCOR_LP_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTATFCOR_LP_COUNT_MASK)
34182 
34183 #define ENETC_GLOBAL_HTATFCOR_LP_HWM_MASK        (0xFF000000U)
34184 #define ENETC_GLOBAL_HTATFCOR_LP_HWM_SHIFT       (24U)
34185 #define ENETC_GLOBAL_HTATFCOR_LP_HWM(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_LP_HWM_SHIFT)) & ENETC_GLOBAL_HTATFCOR_LP_HWM_MASK)
34186 /*! @} */
34187 
34188 /* The count of ENETC_GLOBAL_HTATFCOR */
34189 #define ENETC_GLOBAL_HTATFCOR_COUNT              (1U)
34190 
34191 /*! @name RCSBRLAR - Root complex 0 system bus read latency average register */
34192 /*! @{ */
34193 
34194 #define ENETC_GLOBAL_RCSBRLAR_FRACT_MASK         (0xFFU)
34195 #define ENETC_GLOBAL_RCSBRLAR_FRACT_SHIFT        (0U)
34196 #define ENETC_GLOBAL_RCSBRLAR_FRACT(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLAR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBRLAR_FRACT_MASK)
34197 
34198 #define ENETC_GLOBAL_RCSBRLAR_INT_MASK           (0xFFF00U)
34199 #define ENETC_GLOBAL_RCSBRLAR_INT_SHIFT          (8U)
34200 #define ENETC_GLOBAL_RCSBRLAR_INT(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLAR_INT_SHIFT)) & ENETC_GLOBAL_RCSBRLAR_INT_MASK)
34201 /*! @} */
34202 
34203 /* The count of ENETC_GLOBAL_RCSBRLAR */
34204 #define ENETC_GLOBAL_RCSBRLAR_COUNT              (1U)
34205 
34206 /*! @name RCSBRLHWMR - Root complex 0 system bus read latency high watermark register */
34207 /*! @{ */
34208 
34209 #define ENETC_GLOBAL_RCSBRLHWMR_FRACT_MASK       (0xFFU)
34210 #define ENETC_GLOBAL_RCSBRLHWMR_FRACT_SHIFT      (0U)
34211 #define ENETC_GLOBAL_RCSBRLHWMR_FRACT(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLHWMR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBRLHWMR_FRACT_MASK)
34212 
34213 #define ENETC_GLOBAL_RCSBRLHWMR_INT_MASK         (0xFFF00U)
34214 #define ENETC_GLOBAL_RCSBRLHWMR_INT_SHIFT        (8U)
34215 #define ENETC_GLOBAL_RCSBRLHWMR_INT(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLHWMR_INT_SHIFT)) & ENETC_GLOBAL_RCSBRLHWMR_INT_MASK)
34216 /*! @} */
34217 
34218 /* The count of ENETC_GLOBAL_RCSBRLHWMR */
34219 #define ENETC_GLOBAL_RCSBRLHWMR_COUNT            (1U)
34220 
34221 /*! @name RCSBWLAR - Root complex 0 system bus write latency average register */
34222 /*! @{ */
34223 
34224 #define ENETC_GLOBAL_RCSBWLAR_FRACT_MASK         (0xFFU)
34225 #define ENETC_GLOBAL_RCSBWLAR_FRACT_SHIFT        (0U)
34226 #define ENETC_GLOBAL_RCSBWLAR_FRACT(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLAR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBWLAR_FRACT_MASK)
34227 
34228 #define ENETC_GLOBAL_RCSBWLAR_INT_MASK           (0xFFF00U)
34229 #define ENETC_GLOBAL_RCSBWLAR_INT_SHIFT          (8U)
34230 #define ENETC_GLOBAL_RCSBWLAR_INT(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLAR_INT_SHIFT)) & ENETC_GLOBAL_RCSBWLAR_INT_MASK)
34231 /*! @} */
34232 
34233 /* The count of ENETC_GLOBAL_RCSBWLAR */
34234 #define ENETC_GLOBAL_RCSBWLAR_COUNT              (1U)
34235 
34236 /*! @name RCSBWLHWMR - Root complex 0 system bus write latency high watermark register */
34237 /*! @{ */
34238 
34239 #define ENETC_GLOBAL_RCSBWLHWMR_FRACT_MASK       (0xFFU)
34240 #define ENETC_GLOBAL_RCSBWLHWMR_FRACT_SHIFT      (0U)
34241 #define ENETC_GLOBAL_RCSBWLHWMR_FRACT(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLHWMR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBWLHWMR_FRACT_MASK)
34242 
34243 #define ENETC_GLOBAL_RCSBWLHWMR_INT_MASK         (0xFFF00U)
34244 #define ENETC_GLOBAL_RCSBWLHWMR_INT_SHIFT        (8U)
34245 #define ENETC_GLOBAL_RCSBWLHWMR_INT(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLHWMR_INT_SHIFT)) & ENETC_GLOBAL_RCSBWLHWMR_INT_MASK)
34246 /*! @} */
34247 
34248 /* The count of ENETC_GLOBAL_RCSBWLHWMR */
34249 #define ENETC_GLOBAL_RCSBWLHWMR_COUNT            (1U)
34250 
34251 /*! @name IPBRR0 - IP block revision register 0 */
34252 /*! @{ */
34253 
34254 #define ENETC_GLOBAL_IPBRR0_IP_MN_MASK           (0xFFU)
34255 #define ENETC_GLOBAL_IPBRR0_IP_MN_SHIFT          (0U)
34256 #define ENETC_GLOBAL_IPBRR0_IP_MN(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR0_IP_MN_SHIFT)) & ENETC_GLOBAL_IPBRR0_IP_MN_MASK)
34257 
34258 #define ENETC_GLOBAL_IPBRR0_IP_MJ_MASK           (0xFF00U)
34259 #define ENETC_GLOBAL_IPBRR0_IP_MJ_SHIFT          (8U)
34260 #define ENETC_GLOBAL_IPBRR0_IP_MJ(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR0_IP_MJ_SHIFT)) & ENETC_GLOBAL_IPBRR0_IP_MJ_MASK)
34261 
34262 #define ENETC_GLOBAL_IPBRR0_IP_ID_MASK           (0xFFFF0000U)
34263 #define ENETC_GLOBAL_IPBRR0_IP_ID_SHIFT          (16U)
34264 #define ENETC_GLOBAL_IPBRR0_IP_ID(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR0_IP_ID_SHIFT)) & ENETC_GLOBAL_IPBRR0_IP_ID_MASK)
34265 /*! @} */
34266 
34267 /*! @name IPBRR1 - IP block revision register 1 */
34268 /*! @{ */
34269 
34270 #define ENETC_GLOBAL_IPBRR1_IP_CFG_MASK          (0xFFU)
34271 #define ENETC_GLOBAL_IPBRR1_IP_CFG_SHIFT         (0U)
34272 #define ENETC_GLOBAL_IPBRR1_IP_CFG(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_CFG_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_CFG_MASK)
34273 
34274 #define ENETC_GLOBAL_IPBRR1_IP_MNT_MASK          (0xFF00U)
34275 #define ENETC_GLOBAL_IPBRR1_IP_MNT_SHIFT         (8U)
34276 #define ENETC_GLOBAL_IPBRR1_IP_MNT(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_MNT_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_MNT_MASK)
34277 
34278 #define ENETC_GLOBAL_IPBRR1_IP_INT_MASK          (0xFF0000U)
34279 #define ENETC_GLOBAL_IPBRR1_IP_INT_SHIFT         (16U)
34280 #define ENETC_GLOBAL_IPBRR1_IP_INT(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_INT_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_INT_MASK)
34281 /*! @} */
34282 
34283 /*! @name FBLPR - Function boot loader parameter register 0..Function boot loader parameter register 1 */
34284 /*! @{ */
34285 
34286 #define ENETC_GLOBAL_FBLPR_PARAM_VAL_MASK        (0xFFFFFFFFU)
34287 #define ENETC_GLOBAL_FBLPR_PARAM_VAL_SHIFT       (0U)
34288 #define ENETC_GLOBAL_FBLPR_PARAM_VAL(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_FBLPR_PARAM_VAL_SHIFT)) & ENETC_GLOBAL_FBLPR_PARAM_VAL_MASK)
34289 /*! @} */
34290 
34291 /* The count of ENETC_GLOBAL_FBLPR */
34292 #define ENETC_GLOBAL_FBLPR_COUNT                 (2U)
34293 
34294 /*! @name EMDIOUFSBECR - EMDIO uncorrectable fatal system bus error configuration register */
34295 /*! @{ */
34296 
34297 #define ENETC_GLOBAL_EMDIOUFSBECR_RD_MASK        (0x80000000U)
34298 #define ENETC_GLOBAL_EMDIOUFSBECR_RD_SHIFT       (31U)
34299 /*! RD - Report disable */
34300 #define ENETC_GLOBAL_EMDIOUFSBECR_RD(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBECR_RD_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBECR_RD_MASK)
34301 /*! @} */
34302 
34303 /*! @name EMDIOUFSBESR - EMDIO uncorrectable fatal system bus error status register */
34304 /*! @{ */
34305 
34306 #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_MASK     (0xFU)
34307 #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT    (0U)
34308 /*! SB_ID - System Bus ID */
34309 #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_MASK)
34310 
34311 #define ENETC_GLOBAL_EMDIOUFSBESR_M_MASK         (0x40000000U)
34312 #define ENETC_GLOBAL_EMDIOUFSBESR_M_SHIFT        (30U)
34313 /*! M - Multiple */
34314 #define ENETC_GLOBAL_EMDIOUFSBESR_M(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_M_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_M_MASK)
34315 
34316 #define ENETC_GLOBAL_EMDIOUFSBESR_SBE_MASK       (0x80000000U)
34317 #define ENETC_GLOBAL_EMDIOUFSBESR_SBE_SHIFT      (31U)
34318 /*! SBE - System bus error */
34319 #define ENETC_GLOBAL_EMDIOUFSBESR_SBE(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_SBE_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_SBE_MASK)
34320 /*! @} */
34321 
34322 /*! @name TUFSBECR - Timer uncorrectable fatal system bus error configuration register */
34323 /*! @{ */
34324 
34325 #define ENETC_GLOBAL_TUFSBECR_RD_MASK            (0x80000000U)
34326 #define ENETC_GLOBAL_TUFSBECR_RD_SHIFT           (31U)
34327 /*! RD - Report disable */
34328 #define ENETC_GLOBAL_TUFSBECR_RD(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBECR_RD_SHIFT)) & ENETC_GLOBAL_TUFSBECR_RD_MASK)
34329 /*! @} */
34330 
34331 /*! @name TUFSBESR - Timer uncorrectable fatal system bus error status register */
34332 /*! @{ */
34333 
34334 #define ENETC_GLOBAL_TUFSBESR_SB_ID_MASK         (0xFU)
34335 #define ENETC_GLOBAL_TUFSBESR_SB_ID_SHIFT        (0U)
34336 /*! SB_ID - System Bus ID */
34337 #define ENETC_GLOBAL_TUFSBESR_SB_ID(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_SB_ID_SHIFT)) & ENETC_GLOBAL_TUFSBESR_SB_ID_MASK)
34338 
34339 #define ENETC_GLOBAL_TUFSBESR_M_MASK             (0x40000000U)
34340 #define ENETC_GLOBAL_TUFSBESR_M_SHIFT            (30U)
34341 /*! M - Multiple */
34342 #define ENETC_GLOBAL_TUFSBESR_M(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_M_SHIFT)) & ENETC_GLOBAL_TUFSBESR_M_MASK)
34343 
34344 #define ENETC_GLOBAL_TUFSBESR_SBE_MASK           (0x80000000U)
34345 #define ENETC_GLOBAL_TUFSBESR_SBE_SHIFT          (31U)
34346 /*! SBE - System bus error */
34347 #define ENETC_GLOBAL_TUFSBESR_SBE(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_SBE_SHIFT)) & ENETC_GLOBAL_TUFSBESR_SBE_MASK)
34348 /*! @} */
34349 
34350 
34351 /*!
34352  * @}
34353  */ /* end of group ENETC_GLOBAL_Register_Masks */
34354 
34355 
34356 /* ENETC_GLOBAL - Peripheral instance base addresses */
34357 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
34358   /** Peripheral EMDIO_GLOBAL base address */
34359   #define EMDIO_GLOBAL_BASE                        (0x70BB0000u)
34360   /** Peripheral EMDIO_GLOBAL base address */
34361   #define EMDIO_GLOBAL_BASE_NS                     (0x60BB0000u)
34362   /** Peripheral EMDIO_GLOBAL base pointer */
34363   #define EMDIO_GLOBAL                             ((ENETC_GLOBAL_Type *)EMDIO_GLOBAL_BASE)
34364   /** Peripheral EMDIO_GLOBAL base pointer */
34365   #define EMDIO_GLOBAL_NS                          ((ENETC_GLOBAL_Type *)EMDIO_GLOBAL_BASE_NS)
34366   /** Peripheral ENETC0_GLOBAL base address */
34367   #define ENETC0_GLOBAL_BASE                       (0x70B20000u)
34368   /** Peripheral ENETC0_GLOBAL base address */
34369   #define ENETC0_GLOBAL_BASE_NS                    (0x60B20000u)
34370   /** Peripheral ENETC0_GLOBAL base pointer */
34371   #define ENETC0_GLOBAL                            ((ENETC_GLOBAL_Type *)ENETC0_GLOBAL_BASE)
34372   /** Peripheral ENETC0_GLOBAL base pointer */
34373   #define ENETC0_GLOBAL_NS                         ((ENETC_GLOBAL_Type *)ENETC0_GLOBAL_BASE_NS)
34374   /** Peripheral ENETC1_GLOBAL base address */
34375   #define ENETC1_GLOBAL_BASE                       (0x70B60000u)
34376   /** Peripheral ENETC1_GLOBAL base address */
34377   #define ENETC1_GLOBAL_BASE_NS                    (0x60B60000u)
34378   /** Peripheral ENETC1_GLOBAL base pointer */
34379   #define ENETC1_GLOBAL                            ((ENETC_GLOBAL_Type *)ENETC1_GLOBAL_BASE)
34380   /** Peripheral ENETC1_GLOBAL base pointer */
34381   #define ENETC1_GLOBAL_NS                         ((ENETC_GLOBAL_Type *)ENETC1_GLOBAL_BASE_NS)
34382   /** Peripheral SW0_GLOBAL base address */
34383   #define SW0_GLOBAL_BASE                          (0x70A80000u)
34384   /** Peripheral SW0_GLOBAL base address */
34385   #define SW0_GLOBAL_BASE_NS                       (0x60A80000u)
34386   /** Peripheral SW0_GLOBAL base pointer */
34387   #define SW0_GLOBAL                               ((ENETC_GLOBAL_Type *)SW0_GLOBAL_BASE)
34388   /** Peripheral SW0_GLOBAL base pointer */
34389   #define SW0_GLOBAL_NS                            ((ENETC_GLOBAL_Type *)SW0_GLOBAL_BASE_NS)
34390   /** Peripheral TMR0_GLOBAL base address */
34391   #define TMR0_GLOBAL_BASE                         (0x70B90000u)
34392   /** Peripheral TMR0_GLOBAL base address */
34393   #define TMR0_GLOBAL_BASE_NS                      (0x60B90000u)
34394   /** Peripheral TMR0_GLOBAL base pointer */
34395   #define TMR0_GLOBAL                              ((ENETC_GLOBAL_Type *)TMR0_GLOBAL_BASE)
34396   /** Peripheral TMR0_GLOBAL base pointer */
34397   #define TMR0_GLOBAL_NS                           ((ENETC_GLOBAL_Type *)TMR0_GLOBAL_BASE_NS)
34398   /** Array initializer of ENETC_GLOBAL peripheral base addresses */
34399   #define ENETC_GLOBAL_BASE_ADDRS                  { EMDIO_GLOBAL_BASE, ENETC0_GLOBAL_BASE, ENETC1_GLOBAL_BASE, SW0_GLOBAL_BASE, TMR0_GLOBAL_BASE }
34400   /** Array initializer of ENETC_GLOBAL peripheral base pointers */
34401   #define ENETC_GLOBAL_BASE_PTRS                   { EMDIO_GLOBAL, ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL, TMR0_GLOBAL }
34402   /** Array initializer of ENETC_GLOBAL peripheral base addresses */
34403   #define ENETC_GLOBAL_BASE_ADDRS_NS               { EMDIO_GLOBAL_BASE_NS, ENETC0_GLOBAL_BASE_NS, ENETC1_GLOBAL_BASE_NS, SW0_GLOBAL_BASE_NS, TMR0_GLOBAL_BASE_NS }
34404   /** Array initializer of ENETC_GLOBAL peripheral base pointers */
34405   #define ENETC_GLOBAL_BASE_PTRS_NS                { EMDIO_GLOBAL_NS, ENETC0_GLOBAL_NS, ENETC1_GLOBAL_NS, SW0_GLOBAL_NS, TMR0_GLOBAL_NS }
34406 #else
34407   /** Peripheral EMDIO_GLOBAL base address */
34408   #define EMDIO_GLOBAL_BASE                        (0x60BB0000u)
34409   /** Peripheral EMDIO_GLOBAL base pointer */
34410   #define EMDIO_GLOBAL                             ((ENETC_GLOBAL_Type *)EMDIO_GLOBAL_BASE)
34411   /** Peripheral ENETC0_GLOBAL base address */
34412   #define ENETC0_GLOBAL_BASE                       (0x60B20000u)
34413   /** Peripheral ENETC0_GLOBAL base pointer */
34414   #define ENETC0_GLOBAL                            ((ENETC_GLOBAL_Type *)ENETC0_GLOBAL_BASE)
34415   /** Peripheral ENETC1_GLOBAL base address */
34416   #define ENETC1_GLOBAL_BASE                       (0x60B60000u)
34417   /** Peripheral ENETC1_GLOBAL base pointer */
34418   #define ENETC1_GLOBAL                            ((ENETC_GLOBAL_Type *)ENETC1_GLOBAL_BASE)
34419   /** Peripheral SW0_GLOBAL base address */
34420   #define SW0_GLOBAL_BASE                          (0x60A80000u)
34421   /** Peripheral SW0_GLOBAL base pointer */
34422   #define SW0_GLOBAL                               ((ENETC_GLOBAL_Type *)SW0_GLOBAL_BASE)
34423   /** Peripheral TMR0_GLOBAL base address */
34424   #define TMR0_GLOBAL_BASE                         (0x60B90000u)
34425   /** Peripheral TMR0_GLOBAL base pointer */
34426   #define TMR0_GLOBAL                              ((ENETC_GLOBAL_Type *)TMR0_GLOBAL_BASE)
34427   /** Array initializer of ENETC_GLOBAL peripheral base addresses */
34428   #define ENETC_GLOBAL_BASE_ADDRS                  { EMDIO_GLOBAL_BASE, ENETC0_GLOBAL_BASE, ENETC1_GLOBAL_BASE, SW0_GLOBAL_BASE, TMR0_GLOBAL_BASE }
34429   /** Array initializer of ENETC_GLOBAL peripheral base pointers */
34430   #define ENETC_GLOBAL_BASE_PTRS                   { EMDIO_GLOBAL, ENETC0_GLOBAL, ENETC1_GLOBAL, SW0_GLOBAL, TMR0_GLOBAL }
34431 #endif
34432 
34433 /*!
34434  * @}
34435  */ /* end of group ENETC_GLOBAL_Peripheral_Access_Layer */
34436 
34437 
34438 /* ----------------------------------------------------------------------------
34439    -- ENETC_PCI_TYPE0 Peripheral Access Layer
34440    ---------------------------------------------------------------------------- */
34441 
34442 /*!
34443  * @addtogroup ENETC_PCI_TYPE0_Peripheral_Access_Layer ENETC_PCI_TYPE0 Peripheral Access Layer
34444  * @{
34445  */
34446 
34447 /** ENETC_PCI_TYPE0 - Register Layout Typedef */
34448 typedef struct {
34449   __I  uint32_t PCI_CFH_DID_VID;                   /**< PCI device ID and vendor ID register, offset: 0x0 */
34450   __IO uint16_t PCI_CFH_CMD;                       /**< PCI command register, offset: 0x4 */
34451   __I  uint16_t PCI_CFH_STAT;                      /**< PCI status register, offset: 0x6 */
34452   __I  uint32_t PCI_CFH_REVID_CLASSCODE;           /**< PCI revision ID and classcode register, offset: 0x8 */
34453   __IO uint8_t PCI_CFH_CL_SIZE;                    /**< PCI cache line size register, offset: 0xC */
34454        uint8_t RESERVED_0[1];
34455   __I  uint8_t PCI_CFH_HDR_TYPE;                   /**< PCI header type register, offset: 0xE */
34456        uint8_t RESERVED_1[1];
34457   __I  uint32_t PCI_CFH_BAR0;                      /**< PCI base address register 0, offset: 0x10 */
34458   __I  uint32_t PCI_CFH_BAR1;                      /**< PCI base address register 1, offset: 0x14 */
34459   __I  uint32_t PCI_CFH_BAR2;                      /**< PCI base address register 2, offset: 0x18 */
34460   __I  uint32_t PCI_CFH_BAR3;                      /**< PCI base address register 3, offset: 0x1C */
34461   __I  uint32_t PCI_CFH_BAR4;                      /**< PCI base address register 4, offset: 0x20 */
34462   __I  uint32_t PCI_CFH_BAR5;                      /**< PCI base address register 5, offset: 0x24 */
34463        uint8_t RESERVED_2[4];
34464   __I  uint16_t PCI_CFH_SUBSYS_VID;                /**< PCI subsystem vendor ID register, offset: 0x2C */
34465   __I  uint16_t PCI_CFH_SUBSYS_ID;                 /**< PCI subsystem ID register, offset: 0x2E */
34466        uint8_t RESERVED_3[4];
34467   __I  uint8_t PCI_CFH_CAP_PTR;                    /**< PCI capabilities pointer register, offset: 0x34 */
34468        uint8_t RESERVED_4[11];
34469   __I  uint16_t PCI_CFC_PCIE_CAP_LIST;             /**< PCI PCIe capabilities list register, offset: 0x40 */
34470   __I  uint16_t PCI_CFC_PCIE_CAP;                  /**< PCI PCIe capabilities register, offset: 0x42 */
34471   __I  uint32_t PCI_CFC_PCIE_DEV_CAP;              /**< PCI PCIe device capabilities register, offset: 0x44 */
34472   __IO uint16_t PCI_CFC_PCIE_DEV_CTL;              /**< PCI PCIe device control register, offset: 0x48 */
34473   __I  uint16_t PCI_CFC_PCIE_DEV_STAT;             /**< PCI PCIe device status register, offset: 0x4A */
34474        uint8_t RESERVED_5[24];
34475   __I  uint32_t PCI_CFC_PCIE_DEV_CAP2;             /**< PCI PCIe device capabilities 2 register, offset: 0x64 */
34476   __I  uint16_t PCI_CFC_PCIE_DEV_CTL2;             /**< PCI PCIe device control 2 register, offset: 0x68 */
34477        uint8_t RESERVED_6[22];
34478   __I  uint16_t PCI_CFC_MSIX_CAP_LIST;             /**< PCI MSI-X capabilities list register, offset: 0x80 */
34479   __IO uint16_t PCI_CFC_MSIX_MSG_CTL;              /**< PCI MSI-X message control register, offset: 0x82 */
34480   __I  uint32_t PCI_CFC_MSIX_TABLE_OFF_BIR;        /**< PCI MSI-X table offset/BIR register, offset: 0x84 */
34481   __I  uint32_t PCI_CFC_MSIX_PBA_OFF_BIR;          /**< PCI MSI-X PBA offset/BIR register, offset: 0x88 */
34482        uint8_t RESERVED_7[4];
34483   __I  uint16_t PCI_CFC_PCIPM_CAP_LIST;            /**< PCI PCI-PM capabilities list register, offset: 0x90 */
34484   __I  uint16_t PCI_CFC_PCIPM_CAP;                 /**< PCI PCI-PM capabilities register, offset: 0x92 */
34485   __IO uint16_t PCI_CFC_PCIPM_CTL_STAT;            /**< PCI PCI-PM control and status register, offset: 0x94 */
34486        uint8_t RESERVED_8[1];
34487        uint8_t PCI_CFC_PCIPM_DATA;                 /**< PCI PCI-PM capabilities data register, offset: 0x97 */
34488        uint8_t RESERVED_9[4];
34489   __I  uint16_t PCI_CFC_EA_CAP_LIST;               /**< PCI EA capabilities list register, offset: 0x9C */
34490   __I  uint16_t PCI_CFC_EA_CAP;                    /**< PCI EA capabilities register, offset: 0x9E */
34491   struct {                                         /* offset: 0xA0, array step: 0x10 */
34492     __I  uint32_t PCI_CFC_EA_PE_FMT;                 /**< PCI EA per-entry 0 format register..PCI EA per-entry 3 format register, array offset: 0xA0, array step: 0x10, irregular array, not all indices are valid */
34493     __I  uint32_t PCI_CFC_EA_PE_BASE;                /**< PCI EA per-entry 0 base register..PCI EA per-entry 3 base register, array offset: 0xA4, array step: 0x10, irregular array, not all indices are valid */
34494     __I  uint32_t PCI_CFC_EA_PE_MAXOFF;              /**< PCI EA per-entry 0 max offset register..PCI EA per-entry 3 max offset register, array offset: 0xA8, array step: 0x10, irregular array, not all indices are valid */
34495     __I  uint32_t PCI_CFC_EA_PE_EXT_BASE;            /**< PCI EA per-entry 0 extended base register..PCI EA per-entry 3 extended base register, array offset: 0xAC, array step: 0x10, irregular array, not all indices are valid */
34496   } NUM_EA[4];
34497        uint8_t RESERVED_10[32];
34498   __I  uint32_t PCIE_CFC_AER_EXT_CAP_HDR;          /**< PCIe AER extended capability header, offset: 0x100 */
34499   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_STAT;       /**< PCIe AER uncorrectable error status register, offset: 0x104 */
34500   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_MASK;       /**< PCIe AER uncorrectable error mask register, offset: 0x108 */
34501   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_SEV;        /**< PCIe AER uncorrectable error severity register, offset: 0x10C */
34502   __IO uint32_t PCIE_CFC_AER_CORR_ERR_STAT;        /**< PCIe AER correctable error status register, offset: 0x110 */
34503   __IO uint32_t PCIE_CFC_AER_CORR_ERR_MASK;        /**< PCIe AER correctable error mask register, offset: 0x114 */
34504   __I  uint32_t PCIE_CFC_AER_CAP_CTL;              /**< PCIe AER capabilities and control register, offset: 0x118 */
34505        uint8_t RESERVED_11[20];
34506   __I  uint32_t PCIE_CFC_ACS_CAP_HDR;              /**< PCIe ACS capability header, offset: 0x130 */
34507   __I  uint16_t PCIE_CFC_ACS_CAP;                  /**< PCIe ACS capability register, offset: 0x134 */
34508   __I  uint16_t PCIE_CFC_ACS_CTL;                  /**< PCIe ACS control register, offset: 0x136 */
34509        uint8_t RESERVED_12[8];
34510   __I  uint32_t PCIE_CFC_RTR_CAP_HDR;              /**< PCIe readiness time reporting capability header, offset: 0x140 */
34511   __I  uint32_t PCIE_CFC_RTR_RTR1;                 /**< PCIe RTR readiness time reporting 1 register, offset: 0x144 */
34512   __I  uint32_t PCIE_CFC_RTR_RTR2;                 /**< PCIe RTR readiness time reporting 2 register, offset: 0x148 */
34513        uint8_t RESERVED_13[4];
34514   __I  uint32_t PCIE_CFC_SRIOV_CAP_HDR;            /**< PCIe SR-IOV capability header, offset: 0x150, not available in all instances (available on 2 out of 10) */
34515   __I  uint32_t PCIE_CFC_SRIOV_CAP;                /**< PCIe SR-IOV capability register, offset: 0x154, not available in all instances (available on 2 out of 10) */
34516   __IO uint16_t PCIE_CFC_SRIOV_CTL;                /**< PCIe SR-IOV control register, offset: 0x158, not available in all instances (available on 2 out of 10) */
34517   __I  uint16_t PCIE_CFC_SRIOV_STAT;               /**< PCIe SR-IOV status register, offset: 0x15A, not available in all instances (available on 2 out of 10) */
34518   __I  uint16_t PCIE_CFC_SRIOV_INIT_VFS;           /**< PCIe SR-IOV initial VFs register, offset: 0x15C, not available in all instances (available on 2 out of 10) */
34519   __I  uint16_t PCIE_CFC_SRIOV_TOTAL_VFS;          /**< PCIe SR-IOV total VFs register, offset: 0x15E, not available in all instances (available on 2 out of 10) */
34520   __IO uint16_t PCIE_CFC_SRIOV_NUM_VFS;            /**< PCIe SR-IOV num VFs register, offset: 0x160, not available in all instances (available on 2 out of 10) */
34521   __I  uint16_t PCIE_CFC_SRIOV_FUNC_DEP_LIST;      /**< PCIe SR-IOV function dependency list register, offset: 0x162, not available in all instances (available on 2 out of 10) */
34522   __I  uint16_t PCIE_CFC_SRIOV_FIRST_VF_OFF;       /**< PCIe SR-IOV first VF offset register, offset: 0x164, not available in all instances (available on 2 out of 10) */
34523   __I  uint16_t PCIE_CFC_SRIOV_VF_STRIDE;          /**< PCIe SR-IOV VF stride register, offset: 0x166, not available in all instances (available on 2 out of 10) */
34524        uint8_t RESERVED_14[2];
34525   __I  uint16_t PCIE_CFC_SRIOV_VF_DEV_ID;          /**< PCIe SR-IOV VF device ID register, offset: 0x16A, not available in all instances (available on 2 out of 10) */
34526   __I  uint32_t PCIE_CFC_SRIOV_SUP_PAGE_SIZES;     /**< PCIe SR-IOV supported page sizes ID register, offset: 0x16C, not available in all instances (available on 2 out of 10) */
34527   __I  uint32_t PCIE_CFC_SRIOV_SYS_PAGE_SIZE;      /**< PCIe SR-IOV system page size ID register, offset: 0x170, not available in all instances (available on 2 out of 10) */
34528   __I  uint32_t PCIE_CFC_VF_BAR[6];                /**< PCIe SR-IOV VF base address register 0..PCIe SR-IOV VF base address register 5, array offset: 0x174, array step: 0x4, not available in all instances (available on 2 out of 10) */
34529   __I  uint32_t PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF; /**< PCIe SR-IOV VF migration state array offset register, offset: 0x18C, not available in all instances (available on 2 out of 10) */
34530 } ENETC_PCI_TYPE0_Type;
34531 
34532 /* ----------------------------------------------------------------------------
34533    -- ENETC_PCI_TYPE0 Register Masks
34534    ---------------------------------------------------------------------------- */
34535 
34536 /*!
34537  * @addtogroup ENETC_PCI_TYPE0_Register_Masks ENETC_PCI_TYPE0 Register Masks
34538  * @{
34539  */
34540 
34541 /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */
34542 /*! @{ */
34543 
34544 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU)
34545 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U)
34546 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK)
34547 
34548 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U)
34549 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U)
34550 #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK)
34551 /*! @} */
34552 
34553 /*! @name PCI_CFH_CMD - PCI command register */
34554 /*! @{ */
34555 
34556 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK (0x2U)
34557 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT (1U)
34558 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK)
34559 
34560 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK (0x4U)
34561 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT (2U)
34562 #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK)
34563 /*! @} */
34564 
34565 /*! @name PCI_CFH_STAT - PCI status register */
34566 /*! @{ */
34567 
34568 #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK (0x10U)
34569 #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT (4U)
34570 #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK)
34571 /*! @} */
34572 
34573 /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */
34574 /*! @{ */
34575 
34576 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU)
34577 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U)
34578 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK)
34579 
34580 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U)
34581 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U)
34582 #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK)
34583 /*! @} */
34584 
34585 /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */
34586 /*! @{ */
34587 
34588 #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU)
34589 #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U)
34590 #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK)
34591 /*! @} */
34592 
34593 /*! @name PCI_CFH_HDR_TYPE - PCI header type register */
34594 /*! @{ */
34595 
34596 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU)
34597 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U)
34598 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK)
34599 
34600 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U)
34601 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U)
34602 #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK)
34603 /*! @} */
34604 
34605 /*! @name PCI_CFH_BAR0 - PCI base address register 0 */
34606 /*! @{ */
34607 
34608 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK (0x1U)
34609 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT (0U)
34610 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK)
34611 
34612 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK (0x6U)
34613 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT (1U)
34614 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK)
34615 
34616 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK (0x8U)
34617 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT (3U)
34618 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK)
34619 
34620 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK   (0xFFFFFFF0U)
34621 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT  (4U)
34622 #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK)
34623 /*! @} */
34624 
34625 /*! @name PCI_CFH_BAR1 - PCI base address register 1 */
34626 /*! @{ */
34627 
34628 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK (0x1U)
34629 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT (0U)
34630 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK)
34631 
34632 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK (0x6U)
34633 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT (1U)
34634 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK)
34635 
34636 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK (0x8U)
34637 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT (3U)
34638 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK)
34639 
34640 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK   (0xFFFFFFF0U)
34641 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT  (4U)
34642 #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK)
34643 /*! @} */
34644 
34645 /*! @name PCI_CFH_BAR2 - PCI base address register 2 */
34646 /*! @{ */
34647 
34648 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK (0x1U)
34649 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT (0U)
34650 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK)
34651 
34652 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK (0x6U)
34653 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT (1U)
34654 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK)
34655 
34656 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK (0x8U)
34657 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT (3U)
34658 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK)
34659 
34660 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK   (0xFFFFFFF0U)
34661 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT  (4U)
34662 #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK)
34663 /*! @} */
34664 
34665 /*! @name PCI_CFH_BAR3 - PCI base address register 3 */
34666 /*! @{ */
34667 
34668 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK (0x1U)
34669 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT (0U)
34670 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK)
34671 
34672 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK (0x6U)
34673 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT (1U)
34674 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK)
34675 
34676 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK (0x8U)
34677 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT (3U)
34678 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK)
34679 
34680 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK   (0xFFFFFFF0U)
34681 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT  (4U)
34682 #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK)
34683 /*! @} */
34684 
34685 /*! @name PCI_CFH_BAR4 - PCI base address register 4 */
34686 /*! @{ */
34687 
34688 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK (0x1U)
34689 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT (0U)
34690 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK)
34691 
34692 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK (0x6U)
34693 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT (1U)
34694 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK)
34695 
34696 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK (0x8U)
34697 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT (3U)
34698 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK)
34699 
34700 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK   (0xFFFFFFF0U)
34701 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT  (4U)
34702 #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK)
34703 /*! @} */
34704 
34705 /*! @name PCI_CFH_BAR5 - PCI base address register 5 */
34706 /*! @{ */
34707 
34708 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK (0x1U)
34709 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT (0U)
34710 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK)
34711 
34712 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK (0x6U)
34713 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT (1U)
34714 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK)
34715 
34716 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK (0x8U)
34717 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT (3U)
34718 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK)
34719 
34720 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK   (0xFFFFFFF0U)
34721 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT  (4U)
34722 #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK)
34723 /*! @} */
34724 
34725 /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */
34726 /*! @{ */
34727 
34728 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
34729 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
34730 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK)
34731 /*! @} */
34732 
34733 /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */
34734 /*! @{ */
34735 
34736 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK (0xFFFFU)
34737 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT (0U)
34738 #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK)
34739 /*! @} */
34740 
34741 /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */
34742 /*! @{ */
34743 
34744 #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU)
34745 #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U)
34746 #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK)
34747 /*! @} */
34748 
34749 /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */
34750 /*! @{ */
34751 
34752 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU)
34753 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U)
34754 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK)
34755 
34756 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
34757 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
34758 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK)
34759 /*! @} */
34760 
34761 /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */
34762 /*! @{ */
34763 
34764 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU)
34765 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U)
34766 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK)
34767 
34768 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U)
34769 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U)
34770 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK)
34771 
34772 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U)
34773 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U)
34774 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK)
34775 /*! @} */
34776 
34777 /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */
34778 /*! @{ */
34779 
34780 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U)
34781 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U)
34782 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK)
34783 /*! @} */
34784 
34785 /*! @name PCI_CFC_PCIE_DEV_CTL - PCI PCIe device control register */
34786 /*! @{ */
34787 
34788 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK (0x8000U)
34789 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT (15U)
34790 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK)
34791 /*! @} */
34792 
34793 /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */
34794 /*! @{ */
34795 
34796 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U)
34797 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U)
34798 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK)
34799 /*! @} */
34800 
34801 /*! @name PCI_CFC_PCIE_DEV_CAP2 - PCI PCIe device capabilities 2 register */
34802 /*! @{ */
34803 
34804 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK (0xFU)
34805 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT (0U)
34806 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK)
34807 
34808 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK (0x10U)
34809 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT (4U)
34810 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK)
34811 /*! @} */
34812 
34813 /*! @name PCI_CFC_PCIE_DEV_CTL2 - PCI PCIe device control 2 register */
34814 /*! @{ */
34815 
34816 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK (0xFU)
34817 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT (0U)
34818 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK)
34819 
34820 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK (0x10U)
34821 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT (4U)
34822 #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK)
34823 /*! @} */
34824 
34825 /*! @name PCI_CFC_MSIX_CAP_LIST - PCI MSI-X capabilities list register */
34826 /*! @{ */
34827 
34828 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK (0xFFU)
34829 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT (0U)
34830 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK)
34831 
34832 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
34833 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
34834 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK)
34835 /*! @} */
34836 
34837 /*! @name PCI_CFC_MSIX_MSG_CTL - PCI MSI-X message control register */
34838 /*! @{ */
34839 
34840 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK (0x7FFU)
34841 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT (0U)
34842 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK)
34843 
34844 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK (0x4000U)
34845 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT (14U)
34846 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK)
34847 
34848 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK (0x8000U)
34849 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT (15U)
34850 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK)
34851 /*! @} */
34852 
34853 /*! @name PCI_CFC_MSIX_TABLE_OFF_BIR - PCI MSI-X table offset/BIR register */
34854 /*! @{ */
34855 
34856 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK (0x7U)
34857 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT (0U)
34858 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK)
34859 
34860 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK (0xFFFFFFF8U)
34861 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT (3U)
34862 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK)
34863 /*! @} */
34864 
34865 /*! @name PCI_CFC_MSIX_PBA_OFF_BIR - PCI MSI-X PBA offset/BIR register */
34866 /*! @{ */
34867 
34868 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK (0x7U)
34869 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT (0U)
34870 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK)
34871 
34872 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK (0xFFFFFFF8U)
34873 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT (3U)
34874 #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK)
34875 /*! @} */
34876 
34877 /*! @name PCI_CFC_PCIPM_CAP_LIST - PCI PCI-PM capabilities list register */
34878 /*! @{ */
34879 
34880 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK (0xFFU)
34881 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT (0U)
34882 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK)
34883 
34884 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
34885 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
34886 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK)
34887 /*! @} */
34888 
34889 /*! @name PCI_CFC_PCIPM_CAP - PCI PCI-PM capabilities register */
34890 /*! @{ */
34891 
34892 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_MASK (0x7U)
34893 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_SHIFT (0U)
34894 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_MASK)
34895 
34896 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK (0xF800U)
34897 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT (11U)
34898 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK)
34899 /*! @} */
34900 
34901 /*! @name PCI_CFC_PCIPM_CTL_STAT - PCI PCI-PM control and status register */
34902 /*! @{ */
34903 
34904 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK (0x3U)
34905 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT (0U)
34906 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK)
34907 
34908 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK (0x8U)
34909 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT (3U)
34910 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK)
34911 
34912 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_MASK (0x100U)
34913 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_SHIFT (8U)
34914 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_MASK)
34915 
34916 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_MASK (0x8000U)
34917 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_SHIFT (15U)
34918 #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_MASK)
34919 /*! @} */
34920 
34921 /*! @name PCI_CFC_EA_CAP_LIST - PCI EA capabilities list register */
34922 /*! @{ */
34923 
34924 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_MASK (0xFFU)
34925 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_SHIFT (0U)
34926 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_MASK)
34927 
34928 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
34929 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
34930 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_MASK)
34931 /*! @} */
34932 
34933 /*! @name PCI_CFC_EA_CAP - PCI EA capabilities register */
34934 /*! @{ */
34935 
34936 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_MASK (0x3FU)
34937 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_SHIFT (0U)
34938 #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_MASK)
34939 /*! @} */
34940 
34941 /*! @name PCI_CFC_EA_PE_FMT - PCI EA per-entry 0 format register..PCI EA per-entry 3 format register */
34942 /*! @{ */
34943 
34944 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_MASK (0x7U)
34945 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_SHIFT (0U)
34946 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_MASK)
34947 
34948 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_MASK (0xF0U)
34949 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_SHIFT (4U)
34950 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_MASK)
34951 
34952 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_MASK (0xFF00U)
34953 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_SHIFT (8U)
34954 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_MASK)
34955 
34956 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_MASK (0xFF0000U)
34957 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_SHIFT (16U)
34958 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_MASK)
34959 
34960 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_MASK (0x40000000U)
34961 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_SHIFT (30U)
34962 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_MASK)
34963 
34964 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_MASK (0x80000000U)
34965 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_SHIFT (31U)
34966 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_MASK)
34967 /*! @} */
34968 
34969 /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT */
34970 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_COUNT  (4U)
34971 
34972 /*! @name PCI_CFC_EA_PE_BASE - PCI EA per-entry 0 base register..PCI EA per-entry 3 base register */
34973 /*! @{ */
34974 
34975 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_MASK (0x2U)
34976 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_SHIFT (1U)
34977 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_MASK)
34978 
34979 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_MASK (0xFFFFFFFCU)
34980 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_SHIFT (2U)
34981 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_MASK)
34982 /*! @} */
34983 
34984 /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE */
34985 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_COUNT (4U)
34986 
34987 /*! @name PCI_CFC_EA_PE_MAXOFF - PCI EA per-entry 0 max offset register..PCI EA per-entry 3 max offset register */
34988 /*! @{ */
34989 
34990 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_MASK (0x2U)
34991 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_SHIFT (1U)
34992 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_MASK)
34993 
34994 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_MASK (0xFFFFFFFCU)
34995 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_SHIFT (2U)
34996 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_MASK)
34997 /*! @} */
34998 
34999 /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF */
35000 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_COUNT (4U)
35001 
35002 /*! @name PCI_CFC_EA_PE_EXT_BASE - PCI EA per-entry 0 extended base register..PCI EA per-entry 3 extended base register */
35003 /*! @{ */
35004 
35005 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_MASK (0xFFFFFFFFU)
35006 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_SHIFT (0U)
35007 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_MASK)
35008 /*! @} */
35009 
35010 /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE */
35011 #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_COUNT (4U)
35012 
35013 /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */
35014 /*! @{ */
35015 
35016 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
35017 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
35018 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
35019 
35020 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U)
35021 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U)
35022 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK)
35023 
35024 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
35025 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
35026 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK)
35027 /*! @} */
35028 
35029 /*! @name PCIE_CFC_AER_UCORR_ERR_STAT - PCIe AER uncorrectable error status register */
35030 /*! @{ */
35031 
35032 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_MASK (0x200000U)
35033 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_SHIFT (21U)
35034 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_MASK)
35035 
35036 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK (0x400000U)
35037 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT (22U)
35038 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK)
35039 /*! @} */
35040 
35041 /*! @name PCIE_CFC_AER_UCORR_ERR_MASK - PCIe AER uncorrectable error mask register */
35042 /*! @{ */
35043 
35044 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK (0x400000U)
35045 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT (22U)
35046 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK)
35047 /*! @} */
35048 
35049 /*! @name PCIE_CFC_AER_UCORR_ERR_SEV - PCIe AER uncorrectable error severity register */
35050 /*! @{ */
35051 
35052 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK (0x400000U)
35053 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT (22U)
35054 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK)
35055 /*! @} */
35056 
35057 /*! @name PCIE_CFC_AER_CORR_ERR_STAT - PCIe AER correctable error status register */
35058 /*! @{ */
35059 
35060 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK (0x4000U)
35061 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT (14U)
35062 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK)
35063 /*! @} */
35064 
35065 /*! @name PCIE_CFC_AER_CORR_ERR_MASK - PCIe AER correctable error mask register */
35066 /*! @{ */
35067 
35068 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK (0x4000U)
35069 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT (14U)
35070 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK)
35071 /*! @} */
35072 
35073 /*! @name PCIE_CFC_AER_CAP_CTL - PCIe AER capabilities and control register */
35074 /*! @{ */
35075 
35076 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK (0x1FU)
35077 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT (0U)
35078 #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK)
35079 /*! @} */
35080 
35081 /*! @name PCIE_CFC_ACS_CAP_HDR - PCIe ACS capability header */
35082 /*! @{ */
35083 
35084 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
35085 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
35086 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
35087 
35088 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK (0xF0000U)
35089 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT (16U)
35090 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK)
35091 
35092 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
35093 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
35094 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK)
35095 /*! @} */
35096 
35097 /*! @name PCIE_CFC_ACS_CAP - PCIe ACS capability register */
35098 /*! @{ */
35099 
35100 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK (0x2U)
35101 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT (1U)
35102 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK)
35103 
35104 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK (0x4U)
35105 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT (2U)
35106 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK)
35107 
35108 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK (0x40U)
35109 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT (6U)
35110 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK)
35111 /*! @} */
35112 
35113 /*! @name PCIE_CFC_ACS_CTL - PCIe ACS control register */
35114 /*! @{ */
35115 
35116 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK (0x2U)
35117 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT (1U)
35118 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK)
35119 
35120 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK (0x4U)
35121 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT (2U)
35122 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK)
35123 
35124 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK (0x40U)
35125 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT (6U)
35126 #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK)
35127 /*! @} */
35128 
35129 /*! @name PCIE_CFC_RTR_CAP_HDR - PCIe readiness time reporting capability header */
35130 /*! @{ */
35131 
35132 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
35133 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
35134 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
35135 
35136 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK (0xF0000U)
35137 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT (16U)
35138 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK)
35139 
35140 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
35141 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
35142 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK)
35143 /*! @} */
35144 
35145 /*! @name PCIE_CFC_RTR_RTR1 - PCIe RTR readiness time reporting 1 register */
35146 /*! @{ */
35147 
35148 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK (0xFFFU)
35149 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT (0U)
35150 /*! RESET_TIME - Reset Time */
35151 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK)
35152 
35153 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK (0x80000000U)
35154 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT (31U)
35155 /*! VALID - Valid */
35156 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK)
35157 /*! @} */
35158 
35159 /*! @name PCIE_CFC_RTR_RTR2 - PCIe RTR readiness time reporting 2 register */
35160 /*! @{ */
35161 
35162 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK (0xFFFU)
35163 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT (0U)
35164 /*! FLR_TIME - FLR Time */
35165 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK)
35166 
35167 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK (0xFFF000U)
35168 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT (12U)
35169 /*! D3HOT_D0_TIME - D3 hot to D0 time */
35170 #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK)
35171 /*! @} */
35172 
35173 /*! @name PCIE_CFC_SRIOV_CAP_HDR - PCIe SR-IOV capability header */
35174 /*! @{ */
35175 
35176 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
35177 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
35178 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
35179 
35180 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_MASK (0xF0000U)
35181 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_SHIFT (16U)
35182 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_MASK)
35183 
35184 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
35185 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
35186 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_MASK)
35187 /*! @} */
35188 
35189 /*! @name PCIE_CFC_SRIOV_CAP - PCIe SR-IOV capability register */
35190 /*! @{ */
35191 
35192 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_MASK (0x1U)
35193 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_SHIFT (0U)
35194 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_MASK)
35195 
35196 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_MASK (0x2U)
35197 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_SHIFT (1U)
35198 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_MASK)
35199 
35200 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_MASK (0xFFE00000U)
35201 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_SHIFT (21U)
35202 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_MASK)
35203 /*! @} */
35204 
35205 /*! @name PCIE_CFC_SRIOV_CTL - PCIe SR-IOV control register */
35206 /*! @{ */
35207 
35208 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK (0x1U)
35209 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_SHIFT (0U)
35210 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK)
35211 
35212 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_MASK (0x2U)
35213 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_SHIFT (1U)
35214 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_MASK)
35215 
35216 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_MASK (0x4U)
35217 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_SHIFT (2U)
35218 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_MASK)
35219 
35220 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK (0x8U)
35221 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_SHIFT (3U)
35222 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK)
35223 
35224 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_MASK (0x10U)
35225 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_SHIFT (4U)
35226 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_MASK)
35227 
35228 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_MASK (0x400U)
35229 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_SHIFT (10U)
35230 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_MASK)
35231 
35232 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_MASK (0xF800U)
35233 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_SHIFT (11U)
35234 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_MASK)
35235 /*! @} */
35236 
35237 /*! @name PCIE_CFC_SRIOV_STAT - PCIe SR-IOV status register */
35238 /*! @{ */
35239 
35240 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_MASK (0x1U)
35241 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_SHIFT (0U)
35242 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_MASK)
35243 /*! @} */
35244 
35245 /*! @name PCIE_CFC_SRIOV_INIT_VFS - PCIe SR-IOV initial VFs register */
35246 /*! @{ */
35247 
35248 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_MASK (0xFFFFU)
35249 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_SHIFT (0U)
35250 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_MASK)
35251 /*! @} */
35252 
35253 /*! @name PCIE_CFC_SRIOV_TOTAL_VFS - PCIe SR-IOV total VFs register */
35254 /*! @{ */
35255 
35256 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_MASK (0xFFFFU)
35257 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_SHIFT (0U)
35258 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_MASK)
35259 /*! @} */
35260 
35261 /*! @name PCIE_CFC_SRIOV_NUM_VFS - PCIe SR-IOV num VFs register */
35262 /*! @{ */
35263 
35264 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_MASK (0xFFFFU)
35265 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_SHIFT (0U)
35266 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_MASK)
35267 /*! @} */
35268 
35269 /*! @name PCIE_CFC_SRIOV_FUNC_DEP_LIST - PCIe SR-IOV function dependency list register */
35270 /*! @{ */
35271 
35272 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_MASK (0xFFFFU)
35273 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_SHIFT (0U)
35274 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_MASK)
35275 /*! @} */
35276 
35277 /*! @name PCIE_CFC_SRIOV_FIRST_VF_OFF - PCIe SR-IOV first VF offset register */
35278 /*! @{ */
35279 
35280 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_MASK (0xFFFFU)
35281 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_SHIFT (0U)
35282 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_MASK)
35283 /*! @} */
35284 
35285 /*! @name PCIE_CFC_SRIOV_VF_STRIDE - PCIe SR-IOV VF stride register */
35286 /*! @{ */
35287 
35288 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_MASK (0xFFFFU)
35289 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_SHIFT (0U)
35290 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_MASK)
35291 /*! @} */
35292 
35293 /*! @name PCIE_CFC_SRIOV_VF_DEV_ID - PCIe SR-IOV VF device ID register */
35294 /*! @{ */
35295 
35296 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_MASK (0xFFFFU)
35297 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_SHIFT (0U)
35298 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_MASK)
35299 /*! @} */
35300 
35301 /*! @name PCIE_CFC_SRIOV_SUP_PAGE_SIZES - PCIe SR-IOV supported page sizes ID register */
35302 /*! @{ */
35303 
35304 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_MASK (0xFFFFFFFFU)
35305 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_SHIFT (0U)
35306 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_MASK)
35307 /*! @} */
35308 
35309 /*! @name PCIE_CFC_SRIOV_SYS_PAGE_SIZE - PCIe SR-IOV system page size ID register */
35310 /*! @{ */
35311 
35312 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_MASK (0xFFFFFFFFU)
35313 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_SHIFT (0U)
35314 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_MASK)
35315 /*! @} */
35316 
35317 /*! @name PCIE_CFC_VF_BAR - PCIe SR-IOV VF base address register 0..PCIe SR-IOV VF base address register 5 */
35318 /*! @{ */
35319 
35320 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_MASK (0x1U)
35321 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_SHIFT (0U)
35322 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_MASK)
35323 
35324 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_MASK (0x6U)
35325 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_SHIFT (1U)
35326 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_MASK)
35327 
35328 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_MASK (0x8U)
35329 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_SHIFT (3U)
35330 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_MASK)
35331 
35332 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_MASK (0xFFFFFFF0U)
35333 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_SHIFT (4U)
35334 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_MASK)
35335 /*! @} */
35336 
35337 /* The count of ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR */
35338 #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_COUNT    (6U)
35339 
35340 /*! @name PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF - PCIe SR-IOV VF migration state array offset register */
35341 /*! @{ */
35342 
35343 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_MASK (0xFFFFFFFFU)
35344 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_SHIFT (0U)
35345 #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_MASK)
35346 /*! @} */
35347 
35348 
35349 /*!
35350  * @}
35351  */ /* end of group ENETC_PCI_TYPE0_Register_Masks */
35352 
35353 
35354 /* ENETC_PCI_TYPE0 - Peripheral instance base addresses */
35355 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
35356   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base address */
35357   #define NETC_F0_PCI_HDR_TYPE0_BASE               (0x70000000u)
35358   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base address */
35359   #define NETC_F0_PCI_HDR_TYPE0_BASE_NS            (0x60000000u)
35360   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base pointer */
35361   #define NETC_F0_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F0_PCI_HDR_TYPE0_BASE)
35362   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base pointer */
35363   #define NETC_F0_PCI_HDR_TYPE0_NS                 ((ENETC_PCI_TYPE0_Type *)NETC_F0_PCI_HDR_TYPE0_BASE_NS)
35364   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base address */
35365   #define NETC_F1_PCI_HDR_TYPE0_BASE               (0x70001000u)
35366   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base address */
35367   #define NETC_F1_PCI_HDR_TYPE0_BASE_NS            (0x60001000u)
35368   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base pointer */
35369   #define NETC_F1_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F1_PCI_HDR_TYPE0_BASE)
35370   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base pointer */
35371   #define NETC_F1_PCI_HDR_TYPE0_NS                 ((ENETC_PCI_TYPE0_Type *)NETC_F1_PCI_HDR_TYPE0_BASE_NS)
35372   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base address */
35373   #define NETC_F2_PCI_HDR_TYPE0_BASE               (0x70002000u)
35374   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base address */
35375   #define NETC_F2_PCI_HDR_TYPE0_BASE_NS            (0x60002000u)
35376   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base pointer */
35377   #define NETC_F2_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F2_PCI_HDR_TYPE0_BASE)
35378   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base pointer */
35379   #define NETC_F2_PCI_HDR_TYPE0_NS                 ((ENETC_PCI_TYPE0_Type *)NETC_F2_PCI_HDR_TYPE0_BASE_NS)
35380   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base address */
35381   #define NETC_F3_PCI_HDR_TYPE0_BASE               (0x70003000u)
35382   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base address */
35383   #define NETC_F3_PCI_HDR_TYPE0_BASE_NS            (0x60003000u)
35384   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base pointer */
35385   #define NETC_F3_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F3_PCI_HDR_TYPE0_BASE)
35386   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base pointer */
35387   #define NETC_F3_PCI_HDR_TYPE0_NS                 ((ENETC_PCI_TYPE0_Type *)NETC_F3_PCI_HDR_TYPE0_BASE_NS)
35388   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base address */
35389   #define NETC_F4_PCI_HDR_TYPE0_BASE               (0x70004000u)
35390   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base address */
35391   #define NETC_F4_PCI_HDR_TYPE0_BASE_NS            (0x60004000u)
35392   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base pointer */
35393   #define NETC_F4_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F4_PCI_HDR_TYPE0_BASE)
35394   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base pointer */
35395   #define NETC_F4_PCI_HDR_TYPE0_NS                 ((ENETC_PCI_TYPE0_Type *)NETC_F4_PCI_HDR_TYPE0_BASE_NS)
35396   /** Array initializer of ENETC_PCI_TYPE0 peripheral base addresses */
35397   #define ENETC_PCI_TYPE0_BASE_ADDRS               { NETC_F0_PCI_HDR_TYPE0_BASE, NETC_F1_PCI_HDR_TYPE0_BASE, NETC_F2_PCI_HDR_TYPE0_BASE, NETC_F3_PCI_HDR_TYPE0_BASE, NETC_F4_PCI_HDR_TYPE0_BASE }
35398   /** Array initializer of ENETC_PCI_TYPE0 peripheral base pointers */
35399   #define ENETC_PCI_TYPE0_BASE_PTRS                { NETC_F0_PCI_HDR_TYPE0, NETC_F1_PCI_HDR_TYPE0, NETC_F2_PCI_HDR_TYPE0, NETC_F3_PCI_HDR_TYPE0, NETC_F4_PCI_HDR_TYPE0 }
35400   /** Array initializer of ENETC_PCI_TYPE0 peripheral base addresses */
35401   #define ENETC_PCI_TYPE0_BASE_ADDRS_NS            { NETC_F0_PCI_HDR_TYPE0_BASE_NS, NETC_F1_PCI_HDR_TYPE0_BASE_NS, NETC_F2_PCI_HDR_TYPE0_BASE_NS, NETC_F3_PCI_HDR_TYPE0_BASE_NS, NETC_F4_PCI_HDR_TYPE0_BASE_NS }
35402   /** Array initializer of ENETC_PCI_TYPE0 peripheral base pointers */
35403   #define ENETC_PCI_TYPE0_BASE_PTRS_NS             { NETC_F0_PCI_HDR_TYPE0_NS, NETC_F1_PCI_HDR_TYPE0_NS, NETC_F2_PCI_HDR_TYPE0_NS, NETC_F3_PCI_HDR_TYPE0_NS, NETC_F4_PCI_HDR_TYPE0_NS }
35404 #else
35405   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base address */
35406   #define NETC_F0_PCI_HDR_TYPE0_BASE               (0x60000000u)
35407   /** Peripheral NETC_F0_PCI_HDR_TYPE0 base pointer */
35408   #define NETC_F0_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F0_PCI_HDR_TYPE0_BASE)
35409   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base address */
35410   #define NETC_F1_PCI_HDR_TYPE0_BASE               (0x60001000u)
35411   /** Peripheral NETC_F1_PCI_HDR_TYPE0 base pointer */
35412   #define NETC_F1_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F1_PCI_HDR_TYPE0_BASE)
35413   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base address */
35414   #define NETC_F2_PCI_HDR_TYPE0_BASE               (0x60002000u)
35415   /** Peripheral NETC_F2_PCI_HDR_TYPE0 base pointer */
35416   #define NETC_F2_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F2_PCI_HDR_TYPE0_BASE)
35417   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base address */
35418   #define NETC_F3_PCI_HDR_TYPE0_BASE               (0x60003000u)
35419   /** Peripheral NETC_F3_PCI_HDR_TYPE0 base pointer */
35420   #define NETC_F3_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F3_PCI_HDR_TYPE0_BASE)
35421   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base address */
35422   #define NETC_F4_PCI_HDR_TYPE0_BASE               (0x60004000u)
35423   /** Peripheral NETC_F4_PCI_HDR_TYPE0 base pointer */
35424   #define NETC_F4_PCI_HDR_TYPE0                    ((ENETC_PCI_TYPE0_Type *)NETC_F4_PCI_HDR_TYPE0_BASE)
35425   /** Array initializer of ENETC_PCI_TYPE0 peripheral base addresses */
35426   #define ENETC_PCI_TYPE0_BASE_ADDRS               { NETC_F0_PCI_HDR_TYPE0_BASE, NETC_F1_PCI_HDR_TYPE0_BASE, NETC_F2_PCI_HDR_TYPE0_BASE, NETC_F3_PCI_HDR_TYPE0_BASE, NETC_F4_PCI_HDR_TYPE0_BASE }
35427   /** Array initializer of ENETC_PCI_TYPE0 peripheral base pointers */
35428   #define ENETC_PCI_TYPE0_BASE_PTRS                { NETC_F0_PCI_HDR_TYPE0, NETC_F1_PCI_HDR_TYPE0, NETC_F2_PCI_HDR_TYPE0, NETC_F3_PCI_HDR_TYPE0, NETC_F4_PCI_HDR_TYPE0 }
35429 #endif
35430 
35431 /*!
35432  * @}
35433  */ /* end of group ENETC_PCI_TYPE0_Peripheral_Access_Layer */
35434 
35435 
35436 /* ----------------------------------------------------------------------------
35437    -- ENETC_PF_EMDIO Peripheral Access Layer
35438    ---------------------------------------------------------------------------- */
35439 
35440 /*!
35441  * @addtogroup ENETC_PF_EMDIO_Peripheral_Access_Layer ENETC_PF_EMDIO Peripheral Access Layer
35442  * @{
35443  */
35444 
35445 /** ENETC_PF_EMDIO - Register Layout Typedef */
35446 typedef struct {
35447        uint8_t RESERVED_0[7168];
35448   __IO uint32_t EMDIO_CFG;                         /**< External MDIO configuration register, offset: 0x1C00 */
35449   __IO uint32_t EMDIO_CTL;                         /**< External MDIO interface control register, offset: 0x1C04 */
35450   __IO uint32_t EMDIO_DATA;                        /**< External MDIO interface data register, offset: 0x1C08 */
35451   __IO uint32_t EMDIO_ADDR;                        /**< External MDIO register address register, offset: 0x1C0C */
35452   __I  uint32_t EMDIO_STAT;                        /**< External MDIO status register, offset: 0x1C10 */
35453        uint8_t RESERVED_1[12];
35454   __IO uint32_t PHY_STATUS_CFG;                    /**< PHY status configuration register, offset: 0x1C20 */
35455   __IO uint32_t PHY_STATUS_CTL;                    /**< PHY status control register, offset: 0x1C24 */
35456   __I  uint32_t PHY_STATUS_DATA;                   /**< PHY status data register, offset: 0x1C28 */
35457   __IO uint32_t PHY_STATUS_ADDR;                   /**< PHY status register address register, offset: 0x1C2C */
35458   __IO uint32_t PHY_STATUS_EVENT;                  /**< PHY status event register, offset: 0x1C30 */
35459   __IO uint32_t PHY_STATUS_MASK;                   /**< PHY status mask register, offset: 0x1C34 */
35460        uint8_t RESERVED_2[8];
35461   __I  uint32_t MDIO_CFG;                          /**< MDIO configuration register, offset: 0x1C40 */
35462 } ENETC_PF_EMDIO_Type;
35463 
35464 /* ----------------------------------------------------------------------------
35465    -- ENETC_PF_EMDIO Register Masks
35466    ---------------------------------------------------------------------------- */
35467 
35468 /*!
35469  * @addtogroup ENETC_PF_EMDIO_Register_Masks ENETC_PF_EMDIO Register Masks
35470  * @{
35471  */
35472 
35473 /*! @name EMDIO_CFG - External MDIO configuration register */
35474 /*! @{ */
35475 
35476 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2_MASK       (0x1U)
35477 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2_SHIFT      (0U)
35478 /*! BSY2 - Busy 2 (same as bit 31)
35479  *  0b0..An MDIO transaction is not occurring; software may access other MDIO registers.
35480  *  0b1..An MDIO transaction is occurring.
35481  */
35482 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_BSY2_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_BSY2_MASK)
35483 
35484 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_MASK (0x2U)
35485 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_SHIFT (1U)
35486 /*! MDIO_RD_ER
35487  *  0b0..No error
35488  *  0b1..The last read transaction received no response from a PHY; any data read should be considered invalid
35489  *       (for example, the PHY address does not match any PHY available on the MDIO bus).
35490  */
35491 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_MASK)
35492 
35493 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_MASK  (0x1CU)
35494 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_SHIFT (2U)
35495 /*! MDIO_HOLD
35496  *  0b000..1 NETC cycle
35497  *  0b001..3 NETC cycles
35498  *  0b010..5 NETC cycles (default - recommended value)
35499  *  0b011..7 NETC cycles
35500  *  0b100..9 NETC cycles
35501  *  0b101..11 NETC cycles
35502  *  0b110..13 NETC cycles
35503  *  0b111..15 NETC cycles
35504  */
35505 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_MASK)
35506 
35507 #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_MASK    (0x20U)
35508 #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_SHIFT   (5U)
35509 /*! PRE_DIS
35510  *  0b0..Generation of MDIO preamble is enabled (default operation).
35511  *  0b1..Generation of MDIO preamble is disabled
35512  */
35513 #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_MASK)
35514 
35515 #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45_MASK      (0x40U)
35516 #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45_SHIFT     (6U)
35517 /*! ENC45
35518  *  0b0..Clause 22 transactions are used.
35519  *  0b1..Clause 45 transactions are used.
35520  */
35521 #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_ENC45_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_ENC45_MASK)
35522 
35523 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_MASK (0xFF80U)
35524 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_SHIFT (7U)
35525 /*! MDIO_CLK_DIV - MDIO Clock Divisor */
35526 #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_MASK)
35527 
35528 #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_MASK     (0x70000U)
35529 #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_SHIFT    (16U)
35530 /*! WHOAMI - Returns the virtual port ID. */
35531 #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_MASK)
35532 
35533 #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_MASK      (0x400000U)
35534 #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_SHIFT     (22U)
35535 /*! EHOLD - Extended HOLD
35536  *  0b0..Normal operation. MDIO hold time is specified in .
35537  *  0b1..Extended Operation
35538  */
35539 #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_MASK)
35540 
35541 #define ENETC_PF_EMDIO_EMDIO_CFG_NEG_MASK        (0x800000U)
35542 #define ENETC_PF_EMDIO_EMDIO_CFG_NEG_SHIFT       (23U)
35543 /*! NEG
35544  *  0b0..Normal operation - positive edge
35545  *  0b1..MDIO is driven by master on MDC negative edge (default for external MDIOs)
35546  */
35547 #define ENETC_PF_EMDIO_EMDIO_CFG_NEG(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_NEG_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_NEG_MASK)
35548 
35549 #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_MASK   (0x10000000U)
35550 #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_SHIFT  (28U)
35551 /*! ADDR_ERR
35552  *  0b0..Normal
35553  *  0b1..Error. An access control violation has occurred. The request address used does not match the MDIO PHY's
35554  *       address (clause 22) or MDIO port address (clause 45) assigned.
35555  */
35556 #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_MASK)
35557 
35558 #define ENETC_PF_EMDIO_EMDIO_CFG_CIM_MASK        (0x20000000U)
35559 #define ENETC_PF_EMDIO_EMDIO_CFG_CIM_SHIFT       (29U)
35560 /*! CIM
35561  *  0b0..Masked
35562  *  0b1..Enabled
35563  */
35564 #define ENETC_PF_EMDIO_EMDIO_CFG_CIM(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_CIM_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_CIM_MASK)
35565 
35566 #define ENETC_PF_EMDIO_EMDIO_CFG_CMP_MASK        (0x40000000U)
35567 #define ENETC_PF_EMDIO_EMDIO_CFG_CMP_SHIFT       (30U)
35568 /*! CMP - MDIO Command Completion
35569  *  0b0..An MDIO command completion did not occur.
35570  *  0b1..An MDIO command completion occurred.
35571  */
35572 #define ENETC_PF_EMDIO_EMDIO_CFG_CMP(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_CMP_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_CMP_MASK)
35573 
35574 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1_MASK       (0x80000000U)
35575 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1_SHIFT      (31U)
35576 /*! BSY1 - Busy 1
35577  *  0b0..An MDIO transaction is not occurring; software may access other MDIO registers.
35578  *  0b1..An MDIO transaction is occurring.
35579  */
35580 #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_BSY1_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_BSY1_MASK)
35581 /*! @} */
35582 
35583 /*! @name EMDIO_CTL - External MDIO interface control register */
35584 /*! @{ */
35585 
35586 #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_MASK   (0x1FU)
35587 #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_SHIFT  (0U)
35588 /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */
35589 #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_MASK)
35590 
35591 #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_MASK  (0x3E0U)
35592 #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_SHIFT (5U)
35593 /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */
35594 #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_MASK)
35595 
35596 #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_MASK   (0x4000U)
35597 #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_SHIFT  (14U)
35598 /*! POST_INC - MDIO read with address post-increment initiation. Self-clearing once transaction is complete. */
35599 #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_MASK)
35600 
35601 #define ENETC_PF_EMDIO_EMDIO_CTL_READ_MASK       (0x8000U)
35602 #define ENETC_PF_EMDIO_EMDIO_CTL_READ_SHIFT      (15U)
35603 /*! READ - MDIO read initiation. */
35604 #define ENETC_PF_EMDIO_EMDIO_CTL_READ(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_READ_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_READ_MASK)
35605 
35606 #define ENETC_PF_EMDIO_EMDIO_CTL_BSY_MASK        (0x80000000U)
35607 #define ENETC_PF_EMDIO_EMDIO_CTL_BSY_SHIFT       (31U)
35608 /*! BSY - MDIO busy */
35609 #define ENETC_PF_EMDIO_EMDIO_CTL_BSY(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_BSY_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_BSY_MASK)
35610 /*! @} */
35611 
35612 /*! @name EMDIO_DATA - External MDIO interface data register */
35613 /*! @{ */
35614 
35615 #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_MASK (0xFFFFU)
35616 #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_SHIFT (0U)
35617 /*! MDIO_DATA - 16-bit MDIO data. */
35618 #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_SHIFT)) & ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_MASK)
35619 /*! @} */
35620 
35621 /*! @name EMDIO_ADDR - External MDIO register address register */
35622 /*! @{ */
35623 
35624 #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_MASK   (0xFFFFU)
35625 #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_SHIFT  (0U)
35626 /*! REGADDR - MDIO PHY register address. */
35627 #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_MASK)
35628 /*! @} */
35629 
35630 /*! @name EMDIO_STAT - External MDIO status register */
35631 /*! @{ */
35632 
35633 #define ENETC_PF_EMDIO_EMDIO_STAT_BSY_MASK       (0x1U)
35634 #define ENETC_PF_EMDIO_EMDIO_STAT_BSY_SHIFT      (0U)
35635 /*! BSY - Global MDIO busy */
35636 #define ENETC_PF_EMDIO_EMDIO_STAT_BSY(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_BSY_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_BSY_MASK)
35637 
35638 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_MASK  (0x1F00U)
35639 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_SHIFT (8U)
35640 /*! WHT_LIST - PHY white list */
35641 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_MASK)
35642 
35643 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_MASK (0x8000U)
35644 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_SHIFT (15U)
35645 /*! WHT_LIST_ENA - PHY white list enable */
35646 #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_MASK)
35647 
35648 #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_MASK   (0x70000U)
35649 #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_SHIFT  (16U)
35650 /*! PORT_ID - Port ID */
35651 #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_MASK)
35652 
35653 #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_MASK  (0x80000U)
35654 #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_SHIFT (19U)
35655 /*! REQ_TYPE - Port ID */
35656 #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_MASK)
35657 /*! @} */
35658 
35659 /*! @name PHY_STATUS_CFG - PHY status configuration register */
35660 /*! @{ */
35661 
35662 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_MASK   (0x1U)
35663 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_SHIFT  (0U)
35664 /*! BSY - MDIO busy */
35665 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_MASK)
35666 
35667 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_MASK (0x2U)
35668 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT (1U)
35669 /*! MDIO_RD_ER - MDIO read error */
35670 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_MASK)
35671 
35672 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_MASK (0xFFFF0000U)
35673 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT (16U)
35674 /*! STATUS_INTERVAL - PHY status read interval */
35675 #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_MASK)
35676 /*! @} */
35677 
35678 /*! @name PHY_STATUS_CTL - PHY status control register */
35679 /*! @{ */
35680 
35681 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_MASK (0x1FU)
35682 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_SHIFT (0U)
35683 /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */
35684 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_MASK)
35685 
35686 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_MASK (0x3E0U)
35687 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_SHIFT (5U)
35688 /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */
35689 #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_MASK)
35690 /*! @} */
35691 
35692 /*! @name PHY_STATUS_DATA - PHY status data register */
35693 /*! @{ */
35694 
35695 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_MASK (0xFFFFU)
35696 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_SHIFT (0U)
35697 /*! MDIO_DATA - 16-bit MDIO data */
35698 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_MASK)
35699 
35700 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_MASK (0xFFFF0000U)
35701 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_SHIFT (16U)
35702 /*! CURR_CNT - Current count */
35703 #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_MASK)
35704 /*! @} */
35705 
35706 /*! @name PHY_STATUS_ADDR - PHY status register address register */
35707 /*! @{ */
35708 
35709 #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_MASK (0xFFFFU)
35710 #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_SHIFT (0U)
35711 /*! REGADDR - MDIO PHY register address. Address of the register within the Clause 45 PHY device from which data is to be read. */
35712 #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_MASK)
35713 /*! @} */
35714 
35715 /*! @name PHY_STATUS_EVENT - PHY status event register */
35716 /*! @{ */
35717 
35718 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK (0xFFFFU)
35719 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT (0U)
35720 /*! STATUS_EVENT_HL - Status event high-to-low. Set to 1 if a 1->0 transition on a corresponding data bit has occurred. Write 1 to clear. */
35721 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK)
35722 
35723 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK (0xFFFF0000U)
35724 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT (16U)
35725 /*! STATUS_EVENT_LH - Status event low-to-high. Set to 1 if a 0->1 transition on a corresponding data bit has occurred. Write 1 to clear. */
35726 #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK)
35727 /*! @} */
35728 
35729 /*! @name PHY_STATUS_MASK - PHY status mask register */
35730 /*! @{ */
35731 
35732 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_MASK (0xFFFFU)
35733 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT (0U)
35734 /*! STATUS_MASK_HL - Status high-to-low mask. If set to 1, assert an interrupt if the corresponding event bit is set. */
35735 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_MASK)
35736 
35737 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_MASK (0xFFFF0000U)
35738 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT (16U)
35739 /*! STATUS_MASK_LH - Status mask low-to-high. If set to 1, assert an interrupt if the corresponding event bit is set. */
35740 #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_MASK)
35741 /*! @} */
35742 
35743 /*! @name MDIO_CFG - MDIO configuration register */
35744 /*! @{ */
35745 
35746 #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_MASK   (0x10U)
35747 #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_SHIFT  (4U)
35748 /*! MDIO_MODE - MDIO pin mode */
35749 #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_SHIFT)) & ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_MASK)
35750 
35751 #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_MASK    (0x20U)
35752 #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_SHIFT   (5U)
35753 /*! MDC_MODE - MDC pin mode */
35754 #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_SHIFT)) & ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_MASK)
35755 /*! @} */
35756 
35757 
35758 /*!
35759  * @}
35760  */ /* end of group ENETC_PF_EMDIO_Register_Masks */
35761 
35762 
35763 /* ENETC_PF_EMDIO - Peripheral instance base addresses */
35764 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
35765   /** Peripheral EMDIO_BASE base address */
35766   #define EMDIO_BASE_BASE                          (0x70BA0000u)
35767   /** Peripheral EMDIO_BASE base address */
35768   #define EMDIO_BASE_BASE_NS                       (0x60BA0000u)
35769   /** Peripheral EMDIO_BASE base pointer */
35770   #define EMDIO_BASE                               ((ENETC_PF_EMDIO_Type *)EMDIO_BASE_BASE)
35771   /** Peripheral EMDIO_BASE base pointer */
35772   #define EMDIO_BASE_NS                            ((ENETC_PF_EMDIO_Type *)EMDIO_BASE_BASE_NS)
35773   /** Array initializer of ENETC_PF_EMDIO peripheral base addresses */
35774   #define ENETC_PF_EMDIO_BASE_ADDRS                { EMDIO_BASE_BASE }
35775   /** Array initializer of ENETC_PF_EMDIO peripheral base pointers */
35776   #define ENETC_PF_EMDIO_BASE_PTRS                 { EMDIO_BASE }
35777   /** Array initializer of ENETC_PF_EMDIO peripheral base addresses */
35778   #define ENETC_PF_EMDIO_BASE_ADDRS_NS             { EMDIO_BASE_BASE_NS }
35779   /** Array initializer of ENETC_PF_EMDIO peripheral base pointers */
35780   #define ENETC_PF_EMDIO_BASE_PTRS_NS              { EMDIO_BASE_NS }
35781 #else
35782   /** Peripheral EMDIO_BASE base address */
35783   #define EMDIO_BASE_BASE                          (0x60BA0000u)
35784   /** Peripheral EMDIO_BASE base pointer */
35785   #define EMDIO_BASE                               ((ENETC_PF_EMDIO_Type *)EMDIO_BASE_BASE)
35786   /** Array initializer of ENETC_PF_EMDIO peripheral base addresses */
35787   #define ENETC_PF_EMDIO_BASE_ADDRS                { EMDIO_BASE_BASE }
35788   /** Array initializer of ENETC_PF_EMDIO peripheral base pointers */
35789   #define ENETC_PF_EMDIO_BASE_PTRS                 { EMDIO_BASE }
35790 #endif
35791 
35792 /*!
35793  * @}
35794  */ /* end of group ENETC_PF_EMDIO_Peripheral_Access_Layer */
35795 
35796 
35797 /* ----------------------------------------------------------------------------
35798    -- ENETC_PF_TMR Peripheral Access Layer
35799    ---------------------------------------------------------------------------- */
35800 
35801 /*!
35802  * @addtogroup ENETC_PF_TMR_Peripheral_Access_Layer ENETC_PF_TMR Peripheral Access Layer
35803  * @{
35804  */
35805 
35806 /** ENETC_PF_TMR - Register Layout Typedef */
35807 typedef struct {
35808   __I  uint32_t TMR_ID;                            /**< Module ID Register, offset: 0x0 */
35809        uint8_t RESERVED_0[4];
35810   __I  uint32_t TMR_CAPR;                          /**< Timer Capability Register, offset: 0x8 */
35811        uint8_t RESERVED_1[20];
35812   __I  uint32_t TMR_FRT_L;                         /**< Timer free running time low register, offset: 0x20 */
35813   __I  uint32_t TMR_FRT_H;                         /**< Timer free running time high register, offset: 0x24 */
35814   __I  uint32_t TMR_SRT_L;                         /**< Timer synchronous time low register, offset: 0x28 */
35815   __I  uint32_t TMR_SRT_H;                         /**< Timer synchronous time high register., offset: 0x2C */
35816   __I  uint32_t TMR_DEF_CNT_L;                     /**< Default ns timer counter low register, offset: 0x30 */
35817   __I  uint32_t TMR_DEF_CNT_H;                     /**< Default ns timer counter high register, offset: 0x34 */
35818        uint8_t RESERVED_2[72];
35819   __IO uint32_t TMR_CTRL;                          /**< Timer Control Register, offset: 0x80 */
35820   __IO uint32_t TMR_TEVENT;                        /**< Timer Event Register, offset: 0x84 */
35821   __IO uint32_t TMR_TEMASK;                        /**< Timer event mask register, offset: 0x88 */
35822        uint8_t RESERVED_3[8];
35823   __I  uint32_t TMR_STAT;                          /**< Timer status register, offset: 0x94 */
35824   __IO uint32_t TMR_CNT_L;                         /**< Timer counter low register, offset: 0x98 */
35825   __IO uint32_t TMR_CNT_H;                         /**< Timer counter high register, offset: 0x9C */
35826   __IO uint32_t TMR_ADD;                           /**< Timer addend register, offset: 0xA0 */
35827   __I  uint32_t TMR_ACC;                           /**< Timer accumulator register, offset: 0xA4 */
35828   __IO uint32_t TMR_PRSC;                          /**< Timer prescale register, offset: 0xA8 */
35829   __IO uint32_t TMR_ECTRL;                         /**< Extended timer control register, offset: 0xAC */
35830   __IO uint32_t TMROFF_L;                          /**< Timer offset low register, offset: 0xB0 */
35831   __IO uint32_t TMROFF_H;                          /**< Timer offset high register, offset: 0xB4 */
35832   struct {                                         /* offset: 0xB8, array step: 0x8 */
35833     __IO uint32_t TMR_ALARM_L;                       /**< Alarm 1 time comparator low register..Alarm 2 time comparator low register, array offset: 0xB8, array step: 0x8 */
35834     __IO uint32_t TMR_ALARM_H;                       /**< Alarm 1 time comparator high register..Alarm 2 time comparator high register, array offset: 0xBC, array step: 0x8 */
35835   } TMR_ALARMM[2];
35836        uint8_t RESERVED_4[4];
35837   __IO uint32_t TMR_ALARM_CTRL;                    /**< Timer Alarm Control Register, offset: 0xCC */
35838   __IO uint32_t TMR_FIPER[3];                      /**< Timer 1 fixed interval period register..Timer 3 fixed interval period register, array offset: 0xD0, array step: 0x4 */
35839   __IO uint32_t TMR_FIPER_CTRL;                    /**< Timer FIPER Control Register, offset: 0xDC */
35840   struct {                                         /* offset: 0xE0, array step: 0x8 */
35841     __I  uint32_t TMR_ETTS_L;                        /**< External trigger stamp register, array offset: 0xE0, array step: 0x8 */
35842     __I  uint32_t TMR_ETTS_H;                        /**< External trigger stamp register, array offset: 0xE4, array step: 0x8 */
35843   } TMR_ETTSN[2];
35844   __I  uint32_t TMR_CUR_TIME_L;                    /**< Timer current time low register, offset: 0xF0 */
35845   __I  uint32_t TMR_CUR_TIME_H;                    /**< Timer current time high register, offset: 0xF4 */
35846   __IO uint32_t TMR_PARAM;                         /**< Timer parameter register, offset: 0xF8 */
35847 } ENETC_PF_TMR_Type;
35848 
35849 /* ----------------------------------------------------------------------------
35850    -- ENETC_PF_TMR Register Masks
35851    ---------------------------------------------------------------------------- */
35852 
35853 /*!
35854  * @addtogroup ENETC_PF_TMR_Register_Masks ENETC_PF_TMR Register Masks
35855  * @{
35856  */
35857 
35858 /*! @name TMR_ID - Module ID Register */
35859 /*! @{ */
35860 
35861 #define ENETC_PF_TMR_TMR_ID_REV_MN_MASK          (0xFFU)
35862 #define ENETC_PF_TMR_TMR_ID_REV_MN_SHIFT         (0U)
35863 /*! REV_MN - Minor revision */
35864 #define ENETC_PF_TMR_TMR_ID_REV_MN(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_REV_MN_SHIFT)) & ENETC_PF_TMR_TMR_ID_REV_MN_MASK)
35865 
35866 #define ENETC_PF_TMR_TMR_ID_REV_MJ_MASK          (0xFF00U)
35867 #define ENETC_PF_TMR_TMR_ID_REV_MJ_SHIFT         (8U)
35868 /*! REV_MJ - Major revision */
35869 #define ENETC_PF_TMR_TMR_ID_REV_MJ(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_REV_MJ_SHIFT)) & ENETC_PF_TMR_TMR_ID_REV_MJ_MASK)
35870 
35871 #define ENETC_PF_TMR_TMR_ID_TMR_ID_MASK          (0xFFFF0000U)
35872 #define ENETC_PF_TMR_TMR_ID_TMR_ID_SHIFT         (16U)
35873 /*! TMR_ID - Timer IP ID */
35874 #define ENETC_PF_TMR_TMR_ID_TMR_ID(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_TMR_ID_SHIFT)) & ENETC_PF_TMR_TMR_ID_TMR_ID_MASK)
35875 /*! @} */
35876 
35877 /*! @name TMR_CAPR - Timer Capability Register */
35878 /*! @{ */
35879 
35880 #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722_MASK     (0x1U)
35881 #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722_SHIFT    (0U)
35882 #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_IEEE_1722_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_IEEE_1722_MASK)
35883 
35884 #define ENETC_PF_TMR_TMR_CAPR_ECADJ_MASK         (0x2U)
35885 #define ENETC_PF_TMR_TMR_CAPR_ECADJ_SHIFT        (1U)
35886 #define ENETC_PF_TMR_TMR_CAPR_ECADJ(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_ECADJ_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_ECADJ_MASK)
35887 
35888 #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_MASK (0x4U)
35889 #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_SHIFT (2U)
35890 #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_MASK)
35891 
35892 #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_MASK      (0x10000U)
35893 #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_SHIFT     (16U)
35894 #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_MASK)
35895 /*! @} */
35896 
35897 /*! @name TMR_FRT_L - Timer free running time low register */
35898 /*! @{ */
35899 
35900 #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_MASK    (0xFFFFFFFFU)
35901 #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_SHIFT   (0U)
35902 #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_SHIFT)) & ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_MASK)
35903 /*! @} */
35904 
35905 /*! @name TMR_FRT_H - Timer free running time high register */
35906 /*! @{ */
35907 
35908 #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_MASK    (0xFFFFFFFFU)
35909 #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_SHIFT   (0U)
35910 #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_SHIFT)) & ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_MASK)
35911 /*! @} */
35912 
35913 /*! @name TMR_SRT_L - Timer synchronous time low register */
35914 /*! @{ */
35915 
35916 #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_MASK    (0xFFFFFFFFU)
35917 #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_SHIFT   (0U)
35918 #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_SHIFT)) & ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_MASK)
35919 /*! @} */
35920 
35921 /*! @name TMR_SRT_H - Timer synchronous time high register. */
35922 /*! @{ */
35923 
35924 #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_MASK    (0xFFFFFFFFU)
35925 #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_SHIFT   (0U)
35926 #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_SHIFT)) & ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_MASK)
35927 /*! @} */
35928 
35929 /*! @name TMR_DEF_CNT_L - Default ns timer counter low register */
35930 /*! @{ */
35931 
35932 #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK (0xFFFFFFFFU)
35933 #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT (0U)
35934 #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT)) & ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK)
35935 /*! @} */
35936 
35937 /*! @name TMR_DEF_CNT_H - Default ns timer counter high register */
35938 /*! @{ */
35939 
35940 #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK (0xFFFFFFFFU)
35941 #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT (0U)
35942 #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT)) & ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK)
35943 /*! @} */
35944 
35945 /*! @name TMR_CTRL - Timer Control Register */
35946 /*! @{ */
35947 
35948 #define ENETC_PF_TMR_TMR_CTRL_CK_SEL_MASK        (0x3U)
35949 #define ENETC_PF_TMR_TMR_CTRL_CK_SEL_SHIFT       (0U)
35950 /*! CK_SEL - 1588 timer reference clock source select */
35951 #define ENETC_PF_TMR_TMR_CTRL_CK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_CK_SEL_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_CK_SEL_MASK)
35952 
35953 #define ENETC_PF_TMR_TMR_CTRL_TE_MASK            (0x4U)
35954 #define ENETC_PF_TMR_TMR_CTRL_TE_SHIFT           (2U)
35955 /*! TE - 1588 timer enable */
35956 #define ENETC_PF_TMR_TMR_CTRL_TE(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_TE_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_TE_MASK)
35957 
35958 #define ENETC_PF_TMR_TMR_CTRL_CIPH_MASK          (0x40U)
35959 #define ENETC_PF_TMR_TMR_CTRL_CIPH_SHIFT         (6U)
35960 /*! CIPH - External oscillator input clock phase */
35961 #define ENETC_PF_TMR_TMR_CTRL_CIPH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_CIPH_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_CIPH_MASK)
35962 
35963 #define ENETC_PF_TMR_TMR_CTRL_COPH_MASK          (0x80U)
35964 #define ENETC_PF_TMR_TMR_CTRL_COPH_SHIFT         (7U)
35965 /*! COPH - Generated clock (TMR_GCLK) output phase. */
35966 #define ENETC_PF_TMR_TMR_CTRL_COPH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_COPH_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_COPH_MASK)
35967 
35968 #define ENETC_PF_TMR_TMR_CTRL_ETEP1_MASK         (0x100U)
35969 #define ENETC_PF_TMR_TMR_CTRL_ETEP1_SHIFT        (8U)
35970 /*! ETEP1 - External trigger 1 edge polarity */
35971 #define ENETC_PF_TMR_TMR_CTRL_ETEP1(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ETEP1_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ETEP1_MASK)
35972 
35973 #define ENETC_PF_TMR_TMR_CTRL_ETEP2_MASK         (0x200U)
35974 #define ENETC_PF_TMR_TMR_CTRL_ETEP2_SHIFT        (9U)
35975 /*! ETEP2 - External trigger 2 edge polarity */
35976 #define ENETC_PF_TMR_TMR_CTRL_ETEP2(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ETEP2_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ETEP2_MASK)
35977 
35978 #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE_MASK     (0x8000U)
35979 #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE_SHIFT    (15U)
35980 /*! COMP_MODE - Mode bit to allow atomic writes to TCLK_PERIOD and TMR_ADD */
35981 #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_COMP_MODE_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_COMP_MODE_MASK)
35982 
35983 #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_MASK   (0x3FF0000U)
35984 #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_SHIFT  (16U)
35985 /*! TCLK_PERIOD - 1588 timer reference clock period */
35986 #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_MASK)
35987 
35988 #define ENETC_PF_TMR_TMR_CTRL_PP2L_MASK          (0x4000000U)
35989 #define ENETC_PF_TMR_TMR_CTRL_PP2L_SHIFT         (26U)
35990 /*! PP2L - Fiper2 pulse loop back mode enabled */
35991 #define ENETC_PF_TMR_TMR_CTRL_PP2L(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_PP2L_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_PP2L_MASK)
35992 
35993 #define ENETC_PF_TMR_TMR_CTRL_PP1L_MASK          (0x8000000U)
35994 #define ENETC_PF_TMR_TMR_CTRL_PP1L_SHIFT         (27U)
35995 /*! PP1L - Fiper1 pulse loop back mode enabled */
35996 #define ENETC_PF_TMR_TMR_CTRL_PP1L(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_PP1L_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_PP1L_MASK)
35997 
35998 #define ENETC_PF_TMR_TMR_CTRL_FS_MASK            (0x10000000U)
35999 #define ENETC_PF_TMR_TMR_CTRL_FS_SHIFT           (28U)
36000 /*! FS - FIPER start indication */
36001 #define ENETC_PF_TMR_TMR_CTRL_FS(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_FS_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_FS_MASK)
36002 
36003 #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_MASK    (0x20000000U)
36004 #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_SHIFT   (29U)
36005 /*! SHADOW_DIS - shadow Register disable */
36006 #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_MASK)
36007 
36008 #define ENETC_PF_TMR_TMR_CTRL_ALM2P_MASK         (0x40000000U)
36009 #define ENETC_PF_TMR_TMR_CTRL_ALM2P_SHIFT        (30U)
36010 /*! ALM2P - Alarm2 output polarity */
36011 #define ENETC_PF_TMR_TMR_CTRL_ALM2P(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ALM2P_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ALM2P_MASK)
36012 
36013 #define ENETC_PF_TMR_TMR_CTRL_ALM1P_MASK         (0x80000000U)
36014 #define ENETC_PF_TMR_TMR_CTRL_ALM1P_SHIFT        (31U)
36015 /*! ALM1P - Alarm1 output polarity */
36016 #define ENETC_PF_TMR_TMR_CTRL_ALM1P(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ALM1P_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ALM1P_MASK)
36017 /*! @} */
36018 
36019 /*! @name TMR_TEVENT - Timer Event Register */
36020 /*! @{ */
36021 
36022 #define ENETC_PF_TMR_TMR_TEVENT_PP3EN_MASK       (0x20U)
36023 #define ENETC_PF_TMR_TMR_TEVENT_PP3EN_SHIFT      (5U)
36024 #define ENETC_PF_TMR_TMR_TEVENT_PP3EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP3EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP3EN_MASK)
36025 
36026 #define ENETC_PF_TMR_TMR_TEVENT_PP2EN_MASK       (0x40U)
36027 #define ENETC_PF_TMR_TMR_TEVENT_PP2EN_SHIFT      (6U)
36028 #define ENETC_PF_TMR_TMR_TEVENT_PP2EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP2EN_MASK)
36029 
36030 #define ENETC_PF_TMR_TMR_TEVENT_PP1EN_MASK       (0x80U)
36031 #define ENETC_PF_TMR_TMR_TEVENT_PP1EN_SHIFT      (7U)
36032 #define ENETC_PF_TMR_TMR_TEVENT_PP1EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP1EN_MASK)
36033 
36034 #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN_MASK      (0x10000U)
36035 #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN_SHIFT     (16U)
36036 #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ALM1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ALM1EN_MASK)
36037 
36038 #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN_MASK      (0x20000U)
36039 #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN_SHIFT     (17U)
36040 #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ALM2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ALM2EN_MASK)
36041 
36042 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_MASK  (0x100000U)
36043 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_SHIFT (20U)
36044 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_MASK)
36045 
36046 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_MASK  (0x200000U)
36047 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_SHIFT (21U)
36048 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_MASK)
36049 
36050 #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK      (0x1000000U)
36051 #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN_SHIFT     (24U)
36052 /*! ETS1EN - External trigger 1 new timestamp sample event available */
36053 #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK)
36054 
36055 #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK      (0x2000000U)
36056 #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN_SHIFT     (25U)
36057 /*! ETS2EN - External trigger 2 new timestamp sample event available */
36058 #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK)
36059 
36060 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK   (0x10000000U)
36061 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_SHIFT  (28U)
36062 /*! ETS1_OVEN - External trigger 1 timestamp FIFO Overflow event occurred */
36063 #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK)
36064 
36065 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK   (0x20000000U)
36066 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_SHIFT  (29U)
36067 /*! ETS2_OVEN - External trigger 2 timestamp FIFO Overflow event occurred */
36068 #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK)
36069 /*! @} */
36070 
36071 /*! @name TMR_TEMASK - Timer event mask register */
36072 /*! @{ */
36073 
36074 #define ENETC_PF_TMR_TMR_TEMASK_PP3EN_MASK       (0x20U)
36075 #define ENETC_PF_TMR_TMR_TEMASK_PP3EN_SHIFT      (5U)
36076 #define ENETC_PF_TMR_TMR_TEMASK_PP3EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP3EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP3EN_MASK)
36077 
36078 #define ENETC_PF_TMR_TMR_TEMASK_PP2EN_MASK       (0x40U)
36079 #define ENETC_PF_TMR_TMR_TEMASK_PP2EN_SHIFT      (6U)
36080 #define ENETC_PF_TMR_TMR_TEMASK_PP2EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP2EN_MASK)
36081 
36082 #define ENETC_PF_TMR_TMR_TEMASK_PP1EN_MASK       (0x80U)
36083 #define ENETC_PF_TMR_TMR_TEMASK_PP1EN_SHIFT      (7U)
36084 #define ENETC_PF_TMR_TMR_TEMASK_PP1EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP1EN_MASK)
36085 
36086 #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN_MASK      (0x10000U)
36087 #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN_SHIFT     (16U)
36088 #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ALM1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ALM1EN_MASK)
36089 
36090 #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN_MASK      (0x20000U)
36091 #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN_SHIFT     (17U)
36092 #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ALM2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ALM2EN_MASK)
36093 
36094 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK  (0x100000U)
36095 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_SHIFT (20U)
36096 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK)
36097 
36098 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK  (0x200000U)
36099 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_SHIFT (21U)
36100 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN(x)    (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK)
36101 
36102 #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK      (0x1000000U)
36103 #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN_SHIFT     (24U)
36104 #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK)
36105 
36106 #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK      (0x2000000U)
36107 #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN_SHIFT     (25U)
36108 #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK)
36109 
36110 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_MASK   (0x10000000U)
36111 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_SHIFT  (28U)
36112 #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_MASK)
36113 
36114 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_MASK   (0x20000000U)
36115 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_SHIFT  (29U)
36116 #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN(x)     (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_MASK)
36117 /*! @} */
36118 
36119 /*! @name TMR_STAT - Timer status register */
36120 /*! @{ */
36121 
36122 #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD_MASK      (0x1000000U)
36123 #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD_SHIFT     (24U)
36124 #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_ETS1_VLD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_ETS1_VLD_MASK)
36125 
36126 #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD_MASK      (0x2000000U)
36127 #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD_SHIFT     (25U)
36128 #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_ETS2_VLD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_ETS2_VLD_MASK)
36129 
36130 #define ENETC_PF_TMR_TMR_STAT_RCD_MASK           (0x80000000U)
36131 #define ENETC_PF_TMR_TMR_STAT_RCD_SHIFT          (31U)
36132 /*! RCD - Timer Reference Clock Detected
36133  *  0b0..Reference Clock has not been detected as active. Registers in timer clock domain are not allowed to be
36134  *       accessed; reads return 0, writes are ignored.
36135  *  0b1..Reference Clock has been detected as active. Registers in timer clock domain are allowed to be accessed.
36136  */
36137 #define ENETC_PF_TMR_TMR_STAT_RCD(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_RCD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_RCD_MASK)
36138 /*! @} */
36139 
36140 /*! @name TMR_CNT_L - Timer counter low register */
36141 /*! @{ */
36142 
36143 #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_MASK    (0xFFFFFFFFU)
36144 #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_SHIFT   (0U)
36145 /*! TMR_CNT_L - Timer counter register. */
36146 #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_SHIFT)) & ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_MASK)
36147 /*! @} */
36148 
36149 /*! @name TMR_CNT_H - Timer counter high register */
36150 /*! @{ */
36151 
36152 #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_MASK    (0xFFFFFFFFU)
36153 #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_SHIFT   (0U)
36154 /*! TMR_CNT_H - Timer counter register. */
36155 #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_SHIFT)) & ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_MASK)
36156 /*! @} */
36157 
36158 /*! @name TMR_ADD - Timer addend register */
36159 /*! @{ */
36160 
36161 #define ENETC_PF_TMR_TMR_ADD_ADDEND_MASK         (0xFFFFFFFFU)
36162 #define ENETC_PF_TMR_TMR_ADD_ADDEND_SHIFT        (0U)
36163 /*! ADDEND - Timer addend. */
36164 #define ENETC_PF_TMR_TMR_ADD_ADDEND(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ADD_ADDEND_SHIFT)) & ENETC_PF_TMR_TMR_ADD_ADDEND_MASK)
36165 /*! @} */
36166 
36167 /*! @name TMR_ACC - Timer accumulator register */
36168 /*! @{ */
36169 
36170 #define ENETC_PF_TMR_TMR_ACC_TMR_ACC_MASK        (0xFFFFFFFFU)
36171 #define ENETC_PF_TMR_TMR_ACC_TMR_ACC_SHIFT       (0U)
36172 /*! TMR_ACC - 32-bit timer accumulator register */
36173 #define ENETC_PF_TMR_TMR_ACC_TMR_ACC(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ACC_TMR_ACC_SHIFT)) & ENETC_PF_TMR_TMR_ACC_TMR_ACC_MASK)
36174 /*! @} */
36175 
36176 /*! @name TMR_PRSC - Timer prescale register */
36177 /*! @{ */
36178 
36179 #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_MASK      (0xFFFFU)
36180 #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_SHIFT     (0U)
36181 /*! PRSC_OCK - Output clock division prescale factor. */
36182 #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_SHIFT)) & ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_MASK)
36183 /*! @} */
36184 
36185 /*! @name TMR_ECTRL - Extended timer control register */
36186 /*! @{ */
36187 
36188 #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_MASK     (0xFU)
36189 #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_SHIFT    (0U)
36190 /*! ETFF_THR - External trigger FIFO threshold. */
36191 #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_SHIFT)) & ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_MASK)
36192 /*! @} */
36193 
36194 /*! @name TMROFF_L - Timer offset low register */
36195 /*! @{ */
36196 
36197 #define ENETC_PF_TMR_TMROFF_L_TMROFF_L_MASK      (0xFFFFFFFFU)
36198 #define ENETC_PF_TMR_TMROFF_L_TMROFF_L_SHIFT     (0U)
36199 /*! TMROFF_L - Offset value of the clock counter. */
36200 #define ENETC_PF_TMR_TMROFF_L_TMROFF_L(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMROFF_L_TMROFF_L_SHIFT)) & ENETC_PF_TMR_TMROFF_L_TMROFF_L_MASK)
36201 /*! @} */
36202 
36203 /*! @name TMROFF_H - Timer offset high register */
36204 /*! @{ */
36205 
36206 #define ENETC_PF_TMR_TMROFF_H_TMROFF_H_MASK      (0xFFFFFFFFU)
36207 #define ENETC_PF_TMR_TMROFF_H_TMROFF_H_SHIFT     (0U)
36208 /*! TMROFF_H - Offset value of the clock counter. */
36209 #define ENETC_PF_TMR_TMROFF_H_TMROFF_H(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMROFF_H_TMROFF_H_SHIFT)) & ENETC_PF_TMR_TMROFF_H_TMROFF_H_MASK)
36210 /*! @} */
36211 
36212 /*! @name TMR_ALARM_L - Alarm 1 time comparator low register..Alarm 2 time comparator low register */
36213 /*! @{ */
36214 
36215 #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_MASK    (0xFFFFFFFFU)
36216 #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_SHIFT   (0U)
36217 /*! ALARM_L - Alarm time comparator register. */
36218 #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_MASK)
36219 /*! @} */
36220 
36221 /* The count of ENETC_PF_TMR_TMR_ALARM_L */
36222 #define ENETC_PF_TMR_TMR_ALARM_L_COUNT           (2U)
36223 
36224 /*! @name TMR_ALARM_H - Alarm 1 time comparator high register..Alarm 2 time comparator high register */
36225 /*! @{ */
36226 
36227 #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_MASK    (0xFFFFFFFFU)
36228 #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_SHIFT   (0U)
36229 /*! ALARM_H - Alarm time comparator register. */
36230 #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_MASK)
36231 /*! @} */
36232 
36233 /* The count of ENETC_PF_TMR_TMR_ALARM_H */
36234 #define ENETC_PF_TMR_TMR_ALARM_H_COUNT           (2U)
36235 
36236 /*! @name TMR_ALARM_CTRL - Timer Alarm Control Register */
36237 /*! @{ */
36238 
36239 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_MASK (0x1FU)
36240 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_SHIFT (0U)
36241 /*! ALARM1_PW - ALARM 1 pulse width selector */
36242 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_MASK)
36243 
36244 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_MASK     (0x80U)
36245 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_SHIFT    (7U)
36246 /*! PG1 - Alarm1 pulse generation time */
36247 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_MASK)
36248 
36249 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_MASK (0x1F00U)
36250 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_SHIFT (8U)
36251 /*! ALARM2_PW - ALARM 2 pulse width selector */
36252 #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_MASK)
36253 
36254 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_MASK     (0x8000U)
36255 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_SHIFT    (15U)
36256 /*! PG2 - Alarm2 pulse generation time */
36257 #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_MASK)
36258 /*! @} */
36259 
36260 /*! @name TMR_FIPER - Timer 1 fixed interval period register..Timer 3 fixed interval period register */
36261 /*! @{ */
36262 
36263 #define ENETC_PF_TMR_TMR_FIPER_FIPER_MASK        (0xFFFFFFFFU)
36264 #define ENETC_PF_TMR_TMR_FIPER_FIPER_SHIFT       (0U)
36265 /*! FIPER - Fixed Interval Pulse Period */
36266 #define ENETC_PF_TMR_TMR_FIPER_FIPER(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_FIPER_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_FIPER_MASK)
36267 /*! @} */
36268 
36269 /* The count of ENETC_PF_TMR_TMR_FIPER */
36270 #define ENETC_PF_TMR_TMR_FIPER_COUNT             (3U)
36271 
36272 /*! @name TMR_FIPER_CTRL - Timer FIPER Control Register */
36273 /*! @{ */
36274 
36275 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_MASK (0x1FU)
36276 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_SHIFT (0U)
36277 /*! FIPER1_PW - FIPER 1 pulse width selection */
36278 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_MASK)
36279 
36280 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_MASK     (0x40U)
36281 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_SHIFT    (6U)
36282 /*! PG1 - FIPER1 pulse generation select */
36283 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_MASK)
36284 
36285 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_MASK (0x80U)
36286 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT (7U)
36287 /*! FIPER1_DIS - FIPER1 disable */
36288 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_MASK)
36289 
36290 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_MASK (0x1F00U)
36291 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_SHIFT (8U)
36292 /*! FIPER2_PW - FIPER 2 pulse width selection */
36293 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_MASK)
36294 
36295 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_MASK     (0x4000U)
36296 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_SHIFT    (14U)
36297 /*! PG2 - FIPER2 pulse generation time */
36298 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_MASK)
36299 
36300 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_MASK (0x8000U)
36301 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT (15U)
36302 /*! FIPER2_DIS - FIPER2 disable */
36303 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_MASK)
36304 
36305 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_MASK (0x1F0000U)
36306 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_SHIFT (16U)
36307 /*! FIPER3_PW - FIPER 3 pulse width selection */
36308 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_MASK)
36309 
36310 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_MASK     (0x400000U)
36311 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_SHIFT    (22U)
36312 /*! PG3 - FIPER3 pulse generation time */
36313 #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_MASK)
36314 
36315 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_MASK (0x800000U)
36316 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT (23U)
36317 /*! FIPER3_DIS - FIPER3 disable */
36318 #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_MASK)
36319 /*! @} */
36320 
36321 /*! @name TMR_ETTS_L - External trigger stamp register */
36322 /*! @{ */
36323 
36324 #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_MASK      (0xFFFFFFFFU)
36325 #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_SHIFT     (0U)
36326 #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_SHIFT)) & ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_MASK)
36327 /*! @} */
36328 
36329 /* The count of ENETC_PF_TMR_TMR_ETTS_L */
36330 #define ENETC_PF_TMR_TMR_ETTS_L_COUNT            (2U)
36331 
36332 /*! @name TMR_ETTS_H - External trigger stamp register */
36333 /*! @{ */
36334 
36335 #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_MASK      (0xFFFFFFFFU)
36336 #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_SHIFT     (0U)
36337 #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_SHIFT)) & ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_MASK)
36338 /*! @} */
36339 
36340 /* The count of ENETC_PF_TMR_TMR_ETTS_H */
36341 #define ENETC_PF_TMR_TMR_ETTS_H_COUNT            (2U)
36342 
36343 /*! @name TMR_CUR_TIME_L - Timer current time low register */
36344 /*! @{ */
36345 
36346 #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK (0xFFFFFFFFU)
36347 #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT (0U)
36348 #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT)) & ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK)
36349 /*! @} */
36350 
36351 /*! @name TMR_CUR_TIME_H - Timer current time high register */
36352 /*! @{ */
36353 
36354 #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK (0xFFFFFFFFU)
36355 #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT (0U)
36356 #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT)) & ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK)
36357 /*! @} */
36358 
36359 /*! @name TMR_PARAM - Timer parameter register */
36360 /*! @{ */
36361 
36362 #define ENETC_PF_TMR_TMR_PARAM_SYNC_MASK         (0x1U)
36363 #define ENETC_PF_TMR_TMR_PARAM_SYNC_SHIFT        (0U)
36364 /*! SYNC - Timer synchronization */
36365 #define ENETC_PF_TMR_TMR_PARAM_SYNC(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PARAM_SYNC_SHIFT)) & ENETC_PF_TMR_TMR_PARAM_SYNC_MASK)
36366 
36367 #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_MASK    (0xFFFFFFFEU)
36368 #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_SHIFT   (1U)
36369 /*! PARAM_VAL - User specific parameter values */
36370 #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_SHIFT)) & ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_MASK)
36371 /*! @} */
36372 
36373 
36374 /*!
36375  * @}
36376  */ /* end of group ENETC_PF_TMR_Register_Masks */
36377 
36378 
36379 /* ENETC_PF_TMR - Peripheral instance base addresses */
36380 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
36381   /** Peripheral TMR0_BASE base address */
36382   #define TMR0_BASE_BASE                           (0x70B80000u)
36383   /** Peripheral TMR0_BASE base address */
36384   #define TMR0_BASE_BASE_NS                        (0x60B80000u)
36385   /** Peripheral TMR0_BASE base pointer */
36386   #define TMR0_BASE                                ((ENETC_PF_TMR_Type *)TMR0_BASE_BASE)
36387   /** Peripheral TMR0_BASE base pointer */
36388   #define TMR0_BASE_NS                             ((ENETC_PF_TMR_Type *)TMR0_BASE_BASE_NS)
36389   /** Array initializer of ENETC_PF_TMR peripheral base addresses */
36390   #define ENETC_PF_TMR_BASE_ADDRS                  { TMR0_BASE_BASE }
36391   /** Array initializer of ENETC_PF_TMR peripheral base pointers */
36392   #define ENETC_PF_TMR_BASE_PTRS                   { TMR0_BASE }
36393   /** Array initializer of ENETC_PF_TMR peripheral base addresses */
36394   #define ENETC_PF_TMR_BASE_ADDRS_NS               { TMR0_BASE_BASE_NS }
36395   /** Array initializer of ENETC_PF_TMR peripheral base pointers */
36396   #define ENETC_PF_TMR_BASE_PTRS_NS                { TMR0_BASE_NS }
36397 #else
36398   /** Peripheral TMR0_BASE base address */
36399   #define TMR0_BASE_BASE                           (0x60B80000u)
36400   /** Peripheral TMR0_BASE base pointer */
36401   #define TMR0_BASE                                ((ENETC_PF_TMR_Type *)TMR0_BASE_BASE)
36402   /** Array initializer of ENETC_PF_TMR peripheral base addresses */
36403   #define ENETC_PF_TMR_BASE_ADDRS                  { TMR0_BASE_BASE }
36404   /** Array initializer of ENETC_PF_TMR peripheral base pointers */
36405   #define ENETC_PF_TMR_BASE_PTRS                   { TMR0_BASE }
36406 #endif
36407 
36408 /*!
36409  * @}
36410  */ /* end of group ENETC_PF_TMR_Peripheral_Access_Layer */
36411 
36412 
36413 /* ----------------------------------------------------------------------------
36414    -- ENETC_SI Peripheral Access Layer
36415    ---------------------------------------------------------------------------- */
36416 
36417 /*!
36418  * @addtogroup ENETC_SI_Peripheral_Access_Layer ENETC_SI Peripheral Access Layer
36419  * @{
36420  */
36421 
36422 /** ENETC_SI - Register Layout Typedef */
36423 typedef struct {
36424   __IO uint32_t SIMR;                              /**< Station interface mode register, offset: 0x0 */
36425   __I  uint32_t SISR;                              /**< Station interface status register, offset: 0x4 */
36426        uint8_t RESERVED_0[16];
36427   __I  uint32_t SICTR[2];                          /**< Station interface current time register 0..Station interface current time register 1, array offset: 0x18, array step: 0x4 */
36428   __I  uint32_t SIPCAPR0;                          /**< Station interface port capability register 0, offset: 0x20 */
36429   __I  uint32_t SIPCAPR1;                          /**< Station interface port capability register 1, offset: 0x24 */
36430        uint8_t RESERVED_1[8];
36431   __I  uint32_t SITSR;                             /**< Station interface timer status register, offset: 0x30, available only on: ENETC0_SI0, ENETC1_SI0 (missing on ENETC1_SI1) */
36432        uint8_t RESERVED_2[4];
36433   __IO uint32_t SIRBGCR;                           /**< Station interface receive BDR group control register, offset: 0x38 */
36434        uint8_t RESERVED_3[4];
36435   __IO uint32_t SIBCAR;                            /**< Station interface buffer cache attribute register, offset: 0x40 */
36436   __IO uint32_t SIMCAR;                            /**< Station interface message cache attribute register, offset: 0x44, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36437   __IO uint32_t SICCAR;                            /**< Station interface command cache attribute register, offset: 0x48 */
36438        uint8_t RESERVED_4[52];
36439   __I  uint32_t SIPMAR0;                           /**< Station interface primary MAC address register 0, offset: 0x80 */
36440   __I  uint32_t SIPMAR1;                           /**< Station interface primary MAC address register 1, offset: 0x84 */
36441        uint8_t RESERVED_5[8];
36442   __I  uint32_t SICVLANR1;                         /**< Station interface custom VLAN register 1, offset: 0x90 */
36443   __I  uint32_t SICVLANR2;                         /**< Station interface custom VLAN register 2, offset: 0x94 */
36444        uint8_t RESERVED_6[104];
36445   __IO uint32_t SIVLANIPVMR0;                      /**< Station interface VLAN to IPV mapping register 0, offset: 0x100 */
36446   __IO uint32_t SIVLANIPVMR1;                      /**< Station interface VLAN to IPV mapping register 1, offset: 0x104 */
36447        uint8_t RESERVED_7[72];
36448   __IO uint32_t SIIPVBDRMR0;                       /**< Station interface IPV to ring mapping register, offset: 0x150 */
36449        uint8_t RESERVED_8[176];
36450   union {                                          /* offset: 0x204 */
36451     struct {                                         /* offset: 0x204 */
36452       __IO uint32_t PSIMSGRR;                          /**< Physical station interface message receive register, offset: 0x204, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36453       __IO uint32_t PSIMSGSR;                          /**< Physical station interface message send register, offset: 0x208, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36454            uint8_t RESERVED_0[4];
36455       struct {                                         /* offset: 0x210, array step: 0x8 */
36456         __IO uint32_t PSIVMSGRCVAR0;                     /**< PSI VSI 1 message receive address register 0, array offset: 0x210, array step: 0x8, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36457         __IO uint32_t PSIVMSGRCVAR1;                     /**< PSI VSI 1 message receive address register 1, array offset: 0x214, array step: 0x8, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36458       } VSI_NUM[1];
36459     } PSI_A;
36460     struct {                                         /* offset: 0x204 */
36461       __I  uint32_t VSIMSGSR;                          /**< Virtual station interface message send register, offset: 0x204, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36462       __I  uint32_t VSIMSGRR;                          /**< Virtual station interface message receive register, offset: 0x208, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36463            uint8_t RESERVED_0[4];
36464       __IO uint32_t VSIMSGSNDAR0;                      /**< Virtual station interface message send register 0, offset: 0x210, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36465       __IO uint32_t VSIMSGSNDAR1;                      /**< Virtual station interface message send address register 1, offset: 0x214, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36466     } VSI_A;
36467   };
36468        uint8_t RESERVED_9[232];
36469   __I  uint32_t SIROCT0;                           /**< Station interface receive octets counter (ifInOctets) 0, offset: 0x300 */
36470   __I  uint32_t SIROCT1;                           /**< Station interface receive octets counter (ifInOctets) 1, offset: 0x304 */
36471   __I  uint32_t SIRFRM0;                           /**< Station interface receive frame counter (aFrameReceivedOK) 0, offset: 0x308 */
36472   __I  uint32_t SIRFRM1;                           /**< Station interface receive frame counter (aFrameReceivedOK) 1, offset: 0x30C */
36473   __I  uint32_t SIRUCA0;                           /**< Station interface receive unicast frame counter (ifInUcastPkts) 0, offset: 0x310 */
36474   __I  uint32_t SIRUCA1;                           /**< Station interface receive unicast frame counter (ifInUcastPkts) 1, offset: 0x314 */
36475   __I  uint32_t SIRMCA0;                           /**< Station interface receive multicast frame counter (ifInMulticastPkts) 0, offset: 0x318 */
36476   __I  uint32_t SIRMCA1;                           /**< Station interface receive multicast frame counter (ifInMulticastPkts) 1, offset: 0x31C */
36477   __I  uint32_t SITOCT0;                           /**< Station interface transmit octets counter (ifOutOctets) 0, offset: 0x320 */
36478   __I  uint32_t SITOCT1;                           /**< Station interface transmit octets counter (ifOutOctets) 1, offset: 0x324 */
36479   __I  uint32_t SITFRM0;                           /**< Station interface transmit frame counter (aFrameTransmittedOK) 0, offset: 0x328 */
36480   __I  uint32_t SITFRM1;                           /**< Station interface transmit frame counter (aFrameTransmittedOK) 1, offset: 0x32C */
36481   __I  uint32_t SITUCA0;                           /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 0, offset: 0x330 */
36482   __I  uint32_t SITUCA1;                           /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 1, offset: 0x334 */
36483   __I  uint32_t SITMCA0;                           /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 0, offset: 0x338 */
36484   __I  uint32_t SITMCA1;                           /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 1, offset: 0x33C */
36485        uint8_t RESERVED_10[176];
36486   __I  uint32_t SIBLPR[2];                         /**< Station interface boot loader parameter register 0..Station interface boot loader parameter register 1, array offset: 0x3F0, array step: 0x4, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36487        uint8_t RESERVED_11[1032];
36488   __IO uint32_t SICBDRMR;                          /**< Station interface command BDR mode register, offset: 0x800 */
36489   __I  uint32_t SICBDRSR;                          /**< Station interface command BDR status register, offset: 0x804 */
36490        uint8_t RESERVED_12[8];
36491   __IO uint32_t SICBDRBAR0;                        /**< Station interface command BDR base address register 0, offset: 0x810 */
36492   __IO uint32_t SICBDRBAR1;                        /**< Station interface command BDR base address register 1, offset: 0x814 */
36493   __IO uint32_t SICBDRPIR;                         /**< Station interface command BDR producer index register, offset: 0x818 */
36494   __IO uint32_t SICBDRCIR;                         /**< Station interface command BDR consumer index register, offset: 0x81C */
36495   __IO uint32_t SICBDRLENR;                        /**< Station interface command BDR length register, offset: 0x820 */
36496        uint8_t RESERVED_13[124];
36497   __IO uint32_t SICBDRIER;                         /**< Station interface command BDR interrupt enable register, offset: 0x8A0 */
36498   __IO uint32_t SICBDRIDR;                         /**< Station interface command BDR interrupt detect register, offset: 0x8A4 */
36499        uint8_t RESERVED_14[88];
36500   __I  uint32_t SICAPR0;                           /**< Station interface capability register 0, offset: 0x900 */
36501   __I  uint32_t SICAPR1;                           /**< Station interface capability register 1, offset: 0x904 */
36502   __I  uint32_t SICAPR2;                           /**< Station interface capability register 2, offset: 0x908 */
36503        uint8_t RESERVED_15[244];
36504   union {                                          /* offset: 0xA00 */
36505     struct {                                         /* offset: 0xA00 */
36506       __IO uint32_t PSIIER;                            /**< Physical station interface interrupt enable register, offset: 0xA00, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36507            uint8_t RESERVED_0[4];
36508       __IO uint32_t PSIIDR;                            /**< Physical station interface interrupt detect register, offset: 0xA08, available only on: ENETC1_SI0 (missing on ENETC0_SI0, ENETC1_SI1) */
36509     } PSI;
36510     struct {                                         /* offset: 0xA00 */
36511       __IO uint32_t VSIIER;                            /**< Virtual station interface interrupt enable register, offset: 0xA00, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36512            uint8_t RESERVED_0[4];
36513       __IO uint32_t VSIIDR;                            /**< Virtual station interface interrupt detect register, offset: 0xA08, available only on: ENETC1_SI1 (missing on ENETC0_SI0, ENETC1_SI0) */
36514     } VSI;
36515   };
36516        uint8_t RESERVED_16[12];
36517   __IO uint32_t SITXIDR0;                          /**< Station interface transmit interrupt detect register 0, offset: 0xA18 */
36518        uint8_t RESERVED_17[12];
36519   __IO uint32_t SIRXIDR0;                          /**< Station interface receive interrupt detect register 0, offset: 0xA28 */
36520        uint8_t RESERVED_18[4];
36521   __IO uint32_t SIMSIVR;                           /**< Station interface MSI-X vector register, offset: 0xA30, available only on: ENETC1_SI0, ENETC1_SI1 (missing on ENETC0_SI0) */
36522   __IO uint32_t SICMSIVR;                          /**< Station interface command MSI-X vector register, offset: 0xA34 */
36523        uint8_t RESERVED_19[8];
36524   __IO uint32_t SITMRIER;                          /**< Station interface timer interrupt enable register, offset: 0xA40 */
36525   __IO uint32_t SITMRIDR;                          /**< Station interface timer interrupt detect register, offset: 0xA44 */
36526        uint8_t RESERVED_20[4];
36527   __IO uint32_t SITMRMSIVR;                        /**< Station interface timer MSI-X vector register, offset: 0xA4C */
36528        uint8_t RESERVED_21[176];
36529   __IO uint32_t SIMSITRVR[10];                     /**< Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 9 vector register, array offset: 0xB00, array step: 0x4, irregular array, not all indices are valid */
36530        uint8_t RESERVED_22[88];
36531   __IO uint32_t SIMSIRRVR[10];                     /**< Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 9 vector register, array offset: 0xB80, array step: 0x4, irregular array, not all indices are valid */
36532        uint8_t RESERVED_23[600];
36533   __IO uint32_t SICMECR;                           /**< Station interface correctable memory error configuration register, offset: 0xE00 */
36534   __IO uint32_t SICMESR;                           /**< Station interface correctable memory error status register, offset: 0xE04 */
36535        uint8_t RESERVED_24[4];
36536   __I  uint32_t SICMECTR;                          /**< Station interface correctable memory error count register, offset: 0xE0C */
36537   __IO uint32_t SIUPECR;                           /**< Station interface uncorrectable programming error configuration register, offset: 0xE10 */
36538   __IO uint32_t SIUPESR;                           /**< Station interface uncorrectable programming error status register, offset: 0xE14 */
36539        uint8_t RESERVED_25[4];
36540   __I  uint32_t SIUPECTR;                          /**< Station interface uncorrectable programming error count register, offset: 0xE1C */
36541   __IO uint32_t SIUNSBECR;                         /**< Station interface uncorrectable non-fatal system bus error configuration register, offset: 0xE20 */
36542   __IO uint32_t SIUNSBESR;                         /**< Station interface uncorrectable non-fatal system bus error status register, offset: 0xE24 */
36543        uint8_t RESERVED_26[4];
36544   __I  uint32_t SIUNSBECTR;                        /**< Station interface uncorrectable non-fatal system bus error count register, offset: 0xE2C */
36545   __IO uint32_t SIUFSBECR;                         /**< Station interface uncorrectable fatal system bus error configuration register, offset: 0xE30 */
36546   __IO uint32_t SIUFSBESR;                         /**< Station interface uncorrectable fatal system bus error status register, offset: 0xE34 */
36547        uint8_t RESERVED_27[8];
36548   __IO uint32_t SIUNMECR;                          /**< Station interface uncorrectable non-fatal memory error configuration register, offset: 0xE40 */
36549   __IO uint32_t SIUNMESR0;                         /**< Station interface uncorrectable non-fatal memory error status register 0, offset: 0xE44 */
36550   __I  uint32_t SIUNMESR1;                         /**< Station interface uncorrectable non-fatal memory error status register 1, offset: 0xE48 */
36551   __I  uint32_t SIUNMECTR;                         /**< Station interface uncorrectable non-fatal memory error count register, offset: 0xE4C */
36552   __IO uint32_t SIUFMECR;                          /**< Station interface uncorrectable fatal memory error configuration register, offset: 0xE50 */
36553   __IO uint32_t SIUFMESR0;                         /**< Station interface uncorrectable fatal memory error status register 0, offset: 0xE54 */
36554   __I  uint32_t SIUFMESR1;                         /**< Station interface uncorrectable fatal memory error status register 1, offset: 0xE58 */
36555        uint8_t RESERVED_28[420];
36556   __I  uint32_t SIMAFTCAPR;                        /**< Station interface MAC address filter table capability register, offset: 0x1000 */
36557        uint8_t RESERVED_29[252];
36558   __I  uint32_t SIVFTCAPR;                         /**< Station interface VLAN filter table capability register, offset: 0x1100 */
36559        uint8_t RESERVED_30[28412];
36560   struct {                                         /* offset: 0x8000, array step: 0x200 */
36561     __IO uint32_t TBMR;                              /**< Tx BDR 0 mode register..Tx BDR 9 mode register, array offset: 0x8000, array step: 0x200, irregular array, not all indices are valid */
36562     __IO uint32_t TBSR;                              /**< Tx BDR 0 status register..Tx BDR 9 status register, array offset: 0x8004, array step: 0x200, irregular array, not all indices are valid */
36563          uint8_t RESERVED_0[8];
36564     __IO uint32_t TBBAR0;                            /**< Tx BDR 0 base address register 0..Tx BDR 9 base address register 0, array offset: 0x8010, array step: 0x200, irregular array, not all indices are valid */
36565     __IO uint32_t TBBAR1;                            /**< Tx BDR 0 base address register 1..Tx BDR 9 base address register 1, array offset: 0x8014, array step: 0x200, irregular array, not all indices are valid */
36566     __IO uint32_t TBPIR;                             /**< Tx BDR 0 producer index register..Tx BDR 9 producer index register, array offset: 0x8018, array step: 0x200, irregular array, not all indices are valid */
36567     __IO uint32_t TBCIR;                             /**< Tx BDR 0 consumer index register..Tx BDR 9 consumer index register, array offset: 0x801C, array step: 0x200, irregular array, not all indices are valid */
36568     __IO uint32_t TBLENR;                            /**< Tx BDR 0 length register..Tx BDR 9 length register, array offset: 0x8020, array step: 0x200, irregular array, not all indices are valid */
36569          uint8_t RESERVED_1[124];
36570     __IO uint32_t TBIER;                             /**< Tx BDR 0 interrupt enable register..Tx BDR 9 interrupt enable register, array offset: 0x80A0, array step: 0x200, irregular array, not all indices are valid */
36571     __I  uint32_t TBIDR;                             /**< Tx BDR 0 interrupt detect register..Tx BDR 9 interrupt detect register, array offset: 0x80A4, array step: 0x200, irregular array, not all indices are valid */
36572     __IO uint32_t TBICR0;                            /**< Tx BDR 0 interrupt coalescing register 0..Tx BDR 9 interrupt coalescing register 0, array offset: 0x80A8, array step: 0x200, irregular array, not all indices are valid */
36573     __IO uint32_t TBICR1;                            /**< Tx BDR 0 interrupt coalescing register 1..Tx BDR 9 interrupt coalescing register 1, array offset: 0x80AC, array step: 0x200, irregular array, not all indices are valid */
36574          uint8_t RESERVED_2[80];
36575     __IO uint32_t RBMR;                              /**< Rx BDR 0 mode register..Rx BDR 9 mode register, array offset: 0x8100, array step: 0x200, irregular array, not all indices are valid */
36576     __IO uint32_t RBSR;                              /**< Rx BDR 0 status register..Rx BDR 9 status register, array offset: 0x8104, array step: 0x200, irregular array, not all indices are valid */
36577     __IO uint32_t RBBSR;                             /**< Rx BDR 0 buffer size register..Rx BDR 9 buffer size register, array offset: 0x8108, array step: 0x200, irregular array, not all indices are valid */
36578     __IO uint32_t RBCIR;                             /**< Rx BDR 0 consumer index register..Rx BDR 9 consumer index register, array offset: 0x810C, array step: 0x200, irregular array, not all indices are valid */
36579     __IO uint32_t RBBAR0;                            /**< Rx BDR 0 base address register 0..Rx BDR 9 base address register 0, array offset: 0x8110, array step: 0x200, irregular array, not all indices are valid */
36580     __IO uint32_t RBBAR1;                            /**< Rx BDR 0 base address register 1..Rx BDR 9 base address register 1, array offset: 0x8114, array step: 0x200, irregular array, not all indices are valid */
36581     __IO uint32_t RBPIR;                             /**< Rx BDR 0 producer index register..Rx BDR 9 producer index register, array offset: 0x8118, array step: 0x200, irregular array, not all indices are valid */
36582          uint8_t RESERVED_3[4];
36583     __IO uint32_t RBLENR;                            /**< Rx BDR 0 length register..Rx BDR 9 length register, array offset: 0x8120, array step: 0x200, irregular array, not all indices are valid */
36584          uint8_t RESERVED_4[92];
36585     __I  uint32_t RBDCR;                             /**< Rx BDR 0 drop count register..Rx BDR 9 drop count register, array offset: 0x8180, array step: 0x200, irregular array, not all indices are valid */
36586          uint8_t RESERVED_5[28];
36587     __IO uint32_t RBIER;                             /**< Rx BDR 0 interrupt enable register..Rx BDR 9 interrupt enable register, array offset: 0x81A0, array step: 0x200, irregular array, not all indices are valid */
36588     __I  uint32_t RBIDR;                             /**< Rx BDR 0 interrupt detect register..Rx BDR 9 interrupt detect register, array offset: 0x81A4, array step: 0x200, irregular array, not all indices are valid */
36589     __IO uint32_t RBICR0;                            /**< Rx BDR 0 interrupt coalescing register 0..Rx BDR 9 interrupt coalescing register 0, array offset: 0x81A8, array step: 0x200, irregular array, not all indices are valid */
36590     __IO uint32_t RBICR1;                            /**< Rx BDR 0 interrupt coalescing register 1..Rx BDR 9 interrupt coalescing register 1, array offset: 0x81AC, array step: 0x200, irregular array, not all indices are valid */
36591          uint8_t RESERVED_6[80];
36592   } BDR[10];
36593 } ENETC_SI_Type;
36594 
36595 /* ----------------------------------------------------------------------------
36596    -- ENETC_SI Register Masks
36597    ---------------------------------------------------------------------------- */
36598 
36599 /*!
36600  * @addtogroup ENETC_SI_Register_Masks ENETC_SI Register Masks
36601  * @{
36602  */
36603 
36604 /*! @name SIMR - Station interface mode register */
36605 /*! @{ */
36606 
36607 #define ENETC_SI_SIMR_RSSE_MASK                  (0x1U)
36608 #define ENETC_SI_SIMR_RSSE_SHIFT                 (0U)
36609 #define ENETC_SI_SIMR_RSSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RSSE_SHIFT)) & ENETC_SI_SIMR_RSSE_MASK)
36610 
36611 #define ENETC_SI_SIMR_RNUM_MASK                  (0x2U)
36612 #define ENETC_SI_SIMR_RNUM_SHIFT                 (1U)
36613 #define ENETC_SI_SIMR_RNUM(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNUM_SHIFT)) & ENETC_SI_SIMR_RNUM_MASK)
36614 
36615 #define ENETC_SI_SIMR_RNMM_MASK                  (0x4U)
36616 #define ENETC_SI_SIMR_RNMM_SHIFT                 (2U)
36617 #define ENETC_SI_SIMR_RNMM(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNMM_SHIFT)) & ENETC_SI_SIMR_RNMM_MASK)
36618 
36619 #define ENETC_SI_SIMR_RNBM_MASK                  (0x8U)
36620 #define ENETC_SI_SIMR_RNBM_SHIFT                 (3U)
36621 #define ENETC_SI_SIMR_RNBM(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNBM_SHIFT)) & ENETC_SI_SIMR_RNBM_MASK)
36622 
36623 #define ENETC_SI_SIMR_V2IPVE_MASK                (0x10U)
36624 #define ENETC_SI_SIMR_V2IPVE_SHIFT               (4U)
36625 #define ENETC_SI_SIMR_V2IPVE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_V2IPVE_SHIFT)) & ENETC_SI_SIMR_V2IPVE_MASK)
36626 
36627 #define ENETC_SI_SIMR_DEFAULT_RX_GROUP_MASK      (0x10000U)
36628 #define ENETC_SI_SIMR_DEFAULT_RX_GROUP_SHIFT     (16U)
36629 #define ENETC_SI_SIMR_DEFAULT_RX_GROUP(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_DEFAULT_RX_GROUP_SHIFT)) & ENETC_SI_SIMR_DEFAULT_RX_GROUP_MASK)
36630 
36631 #define ENETC_SI_SIMR_EN_MASK                    (0x80000000U)
36632 #define ENETC_SI_SIMR_EN_SHIFT                   (31U)
36633 #define ENETC_SI_SIMR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_EN_SHIFT)) & ENETC_SI_SIMR_EN_MASK)
36634 /*! @} */
36635 
36636 /*! @name SISR - Station interface status register */
36637 /*! @{ */
36638 
36639 #define ENETC_SI_SISR_TX_BUSY_MASK               (0x1U)
36640 #define ENETC_SI_SISR_TX_BUSY_SHIFT              (0U)
36641 #define ENETC_SI_SISR_TX_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_TX_BUSY_SHIFT)) & ENETC_SI_SISR_TX_BUSY_MASK)
36642 
36643 #define ENETC_SI_SISR_MAC_UP_MASK                (0x2U)
36644 #define ENETC_SI_SISR_MAC_UP_SHIFT               (1U)
36645 #define ENETC_SI_SISR_MAC_UP(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_MAC_UP_SHIFT)) & ENETC_SI_SISR_MAC_UP_MASK)
36646 
36647 #define ENETC_SI_SISR_MAC_MP_MASK                (0x4U)
36648 #define ENETC_SI_SISR_MAC_MP_SHIFT               (2U)
36649 #define ENETC_SI_SISR_MAC_MP(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_MAC_MP_SHIFT)) & ENETC_SI_SISR_MAC_MP_MASK)
36650 
36651 #define ENETC_SI_SISR_VLAN_P_MASK                (0x8U)
36652 #define ENETC_SI_SISR_VLAN_P_SHIFT               (3U)
36653 #define ENETC_SI_SISR_VLAN_P(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_VLAN_P_SHIFT)) & ENETC_SI_SISR_VLAN_P_MASK)
36654 
36655 #define ENETC_SI_SISR_VLAN_UTA_MASK              (0x10U)
36656 #define ENETC_SI_SISR_VLAN_UTA_SHIFT             (4U)
36657 #define ENETC_SI_SISR_VLAN_UTA(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_VLAN_UTA_SHIFT)) & ENETC_SI_SISR_VLAN_UTA_MASK)
36658 /*! @} */
36659 
36660 /*! @name SICTR - Station interface current time register 0..Station interface current time register 1 */
36661 /*! @{ */
36662 
36663 #define ENETC_SI_SICTR_CURR_TIME_MASK            (0xFFFFFFFFU)
36664 #define ENETC_SI_SICTR_CURR_TIME_SHIFT           (0U)
36665 #define ENETC_SI_SICTR_CURR_TIME(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICTR_CURR_TIME_SHIFT)) & ENETC_SI_SICTR_CURR_TIME_MASK)
36666 /*! @} */
36667 
36668 /* The count of ENETC_SI_SICTR */
36669 #define ENETC_SI_SICTR_COUNT                     (2U)
36670 
36671 /*! @name SIPCAPR0 - Station interface port capability register 0 */
36672 /*! @{ */
36673 
36674 #define ENETC_SI_SIPCAPR0_RFS_MASK               (0x4U)
36675 #define ENETC_SI_SIPCAPR0_RFS_SHIFT              (2U)
36676 /*! RFS - Receive Flow Steering
36677  *  0b0..Not supported
36678  *  0b1..Supported
36679  */
36680 #define ENETC_SI_SIPCAPR0_RFS(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RFS_SHIFT)) & ENETC_SI_SIPCAPR0_RFS_MASK)
36681 
36682 #define ENETC_SI_SIPCAPR0_FP_MASK                (0x8U)
36683 #define ENETC_SI_SIPCAPR0_FP_SHIFT               (3U)
36684 /*! FP - Frame Preemption
36685  *  0b0..Not Supported
36686  *  0b1..Supported
36687  */
36688 #define ENETC_SI_SIPCAPR0_FP(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_FP_SHIFT)) & ENETC_SI_SIPCAPR0_FP_MASK)
36689 
36690 #define ENETC_SI_SIPCAPR0_TGS_MASK               (0x10U)
36691 #define ENETC_SI_SIPCAPR0_TGS_SHIFT              (4U)
36692 /*! TGS - Time Gate Scheduling
36693  *  0b0..Not supported
36694  *  0b1..Supported
36695  */
36696 #define ENETC_SI_SIPCAPR0_TGS(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_TGS_SHIFT)) & ENETC_SI_SIPCAPR0_TGS_MASK)
36697 
36698 #define ENETC_SI_SIPCAPR0_TSD_MASK               (0x20U)
36699 #define ENETC_SI_SIPCAPR0_TSD_SHIFT              (5U)
36700 /*! TSD - Time Specific Departure
36701  *  0b0..Not Supported
36702  *  0b1..Supported
36703  */
36704 #define ENETC_SI_SIPCAPR0_TSD(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_TSD_SHIFT)) & ENETC_SI_SIPCAPR0_TSD_MASK)
36705 
36706 #define ENETC_SI_SIPCAPR0_CBS_MASK               (0x40U)
36707 #define ENETC_SI_SIPCAPR0_CBS_SHIFT              (6U)
36708 /*! CBS - Credit Based Shaping (CBS)
36709  *  0b0..Not Supported
36710  *  0b1..Supported
36711  */
36712 #define ENETC_SI_SIPCAPR0_CBS(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_CBS_SHIFT)) & ENETC_SI_SIPCAPR0_CBS_MASK)
36713 
36714 #define ENETC_SI_SIPCAPR0_RSS_MASK               (0x100U)
36715 #define ENETC_SI_SIPCAPR0_RSS_SHIFT              (8U)
36716 /*! RSS - Receive Side Scaling
36717  *  0b0..Not supported
36718  *  0b1..Supported
36719  */
36720 #define ENETC_SI_SIPCAPR0_RSS(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RSS_SHIFT)) & ENETC_SI_SIPCAPR0_RSS_MASK)
36721 
36722 #define ENETC_SI_SIPCAPR0_PSFP_MASK              (0x200U)
36723 #define ENETC_SI_SIPCAPR0_PSFP_SHIFT             (9U)
36724 /*! PSFP - Per-Stream Filtering and Policing (IEEE 802.1Qci)
36725  *  0b0..Not Supported
36726  *  0b1..Supported
36727  */
36728 #define ENETC_SI_SIPCAPR0_PSFP(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_PSFP_SHIFT)) & ENETC_SI_SIPCAPR0_PSFP_MASK)
36729 
36730 #define ENETC_SI_SIPCAPR0_IPFLT_MASK             (0x400U)
36731 #define ENETC_SI_SIPCAPR0_IPFLT_SHIFT            (10U)
36732 /*! IPFLT - Ingress Port Filtering
36733  *  0b0..Not supported
36734  *  0b1..Supported
36735  */
36736 #define ENETC_SI_SIPCAPR0_IPFLT(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_IPFLT_SHIFT)) & ENETC_SI_SIPCAPR0_IPFLT_MASK)
36737 
36738 #define ENETC_SI_SIPCAPR0_RP_MASK                (0x800U)
36739 #define ENETC_SI_SIPCAPR0_RP_SHIFT               (11U)
36740 /*! RP - Rate Policing
36741  *  0b0..Not Supported
36742  *  0b1..Supported
36743  */
36744 #define ENETC_SI_SIPCAPR0_RP(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RP_SHIFT)) & ENETC_SI_SIPCAPR0_RP_MASK)
36745 
36746 #define ENETC_SI_SIPCAPR0_WO_MASK                (0x2000U)
36747 #define ENETC_SI_SIPCAPR0_WO_SHIFT               (13U)
36748 /*! WO - Wake-on-LAN
36749  *  0b0..Not supported
36750  *  0b1..Supported
36751  */
36752 #define ENETC_SI_SIPCAPR0_WO(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_WO_SHIFT)) & ENETC_SI_SIPCAPR0_WO_MASK)
36753 
36754 #define ENETC_SI_SIPCAPR0_FS_MASK                (0x10000U)
36755 #define ENETC_SI_SIPCAPR0_FS_SHIFT               (16U)
36756 /*! FS - Functional Safety
36757  *  0b0..Not supported
36758  *  0b1..Supported
36759  */
36760 #define ENETC_SI_SIPCAPR0_FS(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_FS_SHIFT)) & ENETC_SI_SIPCAPR0_FS_MASK)
36761 /*! @} */
36762 
36763 /*! @name SIPCAPR1 - Station interface port capability register 1 */
36764 /*! @{ */
36765 
36766 #define ENETC_SI_SIPCAPR1_NUM_TCS_MASK           (0x70U)
36767 #define ENETC_SI_SIPCAPR1_NUM_TCS_SHIFT          (4U)
36768 #define ENETC_SI_SIPCAPR1_NUM_TCS(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_TCS_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_TCS_MASK)
36769 
36770 #define ENETC_SI_SIPCAPR1_NUM_MCH_MASK           (0x300U)
36771 #define ENETC_SI_SIPCAPR1_NUM_MCH_SHIFT          (8U)
36772 #define ENETC_SI_SIPCAPR1_NUM_MCH(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_MCH_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_MCH_MASK)
36773 
36774 #define ENETC_SI_SIPCAPR1_NUM_UCH_MASK           (0xC00U)
36775 #define ENETC_SI_SIPCAPR1_NUM_UCH_SHIFT          (10U)
36776 #define ENETC_SI_SIPCAPR1_NUM_UCH(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_UCH_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_UCH_MASK)
36777 
36778 #define ENETC_SI_SIPCAPR1_NUM_MSIX_MASK          (0x3F000U)
36779 #define ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT         (12U)
36780 #define ENETC_SI_SIPCAPR1_NUM_MSIX(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK)
36781 
36782 #define ENETC_SI_SIPCAPR1_NUM_IPV_MASK           (0x80000000U)
36783 #define ENETC_SI_SIPCAPR1_NUM_IPV_SHIFT          (31U)
36784 #define ENETC_SI_SIPCAPR1_NUM_IPV(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_IPV_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_IPV_MASK)
36785 /*! @} */
36786 
36787 /*! @name SITSR - Station interface timer status register */
36788 /*! @{ */
36789 
36790 #define ENETC_SI_SITSR_SYNC_MASK                 (0x1U)
36791 #define ENETC_SI_SITSR_SYNC_SHIFT                (0U)
36792 /*! SYNC - Timer synchronization */
36793 #define ENETC_SI_SITSR_SYNC(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITSR_SYNC_SHIFT)) & ENETC_SI_SITSR_SYNC_MASK)
36794 
36795 #define ENETC_SI_SITSR_PARAM_VAL_MASK            (0xFFFFFFFEU)
36796 #define ENETC_SI_SITSR_PARAM_VAL_SHIFT           (1U)
36797 /*! PARAM_VAL - User specific parameter values */
36798 #define ENETC_SI_SITSR_PARAM_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITSR_PARAM_VAL_SHIFT)) & ENETC_SI_SITSR_PARAM_VAL_MASK)
36799 /*! @} */
36800 
36801 /*! @name SIRBGCR - Station interface receive BDR group control register */
36802 /*! @{ */
36803 
36804 #define ENETC_SI_SIRBGCR_NUM_GROUPS_MASK         (0x3U)
36805 #define ENETC_SI_SIRBGCR_NUM_GROUPS_SHIFT        (0U)
36806 #define ENETC_SI_SIRBGCR_NUM_GROUPS(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRBGCR_NUM_GROUPS_SHIFT)) & ENETC_SI_SIRBGCR_NUM_GROUPS_MASK)
36807 
36808 #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP_MASK    (0x70000U)
36809 #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP_SHIFT   (16U)
36810 #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRBGCR_RINGS_PER_GROUP_SHIFT)) & ENETC_SI_SIRBGCR_RINGS_PER_GROUP_MASK)
36811 /*! @} */
36812 
36813 /*! @name SIBCAR - Station interface buffer cache attribute register */
36814 /*! @{ */
36815 
36816 #define ENETC_SI_SIBCAR_BD_WRCACHE_MASK          (0xFU)
36817 #define ENETC_SI_SIBCAR_BD_WRCACHE_SHIFT         (0U)
36818 #define ENETC_SI_SIBCAR_BD_WRCACHE(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRCACHE_SHIFT)) & ENETC_SI_SIBCAR_BD_WRCACHE_MASK)
36819 
36820 #define ENETC_SI_SIBCAR_BD_WRDOMAIN_MASK         (0x30U)
36821 #define ENETC_SI_SIBCAR_BD_WRDOMAIN_SHIFT        (4U)
36822 #define ENETC_SI_SIBCAR_BD_WRDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_BD_WRDOMAIN_MASK)
36823 
36824 #define ENETC_SI_SIBCAR_BD_WRSNP_MASK            (0x40U)
36825 #define ENETC_SI_SIBCAR_BD_WRSNP_SHIFT           (6U)
36826 #define ENETC_SI_SIBCAR_BD_WRSNP(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRSNP_SHIFT)) & ENETC_SI_SIBCAR_BD_WRSNP_MASK)
36827 
36828 #define ENETC_SI_SIBCAR_WRCACHE_MASK             (0xF00U)
36829 #define ENETC_SI_SIBCAR_WRCACHE_SHIFT            (8U)
36830 #define ENETC_SI_SIBCAR_WRCACHE(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRCACHE_SHIFT)) & ENETC_SI_SIBCAR_WRCACHE_MASK)
36831 
36832 #define ENETC_SI_SIBCAR_WRDOMAIN_MASK            (0x3000U)
36833 #define ENETC_SI_SIBCAR_WRDOMAIN_SHIFT           (12U)
36834 #define ENETC_SI_SIBCAR_WRDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_WRDOMAIN_MASK)
36835 
36836 #define ENETC_SI_SIBCAR_WRSNP_MASK               (0x4000U)
36837 #define ENETC_SI_SIBCAR_WRSNP_SHIFT              (14U)
36838 #define ENETC_SI_SIBCAR_WRSNP(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRSNP_SHIFT)) & ENETC_SI_SIBCAR_WRSNP_MASK)
36839 
36840 #define ENETC_SI_SIBCAR_BD_RDCACHE_MASK          (0xF0000U)
36841 #define ENETC_SI_SIBCAR_BD_RDCACHE_SHIFT         (16U)
36842 #define ENETC_SI_SIBCAR_BD_RDCACHE(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDCACHE_SHIFT)) & ENETC_SI_SIBCAR_BD_RDCACHE_MASK)
36843 
36844 #define ENETC_SI_SIBCAR_BD_RDDOMAIN_MASK         (0x300000U)
36845 #define ENETC_SI_SIBCAR_BD_RDDOMAIN_SHIFT        (20U)
36846 #define ENETC_SI_SIBCAR_BD_RDDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_BD_RDDOMAIN_MASK)
36847 
36848 #define ENETC_SI_SIBCAR_BD_RDSNP_MASK            (0x400000U)
36849 #define ENETC_SI_SIBCAR_BD_RDSNP_SHIFT           (22U)
36850 #define ENETC_SI_SIBCAR_BD_RDSNP(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDSNP_SHIFT)) & ENETC_SI_SIBCAR_BD_RDSNP_MASK)
36851 
36852 #define ENETC_SI_SIBCAR_RDCACHE_MASK             (0xF000000U)
36853 #define ENETC_SI_SIBCAR_RDCACHE_SHIFT            (24U)
36854 #define ENETC_SI_SIBCAR_RDCACHE(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDCACHE_SHIFT)) & ENETC_SI_SIBCAR_RDCACHE_MASK)
36855 
36856 #define ENETC_SI_SIBCAR_RDDOMAIN_MASK            (0x30000000U)
36857 #define ENETC_SI_SIBCAR_RDDOMAIN_SHIFT           (28U)
36858 #define ENETC_SI_SIBCAR_RDDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_RDDOMAIN_MASK)
36859 
36860 #define ENETC_SI_SIBCAR_RDSNP_MASK               (0x40000000U)
36861 #define ENETC_SI_SIBCAR_RDSNP_SHIFT              (30U)
36862 #define ENETC_SI_SIBCAR_RDSNP(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDSNP_SHIFT)) & ENETC_SI_SIBCAR_RDSNP_MASK)
36863 /*! @} */
36864 
36865 /*! @name SIMCAR - Station interface message cache attribute register */
36866 /*! @{ */
36867 
36868 #define ENETC_SI_SIMCAR_MSG_WRCACHE_MASK         (0xFU)
36869 #define ENETC_SI_SIMCAR_MSG_WRCACHE_SHIFT        (0U)
36870 #define ENETC_SI_SIMCAR_MSG_WRCACHE(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRCACHE_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRCACHE_MASK)
36871 
36872 #define ENETC_SI_SIMCAR_MSG_WRDOMAIN_MASK        (0x30U)
36873 #define ENETC_SI_SIMCAR_MSG_WRDOMAIN_SHIFT       (4U)
36874 #define ENETC_SI_SIMCAR_MSG_WRDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRDOMAIN_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRDOMAIN_MASK)
36875 
36876 #define ENETC_SI_SIMCAR_MSG_WRSNP_MASK           (0x40U)
36877 #define ENETC_SI_SIMCAR_MSG_WRSNP_SHIFT          (6U)
36878 #define ENETC_SI_SIMCAR_MSG_WRSNP(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRSNP_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRSNP_MASK)
36879 
36880 #define ENETC_SI_SIMCAR_MSG_RDCACHE_MASK         (0xF0000U)
36881 #define ENETC_SI_SIMCAR_MSG_RDCACHE_SHIFT        (16U)
36882 #define ENETC_SI_SIMCAR_MSG_RDCACHE(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDCACHE_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDCACHE_MASK)
36883 
36884 #define ENETC_SI_SIMCAR_MSG_RDDOMAIN_MASK        (0x300000U)
36885 #define ENETC_SI_SIMCAR_MSG_RDDOMAIN_SHIFT       (20U)
36886 #define ENETC_SI_SIMCAR_MSG_RDDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDDOMAIN_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDDOMAIN_MASK)
36887 
36888 #define ENETC_SI_SIMCAR_MSG_RDSNP_MASK           (0x400000U)
36889 #define ENETC_SI_SIMCAR_MSG_RDSNP_SHIFT          (22U)
36890 #define ENETC_SI_SIMCAR_MSG_RDSNP(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDSNP_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDSNP_MASK)
36891 /*! @} */
36892 
36893 /*! @name SICCAR - Station interface command cache attribute register */
36894 /*! @{ */
36895 
36896 #define ENETC_SI_SICCAR_CBD_WRCACHE_MASK         (0xFU)
36897 #define ENETC_SI_SICCAR_CBD_WRCACHE_SHIFT        (0U)
36898 #define ENETC_SI_SICCAR_CBD_WRCACHE(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRCACHE_SHIFT)) & ENETC_SI_SICCAR_CBD_WRCACHE_MASK)
36899 
36900 #define ENETC_SI_SICCAR_CBD_WRDOMAIN_MASK        (0x30U)
36901 #define ENETC_SI_SICCAR_CBD_WRDOMAIN_SHIFT       (4U)
36902 #define ENETC_SI_SICCAR_CBD_WRDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CBD_WRDOMAIN_MASK)
36903 
36904 #define ENETC_SI_SICCAR_CBD_WRSNP_MASK           (0x40U)
36905 #define ENETC_SI_SICCAR_CBD_WRSNP_SHIFT          (6U)
36906 #define ENETC_SI_SICCAR_CBD_WRSNP(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRSNP_SHIFT)) & ENETC_SI_SICCAR_CBD_WRSNP_MASK)
36907 
36908 #define ENETC_SI_SICCAR_CWRCACHE_MASK            (0xF00U)
36909 #define ENETC_SI_SICCAR_CWRCACHE_SHIFT           (8U)
36910 #define ENETC_SI_SICCAR_CWRCACHE(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRCACHE_SHIFT)) & ENETC_SI_SICCAR_CWRCACHE_MASK)
36911 
36912 #define ENETC_SI_SICCAR_CWRDOMAIN_MASK           (0x3000U)
36913 #define ENETC_SI_SICCAR_CWRDOMAIN_SHIFT          (12U)
36914 #define ENETC_SI_SICCAR_CWRDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CWRDOMAIN_MASK)
36915 
36916 #define ENETC_SI_SICCAR_CWRSNP_MASK              (0x4000U)
36917 #define ENETC_SI_SICCAR_CWRSNP_SHIFT             (14U)
36918 #define ENETC_SI_SICCAR_CWRSNP(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRSNP_SHIFT)) & ENETC_SI_SICCAR_CWRSNP_MASK)
36919 
36920 #define ENETC_SI_SICCAR_CBD_RDCACHE_MASK         (0xF0000U)
36921 #define ENETC_SI_SICCAR_CBD_RDCACHE_SHIFT        (16U)
36922 #define ENETC_SI_SICCAR_CBD_RDCACHE(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDCACHE_SHIFT)) & ENETC_SI_SICCAR_CBD_RDCACHE_MASK)
36923 
36924 #define ENETC_SI_SICCAR_CBD_RDDOMAIN_MASK        (0x300000U)
36925 #define ENETC_SI_SICCAR_CBD_RDDOMAIN_SHIFT       (20U)
36926 #define ENETC_SI_SICCAR_CBD_RDDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CBD_RDDOMAIN_MASK)
36927 
36928 #define ENETC_SI_SICCAR_CBD_RDSNP_MASK           (0x400000U)
36929 #define ENETC_SI_SICCAR_CBD_RDSNP_SHIFT          (22U)
36930 #define ENETC_SI_SICCAR_CBD_RDSNP(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDSNP_SHIFT)) & ENETC_SI_SICCAR_CBD_RDSNP_MASK)
36931 
36932 #define ENETC_SI_SICCAR_CRDCACHE_MASK            (0xF000000U)
36933 #define ENETC_SI_SICCAR_CRDCACHE_SHIFT           (24U)
36934 #define ENETC_SI_SICCAR_CRDCACHE(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDCACHE_SHIFT)) & ENETC_SI_SICCAR_CRDCACHE_MASK)
36935 
36936 #define ENETC_SI_SICCAR_CRDDOMAIN_MASK           (0x30000000U)
36937 #define ENETC_SI_SICCAR_CRDDOMAIN_SHIFT          (28U)
36938 #define ENETC_SI_SICCAR_CRDDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CRDDOMAIN_MASK)
36939 
36940 #define ENETC_SI_SICCAR_CRDSNP_MASK              (0x40000000U)
36941 #define ENETC_SI_SICCAR_CRDSNP_SHIFT             (30U)
36942 #define ENETC_SI_SICCAR_CRDSNP(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDSNP_SHIFT)) & ENETC_SI_SICCAR_CRDSNP_MASK)
36943 /*! @} */
36944 
36945 /*! @name SIPMAR0 - Station interface primary MAC address register 0 */
36946 /*! @{ */
36947 
36948 #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_MASK      (0xFFFFFFFFU)
36949 #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_SHIFT     (0U)
36950 #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_SHIFT)) & ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_MASK)
36951 /*! @} */
36952 
36953 /*! @name SIPMAR1 - Station interface primary MAC address register 1 */
36954 /*! @{ */
36955 
36956 #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_MASK      (0xFFFFU)
36957 #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_SHIFT     (0U)
36958 #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_SHIFT)) & ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_MASK)
36959 /*! @} */
36960 
36961 /*! @name SICVLANR1 - Station interface custom VLAN register 1 */
36962 /*! @{ */
36963 
36964 #define ENETC_SI_SICVLANR1_ETYPE_MASK            (0xFFFFU)
36965 #define ENETC_SI_SICVLANR1_ETYPE_SHIFT           (0U)
36966 #define ENETC_SI_SICVLANR1_ETYPE(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR1_ETYPE_SHIFT)) & ENETC_SI_SICVLANR1_ETYPE_MASK)
36967 
36968 #define ENETC_SI_SICVLANR1_V_MASK                (0x80000000U)
36969 #define ENETC_SI_SICVLANR1_V_SHIFT               (31U)
36970 #define ENETC_SI_SICVLANR1_V(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR1_V_SHIFT)) & ENETC_SI_SICVLANR1_V_MASK)
36971 /*! @} */
36972 
36973 /*! @name SICVLANR2 - Station interface custom VLAN register 2 */
36974 /*! @{ */
36975 
36976 #define ENETC_SI_SICVLANR2_ETYPE_MASK            (0xFFFFU)
36977 #define ENETC_SI_SICVLANR2_ETYPE_SHIFT           (0U)
36978 #define ENETC_SI_SICVLANR2_ETYPE(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR2_ETYPE_SHIFT)) & ENETC_SI_SICVLANR2_ETYPE_MASK)
36979 
36980 #define ENETC_SI_SICVLANR2_V_MASK                (0x80000000U)
36981 #define ENETC_SI_SICVLANR2_V_SHIFT               (31U)
36982 #define ENETC_SI_SICVLANR2_V(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR2_V_SHIFT)) & ENETC_SI_SICVLANR2_V_MASK)
36983 /*! @} */
36984 
36985 /*! @name SIVLANIPVMR0 - Station interface VLAN to IPV mapping register 0 */
36986 /*! @{ */
36987 
36988 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_MASK     (0xFU)
36989 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_SHIFT    (0U)
36990 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_MASK)
36991 
36992 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_MASK     (0xF0U)
36993 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_SHIFT    (4U)
36994 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_MASK)
36995 
36996 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_MASK     (0xF00U)
36997 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_SHIFT    (8U)
36998 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_MASK)
36999 
37000 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_MASK     (0xF000U)
37001 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_SHIFT    (12U)
37002 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_MASK)
37003 
37004 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_MASK     (0xF0000U)
37005 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_SHIFT    (16U)
37006 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_MASK)
37007 
37008 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_MASK     (0xF00000U)
37009 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_SHIFT    (20U)
37010 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_MASK)
37011 
37012 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_MASK     (0xF000000U)
37013 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_SHIFT    (24U)
37014 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_MASK)
37015 
37016 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_MASK     (0xF0000000U)
37017 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_SHIFT    (28U)
37018 #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_MASK)
37019 /*! @} */
37020 
37021 /*! @name SIVLANIPVMR1 - Station interface VLAN to IPV mapping register 1 */
37022 /*! @{ */
37023 
37024 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_MASK     (0xFU)
37025 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_SHIFT    (0U)
37026 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_MASK)
37027 
37028 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_MASK     (0xF0U)
37029 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_SHIFT    (4U)
37030 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_MASK)
37031 
37032 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_MASK    (0xF00U)
37033 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_SHIFT   (8U)
37034 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_MASK)
37035 
37036 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_MASK    (0xF000U)
37037 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_SHIFT   (12U)
37038 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_MASK)
37039 
37040 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_MASK    (0xF0000U)
37041 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_SHIFT   (16U)
37042 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_MASK)
37043 
37044 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_MASK    (0xF00000U)
37045 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_SHIFT   (20U)
37046 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_MASK)
37047 
37048 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_MASK    (0xF000000U)
37049 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_SHIFT   (24U)
37050 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_MASK)
37051 
37052 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_MASK    (0xF0000000U)
37053 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_SHIFT   (28U)
37054 #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_MASK)
37055 /*! @} */
37056 
37057 /*! @name SIIPVBDRMR0 - Station interface IPV to ring mapping register */
37058 /*! @{ */
37059 
37060 #define ENETC_SI_SIIPVBDRMR0_IPV0BDR_MASK        (0x7U)
37061 #define ENETC_SI_SIIPVBDRMR0_IPV0BDR_SHIFT       (0U)
37062 #define ENETC_SI_SIIPVBDRMR0_IPV0BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV0BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV0BDR_MASK)
37063 
37064 #define ENETC_SI_SIIPVBDRMR0_IPV1BDR_MASK        (0x70U)
37065 #define ENETC_SI_SIIPVBDRMR0_IPV1BDR_SHIFT       (4U)
37066 #define ENETC_SI_SIIPVBDRMR0_IPV1BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV1BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV1BDR_MASK)
37067 
37068 #define ENETC_SI_SIIPVBDRMR0_IPV2BDR_MASK        (0x700U)
37069 #define ENETC_SI_SIIPVBDRMR0_IPV2BDR_SHIFT       (8U)
37070 #define ENETC_SI_SIIPVBDRMR0_IPV2BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV2BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV2BDR_MASK)
37071 
37072 #define ENETC_SI_SIIPVBDRMR0_IPV3BDR_MASK        (0x7000U)
37073 #define ENETC_SI_SIIPVBDRMR0_IPV3BDR_SHIFT       (12U)
37074 #define ENETC_SI_SIIPVBDRMR0_IPV3BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV3BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV3BDR_MASK)
37075 
37076 #define ENETC_SI_SIIPVBDRMR0_IPV4BDR_MASK        (0x70000U)
37077 #define ENETC_SI_SIIPVBDRMR0_IPV4BDR_SHIFT       (16U)
37078 #define ENETC_SI_SIIPVBDRMR0_IPV4BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV4BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV4BDR_MASK)
37079 
37080 #define ENETC_SI_SIIPVBDRMR0_IPV5BDR_MASK        (0x700000U)
37081 #define ENETC_SI_SIIPVBDRMR0_IPV5BDR_SHIFT       (20U)
37082 #define ENETC_SI_SIIPVBDRMR0_IPV5BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV5BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV5BDR_MASK)
37083 
37084 #define ENETC_SI_SIIPVBDRMR0_IPV6BDR_MASK        (0x7000000U)
37085 #define ENETC_SI_SIIPVBDRMR0_IPV6BDR_SHIFT       (24U)
37086 #define ENETC_SI_SIIPVBDRMR0_IPV6BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV6BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV6BDR_MASK)
37087 
37088 #define ENETC_SI_SIIPVBDRMR0_IPV7BDR_MASK        (0x70000000U)
37089 #define ENETC_SI_SIIPVBDRMR0_IPV7BDR_SHIFT       (28U)
37090 #define ENETC_SI_SIIPVBDRMR0_IPV7BDR(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV7BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV7BDR_MASK)
37091 /*! @} */
37092 
37093 /*! @name PSIMSGRR - Physical station interface message receive register */
37094 /*! @{ */
37095 
37096 #define ENETC_SI_PSIMSGRR_MR1_MASK               (0x2U)
37097 #define ENETC_SI_PSIMSGRR_MR1_SHIFT              (1U)
37098 #define ENETC_SI_PSIMSGRR_MR1(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGRR_MR1_SHIFT)) & ENETC_SI_PSIMSGRR_MR1_MASK)
37099 
37100 #define ENETC_SI_PSIMSGRR_MC_MASK                (0xFFFF0000U)
37101 #define ENETC_SI_PSIMSGRR_MC_SHIFT               (16U)
37102 /*! MC - Message code */
37103 #define ENETC_SI_PSIMSGRR_MC(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGRR_MC_SHIFT)) & ENETC_SI_PSIMSGRR_MC_MASK)
37104 /*! @} */
37105 
37106 /*! @name PSIMSGSR - Physical station interface message send register */
37107 /*! @{ */
37108 
37109 #define ENETC_SI_PSIMSGSR_MS1_MASK               (0x2U)
37110 #define ENETC_SI_PSIMSGSR_MS1_SHIFT              (1U)
37111 #define ENETC_SI_PSIMSGSR_MS1(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGSR_MS1_SHIFT)) & ENETC_SI_PSIMSGSR_MS1_MASK)
37112 
37113 #define ENETC_SI_PSIMSGSR_MC_MASK                (0xFFFF0000U)
37114 #define ENETC_SI_PSIMSGSR_MC_SHIFT               (16U)
37115 #define ENETC_SI_PSIMSGSR_MC(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGSR_MC_SHIFT)) & ENETC_SI_PSIMSGSR_MC_MASK)
37116 /*! @} */
37117 
37118 /*! @name PSIVMSGRCVAR0 - PSI VSI 1 message receive address register 0 */
37119 /*! @{ */
37120 
37121 #define ENETC_SI_PSIVMSGRCVAR0_MSIZE_MASK        (0x1FU)
37122 #define ENETC_SI_PSIVMSGRCVAR0_MSIZE_SHIFT       (0U)
37123 #define ENETC_SI_PSIVMSGRCVAR0_MSIZE(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR0_MSIZE_SHIFT)) & ENETC_SI_PSIVMSGRCVAR0_MSIZE_MASK)
37124 
37125 #define ENETC_SI_PSIVMSGRCVAR0_ADDRL_MASK        (0xFFFFFFC0U)
37126 #define ENETC_SI_PSIVMSGRCVAR0_ADDRL_SHIFT       (6U)
37127 #define ENETC_SI_PSIVMSGRCVAR0_ADDRL(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR0_ADDRL_SHIFT)) & ENETC_SI_PSIVMSGRCVAR0_ADDRL_MASK)
37128 /*! @} */
37129 
37130 /* The count of ENETC_SI_PSIVMSGRCVAR0 */
37131 #define ENETC_SI_PSIVMSGRCVAR0_COUNT             (1U)
37132 
37133 /*! @name PSIVMSGRCVAR1 - PSI VSI 1 message receive address register 1 */
37134 /*! @{ */
37135 
37136 #define ENETC_SI_PSIVMSGRCVAR1_ADDRH_MASK        (0xFFFFFFFFU)
37137 #define ENETC_SI_PSIVMSGRCVAR1_ADDRH_SHIFT       (0U)
37138 #define ENETC_SI_PSIVMSGRCVAR1_ADDRH(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR1_ADDRH_SHIFT)) & ENETC_SI_PSIVMSGRCVAR1_ADDRH_MASK)
37139 /*! @} */
37140 
37141 /* The count of ENETC_SI_PSIVMSGRCVAR1 */
37142 #define ENETC_SI_PSIVMSGRCVAR1_COUNT             (1U)
37143 
37144 /*! @name VSIMSGSR - Virtual station interface message send register */
37145 /*! @{ */
37146 
37147 #define ENETC_SI_VSIMSGSR_MB_MASK                (0x1U)
37148 #define ENETC_SI_VSIMSGSR_MB_SHIFT               (0U)
37149 #define ENETC_SI_VSIMSGSR_MB(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MB_SHIFT)) & ENETC_SI_VSIMSGSR_MB_MASK)
37150 
37151 #define ENETC_SI_VSIMSGSR_MS_MASK                (0x2U)
37152 #define ENETC_SI_VSIMSGSR_MS_SHIFT               (1U)
37153 #define ENETC_SI_VSIMSGSR_MS(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MS_SHIFT)) & ENETC_SI_VSIMSGSR_MS_MASK)
37154 
37155 #define ENETC_SI_VSIMSGSR_MC_MASK                (0xFFFF0000U)
37156 #define ENETC_SI_VSIMSGSR_MC_SHIFT               (16U)
37157 #define ENETC_SI_VSIMSGSR_MC(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MC_SHIFT)) & ENETC_SI_VSIMSGSR_MC_MASK)
37158 /*! @} */
37159 
37160 /*! @name VSIMSGRR - Virtual station interface message receive register */
37161 /*! @{ */
37162 
37163 #define ENETC_SI_VSIMSGRR_MR_MASK                (0x1U)
37164 #define ENETC_SI_VSIMSGRR_MR_SHIFT               (0U)
37165 #define ENETC_SI_VSIMSGRR_MR(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGRR_MR_SHIFT)) & ENETC_SI_VSIMSGRR_MR_MASK)
37166 
37167 #define ENETC_SI_VSIMSGRR_MC_MASK                (0xFFFF0000U)
37168 #define ENETC_SI_VSIMSGRR_MC_SHIFT               (16U)
37169 #define ENETC_SI_VSIMSGRR_MC(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGRR_MC_SHIFT)) & ENETC_SI_VSIMSGRR_MC_MASK)
37170 /*! @} */
37171 
37172 /*! @name VSIMSGSNDAR0 - Virtual station interface message send register 0 */
37173 /*! @{ */
37174 
37175 #define ENETC_SI_VSIMSGSNDAR0_MSIZE_MASK         (0x1FU)
37176 #define ENETC_SI_VSIMSGSNDAR0_MSIZE_SHIFT        (0U)
37177 #define ENETC_SI_VSIMSGSNDAR0_MSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR0_MSIZE_SHIFT)) & ENETC_SI_VSIMSGSNDAR0_MSIZE_MASK)
37178 
37179 #define ENETC_SI_VSIMSGSNDAR0_ADDRL_MASK         (0xFFFFFFC0U)
37180 #define ENETC_SI_VSIMSGSNDAR0_ADDRL_SHIFT        (6U)
37181 #define ENETC_SI_VSIMSGSNDAR0_ADDRL(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR0_ADDRL_SHIFT)) & ENETC_SI_VSIMSGSNDAR0_ADDRL_MASK)
37182 /*! @} */
37183 
37184 /*! @name VSIMSGSNDAR1 - Virtual station interface message send address register 1 */
37185 /*! @{ */
37186 
37187 #define ENETC_SI_VSIMSGSNDAR1_ADDRH_MASK         (0xFFFFFFFFU)
37188 #define ENETC_SI_VSIMSGSNDAR1_ADDRH_SHIFT        (0U)
37189 #define ENETC_SI_VSIMSGSNDAR1_ADDRH(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR1_ADDRH_SHIFT)) & ENETC_SI_VSIMSGSNDAR1_ADDRH_MASK)
37190 /*! @} */
37191 
37192 /*! @name SIROCT0 - Station interface receive octets counter (ifInOctets) 0 */
37193 /*! @{ */
37194 
37195 #define ENETC_SI_SIROCT0_ROCT_LOW_MASK           (0xFFFFFFFFU)
37196 #define ENETC_SI_SIROCT0_ROCT_LOW_SHIFT          (0U)
37197 #define ENETC_SI_SIROCT0_ROCT_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIROCT0_ROCT_LOW_SHIFT)) & ENETC_SI_SIROCT0_ROCT_LOW_MASK)
37198 /*! @} */
37199 
37200 /*! @name SIROCT1 - Station interface receive octets counter (ifInOctets) 1 */
37201 /*! @{ */
37202 
37203 #define ENETC_SI_SIROCT1_ROCT_HIGH_MASK          (0xFFFFFFFFU)
37204 #define ENETC_SI_SIROCT1_ROCT_HIGH_SHIFT         (0U)
37205 #define ENETC_SI_SIROCT1_ROCT_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIROCT1_ROCT_HIGH_SHIFT)) & ENETC_SI_SIROCT1_ROCT_HIGH_MASK)
37206 /*! @} */
37207 
37208 /*! @name SIRFRM0 - Station interface receive frame counter (aFrameReceivedOK) 0 */
37209 /*! @{ */
37210 
37211 #define ENETC_SI_SIRFRM0_RFRM_LOW_MASK           (0xFFFFFFFFU)
37212 #define ENETC_SI_SIRFRM0_RFRM_LOW_SHIFT          (0U)
37213 #define ENETC_SI_SIRFRM0_RFRM_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRFRM0_RFRM_LOW_SHIFT)) & ENETC_SI_SIRFRM0_RFRM_LOW_MASK)
37214 /*! @} */
37215 
37216 /*! @name SIRFRM1 - Station interface receive frame counter (aFrameReceivedOK) 1 */
37217 /*! @{ */
37218 
37219 #define ENETC_SI_SIRFRM1_RFRM_HIGH_MASK          (0xFFFFFFFFU)
37220 #define ENETC_SI_SIRFRM1_RFRM_HIGH_SHIFT         (0U)
37221 #define ENETC_SI_SIRFRM1_RFRM_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRFRM1_RFRM_HIGH_SHIFT)) & ENETC_SI_SIRFRM1_RFRM_HIGH_MASK)
37222 /*! @} */
37223 
37224 /*! @name SIRUCA0 - Station interface receive unicast frame counter (ifInUcastPkts) 0 */
37225 /*! @{ */
37226 
37227 #define ENETC_SI_SIRUCA0_RUCA_LOW_MASK           (0xFFFFFFFFU)
37228 #define ENETC_SI_SIRUCA0_RUCA_LOW_SHIFT          (0U)
37229 #define ENETC_SI_SIRUCA0_RUCA_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRUCA0_RUCA_LOW_SHIFT)) & ENETC_SI_SIRUCA0_RUCA_LOW_MASK)
37230 /*! @} */
37231 
37232 /*! @name SIRUCA1 - Station interface receive unicast frame counter (ifInUcastPkts) 1 */
37233 /*! @{ */
37234 
37235 #define ENETC_SI_SIRUCA1_RUCA_HIGH_MASK          (0xFFFFFFFFU)
37236 #define ENETC_SI_SIRUCA1_RUCA_HIGH_SHIFT         (0U)
37237 #define ENETC_SI_SIRUCA1_RUCA_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRUCA1_RUCA_HIGH_SHIFT)) & ENETC_SI_SIRUCA1_RUCA_HIGH_MASK)
37238 /*! @} */
37239 
37240 /*! @name SIRMCA0 - Station interface receive multicast frame counter (ifInMulticastPkts) 0 */
37241 /*! @{ */
37242 
37243 #define ENETC_SI_SIRMCA0_RMCA_LOW_MASK           (0xFFFFFFFFU)
37244 #define ENETC_SI_SIRMCA0_RMCA_LOW_SHIFT          (0U)
37245 #define ENETC_SI_SIRMCA0_RMCA_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRMCA0_RMCA_LOW_SHIFT)) & ENETC_SI_SIRMCA0_RMCA_LOW_MASK)
37246 /*! @} */
37247 
37248 /*! @name SIRMCA1 - Station interface receive multicast frame counter (ifInMulticastPkts) 1 */
37249 /*! @{ */
37250 
37251 #define ENETC_SI_SIRMCA1_RMCA_HIGH_MASK          (0xFFFFFFFFU)
37252 #define ENETC_SI_SIRMCA1_RMCA_HIGH_SHIFT         (0U)
37253 #define ENETC_SI_SIRMCA1_RMCA_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRMCA1_RMCA_HIGH_SHIFT)) & ENETC_SI_SIRMCA1_RMCA_HIGH_MASK)
37254 /*! @} */
37255 
37256 /*! @name SITOCT0 - Station interface transmit octets counter (ifOutOctets) 0 */
37257 /*! @{ */
37258 
37259 #define ENETC_SI_SITOCT0_TOCT_LOW_MASK           (0xFFFFFFFFU)
37260 #define ENETC_SI_SITOCT0_TOCT_LOW_SHIFT          (0U)
37261 #define ENETC_SI_SITOCT0_TOCT_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITOCT0_TOCT_LOW_SHIFT)) & ENETC_SI_SITOCT0_TOCT_LOW_MASK)
37262 /*! @} */
37263 
37264 /*! @name SITOCT1 - Station interface transmit octets counter (ifOutOctets) 1 */
37265 /*! @{ */
37266 
37267 #define ENETC_SI_SITOCT1_TOCT_HIGH_MASK          (0xFFFFFFFFU)
37268 #define ENETC_SI_SITOCT1_TOCT_HIGH_SHIFT         (0U)
37269 #define ENETC_SI_SITOCT1_TOCT_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITOCT1_TOCT_HIGH_SHIFT)) & ENETC_SI_SITOCT1_TOCT_HIGH_MASK)
37270 /*! @} */
37271 
37272 /*! @name SITFRM0 - Station interface transmit frame counter (aFrameTransmittedOK) 0 */
37273 /*! @{ */
37274 
37275 #define ENETC_SI_SITFRM0_TFRM_LOW_MASK           (0xFFFFFFFFU)
37276 #define ENETC_SI_SITFRM0_TFRM_LOW_SHIFT          (0U)
37277 #define ENETC_SI_SITFRM0_TFRM_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITFRM0_TFRM_LOW_SHIFT)) & ENETC_SI_SITFRM0_TFRM_LOW_MASK)
37278 /*! @} */
37279 
37280 /*! @name SITFRM1 - Station interface transmit frame counter (aFrameTransmittedOK) 1 */
37281 /*! @{ */
37282 
37283 #define ENETC_SI_SITFRM1_TFRM_HIGH_MASK          (0xFFFFFFFFU)
37284 #define ENETC_SI_SITFRM1_TFRM_HIGH_SHIFT         (0U)
37285 #define ENETC_SI_SITFRM1_TFRM_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITFRM1_TFRM_HIGH_SHIFT)) & ENETC_SI_SITFRM1_TFRM_HIGH_MASK)
37286 /*! @} */
37287 
37288 /*! @name SITUCA0 - Station interface transmit unicast frame counter (ifOutUcastPkts) 0 */
37289 /*! @{ */
37290 
37291 #define ENETC_SI_SITUCA0_TUCA_LOW_MASK           (0xFFFFFFFFU)
37292 #define ENETC_SI_SITUCA0_TUCA_LOW_SHIFT          (0U)
37293 #define ENETC_SI_SITUCA0_TUCA_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITUCA0_TUCA_LOW_SHIFT)) & ENETC_SI_SITUCA0_TUCA_LOW_MASK)
37294 /*! @} */
37295 
37296 /*! @name SITUCA1 - Station interface transmit unicast frame counter (ifOutUcastPkts) 1 */
37297 /*! @{ */
37298 
37299 #define ENETC_SI_SITUCA1_TUCA_HIGH_MASK          (0xFFFFFFFFU)
37300 #define ENETC_SI_SITUCA1_TUCA_HIGH_SHIFT         (0U)
37301 #define ENETC_SI_SITUCA1_TUCA_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITUCA1_TUCA_HIGH_SHIFT)) & ENETC_SI_SITUCA1_TUCA_HIGH_MASK)
37302 /*! @} */
37303 
37304 /*! @name SITMCA0 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 0 */
37305 /*! @{ */
37306 
37307 #define ENETC_SI_SITMCA0_TMCA_LOW_MASK           (0xFFFFFFFFU)
37308 #define ENETC_SI_SITMCA0_TMCA_LOW_SHIFT          (0U)
37309 #define ENETC_SI_SITMCA0_TMCA_LOW(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMCA0_TMCA_LOW_SHIFT)) & ENETC_SI_SITMCA0_TMCA_LOW_MASK)
37310 /*! @} */
37311 
37312 /*! @name SITMCA1 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 1 */
37313 /*! @{ */
37314 
37315 #define ENETC_SI_SITMCA1_TMCA_HIGH_MASK          (0xFFFFFFFFU)
37316 #define ENETC_SI_SITMCA1_TMCA_HIGH_SHIFT         (0U)
37317 #define ENETC_SI_SITMCA1_TMCA_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMCA1_TMCA_HIGH_SHIFT)) & ENETC_SI_SITMCA1_TMCA_HIGH_MASK)
37318 /*! @} */
37319 
37320 /*! @name SIBLPR - Station interface boot loader parameter register 0..Station interface boot loader parameter register 1 */
37321 /*! @{ */
37322 
37323 #define ENETC_SI_SIBLPR_PARAM_VAL_MASK           (0xFFFFFFFFU)
37324 #define ENETC_SI_SIBLPR_PARAM_VAL_SHIFT          (0U)
37325 #define ENETC_SI_SIBLPR_PARAM_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBLPR_PARAM_VAL_SHIFT)) & ENETC_SI_SIBLPR_PARAM_VAL_MASK)
37326 /*! @} */
37327 
37328 /* The count of ENETC_SI_SIBLPR */
37329 #define ENETC_SI_SIBLPR_COUNT                    (2U)
37330 
37331 /*! @name SICBDRMR - Station interface command BDR mode register */
37332 /*! @{ */
37333 
37334 #define ENETC_SI_SICBDRMR_EN_MASK                (0x80000000U)
37335 #define ENETC_SI_SICBDRMR_EN_SHIFT               (31U)
37336 #define ENETC_SI_SICBDRMR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRMR_EN_SHIFT)) & ENETC_SI_SICBDRMR_EN_MASK)
37337 /*! @} */
37338 
37339 /*! @name SICBDRSR - Station interface command BDR status register */
37340 /*! @{ */
37341 
37342 #define ENETC_SI_SICBDRSR_BUSY_MASK              (0x1U)
37343 #define ENETC_SI_SICBDRSR_BUSY_SHIFT             (0U)
37344 #define ENETC_SI_SICBDRSR_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRSR_BUSY_SHIFT)) & ENETC_SI_SICBDRSR_BUSY_MASK)
37345 /*! @} */
37346 
37347 /*! @name SICBDRBAR0 - Station interface command BDR base address register 0 */
37348 /*! @{ */
37349 
37350 #define ENETC_SI_SICBDRBAR0_ADDRL_MASK           (0xFFFFFF80U)
37351 #define ENETC_SI_SICBDRBAR0_ADDRL_SHIFT          (7U)
37352 #define ENETC_SI_SICBDRBAR0_ADDRL(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRBAR0_ADDRL_SHIFT)) & ENETC_SI_SICBDRBAR0_ADDRL_MASK)
37353 /*! @} */
37354 
37355 /*! @name SICBDRBAR1 - Station interface command BDR base address register 1 */
37356 /*! @{ */
37357 
37358 #define ENETC_SI_SICBDRBAR1_ADDRH_MASK           (0xFFFFFFFFU)
37359 #define ENETC_SI_SICBDRBAR1_ADDRH_SHIFT          (0U)
37360 #define ENETC_SI_SICBDRBAR1_ADDRH(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRBAR1_ADDRH_SHIFT)) & ENETC_SI_SICBDRBAR1_ADDRH_MASK)
37361 /*! @} */
37362 
37363 /*! @name SICBDRPIR - Station interface command BDR producer index register */
37364 /*! @{ */
37365 
37366 #define ENETC_SI_SICBDRPIR_BDR_INDEX_MASK        (0x3FFU)
37367 #define ENETC_SI_SICBDRPIR_BDR_INDEX_SHIFT       (0U)
37368 #define ENETC_SI_SICBDRPIR_BDR_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRPIR_BDR_INDEX_SHIFT)) & ENETC_SI_SICBDRPIR_BDR_INDEX_MASK)
37369 /*! @} */
37370 
37371 /*! @name SICBDRCIR - Station interface command BDR consumer index register */
37372 /*! @{ */
37373 
37374 #define ENETC_SI_SICBDRCIR_BDR_INDEX_MASK        (0x3FFU)
37375 #define ENETC_SI_SICBDRCIR_BDR_INDEX_SHIFT       (0U)
37376 #define ENETC_SI_SICBDRCIR_BDR_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRCIR_BDR_INDEX_SHIFT)) & ENETC_SI_SICBDRCIR_BDR_INDEX_MASK)
37377 /*! @} */
37378 
37379 /*! @name SICBDRLENR - Station interface command BDR length register */
37380 /*! @{ */
37381 
37382 #define ENETC_SI_SICBDRLENR_LENGTH_MASK          (0x7F8U)
37383 #define ENETC_SI_SICBDRLENR_LENGTH_SHIFT         (3U)
37384 #define ENETC_SI_SICBDRLENR_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRLENR_LENGTH_SHIFT)) & ENETC_SI_SICBDRLENR_LENGTH_MASK)
37385 /*! @} */
37386 
37387 /*! @name SICBDRIER - Station interface command BDR interrupt enable register */
37388 /*! @{ */
37389 
37390 #define ENETC_SI_SICBDRIER_CBDCIE_MASK           (0x1U)
37391 #define ENETC_SI_SICBDRIER_CBDCIE_SHIFT          (0U)
37392 #define ENETC_SI_SICBDRIER_CBDCIE(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRIER_CBDCIE_SHIFT)) & ENETC_SI_SICBDRIER_CBDCIE_MASK)
37393 /*! @} */
37394 
37395 /*! @name SICBDRIDR - Station interface command BDR interrupt detect register */
37396 /*! @{ */
37397 
37398 #define ENETC_SI_SICBDRIDR_CBDC_MASK             (0x1U)
37399 #define ENETC_SI_SICBDRIDR_CBDC_SHIFT            (0U)
37400 #define ENETC_SI_SICBDRIDR_CBDC(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRIDR_CBDC_SHIFT)) & ENETC_SI_SICBDRIDR_CBDC_MASK)
37401 /*! @} */
37402 
37403 /*! @name SICAPR0 - Station interface capability register 0 */
37404 /*! @{ */
37405 
37406 #define ENETC_SI_SICAPR0_NUM_TX_BDR_MASK         (0xFFU)
37407 #define ENETC_SI_SICAPR0_NUM_TX_BDR_SHIFT        (0U)
37408 #define ENETC_SI_SICAPR0_NUM_TX_BDR(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR0_NUM_TX_BDR_SHIFT)) & ENETC_SI_SICAPR0_NUM_TX_BDR_MASK)
37409 
37410 #define ENETC_SI_SICAPR0_NUM_RX_BDR_MASK         (0xFF0000U)
37411 #define ENETC_SI_SICAPR0_NUM_RX_BDR_SHIFT        (16U)
37412 #define ENETC_SI_SICAPR0_NUM_RX_BDR(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR0_NUM_RX_BDR_SHIFT)) & ENETC_SI_SICAPR0_NUM_RX_BDR_MASK)
37413 
37414 #define ENETC_SI_SICAPR0_NUM_MAC_ADDR_MASK       (0xF0000000U)
37415 #define ENETC_SI_SICAPR0_NUM_MAC_ADDR_SHIFT      (28U)
37416 #define ENETC_SI_SICAPR0_NUM_MAC_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR0_NUM_MAC_ADDR_SHIFT)) & ENETC_SI_SICAPR0_NUM_MAC_ADDR_MASK)
37417 /*! @} */
37418 
37419 /*! @name SICAPR1 - Station interface capability register 1 */
37420 /*! @{ */
37421 
37422 #define ENETC_SI_SICAPR1_NUM_RX_GRP_MASK         (0xFF0000U)
37423 #define ENETC_SI_SICAPR1_NUM_RX_GRP_SHIFT        (16U)
37424 #define ENETC_SI_SICAPR1_NUM_RX_GRP(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR1_NUM_RX_GRP_SHIFT)) & ENETC_SI_SICAPR1_NUM_RX_GRP_MASK)
37425 /*! @} */
37426 
37427 /*! @name SICAPR2 - Station interface capability register 2 */
37428 /*! @{ */
37429 
37430 #define ENETC_SI_SICAPR2_VTP_MASK                (0xFU)
37431 #define ENETC_SI_SICAPR2_VTP_SHIFT               (0U)
37432 #define ENETC_SI_SICAPR2_VTP(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR2_VTP_SHIFT)) & ENETC_SI_SICAPR2_VTP_MASK)
37433 /*! @} */
37434 
37435 /*! @name PSIIER - Physical station interface interrupt enable register */
37436 /*! @{ */
37437 
37438 #define ENETC_SI_PSIIER_MR1IE_MASK               (0x2U)
37439 #define ENETC_SI_PSIIER_MR1IE_SHIFT              (1U)
37440 #define ENETC_SI_PSIIER_MR1IE(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_MR1IE_SHIFT)) & ENETC_SI_PSIIER_MR1IE_MASK)
37441 
37442 #define ENETC_SI_PSIIER_FLR1IE_MASK              (0x20000U)
37443 #define ENETC_SI_PSIIER_FLR1IE_SHIFT             (17U)
37444 #define ENETC_SI_PSIIER_FLR1IE(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_FLR1IE_SHIFT)) & ENETC_SI_PSIIER_FLR1IE_MASK)
37445 /*! @} */
37446 
37447 /*! @name PSIIDR - Physical station interface interrupt detect register */
37448 /*! @{ */
37449 
37450 #define ENETC_SI_PSIIDR_TXR_MASK                 (0x1U)
37451 #define ENETC_SI_PSIIDR_TXR_SHIFT                (0U)
37452 #define ENETC_SI_PSIIDR_TXR(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_TXR_SHIFT)) & ENETC_SI_PSIIDR_TXR_MASK)
37453 
37454 #define ENETC_SI_PSIIDR_MR1_MASK                 (0x2U)
37455 #define ENETC_SI_PSIIDR_MR1_SHIFT                (1U)
37456 #define ENETC_SI_PSIIDR_MR1(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_MR1_SHIFT)) & ENETC_SI_PSIIDR_MR1_MASK)
37457 
37458 #define ENETC_SI_PSIIDR_RXR_MASK                 (0x10000U)
37459 #define ENETC_SI_PSIIDR_RXR_SHIFT                (16U)
37460 #define ENETC_SI_PSIIDR_RXR(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_RXR_SHIFT)) & ENETC_SI_PSIIDR_RXR_MASK)
37461 
37462 #define ENETC_SI_PSIIDR_FLR1_MASK                (0x20000U)
37463 #define ENETC_SI_PSIIDR_FLR1_SHIFT               (17U)
37464 #define ENETC_SI_PSIIDR_FLR1(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_FLR1_SHIFT)) & ENETC_SI_PSIIDR_FLR1_MASK)
37465 /*! @} */
37466 
37467 /*! @name VSIIER - Virtual station interface interrupt enable register */
37468 /*! @{ */
37469 
37470 #define ENETC_SI_VSIIER_MSIE_MASK                (0x100U)
37471 #define ENETC_SI_VSIIER_MSIE_SHIFT               (8U)
37472 #define ENETC_SI_VSIIER_MSIE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIER_MSIE_SHIFT)) & ENETC_SI_VSIIER_MSIE_MASK)
37473 
37474 #define ENETC_SI_VSIIER_MRIE_MASK                (0x200U)
37475 #define ENETC_SI_VSIIER_MRIE_SHIFT               (9U)
37476 #define ENETC_SI_VSIIER_MRIE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIER_MRIE_SHIFT)) & ENETC_SI_VSIIER_MRIE_MASK)
37477 /*! @} */
37478 
37479 /*! @name VSIIDR - Virtual station interface interrupt detect register */
37480 /*! @{ */
37481 
37482 #define ENETC_SI_VSIIDR_TXR_MASK                 (0x1U)
37483 #define ENETC_SI_VSIIDR_TXR_SHIFT                (0U)
37484 #define ENETC_SI_VSIIDR_TXR(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_TXR_SHIFT)) & ENETC_SI_VSIIDR_TXR_MASK)
37485 
37486 #define ENETC_SI_VSIIDR_MS_MASK                  (0x100U)
37487 #define ENETC_SI_VSIIDR_MS_SHIFT                 (8U)
37488 #define ENETC_SI_VSIIDR_MS(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_MS_SHIFT)) & ENETC_SI_VSIIDR_MS_MASK)
37489 
37490 #define ENETC_SI_VSIIDR_MR_MASK                  (0x200U)
37491 #define ENETC_SI_VSIIDR_MR_SHIFT                 (9U)
37492 #define ENETC_SI_VSIIDR_MR(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_MR_SHIFT)) & ENETC_SI_VSIIDR_MR_MASK)
37493 
37494 #define ENETC_SI_VSIIDR_RXR_MASK                 (0x10000U)
37495 #define ENETC_SI_VSIIDR_RXR_SHIFT                (16U)
37496 #define ENETC_SI_VSIIDR_RXR(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_RXR_SHIFT)) & ENETC_SI_VSIIDR_RXR_MASK)
37497 /*! @} */
37498 
37499 /*! @name SITXIDR0 - Station interface transmit interrupt detect register 0 */
37500 /*! @{ */
37501 
37502 #define ENETC_SI_SITXIDR0_TXT0_MASK              (0x1U)
37503 #define ENETC_SI_SITXIDR0_TXT0_SHIFT             (0U)
37504 #define ENETC_SI_SITXIDR0_TXT0(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT0_SHIFT)) & ENETC_SI_SITXIDR0_TXT0_MASK)
37505 
37506 #define ENETC_SI_SITXIDR0_TXT1_MASK              (0x2U)
37507 #define ENETC_SI_SITXIDR0_TXT1_SHIFT             (1U)
37508 #define ENETC_SI_SITXIDR0_TXT1(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT1_SHIFT)) & ENETC_SI_SITXIDR0_TXT1_MASK)
37509 
37510 #define ENETC_SI_SITXIDR0_TXT2_MASK              (0x4U)
37511 #define ENETC_SI_SITXIDR0_TXT2_SHIFT             (2U)
37512 #define ENETC_SI_SITXIDR0_TXT2(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT2_SHIFT)) & ENETC_SI_SITXIDR0_TXT2_MASK)
37513 
37514 #define ENETC_SI_SITXIDR0_TXT3_MASK              (0x8U)
37515 #define ENETC_SI_SITXIDR0_TXT3_SHIFT             (3U)
37516 #define ENETC_SI_SITXIDR0_TXT3(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT3_SHIFT)) & ENETC_SI_SITXIDR0_TXT3_MASK)
37517 
37518 #define ENETC_SI_SITXIDR0_TXT4_MASK              (0x10U)
37519 #define ENETC_SI_SITXIDR0_TXT4_SHIFT             (4U)
37520 #define ENETC_SI_SITXIDR0_TXT4(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT4_SHIFT)) & ENETC_SI_SITXIDR0_TXT4_MASK)
37521 
37522 #define ENETC_SI_SITXIDR0_TXT5_MASK              (0x20U)
37523 #define ENETC_SI_SITXIDR0_TXT5_SHIFT             (5U)
37524 #define ENETC_SI_SITXIDR0_TXT5(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT5_SHIFT)) & ENETC_SI_SITXIDR0_TXT5_MASK)
37525 
37526 #define ENETC_SI_SITXIDR0_TXT6_MASK              (0x40U)
37527 #define ENETC_SI_SITXIDR0_TXT6_SHIFT             (6U)
37528 #define ENETC_SI_SITXIDR0_TXT6(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT6_SHIFT)) & ENETC_SI_SITXIDR0_TXT6_MASK)
37529 
37530 #define ENETC_SI_SITXIDR0_TXT7_MASK              (0x80U)
37531 #define ENETC_SI_SITXIDR0_TXT7_SHIFT             (7U)
37532 #define ENETC_SI_SITXIDR0_TXT7(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT7_SHIFT)) & ENETC_SI_SITXIDR0_TXT7_MASK)
37533 
37534 #define ENETC_SI_SITXIDR0_TXT8_MASK              (0x100U)
37535 #define ENETC_SI_SITXIDR0_TXT8_SHIFT             (8U)
37536 #define ENETC_SI_SITXIDR0_TXT8(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT8_SHIFT)) & ENETC_SI_SITXIDR0_TXT8_MASK)
37537 
37538 #define ENETC_SI_SITXIDR0_TXT9_MASK              (0x200U)
37539 #define ENETC_SI_SITXIDR0_TXT9_SHIFT             (9U)
37540 #define ENETC_SI_SITXIDR0_TXT9(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT9_SHIFT)) & ENETC_SI_SITXIDR0_TXT9_MASK)
37541 
37542 #define ENETC_SI_SITXIDR0_TXT10_MASK             (0x400U)
37543 #define ENETC_SI_SITXIDR0_TXT10_SHIFT            (10U)
37544 #define ENETC_SI_SITXIDR0_TXT10(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT10_SHIFT)) & ENETC_SI_SITXIDR0_TXT10_MASK)
37545 
37546 #define ENETC_SI_SITXIDR0_TXT11_MASK             (0x800U)
37547 #define ENETC_SI_SITXIDR0_TXT11_SHIFT            (11U)
37548 #define ENETC_SI_SITXIDR0_TXT11(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT11_SHIFT)) & ENETC_SI_SITXIDR0_TXT11_MASK)
37549 
37550 #define ENETC_SI_SITXIDR0_TXT12_MASK             (0x1000U)
37551 #define ENETC_SI_SITXIDR0_TXT12_SHIFT            (12U)
37552 #define ENETC_SI_SITXIDR0_TXT12(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT12_SHIFT)) & ENETC_SI_SITXIDR0_TXT12_MASK)
37553 
37554 #define ENETC_SI_SITXIDR0_TXT13_MASK             (0x2000U)
37555 #define ENETC_SI_SITXIDR0_TXT13_SHIFT            (13U)
37556 #define ENETC_SI_SITXIDR0_TXT13(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT13_SHIFT)) & ENETC_SI_SITXIDR0_TXT13_MASK)
37557 
37558 #define ENETC_SI_SITXIDR0_TXF0_MASK              (0x10000U)
37559 #define ENETC_SI_SITXIDR0_TXF0_SHIFT             (16U)
37560 #define ENETC_SI_SITXIDR0_TXF0(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF0_SHIFT)) & ENETC_SI_SITXIDR0_TXF0_MASK)
37561 
37562 #define ENETC_SI_SITXIDR0_TXF1_MASK              (0x20000U)
37563 #define ENETC_SI_SITXIDR0_TXF1_SHIFT             (17U)
37564 #define ENETC_SI_SITXIDR0_TXF1(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF1_SHIFT)) & ENETC_SI_SITXIDR0_TXF1_MASK)
37565 
37566 #define ENETC_SI_SITXIDR0_TXF2_MASK              (0x40000U)
37567 #define ENETC_SI_SITXIDR0_TXF2_SHIFT             (18U)
37568 #define ENETC_SI_SITXIDR0_TXF2(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF2_SHIFT)) & ENETC_SI_SITXIDR0_TXF2_MASK)
37569 
37570 #define ENETC_SI_SITXIDR0_TXF3_MASK              (0x80000U)
37571 #define ENETC_SI_SITXIDR0_TXF3_SHIFT             (19U)
37572 #define ENETC_SI_SITXIDR0_TXF3(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF3_SHIFT)) & ENETC_SI_SITXIDR0_TXF3_MASK)
37573 
37574 #define ENETC_SI_SITXIDR0_TXF4_MASK              (0x100000U)
37575 #define ENETC_SI_SITXIDR0_TXF4_SHIFT             (20U)
37576 #define ENETC_SI_SITXIDR0_TXF4(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF4_SHIFT)) & ENETC_SI_SITXIDR0_TXF4_MASK)
37577 
37578 #define ENETC_SI_SITXIDR0_TXF5_MASK              (0x200000U)
37579 #define ENETC_SI_SITXIDR0_TXF5_SHIFT             (21U)
37580 #define ENETC_SI_SITXIDR0_TXF5(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF5_SHIFT)) & ENETC_SI_SITXIDR0_TXF5_MASK)
37581 
37582 #define ENETC_SI_SITXIDR0_TXF6_MASK              (0x400000U)
37583 #define ENETC_SI_SITXIDR0_TXF6_SHIFT             (22U)
37584 #define ENETC_SI_SITXIDR0_TXF6(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF6_SHIFT)) & ENETC_SI_SITXIDR0_TXF6_MASK)
37585 
37586 #define ENETC_SI_SITXIDR0_TXF7_MASK              (0x800000U)
37587 #define ENETC_SI_SITXIDR0_TXF7_SHIFT             (23U)
37588 #define ENETC_SI_SITXIDR0_TXF7(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF7_SHIFT)) & ENETC_SI_SITXIDR0_TXF7_MASK)
37589 
37590 #define ENETC_SI_SITXIDR0_TXF8_MASK              (0x1000000U)
37591 #define ENETC_SI_SITXIDR0_TXF8_SHIFT             (24U)
37592 #define ENETC_SI_SITXIDR0_TXF8(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF8_SHIFT)) & ENETC_SI_SITXIDR0_TXF8_MASK)
37593 
37594 #define ENETC_SI_SITXIDR0_TXF9_MASK              (0x2000000U)
37595 #define ENETC_SI_SITXIDR0_TXF9_SHIFT             (25U)
37596 #define ENETC_SI_SITXIDR0_TXF9(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF9_SHIFT)) & ENETC_SI_SITXIDR0_TXF9_MASK)
37597 
37598 #define ENETC_SI_SITXIDR0_TXF10_MASK             (0x4000000U)
37599 #define ENETC_SI_SITXIDR0_TXF10_SHIFT            (26U)
37600 #define ENETC_SI_SITXIDR0_TXF10(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF10_SHIFT)) & ENETC_SI_SITXIDR0_TXF10_MASK)
37601 
37602 #define ENETC_SI_SITXIDR0_TXF11_MASK             (0x8000000U)
37603 #define ENETC_SI_SITXIDR0_TXF11_SHIFT            (27U)
37604 #define ENETC_SI_SITXIDR0_TXF11(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF11_SHIFT)) & ENETC_SI_SITXIDR0_TXF11_MASK)
37605 
37606 #define ENETC_SI_SITXIDR0_TXF12_MASK             (0x10000000U)
37607 #define ENETC_SI_SITXIDR0_TXF12_SHIFT            (28U)
37608 #define ENETC_SI_SITXIDR0_TXF12(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF12_SHIFT)) & ENETC_SI_SITXIDR0_TXF12_MASK)
37609 
37610 #define ENETC_SI_SITXIDR0_TXF13_MASK             (0x20000000U)
37611 #define ENETC_SI_SITXIDR0_TXF13_SHIFT            (29U)
37612 #define ENETC_SI_SITXIDR0_TXF13(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF13_SHIFT)) & ENETC_SI_SITXIDR0_TXF13_MASK)
37613 /*! @} */
37614 
37615 /*! @name SIRXIDR0 - Station interface receive interrupt detect register 0 */
37616 /*! @{ */
37617 
37618 #define ENETC_SI_SIRXIDR0_RX0_MASK               (0x1U)
37619 #define ENETC_SI_SIRXIDR0_RX0_SHIFT              (0U)
37620 #define ENETC_SI_SIRXIDR0_RX0(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX0_SHIFT)) & ENETC_SI_SIRXIDR0_RX0_MASK)
37621 
37622 #define ENETC_SI_SIRXIDR0_RX1_MASK               (0x2U)
37623 #define ENETC_SI_SIRXIDR0_RX1_SHIFT              (1U)
37624 #define ENETC_SI_SIRXIDR0_RX1(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX1_SHIFT)) & ENETC_SI_SIRXIDR0_RX1_MASK)
37625 
37626 #define ENETC_SI_SIRXIDR0_RX2_MASK               (0x4U)
37627 #define ENETC_SI_SIRXIDR0_RX2_SHIFT              (2U)
37628 #define ENETC_SI_SIRXIDR0_RX2(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX2_SHIFT)) & ENETC_SI_SIRXIDR0_RX2_MASK)
37629 
37630 #define ENETC_SI_SIRXIDR0_RX3_MASK               (0x8U)
37631 #define ENETC_SI_SIRXIDR0_RX3_SHIFT              (3U)
37632 #define ENETC_SI_SIRXIDR0_RX3(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX3_SHIFT)) & ENETC_SI_SIRXIDR0_RX3_MASK)
37633 
37634 #define ENETC_SI_SIRXIDR0_RX4_MASK               (0x10U)
37635 #define ENETC_SI_SIRXIDR0_RX4_SHIFT              (4U)
37636 #define ENETC_SI_SIRXIDR0_RX4(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX4_SHIFT)) & ENETC_SI_SIRXIDR0_RX4_MASK)
37637 
37638 #define ENETC_SI_SIRXIDR0_RX5_MASK               (0x20U)
37639 #define ENETC_SI_SIRXIDR0_RX5_SHIFT              (5U)
37640 #define ENETC_SI_SIRXIDR0_RX5(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX5_SHIFT)) & ENETC_SI_SIRXIDR0_RX5_MASK)
37641 
37642 #define ENETC_SI_SIRXIDR0_RX6_MASK               (0x40U)
37643 #define ENETC_SI_SIRXIDR0_RX6_SHIFT              (6U)
37644 #define ENETC_SI_SIRXIDR0_RX6(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX6_SHIFT)) & ENETC_SI_SIRXIDR0_RX6_MASK)
37645 
37646 #define ENETC_SI_SIRXIDR0_RX7_MASK               (0x80U)
37647 #define ENETC_SI_SIRXIDR0_RX7_SHIFT              (7U)
37648 #define ENETC_SI_SIRXIDR0_RX7(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX7_SHIFT)) & ENETC_SI_SIRXIDR0_RX7_MASK)
37649 
37650 #define ENETC_SI_SIRXIDR0_RX8_MASK               (0x100U)
37651 #define ENETC_SI_SIRXIDR0_RX8_SHIFT              (8U)
37652 #define ENETC_SI_SIRXIDR0_RX8(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX8_SHIFT)) & ENETC_SI_SIRXIDR0_RX8_MASK)
37653 
37654 #define ENETC_SI_SIRXIDR0_RX9_MASK               (0x200U)
37655 #define ENETC_SI_SIRXIDR0_RX9_SHIFT              (9U)
37656 #define ENETC_SI_SIRXIDR0_RX9(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX9_SHIFT)) & ENETC_SI_SIRXIDR0_RX9_MASK)
37657 
37658 #define ENETC_SI_SIRXIDR0_RX10_MASK              (0x400U)
37659 #define ENETC_SI_SIRXIDR0_RX10_SHIFT             (10U)
37660 #define ENETC_SI_SIRXIDR0_RX10(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX10_SHIFT)) & ENETC_SI_SIRXIDR0_RX10_MASK)
37661 
37662 #define ENETC_SI_SIRXIDR0_RX11_MASK              (0x800U)
37663 #define ENETC_SI_SIRXIDR0_RX11_SHIFT             (11U)
37664 #define ENETC_SI_SIRXIDR0_RX11(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX11_SHIFT)) & ENETC_SI_SIRXIDR0_RX11_MASK)
37665 
37666 #define ENETC_SI_SIRXIDR0_RX12_MASK              (0x1000U)
37667 #define ENETC_SI_SIRXIDR0_RX12_SHIFT             (12U)
37668 #define ENETC_SI_SIRXIDR0_RX12(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX12_SHIFT)) & ENETC_SI_SIRXIDR0_RX12_MASK)
37669 
37670 #define ENETC_SI_SIRXIDR0_RX13_MASK              (0x2000U)
37671 #define ENETC_SI_SIRXIDR0_RX13_SHIFT             (13U)
37672 #define ENETC_SI_SIRXIDR0_RX13(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX13_SHIFT)) & ENETC_SI_SIRXIDR0_RX13_MASK)
37673 /*! @} */
37674 
37675 /*! @name SIMSIVR - Station interface MSI-X vector register */
37676 /*! @{ */
37677 
37678 #define ENETC_SI_SIMSIVR_VECTOR_MASK             (0x3FU)
37679 #define ENETC_SI_SIMSIVR_VECTOR_SHIFT            (0U)
37680 #define ENETC_SI_SIMSIVR_VECTOR(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSIVR_VECTOR_SHIFT)) & ENETC_SI_SIMSIVR_VECTOR_MASK)
37681 /*! @} */
37682 
37683 /*! @name SICMSIVR - Station interface command MSI-X vector register */
37684 /*! @{ */
37685 
37686 #define ENETC_SI_SICMSIVR_VECTOR_MASK            (0x3FU)
37687 #define ENETC_SI_SICMSIVR_VECTOR_SHIFT           (0U)
37688 #define ENETC_SI_SICMSIVR_VECTOR(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMSIVR_VECTOR_SHIFT)) & ENETC_SI_SICMSIVR_VECTOR_MASK)
37689 /*! @} */
37690 
37691 /*! @name SITMRIER - Station interface timer interrupt enable register */
37692 /*! @{ */
37693 
37694 #define ENETC_SI_SITMRIER_SYNCE_MASK             (0x1U)
37695 #define ENETC_SI_SITMRIER_SYNCE_SHIFT            (0U)
37696 #define ENETC_SI_SITMRIER_SYNCE(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRIER_SYNCE_SHIFT)) & ENETC_SI_SITMRIER_SYNCE_MASK)
37697 /*! @} */
37698 
37699 /*! @name SITMRIDR - Station interface timer interrupt detect register */
37700 /*! @{ */
37701 
37702 #define ENETC_SI_SITMRIDR_SYNC_MASK              (0x1U)
37703 #define ENETC_SI_SITMRIDR_SYNC_SHIFT             (0U)
37704 #define ENETC_SI_SITMRIDR_SYNC(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRIDR_SYNC_SHIFT)) & ENETC_SI_SITMRIDR_SYNC_MASK)
37705 /*! @} */
37706 
37707 /*! @name SITMRMSIVR - Station interface timer MSI-X vector register */
37708 /*! @{ */
37709 
37710 #define ENETC_SI_SITMRMSIVR_VECTOR_MASK          (0x3FU)
37711 #define ENETC_SI_SITMRMSIVR_VECTOR_SHIFT         (0U)
37712 #define ENETC_SI_SITMRMSIVR_VECTOR(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRMSIVR_VECTOR_SHIFT)) & ENETC_SI_SITMRMSIVR_VECTOR_MASK)
37713 /*! @} */
37714 
37715 /*! @name SIMSITRVR - Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 9 vector register */
37716 /*! @{ */
37717 
37718 #define ENETC_SI_SIMSITRVR_VECTOR_MASK           (0x3FU)
37719 #define ENETC_SI_SIMSITRVR_VECTOR_SHIFT          (0U)
37720 #define ENETC_SI_SIMSITRVR_VECTOR(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSITRVR_VECTOR_SHIFT)) & ENETC_SI_SIMSITRVR_VECTOR_MASK)
37721 /*! @} */
37722 
37723 /* The count of ENETC_SI_SIMSITRVR */
37724 #define ENETC_SI_SIMSITRVR_COUNT                 (10U)
37725 
37726 /*! @name SIMSIRRVR - Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 9 vector register */
37727 /*! @{ */
37728 
37729 #define ENETC_SI_SIMSIRRVR_VECTOR_MASK           (0x3FU)
37730 #define ENETC_SI_SIMSIRRVR_VECTOR_SHIFT          (0U)
37731 #define ENETC_SI_SIMSIRRVR_VECTOR(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSIRRVR_VECTOR_SHIFT)) & ENETC_SI_SIMSIRRVR_VECTOR_MASK)
37732 /*! @} */
37733 
37734 /* The count of ENETC_SI_SIMSIRRVR */
37735 #define ENETC_SI_SIMSIRRVR_COUNT                 (10U)
37736 
37737 /*! @name SICMECR - Station interface correctable memory error configuration register */
37738 /*! @{ */
37739 
37740 #define ENETC_SI_SICMECR_THRESHOLD_MASK          (0xFFU)
37741 #define ENETC_SI_SICMECR_THRESHOLD_SHIFT         (0U)
37742 /*! THRESHOLD - Threshold */
37743 #define ENETC_SI_SICMECR_THRESHOLD(x)            (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMECR_THRESHOLD_SHIFT)) & ENETC_SI_SICMECR_THRESHOLD_MASK)
37744 /*! @} */
37745 
37746 /*! @name SICMESR - Station interface correctable memory error status register */
37747 /*! @{ */
37748 
37749 #define ENETC_SI_SICMESR_MEM_ID_MASK             (0x1F0000U)
37750 #define ENETC_SI_SICMESR_MEM_ID_SHIFT            (16U)
37751 /*! MEM_ID - Memory ID */
37752 #define ENETC_SI_SICMESR_MEM_ID(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMESR_MEM_ID_SHIFT)) & ENETC_SI_SICMESR_MEM_ID_MASK)
37753 
37754 #define ENETC_SI_SICMESR_SBEE_MASK               (0x80000000U)
37755 #define ENETC_SI_SICMESR_SBEE_SHIFT              (31U)
37756 /*! SBEE - Single-bit ECC error */
37757 #define ENETC_SI_SICMESR_SBEE(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMESR_SBEE_SHIFT)) & ENETC_SI_SICMESR_SBEE_MASK)
37758 /*! @} */
37759 
37760 /*! @name SICMECTR - Station interface correctable memory error count register */
37761 /*! @{ */
37762 
37763 #define ENETC_SI_SICMECTR_COUNT_MASK             (0xFFU)
37764 #define ENETC_SI_SICMECTR_COUNT_SHIFT            (0U)
37765 /*! COUNT - Count */
37766 #define ENETC_SI_SICMECTR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMECTR_COUNT_SHIFT)) & ENETC_SI_SICMECTR_COUNT_MASK)
37767 /*! @} */
37768 
37769 /*! @name SIUPECR - Station interface uncorrectable programming error configuration register */
37770 /*! @{ */
37771 
37772 #define ENETC_SI_SIUPECR_RD_MASK                 (0x80000000U)
37773 #define ENETC_SI_SIUPECR_RD_SHIFT                (31U)
37774 /*! RD - Report disable */
37775 #define ENETC_SI_SIUPECR_RD(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPECR_RD_SHIFT)) & ENETC_SI_SIUPECR_RD_MASK)
37776 /*! @} */
37777 
37778 /*! @name SIUPESR - Station interface uncorrectable programming error status register */
37779 /*! @{ */
37780 
37781 #define ENETC_SI_SIUPESR_DROP_SI_EN_MASK         (0x1U)
37782 #define ENETC_SI_SIUPESR_DROP_SI_EN_SHIFT        (0U)
37783 #define ENETC_SI_SIUPESR_DROP_SI_EN(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_SI_EN_SHIFT)) & ENETC_SI_SIUPESR_DROP_SI_EN_MASK)
37784 
37785 #define ENETC_SI_SIUPESR_DROP_RING_EN_MASK       (0x2U)
37786 #define ENETC_SI_SIUPESR_DROP_RING_EN_SHIFT      (1U)
37787 #define ENETC_SI_SIUPESR_DROP_RING_EN(x)         (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_RING_EN_SHIFT)) & ENETC_SI_SIUPESR_DROP_RING_EN_MASK)
37788 
37789 #define ENETC_SI_SIUPESR_DROP_RING_SEL_MASK      (0x8U)
37790 #define ENETC_SI_SIUPESR_DROP_RING_SEL_SHIFT     (3U)
37791 #define ENETC_SI_SIUPESR_DROP_RING_SEL(x)        (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_RING_SEL_SHIFT)) & ENETC_SI_SIUPESR_DROP_RING_SEL_MASK)
37792 
37793 #define ENETC_SI_SIUPESR_M_MASK                  (0x40000000U)
37794 #define ENETC_SI_SIUPESR_M_SHIFT                 (30U)
37795 /*! M - Multiple */
37796 #define ENETC_SI_SIUPESR_M(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_M_SHIFT)) & ENETC_SI_SIUPESR_M_MASK)
37797 
37798 #define ENETC_SI_SIUPESR_PE_MASK                 (0x80000000U)
37799 #define ENETC_SI_SIUPESR_PE_SHIFT                (31U)
37800 /*! PE - Programming error */
37801 #define ENETC_SI_SIUPESR_PE(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_PE_SHIFT)) & ENETC_SI_SIUPESR_PE_MASK)
37802 /*! @} */
37803 
37804 /*! @name SIUPECTR - Station interface uncorrectable programming error count register */
37805 /*! @{ */
37806 
37807 #define ENETC_SI_SIUPECTR_COUNT_MASK             (0xFFFFFFFFU)
37808 #define ENETC_SI_SIUPECTR_COUNT_SHIFT            (0U)
37809 /*! COUNT - Count */
37810 #define ENETC_SI_SIUPECTR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPECTR_COUNT_SHIFT)) & ENETC_SI_SIUPECTR_COUNT_MASK)
37811 /*! @} */
37812 
37813 /*! @name SIUNSBECR - Station interface uncorrectable non-fatal system bus error configuration register */
37814 /*! @{ */
37815 
37816 #define ENETC_SI_SIUNSBECR_THRESHOLD_MASK        (0xFFU)
37817 #define ENETC_SI_SIUNSBECR_THRESHOLD_SHIFT       (0U)
37818 /*! THRESHOLD - Threshold */
37819 #define ENETC_SI_SIUNSBECR_THRESHOLD(x)          (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBECR_THRESHOLD_SHIFT)) & ENETC_SI_SIUNSBECR_THRESHOLD_MASK)
37820 /*! @} */
37821 
37822 /*! @name SIUNSBESR - Station interface uncorrectable non-fatal system bus error status register */
37823 /*! @{ */
37824 
37825 #define ENETC_SI_SIUNSBESR_SB_ID_MASK            (0xFU)
37826 #define ENETC_SI_SIUNSBESR_SB_ID_SHIFT           (0U)
37827 /*! SB_ID - System Bus ID */
37828 #define ENETC_SI_SIUNSBESR_SB_ID(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBESR_SB_ID_SHIFT)) & ENETC_SI_SIUNSBESR_SB_ID_MASK)
37829 
37830 #define ENETC_SI_SIUNSBESR_SBE_MASK              (0x80000000U)
37831 #define ENETC_SI_SIUNSBESR_SBE_SHIFT             (31U)
37832 /*! SBE - System bus error */
37833 #define ENETC_SI_SIUNSBESR_SBE(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBESR_SBE_SHIFT)) & ENETC_SI_SIUNSBESR_SBE_MASK)
37834 /*! @} */
37835 
37836 /*! @name SIUNSBECTR - Station interface uncorrectable non-fatal system bus error count register */
37837 /*! @{ */
37838 
37839 #define ENETC_SI_SIUNSBECTR_COUNT_MASK           (0xFFU)
37840 #define ENETC_SI_SIUNSBECTR_COUNT_SHIFT          (0U)
37841 /*! COUNT - Count */
37842 #define ENETC_SI_SIUNSBECTR_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBECTR_COUNT_SHIFT)) & ENETC_SI_SIUNSBECTR_COUNT_MASK)
37843 /*! @} */
37844 
37845 /*! @name SIUFSBECR - Station interface uncorrectable fatal system bus error configuration register */
37846 /*! @{ */
37847 
37848 #define ENETC_SI_SIUFSBECR_RD_MASK               (0x80000000U)
37849 #define ENETC_SI_SIUFSBECR_RD_SHIFT              (31U)
37850 /*! RD - Report disable */
37851 #define ENETC_SI_SIUFSBECR_RD(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBECR_RD_SHIFT)) & ENETC_SI_SIUFSBECR_RD_MASK)
37852 /*! @} */
37853 
37854 /*! @name SIUFSBESR - Station interface uncorrectable fatal system bus error status register */
37855 /*! @{ */
37856 
37857 #define ENETC_SI_SIUFSBESR_SB_ID_MASK            (0xFU)
37858 #define ENETC_SI_SIUFSBESR_SB_ID_SHIFT           (0U)
37859 /*! SB_ID - System Bus ID */
37860 #define ENETC_SI_SIUFSBESR_SB_ID(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_SB_ID_SHIFT)) & ENETC_SI_SIUFSBESR_SB_ID_MASK)
37861 
37862 #define ENETC_SI_SIUFSBESR_M_MASK                (0x40000000U)
37863 #define ENETC_SI_SIUFSBESR_M_SHIFT               (30U)
37864 /*! M - Multiple */
37865 #define ENETC_SI_SIUFSBESR_M(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_M_SHIFT)) & ENETC_SI_SIUFSBESR_M_MASK)
37866 
37867 #define ENETC_SI_SIUFSBESR_SBE_MASK              (0x80000000U)
37868 #define ENETC_SI_SIUFSBESR_SBE_SHIFT             (31U)
37869 /*! SBE - System bus error */
37870 #define ENETC_SI_SIUFSBESR_SBE(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_SBE_SHIFT)) & ENETC_SI_SIUFSBESR_SBE_MASK)
37871 /*! @} */
37872 
37873 /*! @name SIUNMECR - Station interface uncorrectable non-fatal memory error configuration register */
37874 /*! @{ */
37875 
37876 #define ENETC_SI_SIUNMECR_THRESHOLD_MASK         (0xFFU)
37877 #define ENETC_SI_SIUNMECR_THRESHOLD_SHIFT        (0U)
37878 /*! THRESHOLD - Threshold */
37879 #define ENETC_SI_SIUNMECR_THRESHOLD(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECR_THRESHOLD_SHIFT)) & ENETC_SI_SIUNMECR_THRESHOLD_MASK)
37880 
37881 #define ENETC_SI_SIUNMECR_RD_MASK                (0x80000000U)
37882 #define ENETC_SI_SIUNMECR_RD_SHIFT               (31U)
37883 /*! RD - Report disable */
37884 #define ENETC_SI_SIUNMECR_RD(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECR_RD_SHIFT)) & ENETC_SI_SIUNMECR_RD_MASK)
37885 /*! @} */
37886 
37887 /*! @name SIUNMESR0 - Station interface uncorrectable non-fatal memory error status register 0 */
37888 /*! @{ */
37889 
37890 #define ENETC_SI_SIUNMESR0_SYNDROME_MASK         (0x7FFU)
37891 #define ENETC_SI_SIUNMESR0_SYNDROME_SHIFT        (0U)
37892 /*! SYNDROME - Syndrome */
37893 #define ENETC_SI_SIUNMESR0_SYNDROME(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_SYNDROME_SHIFT)) & ENETC_SI_SIUNMESR0_SYNDROME_MASK)
37894 
37895 #define ENETC_SI_SIUNMESR0_MEM_ID_MASK           (0x1F0000U)
37896 #define ENETC_SI_SIUNMESR0_MEM_ID_SHIFT          (16U)
37897 /*! MEM_ID - Memory ID */
37898 #define ENETC_SI_SIUNMESR0_MEM_ID(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_MEM_ID_SHIFT)) & ENETC_SI_SIUNMESR0_MEM_ID_MASK)
37899 
37900 #define ENETC_SI_SIUNMESR0_MBEE_MASK             (0x80000000U)
37901 #define ENETC_SI_SIUNMESR0_MBEE_SHIFT            (31U)
37902 /*! MBEE - Multi-bit ECC error */
37903 #define ENETC_SI_SIUNMESR0_MBEE(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_MBEE_SHIFT)) & ENETC_SI_SIUNMESR0_MBEE_MASK)
37904 /*! @} */
37905 
37906 /*! @name SIUNMESR1 - Station interface uncorrectable non-fatal memory error status register 1 */
37907 /*! @{ */
37908 
37909 #define ENETC_SI_SIUNMESR1_ADDR_MASK             (0xFFFFFFFFU)
37910 #define ENETC_SI_SIUNMESR1_ADDR_SHIFT            (0U)
37911 /*! ADDR - Address */
37912 #define ENETC_SI_SIUNMESR1_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR1_ADDR_SHIFT)) & ENETC_SI_SIUNMESR1_ADDR_MASK)
37913 /*! @} */
37914 
37915 /*! @name SIUNMECTR - Station interface uncorrectable non-fatal memory error count register */
37916 /*! @{ */
37917 
37918 #define ENETC_SI_SIUNMECTR_COUNT_MASK            (0xFFU)
37919 #define ENETC_SI_SIUNMECTR_COUNT_SHIFT           (0U)
37920 /*! COUNT - Count */
37921 #define ENETC_SI_SIUNMECTR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECTR_COUNT_SHIFT)) & ENETC_SI_SIUNMECTR_COUNT_MASK)
37922 /*! @} */
37923 
37924 /*! @name SIUFMECR - Station interface uncorrectable fatal memory error configuration register */
37925 /*! @{ */
37926 
37927 #define ENETC_SI_SIUFMECR_RD_MASK                (0x80000000U)
37928 #define ENETC_SI_SIUFMECR_RD_SHIFT               (31U)
37929 /*! RD - Report disable */
37930 #define ENETC_SI_SIUFMECR_RD(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMECR_RD_SHIFT)) & ENETC_SI_SIUFMECR_RD_MASK)
37931 /*! @} */
37932 
37933 /*! @name SIUFMESR0 - Station interface uncorrectable fatal memory error status register 0 */
37934 /*! @{ */
37935 
37936 #define ENETC_SI_SIUFMESR0_SYNDROME_MASK         (0x7FFU)
37937 #define ENETC_SI_SIUFMESR0_SYNDROME_SHIFT        (0U)
37938 /*! SYNDROME - Syndrome */
37939 #define ENETC_SI_SIUFMESR0_SYNDROME(x)           (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_SYNDROME_SHIFT)) & ENETC_SI_SIUFMESR0_SYNDROME_MASK)
37940 
37941 #define ENETC_SI_SIUFMESR0_MEM_ID_MASK           (0x1F0000U)
37942 #define ENETC_SI_SIUFMESR0_MEM_ID_SHIFT          (16U)
37943 /*! MEM_ID - Memory ID */
37944 #define ENETC_SI_SIUFMESR0_MEM_ID(x)             (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_MEM_ID_SHIFT)) & ENETC_SI_SIUFMESR0_MEM_ID_MASK)
37945 
37946 #define ENETC_SI_SIUFMESR0_M_MASK                (0x40000000U)
37947 #define ENETC_SI_SIUFMESR0_M_SHIFT               (30U)
37948 /*! M - Multiple */
37949 #define ENETC_SI_SIUFMESR0_M(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_M_SHIFT)) & ENETC_SI_SIUFMESR0_M_MASK)
37950 
37951 #define ENETC_SI_SIUFMESR0_MBEE_MASK             (0x80000000U)
37952 #define ENETC_SI_SIUFMESR0_MBEE_SHIFT            (31U)
37953 /*! MBEE - Multi-bit ECC error */
37954 #define ENETC_SI_SIUFMESR0_MBEE(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_MBEE_SHIFT)) & ENETC_SI_SIUFMESR0_MBEE_MASK)
37955 /*! @} */
37956 
37957 /*! @name SIUFMESR1 - Station interface uncorrectable fatal memory error status register 1 */
37958 /*! @{ */
37959 
37960 #define ENETC_SI_SIUFMESR1_ADDR_MASK             (0xFFFFFFFFU)
37961 #define ENETC_SI_SIUFMESR1_ADDR_SHIFT            (0U)
37962 /*! ADDR - Address */
37963 #define ENETC_SI_SIUFMESR1_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR1_ADDR_SHIFT)) & ENETC_SI_SIUFMESR1_ADDR_MASK)
37964 /*! @} */
37965 
37966 /*! @name SIMAFTCAPR - Station interface MAC address filter table capability register */
37967 /*! @{ */
37968 
37969 #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_MASK    (0xFFU)
37970 #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT   (0U)
37971 #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE(x)      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT)) & ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_MASK)
37972 /*! @} */
37973 
37974 /*! @name SIVFTCAPR - Station interface VLAN filter table capability register */
37975 /*! @{ */
37976 
37977 #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_MASK     (0xFFU)
37978 #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_SHIFT    (0U)
37979 #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE(x)       (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_SHIFT)) & ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_MASK)
37980 /*! @} */
37981 
37982 /*! @name TBMR - Tx BDR 0 mode register..Tx BDR 9 mode register */
37983 /*! @{ */
37984 
37985 #define ENETC_SI_TBMR_PRIO_MASK                  (0x7U)
37986 #define ENETC_SI_TBMR_PRIO_SHIFT                 (0U)
37987 #define ENETC_SI_TBMR_PRIO(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_PRIO_SHIFT)) & ENETC_SI_TBMR_PRIO_MASK)
37988 
37989 #define ENETC_SI_TBMR_WRR_MASK                   (0x70U)
37990 #define ENETC_SI_TBMR_WRR_SHIFT                  (4U)
37991 #define ENETC_SI_TBMR_WRR(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_WRR_SHIFT)) & ENETC_SI_TBMR_WRR_MASK)
37992 
37993 #define ENETC_SI_TBMR_CRC_MASK                   (0x100U)
37994 #define ENETC_SI_TBMR_CRC_SHIFT                  (8U)
37995 #define ENETC_SI_TBMR_CRC(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_CRC_SHIFT)) & ENETC_SI_TBMR_CRC_MASK)
37996 
37997 #define ENETC_SI_TBMR_VIH_MASK                   (0x200U)
37998 #define ENETC_SI_TBMR_VIH_SHIFT                  (9U)
37999 #define ENETC_SI_TBMR_VIH(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_VIH_SHIFT)) & ENETC_SI_TBMR_VIH_MASK)
38000 
38001 #define ENETC_SI_TBMR_EN_MASK                    (0x80000000U)
38002 #define ENETC_SI_TBMR_EN_SHIFT                   (31U)
38003 #define ENETC_SI_TBMR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_EN_SHIFT)) & ENETC_SI_TBMR_EN_MASK)
38004 /*! @} */
38005 
38006 /* The count of ENETC_SI_TBMR */
38007 #define ENETC_SI_TBMR_COUNT                      (10U)
38008 
38009 /*! @name TBSR - Tx BDR 0 status register..Tx BDR 9 status register */
38010 /*! @{ */
38011 
38012 #define ENETC_SI_TBSR_BUSY_MASK                  (0x1U)
38013 #define ENETC_SI_TBSR_BUSY_SHIFT                 (0U)
38014 #define ENETC_SI_TBSR_BUSY(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBSR_BUSY_SHIFT)) & ENETC_SI_TBSR_BUSY_MASK)
38015 
38016 #define ENETC_SI_TBSR_SBE_MASK                   (0x10000U)
38017 #define ENETC_SI_TBSR_SBE_SHIFT                  (16U)
38018 #define ENETC_SI_TBSR_SBE(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBSR_SBE_SHIFT)) & ENETC_SI_TBSR_SBE_MASK)
38019 /*! @} */
38020 
38021 /* The count of ENETC_SI_TBSR */
38022 #define ENETC_SI_TBSR_COUNT                      (10U)
38023 
38024 /*! @name TBBAR0 - Tx BDR 0 base address register 0..Tx BDR 9 base address register 0 */
38025 /*! @{ */
38026 
38027 #define ENETC_SI_TBBAR0_ADDRL_MASK               (0xFFFFFF80U)
38028 #define ENETC_SI_TBBAR0_ADDRL_SHIFT              (7U)
38029 #define ENETC_SI_TBBAR0_ADDRL(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBBAR0_ADDRL_SHIFT)) & ENETC_SI_TBBAR0_ADDRL_MASK)
38030 /*! @} */
38031 
38032 /* The count of ENETC_SI_TBBAR0 */
38033 #define ENETC_SI_TBBAR0_COUNT                    (10U)
38034 
38035 /*! @name TBBAR1 - Tx BDR 0 base address register 1..Tx BDR 9 base address register 1 */
38036 /*! @{ */
38037 
38038 #define ENETC_SI_TBBAR1_ADDRH_MASK               (0xFFFFFFFFU)
38039 #define ENETC_SI_TBBAR1_ADDRH_SHIFT              (0U)
38040 #define ENETC_SI_TBBAR1_ADDRH(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBBAR1_ADDRH_SHIFT)) & ENETC_SI_TBBAR1_ADDRH_MASK)
38041 /*! @} */
38042 
38043 /* The count of ENETC_SI_TBBAR1 */
38044 #define ENETC_SI_TBBAR1_COUNT                    (10U)
38045 
38046 /*! @name TBPIR - Tx BDR 0 producer index register..Tx BDR 9 producer index register */
38047 /*! @{ */
38048 
38049 #define ENETC_SI_TBPIR_BDR_INDEX_MASK            (0xFFFFU)
38050 #define ENETC_SI_TBPIR_BDR_INDEX_SHIFT           (0U)
38051 #define ENETC_SI_TBPIR_BDR_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBPIR_BDR_INDEX_SHIFT)) & ENETC_SI_TBPIR_BDR_INDEX_MASK)
38052 /*! @} */
38053 
38054 /* The count of ENETC_SI_TBPIR */
38055 #define ENETC_SI_TBPIR_COUNT                     (10U)
38056 
38057 /*! @name TBCIR - Tx BDR 0 consumer index register..Tx BDR 9 consumer index register */
38058 /*! @{ */
38059 
38060 #define ENETC_SI_TBCIR_BDR_INDEX_MASK            (0xFFFFU)
38061 #define ENETC_SI_TBCIR_BDR_INDEX_SHIFT           (0U)
38062 #define ENETC_SI_TBCIR_BDR_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBCIR_BDR_INDEX_SHIFT)) & ENETC_SI_TBCIR_BDR_INDEX_MASK)
38063 
38064 #define ENETC_SI_TBCIR_STAT_ID_MASK              (0xFFFF0000U)
38065 #define ENETC_SI_TBCIR_STAT_ID_SHIFT             (16U)
38066 #define ENETC_SI_TBCIR_STAT_ID(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBCIR_STAT_ID_SHIFT)) & ENETC_SI_TBCIR_STAT_ID_MASK)
38067 /*! @} */
38068 
38069 /* The count of ENETC_SI_TBCIR */
38070 #define ENETC_SI_TBCIR_COUNT                     (10U)
38071 
38072 /*! @name TBLENR - Tx BDR 0 length register..Tx BDR 9 length register */
38073 /*! @{ */
38074 
38075 #define ENETC_SI_TBLENR_LENGTH_MASK              (0x1FFF8U)
38076 #define ENETC_SI_TBLENR_LENGTH_SHIFT             (3U)
38077 #define ENETC_SI_TBLENR_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBLENR_LENGTH_SHIFT)) & ENETC_SI_TBLENR_LENGTH_MASK)
38078 /*! @} */
38079 
38080 /* The count of ENETC_SI_TBLENR */
38081 #define ENETC_SI_TBLENR_COUNT                    (10U)
38082 
38083 /*! @name TBIER - Tx BDR 0 interrupt enable register..Tx BDR 9 interrupt enable register */
38084 /*! @{ */
38085 
38086 #define ENETC_SI_TBIER_TXTIE_MASK                (0x1U)
38087 #define ENETC_SI_TBIER_TXTIE_SHIFT               (0U)
38088 #define ENETC_SI_TBIER_TXTIE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIER_TXTIE_SHIFT)) & ENETC_SI_TBIER_TXTIE_MASK)
38089 
38090 #define ENETC_SI_TBIER_TXFIE_MASK                (0x2U)
38091 #define ENETC_SI_TBIER_TXFIE_SHIFT               (1U)
38092 #define ENETC_SI_TBIER_TXFIE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIER_TXFIE_SHIFT)) & ENETC_SI_TBIER_TXFIE_MASK)
38093 /*! @} */
38094 
38095 /* The count of ENETC_SI_TBIER */
38096 #define ENETC_SI_TBIER_COUNT                     (10U)
38097 
38098 /*! @name TBIDR - Tx BDR 0 interrupt detect register..Tx BDR 9 interrupt detect register */
38099 /*! @{ */
38100 
38101 #define ENETC_SI_TBIDR_TXT_MASK                  (0x1U)
38102 #define ENETC_SI_TBIDR_TXT_SHIFT                 (0U)
38103 #define ENETC_SI_TBIDR_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIDR_TXT_SHIFT)) & ENETC_SI_TBIDR_TXT_MASK)
38104 
38105 #define ENETC_SI_TBIDR_TXF_MASK                  (0x2U)
38106 #define ENETC_SI_TBIDR_TXF_SHIFT                 (1U)
38107 #define ENETC_SI_TBIDR_TXF(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIDR_TXF_SHIFT)) & ENETC_SI_TBIDR_TXF_MASK)
38108 /*! @} */
38109 
38110 /* The count of ENETC_SI_TBIDR */
38111 #define ENETC_SI_TBIDR_COUNT                     (10U)
38112 
38113 /*! @name TBICR0 - Tx BDR 0 interrupt coalescing register 0..Tx BDR 9 interrupt coalescing register 0 */
38114 /*! @{ */
38115 
38116 #define ENETC_SI_TBICR0_ICPT_MASK                (0xFU)
38117 #define ENETC_SI_TBICR0_ICPT_SHIFT               (0U)
38118 #define ENETC_SI_TBICR0_ICPT(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR0_ICPT_SHIFT)) & ENETC_SI_TBICR0_ICPT_MASK)
38119 
38120 #define ENETC_SI_TBICR0_ICEN_MASK                (0x80000000U)
38121 #define ENETC_SI_TBICR0_ICEN_SHIFT               (31U)
38122 #define ENETC_SI_TBICR0_ICEN(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR0_ICEN_SHIFT)) & ENETC_SI_TBICR0_ICEN_MASK)
38123 /*! @} */
38124 
38125 /* The count of ENETC_SI_TBICR0 */
38126 #define ENETC_SI_TBICR0_COUNT                    (10U)
38127 
38128 /*! @name TBICR1 - Tx BDR 0 interrupt coalescing register 1..Tx BDR 9 interrupt coalescing register 1 */
38129 /*! @{ */
38130 
38131 #define ENETC_SI_TBICR1_ICTT_MASK                (0xFFFFFFFFU)
38132 #define ENETC_SI_TBICR1_ICTT_SHIFT               (0U)
38133 #define ENETC_SI_TBICR1_ICTT(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR1_ICTT_SHIFT)) & ENETC_SI_TBICR1_ICTT_MASK)
38134 /*! @} */
38135 
38136 /* The count of ENETC_SI_TBICR1 */
38137 #define ENETC_SI_TBICR1_COUNT                    (10U)
38138 
38139 /*! @name RBMR - Rx BDR 0 mode register..Rx BDR 9 mode register */
38140 /*! @{ */
38141 
38142 #define ENETC_SI_RBMR_AL_MASK                    (0x1U)
38143 #define ENETC_SI_RBMR_AL_SHIFT                   (0U)
38144 #define ENETC_SI_RBMR_AL(x)                      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_AL_SHIFT)) & ENETC_SI_RBMR_AL_MASK)
38145 
38146 #define ENETC_SI_RBMR_BDS_MASK                   (0x4U)
38147 #define ENETC_SI_RBMR_BDS_SHIFT                  (2U)
38148 #define ENETC_SI_RBMR_BDS(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_BDS_SHIFT)) & ENETC_SI_RBMR_BDS_MASK)
38149 
38150 #define ENETC_SI_RBMR_CM_MASK                    (0x10U)
38151 #define ENETC_SI_RBMR_CM_SHIFT                   (4U)
38152 #define ENETC_SI_RBMR_CM(x)                      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_CM_SHIFT)) & ENETC_SI_RBMR_CM_MASK)
38153 
38154 #define ENETC_SI_RBMR_VTE_MASK                   (0x20U)
38155 #define ENETC_SI_RBMR_VTE_SHIFT                  (5U)
38156 #define ENETC_SI_RBMR_VTE(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_VTE_SHIFT)) & ENETC_SI_RBMR_VTE_MASK)
38157 
38158 #define ENETC_SI_RBMR_VTPD_MASK                  (0x40U)
38159 #define ENETC_SI_RBMR_VTPD_SHIFT                 (6U)
38160 #define ENETC_SI_RBMR_VTPD(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_VTPD_SHIFT)) & ENETC_SI_RBMR_VTPD_MASK)
38161 
38162 #define ENETC_SI_RBMR_CRC_MASK                   (0x100U)
38163 #define ENETC_SI_RBMR_CRC_SHIFT                  (8U)
38164 #define ENETC_SI_RBMR_CRC(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_CRC_SHIFT)) & ENETC_SI_RBMR_CRC_MASK)
38165 
38166 #define ENETC_SI_RBMR_EN_MASK                    (0x80000000U)
38167 #define ENETC_SI_RBMR_EN_SHIFT                   (31U)
38168 #define ENETC_SI_RBMR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_EN_SHIFT)) & ENETC_SI_RBMR_EN_MASK)
38169 /*! @} */
38170 
38171 /* The count of ENETC_SI_RBMR */
38172 #define ENETC_SI_RBMR_COUNT                      (10U)
38173 
38174 /*! @name RBSR - Rx BDR 0 status register..Rx BDR 9 status register */
38175 /*! @{ */
38176 
38177 #define ENETC_SI_RBSR_EMPTY_MASK                 (0x1U)
38178 #define ENETC_SI_RBSR_EMPTY_SHIFT                (0U)
38179 #define ENETC_SI_RBSR_EMPTY(x)                   (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBSR_EMPTY_SHIFT)) & ENETC_SI_RBSR_EMPTY_MASK)
38180 
38181 #define ENETC_SI_RBSR_SBE_MASK                   (0x10000U)
38182 #define ENETC_SI_RBSR_SBE_SHIFT                  (16U)
38183 #define ENETC_SI_RBSR_SBE(x)                     (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBSR_SBE_SHIFT)) & ENETC_SI_RBSR_SBE_MASK)
38184 /*! @} */
38185 
38186 /* The count of ENETC_SI_RBSR */
38187 #define ENETC_SI_RBSR_COUNT                      (10U)
38188 
38189 /*! @name RBBSR - Rx BDR 0 buffer size register..Rx BDR 9 buffer size register */
38190 /*! @{ */
38191 
38192 #define ENETC_SI_RBBSR_BSIZE_MASK                (0xFFFFU)
38193 #define ENETC_SI_RBBSR_BSIZE_SHIFT               (0U)
38194 #define ENETC_SI_RBBSR_BSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBSR_BSIZE_SHIFT)) & ENETC_SI_RBBSR_BSIZE_MASK)
38195 /*! @} */
38196 
38197 /* The count of ENETC_SI_RBBSR */
38198 #define ENETC_SI_RBBSR_COUNT                     (10U)
38199 
38200 /*! @name RBCIR - Rx BDR 0 consumer index register..Rx BDR 9 consumer index register */
38201 /*! @{ */
38202 
38203 #define ENETC_SI_RBCIR_BDR_INDEX_MASK            (0xFFFFU)
38204 #define ENETC_SI_RBCIR_BDR_INDEX_SHIFT           (0U)
38205 #define ENETC_SI_RBCIR_BDR_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBCIR_BDR_INDEX_SHIFT)) & ENETC_SI_RBCIR_BDR_INDEX_MASK)
38206 /*! @} */
38207 
38208 /* The count of ENETC_SI_RBCIR */
38209 #define ENETC_SI_RBCIR_COUNT                     (10U)
38210 
38211 /*! @name RBBAR0 - Rx BDR 0 base address register 0..Rx BDR 9 base address register 0 */
38212 /*! @{ */
38213 
38214 #define ENETC_SI_RBBAR0_ADDRL_MASK               (0xFFFFFF80U)
38215 #define ENETC_SI_RBBAR0_ADDRL_SHIFT              (7U)
38216 #define ENETC_SI_RBBAR0_ADDRL(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBAR0_ADDRL_SHIFT)) & ENETC_SI_RBBAR0_ADDRL_MASK)
38217 /*! @} */
38218 
38219 /* The count of ENETC_SI_RBBAR0 */
38220 #define ENETC_SI_RBBAR0_COUNT                    (10U)
38221 
38222 /*! @name RBBAR1 - Rx BDR 0 base address register 1..Rx BDR 9 base address register 1 */
38223 /*! @{ */
38224 
38225 #define ENETC_SI_RBBAR1_ADDRH_MASK               (0xFFFFFFFFU)
38226 #define ENETC_SI_RBBAR1_ADDRH_SHIFT              (0U)
38227 #define ENETC_SI_RBBAR1_ADDRH(x)                 (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBAR1_ADDRH_SHIFT)) & ENETC_SI_RBBAR1_ADDRH_MASK)
38228 /*! @} */
38229 
38230 /* The count of ENETC_SI_RBBAR1 */
38231 #define ENETC_SI_RBBAR1_COUNT                    (10U)
38232 
38233 /*! @name RBPIR - Rx BDR 0 producer index register..Rx BDR 9 producer index register */
38234 /*! @{ */
38235 
38236 #define ENETC_SI_RBPIR_BDR_INDEX_MASK            (0xFFFFU)
38237 #define ENETC_SI_RBPIR_BDR_INDEX_SHIFT           (0U)
38238 #define ENETC_SI_RBPIR_BDR_INDEX(x)              (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBPIR_BDR_INDEX_SHIFT)) & ENETC_SI_RBPIR_BDR_INDEX_MASK)
38239 /*! @} */
38240 
38241 /* The count of ENETC_SI_RBPIR */
38242 #define ENETC_SI_RBPIR_COUNT                     (10U)
38243 
38244 /*! @name RBLENR - Rx BDR 0 length register..Rx BDR 9 length register */
38245 /*! @{ */
38246 
38247 #define ENETC_SI_RBLENR_LENGTH_MASK              (0x1FFF8U)
38248 #define ENETC_SI_RBLENR_LENGTH_SHIFT             (3U)
38249 #define ENETC_SI_RBLENR_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBLENR_LENGTH_SHIFT)) & ENETC_SI_RBLENR_LENGTH_MASK)
38250 /*! @} */
38251 
38252 /* The count of ENETC_SI_RBLENR */
38253 #define ENETC_SI_RBLENR_COUNT                    (10U)
38254 
38255 /*! @name RBDCR - Rx BDR 0 drop count register..Rx BDR 9 drop count register */
38256 /*! @{ */
38257 
38258 #define ENETC_SI_RBDCR_COUNT_MASK                (0xFFFFFFFFU)
38259 #define ENETC_SI_RBDCR_COUNT_SHIFT               (0U)
38260 #define ENETC_SI_RBDCR_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBDCR_COUNT_SHIFT)) & ENETC_SI_RBDCR_COUNT_MASK)
38261 /*! @} */
38262 
38263 /* The count of ENETC_SI_RBDCR */
38264 #define ENETC_SI_BDR_RBDCR_COUNT                 (10U)
38265 
38266 /*! @name RBIER - Rx BDR 0 interrupt enable register..Rx BDR 9 interrupt enable register */
38267 /*! @{ */
38268 
38269 #define ENETC_SI_RBIER_RXTIE_MASK                (0x1U)
38270 #define ENETC_SI_RBIER_RXTIE_SHIFT               (0U)
38271 #define ENETC_SI_RBIER_RXTIE(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBIER_RXTIE_SHIFT)) & ENETC_SI_RBIER_RXTIE_MASK)
38272 /*! @} */
38273 
38274 /* The count of ENETC_SI_RBIER */
38275 #define ENETC_SI_RBIER_COUNT                     (10U)
38276 
38277 /*! @name RBIDR - Rx BDR 0 interrupt detect register..Rx BDR 9 interrupt detect register */
38278 /*! @{ */
38279 
38280 #define ENETC_SI_RBIDR_RXT_MASK                  (0x1U)
38281 #define ENETC_SI_RBIDR_RXT_SHIFT                 (0U)
38282 #define ENETC_SI_RBIDR_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBIDR_RXT_SHIFT)) & ENETC_SI_RBIDR_RXT_MASK)
38283 /*! @} */
38284 
38285 /* The count of ENETC_SI_RBIDR */
38286 #define ENETC_SI_RBIDR_COUNT                     (10U)
38287 
38288 /*! @name RBICR0 - Rx BDR 0 interrupt coalescing register 0..Rx BDR 9 interrupt coalescing register 0 */
38289 /*! @{ */
38290 
38291 #define ENETC_SI_RBICR0_ICPT_MASK                (0x1FFU)
38292 #define ENETC_SI_RBICR0_ICPT_SHIFT               (0U)
38293 #define ENETC_SI_RBICR0_ICPT(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR0_ICPT_SHIFT)) & ENETC_SI_RBICR0_ICPT_MASK)
38294 
38295 #define ENETC_SI_RBICR0_ICEN_MASK                (0x80000000U)
38296 #define ENETC_SI_RBICR0_ICEN_SHIFT               (31U)
38297 #define ENETC_SI_RBICR0_ICEN(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR0_ICEN_SHIFT)) & ENETC_SI_RBICR0_ICEN_MASK)
38298 /*! @} */
38299 
38300 /* The count of ENETC_SI_RBICR0 */
38301 #define ENETC_SI_RBICR0_COUNT                    (10U)
38302 
38303 /*! @name RBICR1 - Rx BDR 0 interrupt coalescing register 1..Rx BDR 9 interrupt coalescing register 1 */
38304 /*! @{ */
38305 
38306 #define ENETC_SI_RBICR1_ICTT_MASK                (0xFFFFFFFFU)
38307 #define ENETC_SI_RBICR1_ICTT_SHIFT               (0U)
38308 #define ENETC_SI_RBICR1_ICTT(x)                  (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR1_ICTT_SHIFT)) & ENETC_SI_RBICR1_ICTT_MASK)
38309 /*! @} */
38310 
38311 /* The count of ENETC_SI_RBICR1 */
38312 #define ENETC_SI_RBICR1_COUNT                    (10U)
38313 
38314 
38315 /*!
38316  * @}
38317  */ /* end of group ENETC_SI_Register_Masks */
38318 
38319 
38320 /* ENETC_SI - Peripheral instance base addresses */
38321 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
38322   /** Peripheral ENETC0_SI0 base address */
38323   #define ENETC0_SI0_BASE                          (0x70B00000u)
38324   /** Peripheral ENETC0_SI0 base address */
38325   #define ENETC0_SI0_BASE_NS                       (0x60B00000u)
38326   /** Peripheral ENETC0_SI0 base pointer */
38327   #define ENETC0_SI0                               ((ENETC_SI_Type *)ENETC0_SI0_BASE)
38328   /** Peripheral ENETC0_SI0 base pointer */
38329   #define ENETC0_SI0_NS                            ((ENETC_SI_Type *)ENETC0_SI0_BASE_NS)
38330   /** Peripheral ENETC1_SI0 base address */
38331   #define ENETC1_SI0_BASE                          (0x70B40000u)
38332   /** Peripheral ENETC1_SI0 base address */
38333   #define ENETC1_SI0_BASE_NS                       (0x60B40000u)
38334   /** Peripheral ENETC1_SI0 base pointer */
38335   #define ENETC1_SI0                               ((ENETC_SI_Type *)ENETC1_SI0_BASE)
38336   /** Peripheral ENETC1_SI0 base pointer */
38337   #define ENETC1_SI0_NS                            ((ENETC_SI_Type *)ENETC1_SI0_BASE_NS)
38338   /** Peripheral ENETC1_SI1 base address */
38339   #define ENETC1_SI1_BASE                          (0x70C10000u)
38340   /** Peripheral ENETC1_SI1 base address */
38341   #define ENETC1_SI1_BASE_NS                       (0x60C10000u)
38342   /** Peripheral ENETC1_SI1 base pointer */
38343   #define ENETC1_SI1                               ((ENETC_SI_Type *)ENETC1_SI1_BASE)
38344   /** Peripheral ENETC1_SI1 base pointer */
38345   #define ENETC1_SI1_NS                            ((ENETC_SI_Type *)ENETC1_SI1_BASE_NS)
38346   /** Array initializer of ENETC_SI peripheral base addresses */
38347   #define ENETC_SI_BASE_ADDRS                      { ENETC0_SI0_BASE, ENETC1_SI0_BASE, ENETC1_SI1_BASE }
38348   /** Array initializer of ENETC_SI peripheral base pointers */
38349   #define ENETC_SI_BASE_PTRS                       { ENETC0_SI0, ENETC1_SI0, ENETC1_SI1 }
38350   /** Array initializer of ENETC_SI peripheral base addresses */
38351   #define ENETC_SI_BASE_ADDRS_NS                   { ENETC0_SI0_BASE_NS, ENETC1_SI0_BASE_NS, ENETC1_SI1_BASE_NS }
38352   /** Array initializer of ENETC_SI peripheral base pointers */
38353   #define ENETC_SI_BASE_PTRS_NS                    { ENETC0_SI0_NS, ENETC1_SI0_NS, ENETC1_SI1_NS }
38354 #else
38355   /** Peripheral ENETC0_SI0 base address */
38356   #define ENETC0_SI0_BASE                          (0x60B00000u)
38357   /** Peripheral ENETC0_SI0 base pointer */
38358   #define ENETC0_SI0                               ((ENETC_SI_Type *)ENETC0_SI0_BASE)
38359   /** Peripheral ENETC1_SI0 base address */
38360   #define ENETC1_SI0_BASE                          (0x60B40000u)
38361   /** Peripheral ENETC1_SI0 base pointer */
38362   #define ENETC1_SI0                               ((ENETC_SI_Type *)ENETC1_SI0_BASE)
38363   /** Peripheral ENETC1_SI1 base address */
38364   #define ENETC1_SI1_BASE                          (0x60C10000u)
38365   /** Peripheral ENETC1_SI1 base pointer */
38366   #define ENETC1_SI1                               ((ENETC_SI_Type *)ENETC1_SI1_BASE)
38367   /** Array initializer of ENETC_SI peripheral base addresses */
38368   #define ENETC_SI_BASE_ADDRS                      { ENETC0_SI0_BASE, ENETC1_SI0_BASE, ENETC1_SI1_BASE }
38369   /** Array initializer of ENETC_SI peripheral base pointers */
38370   #define ENETC_SI_BASE_PTRS                       { ENETC0_SI0, ENETC1_SI0, ENETC1_SI1 }
38371 #endif
38372 
38373 /*!
38374  * @}
38375  */ /* end of group ENETC_SI_Peripheral_Access_Layer */
38376 
38377 
38378 /* ----------------------------------------------------------------------------
38379    -- ENETC_VF_PCI_TYPE0 Peripheral Access Layer
38380    ---------------------------------------------------------------------------- */
38381 
38382 /*!
38383  * @addtogroup ENETC_VF_PCI_TYPE0_Peripheral_Access_Layer ENETC_VF_PCI_TYPE0 Peripheral Access Layer
38384  * @{
38385  */
38386 
38387 /** ENETC_VF_PCI_TYPE0 - Register Layout Typedef */
38388 typedef struct {
38389   __I  uint32_t PCI_CFH_DID_VID;                   /**< PCI device ID and vendor ID register, offset: 0x0 */
38390   __IO uint16_t PCI_CFH_CMD;                       /**< PCI command register, offset: 0x4 */
38391   __I  uint16_t PCI_CFH_STAT;                      /**< PCI status register, offset: 0x6 */
38392   __I  uint32_t PCI_CFH_REVID_CLASSCODE;           /**< PCI revision ID and classcode register, offset: 0x8 */
38393   __I  uint8_t PCI_CFH_CL_SIZE;                    /**< PCI cache line size register, offset: 0xC */
38394   __I  uint8_t PCI_CFH_LAT_TIMER;                  /**< PCI latency timer register, offset: 0xD */
38395   __I  uint8_t PCI_CFH_HDR_TYPE;                   /**< PCI header type register, offset: 0xE */
38396   __I  uint8_t PCI_CFH_BIST;                       /**< PCI BIST register, offset: 0xF */
38397   __I  uint32_t PCI_CFH_BAR0;                      /**< PCI base address register 0, offset: 0x10 */
38398   __I  uint32_t PCI_CFH_BAR1;                      /**< PCI base address register 1, offset: 0x14 */
38399   __I  uint32_t PCI_CFH_BAR2;                      /**< PCI base address register 2, offset: 0x18 */
38400   __I  uint32_t PCI_CFH_BAR3;                      /**< PCI base address register 3, offset: 0x1C */
38401   __I  uint32_t PCI_CFH_BAR4;                      /**< PCI base address register 4, offset: 0x20 */
38402   __I  uint32_t PCI_CFH_BAR5;                      /**< PCI base address register 5, offset: 0x24 */
38403   __I  uint32_t PCI_CFH_CARDBUS_CIS;               /**< PCI cardbus CIS register, offset: 0x28 */
38404   __I  uint16_t PCI_CFH_SUBSYS_VID;                /**< PCI subsystem vendor ID register, offset: 0x2C */
38405   __I  uint16_t PCI_CFH_SUBSYS_ID;                 /**< PCI subsystem ID register, offset: 0x2E */
38406   __I  uint32_t PCI_CFH_EXP_ROM_BA;                /**< PCI expansion ROM base address register, offset: 0x30 */
38407   __I  uint8_t PCI_CFH_CAP_PTR;                    /**< PCI capabilities pointer register, offset: 0x34 */
38408        uint8_t RESERVED_0[11];
38409   __I  uint16_t PCI_CFC_PCIE_CAP_LIST;             /**< PCI PCIe capabilities list register, offset: 0x40 */
38410   __I  uint16_t PCI_CFC_PCIE_CAP;                  /**< PCI PCIe capabilities register, offset: 0x42 */
38411   __I  uint32_t PCI_CFC_PCIE_DEV_CAP;              /**< PCI PCIe device capabilities register, offset: 0x44 */
38412   __IO uint16_t PCI_CFC_PCIE_DEV_CTL;              /**< PCI PCIe device control register, offset: 0x48 */
38413   __I  uint16_t PCI_CFC_PCIE_DEV_STAT;             /**< PCI PCIe device status register, offset: 0x4A */
38414        uint8_t RESERVED_1[24];
38415   __I  uint32_t PCI_CFC_PCIE_DEV_CAP2;             /**< PCI PCIe device capabilities 2 register, offset: 0x64 */
38416   __I  uint16_t PCI_CFC_PCIE_DEV_CTL2;             /**< PCI PCIe device control 2 register, offset: 0x68 */
38417        uint8_t RESERVED_2[22];
38418   __I  uint16_t PCI_CFC_MSIX_CAP_LIST;             /**< PCI MSI-X capabilities list register, offset: 0x80 */
38419   __IO uint16_t PCI_CFC_MSIX_MSG_CTL;              /**< PCI MSI-X message control register, offset: 0x82 */
38420   __I  uint32_t PCI_CFC_MSIX_TABLE_OFF_BIR;        /**< PCI MSI-X table offset/BIR register, offset: 0x84 */
38421   __I  uint32_t PCI_CFC_MSIX_PBA_OFF_BIR;          /**< PCI MSI-X PBA offset/BIR register, offset: 0x88 */
38422        uint8_t RESERVED_3[116];
38423   __I  uint32_t PCIE_CFC_AER_EXT_CAP_HDR;          /**< PCIe AER extended capability header, offset: 0x100 */
38424   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_STAT;       /**< PCIe AER uncorrectable error status register, offset: 0x104 */
38425   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_MASK;       /**< PCIe AER uncorrectable error mask register, offset: 0x108 */
38426   __IO uint32_t PCIE_CFC_AER_UCORR_ERR_SEV;        /**< PCIe AER uncorrectable error severity register, offset: 0x10C */
38427   __IO uint32_t PCIE_CFC_AER_CORR_ERR_STAT;        /**< PCIe AER correctable error status register, offset: 0x110 */
38428   __IO uint32_t PCIE_CFC_AER_CORR_ERR_MASK;        /**< PCIe AER correctable error mask register, offset: 0x114 */
38429   __I  uint32_t PCIE_CFC_AER_CAP_CTL;              /**< PCIe AER capabilities and control register, offset: 0x118 */
38430        uint8_t RESERVED_4[20];
38431   __I  uint32_t PCIE_CFC_ACS_CAP_HDR;              /**< PCIe ACS capability header, offset: 0x130 */
38432   __I  uint16_t PCIE_CFC_ACS_CAP;                  /**< PCIe ACS capability register, offset: 0x134 */
38433   __I  uint16_t PCIE_CFC_ACS_CTL;                  /**< PCIe ACS control register, offset: 0x136 */
38434        uint8_t RESERVED_5[8];
38435   __I  uint32_t PCIE_CFC_RTR_CAP_HDR;              /**< PCIe readiness time reporting capability header, offset: 0x140 */
38436   __I  uint32_t PCIE_CFC_RTR_RTR1;                 /**< PCIe RTR readiness time reporting 1 register, offset: 0x144 */
38437   __I  uint32_t PCIE_CFC_RTR_RTR2;                 /**< PCIe RTR readiness time reporting 2 register, offset: 0x148 */
38438 } ENETC_VF_PCI_TYPE0_Type;
38439 
38440 /* ----------------------------------------------------------------------------
38441    -- ENETC_VF_PCI_TYPE0 Register Masks
38442    ---------------------------------------------------------------------------- */
38443 
38444 /*!
38445  * @addtogroup ENETC_VF_PCI_TYPE0_Register_Masks ENETC_VF_PCI_TYPE0 Register Masks
38446  * @{
38447  */
38448 
38449 /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */
38450 /*! @{ */
38451 
38452 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU)
38453 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U)
38454 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK)
38455 
38456 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U)
38457 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U)
38458 #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK)
38459 /*! @} */
38460 
38461 /*! @name PCI_CFH_CMD - PCI command register */
38462 /*! @{ */
38463 
38464 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK (0x4U)
38465 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT (2U)
38466 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK)
38467 /*! @} */
38468 
38469 /*! @name PCI_CFH_STAT - PCI status register */
38470 /*! @{ */
38471 
38472 #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK (0x10U)
38473 #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT (4U)
38474 #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK)
38475 /*! @} */
38476 
38477 /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */
38478 /*! @{ */
38479 
38480 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU)
38481 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U)
38482 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK)
38483 
38484 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U)
38485 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U)
38486 #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK)
38487 /*! @} */
38488 
38489 /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */
38490 /*! @{ */
38491 
38492 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU)
38493 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U)
38494 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK)
38495 /*! @} */
38496 
38497 /*! @name PCI_CFH_LAT_TIMER - PCI latency timer register */
38498 /*! @{ */
38499 
38500 #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_MASK (0xFFU)
38501 #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_SHIFT (0U)
38502 #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_MASK)
38503 /*! @} */
38504 
38505 /*! @name PCI_CFH_HDR_TYPE - PCI header type register */
38506 /*! @{ */
38507 
38508 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU)
38509 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U)
38510 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK)
38511 
38512 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U)
38513 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U)
38514 #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK)
38515 /*! @} */
38516 
38517 /*! @name PCI_CFH_BIST - PCI BIST register */
38518 /*! @{ */
38519 
38520 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_MASK (0xFFU)
38521 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_SHIFT (0U)
38522 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST(x)  (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_MASK)
38523 /*! @} */
38524 
38525 /*! @name PCI_CFH_BAR0 - PCI base address register 0 */
38526 /*! @{ */
38527 
38528 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK (0x1U)
38529 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT (0U)
38530 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK)
38531 
38532 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK (0x6U)
38533 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT (1U)
38534 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK)
38535 
38536 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK (0x8U)
38537 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT (3U)
38538 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK)
38539 
38540 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK (0xFFFFFFF0U)
38541 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT (4U)
38542 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK)
38543 /*! @} */
38544 
38545 /*! @name PCI_CFH_BAR1 - PCI base address register 1 */
38546 /*! @{ */
38547 
38548 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK (0x1U)
38549 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT (0U)
38550 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK)
38551 
38552 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK (0x6U)
38553 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT (1U)
38554 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK)
38555 
38556 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK (0x8U)
38557 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT (3U)
38558 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK)
38559 
38560 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK (0xFFFFFFF0U)
38561 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT (4U)
38562 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK)
38563 /*! @} */
38564 
38565 /*! @name PCI_CFH_BAR2 - PCI base address register 2 */
38566 /*! @{ */
38567 
38568 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK (0x1U)
38569 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT (0U)
38570 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK)
38571 
38572 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK (0x6U)
38573 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT (1U)
38574 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK)
38575 
38576 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK (0x8U)
38577 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT (3U)
38578 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK)
38579 
38580 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK (0xFFFFFFF0U)
38581 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT (4U)
38582 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK)
38583 /*! @} */
38584 
38585 /*! @name PCI_CFH_BAR3 - PCI base address register 3 */
38586 /*! @{ */
38587 
38588 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK (0x1U)
38589 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT (0U)
38590 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK)
38591 
38592 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK (0x6U)
38593 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT (1U)
38594 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK)
38595 
38596 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK (0x8U)
38597 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT (3U)
38598 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK)
38599 
38600 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK (0xFFFFFFF0U)
38601 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT (4U)
38602 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK)
38603 /*! @} */
38604 
38605 /*! @name PCI_CFH_BAR4 - PCI base address register 4 */
38606 /*! @{ */
38607 
38608 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK (0x1U)
38609 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT (0U)
38610 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK)
38611 
38612 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK (0x6U)
38613 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT (1U)
38614 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK)
38615 
38616 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK (0x8U)
38617 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT (3U)
38618 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK)
38619 
38620 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK (0xFFFFFFF0U)
38621 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT (4U)
38622 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK)
38623 /*! @} */
38624 
38625 /*! @name PCI_CFH_BAR5 - PCI base address register 5 */
38626 /*! @{ */
38627 
38628 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK (0x1U)
38629 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT (0U)
38630 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK)
38631 
38632 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK (0x6U)
38633 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT (1U)
38634 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK)
38635 
38636 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK (0x8U)
38637 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT (3U)
38638 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK)
38639 
38640 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK (0xFFFFFFF0U)
38641 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT (4U)
38642 #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK)
38643 /*! @} */
38644 
38645 /*! @name PCI_CFH_CARDBUS_CIS - PCI cardbus CIS register */
38646 /*! @{ */
38647 
38648 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_MASK (0xFFFFFFFFU)
38649 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_SHIFT (0U)
38650 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_MASK)
38651 /*! @} */
38652 
38653 /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */
38654 /*! @{ */
38655 
38656 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
38657 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_SHIFT (0U)
38658 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_MASK)
38659 /*! @} */
38660 
38661 /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */
38662 /*! @{ */
38663 
38664 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_MASK (0xFFFFU)
38665 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_SHIFT (0U)
38666 #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_MASK)
38667 /*! @} */
38668 
38669 /*! @name PCI_CFH_EXP_ROM_BA - PCI expansion ROM base address register */
38670 /*! @{ */
38671 
38672 #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_MASK (0xFFFFFFFFU)
38673 #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_SHIFT (0U)
38674 #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_MASK)
38675 /*! @} */
38676 
38677 /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */
38678 /*! @{ */
38679 
38680 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU)
38681 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U)
38682 #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK)
38683 /*! @} */
38684 
38685 /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */
38686 /*! @{ */
38687 
38688 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU)
38689 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U)
38690 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK)
38691 
38692 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
38693 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
38694 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK)
38695 /*! @} */
38696 
38697 /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */
38698 /*! @{ */
38699 
38700 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU)
38701 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U)
38702 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK)
38703 
38704 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U)
38705 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U)
38706 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK)
38707 
38708 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U)
38709 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U)
38710 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK)
38711 /*! @} */
38712 
38713 /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */
38714 /*! @{ */
38715 
38716 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U)
38717 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U)
38718 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK)
38719 /*! @} */
38720 
38721 /*! @name PCI_CFC_PCIE_DEV_CTL - PCI PCIe device control register */
38722 /*! @{ */
38723 
38724 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK (0x8000U)
38725 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT (15U)
38726 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK)
38727 /*! @} */
38728 
38729 /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */
38730 /*! @{ */
38731 
38732 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U)
38733 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U)
38734 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK)
38735 /*! @} */
38736 
38737 /*! @name PCI_CFC_PCIE_DEV_CAP2 - PCI PCIe device capabilities 2 register */
38738 /*! @{ */
38739 
38740 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK (0xFU)
38741 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT (0U)
38742 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK)
38743 
38744 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK (0x10U)
38745 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT (4U)
38746 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK)
38747 /*! @} */
38748 
38749 /*! @name PCI_CFC_PCIE_DEV_CTL2 - PCI PCIe device control 2 register */
38750 /*! @{ */
38751 
38752 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK (0xFU)
38753 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT (0U)
38754 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK)
38755 
38756 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK (0x10U)
38757 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT (4U)
38758 #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK)
38759 /*! @} */
38760 
38761 /*! @name PCI_CFC_MSIX_CAP_LIST - PCI MSI-X capabilities list register */
38762 /*! @{ */
38763 
38764 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK (0xFFU)
38765 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT (0U)
38766 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK)
38767 
38768 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U)
38769 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U)
38770 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK)
38771 /*! @} */
38772 
38773 /*! @name PCI_CFC_MSIX_MSG_CTL - PCI MSI-X message control register */
38774 /*! @{ */
38775 
38776 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK (0x7FFU)
38777 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT (0U)
38778 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK)
38779 
38780 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK (0x4000U)
38781 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT (14U)
38782 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK)
38783 
38784 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK (0x8000U)
38785 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT (15U)
38786 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK)
38787 /*! @} */
38788 
38789 /*! @name PCI_CFC_MSIX_TABLE_OFF_BIR - PCI MSI-X table offset/BIR register */
38790 /*! @{ */
38791 
38792 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK (0x7U)
38793 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT (0U)
38794 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK)
38795 
38796 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK (0xFFFFFFF8U)
38797 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT (3U)
38798 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK)
38799 /*! @} */
38800 
38801 /*! @name PCI_CFC_MSIX_PBA_OFF_BIR - PCI MSI-X PBA offset/BIR register */
38802 /*! @{ */
38803 
38804 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK (0x7U)
38805 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT (0U)
38806 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK)
38807 
38808 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK (0xFFFFFFF8U)
38809 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT (3U)
38810 #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK)
38811 /*! @} */
38812 
38813 /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */
38814 /*! @{ */
38815 
38816 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
38817 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
38818 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
38819 
38820 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U)
38821 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U)
38822 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK)
38823 
38824 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
38825 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
38826 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK)
38827 /*! @} */
38828 
38829 /*! @name PCIE_CFC_AER_UCORR_ERR_STAT - PCIe AER uncorrectable error status register */
38830 /*! @{ */
38831 
38832 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK (0x400000U)
38833 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT (22U)
38834 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK)
38835 /*! @} */
38836 
38837 /*! @name PCIE_CFC_AER_UCORR_ERR_MASK - PCIe AER uncorrectable error mask register */
38838 /*! @{ */
38839 
38840 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK (0x400000U)
38841 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT (22U)
38842 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK)
38843 /*! @} */
38844 
38845 /*! @name PCIE_CFC_AER_UCORR_ERR_SEV - PCIe AER uncorrectable error severity register */
38846 /*! @{ */
38847 
38848 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK (0x400000U)
38849 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT (22U)
38850 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK)
38851 /*! @} */
38852 
38853 /*! @name PCIE_CFC_AER_CORR_ERR_STAT - PCIe AER correctable error status register */
38854 /*! @{ */
38855 
38856 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK (0x4000U)
38857 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT (14U)
38858 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK)
38859 /*! @} */
38860 
38861 /*! @name PCIE_CFC_AER_CORR_ERR_MASK - PCIe AER correctable error mask register */
38862 /*! @{ */
38863 
38864 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK (0x4000U)
38865 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT (14U)
38866 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK)
38867 /*! @} */
38868 
38869 /*! @name PCIE_CFC_AER_CAP_CTL - PCIe AER capabilities and control register */
38870 /*! @{ */
38871 
38872 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK (0x1FU)
38873 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT (0U)
38874 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK)
38875 /*! @} */
38876 
38877 /*! @name PCIE_CFC_ACS_CAP_HDR - PCIe ACS capability header */
38878 /*! @{ */
38879 
38880 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
38881 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
38882 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
38883 
38884 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK (0xF0000U)
38885 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT (16U)
38886 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK)
38887 
38888 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
38889 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
38890 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK)
38891 /*! @} */
38892 
38893 /*! @name PCIE_CFC_ACS_CAP - PCIe ACS capability register */
38894 /*! @{ */
38895 
38896 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK (0x2U)
38897 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT (1U)
38898 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK)
38899 
38900 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK (0x4U)
38901 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT (2U)
38902 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK)
38903 
38904 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK (0x40U)
38905 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT (6U)
38906 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK)
38907 /*! @} */
38908 
38909 /*! @name PCIE_CFC_ACS_CTL - PCIe ACS control register */
38910 /*! @{ */
38911 
38912 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK (0x2U)
38913 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT (1U)
38914 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK)
38915 
38916 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK (0x4U)
38917 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT (2U)
38918 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK)
38919 
38920 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK (0x40U)
38921 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT (6U)
38922 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK)
38923 /*! @} */
38924 
38925 /*! @name PCIE_CFC_RTR_CAP_HDR - PCIe readiness time reporting capability header */
38926 /*! @{ */
38927 
38928 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
38929 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
38930 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
38931 
38932 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK (0xF0000U)
38933 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT (16U)
38934 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK)
38935 
38936 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
38937 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
38938 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK)
38939 /*! @} */
38940 
38941 /*! @name PCIE_CFC_RTR_RTR1 - PCIe RTR readiness time reporting 1 register */
38942 /*! @{ */
38943 
38944 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK (0xFFFU)
38945 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT (0U)
38946 /*! RESET_TIME - Reset Time */
38947 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK)
38948 
38949 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK (0x80000000U)
38950 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT (31U)
38951 /*! VALID - Valid */
38952 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK)
38953 /*! @} */
38954 
38955 /*! @name PCIE_CFC_RTR_RTR2 - PCIe RTR readiness time reporting 2 register */
38956 /*! @{ */
38957 
38958 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK (0xFFFU)
38959 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT (0U)
38960 /*! FLR_TIME - FLR Time */
38961 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK)
38962 
38963 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK (0xFFF000U)
38964 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT (12U)
38965 /*! D3HOT_D0_TIME - D3 hot to D0 time */
38966 #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK)
38967 /*! @} */
38968 
38969 
38970 /*!
38971  * @}
38972  */ /* end of group ENETC_VF_PCI_TYPE0_Register_Masks */
38973 
38974 
38975 /* ENETC_VF_PCI_TYPE0 - Peripheral instance base addresses */
38976 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
38977   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base address */
38978   #define NETC_VF1_PCI_HDR_TYPE0_BASE              (0x70100000u)
38979   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base address */
38980   #define NETC_VF1_PCI_HDR_TYPE0_BASE_NS           (0x60100000u)
38981   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base pointer */
38982   #define NETC_VF1_PCI_HDR_TYPE0                   ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF1_PCI_HDR_TYPE0_BASE)
38983   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base pointer */
38984   #define NETC_VF1_PCI_HDR_TYPE0_NS                ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF1_PCI_HDR_TYPE0_BASE_NS)
38985   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base addresses */
38986   #define ENETC_VF_PCI_TYPE0_BASE_ADDRS            { NETC_VF1_PCI_HDR_TYPE0_BASE }
38987   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base pointers */
38988   #define ENETC_VF_PCI_TYPE0_BASE_PTRS             { NETC_VF1_PCI_HDR_TYPE0 }
38989   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base addresses */
38990   #define ENETC_VF_PCI_TYPE0_BASE_ADDRS_NS         { NETC_VF1_PCI_HDR_TYPE0_BASE_NS }
38991   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base pointers */
38992   #define ENETC_VF_PCI_TYPE0_BASE_PTRS_NS          { NETC_VF1_PCI_HDR_TYPE0_NS }
38993 #else
38994   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base address */
38995   #define NETC_VF1_PCI_HDR_TYPE0_BASE              (0x60100000u)
38996   /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base pointer */
38997   #define NETC_VF1_PCI_HDR_TYPE0                   ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF1_PCI_HDR_TYPE0_BASE)
38998   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base addresses */
38999   #define ENETC_VF_PCI_TYPE0_BASE_ADDRS            { NETC_VF1_PCI_HDR_TYPE0_BASE }
39000   /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base pointers */
39001   #define ENETC_VF_PCI_TYPE0_BASE_PTRS             { NETC_VF1_PCI_HDR_TYPE0 }
39002 #endif
39003 
39004 /*!
39005  * @}
39006  */ /* end of group ENETC_VF_PCI_TYPE0_Peripheral_Access_Layer */
39007 
39008 
39009 /* ----------------------------------------------------------------------------
39010    -- EQDC Peripheral Access Layer
39011    ---------------------------------------------------------------------------- */
39012 
39013 /*!
39014  * @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer
39015  * @{
39016  */
39017 
39018 /** EQDC - Register Layout Typedef */
39019 typedef struct {
39020   __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
39021   __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x2 */
39022   __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x4 */
39023   __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x6 */
39024   __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x8 */
39025   __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0xA */
39026   __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xC */
39027   __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0xE */
39028   __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x10 */
39029   __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x12 */
39030   __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x14 */
39031   __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x16 */
39032   __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x18 */
39033   __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x1A */
39034   __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0x1C */
39035   __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0x1E */
39036   __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x20 */
39037   __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x22 */
39038   __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x24 */
39039   __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x26 */
39040   __IO uint16_t UCOMP0;                            /**< Upper Position Compare Register 0, offset: 0x28 */
39041   __IO uint16_t LCOMP0;                            /**< Lower Position Compare Register 0, offset: 0x2A */
39042   union {                                          /* offset: 0x2C */
39043     __O  uint16_t UCOMP1;                            /**< Upper Position Compare 1, offset: 0x2C */
39044     __I  uint16_t UPOSH1;                            /**< Upper Position Holder Register 1, offset: 0x2C */
39045   };
39046   union {                                          /* offset: 0x2E */
39047     __O  uint16_t LCOMP1;                            /**< Lower Position Compare 1, offset: 0x2E */
39048     __I  uint16_t LPOSH1;                            /**< Lower Position Holder Register 1, offset: 0x2E */
39049   };
39050   union {                                          /* offset: 0x30 */
39051     __O  uint16_t UCOMP2;                            /**< Upper Position Compare 2, offset: 0x30 */
39052     __I  uint16_t UPOSH2;                            /**< Upper Position Holder Register 3, offset: 0x30 */
39053   };
39054   union {                                          /* offset: 0x32 */
39055     __O  uint16_t LCOMP2;                            /**< Lower Position Compare 2, offset: 0x32 */
39056     __I  uint16_t LPOSH2;                            /**< Lower Position Holder Register 2, offset: 0x32 */
39057   };
39058   union {                                          /* offset: 0x34 */
39059     __O  uint16_t UCOMP3;                            /**< Upper Position Compare 3, offset: 0x34 */
39060     __I  uint16_t UPOSH3;                            /**< Upper Position Holder Register 3, offset: 0x34 */
39061   };
39062   union {                                          /* offset: 0x36 */
39063     __O  uint16_t LCOMP3;                            /**< Lower Position Compare 3, offset: 0x36 */
39064     __I  uint16_t LPOSH3;                            /**< Lower Position Holder Register 3, offset: 0x36 */
39065   };
39066   __IO uint16_t INTCTRL;                           /**< Interrupt Control Register, offset: 0x38 */
39067   __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x3A */
39068   __IO uint16_t IMR;                               /**< Input Monitor Register, offset: 0x3C */
39069   __IO uint16_t TST;                               /**< Test Register, offset: 0x3E */
39070        uint8_t RESERVED_0[16];
39071   __I  uint16_t UVERID;                            /**< Upper VERID, offset: 0x50 */
39072   __I  uint16_t LVERID;                            /**< Lower VERID, offset: 0x52 */
39073 } EQDC_Type;
39074 
39075 /* ----------------------------------------------------------------------------
39076    -- EQDC Register Masks
39077    ---------------------------------------------------------------------------- */
39078 
39079 /*!
39080  * @addtogroup EQDC_Register_Masks EQDC Register Masks
39081  * @{
39082  */
39083 
39084 /*! @name CTRL - Control Register */
39085 /*! @{ */
39086 
39087 #define EQDC_CTRL_LDOK_MASK                      (0x1U)
39088 #define EQDC_CTRL_LDOK_SHIFT                     (0U)
39089 /*! LDOK - Load Okay
39090  *  0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers)
39091  *  0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD].
39092  */
39093 #define EQDC_CTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK)
39094 
39095 #define EQDC_CTRL_DMAEN_MASK                     (0x2U)
39096 #define EQDC_CTRL_DMAEN_SHIFT                    (1U)
39097 /*! DMAEN - DMA Enable
39098  *  0b0..DMA is disabled
39099  *  0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare
39100  *       registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and
39101  *       modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically.
39102  *       After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be
39103  *       loaded into inner-set which in turn triggers DMA again.
39104  */
39105 #define EQDC_CTRL_DMAEN(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK)
39106 
39107 #define EQDC_CTRL_WDE_MASK                       (0x4U)
39108 #define EQDC_CTRL_WDE_SHIFT                      (2U)
39109 /*! WDE - Watchdog Enable
39110  *  0b0..Disabled
39111  *  0b1..Enabled
39112  */
39113 #define EQDC_CTRL_WDE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK)
39114 
39115 #define EQDC_CTRL_WDIE_MASK                      (0x8U)
39116 #define EQDC_CTRL_WDIE_SHIFT                     (3U)
39117 /*! WDIE - Watchdog Timeout Interrupt Enable
39118  *  0b0..Disabled
39119  *  0b1..Enabled
39120  */
39121 #define EQDC_CTRL_WDIE(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK)
39122 
39123 #define EQDC_CTRL_WDIRQ_MASK                     (0x10U)
39124 #define EQDC_CTRL_WDIRQ_SHIFT                    (4U)
39125 /*! WDIRQ - Watchdog Timeout Interrupt Request
39126  *  0b0..No Watchdog timeout interrupt has occurred
39127  *  0b1..Watchdog timeout interrupt has occurred
39128  */
39129 #define EQDC_CTRL_WDIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK)
39130 
39131 #define EQDC_CTRL_XNE_MASK                       (0x20U)
39132 #define EQDC_CTRL_XNE_SHIFT                      (5U)
39133 /*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse
39134  *  0b0..Use positive edge of INDEX/PRESET pulse
39135  *  0b1..Use negative edge of INDEX/PRESET pulse
39136  */
39137 #define EQDC_CTRL_XNE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK)
39138 
39139 #define EQDC_CTRL_XIP_MASK                       (0x40U)
39140 #define EQDC_CTRL_XIP_SHIFT                      (6U)
39141 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
39142  *  0b0..INDEX pulse does not initialize the position counter
39143  *  0b1..INDEX pulse initializes the position counter
39144  */
39145 #define EQDC_CTRL_XIP(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK)
39146 
39147 #define EQDC_CTRL_XIE_MASK                       (0x80U)
39148 #define EQDC_CTRL_XIE_SHIFT                      (7U)
39149 /*! XIE - INDEX/PRESET Pulse Interrupt Enable
39150  *  0b0..Disabled
39151  *  0b1..Enabled
39152  */
39153 #define EQDC_CTRL_XIE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK)
39154 
39155 #define EQDC_CTRL_XIRQ_MASK                      (0x100U)
39156 #define EQDC_CTRL_XIRQ_SHIFT                     (8U)
39157 /*! XIRQ - INDEX/PRESET Pulse Interrupt Request
39158  *  0b0..INDEX/PRESET pulse has not occurred
39159  *  0b1..INDEX/PRESET pulse has occurred
39160  */
39161 #define EQDC_CTRL_XIRQ(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK)
39162 
39163 #define EQDC_CTRL_PH1_MASK                       (0x200U)
39164 #define EQDC_CTRL_PH1_SHIFT                      (9U)
39165 /*! PH1 - Enable Single Phase Mode
39166  *  0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
39167  *  0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description
39168  */
39169 #define EQDC_CTRL_PH1(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK)
39170 
39171 #define EQDC_CTRL_REV_MASK                       (0x400U)
39172 #define EQDC_CTRL_REV_SHIFT                      (10U)
39173 /*! REV - Enable Reverse Direction Counting
39174  *  0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT
39175  *  0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD
39176  */
39177 #define EQDC_CTRL_REV(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK)
39178 
39179 #define EQDC_CTRL_SWIP_MASK                      (0x800U)
39180 #define EQDC_CTRL_SWIP_SHIFT                     (11U)
39181 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
39182  *  0b0..No action
39183  *  0b1..Initialize position counter
39184  */
39185 #define EQDC_CTRL_SWIP(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK)
39186 
39187 #define EQDC_CTRL_HNE_MASK                       (0x1000U)
39188 #define EQDC_CTRL_HNE_SHIFT                      (12U)
39189 /*! HNE - Use Negative Edge of HOME/ENABLE Input
39190  *  0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When
39191  *       CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters
39192  *  0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When
39193  *       CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters
39194  */
39195 #define EQDC_CTRL_HNE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK)
39196 
39197 #define EQDC_CTRL_HIP_MASK                       (0x2000U)
39198 #define EQDC_CTRL_HIP_SHIFT                      (13U)
39199 /*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS
39200  *  0b0..No action
39201  *  0b1..HOME signal initializes the position counter
39202  */
39203 #define EQDC_CTRL_HIP(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK)
39204 
39205 #define EQDC_CTRL_HIE_MASK                       (0x4000U)
39206 #define EQDC_CTRL_HIE_SHIFT                      (14U)
39207 /*! HIE - HOME/ENABLE Interrupt Enable
39208  *  0b0..Disabled
39209  *  0b1..Enabled
39210  */
39211 #define EQDC_CTRL_HIE(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK)
39212 
39213 #define EQDC_CTRL_HIRQ_MASK                      (0x8000U)
39214 #define EQDC_CTRL_HIRQ_SHIFT                     (15U)
39215 /*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request
39216  *  0b0..No transition on the HOME/ENABLE signal has occurred
39217  *  0b1..A transition on the HOME/ENABLE signal has occurred
39218  */
39219 #define EQDC_CTRL_HIRQ(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK)
39220 /*! @} */
39221 
39222 /*! @name CTRL2 - Control 2 Register */
39223 /*! @{ */
39224 
39225 #define EQDC_CTRL2_UPDHLD_MASK                   (0x1U)
39226 #define EQDC_CTRL2_UPDHLD_SHIFT                  (0U)
39227 /*! UPDHLD - Update Hold Registers */
39228 #define EQDC_CTRL2_UPDHLD(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK)
39229 
39230 #define EQDC_CTRL2_UPDPOS_MASK                   (0x2U)
39231 #define EQDC_CTRL2_UPDPOS_SHIFT                  (1U)
39232 /*! UPDPOS - Update Position Registers */
39233 #define EQDC_CTRL2_UPDPOS(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK)
39234 
39235 #define EQDC_CTRL2_OPMODE_MASK                   (0x4U)
39236 #define EQDC_CTRL2_OPMODE_SHIFT                  (2U)
39237 /*! OPMODE - Operation Mode Select
39238  *  0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME.
39239  *  0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In
39240  *       this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run,
39241  *       when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising
39242  *       edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization
39243  *       also need referring to bit CTRL[REV]).
39244  */
39245 #define EQDC_CTRL2_OPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK)
39246 
39247 #define EQDC_CTRL2_LDMOD_MASK                    (0x8U)
39248 #define EQDC_CTRL2_LDMOD_SHIFT                   (3U)
39249 /*! LDMOD - Buffered Register Load (Update) Mode Select
39250  *  0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.
39251  *  0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
39252  */
39253 #define EQDC_CTRL2_LDMOD(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK)
39254 
39255 #define EQDC_CTRL2_REVMOD_MASK                   (0x100U)
39256 #define EQDC_CTRL2_REVMOD_SHIFT                  (8U)
39257 /*! REVMOD - Revolution Counter Modulus Enable
39258  *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
39259  *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
39260  */
39261 #define EQDC_CTRL2_REVMOD(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK)
39262 
39263 #define EQDC_CTRL2_OUTCTL_MASK                   (0x200U)
39264 #define EQDC_CTRL2_OUTCTL_SHIFT                  (9U)
39265 /*! OUTCTL - Output Control
39266  *  0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value
39267  *       (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value
39268  *       (UCOMPx/LCOMPx)(x range is 0-3)
39269  *  0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read
39270  */
39271 #define EQDC_CTRL2_OUTCTL(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK)
39272 
39273 #define EQDC_CTRL2_PMEN_MASK                     (0x400U)
39274 #define EQDC_CTRL2_PMEN_SHIFT                    (10U)
39275 /*! PMEN - Period measurement function enable
39276  *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read.
39277  *  0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read.
39278  */
39279 #define EQDC_CTRL2_PMEN(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK)
39280 
39281 #define EQDC_CTRL2_INITPOS_MASK                  (0x1000U)
39282 #define EQDC_CTRL2_INITPOS_SHIFT                 (12U)
39283 /*! INITPOS - Initial Position Register
39284  *  0b0..Don't initialize position counter on rising edge of TRIGGER
39285  *  0b1..Initialize position counter on rising edge of TRIGGER
39286  */
39287 #define EQDC_CTRL2_INITPOS(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK)
39288 
39289 #define EQDC_CTRL2_ONCE_MASK                     (0x2000U)
39290 #define EQDC_CTRL2_ONCE_SHIFT                    (13U)
39291 /*! ONCE - Count Once
39292  *  0b0..Position counter counts repeatedly
39293  *  0b1..Position counter counts until roll-over or roll-under, then stop.
39294  */
39295 #define EQDC_CTRL2_ONCE(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK)
39296 
39297 #define EQDC_CTRL2_CMODE_MASK                    (0xC000U)
39298 #define EQDC_CTRL2_CMODE_SHIFT                   (14U)
39299 /*! CMODE - Counting Mode */
39300 #define EQDC_CTRL2_CMODE(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK)
39301 /*! @} */
39302 
39303 /*! @name FILT - Input Filter Register */
39304 /*! @{ */
39305 
39306 #define EQDC_FILT_FILT_PER_MASK                  (0xFFU)
39307 #define EQDC_FILT_FILT_PER_SHIFT                 (0U)
39308 /*! FILT_PER - Input Filter Sample Period */
39309 #define EQDC_FILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK)
39310 
39311 #define EQDC_FILT_FILT_CNT_MASK                  (0x700U)
39312 #define EQDC_FILT_FILT_CNT_SHIFT                 (8U)
39313 /*! FILT_CNT - Input Filter Sample Count */
39314 #define EQDC_FILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK)
39315 
39316 #define EQDC_FILT_FILT_CS_MASK                   (0x800U)
39317 #define EQDC_FILT_FILT_CS_SHIFT                  (11U)
39318 /*! FILT_CS - Filter Clock Source selection
39319  *  0b0..Peripheral Clock
39320  *  0b1..Prescaled peripheral clock by PRSC
39321  */
39322 #define EQDC_FILT_FILT_CS(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK)
39323 
39324 #define EQDC_FILT_PRSC_MASK                      (0xF000U)
39325 #define EQDC_FILT_PRSC_SHIFT                     (12U)
39326 /*! PRSC - Prescaler */
39327 #define EQDC_FILT_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK)
39328 /*! @} */
39329 
39330 /*! @name LASTEDGE - Last Edge Time Register */
39331 /*! @{ */
39332 
39333 #define EQDC_LASTEDGE_LASTEDGE_MASK              (0xFFFFU)
39334 #define EQDC_LASTEDGE_LASTEDGE_SHIFT             (0U)
39335 /*! LASTEDGE - Last Edge Time Counter */
39336 #define EQDC_LASTEDGE_LASTEDGE(x)                (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK)
39337 /*! @} */
39338 
39339 /*! @name POSDPER - Position Difference Period Counter Register */
39340 /*! @{ */
39341 
39342 #define EQDC_POSDPER_POSDPER_MASK                (0xFFFFU)
39343 #define EQDC_POSDPER_POSDPER_SHIFT               (0U)
39344 /*! POSDPER - Position difference period */
39345 #define EQDC_POSDPER_POSDPER(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK)
39346 /*! @} */
39347 
39348 /*! @name POSDPERBFR - Position Difference Period Buffer Register */
39349 /*! @{ */
39350 
39351 #define EQDC_POSDPERBFR_POSDPERBFR_MASK          (0xFFFFU)
39352 #define EQDC_POSDPERBFR_POSDPERBFR_SHIFT         (0U)
39353 /*! POSDPERBFR - Position difference period buffer */
39354 #define EQDC_POSDPERBFR_POSDPERBFR(x)            (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK)
39355 /*! @} */
39356 
39357 /*! @name UPOS - Upper Position Counter Register */
39358 /*! @{ */
39359 
39360 #define EQDC_UPOS_POS_MASK                       (0xFFFFU)
39361 #define EQDC_UPOS_POS_SHIFT                      (0U)
39362 /*! POS - POS */
39363 #define EQDC_UPOS_POS(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK)
39364 /*! @} */
39365 
39366 /*! @name LPOS - Lower Position Counter Register */
39367 /*! @{ */
39368 
39369 #define EQDC_LPOS_POS_MASK                       (0xFFFFU)
39370 #define EQDC_LPOS_POS_SHIFT                      (0U)
39371 /*! POS - POS */
39372 #define EQDC_LPOS_POS(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK)
39373 /*! @} */
39374 
39375 /*! @name POSD - Position Difference Counter Register */
39376 /*! @{ */
39377 
39378 #define EQDC_POSD_POSD_MASK                      (0xFFFFU)
39379 #define EQDC_POSD_POSD_SHIFT                     (0U)
39380 /*! POSD - POSD */
39381 #define EQDC_POSD_POSD(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK)
39382 /*! @} */
39383 
39384 /*! @name POSDH - Position Difference Hold Register */
39385 /*! @{ */
39386 
39387 #define EQDC_POSDH_POSDH_MASK                    (0xFFFFU)
39388 #define EQDC_POSDH_POSDH_SHIFT                   (0U)
39389 /*! POSDH - POSDH */
39390 #define EQDC_POSDH_POSDH(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK)
39391 /*! @} */
39392 
39393 /*! @name UPOSH - Upper Position Hold Register */
39394 /*! @{ */
39395 
39396 #define EQDC_UPOSH_POSH_MASK                     (0xFFFFU)
39397 #define EQDC_UPOSH_POSH_SHIFT                    (0U)
39398 /*! POSH - POSH */
39399 #define EQDC_UPOSH_POSH(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK)
39400 /*! @} */
39401 
39402 /*! @name LPOSH - Lower Position Hold Register */
39403 /*! @{ */
39404 
39405 #define EQDC_LPOSH_LPOSH_MASK                    (0xFFFFU)
39406 #define EQDC_LPOSH_LPOSH_SHIFT                   (0U)
39407 /*! LPOSH - POSH */
39408 #define EQDC_LPOSH_LPOSH(x)                      (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK)
39409 /*! @} */
39410 
39411 /*! @name LASTEDGEH - Last Edge Time Hold Register */
39412 /*! @{ */
39413 
39414 #define EQDC_LASTEDGEH_LASTEDGEH_MASK            (0xFFFFU)
39415 #define EQDC_LASTEDGEH_LASTEDGEH_SHIFT           (0U)
39416 /*! LASTEDGEH - Last Edge Time Hold */
39417 #define EQDC_LASTEDGEH_LASTEDGEH(x)              (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK)
39418 /*! @} */
39419 
39420 /*! @name POSDPERH - Position Difference Period Hold Register */
39421 /*! @{ */
39422 
39423 #define EQDC_POSDPERH_POSDPERH_MASK              (0xFFFFU)
39424 #define EQDC_POSDPERH_POSDPERH_SHIFT             (0U)
39425 /*! POSDPERH - Position difference period hold */
39426 #define EQDC_POSDPERH_POSDPERH(x)                (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK)
39427 /*! @} */
39428 
39429 /*! @name REVH - Revolution Hold Register */
39430 /*! @{ */
39431 
39432 #define EQDC_REVH_REVH_MASK                      (0xFFFFU)
39433 #define EQDC_REVH_REVH_SHIFT                     (0U)
39434 /*! REVH - REVH */
39435 #define EQDC_REVH_REVH(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK)
39436 /*! @} */
39437 
39438 /*! @name REV - Revolution Counter Register */
39439 /*! @{ */
39440 
39441 #define EQDC_REV_REV_MASK                        (0xFFFFU)
39442 #define EQDC_REV_REV_SHIFT                       (0U)
39443 /*! REV - REV */
39444 #define EQDC_REV_REV(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK)
39445 /*! @} */
39446 
39447 /*! @name UINIT - Upper Initialization Register */
39448 /*! @{ */
39449 
39450 #define EQDC_UINIT_INIT_MASK                     (0xFFFFU)
39451 #define EQDC_UINIT_INIT_SHIFT                    (0U)
39452 /*! INIT - INIT */
39453 #define EQDC_UINIT_INIT(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK)
39454 /*! @} */
39455 
39456 /*! @name LINIT - Lower Initialization Register */
39457 /*! @{ */
39458 
39459 #define EQDC_LINIT_INIT_MASK                     (0xFFFFU)
39460 #define EQDC_LINIT_INIT_SHIFT                    (0U)
39461 /*! INIT - INIT */
39462 #define EQDC_LINIT_INIT(x)                       (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK)
39463 /*! @} */
39464 
39465 /*! @name UMOD - Upper Modulus Register */
39466 /*! @{ */
39467 
39468 #define EQDC_UMOD_MOD_MASK                       (0xFFFFU)
39469 #define EQDC_UMOD_MOD_SHIFT                      (0U)
39470 /*! MOD - MOD */
39471 #define EQDC_UMOD_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK)
39472 /*! @} */
39473 
39474 /*! @name LMOD - Lower Modulus Register */
39475 /*! @{ */
39476 
39477 #define EQDC_LMOD_MOD_MASK                       (0xFFFFU)
39478 #define EQDC_LMOD_MOD_SHIFT                      (0U)
39479 /*! MOD - MOD */
39480 #define EQDC_LMOD_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK)
39481 /*! @} */
39482 
39483 /*! @name UCOMP0 - Upper Position Compare Register 0 */
39484 /*! @{ */
39485 
39486 #define EQDC_UCOMP0_UCOMP0_MASK                  (0xFFFFU)
39487 #define EQDC_UCOMP0_UCOMP0_SHIFT                 (0U)
39488 /*! UCOMP0 - UCOMP0 */
39489 #define EQDC_UCOMP0_UCOMP0(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK)
39490 /*! @} */
39491 
39492 /*! @name LCOMP0 - Lower Position Compare Register 0 */
39493 /*! @{ */
39494 
39495 #define EQDC_LCOMP0_LCOMP0_MASK                  (0xFFFFU)
39496 #define EQDC_LCOMP0_LCOMP0_SHIFT                 (0U)
39497 /*! LCOMP0 - LCOMP0 */
39498 #define EQDC_LCOMP0_LCOMP0(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK)
39499 /*! @} */
39500 
39501 /*! @name UCOMP1 - Upper Position Compare 1 */
39502 /*! @{ */
39503 
39504 #define EQDC_UCOMP1_UCOMP1_MASK                  (0xFFFFU)
39505 #define EQDC_UCOMP1_UCOMP1_SHIFT                 (0U)
39506 /*! UCOMP1 - UCOMP1 */
39507 #define EQDC_UCOMP1_UCOMP1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK)
39508 /*! @} */
39509 
39510 /*! @name UPOSH1 - Upper Position Holder Register 1 */
39511 /*! @{ */
39512 
39513 #define EQDC_UPOSH1_UPOSH1_MASK                  (0xFFFFU)
39514 #define EQDC_UPOSH1_UPOSH1_SHIFT                 (0U)
39515 /*! UPOSH1 - UPOSH1 */
39516 #define EQDC_UPOSH1_UPOSH1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK)
39517 /*! @} */
39518 
39519 /*! @name LCOMP1 - Lower Position Compare 1 */
39520 /*! @{ */
39521 
39522 #define EQDC_LCOMP1_LCOMP1_MASK                  (0xFFFFU)
39523 #define EQDC_LCOMP1_LCOMP1_SHIFT                 (0U)
39524 /*! LCOMP1 - LCOMP1 */
39525 #define EQDC_LCOMP1_LCOMP1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK)
39526 /*! @} */
39527 
39528 /*! @name LPOSH1 - Lower Position Holder Register 1 */
39529 /*! @{ */
39530 
39531 #define EQDC_LPOSH1_LPOSH1_MASK                  (0xFFFFU)
39532 #define EQDC_LPOSH1_LPOSH1_SHIFT                 (0U)
39533 /*! LPOSH1 - LPOSH1 */
39534 #define EQDC_LPOSH1_LPOSH1(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK)
39535 /*! @} */
39536 
39537 /*! @name UCOMP2 - Upper Position Compare 2 */
39538 /*! @{ */
39539 
39540 #define EQDC_UCOMP2_UCOMP2_MASK                  (0xFFFFU)
39541 #define EQDC_UCOMP2_UCOMP2_SHIFT                 (0U)
39542 /*! UCOMP2 - UCOMP2 */
39543 #define EQDC_UCOMP2_UCOMP2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK)
39544 /*! @} */
39545 
39546 /*! @name UPOSH2 - Upper Position Holder Register 3 */
39547 /*! @{ */
39548 
39549 #define EQDC_UPOSH2_UPOSH2_MASK                  (0xFFFFU)
39550 #define EQDC_UPOSH2_UPOSH2_SHIFT                 (0U)
39551 /*! UPOSH2 - UPOSH2 */
39552 #define EQDC_UPOSH2_UPOSH2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK)
39553 /*! @} */
39554 
39555 /*! @name LCOMP2 - Lower Position Compare 2 */
39556 /*! @{ */
39557 
39558 #define EQDC_LCOMP2_LCOMP2_MASK                  (0xFFFFU)
39559 #define EQDC_LCOMP2_LCOMP2_SHIFT                 (0U)
39560 /*! LCOMP2 - LCOMP2 */
39561 #define EQDC_LCOMP2_LCOMP2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK)
39562 /*! @} */
39563 
39564 /*! @name LPOSH2 - Lower Position Holder Register 2 */
39565 /*! @{ */
39566 
39567 #define EQDC_LPOSH2_LPOSH2_MASK                  (0xFFFFU)
39568 #define EQDC_LPOSH2_LPOSH2_SHIFT                 (0U)
39569 /*! LPOSH2 - LPOSH2 */
39570 #define EQDC_LPOSH2_LPOSH2(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK)
39571 /*! @} */
39572 
39573 /*! @name UCOMP3 - Upper Position Compare 3 */
39574 /*! @{ */
39575 
39576 #define EQDC_UCOMP3_UCOMP3_MASK                  (0xFFFFU)
39577 #define EQDC_UCOMP3_UCOMP3_SHIFT                 (0U)
39578 /*! UCOMP3 - UCOMP3 */
39579 #define EQDC_UCOMP3_UCOMP3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK)
39580 /*! @} */
39581 
39582 /*! @name UPOSH3 - Upper Position Holder Register 3 */
39583 /*! @{ */
39584 
39585 #define EQDC_UPOSH3_UPOSH3_MASK                  (0xFFFFU)
39586 #define EQDC_UPOSH3_UPOSH3_SHIFT                 (0U)
39587 /*! UPOSH3 - UPOSH3 */
39588 #define EQDC_UPOSH3_UPOSH3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK)
39589 /*! @} */
39590 
39591 /*! @name LCOMP3 - Lower Position Compare 3 */
39592 /*! @{ */
39593 
39594 #define EQDC_LCOMP3_LCOMP3_MASK                  (0xFFFFU)
39595 #define EQDC_LCOMP3_LCOMP3_SHIFT                 (0U)
39596 /*! LCOMP3 - LCOMP3 */
39597 #define EQDC_LCOMP3_LCOMP3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK)
39598 /*! @} */
39599 
39600 /*! @name LPOSH3 - Lower Position Holder Register 3 */
39601 /*! @{ */
39602 
39603 #define EQDC_LPOSH3_LPOSH3_MASK                  (0xFFFFU)
39604 #define EQDC_LPOSH3_LPOSH3_SHIFT                 (0U)
39605 /*! LPOSH3 - LPOSH3 */
39606 #define EQDC_LPOSH3_LPOSH3(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK)
39607 /*! @} */
39608 
39609 /*! @name INTCTRL - Interrupt Control Register */
39610 /*! @{ */
39611 
39612 #define EQDC_INTCTRL_SABIE_MASK                  (0x1U)
39613 #define EQDC_INTCTRL_SABIE_SHIFT                 (0U)
39614 /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
39615  *  0b0..Disabled
39616  *  0b1..Enabled
39617  */
39618 #define EQDC_INTCTRL_SABIE(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK)
39619 
39620 #define EQDC_INTCTRL_SABIRQ_MASK                 (0x2U)
39621 #define EQDC_INTCTRL_SABIRQ_SHIFT                (1U)
39622 /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
39623  *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
39624  *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
39625  */
39626 #define EQDC_INTCTRL_SABIRQ(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK)
39627 
39628 #define EQDC_INTCTRL_DIRIE_MASK                  (0x4U)
39629 #define EQDC_INTCTRL_DIRIE_SHIFT                 (2U)
39630 /*! DIRIE - Count direction change interrupt enable
39631  *  0b0..Disabled
39632  *  0b1..Enabled
39633  */
39634 #define EQDC_INTCTRL_DIRIE(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK)
39635 
39636 #define EQDC_INTCTRL_DIRIRQ_MASK                 (0x8U)
39637 #define EQDC_INTCTRL_DIRIRQ_SHIFT                (3U)
39638 /*! DIRIRQ - Count direction change interrupt
39639  *  0b0..Count direction unchanged
39640  *  0b1..Count direction changed
39641  */
39642 #define EQDC_INTCTRL_DIRIRQ(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK)
39643 
39644 #define EQDC_INTCTRL_RUIE_MASK                   (0x10U)
39645 #define EQDC_INTCTRL_RUIE_SHIFT                  (4U)
39646 /*! RUIE - Roll-under Interrupt Enable
39647  *  0b0..Disabled
39648  *  0b1..Enabled
39649  */
39650 #define EQDC_INTCTRL_RUIE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK)
39651 
39652 #define EQDC_INTCTRL_RUIRQ_MASK                  (0x20U)
39653 #define EQDC_INTCTRL_RUIRQ_SHIFT                 (5U)
39654 /*! RUIRQ - Roll-under Interrupt Request
39655  *  0b0..No roll-under has occurred
39656  *  0b1..Roll-under has occurred
39657  */
39658 #define EQDC_INTCTRL_RUIRQ(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK)
39659 
39660 #define EQDC_INTCTRL_ROIE_MASK                   (0x40U)
39661 #define EQDC_INTCTRL_ROIE_SHIFT                  (6U)
39662 /*! ROIE - Roll-over Interrupt Enable
39663  *  0b0..Disabled
39664  *  0b1..Enabled
39665  */
39666 #define EQDC_INTCTRL_ROIE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK)
39667 
39668 #define EQDC_INTCTRL_ROIRQ_MASK                  (0x80U)
39669 #define EQDC_INTCTRL_ROIRQ_SHIFT                 (7U)
39670 /*! ROIRQ - Roll-over Interrupt Request
39671  *  0b0..No roll-over has occurred
39672  *  0b1..Roll-over has occurred
39673  */
39674 #define EQDC_INTCTRL_ROIRQ(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK)
39675 
39676 #define EQDC_INTCTRL_CMP0IRQ_MASK                (0x200U)
39677 #define EQDC_INTCTRL_CMP0IRQ_SHIFT               (9U)
39678 /*! CMP0IRQ - Compare 0 Interrupt Request
39679  *  0b0..No match has occurred (the position counter does not match the COMP0 value)
39680  *  0b1..COMP match has occurred (the position counter matches the COMP0 value)
39681  */
39682 #define EQDC_INTCTRL_CMP0IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK)
39683 
39684 #define EQDC_INTCTRL_CMP1IRQ_MASK                (0x800U)
39685 #define EQDC_INTCTRL_CMP1IRQ_SHIFT               (11U)
39686 /*! CMP1IRQ - Compare1 Interrupt Request
39687  *  0b0..No match has occurred (the position counter does not match the COMP1 value)
39688  *  0b1..COMP1 match has occurred (the position counter matches the COMP1 value)
39689  */
39690 #define EQDC_INTCTRL_CMP1IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK)
39691 
39692 #define EQDC_INTCTRL_CMP2IRQ_MASK                (0x2000U)
39693 #define EQDC_INTCTRL_CMP2IRQ_SHIFT               (13U)
39694 /*! CMP2IRQ - Compare2 Interrupt Request
39695  *  0b0..No match has occurred (the position counter does not match the COMP2 value)
39696  *  0b1..COMP2 match has occurred (the position counter matches the COMP2 value)
39697  */
39698 #define EQDC_INTCTRL_CMP2IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK)
39699 
39700 #define EQDC_INTCTRL_CMP3IRQ_MASK                (0x8000U)
39701 #define EQDC_INTCTRL_CMP3IRQ_SHIFT               (15U)
39702 /*! CMP3IRQ - Compare3 Interrupt Request
39703  *  0b0..No match has occurred (the position counter does not match the COMP3 value)
39704  *  0b1..COMP3 match has occurred (the position counter matches the COMP3 value)
39705  */
39706 #define EQDC_INTCTRL_CMP3IRQ(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK)
39707 /*! @} */
39708 
39709 /*! @name WTR - Watchdog Timeout Register */
39710 /*! @{ */
39711 
39712 #define EQDC_WTR_WDOG_MASK                       (0xFFFFU)
39713 #define EQDC_WTR_WDOG_SHIFT                      (0U)
39714 /*! WDOG - WDOG */
39715 #define EQDC_WTR_WDOG(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK)
39716 /*! @} */
39717 
39718 /*! @name IMR - Input Monitor Register */
39719 /*! @{ */
39720 
39721 #define EQDC_IMR_HOME_ENABLE_MASK                (0x1U)
39722 #define EQDC_IMR_HOME_ENABLE_SHIFT               (0U)
39723 /*! HOME_ENABLE - HOME_ENABLE */
39724 #define EQDC_IMR_HOME_ENABLE(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK)
39725 
39726 #define EQDC_IMR_INDEX_PRESET_MASK               (0x2U)
39727 #define EQDC_IMR_INDEX_PRESET_SHIFT              (1U)
39728 /*! INDEX_PRESET - INDEX_PRESET */
39729 #define EQDC_IMR_INDEX_PRESET(x)                 (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK)
39730 
39731 #define EQDC_IMR_PHB_MASK                        (0x4U)
39732 #define EQDC_IMR_PHB_SHIFT                       (2U)
39733 /*! PHB - PHB */
39734 #define EQDC_IMR_PHB(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK)
39735 
39736 #define EQDC_IMR_PHA_MASK                        (0x8U)
39737 #define EQDC_IMR_PHA_SHIFT                       (3U)
39738 /*! PHA - PHA */
39739 #define EQDC_IMR_PHA(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK)
39740 
39741 #define EQDC_IMR_FHOM_ENA_MASK                   (0x10U)
39742 #define EQDC_IMR_FHOM_ENA_SHIFT                  (4U)
39743 /*! FHOM_ENA - filter operation on HOME/ENABLE input */
39744 #define EQDC_IMR_FHOM_ENA(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK)
39745 
39746 #define EQDC_IMR_FIND_PRE_MASK                   (0x20U)
39747 #define EQDC_IMR_FIND_PRE_SHIFT                  (5U)
39748 /*! FIND_PRE - filter operation on INDEX/PRESET input */
39749 #define EQDC_IMR_FIND_PRE(x)                     (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK)
39750 
39751 #define EQDC_IMR_FPHB_MASK                       (0x40U)
39752 #define EQDC_IMR_FPHB_SHIFT                      (6U)
39753 /*! FPHB - filter operation on PHASEB input */
39754 #define EQDC_IMR_FPHB(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK)
39755 
39756 #define EQDC_IMR_FPHA_MASK                       (0x80U)
39757 #define EQDC_IMR_FPHA_SHIFT                      (7U)
39758 /*! FPHA - filter operation on PHASEA input */
39759 #define EQDC_IMR_FPHA(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK)
39760 
39761 #define EQDC_IMR_CMPF0_MASK                      (0x100U)
39762 #define EQDC_IMR_CMPF0_SHIFT                     (8U)
39763 /*! CMPF0 - Position Compare 0 Flag Output
39764  *  0b0..When the position counter is less than value of COMP0 register
39765  *  0b1..When the position counter is greater or equal than value of COMP0 register
39766  */
39767 #define EQDC_IMR_CMPF0(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK)
39768 
39769 #define EQDC_IMR_CMP1F_MASK                      (0x200U)
39770 #define EQDC_IMR_CMP1F_SHIFT                     (9U)
39771 /*! CMP1F - Position Compare1 Flag Output
39772  *  0b0..When the position counter is less than value of COMP1 register
39773  *  0b1..When the position counter is greater or equal than value of COMP1 register
39774  */
39775 #define EQDC_IMR_CMP1F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK)
39776 
39777 #define EQDC_IMR_CMP2F_MASK                      (0x400U)
39778 #define EQDC_IMR_CMP2F_SHIFT                     (10U)
39779 /*! CMP2F - Position Compare2 Flag Output
39780  *  0b0..When the position counter is less than value of COMP2 register
39781  *  0b1..When the position counter is greater or equal than value of COMP2 register
39782  */
39783 #define EQDC_IMR_CMP2F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK)
39784 
39785 #define EQDC_IMR_CMP3F_MASK                      (0x800U)
39786 #define EQDC_IMR_CMP3F_SHIFT                     (11U)
39787 /*! CMP3F - Position Compare3 Flag Output
39788  *  0b0..When the position counter value is less than value of COMP3 register
39789  *  0b1..When the position counter is greater or equal than value of COMP3 register
39790  */
39791 #define EQDC_IMR_CMP3F(x)                        (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK)
39792 
39793 #define EQDC_IMR_DIRH_MASK                       (0x4000U)
39794 #define EQDC_IMR_DIRH_SHIFT                      (14U)
39795 /*! DIRH - Count Direction Flag Hold */
39796 #define EQDC_IMR_DIRH(x)                         (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK)
39797 
39798 #define EQDC_IMR_DIR_MASK                        (0x8000U)
39799 #define EQDC_IMR_DIR_SHIFT                       (15U)
39800 /*! DIR - Count Direction Flag Output
39801  *  0b0..Current count was in the down direction
39802  *  0b1..Current count was in the up direction
39803  */
39804 #define EQDC_IMR_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK)
39805 /*! @} */
39806 
39807 /*! @name TST - Test Register */
39808 /*! @{ */
39809 
39810 #define EQDC_TST_TEST_COUNT_MASK                 (0xFFU)
39811 #define EQDC_TST_TEST_COUNT_SHIFT                (0U)
39812 /*! TEST_COUNT - TEST_COUNT */
39813 #define EQDC_TST_TEST_COUNT(x)                   (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK)
39814 
39815 #define EQDC_TST_TEST_PERIOD_MASK                (0x1F00U)
39816 #define EQDC_TST_TEST_PERIOD_SHIFT               (8U)
39817 /*! TEST_PERIOD - TEST_PERIOD */
39818 #define EQDC_TST_TEST_PERIOD(x)                  (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK)
39819 
39820 #define EQDC_TST_QDN_MASK                        (0x2000U)
39821 #define EQDC_TST_QDN_SHIFT                       (13U)
39822 /*! QDN - Quadrature Decoder Negative Signal
39823  *  0b0..Generates a positive quadrature decoder signal
39824  *  0b1..Generates a negative quadrature decoder signal
39825  */
39826 #define EQDC_TST_QDN(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK)
39827 
39828 #define EQDC_TST_TCE_MASK                        (0x4000U)
39829 #define EQDC_TST_TCE_SHIFT                       (14U)
39830 /*! TCE - Test Counter Enable
39831  *  0b0..Disabled
39832  *  0b1..Enabled
39833  */
39834 #define EQDC_TST_TCE(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK)
39835 
39836 #define EQDC_TST_TEN_MASK                        (0x8000U)
39837 #define EQDC_TST_TEN_SHIFT                       (15U)
39838 /*! TEN - Test Mode Enable
39839  *  0b0..Disabled
39840  *  0b1..Enabled
39841  */
39842 #define EQDC_TST_TEN(x)                          (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK)
39843 /*! @} */
39844 
39845 /*! @name UVERID - Upper VERID */
39846 /*! @{ */
39847 
39848 #define EQDC_UVERID_UVERID_MASK                  (0xFFFFU)
39849 #define EQDC_UVERID_UVERID_SHIFT                 (0U)
39850 /*! UVERID - UVERID */
39851 #define EQDC_UVERID_UVERID(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK)
39852 /*! @} */
39853 
39854 /*! @name LVERID - Lower VERID */
39855 /*! @{ */
39856 
39857 #define EQDC_LVERID_LVERID_MASK                  (0xFFFFU)
39858 #define EQDC_LVERID_LVERID_SHIFT                 (0U)
39859 /*! LVERID - LVERID */
39860 #define EQDC_LVERID_LVERID(x)                    (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK)
39861 /*! @} */
39862 
39863 
39864 /*!
39865  * @}
39866  */ /* end of group EQDC_Register_Masks */
39867 
39868 
39869 /* EQDC - Peripheral instance base addresses */
39870 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
39871   /** Peripheral EQDC1 base address */
39872   #define EQDC1_BASE                               (0x52710000u)
39873   /** Peripheral EQDC1 base address */
39874   #define EQDC1_BASE_NS                            (0x42710000u)
39875   /** Peripheral EQDC1 base pointer */
39876   #define EQDC1                                    ((EQDC_Type *)EQDC1_BASE)
39877   /** Peripheral EQDC1 base pointer */
39878   #define EQDC1_NS                                 ((EQDC_Type *)EQDC1_BASE_NS)
39879   /** Peripheral EQDC2 base address */
39880   #define EQDC2_BASE                               (0x52720000u)
39881   /** Peripheral EQDC2 base address */
39882   #define EQDC2_BASE_NS                            (0x42720000u)
39883   /** Peripheral EQDC2 base pointer */
39884   #define EQDC2                                    ((EQDC_Type *)EQDC2_BASE)
39885   /** Peripheral EQDC2 base pointer */
39886   #define EQDC2_NS                                 ((EQDC_Type *)EQDC2_BASE_NS)
39887   /** Array initializer of EQDC peripheral base addresses */
39888   #define EQDC_BASE_ADDRS                          { 0u, EQDC1_BASE, EQDC2_BASE }
39889   /** Array initializer of EQDC peripheral base pointers */
39890   #define EQDC_BASE_PTRS                           { (EQDC_Type *)0u, EQDC1, EQDC2 }
39891   /** Array initializer of EQDC peripheral base addresses */
39892   #define EQDC_BASE_ADDRS_NS                       { 0u, EQDC1_BASE_NS, EQDC2_BASE_NS }
39893   /** Array initializer of EQDC peripheral base pointers */
39894   #define EQDC_BASE_PTRS_NS                        { (EQDC_Type *)0u, EQDC1_NS, EQDC2_NS }
39895 #else
39896   /** Peripheral EQDC1 base address */
39897   #define EQDC1_BASE                               (0x42710000u)
39898   /** Peripheral EQDC1 base pointer */
39899   #define EQDC1                                    ((EQDC_Type *)EQDC1_BASE)
39900   /** Peripheral EQDC2 base address */
39901   #define EQDC2_BASE                               (0x42720000u)
39902   /** Peripheral EQDC2 base pointer */
39903   #define EQDC2                                    ((EQDC_Type *)EQDC2_BASE)
39904   /** Array initializer of EQDC peripheral base addresses */
39905   #define EQDC_BASE_ADDRS                          { 0u, EQDC1_BASE, EQDC2_BASE }
39906   /** Array initializer of EQDC peripheral base pointers */
39907   #define EQDC_BASE_PTRS                           { (EQDC_Type *)0u, EQDC1, EQDC2 }
39908 #endif
39909 /** Interrupt vectors for the EQDC peripheral type */
39910 #define EQDC_COMPARE_IRQS                        { NotAvail_IRQn, EQDC1_IRQn, EQDC2_IRQn }
39911 #define EQDC_HOME_IRQS                           { NotAvail_IRQn, EQDC1_IRQn, EQDC2_IRQn }
39912 #define EQDC_WDOG_IRQS                           { NotAvail_IRQn, EQDC1_IRQn, EQDC2_IRQn }
39913 #define EQDC_INDEX_IRQS                          { NotAvail_IRQn, EQDC1_IRQn, EQDC2_IRQn }
39914 #define EQDC_INPUT_SWITCH_IRQS                   { NotAvail_IRQn, EQDC1_IRQn, EQDC2_IRQn }
39915 
39916 /*!
39917  * @}
39918  */ /* end of group EQDC_Peripheral_Access_Layer */
39919 
39920 
39921 /* ----------------------------------------------------------------------------
39922    -- ERM Peripheral Access Layer
39923    ---------------------------------------------------------------------------- */
39924 
39925 /*!
39926  * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer
39927  * @{
39928  */
39929 
39930 /** ERM - Register Layout Typedef */
39931 typedef struct {
39932   __IO uint32_t CR0;                               /**< ERM Configuration Register 0, offset: 0x0 */
39933        uint8_t RESERVED_0[12];
39934   __IO uint32_t SR0;                               /**< ERM Status Register 0, offset: 0x10 */
39935        uint8_t RESERVED_1[244];
39936   struct {                                         /* offset: 0x108, array step: 0x10 */
39937     __IO uint32_t CORR_ERR;                          /**< ERM Memory 0 Correctable Error Count Register..ERM Memory 3 Correctable Error Count Register, array offset: 0x108, array step: 0x10 */
39938          uint8_t RESERVED_0[12];
39939   } CORR_ERR_CNT[4];
39940 } ERM_Type;
39941 
39942 /* ----------------------------------------------------------------------------
39943    -- ERM Register Masks
39944    ---------------------------------------------------------------------------- */
39945 
39946 /*!
39947  * @addtogroup ERM_Register_Masks ERM Register Masks
39948  * @{
39949  */
39950 
39951 /*! @name CR0 - ERM Configuration Register 0 */
39952 /*! @{ */
39953 
39954 #define ERM_CR0_ENCIE3_MASK                      (0x40000U)
39955 #define ERM_CR0_ENCIE3_SHIFT                     (18U)
39956 /*! ENCIE3 - ENCIE3
39957  *  0b0..Interrupt notification of Memory 3 non-correctable error events is disabled.
39958  *  0b1..Interrupt notification of Memory 3 non-correctable error events is enabled.
39959  */
39960 #define ERM_CR0_ENCIE3(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK)
39961 
39962 #define ERM_CR0_ESCIE3_MASK                      (0x80000U)
39963 #define ERM_CR0_ESCIE3_SHIFT                     (19U)
39964 /*! ESCIE3 - ESCIE3
39965  *  0b0..Interrupt notification of Memory 3 single-bit correction events is disabled.
39966  *  0b1..Interrupt notification of Memory 3 single-bit correction events is enabled.
39967  */
39968 #define ERM_CR0_ESCIE3(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK)
39969 
39970 #define ERM_CR0_ENCIE2_MASK                      (0x400000U)
39971 #define ERM_CR0_ENCIE2_SHIFT                     (22U)
39972 /*! ENCIE2 - ENCIE2
39973  *  0b0..Interrupt notification of Memory 2 non-correctable error events is disabled.
39974  *  0b1..Interrupt notification of Memory 2 non-correctable error events is enabled.
39975  */
39976 #define ERM_CR0_ENCIE2(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK)
39977 
39978 #define ERM_CR0_ESCIE2_MASK                      (0x800000U)
39979 #define ERM_CR0_ESCIE2_SHIFT                     (23U)
39980 /*! ESCIE2 - ESCIE2
39981  *  0b0..Interrupt notification of Memory 2 single-bit correction events is disabled.
39982  *  0b1..Interrupt notification of Memory 2 single-bit correction events is enabled.
39983  */
39984 #define ERM_CR0_ESCIE2(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK)
39985 
39986 #define ERM_CR0_ENCIE1_MASK                      (0x4000000U)
39987 #define ERM_CR0_ENCIE1_SHIFT                     (26U)
39988 /*! ENCIE1 - ENCIE1
39989  *  0b0..Interrupt notification of Memory 1 non-correctable error events is disabled.
39990  *  0b1..Interrupt notification of Memory 1 non-correctable error events is enabled.
39991  */
39992 #define ERM_CR0_ENCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK)
39993 
39994 #define ERM_CR0_ESCIE1_MASK                      (0x8000000U)
39995 #define ERM_CR0_ESCIE1_SHIFT                     (27U)
39996 /*! ESCIE1 - ESCIE1
39997  *  0b0..Interrupt notification of Memory 1 single-bit correction events is disabled.
39998  *  0b1..Interrupt notification of Memory 1 single-bit correction events is enabled.
39999  */
40000 #define ERM_CR0_ESCIE1(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK)
40001 
40002 #define ERM_CR0_ENCIE0_MASK                      (0x40000000U)
40003 #define ERM_CR0_ENCIE0_SHIFT                     (30U)
40004 /*! ENCIE0 - ENCIE0
40005  *  0b0..Interrupt notification of Memory 0 non-correctable error events is disabled.
40006  *  0b1..Interrupt notification of Memory 0 non-correctable error events is enabled.
40007  */
40008 #define ERM_CR0_ENCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK)
40009 
40010 #define ERM_CR0_ESCIE0_MASK                      (0x80000000U)
40011 #define ERM_CR0_ESCIE0_SHIFT                     (31U)
40012 /*! ESCIE0 - ESCIE0
40013  *  0b0..Interrupt notification of Memory 0 single-bit correction events is disabled.
40014  *  0b1..Interrupt notification of Memory 0 single-bit correction events is enabled.
40015  */
40016 #define ERM_CR0_ESCIE0(x)                        (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK)
40017 /*! @} */
40018 
40019 /*! @name SR0 - ERM Status Register 0 */
40020 /*! @{ */
40021 
40022 #define ERM_SR0_NCE3_MASK                        (0x40000U)
40023 #define ERM_SR0_NCE3_SHIFT                       (18U)
40024 /*! NCE3 - NCE3
40025  *  0b0..No non-correctable error event on Memory 3 detected.
40026  *  0b1..Non-correctable error event on Memory 3 detected.
40027  */
40028 #define ERM_SR0_NCE3(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK)
40029 
40030 #define ERM_SR0_SBC3_MASK                        (0x80000U)
40031 #define ERM_SR0_SBC3_SHIFT                       (19U)
40032 /*! SBC3 - SBC3
40033  *  0b0..No single-bit correction event on Memory 3 detected.
40034  *  0b1..Single-bit correction event on Memory 3 detected.
40035  */
40036 #define ERM_SR0_SBC3(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK)
40037 
40038 #define ERM_SR0_NCE2_MASK                        (0x400000U)
40039 #define ERM_SR0_NCE2_SHIFT                       (22U)
40040 /*! NCE2 - NCE2
40041  *  0b0..No non-correctable error event on Memory 2 detected.
40042  *  0b1..Non-correctable error event on Memory 2 detected.
40043  */
40044 #define ERM_SR0_NCE2(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK)
40045 
40046 #define ERM_SR0_SBC2_MASK                        (0x800000U)
40047 #define ERM_SR0_SBC2_SHIFT                       (23U)
40048 /*! SBC2 - SBC2
40049  *  0b0..No single-bit correction event on Memory 2 detected.
40050  *  0b1..Single-bit correction event on Memory 2 detected.
40051  */
40052 #define ERM_SR0_SBC2(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK)
40053 
40054 #define ERM_SR0_NCE1_MASK                        (0x4000000U)
40055 #define ERM_SR0_NCE1_SHIFT                       (26U)
40056 /*! NCE1 - NCE1
40057  *  0b0..No non-correctable error event on Memory 1 detected.
40058  *  0b1..Non-correctable error event on Memory 1 detected.
40059  */
40060 #define ERM_SR0_NCE1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK)
40061 
40062 #define ERM_SR0_SBC1_MASK                        (0x8000000U)
40063 #define ERM_SR0_SBC1_SHIFT                       (27U)
40064 /*! SBC1 - SBC1
40065  *  0b0..No single-bit correction event on Memory 1 detected.
40066  *  0b1..Single-bit correction event on Memory 1 detected.
40067  */
40068 #define ERM_SR0_SBC1(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK)
40069 
40070 #define ERM_SR0_NCE0_MASK                        (0x40000000U)
40071 #define ERM_SR0_NCE0_SHIFT                       (30U)
40072 /*! NCE0 - NCE0
40073  *  0b0..No non-correctable error event on Memory 0 detected.
40074  *  0b1..Non-correctable error event on Memory 0 detected.
40075  */
40076 #define ERM_SR0_NCE0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK)
40077 
40078 #define ERM_SR0_SBC0_MASK                        (0x80000000U)
40079 #define ERM_SR0_SBC0_SHIFT                       (31U)
40080 /*! SBC0 - SBC0
40081  *  0b0..No single-bit correction event on Memory 0 detected.
40082  *  0b1..Single-bit correction event on Memory 0 detected.
40083  */
40084 #define ERM_SR0_SBC0(x)                          (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK)
40085 /*! @} */
40086 
40087 /*! @name CORR_ERR - ERM Memory 0 Correctable Error Count Register..ERM Memory 3 Correctable Error Count Register */
40088 /*! @{ */
40089 
40090 #define ERM_CORR_ERR_COUNT_MASK                  (0xFFU)
40091 #define ERM_CORR_ERR_COUNT_SHIFT                 (0U)
40092 /*! COUNT - Memory n Correctable Error Count */
40093 #define ERM_CORR_ERR_COUNT(x)                    (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_COUNT_SHIFT)) & ERM_CORR_ERR_COUNT_MASK)
40094 /*! @} */
40095 
40096 /* The count of ERM_CORR_ERR */
40097 #define ERM_CORR_ERR_CNT_CORR_ERR_COUNT          (4U)
40098 
40099 
40100 /*!
40101  * @}
40102  */ /* end of group ERM_Register_Masks */
40103 
40104 
40105 /* ERM - Peripheral instance base addresses */
40106 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
40107   /** Peripheral ERM base address */
40108   #define ERM_BASE                                 (0x5B864000u)
40109   /** Peripheral ERM base address */
40110   #define ERM_BASE_NS                              (0x4B864000u)
40111   /** Peripheral ERM base pointer */
40112   #define ERM                                      ((ERM_Type *)ERM_BASE)
40113   /** Peripheral ERM base pointer */
40114   #define ERM_NS                                   ((ERM_Type *)ERM_BASE_NS)
40115   /** Array initializer of ERM peripheral base addresses */
40116   #define ERM_BASE_ADDRS                           { ERM_BASE }
40117   /** Array initializer of ERM peripheral base pointers */
40118   #define ERM_BASE_PTRS                            { ERM }
40119   /** Array initializer of ERM peripheral base addresses */
40120   #define ERM_BASE_ADDRS_NS                        { ERM_BASE_NS }
40121   /** Array initializer of ERM peripheral base pointers */
40122   #define ERM_BASE_PTRS_NS                         { ERM_NS }
40123 #else
40124   /** Peripheral ERM base address */
40125   #define ERM_BASE                                 (0x4B864000u)
40126   /** Peripheral ERM base pointer */
40127   #define ERM                                      ((ERM_Type *)ERM_BASE)
40128   /** Array initializer of ERM peripheral base addresses */
40129   #define ERM_BASE_ADDRS                           { ERM_BASE }
40130   /** Array initializer of ERM peripheral base pointers */
40131   #define ERM_BASE_PTRS                            { ERM }
40132 #endif
40133 
40134 /*!
40135  * @}
40136  */ /* end of group ERM_Peripheral_Access_Layer */
40137 
40138 
40139 /* ----------------------------------------------------------------------------
40140    -- EWM Peripheral Access Layer
40141    ---------------------------------------------------------------------------- */
40142 
40143 /*!
40144  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
40145  * @{
40146  */
40147 
40148 /** EWM - Register Layout Typedef */
40149 typedef struct {
40150   __IO uint8_t CTRL;                               /**< Control, offset: 0x0 */
40151   __O  uint8_t SERV;                               /**< Service, offset: 0x1 */
40152   __IO uint8_t CMPL;                               /**< Compare Low, offset: 0x2 */
40153   __IO uint8_t CMPH;                               /**< Compare High, offset: 0x3 */
40154   __IO uint8_t CLKCTRL;                            /**< Clock Control, offset: 0x4 */
40155   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler, offset: 0x5 */
40156 } EWM_Type;
40157 
40158 /* ----------------------------------------------------------------------------
40159    -- EWM Register Masks
40160    ---------------------------------------------------------------------------- */
40161 
40162 /*!
40163  * @addtogroup EWM_Register_Masks EWM Register Masks
40164  * @{
40165  */
40166 
40167 /*! @name CTRL - Control */
40168 /*! @{ */
40169 
40170 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
40171 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
40172 /*! EWMEN - EWM Enable
40173  *  0b0..Disables
40174  *  0b1..Enables
40175  */
40176 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
40177 
40178 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
40179 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
40180 /*! ASSIN - Assertion State Select
40181  *  0b0..Logic 0
40182  *  0b1..Logic 1
40183  */
40184 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
40185 
40186 #define EWM_CTRL_INEN_MASK                       (0x4U)
40187 #define EWM_CTRL_INEN_SHIFT                      (2U)
40188 /*! INEN - Input Enable
40189  *  0b0..Disables
40190  *  0b1..Enables
40191  */
40192 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
40193 
40194 #define EWM_CTRL_INTEN_MASK                      (0x8U)
40195 #define EWM_CTRL_INTEN_SHIFT                     (3U)
40196 /*! INTEN - Interrupt Enable
40197  *  0b1..Generates interrupt requests
40198  *  0b0..Deasserts interrupt requests
40199  */
40200 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
40201 /*! @} */
40202 
40203 /*! @name SERV - Service */
40204 /*! @{ */
40205 
40206 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
40207 #define EWM_SERV_SERVICE_SHIFT                   (0U)
40208 /*! SERVICE - Service */
40209 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
40210 /*! @} */
40211 
40212 /*! @name CMPL - Compare Low */
40213 /*! @{ */
40214 
40215 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
40216 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
40217 /*! COMPAREL - Compare Low */
40218 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
40219 /*! @} */
40220 
40221 /*! @name CMPH - Compare High */
40222 /*! @{ */
40223 
40224 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
40225 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
40226 /*! COMPAREH - Compare High */
40227 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
40228 /*! @} */
40229 
40230 /*! @name CLKCTRL - Clock Control */
40231 /*! @{ */
40232 
40233 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
40234 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
40235 /*! CLKSEL - Clock Select */
40236 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
40237 /*! @} */
40238 
40239 /*! @name CLKPRESCALER - Clock Prescaler */
40240 /*! @{ */
40241 
40242 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
40243 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
40244 /*! CLK_DIV - Clock Divider */
40245 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
40246 /*! @} */
40247 
40248 
40249 /*!
40250  * @}
40251  */ /* end of group EWM_Register_Masks */
40252 
40253 
40254 /* EWM - Peripheral instance base addresses */
40255 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
40256   /** Peripheral EWM base address */
40257   #define EWM_BASE                                 (0x527B0000u)
40258   /** Peripheral EWM base address */
40259   #define EWM_BASE_NS                              (0x427B0000u)
40260   /** Peripheral EWM base pointer */
40261   #define EWM                                      ((EWM_Type *)EWM_BASE)
40262   /** Peripheral EWM base pointer */
40263   #define EWM_NS                                   ((EWM_Type *)EWM_BASE_NS)
40264   /** Array initializer of EWM peripheral base addresses */
40265   #define EWM_BASE_ADDRS                           { EWM_BASE }
40266   /** Array initializer of EWM peripheral base pointers */
40267   #define EWM_BASE_PTRS                            { EWM }
40268   /** Array initializer of EWM peripheral base addresses */
40269   #define EWM_BASE_ADDRS_NS                        { EWM_BASE_NS }
40270   /** Array initializer of EWM peripheral base pointers */
40271   #define EWM_BASE_PTRS_NS                         { EWM_NS }
40272 #else
40273   /** Peripheral EWM base address */
40274   #define EWM_BASE                                 (0x427B0000u)
40275   /** Peripheral EWM base pointer */
40276   #define EWM                                      ((EWM_Type *)EWM_BASE)
40277   /** Array initializer of EWM peripheral base addresses */
40278   #define EWM_BASE_ADDRS                           { EWM_BASE }
40279   /** Array initializer of EWM peripheral base pointers */
40280   #define EWM_BASE_PTRS                            { EWM }
40281 #endif
40282 /** Interrupt vectors for the EWM peripheral type */
40283 #define EWM_IRQS                                 { EWM_IRQn }
40284 
40285 /*!
40286  * @}
40287  */ /* end of group EWM_Peripheral_Access_Layer */
40288 
40289 
40290 /* ----------------------------------------------------------------------------
40291    -- FLEXIO Peripheral Access Layer
40292    ---------------------------------------------------------------------------- */
40293 
40294 /*!
40295  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
40296  * @{
40297  */
40298 
40299 /** FLEXIO - Register Layout Typedef */
40300 typedef struct {
40301   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
40302   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
40303   __IO uint32_t CTRL;                              /**< FLEXIO Control, offset: 0x8 */
40304   __I  uint32_t PIN;                               /**< Pin State, offset: 0xC */
40305   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status, offset: 0x10 */
40306   __IO uint32_t SHIFTERR;                          /**< Shifter Error, offset: 0x14 */
40307   __IO uint32_t TIMSTAT;                           /**< Timer Status, offset: 0x18 */
40308        uint8_t RESERVED_0[4];
40309   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
40310   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
40311   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable, offset: 0x28 */
40312        uint8_t RESERVED_1[4];
40313   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
40314        uint8_t RESERVED_2[4];
40315   __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
40316        uint8_t RESERVED_3[4];
40317   __IO uint32_t SHIFTSTATE;                        /**< Shifter State, offset: 0x40 */
40318        uint8_t RESERVED_4[4];
40319   __IO uint32_t TRGSTAT;                           /**< Trigger Status, offset: 0x48 */
40320   __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable, offset: 0x4C */
40321   __IO uint32_t PINSTAT;                           /**< Pin Status, offset: 0x50 */
40322   __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable, offset: 0x54 */
40323   __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable, offset: 0x58 */
40324   __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable, offset: 0x5C */
40325   __IO uint32_t PINOUTD;                           /**< Pin Output Data, offset: 0x60 */
40326   __IO uint32_t PINOUTE;                           /**< Pin Output Enable, offset: 0x64 */
40327   __O  uint32_t PINOUTDIS;                         /**< Pin Output Disable, offset: 0x68 */
40328   __O  uint32_t PINOUTCLR;                         /**< Pin Output Clear, offset: 0x6C */
40329   __O  uint32_t PINOUTSET;                         /**< Pin Output Set, offset: 0x70 */
40330   __O  uint32_t PINOUTTOG;                         /**< Pin Output Toggle, offset: 0x74 */
40331        uint8_t RESERVED_5[8];
40332   __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N, array offset: 0x80, array step: 0x4 */
40333        uint8_t RESERVED_6[96];
40334   __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N, array offset: 0x100, array step: 0x4 */
40335        uint8_t RESERVED_7[224];
40336   __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N, array offset: 0x200, array step: 0x4 */
40337        uint8_t RESERVED_8[96];
40338   __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped, array offset: 0x280, array step: 0x4 */
40339        uint8_t RESERVED_9[96];
40340   __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped, array offset: 0x300, array step: 0x4 */
40341        uint8_t RESERVED_10[96];
40342   __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped, array offset: 0x380, array step: 0x4 */
40343        uint8_t RESERVED_11[96];
40344   __IO uint32_t TIMCTL[8];                         /**< Timer Control N, array offset: 0x400, array step: 0x4 */
40345        uint8_t RESERVED_12[96];
40346   __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N, array offset: 0x480, array step: 0x4 */
40347        uint8_t RESERVED_13[96];
40348   __IO uint32_t TIMCMP[8];                         /**< Timer Compare N, array offset: 0x500, array step: 0x4 */
40349        uint8_t RESERVED_14[352];
40350   __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */
40351        uint8_t RESERVED_15[96];
40352   __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Halfword Swapped, array offset: 0x700, array step: 0x4 */
40353        uint8_t RESERVED_16[96];
40354   __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped, array offset: 0x780, array step: 0x4 */
40355        uint8_t RESERVED_17[96];
40356   __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped, array offset: 0x800, array step: 0x4 */
40357        uint8_t RESERVED_18[96];
40358   __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped, array offset: 0x880, array step: 0x4 */
40359        uint8_t RESERVED_19[96];
40360   __IO uint32_t SHIFTBUFHBS[8];                    /**< Shifter Buffer N Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */
40361 } FLEXIO_Type;
40362 
40363 /* ----------------------------------------------------------------------------
40364    -- FLEXIO Register Masks
40365    ---------------------------------------------------------------------------- */
40366 
40367 /*!
40368  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
40369  * @{
40370  */
40371 
40372 /*! @name VERID - Version ID */
40373 /*! @{ */
40374 
40375 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
40376 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
40377 /*! FEATURE - Feature Specification Number
40378  *  0b0000000000000000..Standard features implemented.
40379  *  0b0000000000000001..Supports state, logic, and parallel modes.
40380  *  0b0000000000000010..Supports pin control registers.
40381  *  0b0000000000000011..Supports state, logic, and parallel modes, plus pin control registers.
40382  */
40383 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
40384 
40385 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
40386 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
40387 /*! MINOR - Minor Version Number */
40388 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
40389 
40390 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
40391 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
40392 /*! MAJOR - Major Version Number */
40393 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
40394 /*! @} */
40395 
40396 /*! @name PARAM - Parameter */
40397 /*! @{ */
40398 
40399 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
40400 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
40401 /*! SHIFTER - Shifter Number */
40402 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
40403 
40404 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
40405 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
40406 /*! TIMER - Timer Number */
40407 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
40408 
40409 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
40410 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
40411 /*! PIN - Pin Number */
40412 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
40413 
40414 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
40415 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
40416 /*! TRIGGER - Trigger Number */
40417 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
40418 /*! @} */
40419 
40420 /*! @name CTRL - FLEXIO Control */
40421 /*! @{ */
40422 
40423 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
40424 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
40425 /*! FLEXEN - FLEXIO Enable
40426  *  0b0..FLEXIO module is disabled.
40427  *  0b1..FLEXIO module is enabled.
40428  */
40429 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
40430 
40431 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
40432 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
40433 /*! SWRST - Software Reset
40434  *  0b0..Software reset is disabled
40435  *  0b1..Software reset is enabled. All FLEXIO registers except the Control Register are reset.
40436  */
40437 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
40438 
40439 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
40440 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
40441 /*! FASTACC - Fast Access
40442  *  0b0..Configures for normal register accesses to FLEXIO
40443  *  0b1..Configures for fast register accesses to FLEXIO
40444  */
40445 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
40446 
40447 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
40448 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
40449 /*! DBGE - Debug Enable
40450  *  0b0..FLEXIO is disabled in Debug modes.
40451  *  0b1..FLEXIO is enabled in Debug modes.
40452  */
40453 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
40454 
40455 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
40456 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
40457 /*! DOZEN - Doze Enable
40458  *  0b0..FLEXIO enabled in Doze modes.
40459  *  0b1..FLEXIO disabled in Doze modes.
40460  */
40461 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
40462 /*! @} */
40463 
40464 /*! @name PIN - Pin State */
40465 /*! @{ */
40466 
40467 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
40468 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
40469 /*! PDI - Pin Data Input */
40470 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
40471 /*! @} */
40472 
40473 /*! @name SHIFTSTAT - Shifter Status */
40474 /*! @{ */
40475 
40476 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
40477 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
40478 /*! SSF - Shifter Status Flag */
40479 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
40480 /*! @} */
40481 
40482 /*! @name SHIFTERR - Shifter Error */
40483 /*! @{ */
40484 
40485 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
40486 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
40487 /*! SEF - Shifter Error Flags */
40488 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
40489 /*! @} */
40490 
40491 /*! @name TIMSTAT - Timer Status */
40492 /*! @{ */
40493 
40494 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
40495 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
40496 /*! TSF - Timer Status Flags */
40497 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
40498 /*! @} */
40499 
40500 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
40501 /*! @{ */
40502 
40503 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
40504 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
40505 /*! SSIE - Shifter Status Interrupt Enable */
40506 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
40507 /*! @} */
40508 
40509 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
40510 /*! @{ */
40511 
40512 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
40513 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
40514 /*! SEIE - Shifter Error Interrupt Enable */
40515 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
40516 /*! @} */
40517 
40518 /*! @name TIMIEN - Timer Interrupt Enable */
40519 /*! @{ */
40520 
40521 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
40522 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
40523 /*! TEIE - Timer Status Interrupt Enable */
40524 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
40525 /*! @} */
40526 
40527 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
40528 /*! @{ */
40529 
40530 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
40531 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
40532 /*! SSDE - Shifter Status DMA Enable */
40533 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
40534 /*! @} */
40535 
40536 /*! @name TIMERSDEN - Timer Status DMA Enable */
40537 /*! @{ */
40538 
40539 #define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
40540 #define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
40541 /*! TSDE - Timer Status DMA Enable */
40542 #define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
40543 /*! @} */
40544 
40545 /*! @name SHIFTSTATE - Shifter State */
40546 /*! @{ */
40547 
40548 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
40549 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
40550 /*! STATE - Current State Pointer */
40551 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
40552 /*! @} */
40553 
40554 /*! @name TRGSTAT - Trigger Status */
40555 /*! @{ */
40556 
40557 #define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFU)
40558 #define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
40559 /*! ETSF - External Trigger Status Flags */
40560 #define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
40561 /*! @} */
40562 
40563 /*! @name TRIGIEN - External Trigger Interrupt Enable */
40564 /*! @{ */
40565 
40566 #define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFU)
40567 #define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
40568 /*! TRIE - External Trigger Interrupt Enable */
40569 #define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
40570 /*! @} */
40571 
40572 /*! @name PINSTAT - Pin Status */
40573 /*! @{ */
40574 
40575 #define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFFFFFU)
40576 #define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
40577 /*! PSF - Pin Status Flags */
40578 #define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
40579 /*! @} */
40580 
40581 /*! @name PINIEN - Pin Interrupt Enable */
40582 /*! @{ */
40583 
40584 #define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFFFFFU)
40585 #define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
40586 /*! PSIE - Pin Status Interrupt Enable */
40587 #define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
40588 /*! @} */
40589 
40590 /*! @name PINREN - Pin Rising Edge Enable */
40591 /*! @{ */
40592 
40593 #define FLEXIO_PINREN_PRE_MASK                   (0xFFFFFFFFU)
40594 #define FLEXIO_PINREN_PRE_SHIFT                  (0U)
40595 /*! PRE - Pin Rising Edge */
40596 #define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
40597 /*! @} */
40598 
40599 /*! @name PINFEN - Pin Falling Edge Enable */
40600 /*! @{ */
40601 
40602 #define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFFFFFU)
40603 #define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
40604 /*! PFE - Pin Falling Edge */
40605 #define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
40606 /*! @} */
40607 
40608 /*! @name PINOUTD - Pin Output Data */
40609 /*! @{ */
40610 
40611 #define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFFFFFU)
40612 #define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
40613 /*! OUTD - Output Data */
40614 #define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
40615 /*! @} */
40616 
40617 /*! @name PINOUTE - Pin Output Enable */
40618 /*! @{ */
40619 
40620 #define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFFFFFU)
40621 #define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
40622 /*! OUTE - Output Enable */
40623 #define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
40624 /*! @} */
40625 
40626 /*! @name PINOUTDIS - Pin Output Disable */
40627 /*! @{ */
40628 
40629 #define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFFFFFU)
40630 #define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
40631 /*! OUTDIS - Output Disable */
40632 #define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
40633 /*! @} */
40634 
40635 /*! @name PINOUTCLR - Pin Output Clear */
40636 /*! @{ */
40637 
40638 #define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFFFFFU)
40639 #define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
40640 /*! OUTCLR - Output Clear */
40641 #define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
40642 /*! @} */
40643 
40644 /*! @name PINOUTSET - Pin Output Set */
40645 /*! @{ */
40646 
40647 #define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFFFFFU)
40648 #define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
40649 /*! OUTSET - Output Set */
40650 #define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
40651 /*! @} */
40652 
40653 /*! @name PINOUTTOG - Pin Output Toggle */
40654 /*! @{ */
40655 
40656 #define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFFFFFU)
40657 #define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
40658 /*! OUTTOG - Output Toggle */
40659 #define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
40660 /*! @} */
40661 
40662 /*! @name SHIFTCTL - Shifter Control N */
40663 /*! @{ */
40664 
40665 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
40666 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
40667 /*! SMOD - Shifter Mode
40668  *  0b000..Disabled.
40669  *  0b001..Receive mode. Captures the current shifter content into the SHIFTBUF on expiration of the timer.
40670  *  0b010..Transmit mode. Load SHIFTBUF contents into the shifter on expiration of the timer.
40671  *  0b011..Reserved.
40672  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the timer.
40673  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
40674  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
40675  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic lookup table.
40676  */
40677 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
40678 
40679 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
40680 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
40681 /*! PINPOL - Shifter Pin Polarity
40682  *  0b0..Pin is active high
40683  *  0b1..Pin is active low
40684  */
40685 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
40686 
40687 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
40688 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
40689 /*! PINSEL - Shifter Pin Select */
40690 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
40691 
40692 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
40693 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
40694 /*! PINCFG - Shifter Pin Configuration
40695  *  0b00..Shifter pin output disabled
40696  *  0b01..Shifter pin open-drain or bidirectional output enable
40697  *  0b10..Shifter pin bidirectional output data
40698  *  0b11..Shifter pin output
40699  */
40700 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
40701 
40702 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
40703 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
40704 /*! TIMPOL - Timer Polarity
40705  *  0b0..Shift on posedge of shift clock
40706  *  0b1..Shift on negedge of shift clock
40707  */
40708 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
40709 
40710 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
40711 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
40712 /*! TIMSEL - Timer Select */
40713 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
40714 /*! @} */
40715 
40716 /* The count of FLEXIO_SHIFTCTL */
40717 #define FLEXIO_SHIFTCTL_COUNT                    (8U)
40718 
40719 /*! @name SHIFTCFG - Shifter Configuration N */
40720 /*! @{ */
40721 
40722 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
40723 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
40724 /*! SSTART - Shifter Start Bit
40725  *  0b00..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on enable.
40726  *  0b01..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on first shift.
40727  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift. If start bit is not 0, receiver/match store sets error flag.
40728  *  0b11..Transmitter outputs start bit value 1 before loading data on first shift. If start bit is not 1, receiver/match store sets error flag.
40729  */
40730 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
40731 
40732 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
40733 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
40734 /*! SSTOP - Shifter Stop bit
40735  *  0b00..Stop bit disabled for transmitter/receiver/match store
40736  *  0b01..Stop bit disabled for transmitter/receiver/match store. When timer is in stop condition, receiver/match
40737  *        store stores receive data on the configured shift edge.
40738  *  0b10..Transmitter outputs stop bit value 0 on store. If stop bit is not 0, receiver/match store sets error
40739  *        flag. When timer is in stop condition, receiver/match stores also store receive data on the configured shift
40740  *        edge.
40741  *  0b11..Transmitter outputs stop bit value 1 on store. If stop bit is not 1, receiver/match store sets error
40742  *        flag. When timer is in stop condition, receiver/match store also stores receive data on the configured shift
40743  *        edge.
40744  */
40745 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
40746 
40747 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
40748 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
40749 /*! INSRC - Input Source
40750  *  0b0..Pin
40751  *  0b1..Shifter N+1 Output
40752  */
40753 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
40754 
40755 #define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
40756 #define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
40757 /*! LATST - Late Store
40758  *  0b0..Shift register stores the pre-shift register state.
40759  *  0b1..Shift register stores the post-shift register state.
40760  */
40761 #define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
40762 
40763 #define FLEXIO_SHIFTCFG_SSIZE_MASK               (0x1000U)
40764 #define FLEXIO_SHIFTCFG_SSIZE_SHIFT              (12U)
40765 /*! SSIZE - Shifter Size
40766  *  0b0..Shift register is 32-bit.
40767  *  0b1..Shift register is 24-bit.
40768  */
40769 #define FLEXIO_SHIFTCFG_SSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)
40770 
40771 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
40772 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
40773 /*! PWIDTH - Parallel Width */
40774 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
40775 /*! @} */
40776 
40777 /* The count of FLEXIO_SHIFTCFG */
40778 #define FLEXIO_SHIFTCFG_COUNT                    (8U)
40779 
40780 /*! @name SHIFTBUF - Shifter Buffer N */
40781 /*! @{ */
40782 
40783 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
40784 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
40785 /*! SHIFTBUF - Shift Buffer */
40786 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
40787 /*! @} */
40788 
40789 /* The count of FLEXIO_SHIFTBUF */
40790 #define FLEXIO_SHIFTBUF_COUNT                    (8U)
40791 
40792 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped */
40793 /*! @{ */
40794 
40795 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
40796 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
40797 /*! SHIFTBUFBIS - Shift Buffer */
40798 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
40799 /*! @} */
40800 
40801 /* The count of FLEXIO_SHIFTBUFBIS */
40802 #define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
40803 
40804 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped */
40805 /*! @{ */
40806 
40807 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
40808 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
40809 /*! SHIFTBUFBYS - Shift Buffer */
40810 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
40811 /*! @} */
40812 
40813 /* The count of FLEXIO_SHIFTBUFBYS */
40814 #define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
40815 
40816 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped */
40817 /*! @{ */
40818 
40819 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
40820 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
40821 /*! SHIFTBUFBBS - Shift Buffer */
40822 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
40823 /*! @} */
40824 
40825 /* The count of FLEXIO_SHIFTBUFBBS */
40826 #define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
40827 
40828 /*! @name TIMCTL - Timer Control N */
40829 /*! @{ */
40830 
40831 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
40832 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
40833 /*! TIMOD - Timer Mode
40834  *  0b000..Timer disabled.
40835  *  0b001..Dual 8-bit counters baud mode.
40836  *  0b010..Dual 8-bit counters PWM high mode.
40837  *  0b011..Single 16-bit counter mode.
40838  *  0b100..Single 16-bit counter disable mode.
40839  *  0b101..Dual 8-bit counters word mode.
40840  *  0b110..Dual 8-bit counters PWM low mode.
40841  *  0b111..Single 16-bit input capture mode.
40842  */
40843 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
40844 
40845 #define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
40846 #define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
40847 /*! ONETIM - Timer One Time Operation
40848  *  0b0..The timer enable event is generated as normal.
40849  *  0b1..The timer enable event is blocked unless timer status flag is clear.
40850  */
40851 #define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
40852 
40853 #define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
40854 #define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
40855 /*! PININS - Timer Pin Input Select
40856  *  0b0..Timer pin input and output are selected by PINSEL.
40857  *  0b1..Timer pin input is selected by PINSEL+1. Timer pin output remains selected by PINSEL.
40858  */
40859 #define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
40860 
40861 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
40862 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
40863 /*! PINPOL - Timer Pin Polarity
40864  *  0b0..Pin is active high
40865  *  0b1..Pin is active low
40866  */
40867 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
40868 
40869 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
40870 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
40871 /*! PINSEL - Timer Pin Select */
40872 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
40873 
40874 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
40875 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
40876 /*! PINCFG - Timer Pin Configuration
40877  *  0b00..Timer pin output disabled
40878  *  0b01..Timer pin open-drain or bidirectional output enable
40879  *  0b10..Timer pin bidirectional output data
40880  *  0b11..Timer pin output
40881  */
40882 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
40883 
40884 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
40885 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
40886 /*! TRGSRC - Trigger Source
40887  *  0b0..External trigger selected
40888  *  0b1..Internal trigger selected
40889  */
40890 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
40891 
40892 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
40893 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
40894 /*! TRGPOL - Trigger Polarity
40895  *  0b0..Trigger active high
40896  *  0b1..Trigger active low
40897  */
40898 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
40899 
40900 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
40901 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
40902 /*! TRGSEL - Trigger Select */
40903 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
40904 /*! @} */
40905 
40906 /* The count of FLEXIO_TIMCTL */
40907 #define FLEXIO_TIMCTL_COUNT                      (8U)
40908 
40909 /*! @name TIMCFG - Timer Configuration N */
40910 /*! @{ */
40911 
40912 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
40913 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
40914 /*! TSTART - Timer Start Bit
40915  *  0b0..Start bit disabled
40916  *  0b1..Start bit enabled
40917  */
40918 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
40919 
40920 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
40921 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
40922 /*! TSTOP - Timer Stop Bit
40923  *  0b00..Stop bit disabled
40924  *  0b01..Stop bit is enabled on timer compare
40925  *  0b10..Stop bit is enabled on timer disable
40926  *  0b11..Stop bit is enabled on timer compare and timer disable
40927  */
40928 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
40929 
40930 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
40931 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
40932 /*! TIMENA - Timer Enable
40933  *  0b000..Timer always enabled
40934  *  0b001..Timer enabled on Timer N-1 enable
40935  *  0b010..Timer enabled on Trigger high
40936  *  0b011..Timer enabled on Trigger high and Pin high
40937  *  0b100..Timer enabled on Pin rising edge
40938  *  0b101..Timer enabled on Pin rising edge and Trigger high
40939  *  0b110..Timer enabled on Trigger rising edge
40940  *  0b111..Timer enabled on Trigger rising or falling edge
40941  */
40942 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
40943 
40944 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
40945 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
40946 /*! TIMDIS - Timer Disable
40947  *  0b000..Timer never disabled
40948  *  0b001..Timer disabled on Timer N-1 disable
40949  *  0b010..Timer disabled on timer compare (upper 8-bits match and decrement)
40950  *  0b011..Timer disabled on timer compare (upper 8-bits match and decrement) and trigger low
40951  *  0b100..Timer disabled on pin rising or falling edge
40952  *  0b101..Timer disabled on pin rising or falling edge provided trigger is high
40953  *  0b110..Timer disabled on trigger falling edge
40954  *  0b111..Reserved
40955  */
40956 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
40957 
40958 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
40959 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
40960 /*! TIMRST - Timer Reset
40961  *  0b000..Timer never reset
40962  *  0b001..Timer reset on timer output high.
40963  *  0b010..Timer reset on timer pin equal to timer output
40964  *  0b011..Timer reset on timer trigger equal to timer output
40965  *  0b100..Timer reset on timer pin rising edge
40966  *  0b101..Reserved
40967  *  0b110..Timer reset on trigger rising edge
40968  *  0b111..Timer reset on trigger rising or falling edge
40969  */
40970 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
40971 
40972 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
40973 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
40974 /*! TIMDEC - Timer Decrement
40975  *  0b000..Decrement counter on FLEXIO clock. Shift clock equals timer output.
40976  *  0b001..Decrement counter on trigger input (both edges). Shift clock equals timer output.
40977  *  0b010..Decrement counter on pin input (both edges). Shift clock equals pin input.
40978  *  0b011..Decrement counter on trigger input (both edges). Shift clock equals trigger input.
40979  *  0b100..Decrement counter on FLEXIO clock divided by 16. Shift clock equals timer output.
40980  *  0b101..Decrement counter on FLEXIO clock divided by 256. Shift clock equals timer output.
40981  *  0b110..Decrement counter on pin input (rising edge). Shift clock equals pin input.
40982  *  0b111..Decrement counter on trigger input (rising edge). Shift clock equals trigger input.
40983  */
40984 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
40985 
40986 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
40987 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
40988 /*! TIMOUT - Timer Output
40989  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
40990  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
40991  *  0b10..Timer output is logic one when enabled and on timer reset
40992  *  0b11..Timer output is logic zero when enabled and on timer reset
40993  */
40994 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
40995 /*! @} */
40996 
40997 /* The count of FLEXIO_TIMCFG */
40998 #define FLEXIO_TIMCFG_COUNT                      (8U)
40999 
41000 /*! @name TIMCMP - Timer Compare N */
41001 /*! @{ */
41002 
41003 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
41004 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
41005 /*! CMP - Timer Compare Value */
41006 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
41007 /*! @} */
41008 
41009 /* The count of FLEXIO_TIMCMP */
41010 #define FLEXIO_TIMCMP_COUNT                      (8U)
41011 
41012 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped */
41013 /*! @{ */
41014 
41015 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
41016 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
41017 /*! SHIFTBUFNBS - Shift Buffer */
41018 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
41019 /*! @} */
41020 
41021 /* The count of FLEXIO_SHIFTBUFNBS */
41022 #define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
41023 
41024 /*! @name SHIFTBUFHWS - Shifter Buffer N Halfword Swapped */
41025 /*! @{ */
41026 
41027 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
41028 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
41029 /*! SHIFTBUFHWS - Shift Buffer */
41030 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
41031 /*! @} */
41032 
41033 /* The count of FLEXIO_SHIFTBUFHWS */
41034 #define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
41035 
41036 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped */
41037 /*! @{ */
41038 
41039 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
41040 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
41041 /*! SHIFTBUFNIS - Shift Buffer */
41042 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
41043 /*! @} */
41044 
41045 /* The count of FLEXIO_SHIFTBUFNIS */
41046 #define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
41047 
41048 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped */
41049 /*! @{ */
41050 
41051 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
41052 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
41053 /*! SHIFTBUFOES - Shift Buffer */
41054 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
41055 /*! @} */
41056 
41057 /* The count of FLEXIO_SHIFTBUFOES */
41058 #define FLEXIO_SHIFTBUFOES_COUNT                 (8U)
41059 
41060 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped */
41061 /*! @{ */
41062 
41063 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
41064 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
41065 /*! SHIFTBUFEOS - Shift Buffer */
41066 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
41067 /*! @} */
41068 
41069 /* The count of FLEXIO_SHIFTBUFEOS */
41070 #define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)
41071 
41072 /*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped */
41073 /*! @{ */
41074 
41075 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK      (0xFFFFFFFFU)
41076 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT     (0U)
41077 /*! SHIFTBUFHBS - Shift Buffer */
41078 #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
41079 /*! @} */
41080 
41081 /* The count of FLEXIO_SHIFTBUFHBS */
41082 #define FLEXIO_SHIFTBUFHBS_COUNT                 (8U)
41083 
41084 
41085 /*!
41086  * @}
41087  */ /* end of group FLEXIO_Register_Masks */
41088 
41089 
41090 /* FLEXIO - Peripheral instance base addresses */
41091 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
41092   /** Peripheral FLEXIO1 base address */
41093   #define FLEXIO1_BASE                             (0x525C0000u)
41094   /** Peripheral FLEXIO1 base address */
41095   #define FLEXIO1_BASE_NS                          (0x425C0000u)
41096   /** Peripheral FLEXIO1 base pointer */
41097   #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
41098   /** Peripheral FLEXIO1 base pointer */
41099   #define FLEXIO1_NS                               ((FLEXIO_Type *)FLEXIO1_BASE_NS)
41100   /** Peripheral FLEXIO2 base address */
41101   #define FLEXIO2_BASE                             (0x525D0000u)
41102   /** Peripheral FLEXIO2 base address */
41103   #define FLEXIO2_BASE_NS                          (0x425D0000u)
41104   /** Peripheral FLEXIO2 base pointer */
41105   #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
41106   /** Peripheral FLEXIO2 base pointer */
41107   #define FLEXIO2_NS                               ((FLEXIO_Type *)FLEXIO2_BASE_NS)
41108   /** Array initializer of FLEXIO peripheral base addresses */
41109   #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
41110   /** Array initializer of FLEXIO peripheral base pointers */
41111   #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
41112   /** Array initializer of FLEXIO peripheral base addresses */
41113   #define FLEXIO_BASE_ADDRS_NS                     { 0u, FLEXIO1_BASE_NS, FLEXIO2_BASE_NS }
41114   /** Array initializer of FLEXIO peripheral base pointers */
41115   #define FLEXIO_BASE_PTRS_NS                      { (FLEXIO_Type *)0u, FLEXIO1_NS, FLEXIO2_NS }
41116 #else
41117   /** Peripheral FLEXIO1 base address */
41118   #define FLEXIO1_BASE                             (0x425C0000u)
41119   /** Peripheral FLEXIO1 base pointer */
41120   #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
41121   /** Peripheral FLEXIO2 base address */
41122   #define FLEXIO2_BASE                             (0x425D0000u)
41123   /** Peripheral FLEXIO2 base pointer */
41124   #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
41125   /** Array initializer of FLEXIO peripheral base addresses */
41126   #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
41127   /** Array initializer of FLEXIO peripheral base pointers */
41128   #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
41129 #endif
41130 /** Interrupt vectors for the FLEXIO peripheral type */
41131 #define FLEXIO_IRQS                              { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
41132 
41133 /*!
41134  * @}
41135  */ /* end of group FLEXIO_Peripheral_Access_Layer */
41136 
41137 
41138 /* ----------------------------------------------------------------------------
41139    -- FLEXSPI Peripheral Access Layer
41140    ---------------------------------------------------------------------------- */
41141 
41142 /*!
41143  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
41144  * @{
41145  */
41146 
41147 /** FLEXSPI - Register Layout Typedef */
41148 typedef struct {
41149   __IO uint32_t MCR0;                              /**< Module Control 0, offset: 0x0 */
41150   __IO uint32_t MCR1;                              /**< Module Control 1, offset: 0x4 */
41151   __IO uint32_t MCR2;                              /**< Module Control 2, offset: 0x8 */
41152   __IO uint32_t AHBCR;                             /**< AHB Bus Control, offset: 0xC */
41153   __IO uint32_t INTEN;                             /**< Interrupt Enable, offset: 0x10 */
41154   __IO uint32_t INTR;                              /**< Interrupt, offset: 0x14 */
41155   __IO uint32_t LUTKEY;                            /**< LUT Key, offset: 0x18 */
41156   __IO uint32_t LUTCR;                             /**< LUT Control, offset: 0x1C */
41157   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */
41158        uint8_t RESERVED_0[32];
41159   __IO uint32_t FLSHCR0[4];                        /**< Flash Control 0, array offset: 0x60, array step: 0x4 */
41160   __IO uint32_t FLSHCR1[4];                        /**< Flash Control 1, array offset: 0x70, array step: 0x4 */
41161   __IO uint32_t FLSHCR2[4];                        /**< Flash Control 2, array offset: 0x80, array step: 0x4 */
41162        uint8_t RESERVED_1[4];
41163   __IO uint32_t FLSHCR4;                           /**< Flash Control 4, offset: 0x94 */
41164        uint8_t RESERVED_2[8];
41165   __IO uint32_t IPCR0;                             /**< IP Control 0, offset: 0xA0 */
41166   __IO uint32_t IPCR1;                             /**< IP Control 1, offset: 0xA4 */
41167        uint8_t RESERVED_3[8];
41168   __O  uint32_t IPCMD;                             /**< IP Command, offset: 0xB0 */
41169        uint8_t RESERVED_4[4];
41170   __IO uint32_t IPRXFCR;                           /**< IP Receive FIFO Control, offset: 0xB8 */
41171   __IO uint32_t IPTXFCR;                           /**< IP Transmit FIFO Control, offset: 0xBC */
41172   __IO uint32_t DLLCR[2];                          /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */
41173        uint8_t RESERVED_5[24];
41174   __I  uint32_t STS0;                              /**< Status 0, offset: 0xE0 */
41175   __I  uint32_t STS1;                              /**< Status 1, offset: 0xE4 */
41176   __I  uint32_t STS2;                              /**< Status 2, offset: 0xE8 */
41177   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status, offset: 0xEC */
41178   __I  uint32_t IPRXFSTS;                          /**< IP Receive FIFO Status, offset: 0xF0 */
41179   __I  uint32_t IPTXFSTS;                          /**< IP Transmit FIFO Status, offset: 0xF4 */
41180        uint8_t RESERVED_6[8];
41181   __I  uint32_t RFDR[32];                          /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */
41182   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */
41183   __IO uint32_t LUT[128];                          /**< Lookup Table 0..Lookup Table 127, array offset: 0x200, array step: 0x4 */
41184        uint8_t RESERVED_7[64];
41185   __IO uint32_t AHBBUFREGIONSTART0;                /**< Receive Buffer Start Address of Region 0, offset: 0x440 */
41186   __IO uint32_t AHBBUFREGIONEND0;                  /**< Receive Buffer Region 0 End Address, offset: 0x444 */
41187   __IO uint32_t AHBBUFREGIONSTART1;                /**< Receive Buffer Start Address of Region 1, offset: 0x448 */
41188   __IO uint32_t AHBBUFREGIONEND1;                  /**< Receive Buffer Region 1 End Address, offset: 0x44C */
41189   __IO uint32_t AHBBUFREGIONSTART2;                /**< Receive Buffer Start Address of Region 2, offset: 0x450 */
41190   __IO uint32_t AHBBUFREGIONEND2;                  /**< Receive Buffer Region 2 End Address, offset: 0x454 */
41191   __IO uint32_t AHBBUFREGIONSTART3;                /**< Receive Buffer Start Address of Region 3, offset: 0x458 */
41192   __IO uint32_t AHBBUFREGIONEND3;                  /**< Receive Buffer Region 3 End Address, offset: 0x45C */
41193 } FLEXSPI_Type;
41194 
41195 /* ----------------------------------------------------------------------------
41196    -- FLEXSPI Register Masks
41197    ---------------------------------------------------------------------------- */
41198 
41199 /*!
41200  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
41201  * @{
41202  */
41203 
41204 /*! @name MCR0 - Module Control 0 */
41205 /*! @{ */
41206 
41207 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
41208 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
41209 /*! SWRESET - Software Reset
41210  *  0b0..No impact
41211  *  0b1..Software reset
41212  */
41213 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
41214 
41215 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
41216 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
41217 /*! MDIS - Module Disable
41218  *  0b0..No impact
41219  *  0b1..Module disable
41220  */
41221 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
41222 
41223 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
41224 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
41225 /*! RXCLKSRC - Sample Clock Source for Flash Reading
41226  *  0b00..Dummy Read strobe that FlexSPI generates, looped back internally
41227  *  0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad
41228  *  0b10..Reserved
41229  *  0b11..Flash-memory-provided read strobe and input from DQS pad
41230  */
41231 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
41232 
41233 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
41234 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
41235 /*! ARDFEN - AHB Read Access to IP Receive FIFO Enable
41236  *  0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error.
41237  *  0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory
41238  *       space returns data zero and causes no bus error.
41239  */
41240 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
41241 
41242 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
41243 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
41244 /*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable
41245  *  0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error.
41246  *  0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO
41247  *       memory space is ignored and causes no bus error.
41248  */
41249 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
41250 
41251 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
41252 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
41253 /*! SERCLKDIV - Serial Root Clock Divider
41254  *  0b000..Divided by 1
41255  *  0b001..Divided by 2
41256  *  0b010..Divided by 3
41257  *  0b011..Divided by 4
41258  *  0b100..Divided by 5
41259  *  0b101..Divided by 6
41260  *  0b110..Divided by 7
41261  *  0b111..Divided by 8
41262  */
41263 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
41264 
41265 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
41266 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
41267 /*! HSEN - Half Speed Serial Flash Memory Access Enable
41268  *  0b0..Disable
41269  *  0b1..Enable
41270  */
41271 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
41272 
41273 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
41274 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
41275 /*! DOZEEN - Doze Mode Enable
41276  *  0b0..Disable
41277  *  0b1..Enable
41278  */
41279 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
41280 
41281 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
41282 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
41283 /*! COMBINATIONEN - Combination Mode Enable
41284  *  0b0..Disable
41285  *  0b1..Enable
41286  */
41287 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
41288 
41289 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
41290 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
41291 /*! SCKFREERUNEN - SCLK Free-running Enable
41292  *  0b0..Disable
41293  *  0b1..Enable
41294  */
41295 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
41296 
41297 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
41298 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
41299 /*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */
41300 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
41301 
41302 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
41303 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
41304 /*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */
41305 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
41306 /*! @} */
41307 
41308 /*! @name MCR1 - Module Control 1 */
41309 /*! @{ */
41310 
41311 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
41312 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
41313 /*! AHBBUSWAIT - AHB Bus Wait */
41314 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
41315 
41316 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
41317 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
41318 /*! SEQWAIT - Command Sequence Wait */
41319 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
41320 /*! @} */
41321 
41322 /*! @name MCR2 - Module Control 2 */
41323 /*! @{ */
41324 
41325 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
41326 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
41327 /*! CLRAHBBUFOPT - Clear AHB Buffer
41328  *  0b0..Not cleared automatically
41329  *  0b1..Cleared automatically
41330  */
41331 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
41332 
41333 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
41334 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
41335 /*! SAMEDEVICEEN - Same Device Enable
41336  *  0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1,
41337  *       A2, B1, B2 separately. In Parallel mode, FLSHA1CRx register setting is applied to Flash A1 and B1, FLSHA2CRx
41338  *       register setting is applied to Flash A2 and B2. FLSHB1CRx and FLSHB2CRx register settings are ignored.
41339  *  0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx,
41340  *       FLSHB1CRx, and FLSHB2CRx settings are ignored.
41341  */
41342 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
41343 
41344 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
41345 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
41346 /*! SCKBDIFFOPT - SCLK Port B Differential Output
41347  *  0b1..Use B_SCLK pad as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash memory access is not available.
41348  *  0b0..Use B_SCLK pad as port B SCLK clock output. Port B flash memory access is available.
41349  */
41350 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
41351 
41352 #define FLEXSPI_MCR2_RXCLKSRC_B_MASK             (0x600000U)
41353 #define FLEXSPI_MCR2_RXCLKSRC_B_SHIFT            (21U)
41354 /*! RXCLKSRC_B - Port B Receiver Clock Source
41355  *  0b00..Dummy read strobe that FlexSPI generates, looped back internally.
41356  *  0b01..Dummy read strobe that FlexSPI generates, looped back from DQS pad.
41357  *  0b10..SCLK output clock and looped back from SCLK padReserved
41358  *  0b11..Flash-memory-provided read strobe and input from DQS pad
41359  */
41360 #define FLEXSPI_MCR2_RXCLKSRC_B(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXCLKSRC_B_SHIFT)) & FLEXSPI_MCR2_RXCLKSRC_B_MASK)
41361 
41362 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK        (0x800000U)
41363 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT       (23U)
41364 /*! RX_CLK_SRC_DIFF - Sample Clock Source Different
41365  *  0b0..Use MCR0[RXCLKSRC] for Port A and Port B. MCR2[RXCLKSRC_B] is ignored and MCR0[RXCLKSRC] selects the
41366  *       Sample Clock source for Flash Reading of both ports A and B.
41367  *  0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. MCR0[RXCLKSRC] selects the Sample Clock
41368  *       source for Flash Reading of port A (A_SCLK) and MCR2[RXCLKSRC_B] selects the Sample Clock source for Flash
41369  *       Reading of port B (B_SCLK).
41370  */
41371 #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK)
41372 
41373 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
41374 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
41375 /*! RESUMEWAIT - Resume Wait Duration */
41376 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
41377 /*! @} */
41378 
41379 /*! @name AHBCR - AHB Bus Control */
41380 /*! @{ */
41381 
41382 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
41383 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
41384 /*! APAREN - AHB Parallel Mode Enable
41385  *  0b0..Flash is accessed in Individual mode.
41386  *  0b1..Flash is accessed in Parallel mode.
41387  */
41388 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
41389 
41390 #define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
41391 #define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
41392 /*! CLRAHBTXBUF - Clear AHB Transmit Buffer
41393  *  0b0..No impact.
41394  *  0b1..Enable clear operation.
41395  */
41396 #define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
41397 
41398 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
41399 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
41400 /*! CACHABLEEN - Cacheable Read Access Enable
41401  *  0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer.
41402  *  0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer.
41403  */
41404 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
41405 
41406 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
41407 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
41408 /*! BUFFERABLEEN - Bufferable Write Access Enable
41409  *  0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after
41410  *       transmitting all data and finishing command.
41411  *  0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the
41412  *       AHB command. FlexSPI does not wait for the AHB command to finish.
41413  */
41414 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
41415 
41416 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
41417 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
41418 /*! PREFETCHEN - AHB Read Prefetch Enable
41419  *  0b0..Disable
41420  *  0b1..Enable
41421  */
41422 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
41423 
41424 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
41425 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
41426 /*! READADDROPT - AHB Read Address Option
41427  *  0b0..AHB read burst start address alignment is limited when flash memory is accessed in parallel mode or flash is word-addressable.
41428  *  0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment.
41429  */
41430 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
41431 
41432 #define FLEXSPI_AHBCR_RESUMEDISABLE_MASK         (0x80U)
41433 #define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT        (7U)
41434 /*! RESUMEDISABLE - AHB Read Resume Disable
41435  *  0b0..Suspended AHB read prefetch resumes when AHB is IDLE.
41436  *  0b1..Suspended AHB read prefetch does not resume once aborted.
41437  */
41438 #define FLEXSPI_AHBCR_RESUMEDISABLE(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK)
41439 
41440 #define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
41441 #define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
41442 /*! READSZALIGN - AHB Read Size Alignment
41443  *  0b0..Register settings such as PREFETCH_EN and OTFAD_EN determine AHB read size.
41444  *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
41445  */
41446 #define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
41447 
41448 #define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
41449 #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
41450 /*! ALIGNMENT - AHB Boundary Alignment
41451  *  0b00..No limit
41452  *  0b01..1 KB
41453  *  0b10..512 bytes
41454  *  0b11..256 bytes
41455  */
41456 #define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
41457 
41458 #define FLEXSPI_AHBCR_AFLASHBASE_MASK            (0xFC000000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
41459 #define FLEXSPI_AHBCR_AFLASHBASE_SHIFT           (26U)
41460 /*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */
41461 #define FLEXSPI_AHBCR_AFLASHBASE(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
41462 /*! @} */
41463 
41464 /*! @name INTEN - Interrupt Enable */
41465 /*! @{ */
41466 
41467 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
41468 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
41469 /*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable
41470  *  0b0..Disable interrupt or no impact
41471  *  0b1..Enable interrupt
41472  */
41473 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
41474 
41475 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
41476 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
41477 /*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable
41478  *  0b0..Disable interrupt or no impact
41479  *  0b1..Enable interrupt
41480  */
41481 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
41482 
41483 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
41484 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
41485 /*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable.
41486  *  0b0..Disable interrupt or no impact
41487  *  0b1..Enable interrupt
41488  */
41489 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
41490 
41491 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
41492 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
41493 /*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable
41494  *  0b0..Disable interrupt or no impact
41495  *  0b1..Enable interrupt
41496  */
41497 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
41498 
41499 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
41500 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
41501 /*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable
41502  *  0b0..Disable interrupt or no impact
41503  *  0b1..Enable interrupt
41504  */
41505 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
41506 
41507 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
41508 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
41509 /*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable
41510  *  0b0..Disable interrupt or no impact
41511  *  0b1..Enable interrupt
41512  */
41513 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
41514 
41515 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
41516 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
41517 /*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable
41518  *  0b0..Disable interrupt or no impact
41519  *  0b1..Enable interrupt
41520  */
41521 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
41522 
41523 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
41524 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
41525 /*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable
41526  *  0b0..Disable interrupt or no impact
41527  *  0b1..Enable interrupt
41528  */
41529 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
41530 
41531 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
41532 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
41533 /*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable
41534  *  0b0..Disable interrupt or no impact
41535  *  0b1..Enable interrupt
41536  */
41537 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
41538 
41539 #define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
41540 #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
41541 /*! AHBBUSERROREN - AHB Bus Error Interrupt Enable
41542  *  0b0..Disable interrupt or no impact
41543  *  0b1..Enable interrupt
41544  */
41545 #define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
41546 
41547 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
41548 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
41549 /*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable
41550  *  0b0..Disable interrupt or no impact
41551  *  0b1..Enable interrupt
41552  */
41553 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
41554 
41555 #define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
41556 #define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
41557 /*! KEYDONEEN - OTFAD Key Blob Processing Done Interrupt Enable
41558  *  0b0..Disable interrupt or no impact
41559  *  0b1..Enable interrupt
41560  */
41561 #define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
41562 
41563 #define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
41564 #define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
41565 /*! KEYERROREN - OTFAD Key Blob Processing Error Interrupt Enable
41566  *  0b0..Disable interrupt or no impact
41567  *  0b1..Enable interrupt
41568  */
41569 #define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
41570 /*! @} */
41571 
41572 /*! @name INTR - Interrupt */
41573 /*! @{ */
41574 
41575 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
41576 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
41577 /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished
41578  *  0b0..Interrupt condition has not occurred
41579  *  0b1..Interrupt condition has occurred
41580  *  0b0..No effect
41581  *  0b1..Clear the flag
41582  */
41583 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
41584 
41585 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
41586 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
41587 /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout
41588  *  0b0..Interrupt condition has not occurred
41589  *  0b1..Interrupt condition has occurred
41590  *  0b0..No effect
41591  *  0b1..Clear the flag
41592  */
41593 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
41594 
41595 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
41596 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
41597 /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout
41598  *  0b0..Interrupt condition has not occurred
41599  *  0b1..Interrupt condition has occurred
41600  *  0b0..No effect
41601  *  0b1..Clear the flag
41602  */
41603 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
41604 
41605 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
41606 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
41607 /*! IPCMDERR - IP-Triggered Command Sequences Error
41608  *  0b0..Interrupt condition has not occurred
41609  *  0b1..Interrupt condition has occurred
41610  *  0b0..No effect
41611  *  0b1..Clear the flag
41612  */
41613 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
41614 
41615 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
41616 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
41617 /*! AHBCMDERR - AHB-Triggered Command Sequences Error
41618  *  0b0..Interrupt condition has not occurred
41619  *  0b1..Interrupt condition has occurred
41620  *  0b0..No effect
41621  *  0b1..Clear the flag
41622  */
41623 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
41624 
41625 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
41626 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
41627 /*! IPRXWA - IP Receive FIFO Watermark Available
41628  *  0b0..Interrupt condition has not occurred
41629  *  0b1..Interrupt condition has occurred
41630  *  0b0..No effect
41631  *  0b1..Clear the flag
41632  */
41633 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
41634 
41635 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
41636 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
41637 /*! IPTXWE - IP Transmit FIFO Watermark Empty
41638  *  0b0..Interrupt condition has not occurred
41639  *  0b1..Interrupt condition has occurred
41640  *  0b0..No effect
41641  *  0b1..Clear the flag
41642  */
41643 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
41644 
41645 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
41646 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
41647 /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO
41648  *  0b0..Interrupt condition has not occurred
41649  *  0b1..Interrupt condition has occurred
41650  *  0b0..No effect
41651  *  0b1..Clear the flag
41652  */
41653 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
41654 
41655 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
41656 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
41657 /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO
41658  *  0b0..Interrupt condition has not occurred
41659  *  0b1..Interrupt condition has occurred
41660  *  0b0..No effect
41661  *  0b1..Clear the flag
41662  */
41663 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
41664 
41665 #define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
41666 #define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
41667 /*! AHBBUSERROR - AHB Bus Error
41668  *  0b0..Interrupt condition has not occurred
41669  *  0b1..Interrupt condition has occurred
41670  *  0b0..No effect
41671  *  0b1..Clear the flag
41672  */
41673 #define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
41674 
41675 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
41676 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
41677 /*! SEQTIMEOUT - Sequence Execution Timeout
41678  *  0b0..Interrupt condition has not occurred
41679  *  0b1..Interrupt condition has occurred
41680  *  0b0..No effect
41681  *  0b1..Clear the flag
41682  */
41683 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
41684 
41685 #define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
41686 #define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
41687 /*! KEYDONE - OTFAD key blob processing done interrupt. */
41688 #define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
41689 
41690 #define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
41691 #define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
41692 /*! KEYERROR - OTFAD Key Blob Processing Error
41693  *  0b0..Interrupt condition has not occurred
41694  *  0b1..Interrupt condition has occurred
41695  *  0b0..No effect
41696  *  0b1..Clear the flag
41697  */
41698 #define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
41699 /*! @} */
41700 
41701 /*! @name LUTKEY - LUT Key */
41702 /*! @{ */
41703 
41704 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
41705 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
41706 /*! KEY - LUT Key */
41707 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
41708 /*! @} */
41709 
41710 /*! @name LUTCR - LUT Control */
41711 /*! @{ */
41712 
41713 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
41714 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
41715 /*! LOCK - Lock LUT
41716  *  0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1)
41717  *  0b1..LUT is locked and cannot be written
41718  */
41719 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
41720 
41721 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
41722 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
41723 /*! UNLOCK - Unlock LUT
41724  *  0b0..LUT is locked (LUTCR[LOCK] must be 1)
41725  *  0b1..LUT is unlocked and can be written
41726  */
41727 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
41728 /*! @} */
41729 
41730 /*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */
41731 /*! @{ */
41732 
41733 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x3FFU)
41734 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
41735 /*! BUFSZ - AHB Receive Buffer Size */
41736 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
41737 
41738 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
41739 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
41740 /*! MSTRID - AHB Controller ID */
41741 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
41742 
41743 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
41744 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
41745 /*! PRIORITY - AHB Controller Read Priority */
41746 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
41747 
41748 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK        (0x40000000U)
41749 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT       (30U)
41750 /*! REGIONEN - AHB Receive Buffer Address Region Enable
41751  *  0b0..Disabled. The buffer hit is based on the value of MSTRID only.
41752  *  0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn.
41753  */
41754 #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
41755 
41756 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
41757 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
41758 /*! PREFETCHEN - AHB Read Prefetch Enable
41759  *  0b0..Disabled
41760  *  0b1..Enabled when is enabled.
41761  */
41762 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
41763 /*! @} */
41764 
41765 /* The count of FLEXSPI_AHBRXBUFCR0 */
41766 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
41767 
41768 /*! @name FLSHCR0 - Flash Control 0 */
41769 /*! @{ */
41770 
41771 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
41772 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
41773 /*! FLSHSZ - Flash Size in KB */
41774 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
41775 
41776 #define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK           (0x20000000U)
41777 #define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT          (29U)
41778 /*! ADDRSHIFT - AHB Address Shift Function control
41779  *  0b0..Disabled
41780  *  0b1..Enabled
41781  */
41782 #define FLEXSPI_FLSHCR0_ADDRSHIFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK)
41783 /*! @} */
41784 
41785 /* The count of FLEXSPI_FLSHCR0 */
41786 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
41787 
41788 /*! @name FLSHCR1 - Flash Control 1 */
41789 /*! @{ */
41790 
41791 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
41792 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
41793 /*! TCSS - Serial Flash CS Setup Time */
41794 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
41795 
41796 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
41797 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
41798 /*! TCSH - Serial Flash CS Hold Time */
41799 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
41800 
41801 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
41802 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
41803 /*! WA - Word-Addressable
41804  *  0b0..Byte-addressable
41805  *  0b1..Word-addressable
41806  */
41807 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
41808 
41809 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
41810 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
41811 /*! CAS - Column Address Size */
41812 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
41813 
41814 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
41815 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
41816 /*! CSINTERVALUNIT - Chip Select Interval Unit
41817  *  0b0..1 serial clock cycle
41818  *  0b1..256 serial clock cycles
41819  */
41820 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
41821 
41822 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
41823 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
41824 /*! CSINTERVAL - Chip Select Interval */
41825 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
41826 /*! @} */
41827 
41828 /* The count of FLEXSPI_FLSHCR1 */
41829 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
41830 
41831 /*! @name FLSHCR2 - Flash Control 2 */
41832 /*! @{ */
41833 
41834 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0x1FU)
41835 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
41836 /*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */
41837 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
41838 
41839 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
41840 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
41841 /*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */
41842 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
41843 
41844 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0x1F00U)
41845 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
41846 /*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */
41847 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
41848 
41849 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
41850 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
41851 /*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */
41852 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
41853 
41854 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
41855 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
41856 /*! AWRWAIT - AHB Write Wait */
41857 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
41858 
41859 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
41860 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
41861 /*! AWRWAITUNIT - AWRWAIT Unit
41862  *  0b000..2
41863  *  0b001..8
41864  *  0b010..32
41865  *  0b011..128
41866  *  0b100..512
41867  *  0b101..2048
41868  *  0b110..8192
41869  *  0b111..32768
41870  */
41871 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
41872 
41873 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
41874 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
41875 /*! CLRINSTRPTR - Clear Instruction Pointer */
41876 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
41877 /*! @} */
41878 
41879 /* The count of FLEXSPI_FLSHCR2 */
41880 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
41881 
41882 /*! @name FLSHCR4 - Flash Control 4 */
41883 /*! @{ */
41884 
41885 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
41886 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
41887 /*! WMOPT1 - Write Mask Option 1
41888  *  0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in
41889  *       individual mode, AHB or IP write burst start address alignment is not limited.
41890  *  0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in
41891  *       individual mode, AHB or IP write burst start address alignment is limited.
41892  */
41893 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
41894 
41895 #define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
41896 #define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
41897 /*! WMOPT2 - Write Mask Option 2
41898  *  0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in
41899  *       individual mode, AHB or IP write burst length is not limited.
41900  *  0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in
41901  *       individual mode, AHB or IP write burst length is limited. The minimum write burst length should be 4.
41902  */
41903 #define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
41904 
41905 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
41906 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
41907 /*! WMENA - Write Mask Enable for Port A
41908  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
41909  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
41910  */
41911 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
41912 
41913 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
41914 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
41915 /*! WMENB - Write Mask Enable for Port B
41916  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
41917  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
41918  */
41919 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
41920 /*! @} */
41921 
41922 /*! @name IPCR0 - IP Control 0 */
41923 /*! @{ */
41924 
41925 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
41926 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
41927 /*! SFAR - Serial Flash Address */
41928 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
41929 /*! @} */
41930 
41931 /*! @name IPCR1 - IP Control 1 */
41932 /*! @{ */
41933 
41934 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
41935 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
41936 /*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */
41937 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
41938 
41939 #define FLEXSPI_IPCR1_ISEQID_MASK                (0x1F0000U)
41940 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
41941 /*! ISEQID - Sequence Index in LUT for IP command. */
41942 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
41943 
41944 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
41945 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
41946 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
41947 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
41948 
41949 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
41950 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
41951 /*! IPAREN - Parallel Mode Enable for IP Commands
41952  *  0b0..Disabled. Flash memory is accessed in Individual mode.
41953  *  0b1..Enabled. Flash memory is accessed in Parallel mode.
41954  */
41955 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
41956 /*! @} */
41957 
41958 /*! @name IPCMD - IP Command */
41959 /*! @{ */
41960 
41961 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
41962 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
41963 /*! TRG - Command Trigger
41964  *  0b0..No action
41965  *  0b1..Start the IP command that the IPCR0 and IPCR1 registers define.
41966  */
41967 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
41968 /*! @} */
41969 
41970 /*! @name IPRXFCR - IP Receive FIFO Control */
41971 /*! @{ */
41972 
41973 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
41974 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
41975 /*! CLRIPRXF - Clear IP Receive FIFO
41976  *  0b0..No function
41977  *  0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO.
41978  */
41979 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
41980 
41981 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
41982 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
41983 /*! RXDMAEN - IP Receive FIFO Reading by DMA Enable
41984  *  0b0..Disabled. The processor reads the FIFO.
41985  *  0b1..Enabled. DMA reads the FIFO.
41986  */
41987 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
41988 
41989 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x7CU)
41990 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
41991 /*! RXWMRK - IP Receive FIFO Watermark Level */
41992 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
41993 /*! @} */
41994 
41995 /*! @name IPTXFCR - IP Transmit FIFO Control */
41996 /*! @{ */
41997 
41998 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
41999 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
42000 /*! CLRIPTXF - Clear IP Transmit FIFO
42001  *  0b0..No function
42002  *  0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO.
42003  */
42004 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
42005 
42006 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
42007 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
42008 /*! TXDMAEN - Transmit FIFO DMA Enable
42009  *  0b0..Processor
42010  *  0b1..DMA
42011  */
42012 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
42013 
42014 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
42015 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
42016 /*! TXWMRK - Transmit Watermark Level */
42017 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
42018 /*! @} */
42019 
42020 /*! @name DLLCR - DLL Control 0 */
42021 /*! @{ */
42022 
42023 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
42024 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
42025 /*! DLLEN - DLL Calibration Enable
42026  *  0b0..Disable
42027  *  0b1..Enable
42028  */
42029 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
42030 
42031 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
42032 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
42033 /*! DLLRESET - DLL reset
42034  *  0b0..No function
42035  *  0b1..Force DLL reset.
42036  */
42037 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
42038 
42039 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
42040 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
42041 /*! SLVDLYTARGET - Target Delay Line */
42042 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
42043 
42044 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
42045 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
42046 /*! OVRDEN - Target Clock Delay Line Override Value Enable
42047  *  0b0..Disable
42048  *  0b1..Enable
42049  */
42050 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
42051 
42052 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
42053 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
42054 /*! OVRDVAL - Target Clock Delay Line Override Value */
42055 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
42056 
42057 #define FLEXSPI_DLLCR_REFPHASEGAP_MASK           (0x18000U)
42058 #define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT          (15U)
42059 /*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */
42060 #define FLEXSPI_DLLCR_REFPHASEGAP(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK)
42061 /*! @} */
42062 
42063 /* The count of FLEXSPI_DLLCR */
42064 #define FLEXSPI_DLLCR_COUNT                      (2U)
42065 
42066 /*! @name STS0 - Status 0 */
42067 /*! @{ */
42068 
42069 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
42070 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
42071 /*! SEQIDLE - SEQ_CTL State Machine Idle
42072  *  0b0..Not idle
42073  *  0b1..Idle
42074  */
42075 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
42076 
42077 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
42078 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
42079 /*! ARBIDLE - ARB_CTL State Machine Idle
42080  *  0b0..Not idle
42081  *  0b1..Idle
42082  */
42083 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
42084 
42085 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
42086 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
42087 /*! ARBCMDSRC - ARB Command Source
42088  *  0b00..Trigger source is AHB read command.
42089  *  0b01..Trigger source is AHB write command.
42090  *  0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]).
42091  *  0b11..Trigger source is a suspended command that has resumed.
42092  */
42093 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
42094 /*! @} */
42095 
42096 /*! @name STS1 - Status 1 */
42097 /*! @{ */
42098 
42099 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0x1FU)
42100 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
42101 /*! AHBCMDERRID - AHB Command Error ID */
42102 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
42103 
42104 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
42105 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
42106 /*! AHBCMDERRCODE - AHB Command Error Code
42107  *  0b0000..No error
42108  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence
42109  *  0b0011..Unknown instruction opcode in the sequence
42110  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
42111  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
42112  *  0b1110..Sequence execution timeout
42113  */
42114 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
42115 
42116 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0x1F0000U)
42117 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
42118 /*! IPCMDERRID - IP Command Error ID */
42119 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
42120 
42121 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
42122 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
42123 /*! IPCMDERRCODE - IP Command Error Code
42124  *  0b0000..No error
42125  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence
42126  *  0b0011..Unknown instruction opcode in the sequence
42127  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
42128  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
42129  *  0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2)
42130  *  0b1110..Sequence execution timeout
42131  *  0b1111..Flash boundary crossed
42132  */
42133 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
42134 /*! @} */
42135 
42136 /*! @name STS2 - Status 2 */
42137 /*! @{ */
42138 
42139 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
42140 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
42141 /*! ASLVLOCK - Flash A Sample Target Delay Line Locked
42142  *  0b0..Not locked
42143  *  0b1..Locked
42144  */
42145 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
42146 
42147 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
42148 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
42149 /*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked
42150  *  0b0..Not locked
42151  *  0b1..Locked
42152  */
42153 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
42154 
42155 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
42156 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
42157 /*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */
42158 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
42159 
42160 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
42161 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
42162 /*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */
42163 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
42164 
42165 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
42166 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
42167 /*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked
42168  *  0b0..Not locked
42169  *  0b1..Locked
42170  */
42171 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
42172 
42173 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
42174 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
42175 /*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked
42176  *  0b0..Not locked
42177  *  0b1..Locked
42178  */
42179 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
42180 
42181 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
42182 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
42183 /*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */
42184 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
42185 
42186 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
42187 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
42188 /*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */
42189 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
42190 /*! @} */
42191 
42192 /*! @name AHBSPNDSTS - AHB Suspend Status */
42193 /*! @{ */
42194 
42195 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
42196 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
42197 /*! ACTIVE - Active AHB Read Prefetch Suspended
42198  *  0b0..No suspended AHB read prefetch command.
42199  *  0b1..An AHB read prefetch command sequence has been suspended.
42200  */
42201 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
42202 
42203 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
42204 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
42205 /*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */
42206 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
42207 
42208 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
42209 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
42210 /*! DATLFT - Data Left */
42211 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
42212 /*! @} */
42213 
42214 /*! @name IPRXFSTS - IP Receive FIFO Status */
42215 /*! @{ */
42216 
42217 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
42218 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
42219 /*! FILL - Fill Level of IP Receive FIFO */
42220 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
42221 
42222 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
42223 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
42224 /*! RDCNTR - Read Data Counter */
42225 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
42226 /*! @} */
42227 
42228 /*! @name IPTXFSTS - IP Transmit FIFO Status */
42229 /*! @{ */
42230 
42231 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
42232 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
42233 /*! FILL - Fill Level of IP Transmit FIFO */
42234 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
42235 
42236 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
42237 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
42238 /*! WRCNTR - Write Data Counter */
42239 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
42240 /*! @} */
42241 
42242 /*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */
42243 /*! @{ */
42244 
42245 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
42246 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
42247 /*! RXDATA - Receive Data */
42248 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
42249 /*! @} */
42250 
42251 /* The count of FLEXSPI_RFDR */
42252 #define FLEXSPI_RFDR_COUNT                       (32U)
42253 
42254 /*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */
42255 /*! @{ */
42256 
42257 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
42258 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
42259 /*! TXDATA - Transmit Data */
42260 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
42261 /*! @} */
42262 
42263 /* The count of FLEXSPI_TFDR */
42264 #define FLEXSPI_TFDR_COUNT                       (32U)
42265 
42266 /*! @name LUT - Lookup Table 0..Lookup Table 127 */
42267 /*! @{ */
42268 
42269 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
42270 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
42271 /*! OPERAND0 - OPERAND0 */
42272 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
42273 
42274 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
42275 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
42276 /*! NUM_PADS0 - NUM_PADS0 */
42277 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
42278 
42279 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
42280 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
42281 /*! OPCODE0 - OPCODE */
42282 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
42283 
42284 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
42285 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
42286 /*! OPERAND1 - OPERAND1 */
42287 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
42288 
42289 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
42290 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
42291 /*! NUM_PADS1 - NUM_PADS1 */
42292 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
42293 
42294 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
42295 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
42296 /*! OPCODE1 - OPCODE1 */
42297 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
42298 /*! @} */
42299 
42300 /* The count of FLEXSPI_LUT */
42301 #define FLEXSPI_LUT_COUNT                        (128U)
42302 
42303 /*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */
42304 /*! @{ */
42305 
42306 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U)
42307 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U)
42308 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
42309 #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK)
42310 /*! @} */
42311 
42312 /*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */
42313 /*! @{ */
42314 
42315 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U)
42316 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U)
42317 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
42318 #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK)
42319 /*! @} */
42320 
42321 /*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */
42322 /*! @{ */
42323 
42324 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U)
42325 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U)
42326 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
42327 #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK)
42328 /*! @} */
42329 
42330 /*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */
42331 /*! @{ */
42332 
42333 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U)
42334 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U)
42335 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
42336 #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK)
42337 /*! @} */
42338 
42339 /*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */
42340 /*! @{ */
42341 
42342 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U)
42343 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U)
42344 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
42345 #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK)
42346 /*! @} */
42347 
42348 /*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */
42349 /*! @{ */
42350 
42351 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U)
42352 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U)
42353 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
42354 #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK)
42355 /*! @} */
42356 
42357 /*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */
42358 /*! @{ */
42359 
42360 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U)
42361 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U)
42362 /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */
42363 #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK)
42364 /*! @} */
42365 
42366 /*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */
42367 /*! @{ */
42368 
42369 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U)
42370 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U)
42371 /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */
42372 #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK)
42373 /*! @} */
42374 
42375 
42376 /*!
42377  * @}
42378  */ /* end of group FLEXSPI_Register_Masks */
42379 
42380 
42381 /* FLEXSPI - Peripheral instance base addresses */
42382 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
42383   /** Peripheral FLEXSPI1 base address */
42384   #define FLEXSPI1_BASE                            (0x525E0000u)
42385   /** Peripheral FLEXSPI1 base address */
42386   #define FLEXSPI1_BASE_NS                         (0x425E0000u)
42387   /** Peripheral FLEXSPI1 base pointer */
42388   #define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
42389   /** Peripheral FLEXSPI1 base pointer */
42390   #define FLEXSPI1_NS                              ((FLEXSPI_Type *)FLEXSPI1_BASE_NS)
42391   /** Peripheral FLEXSPI2 base address */
42392   #define FLEXSPI2_BASE                            (0x545E0000u)
42393   /** Peripheral FLEXSPI2 base address */
42394   #define FLEXSPI2_BASE_NS                         (0x445E0000u)
42395   /** Peripheral FLEXSPI2 base pointer */
42396   #define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
42397   /** Peripheral FLEXSPI2 base pointer */
42398   #define FLEXSPI2_NS                              ((FLEXSPI_Type *)FLEXSPI2_BASE_NS)
42399   /** Array initializer of FLEXSPI peripheral base addresses */
42400   #define FLEXSPI_BASE_ADDRS                       { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
42401   /** Array initializer of FLEXSPI peripheral base pointers */
42402   #define FLEXSPI_BASE_PTRS                        { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
42403   /** Array initializer of FLEXSPI peripheral base addresses */
42404   #define FLEXSPI_BASE_ADDRS_NS                    { 0u, FLEXSPI1_BASE_NS, FLEXSPI2_BASE_NS }
42405   /** Array initializer of FLEXSPI peripheral base pointers */
42406   #define FLEXSPI_BASE_PTRS_NS                     { (FLEXSPI_Type *)0u, FLEXSPI1_NS, FLEXSPI2_NS }
42407 #else
42408   /** Peripheral FLEXSPI1 base address */
42409   #define FLEXSPI1_BASE                            (0x425E0000u)
42410   /** Peripheral FLEXSPI1 base pointer */
42411   #define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
42412   /** Peripheral FLEXSPI2 base address */
42413   #define FLEXSPI2_BASE                            (0x445E0000u)
42414   /** Peripheral FLEXSPI2 base pointer */
42415   #define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
42416   /** Array initializer of FLEXSPI peripheral base addresses */
42417   #define FLEXSPI_BASE_ADDRS                       { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
42418   /** Array initializer of FLEXSPI peripheral base pointers */
42419   #define FLEXSPI_BASE_PTRS                        { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
42420 #endif
42421 /** Interrupt vectors for the FLEXSPI peripheral type */
42422 #define FLEXSPI_IRQS                             { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
42423 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
42424   /* FlexSPI1 AMBA base address. */
42425   #define FlexSPI1_AMBA_BASE                       (0x38000000U)
42426   /* FlexSPI1 AMBA end address. */
42427   #define FlexSPI1_AMBA_END                        (0x3FFFFFFFU)
42428   /* FlexSPI1 ASFM address. */
42429   #define FlexSPI1_ASFM_BASE                       (0x38000000U)
42430   /* Base Address of AHB address space mapped to IP RX FIFO. */
42431   #define FlexSPI1_ARDF_BASE                       (0x57420000U)
42432   /* Base Address of AHB address space mapped to IP TX FIFO. */
42433   #define FlexSPI1_ATDF_BASE                       (0x57430000U)
42434   /* FlexSPI1 alias base address. */
42435   #define FlexSPI1_ALIAS_BASE                      (0x12000000U)
42436   /* FlexSPI2 AMBA base address. */
42437   #define FlexSPI2_AMBA_BASE                       (0x14000000U)
42438   /* FlexSPI2 AMBA end address. */
42439   #define FlexSPI2_AMBA_END                        (0x17FFFFFFU)
42440   /* FlexSPI ASFM address. */
42441   #define FlexSPI2_ASFM_BASE                       (0x14000000U)
42442   /* Base Address of AHB address space mapped to IP RX FIFO. */
42443   #define FlexSPI2_ARDF_BASE                       (0x5DE00000U)
42444   /* Base Address of AHB address space mapped to IP TX FIFO. */
42445   #define FlexSPI2_ATDF_BASE                       (0x5DE10000U)
42446   /* FlexSPI2 alias base address. */
42447   #define FlexSPI2_ALIAS_BASE                      (0x22000000U)
42448 #else
42449   /* FlexSPI1 AMBA base address. */
42450   #define FlexSPI1_AMBA_BASE                       (0x38000000U)
42451   #define FlexSPI1_AMBA_BASE_NS                    (0x28000000U)
42452   /* FlexSPI1 AMBA end address. */
42453   #define FlexSPI1_AMBA_END                        (0x3FFFFFFFU)
42454   #define FlexSPI1_AMBA_END_NS                     (0x2FFFFFFFU)
42455   /* FlexSPI1 ASFM address. */
42456   #define FlexSPI1_ASFM_BASE                       (0x38000000U)
42457   #define FlexSPI1_ASFM_BASE_NS                    (0x28000000U)
42458   /* Base Address of AHB address space mapped to IP RX FIFO. */
42459   #define FlexSPI1_ARDF_BASE                       (0x57420000U)
42460   #define FlexSPI1_ARDF_BASE_NS                    (0x47420000U)
42461   /* Base Address of AHB address space mapped to IP TX FIFO. */
42462   #define FlexSPI1_ATDF_BASE                       (0x57430000U)
42463   #define FlexSPI1_ATDF_BASE_NS                    (0x47430000U)
42464   /* FlexSPI1 alias base address. */
42465   #define FlexSPI1_ALIAS_BASE                      (0x12000000U)
42466   /* FlexSPI2 AMBA base address. */
42467   #define FlexSPI2_AMBA_BASE                       (0x14000000U)
42468   #define FlexSPI2_AMBA_BASE_NS                    (0x4000000U)
42469   /* FlexSPI2 AMBA end address. */
42470   #define FlexSPI2_AMBA_END                        (0x17FFFFFFU)
42471   #define FlexSPI2_AMBA_END_NS                     (0x7FFFFFFU)
42472   /* FlexSPI ASFM address. */
42473   #define FlexSPI2_ASFM_BASE                       (0x14000000U)
42474   #define FlexSPI2_ASFM_BASE_NS                    (0x4000000U)
42475   /* Base Address of AHB address space mapped to IP RX FIFO. */
42476   #define FlexSPI2_ARDF_BASE                       (0x5DE00000U)
42477   #define FlexSPI2_ARDF_BASE_NS                    (0x4DE00000U)
42478   /* Base Address of AHB address space mapped to IP TX FIFO. */
42479   #define FlexSPI2_ATDF_BASE                       (0x5DE10000U)
42480   #define FlexSPI2_ATDF_BASE_NS                    (0x4DE10000U)
42481   /* FlexSPI2 alias base address. */
42482   #define FlexSPI2_ALIAS_BASE                      (0x22000000U)
42483 #endif
42484 
42485 
42486 /*!
42487  * @}
42488  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
42489 
42490 
42491 /* ----------------------------------------------------------------------------
42492    -- FLEXSPI_SLV Peripheral Access Layer
42493    ---------------------------------------------------------------------------- */
42494 
42495 /*!
42496  * @addtogroup FLEXSPI_SLV_Peripheral_Access_Layer FLEXSPI_SLV Peripheral Access Layer
42497  * @{
42498  */
42499 
42500 /** FLEXSPI_SLV - Register Layout Typedef */
42501 typedef struct {
42502   __IO uint32_t MODULE_CONTROL;                    /**< Module Control, offset: 0x0 */
42503   __IO uint32_t READ_COMMAND_CONTROL;              /**< Read Command Control, offset: 0x4 */
42504   __IO uint32_t READ_REGISTER_COMMAND0;            /**< Read Register Command Setting, offset: 0x8 */
42505   __IO uint32_t READ_COMMAND[2];                   /**< Read Command 1 setting..Read Command 2 setting, array offset: 0xC, array step: 0x4 */
42506   __IO uint32_t WRITE_COMMAND_CONTROL;             /**< Write Command Control, offset: 0x14 */
42507   __IO uint32_t WRITE_REGISTER_COMMAND0;           /**< Write Register Command 0 Setting, offset: 0x18 */
42508   __IO uint32_t WRITE_COMMAND[2];                  /**< Write Command 1 Setting..Write Command 2 Setting, array offset: 0x1C, array step: 0x4 */
42509   __IO uint32_t RW_COMMAND_BASE;                   /**< Read Write Command Address Base, offset: 0x24 */
42510   __IO uint32_t CMD_RANGE[2];                      /**< Command Suit 1 Range..Command Suit 2 Range, array offset: 0x28, array step: 0x4 */
42511   __I  uint32_t MODULE_STATUS;                     /**< Module Status, offset: 0x30 */
42512   __IO uint32_t MODULE_INT;                        /**< SPI FLR interrupt, offset: 0x34 */
42513   __IO uint32_t MODULE_INTEN;                      /**< SPI FLR Interrupt Enable, offset: 0x38 */
42514   __IO uint32_t SPI_MAIL_CTRL;                     /**< SPI Mailbox control, offset: 0x3C */
42515   __I  uint32_t SPIMAIL[9];                        /**< SPI Mail Interrupt, array offset: 0x40, array step: 0x4 */
42516 } FLEXSPI_SLV_Type;
42517 
42518 /* ----------------------------------------------------------------------------
42519    -- FLEXSPI_SLV Register Masks
42520    ---------------------------------------------------------------------------- */
42521 
42522 /*!
42523  * @addtogroup FLEXSPI_SLV_Register_Masks FLEXSPI_SLV Register Masks
42524  * @{
42525  */
42526 
42527 /*! @name MODULE_CONTROL - Module Control */
42528 /*! @{ */
42529 
42530 #define FLEXSPI_SLV_MODULE_CONTROL_SWRESET_MASK  (0x1U)
42531 #define FLEXSPI_SLV_MODULE_CONTROL_SWRESET_SHIFT (0U)
42532 /*! SWRESET - Software Reset
42533  *  0b1..Initiate
42534  *  0b0..Finished
42535  */
42536 #define FLEXSPI_SLV_MODULE_CONTROL_SWRESET(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_SWRESET_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_SWRESET_MASK)
42537 
42538 #define FLEXSPI_SLV_MODULE_CONTROL_IOMODE_MASK   (0x6U)
42539 #define FLEXSPI_SLV_MODULE_CONTROL_IOMODE_SHIFT  (1U)
42540 /*! IOMODE - SPI IO Mode Control
42541  *  0b00..SDR*4
42542  *  0b01..SDR*8
42543  *  0b10..DDR*4
42544  *  0b11..DDR*8
42545  */
42546 #define FLEXSPI_SLV_MODULE_CONTROL_IOMODE(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_IOMODE_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_IOMODE_MASK)
42547 
42548 #define FLEXSPI_SLV_MODULE_CONTROL_DQSSTOP_MASK  (0x8U)
42549 #define FLEXSPI_SLV_MODULE_CONTROL_DQSSTOP_SHIFT (3U)
42550 /*! DQSSTOP - DQS Stop Feature
42551  *  0b1..Enable
42552  *  0b0..Disable
42553  */
42554 #define FLEXSPI_SLV_MODULE_CONTROL_DQSSTOP(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_DQSSTOP_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_DQSSTOP_MASK)
42555 
42556 #define FLEXSPI_SLV_MODULE_CONTROL_CSMASK_MASK   (0x10U)
42557 #define FLEXSPI_SLV_MODULE_CONTROL_CSMASK_SHIFT  (4U)
42558 /*! CSMASK - Chip Select Mask
42559  *  0b1..Masked
42560  *  0b0..Not masked
42561  */
42562 #define FLEXSPI_SLV_MODULE_CONTROL_CSMASK(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_CSMASK_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_CSMASK_MASK)
42563 
42564 #define FLEXSPI_SLV_MODULE_CONTROL_BLKREAD_MASK  (0x20U)
42565 #define FLEXSPI_SLV_MODULE_CONTROL_BLKREAD_SHIFT (5U)
42566 /*! BLKREAD - Block Read
42567  *  0b1..Blocked
42568  *  0b0..Allowed
42569  */
42570 #define FLEXSPI_SLV_MODULE_CONTROL_BLKREAD(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_BLKREAD_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_BLKREAD_MASK)
42571 
42572 #define FLEXSPI_SLV_MODULE_CONTROL_BLKWRITE_MASK (0x40U)
42573 #define FLEXSPI_SLV_MODULE_CONTROL_BLKWRITE_SHIFT (6U)
42574 /*! BLKWRITE - Block Write
42575  *  0b1..Blocked
42576  *  0b0..Allowed
42577  */
42578 #define FLEXSPI_SLV_MODULE_CONTROL_BLKWRITE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_BLKWRITE_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_BLKWRITE_MASK)
42579 
42580 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTWR_MASK (0x80U)
42581 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTWR_SHIFT (7U)
42582 /*! BLKNXTWR - Block Next Write Command
42583  *  0b1..Blocked
42584  *  0b0..Allowed
42585  */
42586 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTWR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_BLKNXTWR_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_BLKNXTWR_MASK)
42587 
42588 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTRD_MASK (0x100U)
42589 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTRD_SHIFT (8U)
42590 /*! BLKNXTRD - Block Next Read
42591  *  0b1..Blocked
42592  *  0b0..Allowed
42593  */
42594 #define FLEXSPI_SLV_MODULE_CONTROL_BLKNXTRD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_BLKNXTRD_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_BLKNXTRD_MASK)
42595 
42596 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONEWR_MASK (0x200U)
42597 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONEWR_SHIFT (9U)
42598 /*! ALLOWONEWR - Allow One More Write
42599  *  0b1..Allowed
42600  *  0b0..Not allowed
42601  */
42602 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONEWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_ALLOWONEWR_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_ALLOWONEWR_MASK)
42603 
42604 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONERD_MASK (0x400U)
42605 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONERD_SHIFT (10U)
42606 /*! ALLOWONERD - Allow One More Read
42607  *  0b1..Allowed
42608  *  0b0..Not allowed
42609  */
42610 #define FLEXSPI_SLV_MODULE_CONTROL_ALLOWONERD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_ALLOWONERD_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_ALLOWONERD_MASK)
42611 
42612 #define FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE_MASK (0x800U)
42613 #define FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE_SHIFT (11U)
42614 /*! CMDRANGEBASEUPDATE - AXI Command Range Base Update
42615  *  0b1..Updated
42616  *  0b0..Not updated
42617  */
42618 #define FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE_SHIFT)) & FLEXSPI_SLV_MODULE_CONTROL_CMDRANGEBASEUPDATE_MASK)
42619 /*! @} */
42620 
42621 /*! @name READ_COMMAND_CONTROL - Read Command Control */
42622 /*! @{ */
42623 
42624 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK (0x3U)
42625 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_SHIFT (0U)
42626 /*! RDFETCHSIZE - Read Fetch Size
42627  *  0b00..256 bytes
42628  *  0b01..512 bytes
42629  *  0b10..1 KB
42630  *  0b11..2 KB
42631  */
42632 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK)
42633 
42634 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_MASK (0xFCU)
42635 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_SHIFT (2U)
42636 /*! RDWM - Read Watermark Level */
42637 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_CONTROL_RDWM_MASK)
42638 
42639 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDOT_MASK (0x100U)
42640 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDOT_SHIFT (8U)
42641 /*! RDOT - Read Outstanding
42642  *  0b1..Send requests outstandingly
42643  *  0b0..Send requests after previous leaders finish
42644  */
42645 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_RDOT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_CONTROL_RDOT_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_CONTROL_RDOT_MASK)
42646 
42647 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_MASK (0x200U)
42648 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_SHIFT (9U)
42649 /*! WMEN - Read Water Mark Enable
42650  *  0b1..Enable
42651  *  0b0..Disable
42652  */
42653 #define FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_CONTROL_WMEN_MASK)
42654 /*! @} */
42655 
42656 /*! @name READ_REGISTER_COMMAND0 - Read Register Command Setting */
42657 /*! @{ */
42658 
42659 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES_MASK (0xFFFFU)
42660 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES_SHIFT (0U)
42661 /*! DUMMYCYCLES - Read Register Dummy Cycles */
42662 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES_SHIFT)) & FLEXSPI_SLV_READ_REGISTER_COMMAND0_DUMMYCYCLES_MASK)
42663 
42664 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET_MASK (0xFFFF0000U)
42665 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET_SHIFT (16U)
42666 /*! COMMANDSET - Read Register Command Setting */
42667 #define FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET_SHIFT)) & FLEXSPI_SLV_READ_REGISTER_COMMAND0_COMMANDSET_MASK)
42668 /*! @} */
42669 
42670 /*! @name READ_COMMAND - Read Command 1 setting..Read Command 2 setting */
42671 /*! @{ */
42672 
42673 #define FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_MASK (0xFFFFU)
42674 #define FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_SHIFT (0U)
42675 /*! DUMMYCYCLES - Read Command 2 Dummy Cycles */
42676 #define FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_DUMMYCYCLES_MASK)
42677 
42678 #define FLEXSPI_SLV_READ_COMMAND_COMMANDSET_MASK (0xFFFF0000U)
42679 #define FLEXSPI_SLV_READ_COMMAND_COMMANDSET_SHIFT (16U)
42680 /*! COMMANDSET - Read Command 2 Setting */
42681 #define FLEXSPI_SLV_READ_COMMAND_COMMANDSET(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_READ_COMMAND_COMMANDSET_SHIFT)) & FLEXSPI_SLV_READ_COMMAND_COMMANDSET_MASK)
42682 /*! @} */
42683 
42684 /* The count of FLEXSPI_SLV_READ_COMMAND */
42685 #define FLEXSPI_SLV_READ_COMMAND_COUNT           (2U)
42686 
42687 /*! @name WRITE_COMMAND_CONTROL - Write Command Control */
42688 /*! @{ */
42689 
42690 #define FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_MASK (0x3U)
42691 #define FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_SHIFT (0U)
42692 /*! WRWM - Write Watermark
42693  *  0b00..32 bytes
42694  *  0b01..64 bytes
42695  *  0b10..128 bytes
42696  *  0b11..256 bytes
42697  */
42698 #define FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_SHIFT)) & FLEXSPI_SLV_WRITE_COMMAND_CONTROL_WRWM_MASK)
42699 /*! @} */
42700 
42701 /*! @name WRITE_REGISTER_COMMAND0 - Write Register Command 0 Setting */
42702 /*! @{ */
42703 
42704 #define FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET_MASK (0xFFFF0000U)
42705 #define FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET_SHIFT (16U)
42706 /*! COMMANDSET - Write Register Command Setting */
42707 #define FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET_SHIFT)) & FLEXSPI_SLV_WRITE_REGISTER_COMMAND0_COMMANDSET_MASK)
42708 /*! @} */
42709 
42710 /*! @name WRITE_COMMAND - Write Command 1 Setting..Write Command 2 Setting */
42711 /*! @{ */
42712 
42713 #define FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET_MASK (0xFFFF0000U)
42714 #define FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET_SHIFT (16U)
42715 /*! COMMANDSET - Write Command 2 Setting */
42716 #define FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET_SHIFT)) & FLEXSPI_SLV_WRITE_COMMAND_COMMANDSET_MASK)
42717 /*! @} */
42718 
42719 /* The count of FLEXSPI_SLV_WRITE_COMMAND */
42720 #define FLEXSPI_SLV_WRITE_COMMAND_COUNT          (2U)
42721 
42722 /*! @name RW_COMMAND_BASE - Read Write Command Address Base */
42723 /*! @{ */
42724 
42725 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1_MASK (0xFFFFU)
42726 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1_SHIFT (0U)
42727 /*! ADDRBASE1 - Address Base 1 */
42728 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1_SHIFT)) & FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1_MASK)
42729 
42730 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2_MASK (0xFFFF0000U)
42731 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2_SHIFT (16U)
42732 /*! ADDRBASE2 - Address Base 2 */
42733 #define FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2_SHIFT)) & FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2_MASK)
42734 /*! @} */
42735 
42736 /*! @name CMD_RANGE - Command Suit 1 Range..Command Suit 2 Range */
42737 /*! @{ */
42738 
42739 #define FLEXSPI_SLV_CMD_RANGE_RANGE_MASK         (0xFFFFFC00U)
42740 #define FLEXSPI_SLV_CMD_RANGE_RANGE_SHIFT        (10U)
42741 /*! RANGE - Memory Range */
42742 #define FLEXSPI_SLV_CMD_RANGE_RANGE(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_CMD_RANGE_RANGE_SHIFT)) & FLEXSPI_SLV_CMD_RANGE_RANGE_MASK)
42743 /*! @} */
42744 
42745 /* The count of FLEXSPI_SLV_CMD_RANGE */
42746 #define FLEXSPI_SLV_CMD_RANGE_COUNT              (2U)
42747 
42748 /*! @name MODULE_STATUS - Module Status */
42749 /*! @{ */
42750 
42751 #define FLEXSPI_SLV_MODULE_STATUS_WIP_MASK       (0x1U)
42752 #define FLEXSPI_SLV_MODULE_STATUS_WIP_SHIFT      (0U)
42753 /*! WIP - Write in Progress
42754  *  0b1..Busy
42755  *  0b0..Not busy
42756  */
42757 #define FLEXSPI_SLV_MODULE_STATUS_WIP(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_WIP_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_WIP_MASK)
42758 
42759 #define FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_MASK (0x2U)
42760 #define FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_SHIFT (1U)
42761 /*! AXIREADIDLE - AXI Read Leader Idle
42762  *  0b1..Idle
42763  *  0b0..Busy
42764  */
42765 #define FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_AXIREADIDLE_MASK)
42766 
42767 #define FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_MASK (0x4U)
42768 #define FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_SHIFT (2U)
42769 /*! REGRWIDLE - Register Read Write Idle
42770  *  0b1..Idle
42771  *  0b0..Busy
42772  */
42773 #define FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_REGRWIDLE_MASK)
42774 
42775 #define FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_MASK   (0x8U)
42776 #define FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_SHIFT  (3U)
42777 /*! SEQIDLE - SEQ Controller Idle
42778  *  0b1..Idle
42779  *  0b0..Busy
42780  */
42781 #define FLEXSPI_SLV_MODULE_STATUS_SEQIDLE(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_SEQIDLE_MASK)
42782 
42783 #define FLEXSPI_SLV_MODULE_STATUS_RDOFR_MASK     (0xF0U)
42784 #define FLEXSPI_SLV_MODULE_STATUS_RDOFR_SHIFT    (4U)
42785 /*! RDOFR - Read Out-of-Range Counter */
42786 #define FLEXSPI_SLV_MODULE_STATUS_RDOFR(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_RDOFR_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_RDOFR_MASK)
42787 
42788 #define FLEXSPI_SLV_MODULE_STATUS_WROFR_MASK     (0xF00U)
42789 #define FLEXSPI_SLV_MODULE_STATUS_WROFR_SHIFT    (8U)
42790 /*! WROFR - Write Out-of-Range Counter */
42791 #define FLEXSPI_SLV_MODULE_STATUS_WROFR(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_WROFR_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_WROFR_MASK)
42792 
42793 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIRD_MASK (0x1000U)
42794 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIRD_SHIFT (12U)
42795 /*! ALLOWAXIRD - Allow AXI Read Access
42796  *  0b1..Allowed
42797  *  0b0..Denied
42798  */
42799 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIRD(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIRD_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIRD_MASK)
42800 
42801 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIWR_MASK (0x2000U)
42802 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIWR_SHIFT (13U)
42803 /*! ALLOWAXIWR - Allow AXI Write Access
42804  *  0b1..Allowed
42805  *  0b0..Denied
42806  */
42807 #define FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIWR(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIWR_SHIFT)) & FLEXSPI_SLV_MODULE_STATUS_ALLOWAXIWR_MASK)
42808 /*! @} */
42809 
42810 /*! @name MODULE_INT - SPI FLR interrupt */
42811 /*! @{ */
42812 
42813 #define FLEXSPI_SLV_MODULE_INT_WOF_MASK          (0x1U)
42814 #define FLEXSPI_SLV_MODULE_INT_WOF_SHIFT         (0U)
42815 /*! WOF - Write Overflow Interrupt
42816  *  0b1..Occurred
42817  *  0b0..Did not occur
42818  */
42819 #define FLEXSPI_SLV_MODULE_INT_WOF(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INT_WOF_SHIFT)) & FLEXSPI_SLV_MODULE_INT_WOF_MASK)
42820 
42821 #define FLEXSPI_SLV_MODULE_INT_RUF_MASK          (0x2U)
42822 #define FLEXSPI_SLV_MODULE_INT_RUF_SHIFT         (1U)
42823 /*! RUF - Read Underflow
42824  *  0b1..Occurred
42825  *  0b0..Did not occur
42826  */
42827 #define FLEXSPI_SLV_MODULE_INT_RUF(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INT_RUF_SHIFT)) & FLEXSPI_SLV_MODULE_INT_RUF_MASK)
42828 
42829 #define FLEXSPI_SLV_MODULE_INT_ERRCMD_MASK       (0x4U)
42830 #define FLEXSPI_SLV_MODULE_INT_ERRCMD_SHIFT      (2U)
42831 /*! ERRCMD - Error Command
42832  *  0b1..Received
42833  *  0b0..Not received
42834  */
42835 #define FLEXSPI_SLV_MODULE_INT_ERRCMD(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INT_ERRCMD_SHIFT)) & FLEXSPI_SLV_MODULE_INT_ERRCMD_MASK)
42836 /*! @} */
42837 
42838 /*! @name MODULE_INTEN - SPI FLR Interrupt Enable */
42839 /*! @{ */
42840 
42841 #define FLEXSPI_SLV_MODULE_INTEN_WOFEN_MASK      (0x1U)
42842 #define FLEXSPI_SLV_MODULE_INTEN_WOFEN_SHIFT     (0U)
42843 /*! WOFEN - Write Overflow Interrupt Enable
42844  *  0b1..Enable
42845  *  0b0..Disable
42846  */
42847 #define FLEXSPI_SLV_MODULE_INTEN_WOFEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INTEN_WOFEN_SHIFT)) & FLEXSPI_SLV_MODULE_INTEN_WOFEN_MASK)
42848 
42849 #define FLEXSPI_SLV_MODULE_INTEN_RUFEN_MASK      (0x2U)
42850 #define FLEXSPI_SLV_MODULE_INTEN_RUFEN_SHIFT     (1U)
42851 /*! RUFEN - Read Underflow Interrupt Enable
42852  *  0b1..Enable
42853  *  0b0..Disable
42854  */
42855 #define FLEXSPI_SLV_MODULE_INTEN_RUFEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INTEN_RUFEN_SHIFT)) & FLEXSPI_SLV_MODULE_INTEN_RUFEN_MASK)
42856 
42857 #define FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN_MASK   (0x4U)
42858 #define FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN_SHIFT  (2U)
42859 /*! ERRCMDEN - Error Command Interrupt Enable
42860  *  0b1..Enable
42861  *  0b0..Disable
42862  */
42863 #define FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN(x)     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN_SHIFT)) & FLEXSPI_SLV_MODULE_INTEN_ERRCMDEN_MASK)
42864 /*! @} */
42865 
42866 /*! @name SPI_MAIL_CTRL - SPI Mailbox control */
42867 /*! @{ */
42868 
42869 #define FLEXSPI_SLV_SPI_MAIL_CTRL_CLRINT_MASK    (0x1U)
42870 #define FLEXSPI_SLV_SPI_MAIL_CTRL_CLRINT_SHIFT   (0U)
42871 /*! CLRINT - Clear Interrupt
42872  *  0b1..Clear
42873  *  0b0..Do not clear
42874  */
42875 #define FLEXSPI_SLV_SPI_MAIL_CTRL_CLRINT(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_SPI_MAIL_CTRL_CLRINT_SHIFT)) & FLEXSPI_SLV_SPI_MAIL_CTRL_CLRINT_MASK)
42876 
42877 #define FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_MASK  (0x2U)
42878 #define FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_SHIFT (1U)
42879 /*! SPIINTEN - SPI Leader Interrupt Enable
42880  *  0b1..Enable
42881  *  0b0..Disable
42882  */
42883 #define FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_SHIFT)) & FLEXSPI_SLV_SPI_MAIL_CTRL_SPIINTEN_MASK)
42884 /*! @} */
42885 
42886 /*! @name SPIMAIL - SPI Mail Interrupt */
42887 /*! @{ */
42888 
42889 #define FLEXSPI_SLV_SPIMAIL_MAILn_MASK           (0xFFFFFFFFU)
42890 #define FLEXSPI_SLV_SPIMAIL_MAILn_SHIFT          (0U)
42891 #define FLEXSPI_SLV_SPIMAIL_MAILn(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_SLV_SPIMAIL_MAILn_SHIFT)) & FLEXSPI_SLV_SPIMAIL_MAILn_MASK)
42892 /*! @} */
42893 
42894 /* The count of FLEXSPI_SLV_SPIMAIL */
42895 #define FLEXSPI_SLV_SPIMAIL_COUNT                (9U)
42896 
42897 
42898 /*!
42899  * @}
42900  */ /* end of group FLEXSPI_SLV_Register_Masks */
42901 
42902 
42903 /* FLEXSPI_SLV - Peripheral instance base addresses */
42904 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
42905   /** Peripheral FLEXSPI_SLV base address */
42906   #define FLEXSPI_SLV_BASE                         (0x52900000u)
42907   /** Peripheral FLEXSPI_SLV base address */
42908   #define FLEXSPI_SLV_BASE_NS                      (0x42900000u)
42909   /** Peripheral FLEXSPI_SLV base pointer */
42910   #define FLEXSPI_SLV                              ((FLEXSPI_SLV_Type *)FLEXSPI_SLV_BASE)
42911   /** Peripheral FLEXSPI_SLV base pointer */
42912   #define FLEXSPI_SLV_NS                           ((FLEXSPI_SLV_Type *)FLEXSPI_SLV_BASE_NS)
42913   /** Array initializer of FLEXSPI_SLV peripheral base addresses */
42914   #define FLEXSPI_SLV_BASE_ADDRS                   { FLEXSPI_SLV_BASE }
42915   /** Array initializer of FLEXSPI_SLV peripheral base pointers */
42916   #define FLEXSPI_SLV_BASE_PTRS                    { FLEXSPI_SLV }
42917   /** Array initializer of FLEXSPI_SLV peripheral base addresses */
42918   #define FLEXSPI_SLV_BASE_ADDRS_NS                { FLEXSPI_SLV_BASE_NS }
42919   /** Array initializer of FLEXSPI_SLV peripheral base pointers */
42920   #define FLEXSPI_SLV_BASE_PTRS_NS                 { FLEXSPI_SLV_NS }
42921 #else
42922   /** Peripheral FLEXSPI_SLV base address */
42923   #define FLEXSPI_SLV_BASE                         (0x42900000u)
42924   /** Peripheral FLEXSPI_SLV base pointer */
42925   #define FLEXSPI_SLV                              ((FLEXSPI_SLV_Type *)FLEXSPI_SLV_BASE)
42926   /** Array initializer of FLEXSPI_SLV peripheral base addresses */
42927   #define FLEXSPI_SLV_BASE_ADDRS                   { FLEXSPI_SLV_BASE }
42928   /** Array initializer of FLEXSPI_SLV peripheral base pointers */
42929   #define FLEXSPI_SLV_BASE_PTRS                    { FLEXSPI_SLV }
42930 #endif
42931 
42932 /*!
42933  * @}
42934  */ /* end of group FLEXSPI_SLV_Peripheral_Access_Layer */
42935 
42936 
42937 /* ----------------------------------------------------------------------------
42938    -- GPC_CPU_CTRL Peripheral Access Layer
42939    ---------------------------------------------------------------------------- */
42940 
42941 /*!
42942  * @addtogroup GPC_CPU_CTRL_Peripheral_Access_Layer GPC_CPU_CTRL Peripheral Access Layer
42943  * @{
42944  */
42945 
42946 /** GPC_CPU_CTRL - Register Layout Typedef */
42947 typedef struct {
42948   struct {                                         /* offset: 0x0, array step: 0x800 */
42949          uint8_t RESERVED_0[4];
42950     __IO uint32_t CM_AUTHEN_CTRL;                    /**< CM Authentication Control, array offset: 0x4, array step: 0x800 */
42951          uint8_t RESERVED_1[4];
42952     __IO uint32_t CM_MISC;                           /**< Miscellaneous, array offset: 0xC, array step: 0x800 */
42953     __IO uint32_t CM_MODE_CTRL;                      /**< CPU mode control, array offset: 0x10, array step: 0x800 */
42954     __I  uint32_t CM_MODE_STAT;                      /**< CM CPU mode Status, array offset: 0x14, array step: 0x800 */
42955          uint8_t RESERVED_2[232];
42956     __IO uint32_t CM_IRQ_WAKEUP_MASK[8];             /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: index*0x800, index2*0x4 */
42957          uint8_t RESERVED_3[32];
42958     __IO uint32_t CM_NON_IRQ_WAKEUP_MASK;            /**< CM non-IRQ wakeup mask, array offset: 0x140, array step: 0x800 */
42959          uint8_t RESERVED_4[12];
42960     __I  uint32_t CM_IRQ_WAKEUP_STAT[8];             /**< CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: index*0x800, index2*0x4 */
42961          uint8_t RESERVED_5[32];
42962     __I  uint32_t CM_NON_IRQ_WAKEUP_STAT;            /**< CM non-irq wakeup status, array offset: 0x190, array step: 0x800 */
42963          uint8_t RESERVED_6[108];
42964     __IO uint32_t CM_SLEEP_SSAR_CTRL;                /**< CM sleep SSAR control, array offset: 0x200, array step: 0x800 */
42965          uint8_t RESERVED_7[4];
42966     __IO uint32_t CM_SLEEP_LPCG_CTRL;                /**< CM sleep LPCG control, array offset: 0x208, array step: 0x800 */
42967          uint8_t RESERVED_8[4];
42968     __IO uint32_t CM_SLEEP_PLL_CTRL;                 /**< CM sleep PLL control, array offset: 0x210, array step: 0x800 */
42969          uint8_t RESERVED_9[4];
42970     __IO uint32_t CM_SLEEP_ISO_CTRL;                 /**< CM sleep isolation control, array offset: 0x218, array step: 0x800 */
42971          uint8_t RESERVED_10[4];
42972     __IO uint32_t CM_SLEEP_RESET_CTRL;               /**< CM sleep reset control, array offset: 0x220, array step: 0x800 */
42973          uint8_t RESERVED_11[4];
42974     __IO uint32_t CM_SLEEP_POWER_CTRL;               /**< CM sleep power control, array offset: 0x228, array step: 0x800 */
42975          uint8_t RESERVED_12[100];
42976     __IO uint32_t CM_WAKEUP_POWER_CTRL;              /**< CM wakeup power control, array offset: 0x290, array step: 0x800 */
42977          uint8_t RESERVED_13[4];
42978     __IO uint32_t CM_WAKEUP_RESET_CTRL;              /**< CM wakeup reset control, array offset: 0x298, array step: 0x800 */
42979          uint8_t RESERVED_14[4];
42980     __IO uint32_t CM_WAKEUP_ISO_CTRL;                /**< CM wakeup isolation control, array offset: 0x2A0, array step: 0x800 */
42981          uint8_t RESERVED_15[4];
42982     __IO uint32_t CM_WAKEUP_PLL_CTRL;                /**< CM wakeup PLL control, array offset: 0x2A8, array step: 0x800 */
42983          uint8_t RESERVED_16[4];
42984     __IO uint32_t CM_WAKEUP_LPCG_CTRL;               /**< CM wakeup LPCG control, array offset: 0x2B0, array step: 0x800 */
42985          uint8_t RESERVED_17[12];
42986     __IO uint32_t CM_WAKEUP_SSAR_CTRL;               /**< CM wakeup SSAR control, array offset: 0x2C0, array step: 0x800 */
42987          uint8_t RESERVED_18[188];
42988     __IO uint32_t CM_SYS_SLEEP_CTRL;                 /**< CM system sleep control, array offset: 0x380, array step: 0x800 */
42989          uint8_t RESERVED_19[1148];
42990   } AUTHEN[2];
42991 } GPC_CPU_CTRL_Type;
42992 
42993 /* ----------------------------------------------------------------------------
42994    -- GPC_CPU_CTRL Register Masks
42995    ---------------------------------------------------------------------------- */
42996 
42997 /*!
42998  * @addtogroup GPC_CPU_CTRL_Register_Masks GPC_CPU_CTRL Register Masks
42999  * @{
43000  */
43001 
43002 /*! @name CM_AUTHEN_CTRL - CM Authentication Control */
43003 /*! @{ */
43004 
43005 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U)
43006 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U)
43007 /*! LOCK_CFG - Configuration lock
43008  *  0b0..The value of low power configuration fields are not locked.
43009  *  0b1..The value of low power configuration fields are locked. It locks the CPUx_CM registers which are marked
43010  *       as "Locked by LOCK_CFG field" in the function field.
43011  */
43012 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x)  (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
43013 
43014 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK    (0x100U)
43015 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT   (8U)
43016 /*! USER - Allow user mode access
43017  *  0b0..Allow only privilege mode to access CPU mode control registers
43018  *  0b1..Allow both privilege and user mode to access CPU mode control registers
43019  */
43020 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER(x)      (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK)
43021 
43022 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x200U)
43023 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (9U)
43024 /*! NONSECURE - Allow non-secure mode access
43025  *  0b0..Allow only secure mode to access CPU mode control
43026  *  0b1..Allow both secure and non-secure mode to access CPU mode control registers
43027  */
43028 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
43029 
43030 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U)
43031 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U)
43032 /*! LOCK_SETTING - Lock NONSECURE and USER
43033  *  0b0..NONSECURE and USER fields are not locked
43034  *  0b1..NONSECURE and USER fields are locked
43035  */
43036 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
43037 
43038 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U)
43039 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U)
43040 /*! LOCK_LIST - White list lock
43041  *  0b0..WHITE_LIST is not locked
43042  *  0b1..WHITE_LIST is locked
43043  */
43044 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
43045 
43046 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U)
43047 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U)
43048 /*! WHITE_LIST - Domain ID white list */
43049 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
43050 /*! @} */
43051 
43052 /* The count of GPC_CPU_CTRL_CM_AUTHEN_CTRL */
43053 #define GPC_CPU_CTRL_CM_AUTHEN_CTRL_COUNT        (2U)
43054 
43055 /*! @name CM_MISC - Miscellaneous */
43056 /*! @{ */
43057 
43058 #define GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK       (0x1U)
43059 #define GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT      (0U)
43060 /*! NMI_STAT - Non-masked interrupt status
43061  *  0b0..NMI is not asserted
43062  *  0b1..NMI is asserted
43063  */
43064 #define GPC_CPU_CTRL_CM_MISC_NMI_STAT(x)         (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK)
43065 
43066 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK  (0x2U)
43067 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
43068 /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req to assert during CPU low power status
43069  *  0b0..Disable cpu_sleep_hold_req
43070  *  0b1..Allow cpu_sleep_hold_req to assert during CPU low power status
43071  */
43072 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN(x)    (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
43073 
43074 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
43075 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
43076 /*! SLEEP_HOLD_STAT - CPU sleep hold status
43077  *  0b0..CPU sleep hold is acknowledged
43078  *  0b1..CPU is not in sleep hold
43079  */
43080 #define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT(x)  (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
43081 /*! @} */
43082 
43083 /* The count of GPC_CPU_CTRL_CM_MISC */
43084 #define GPC_CPU_CTRL_CM_MISC_COUNT               (2U)
43085 
43086 /*! @name CM_MODE_CTRL - CPU mode control */
43087 /*! @{ */
43088 
43089 #define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
43090 #define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
43091 /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event
43092  *  0b00..Stay in RUN mode
43093  *  0b01..Transit to WAIT mode
43094  *  0b10..Transit to STOP mode
43095  *  0b11..Transit to SUSPEND mode
43096  */
43097 #define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
43098 
43099 #define GPC_CPU_CTRL_CM_MODE_CTRL_WFE_EN_MASK    (0x10U)
43100 #define GPC_CPU_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT   (4U)
43101 /*! WFE_EN - WFE assertion can be sleep event
43102  *  0b0..WFE assertion can not trigger low power
43103  *  0b1..WFE assertion can trigger low power
43104  */
43105 #define GPC_CPU_CTRL_CM_MODE_CTRL_WFE_EN(x)      (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
43106 /*! @} */
43107 
43108 /* The count of GPC_CPU_CTRL_CM_MODE_CTRL */
43109 #define GPC_CPU_CTRL_CM_MODE_CTRL_COUNT          (2U)
43110 
43111 /*! @name CM_MODE_STAT - CM CPU mode Status */
43112 /*! @{ */
43113 
43114 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
43115 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
43116 /*! CPU_MODE_CURRENT - Current CPU mode
43117  *  0b00..CPU is currently in RUN mode
43118  *  0b01..CPU is currently in WAIT mode
43119  *  0b10..CPU is currently in STOP mode
43120  *  0b11..CPU is currently in SUSPEND mode
43121  */
43122 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
43123 
43124 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
43125 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
43126 /*! CPU_MODE_PREVIOUS - Previous CPU mode
43127  *  0b00..CPU was previously in RUN mode
43128  *  0b01..CPU was previously in WAIT mode
43129  *  0b10..CPU was previously in STOP mode
43130  *  0b11..CPU was previously in SUSPEND mode
43131  */
43132 #define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
43133 /*! @} */
43134 
43135 /* The count of GPC_CPU_CTRL_CM_MODE_STAT */
43136 #define GPC_CPU_CTRL_CM_MODE_STAT_COUNT          (2U)
43137 
43138 /*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */
43139 /*! @{ */
43140 
43141 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_0_31_MASK (0xFFFFFFFFU)
43142 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_0_31_SHIFT (0U)
43143 /*! MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform */
43144 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_0_31_MASK)
43145 
43146 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_32_63_MASK (0xFFFFFFFFU)
43147 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_32_63_SHIFT (0U)
43148 /*! MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform */
43149 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_32_63_MASK)
43150 
43151 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_64_95_MASK (0xFFFFFFFFU)
43152 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_64_95_SHIFT (0U)
43153 /*! MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform */
43154 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_64_95_MASK)
43155 
43156 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_96_127_MASK (0xFFFFFFFFU)
43157 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_96_127_SHIFT (0U)
43158 /*! MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform */
43159 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_96_127_MASK)
43160 
43161 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_128_159_MASK (0xFFFFFFFFU)
43162 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_128_159_SHIFT (0U)
43163 /*! MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform */
43164 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_128_159_MASK)
43165 
43166 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_160_191_MASK (0xFFFFFFFFU)
43167 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_160_191_SHIFT (0U)
43168 /*! MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform */
43169 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_160_191_MASK)
43170 
43171 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_192_223_MASK (0xFFFFFFFFU)
43172 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_192_223_SHIFT (0U)
43173 /*! MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform */
43174 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_192_223_MASK)
43175 
43176 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_224_255_MASK (0xFFFFFFFFU)
43177 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_224_255_SHIFT (0U)
43178 /*! MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform */
43179 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_MASK_224_255_MASK)
43180 /*! @} */
43181 
43182 /* The count of GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK */
43183 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_COUNT    (2U)
43184 
43185 /* The count of GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK */
43186 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_COUNT2   (8U)
43187 
43188 /*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-IRQ wakeup mask */
43189 /*! @{ */
43190 
43191 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
43192 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
43193 /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform */
43194 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
43195 /*! @} */
43196 
43197 /* The count of GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK */
43198 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_COUNT (2U)
43199 
43200 /*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */
43201 /*! @{ */
43202 
43203 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_0_31_MASK (0xFFFFFFFFU)
43204 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_0_31_SHIFT (0U)
43205 /*! STAT_0_31 - IRQ status */
43206 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_0_31_MASK)
43207 
43208 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_32_63_MASK (0xFFFFFFFFU)
43209 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_32_63_SHIFT (0U)
43210 /*! STAT_32_63 - IRQ status */
43211 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_32_63_MASK)
43212 
43213 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_64_95_MASK (0xFFFFFFFFU)
43214 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_64_95_SHIFT (0U)
43215 /*! STAT_64_95 - IRQ status */
43216 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_64_95_MASK)
43217 
43218 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_96_127_MASK (0xFFFFFFFFU)
43219 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_96_127_SHIFT (0U)
43220 /*! STAT_96_127 - IRQ status */
43221 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_96_127_MASK)
43222 
43223 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_128_159_MASK (0xFFFFFFFFU)
43224 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_128_159_SHIFT (0U)
43225 /*! STAT_128_159 - IRQ status */
43226 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_128_159_MASK)
43227 
43228 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_160_191_MASK (0xFFFFFFFFU)
43229 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_160_191_SHIFT (0U)
43230 /*! STAT_160_191 - IRQ status */
43231 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_160_191_MASK)
43232 
43233 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_192_223_MASK (0xFFFFFFFFU)
43234 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_192_223_SHIFT (0U)
43235 /*! STAT_192_223 - IRQ status */
43236 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_192_223_MASK)
43237 
43238 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_224_255_MASK (0xFFFFFFFFU)
43239 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_224_255_SHIFT (0U)
43240 /*! STAT_224_255 - IRQ status */
43241 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_STAT_224_255_MASK)
43242 /*! @} */
43243 
43244 /* The count of GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT */
43245 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_COUNT    (2U)
43246 
43247 /* The count of GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT */
43248 #define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_COUNT2   (8U)
43249 
43250 /*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */
43251 /*! @{ */
43252 
43253 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
43254 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
43255 /*! DEBUG_WAKEUP_STAT - Debug wakeup status
43256  *  0b0..No debug wakeup is requested
43257  *  0b1..Debug wakeup is requested
43258  */
43259 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
43260 /*! @} */
43261 
43262 /* The count of GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT */
43263 #define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_COUNT (2U)
43264 
43265 /*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */
43266 /*! @{ */
43267 
43268 #define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
43269 #define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
43270 /*! DISABLE - Disable this step
43271  *  0b0..This step is enabled.
43272  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43273  */
43274 #define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
43275 /*! @} */
43276 
43277 /* The count of GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL */
43278 #define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_COUNT    (2U)
43279 
43280 /*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */
43281 /*! @{ */
43282 
43283 #define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
43284 #define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
43285 /*! DISABLE - Disable this step
43286  *  0b0..This step is enabled.
43287  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43288  */
43289 #define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
43290 /*! @} */
43291 
43292 /* The count of GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL */
43293 #define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_COUNT    (2U)
43294 
43295 /*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */
43296 /*! @{ */
43297 
43298 #define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
43299 #define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
43300 /*! DISABLE - Disable this step
43301  *  0b0..This step is enabled.
43302  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43303  */
43304 #define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
43305 /*! @} */
43306 
43307 /* The count of GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL */
43308 #define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_COUNT     (2U)
43309 
43310 /*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */
43311 /*! @{ */
43312 
43313 #define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
43314 #define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
43315 /*! DISABLE - Disable this step
43316  *  0b0..This step is enabled.
43317  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43318  */
43319 #define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
43320 /*! @} */
43321 
43322 /* The count of GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL */
43323 #define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_COUNT     (2U)
43324 
43325 /*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */
43326 /*! @{ */
43327 
43328 #define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
43329 #define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
43330 /*! DISABLE - Disable this step
43331  *  0b0..This step is enabled.
43332  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43333  */
43334 #define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
43335 /*! @} */
43336 
43337 /* The count of GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL */
43338 #define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_COUNT   (2U)
43339 
43340 /*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */
43341 /*! @{ */
43342 
43343 #define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
43344 #define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
43345 /*! DISABLE - Disable this step
43346  *  0b0..This step is enabled.
43347  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43348  */
43349 #define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
43350 /*! @} */
43351 
43352 /* The count of GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL */
43353 #define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_COUNT   (2U)
43354 
43355 /*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */
43356 /*! @{ */
43357 
43358 #define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
43359 #define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
43360 /*! DISABLE - Disable this step
43361  *  0b0..This step is enabled.
43362  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43363  */
43364 #define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
43365 /*! @} */
43366 
43367 /* The count of GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL */
43368 #define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_COUNT  (2U)
43369 
43370 /*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */
43371 /*! @{ */
43372 
43373 #define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
43374 #define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
43375 /*! DISABLE - Disable this step
43376  *  0b0..This step is enabled.
43377  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43378  */
43379 #define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
43380 /*! @} */
43381 
43382 /* The count of GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL */
43383 #define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_COUNT  (2U)
43384 
43385 /*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */
43386 /*! @{ */
43387 
43388 #define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
43389 #define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
43390 /*! DISABLE - Disable this step
43391  *  0b0..This step is enabled.
43392  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43393  */
43394 #define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
43395 /*! @} */
43396 
43397 /* The count of GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL */
43398 #define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_COUNT    (2U)
43399 
43400 /*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */
43401 /*! @{ */
43402 
43403 #define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
43404 #define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
43405 /*! DISABLE - Disable this step
43406  *  0b0..This step is enabled.
43407  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43408  */
43409 #define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
43410 /*! @} */
43411 
43412 /* The count of GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL */
43413 #define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_COUNT    (2U)
43414 
43415 /*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */
43416 /*! @{ */
43417 
43418 #define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
43419 #define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
43420 /*! DISABLE - Disable this step
43421  *  0b0..This step is enabled.
43422  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43423  */
43424 #define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
43425 /*! @} */
43426 
43427 /* The count of GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL */
43428 #define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_COUNT   (2U)
43429 
43430 /*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */
43431 /*! @{ */
43432 
43433 #define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
43434 #define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
43435 /*! DISABLE - Disable this step
43436  *  0b0..This step is enabled.
43437  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43438  */
43439 #define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
43440 /*! @} */
43441 
43442 /* The count of GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL */
43443 #define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_COUNT   (2U)
43444 
43445 /*! @name CM_SYS_SLEEP_CTRL - CM system sleep control */
43446 /*! @{ */
43447 
43448 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK (0x1U)
43449 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT (0U)
43450 /*! SS_WAIT - Request system sleep when CPU is in WAIT mode
43451  *  0b0..Do not request system sleep when CPU is in WAIT mode
43452  *  0b1..Request system sleep when CPU is in WAIT mode
43453  */
43454 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK)
43455 
43456 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK (0x2U)
43457 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT (1U)
43458 /*! SS_STOP - Request system sleep when CPU is in STOP mode
43459  *  0b0..Do not request system sleep when CPU is in STOP mode
43460  *  0b1..Request system sleep when CPU is in STOP mode
43461  */
43462 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK)
43463 
43464 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK (0x4U)
43465 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT (2U)
43466 /*! SS_SUSPEND - Request system sleep when CPU is in SUSPEND mode
43467  *  0b0..Do not request system sleep when CPU is in SUSPEND mode
43468  *  0b1..Request system sleep when CPU is in SUSPEND mode
43469  */
43470 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK)
43471 /*! @} */
43472 
43473 /* The count of GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL */
43474 #define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_COUNT     (2U)
43475 
43476 
43477 /*!
43478  * @}
43479  */ /* end of group GPC_CPU_CTRL_Register_Masks */
43480 
43481 
43482 /* GPC_CPU_CTRL - Peripheral instance base addresses */
43483 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
43484   /** Peripheral GPC_CPU_CTRL base address */
43485   #define GPC_CPU_CTRL_BASE                        (0x54470000u)
43486   /** Peripheral GPC_CPU_CTRL base address */
43487   #define GPC_CPU_CTRL_BASE_NS                     (0x44470000u)
43488   /** Peripheral GPC_CPU_CTRL base pointer */
43489   #define GPC_CPU_CTRL                             ((GPC_CPU_CTRL_Type *)GPC_CPU_CTRL_BASE)
43490   /** Peripheral GPC_CPU_CTRL base pointer */
43491   #define GPC_CPU_CTRL_NS                          ((GPC_CPU_CTRL_Type *)GPC_CPU_CTRL_BASE_NS)
43492   /** Array initializer of GPC_CPU_CTRL peripheral base addresses */
43493   #define GPC_CPU_CTRL_BASE_ADDRS                  { GPC_CPU_CTRL_BASE }
43494   /** Array initializer of GPC_CPU_CTRL peripheral base pointers */
43495   #define GPC_CPU_CTRL_BASE_PTRS                   { GPC_CPU_CTRL }
43496   /** Array initializer of GPC_CPU_CTRL peripheral base addresses */
43497   #define GPC_CPU_CTRL_BASE_ADDRS_NS               { GPC_CPU_CTRL_BASE_NS }
43498   /** Array initializer of GPC_CPU_CTRL peripheral base pointers */
43499   #define GPC_CPU_CTRL_BASE_PTRS_NS                { GPC_CPU_CTRL_NS }
43500 #else
43501   /** Peripheral GPC_CPU_CTRL base address */
43502   #define GPC_CPU_CTRL_BASE                        (0x44470000u)
43503   /** Peripheral GPC_CPU_CTRL base pointer */
43504   #define GPC_CPU_CTRL                             ((GPC_CPU_CTRL_Type *)GPC_CPU_CTRL_BASE)
43505   /** Array initializer of GPC_CPU_CTRL peripheral base addresses */
43506   #define GPC_CPU_CTRL_BASE_ADDRS                  { GPC_CPU_CTRL_BASE }
43507   /** Array initializer of GPC_CPU_CTRL peripheral base pointers */
43508   #define GPC_CPU_CTRL_BASE_PTRS                   { GPC_CPU_CTRL }
43509 #endif
43510 
43511 /*!
43512  * @}
43513  */ /* end of group GPC_CPU_CTRL_Peripheral_Access_Layer */
43514 
43515 
43516 /* ----------------------------------------------------------------------------
43517    -- GPC_GLOBAL Peripheral Access Layer
43518    ---------------------------------------------------------------------------- */
43519 
43520 /*!
43521  * @addtogroup GPC_GLOBAL_Peripheral_Access_Layer GPC_GLOBAL Peripheral Access Layer
43522  * @{
43523  */
43524 
43525 /** GPC_GLOBAL - Register Layout Typedef */
43526 typedef struct {
43527        uint8_t RESERVED_0[4];
43528   __IO uint32_t AUTHEN_CTRL;                       /**< GPC Global Authentication Control, offset: 0x4 */
43529        uint8_t RESERVED_1[8];
43530   __IO uint32_t GPC_CPU0_DOMAIN;                   /**< GPC CPU0 domain assignment, offset: 0x10 */
43531   __IO uint32_t GPC_CPU1_DOMAIN;                   /**< GPC CPU1 domain assignment, offset: 0x14 */
43532        uint8_t RESERVED_2[12];
43533   __IO uint32_t GPC_MASTER;                        /**< GPC master CPU configuration, offset: 0x24 */
43534        uint8_t RESERVED_3[472];
43535   __IO uint32_t GPC_ROSC_CTRL;                     /**< RCOSC control, offset: 0x200 */
43536 } GPC_GLOBAL_Type;
43537 
43538 /* ----------------------------------------------------------------------------
43539    -- GPC_GLOBAL Register Masks
43540    ---------------------------------------------------------------------------- */
43541 
43542 /*!
43543  * @addtogroup GPC_GLOBAL_Register_Masks GPC_GLOBAL Register Masks
43544  * @{
43545  */
43546 
43547 /*! @name AUTHEN_CTRL - GPC Global Authentication Control */
43548 /*! @{ */
43549 
43550 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK     (0x80U)
43551 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT    (7U)
43552 /*! LOCK_CFG - Configuration lock
43553  *  0b0..The value of low power configuration fields are not locked.
43554  *  0b1..The value of low power configuration fields are locked. Refer to the function field of each gpc_global registers.
43555  */
43556 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG(x)       (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK)
43557 
43558 #define GPC_GLOBAL_AUTHEN_CTRL_USER_MASK         (0x100U)
43559 #define GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT        (8U)
43560 /*! USER - Allow user mode access
43561  *  0b0..Allow only privilege mode to access CPU mode control registers
43562  *  0b1..Allow both privilege and user mode to access CPU mode control registers
43563  */
43564 #define GPC_GLOBAL_AUTHEN_CTRL_USER(x)           (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_USER_MASK)
43565 
43566 #define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK    (0x200U)
43567 #define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT   (9U)
43568 /*! NONSECURE - Allow non-secure mode access
43569  *  0b0..Allow only secure mode to access CPU mode registers
43570  *  0b1..Allow both secure and non-secure mode to access CPU mode control registers.
43571  */
43572 #define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE(x)      (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK)
43573 
43574 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U)
43575 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U)
43576 /*! LOCK_SETTING - Lock NONSECURE and USER
43577  *  0b0..NONSECURE and USER fields are not locked
43578  *  0b1..NONSECURE and USER fields are locked
43579  */
43580 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING(x)   (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK)
43581 
43582 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK    (0x8000U)
43583 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT   (15U)
43584 /*! LOCK_LIST - White list lock
43585  *  0b0..WHITE_LIST is not locked
43586  *  0b1..WHITE_LIST is locked
43587  */
43588 #define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK)
43589 
43590 #define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK   (0xFFFF0000U)
43591 #define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT  (16U)
43592 /*! WHITE_LIST - Domain ID white list */
43593 #define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK)
43594 /*! @} */
43595 
43596 /*! @name GPC_CPU0_DOMAIN - GPC CPU0 domain assignment */
43597 /*! @{ */
43598 
43599 #define GPC_GLOBAL_GPC_CPU0_DOMAIN_CPU0_DOMAIN_MASK (0xFFFFU)
43600 #define GPC_GLOBAL_GPC_CPU0_DOMAIN_CPU0_DOMAIN_SHIFT (0U)
43601 /*! CPU0_DOMAIN - CPU0 domain assignment */
43602 #define GPC_GLOBAL_GPC_CPU0_DOMAIN_CPU0_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_CPU0_DOMAIN_CPU0_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_CPU0_DOMAIN_CPU0_DOMAIN_MASK)
43603 /*! @} */
43604 
43605 /*! @name GPC_CPU1_DOMAIN - GPC CPU1 domain assignment */
43606 /*! @{ */
43607 
43608 #define GPC_GLOBAL_GPC_CPU1_DOMAIN_CPU1_DOMAIN_MASK (0xFFFFU)
43609 #define GPC_GLOBAL_GPC_CPU1_DOMAIN_CPU1_DOMAIN_SHIFT (0U)
43610 /*! CPU1_DOMAIN - CPU1 domain assignment */
43611 #define GPC_GLOBAL_GPC_CPU1_DOMAIN_CPU1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_CPU1_DOMAIN_CPU1_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_CPU1_DOMAIN_CPU1_DOMAIN_MASK)
43612 /*! @} */
43613 
43614 /*! @name GPC_MASTER - GPC master CPU configuration */
43615 /*! @{ */
43616 
43617 #define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK   (0x1U)
43618 #define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT  (0U)
43619 /*! CPU0_MASTER - Setting to 1 means CPU0 is the master CPU of its domain
43620  *  0b0..CPU0 is not the master CPU of its domain
43621  *  0b1..CPU0 is the master CPU of its domain
43622  */
43623 #define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER(x)     (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK)
43624 
43625 #define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK   (0x2U)
43626 #define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT  (1U)
43627 /*! CPU1_MASTER - Setting to 1 means CPU1 is the master CPU of its domain
43628  *  0b0..CPU1 is not the master CPU of its domain
43629  *  0b1..CPU1 is the master CPU of its domain
43630  */
43631 #define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER(x)     (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK)
43632 /*! @} */
43633 
43634 /*! @name GPC_ROSC_CTRL - RCOSC control */
43635 /*! @{ */
43636 
43637 #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK (0x1U)
43638 #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT (0U)
43639 /*! ROSC_OFF_EN - Shut off the 24 MHz RCOSC clock when system sleep
43640  *  0b0..Keep 24 MHz ROSC clock running during system sleep
43641  *  0b1..Shut off 24 MHz ROSC clock during system sleep
43642  */
43643 #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN(x)  (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT)) & GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK)
43644 /*! @} */
43645 
43646 
43647 /*!
43648  * @}
43649  */ /* end of group GPC_GLOBAL_Register_Masks */
43650 
43651 
43652 /* GPC_GLOBAL - Peripheral instance base addresses */
43653 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
43654   /** Peripheral GPC_GLOBAL base address */
43655   #define GPC_GLOBAL_BASE                          (0x54472000u)
43656   /** Peripheral GPC_GLOBAL base address */
43657   #define GPC_GLOBAL_BASE_NS                       (0x44472000u)
43658   /** Peripheral GPC_GLOBAL base pointer */
43659   #define GPC_GLOBAL                               ((GPC_GLOBAL_Type *)GPC_GLOBAL_BASE)
43660   /** Peripheral GPC_GLOBAL base pointer */
43661   #define GPC_GLOBAL_NS                            ((GPC_GLOBAL_Type *)GPC_GLOBAL_BASE_NS)
43662   /** Array initializer of GPC_GLOBAL peripheral base addresses */
43663   #define GPC_GLOBAL_BASE_ADDRS                    { GPC_GLOBAL_BASE }
43664   /** Array initializer of GPC_GLOBAL peripheral base pointers */
43665   #define GPC_GLOBAL_BASE_PTRS                     { GPC_GLOBAL }
43666   /** Array initializer of GPC_GLOBAL peripheral base addresses */
43667   #define GPC_GLOBAL_BASE_ADDRS_NS                 { GPC_GLOBAL_BASE_NS }
43668   /** Array initializer of GPC_GLOBAL peripheral base pointers */
43669   #define GPC_GLOBAL_BASE_PTRS_NS                  { GPC_GLOBAL_NS }
43670 #else
43671   /** Peripheral GPC_GLOBAL base address */
43672   #define GPC_GLOBAL_BASE                          (0x44472000u)
43673   /** Peripheral GPC_GLOBAL base pointer */
43674   #define GPC_GLOBAL                               ((GPC_GLOBAL_Type *)GPC_GLOBAL_BASE)
43675   /** Array initializer of GPC_GLOBAL peripheral base addresses */
43676   #define GPC_GLOBAL_BASE_ADDRS                    { GPC_GLOBAL_BASE }
43677   /** Array initializer of GPC_GLOBAL peripheral base pointers */
43678   #define GPC_GLOBAL_BASE_PTRS                     { GPC_GLOBAL }
43679 #endif
43680 
43681 /*!
43682  * @}
43683  */ /* end of group GPC_GLOBAL_Peripheral_Access_Layer */
43684 
43685 
43686 /* ----------------------------------------------------------------------------
43687    -- GPC_SYS_SLEEP_CTRL Peripheral Access Layer
43688    ---------------------------------------------------------------------------- */
43689 
43690 /*!
43691  * @addtogroup GPC_SYS_SLEEP_CTRL_Peripheral_Access_Layer GPC_SYS_SLEEP_CTRL Peripheral Access Layer
43692  * @{
43693  */
43694 
43695 /** GPC_SYS_SLEEP_CTRL - Register Layout Typedef */
43696 typedef struct {
43697        uint8_t RESERVED_0[4];
43698   __IO uint32_t SS_AUTHEN_CTRL;                    /**< System Sleep Authentication Control, offset: 0x4 */
43699        uint8_t RESERVED_1[4];
43700   __IO uint32_t SS_MISC;                           /**< System Sleep Misc, offset: 0xC */
43701        uint8_t RESERVED_2[48];
43702   __IO uint32_t PMIC_CTRL;                         /**< PMIC standby control, offset: 0x40 */
43703        uint8_t RESERVED_3[172];
43704   __IO uint32_t SS_STEP0_IN_CTRL;                  /**< System Sleep STEP0 (BIAS) in control, offset: 0xF0 */
43705        uint8_t RESERVED_4[12];
43706   __IO uint32_t SS_STEP1_IN_CTRL;                  /**< System Sleep STEP1 (PLDO) in control, offset: 0x100 */
43707        uint8_t RESERVED_5[12];
43708   __IO uint32_t SS_STEP2_IN_CTRL;                  /**< System Sleep STEP2 (BANDGAP) in control, offset: 0x110 */
43709        uint8_t RESERVED_6[12];
43710   __IO uint32_t SS_STEP3_IN_CTRL;                  /**< System Sleep STEP3 (LDO) in control, offset: 0x120 */
43711        uint8_t RESERVED_7[28];
43712   __IO uint32_t SS_DCDC_IN_CTRL;                   /**< System Sleep DCDC in control, offset: 0x140 */
43713        uint8_t RESERVED_8[12];
43714   __IO uint32_t SS_PMIC_IN_CTRL;                   /**< System Sleep PMIC in control, offset: 0x150 */
43715        uint8_t RESERVED_9[172];
43716   __IO uint32_t SS_PMIC_OUT_CTRL;                  /**< System Sleep PMIC out control, offset: 0x200 */
43717        uint8_t RESERVED_10[12];
43718   __IO uint32_t SS_DCDC_OUT_CTRL;                  /**< System Sleep DCDC out control, offset: 0x210 */
43719        uint8_t RESERVED_11[36];
43720   __IO uint32_t SS_STEP3_OUT_CTRL;                 /**< System Sleep STEP3 (LDO) out control, offset: 0x238 */
43721        uint8_t RESERVED_12[4];
43722   __IO uint32_t SS_STEP2_OUT_CTRL;                 /**< System Sleep STEP2 (BANDGAP) out control, offset: 0x240 */
43723        uint8_t RESERVED_13[12];
43724   __IO uint32_t SS_STEP1_OUT_CTRL;                 /**< System Sleep STEP1 (PLDO) out control, offset: 0x250 */
43725        uint8_t RESERVED_14[12];
43726   __IO uint32_t SS_STEP0_OUT_CTRL;                 /**< System Sleep STEP0 (BIAS) out control, offset: 0x260 */
43727 } GPC_SYS_SLEEP_CTRL_Type;
43728 
43729 /* ----------------------------------------------------------------------------
43730    -- GPC_SYS_SLEEP_CTRL Register Masks
43731    ---------------------------------------------------------------------------- */
43732 
43733 /*!
43734  * @addtogroup GPC_SYS_SLEEP_CTRL_Register_Masks GPC_SYS_SLEEP_CTRL Register Masks
43735  * @{
43736  */
43737 
43738 /*! @name SS_AUTHEN_CTRL - System Sleep Authentication Control */
43739 /*! @{ */
43740 
43741 #define GPC_SYS_SLEEP_CTRL_SS_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
43742 #define GPC_SYS_SLEEP_CTRL_SS_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
43743 /*! LOCK_CFG - Configuration lock
43744  *  0b0..The value of low power configuration fields are not locked.
43745  *  0b1..The value of low power configuration fields are locked. Refer to the function field of each gpc_sys_sleep_ctrl registers.
43746  */
43747 #define GPC_SYS_SLEEP_CTRL_SS_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_AUTHEN_CTRL_LOCK_CFG_MASK)
43748 /*! @} */
43749 
43750 /*! @name SS_MISC - System Sleep Misc */
43751 /*! @{ */
43752 
43753 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU0_SYS_SLEEP_MASK (0x1U)
43754 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU0_SYS_SLEEP_SHIFT (0U)
43755 /*! FORCE_CPU0_SYS_SLEEP - Force CPU0 to request system sleep mode
43756  *  0b0..Do not force CPU0 to request system sleep mode
43757  *  0b1..Force CPU0 to request system sleep mode
43758  */
43759 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU0_SYS_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU0_SYS_SLEEP_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU0_SYS_SLEEP_MASK)
43760 
43761 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU1_SYS_SLEEP_MASK (0x2U)
43762 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU1_SYS_SLEEP_SHIFT (1U)
43763 /*! FORCE_CPU1_SYS_SLEEP - Force CPU1 to request system sleep mode
43764  *  0b0..Do not force CPU1 to request system sleep mode
43765  *  0b1..Force CPU1 to request system sleep mode
43766  */
43767 #define GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU1_SYS_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU1_SYS_SLEEP_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_MISC_FORCE_CPU1_SYS_SLEEP_MASK)
43768 /*! @} */
43769 
43770 /*! @name PMIC_CTRL - PMIC standby control */
43771 /*! @{ */
43772 
43773 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_EN_MASK (0x1U)
43774 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_EN_SHIFT (0U)
43775 /*! PMIC_STBY_EN - Assert the PMIC standby request when system sleep
43776  *  0b0..Do not assert PMIC_STBY_REQ when system sleep is entered
43777  *  0b1..Assert PMIC_STBY_REQ when system sleep is entered
43778  */
43779 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_EN_SHIFT)) & GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_EN_MASK)
43780 
43781 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_MASK (0x2U)
43782 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_SHIFT (1U)
43783 /*! PMIC_READY - PMIC_READY pin status
43784  *  0b0..PMIC_READY not asserted
43785  *  0b1..PMIC_READY asserted
43786  */
43787 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_SHIFT)) & GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_MASK)
43788 
43789 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_EXIST_MASK (0x4U)
43790 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_EXIST_SHIFT (2U)
43791 /*! PMIC_READY_EXIST - PMIC_READY is driven from pad
43792  *  0b0..PMIC_READY is not driven.
43793  *  0b1..PMIC_READY is driven from pad. If PMIC_READY_EXIST = 1, PMIC_READY = 1 means external PMIC drives PMIC_READY pin.
43794  */
43795 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_EXIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_EXIST_SHIFT)) & GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_READY_EXIST_MASK)
43796 
43797 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_SOFT_MASK (0x10U)
43798 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_SOFT_SHIFT (4U)
43799 /*! PMIC_STBY_SOFT - Software PMIC standby trigger
43800  *  0b0..Exit PMIC standby
43801  *  0b1..Trigger PMIC standby
43802  */
43803 #define GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_SOFT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_SOFT_SHIFT)) & GPC_SYS_SLEEP_CTRL_PMIC_CTRL_PMIC_STBY_SOFT_MASK)
43804 /*! @} */
43805 
43806 /*! @name SS_STEP0_IN_CTRL - System Sleep STEP0 (BIAS) in control */
43807 /*! @{ */
43808 
43809 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_IN_CTRL_DISABLE_MASK (0x80000000U)
43810 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_IN_CTRL_DISABLE_SHIFT (31U)
43811 /*! DISABLE - Disable this step
43812  *  0b0..This step is enabled.
43813  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43814  */
43815 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP0_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP0_IN_CTRL_DISABLE_MASK)
43816 /*! @} */
43817 
43818 /*! @name SS_STEP1_IN_CTRL - System Sleep STEP1 (PLDO) in control */
43819 /*! @{ */
43820 
43821 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_IN_CTRL_DISABLE_MASK (0x80000000U)
43822 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_IN_CTRL_DISABLE_SHIFT (31U)
43823 /*! DISABLE - Disable this step
43824  *  0b0..This step is enabled.
43825  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43826  */
43827 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP1_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP1_IN_CTRL_DISABLE_MASK)
43828 /*! @} */
43829 
43830 /*! @name SS_STEP2_IN_CTRL - System Sleep STEP2 (BANDGAP) in control */
43831 /*! @{ */
43832 
43833 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_IN_CTRL_DISABLE_MASK (0x80000000U)
43834 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_IN_CTRL_DISABLE_SHIFT (31U)
43835 /*! DISABLE - Disable this step
43836  *  0b0..This step is enabled.
43837  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43838  */
43839 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP2_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP2_IN_CTRL_DISABLE_MASK)
43840 /*! @} */
43841 
43842 /*! @name SS_STEP3_IN_CTRL - System Sleep STEP3 (LDO) in control */
43843 /*! @{ */
43844 
43845 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_IN_CTRL_DISABLE_MASK (0x80000000U)
43846 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_IN_CTRL_DISABLE_SHIFT (31U)
43847 /*! DISABLE - Disable this step
43848  *  0b0..This step is enabled.
43849  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43850  */
43851 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP3_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP3_IN_CTRL_DISABLE_MASK)
43852 /*! @} */
43853 
43854 /*! @name SS_DCDC_IN_CTRL - System Sleep DCDC in control */
43855 /*! @{ */
43856 
43857 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
43858 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
43859 /*! DISABLE - Disable this step
43860  *  0b0..This step is enabled.
43861  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43862  */
43863 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_DCDC_IN_CTRL_DISABLE_MASK)
43864 /*! @} */
43865 
43866 /*! @name SS_PMIC_IN_CTRL - System Sleep PMIC in control */
43867 /*! @{ */
43868 
43869 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
43870 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
43871 /*! DISABLE - Disable this step
43872  *  0b0..This step is enabled.
43873  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43874  */
43875 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_IN_CTRL_DISABLE_MASK)
43876 /*! @} */
43877 
43878 /*! @name SS_PMIC_OUT_CTRL - System Sleep PMIC out control */
43879 /*! @{ */
43880 
43881 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
43882 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
43883 /*! DISABLE - Disable this step
43884  *  0b0..This step is enabled.
43885  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43886  */
43887 #define GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_PMIC_OUT_CTRL_DISABLE_MASK)
43888 /*! @} */
43889 
43890 /*! @name SS_DCDC_OUT_CTRL - System Sleep DCDC out control */
43891 /*! @{ */
43892 
43893 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
43894 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
43895 /*! DISABLE - Disable this step
43896  *  0b0..This step is enabled.
43897  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43898  */
43899 #define GPC_SYS_SLEEP_CTRL_SS_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_DCDC_OUT_CTRL_DISABLE_MASK)
43900 /*! @} */
43901 
43902 /*! @name SS_STEP3_OUT_CTRL - System Sleep STEP3 (LDO) out control */
43903 /*! @{ */
43904 
43905 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_OUT_CTRL_DISABLE_MASK (0x80000000U)
43906 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_OUT_CTRL_DISABLE_SHIFT (31U)
43907 /*! DISABLE - Disable this step
43908  *  0b0..This step is enabled.
43909  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43910  */
43911 #define GPC_SYS_SLEEP_CTRL_SS_STEP3_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP3_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP3_OUT_CTRL_DISABLE_MASK)
43912 /*! @} */
43913 
43914 /*! @name SS_STEP2_OUT_CTRL - System Sleep STEP2 (BANDGAP) out control */
43915 /*! @{ */
43916 
43917 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_OUT_CTRL_DISABLE_MASK (0x80000000U)
43918 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_OUT_CTRL_DISABLE_SHIFT (31U)
43919 /*! DISABLE - Disable this step
43920  *  0b0..This step is enabled.
43921  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43922  */
43923 #define GPC_SYS_SLEEP_CTRL_SS_STEP2_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP2_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP2_OUT_CTRL_DISABLE_MASK)
43924 /*! @} */
43925 
43926 /*! @name SS_STEP1_OUT_CTRL - System Sleep STEP1 (PLDO) out control */
43927 /*! @{ */
43928 
43929 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_OUT_CTRL_DISABLE_MASK (0x80000000U)
43930 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_OUT_CTRL_DISABLE_SHIFT (31U)
43931 /*! DISABLE - Disable this step
43932  *  0b0..This step is enabled.
43933  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43934  */
43935 #define GPC_SYS_SLEEP_CTRL_SS_STEP1_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP1_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP1_OUT_CTRL_DISABLE_MASK)
43936 /*! @} */
43937 
43938 /*! @name SS_STEP0_OUT_CTRL - System Sleep STEP0 (BIAS) out control */
43939 /*! @{ */
43940 
43941 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_OUT_CTRL_DISABLE_MASK (0x80000000U)
43942 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_OUT_CTRL_DISABLE_SHIFT (31U)
43943 /*! DISABLE - Disable this step
43944  *  0b0..This step is enabled.
43945  *  0b1..This step is disabled. GPC will skip this step and not send any request.
43946  */
43947 #define GPC_SYS_SLEEP_CTRL_SS_STEP0_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SYS_SLEEP_CTRL_SS_STEP0_OUT_CTRL_DISABLE_SHIFT)) & GPC_SYS_SLEEP_CTRL_SS_STEP0_OUT_CTRL_DISABLE_MASK)
43948 /*! @} */
43949 
43950 
43951 /*!
43952  * @}
43953  */ /* end of group GPC_SYS_SLEEP_CTRL_Register_Masks */
43954 
43955 
43956 /* GPC_SYS_SLEEP_CTRL - Peripheral instance base addresses */
43957 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
43958   /** Peripheral GPC_SYS_SLEEP_CTRL base address */
43959   #define GPC_SYS_SLEEP_CTRL_BASE                  (0x54472800u)
43960   /** Peripheral GPC_SYS_SLEEP_CTRL base address */
43961   #define GPC_SYS_SLEEP_CTRL_BASE_NS               (0x44472800u)
43962   /** Peripheral GPC_SYS_SLEEP_CTRL base pointer */
43963   #define GPC_SYS_SLEEP_CTRL                       ((GPC_SYS_SLEEP_CTRL_Type *)GPC_SYS_SLEEP_CTRL_BASE)
43964   /** Peripheral GPC_SYS_SLEEP_CTRL base pointer */
43965   #define GPC_SYS_SLEEP_CTRL_NS                    ((GPC_SYS_SLEEP_CTRL_Type *)GPC_SYS_SLEEP_CTRL_BASE_NS)
43966   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base addresses */
43967   #define GPC_SYS_SLEEP_CTRL_BASE_ADDRS            { GPC_SYS_SLEEP_CTRL_BASE }
43968   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base pointers */
43969   #define GPC_SYS_SLEEP_CTRL_BASE_PTRS             { GPC_SYS_SLEEP_CTRL }
43970   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base addresses */
43971   #define GPC_SYS_SLEEP_CTRL_BASE_ADDRS_NS         { GPC_SYS_SLEEP_CTRL_BASE_NS }
43972   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base pointers */
43973   #define GPC_SYS_SLEEP_CTRL_BASE_PTRS_NS          { GPC_SYS_SLEEP_CTRL_NS }
43974 #else
43975   /** Peripheral GPC_SYS_SLEEP_CTRL base address */
43976   #define GPC_SYS_SLEEP_CTRL_BASE                  (0x44472800u)
43977   /** Peripheral GPC_SYS_SLEEP_CTRL base pointer */
43978   #define GPC_SYS_SLEEP_CTRL                       ((GPC_SYS_SLEEP_CTRL_Type *)GPC_SYS_SLEEP_CTRL_BASE)
43979   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base addresses */
43980   #define GPC_SYS_SLEEP_CTRL_BASE_ADDRS            { GPC_SYS_SLEEP_CTRL_BASE }
43981   /** Array initializer of GPC_SYS_SLEEP_CTRL peripheral base pointers */
43982   #define GPC_SYS_SLEEP_CTRL_BASE_PTRS             { GPC_SYS_SLEEP_CTRL }
43983 #endif
43984 
43985 /*!
43986  * @}
43987  */ /* end of group GPC_SYS_SLEEP_CTRL_Peripheral_Access_Layer */
43988 
43989 
43990 /* ----------------------------------------------------------------------------
43991    -- GPT Peripheral Access Layer
43992    ---------------------------------------------------------------------------- */
43993 
43994 /*!
43995  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
43996  * @{
43997  */
43998 
43999 /** GPT - Register Layout Typedef */
44000 typedef struct {
44001   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
44002   __IO uint32_t PR;                                /**< Prescaler, offset: 0x4 */
44003   __IO uint32_t SR;                                /**< Status, offset: 0x8 */
44004   __IO uint32_t IR;                                /**< Interrupt, offset: 0xC */
44005   __IO uint32_t OCR[3];                            /**< Output Compare, array offset: 0x10, array step: 0x4 */
44006   __I  uint32_t ICR[2];                            /**< Input Capture, array offset: 0x1C, array step: 0x4 */
44007   __I  uint32_t CNT;                               /**< Counter, offset: 0x24 */
44008 } GPT_Type;
44009 
44010 /* ----------------------------------------------------------------------------
44011    -- GPT Register Masks
44012    ---------------------------------------------------------------------------- */
44013 
44014 /*!
44015  * @addtogroup GPT_Register_Masks GPT Register Masks
44016  * @{
44017  */
44018 
44019 /*! @name CR - Control */
44020 /*! @{ */
44021 
44022 #define GPT_CR_EN_MASK                           (0x1U)
44023 #define GPT_CR_EN_SHIFT                          (0U)
44024 /*! EN - GPT Enable
44025  *  0b0..Disable
44026  *  0b1..Enable
44027  */
44028 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
44029 
44030 #define GPT_CR_ENMOD_MASK                        (0x2U)
44031 #define GPT_CR_ENMOD_SHIFT                       (1U)
44032 /*! ENMOD - GPT Enable Mode
44033  *  0b0..Restart counting from frozen values after GPT is enabled (EN=1).
44034  *  0b1..Reset counting from 0 after GPT is enabled (EN=1).
44035  */
44036 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
44037 
44038 #define GPT_CR_DBGEN_MASK                        (0x4U)
44039 #define GPT_CR_DBGEN_SHIFT                       (2U)
44040 /*! DBGEN - GPT Debug Mode Enable
44041  *  0b0..Disable in Debug mode
44042  *  0b1..Enable in Debug mode
44043  */
44044 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
44045 
44046 #define GPT_CR_WAITEN_MASK                       (0x8U)
44047 #define GPT_CR_WAITEN_SHIFT                      (3U)
44048 /*! WAITEN - GPT Wait Mode Enable
44049  *  0b0..Disable in Wait mode
44050  *  0b1..Enable in Wait mode
44051  */
44052 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
44053 
44054 #define GPT_CR_DOZEEN_MASK                       (0x10U)
44055 #define GPT_CR_DOZEEN_SHIFT                      (4U)
44056 /*! DOZEEN - GPT Doze Mode Enable
44057  *  0b0..Disable in Doze mode
44058  *  0b1..Enable in Doze mode
44059  */
44060 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
44061 
44062 #define GPT_CR_STOPEN_MASK                       (0x20U)
44063 #define GPT_CR_STOPEN_SHIFT                      (5U)
44064 /*! STOPEN - GPT Stop Mode Enable
44065  *  0b0..Disable in Stop mode
44066  *  0b1..Enable in Stop mode
44067  */
44068 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
44069 
44070 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
44071 #define GPT_CR_CLKSRC_SHIFT                      (6U)
44072 /*! CLKSRC - Clock Source Select
44073  *  0b000..No clock
44074  *  0b001..Peripheral clock (MODULE_CLK)
44075  *  0b010..High-frequency reference clock (ipg_clk_highfreq)
44076  *  0b011..External clock
44077  *  0b100..Low-frequency reference clock (ipg_clk_32k)
44078  */
44079 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
44080 
44081 #define GPT_CR_FRR_MASK                          (0x200U)
44082 #define GPT_CR_FRR_SHIFT                         (9U)
44083 /*! FRR - Free-Run or Restart Mode
44084  *  0b0..Restart mode. After a compare event, the counter resets to 0000_0000h and resumes counting.
44085  *  0b1..Free-Run mode. After a compare event, the counter continues counting until FFFF_FFFFh and then rolls over to 0.
44086  */
44087 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
44088 
44089 #define GPT_CR_EN_24M_MASK                       (0x400U)
44090 #define GPT_CR_EN_24M_SHIFT                      (10U)
44091 /*! EN_24M - Enable Oscillator Clock Input
44092  *  0b0..Disable
44093  *  0b1..Enable
44094  */
44095 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
44096 
44097 #define GPT_CR_SWR_MASK                          (0x8000U)
44098 #define GPT_CR_SWR_SHIFT                         (15U)
44099 /*! SWR - Software Reset
44100  *  0b0..GPT is not in software reset state
44101  *  0b1..GPT is in software reset state
44102  */
44103 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
44104 
44105 #define GPT_CR_IM1_MASK                          (0x30000U)
44106 #define GPT_CR_IM1_SHIFT                         (16U)
44107 /*! IM1 - Input Capture Operating Mode for Channel 1
44108  *  0b00..Capture disabled
44109  *  0b01..Capture on rising edge only
44110  *  0b10..Capture on falling edge only
44111  *  0b11..Capture on both edges
44112  */
44113 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
44114 
44115 #define GPT_CR_IM2_MASK                          (0xC0000U)
44116 #define GPT_CR_IM2_SHIFT                         (18U)
44117 /*! IM2 - Input Capture Operating Mode for Channel 2
44118  *  0b00..Capture disabled
44119  *  0b01..Capture on rising edge only
44120  *  0b10..Capture on falling edge only
44121  *  0b11..Capture on both edges
44122  */
44123 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
44124 
44125 #define GPT_CR_OM1_MASK                          (0x700000U)
44126 #define GPT_CR_OM1_SHIFT                         (20U)
44127 /*! OM1 - Output Compare Operating Mode for Channel 1
44128  *  0b000..Output disabled. No response on the signal.
44129  *  0b001..Toggle output
44130  *  0b010..Clear output
44131  *  0b011..Set output
44132  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output signal. When OMn is first
44133  *         programmed as 1xx, the output is set to one immediately on the next input clock (if it was not already). The
44134  *         input clock here refers to the clock selected by the CLKSRC field of this register.
44135  */
44136 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
44137 
44138 #define GPT_CR_OM2_MASK                          (0x3800000U)
44139 #define GPT_CR_OM2_SHIFT                         (23U)
44140 /*! OM2 - Output Compare Operating Mode for Channel 2
44141  *  0b000..Output disabled. No response on the signal.
44142  *  0b001..Toggle output
44143  *  0b010..Clear output
44144  *  0b011..Set output
44145  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output signal. When OMn is first
44146  *         programmed as 1xx, the output is set to one immediately on the next input clock (if it was not already). The
44147  *         input clock here refers to the clock selected by the CLKSRC field of this register.
44148  */
44149 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
44150 
44151 #define GPT_CR_OM3_MASK                          (0x1C000000U)
44152 #define GPT_CR_OM3_SHIFT                         (26U)
44153 /*! OM3 - Output Compare Operating Mode for Channel 3
44154  *  0b000..Output disabled. No response on the signal.
44155  *  0b001..Toggle output
44156  *  0b010..Clear output
44157  *  0b011..Set output
44158  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output signal. When OMn is first
44159  *         programmed as 1xx, the output is set to one immediately on the next input clock (if it was not already). The
44160  *         input clock here refers to the clock selected by the CLKSRC field of this register.
44161  */
44162 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
44163 
44164 #define GPT_CR_FO1_MASK                          (0x20000000U)
44165 #define GPT_CR_FO1_SHIFT                         (29U)
44166 /*! FO1 - Force Output Compare for Channel 1
44167  *  0b0..No effect
44168  *  0b1..Trigger the programmed response on the output signal
44169  */
44170 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
44171 
44172 #define GPT_CR_FO2_MASK                          (0x40000000U)
44173 #define GPT_CR_FO2_SHIFT                         (30U)
44174 /*! FO2 - Force Output Compare for Channel 2
44175  *  0b0..No effect
44176  *  0b1..Trigger the programmed response on the output signal
44177  */
44178 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
44179 
44180 #define GPT_CR_FO3_MASK                          (0x80000000U)
44181 #define GPT_CR_FO3_SHIFT                         (31U)
44182 /*! FO3 - Force Output Compare for Channel 3
44183  *  0b0..No effect
44184  *  0b1..Trigger the programmed response on the output signal
44185  */
44186 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
44187 /*! @} */
44188 
44189 /*! @name PR - Prescaler */
44190 /*! @{ */
44191 
44192 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
44193 #define GPT_PR_PRESCALER_SHIFT                   (0U)
44194 /*! PRESCALER - Prescaler Divide Value
44195  *  0b000000000000..Divide by 1
44196  *  0b000000000001..Divide by 2
44197  *  0b111111111111..Divide by 4096
44198  */
44199 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
44200 
44201 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
44202 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
44203 /*! PRESCALER24M - Prescaler Divide Value for the Oscillator Clock
44204  *  0b0000..Divide by 1
44205  *  0b0001..Divide by 2
44206  *  0b1111..Divide by 16
44207  */
44208 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
44209 /*! @} */
44210 
44211 /*! @name SR - Status */
44212 /*! @{ */
44213 
44214 #define GPT_SR_OF1_MASK                          (0x1U)
44215 #define GPT_SR_OF1_SHIFT                         (0U)
44216 /*! OF1 - Output Compare Flag for Channel 1
44217  *  0b0..Compare event has not occurred.
44218  *  0b1..Compare event has occurred.
44219  */
44220 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
44221 
44222 #define GPT_SR_OF2_MASK                          (0x2U)
44223 #define GPT_SR_OF2_SHIFT                         (1U)
44224 /*! OF2 - Output Compare Flag for Channel 2
44225  *  0b0..Compare event has not occurred.
44226  *  0b1..Compare event has occurred.
44227  */
44228 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
44229 
44230 #define GPT_SR_OF3_MASK                          (0x4U)
44231 #define GPT_SR_OF3_SHIFT                         (2U)
44232 /*! OF3 - Output Compare Flag for Channel 3
44233  *  0b0..Compare event has not occurred.
44234  *  0b1..Compare event has occurred.
44235  */
44236 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
44237 
44238 #define GPT_SR_IF1_MASK                          (0x8U)
44239 #define GPT_SR_IF1_SHIFT                         (3U)
44240 /*! IF1 - Input Capture Flag for Channel 1
44241  *  0b0..Capture event has not occurred.
44242  *  0b1..Capture event has occurred.
44243  */
44244 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
44245 
44246 #define GPT_SR_IF2_MASK                          (0x10U)
44247 #define GPT_SR_IF2_SHIFT                         (4U)
44248 /*! IF2 - Input Capture Flag for Channel 2
44249  *  0b0..Capture event has not occurred.
44250  *  0b1..Capture event has occurred.
44251  */
44252 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
44253 
44254 #define GPT_SR_ROV_MASK                          (0x20U)
44255 #define GPT_SR_ROV_SHIFT                         (5U)
44256 /*! ROV - Rollover Flag
44257  *  0b0..Rollover has not occurred.
44258  *  0b1..Rollover has occurred.
44259  */
44260 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
44261 /*! @} */
44262 
44263 /*! @name IR - Interrupt */
44264 /*! @{ */
44265 
44266 #define GPT_IR_OF1IE_MASK                        (0x1U)
44267 #define GPT_IR_OF1IE_SHIFT                       (0U)
44268 /*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable
44269  *  0b0..Disable
44270  *  0b1..Enable
44271  */
44272 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
44273 
44274 #define GPT_IR_OF2IE_MASK                        (0x2U)
44275 #define GPT_IR_OF2IE_SHIFT                       (1U)
44276 /*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable
44277  *  0b0..Disable
44278  *  0b1..Enable
44279  */
44280 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
44281 
44282 #define GPT_IR_OF3IE_MASK                        (0x4U)
44283 #define GPT_IR_OF3IE_SHIFT                       (2U)
44284 /*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable
44285  *  0b0..Disable
44286  *  0b1..Enable
44287  */
44288 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
44289 
44290 #define GPT_IR_IF1IE_MASK                        (0x8U)
44291 #define GPT_IR_IF1IE_SHIFT                       (3U)
44292 /*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable
44293  *  0b0..Disable
44294  *  0b1..Enable
44295  */
44296 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
44297 
44298 #define GPT_IR_IF2IE_MASK                        (0x10U)
44299 #define GPT_IR_IF2IE_SHIFT                       (4U)
44300 /*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable
44301  *  0b0..Disable
44302  *  0b1..Enable
44303  */
44304 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
44305 
44306 #define GPT_IR_ROVIE_MASK                        (0x20U)
44307 #define GPT_IR_ROVIE_SHIFT                       (5U)
44308 /*! ROVIE - Rollover Interrupt Enable
44309  *  0b0..Disable
44310  *  0b1..Enable
44311  */
44312 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
44313 /*! @} */
44314 
44315 /*! @name OCR - Output Compare */
44316 /*! @{ */
44317 
44318 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
44319 #define GPT_OCR_COMP_SHIFT                       (0U)
44320 /*! COMP - Compare Value */
44321 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
44322 /*! @} */
44323 
44324 /* The count of GPT_OCR */
44325 #define GPT_OCR_COUNT                            (3U)
44326 
44327 /*! @name ICR - Input Capture */
44328 /*! @{ */
44329 
44330 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
44331 #define GPT_ICR_CAPT_SHIFT                       (0U)
44332 /*! CAPT - Capture Value */
44333 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
44334 /*! @} */
44335 
44336 /* The count of GPT_ICR */
44337 #define GPT_ICR_COUNT                            (2U)
44338 
44339 /*! @name CNT - Counter */
44340 /*! @{ */
44341 
44342 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
44343 #define GPT_CNT_COUNT_SHIFT                      (0U)
44344 /*! COUNT - Counter Value */
44345 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
44346 /*! @} */
44347 
44348 
44349 /*!
44350  * @}
44351  */ /* end of group GPT_Register_Masks */
44352 
44353 
44354 /* GPT - Peripheral instance base addresses */
44355 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
44356   /** Peripheral GPT1 base address */
44357   #define GPT1_BASE                                (0x546C0000u)
44358   /** Peripheral GPT1 base address */
44359   #define GPT1_BASE_NS                             (0x446C0000u)
44360   /** Peripheral GPT1 base pointer */
44361   #define GPT1                                     ((GPT_Type *)GPT1_BASE)
44362   /** Peripheral GPT1 base pointer */
44363   #define GPT1_NS                                  ((GPT_Type *)GPT1_BASE_NS)
44364   /** Peripheral GPT2 base address */
44365   #define GPT2_BASE                                (0x52EC0000u)
44366   /** Peripheral GPT2 base address */
44367   #define GPT2_BASE_NS                             (0x42EC0000u)
44368   /** Peripheral GPT2 base pointer */
44369   #define GPT2                                     ((GPT_Type *)GPT2_BASE)
44370   /** Peripheral GPT2 base pointer */
44371   #define GPT2_NS                                  ((GPT_Type *)GPT2_BASE_NS)
44372   /** Array initializer of GPT peripheral base addresses */
44373   #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE }
44374   /** Array initializer of GPT peripheral base pointers */
44375   #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2 }
44376   /** Array initializer of GPT peripheral base addresses */
44377   #define GPT_BASE_ADDRS_NS                        { 0u, GPT1_BASE_NS, GPT2_BASE_NS }
44378   /** Array initializer of GPT peripheral base pointers */
44379   #define GPT_BASE_PTRS_NS                         { (GPT_Type *)0u, GPT1_NS, GPT2_NS }
44380 #else
44381   /** Peripheral GPT1 base address */
44382   #define GPT1_BASE                                (0x446C0000u)
44383   /** Peripheral GPT1 base pointer */
44384   #define GPT1                                     ((GPT_Type *)GPT1_BASE)
44385   /** Peripheral GPT2 base address */
44386   #define GPT2_BASE                                (0x42EC0000u)
44387   /** Peripheral GPT2 base pointer */
44388   #define GPT2                                     ((GPT_Type *)GPT2_BASE)
44389   /** Array initializer of GPT peripheral base addresses */
44390   #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE }
44391   /** Array initializer of GPT peripheral base pointers */
44392   #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2 }
44393 #endif
44394 /** Interrupt vectors for the GPT peripheral type */
44395 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
44396 
44397 /*!
44398  * @}
44399  */ /* end of group GPT_Peripheral_Access_Layer */
44400 
44401 
44402 /* ----------------------------------------------------------------------------
44403    -- I2S Peripheral Access Layer
44404    ---------------------------------------------------------------------------- */
44405 
44406 /*!
44407  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
44408  * @{
44409  */
44410 
44411 /** I2S - Register Layout Typedef */
44412 typedef struct {
44413   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
44414   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
44415   __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
44416   __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
44417   __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
44418   __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
44419   __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
44420   __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
44421   __O  uint32_t TDR[4];                            /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */
44422        uint8_t RESERVED_0[16];
44423   __I  uint32_t TFR[4];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */
44424        uint8_t RESERVED_1[16];
44425   __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
44426        uint8_t RESERVED_2[36];
44427   __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
44428   __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
44429   __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
44430   __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
44431   __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
44432   __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
44433   __I  uint32_t RDR[4];                            /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */
44434        uint8_t RESERVED_3[16];
44435   __I  uint32_t RFR[4];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */
44436        uint8_t RESERVED_4[16];
44437   __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
44438 } I2S_Type;
44439 
44440 /* ----------------------------------------------------------------------------
44441    -- I2S Register Masks
44442    ---------------------------------------------------------------------------- */
44443 
44444 /*!
44445  * @addtogroup I2S_Register_Masks I2S Register Masks
44446  * @{
44447  */
44448 
44449 /*! @name VERID - Version ID */
44450 /*! @{ */
44451 
44452 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
44453 #define I2S_VERID_FEATURE_SHIFT                  (0U)
44454 /*! FEATURE - Feature Specification Number
44455  *  0b0000000000000000..Standard feature set.
44456  */
44457 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
44458 
44459 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
44460 #define I2S_VERID_MINOR_SHIFT                    (16U)
44461 /*! MINOR - Minor Version Number */
44462 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
44463 
44464 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
44465 #define I2S_VERID_MAJOR_SHIFT                    (24U)
44466 /*! MAJOR - Major Version Number */
44467 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
44468 /*! @} */
44469 
44470 /*! @name PARAM - Parameter */
44471 /*! @{ */
44472 
44473 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
44474 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
44475 /*! DATALINE - Number of Datalinks */
44476 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
44477 
44478 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
44479 #define I2S_PARAM_FIFO_SHIFT                     (8U)
44480 /*! FIFO - FIFO Size */
44481 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
44482 
44483 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
44484 #define I2S_PARAM_FRAME_SHIFT                    (16U)
44485 /*! FRAME - Frame Size */
44486 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
44487 /*! @} */
44488 
44489 /*! @name TCSR - Transmit Control */
44490 /*! @{ */
44491 
44492 #define I2S_TCSR_FRDE_MASK                       (0x1U)
44493 #define I2S_TCSR_FRDE_SHIFT                      (0U)
44494 /*! FRDE - FIFO Request DMA Enable
44495  *  0b0..Disables the DMA request.
44496  *  0b1..Enables the DMA request.
44497  */
44498 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
44499 
44500 #define I2S_TCSR_FWDE_MASK                       (0x2U)
44501 #define I2S_TCSR_FWDE_SHIFT                      (1U)
44502 /*! FWDE - FIFO Warning DMA Enable
44503  *  0b0..Disables the DMA warning.
44504  *  0b1..Enables the DMA warning.
44505  */
44506 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
44507 
44508 #define I2S_TCSR_FRIE_MASK                       (0x100U)
44509 #define I2S_TCSR_FRIE_SHIFT                      (8U)
44510 /*! FRIE - FIFO Request Interrupt Enable
44511  *  0b0..Disables the interrupt.
44512  *  0b1..Enables the interrupt.
44513  */
44514 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
44515 
44516 #define I2S_TCSR_FWIE_MASK                       (0x200U)
44517 #define I2S_TCSR_FWIE_SHIFT                      (9U)
44518 /*! FWIE - FIFO Warning Interrupt Enable
44519  *  0b0..Disables the interrupt.
44520  *  0b1..Enables the interrupt.
44521  */
44522 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
44523 
44524 #define I2S_TCSR_FEIE_MASK                       (0x400U)
44525 #define I2S_TCSR_FEIE_SHIFT                      (10U)
44526 /*! FEIE - FIFO Error Interrupt Enable
44527  *  0b0..Disables the interrupt.
44528  *  0b1..Enables the interrupt.
44529  */
44530 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
44531 
44532 #define I2S_TCSR_SEIE_MASK                       (0x800U)
44533 #define I2S_TCSR_SEIE_SHIFT                      (11U)
44534 /*! SEIE - Sync Error Interrupt Enable
44535  *  0b0..Disables interrupt.
44536  *  0b1..Enables interrupt.
44537  */
44538 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
44539 
44540 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
44541 #define I2S_TCSR_WSIE_SHIFT                      (12U)
44542 /*! WSIE - Word Start Interrupt Enable
44543  *  0b0..Disables interrupt.
44544  *  0b1..Enables interrupt.
44545  */
44546 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
44547 
44548 #define I2S_TCSR_FRF_MASK                        (0x10000U)
44549 #define I2S_TCSR_FRF_SHIFT                       (16U)
44550 /*! FRF - FIFO Request Flag
44551  *  0b0..Transmit FIFO watermark has not been reached.
44552  *  0b1..Transmit FIFO watermark has been reached.
44553  */
44554 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
44555 
44556 #define I2S_TCSR_FWF_MASK                        (0x20000U)
44557 #define I2S_TCSR_FWF_SHIFT                       (17U)
44558 /*! FWF - FIFO Warning Flag
44559  *  0b0..No enabled transmit FIFO is empty.
44560  *  0b1..Enabled transmit FIFO is empty.
44561  */
44562 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
44563 
44564 #define I2S_TCSR_FEF_MASK                        (0x40000U)
44565 #define I2S_TCSR_FEF_SHIFT                       (18U)
44566 /*! FEF - FIFO Error Flag
44567  *  0b0..Transmit underrun not detected.
44568  *  0b1..Transmit underrun detected.
44569  */
44570 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
44571 
44572 #define I2S_TCSR_SEF_MASK                        (0x80000U)
44573 #define I2S_TCSR_SEF_SHIFT                       (19U)
44574 /*! SEF - Sync Error Flag
44575  *  0b0..Sync error not detected.
44576  *  0b1..Frame sync error detected.
44577  */
44578 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
44579 
44580 #define I2S_TCSR_WSF_MASK                        (0x100000U)
44581 #define I2S_TCSR_WSF_SHIFT                       (20U)
44582 /*! WSF - Word Start Flag
44583  *  0b0..Start of word not detected.
44584  *  0b1..Start of word detected.
44585  */
44586 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
44587 
44588 #define I2S_TCSR_SR_MASK                         (0x1000000U)
44589 #define I2S_TCSR_SR_SHIFT                        (24U)
44590 /*! SR - Software Reset
44591  *  0b0..No effect
44592  *  0b1..Software reset
44593  */
44594 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
44595 
44596 #define I2S_TCSR_FR_MASK                         (0x2000000U)
44597 #define I2S_TCSR_FR_SHIFT                        (25U)
44598 /*! FR - FIFO Reset
44599  *  0b0..No effect.
44600  *  0b1..FIFO reset.
44601  */
44602 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
44603 
44604 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
44605 #define I2S_TCSR_BCE_SHIFT                       (28U)
44606 /*! BCE - Bit Clock Enable
44607  *  0b0..Transmit bit clock is disabled.
44608  *  0b1..Transmit bit clock is enabled.
44609  */
44610 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
44611 
44612 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
44613 #define I2S_TCSR_DBGE_SHIFT                      (29U)
44614 /*! DBGE - Debug Enable
44615  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
44616  *  0b1..Transmitter is enabled in Debug mode.
44617  */
44618 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
44619 
44620 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
44621 #define I2S_TCSR_STOPE_SHIFT                     (30U)
44622 /*! STOPE - Stop Enable
44623  *  0b0..Transmitter disabled in Stop mode.
44624  *  0b1..Transmitter enabled in Stop mode.
44625  */
44626 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
44627 
44628 #define I2S_TCSR_TE_MASK                         (0x80000000U)
44629 #define I2S_TCSR_TE_SHIFT                        (31U)
44630 /*! TE - Transmitter Enable
44631  *  0b0..Transmitter is disabled.
44632  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
44633  */
44634 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
44635 /*! @} */
44636 
44637 /*! @name TCR1 - Transmit Configuration 1 */
44638 /*! @{ */
44639 
44640 #define I2S_TCR1_TFW_MASK                        (0x1FU)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
44641 #define I2S_TCR1_TFW_SHIFT                       (0U)
44642 /*! TFW - Transmit FIFO Watermark
44643  *  0b00000..1 FIFO word
44644  *  0b00001..2 FIFO words
44645  *  0b00010-0b11110..(TFW +1) FIFO words
44646  *  0b11111..32 FIFO words
44647  */
44648 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
44649 /*! @} */
44650 
44651 /*! @name TCR2 - Transmit Configuration 2 */
44652 /*! @{ */
44653 
44654 #define I2S_TCR2_DIV_MASK                        (0xFFU)
44655 #define I2S_TCR2_DIV_SHIFT                       (0U)
44656 /*! DIV - Bit Clock Divide */
44657 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
44658 
44659 #define I2S_TCR2_BYP_MASK                        (0x800000U)
44660 #define I2S_TCR2_BYP_SHIFT                       (23U)
44661 /*! BYP - Bit Clock Bypass
44662  *  0b0..Internal bit clock is generated from bit clock divider.
44663  *  0b1..Internal bit clock is divide-by-one of the audio master clock.
44664  */
44665 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
44666 
44667 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
44668 #define I2S_TCR2_BCD_SHIFT                       (24U)
44669 /*! BCD - Bit Clock Direction
44670  *  0b0..Bit clock is generated externally in Slave mode.
44671  *  0b1..Bit clock is generated internally in Master mode.
44672  */
44673 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
44674 
44675 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
44676 #define I2S_TCR2_BCP_SHIFT                       (25U)
44677 /*! BCP - Bit Clock Polarity
44678  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
44679  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
44680  */
44681 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
44682 
44683 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
44684 #define I2S_TCR2_MSEL_SHIFT                      (26U)
44685 /*! MSEL - MCLK Select
44686  *  0b00..Bus Clock selected.
44687  *  0b01..Master Clock (MCLK) 1 option selected.
44688  *  0b10..Master Clock (MCLK) 2 option selected.
44689  *  0b11..Master Clock (MCLK) 3 option selected.
44690  */
44691 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
44692 
44693 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
44694 #define I2S_TCR2_BCI_SHIFT                       (28U)
44695 /*! BCI - Bit Clock Input
44696  *  0b0..No effect.
44697  *  0b1..Internal logic is clocked as if bit clock was externally generated.
44698  */
44699 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
44700 
44701 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
44702 #define I2S_TCR2_BCS_SHIFT                       (29U)
44703 /*! BCS - Bit Clock Swap
44704  *  0b0..Use the normal bit clock source.
44705  *  0b1..Swap the bit clock source.
44706  */
44707 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
44708 
44709 #define I2S_TCR2_SYNC_MASK                       (0x40000000U)
44710 #define I2S_TCR2_SYNC_SHIFT                      (30U)
44711 /*! SYNC - Synchronous Mode
44712  *  0b0..Asynchronous mode
44713  *  0b1..Synchronous with receiver
44714  */
44715 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
44716 /*! @} */
44717 
44718 /*! @name TCR3 - Transmit Configuration 3 */
44719 /*! @{ */
44720 
44721 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
44722 #define I2S_TCR3_WDFL_SHIFT                      (0U)
44723 /*! WDFL - Word Flag Configuration */
44724 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
44725 
44726 #define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 2, 4), largest definition used */
44727 #define I2S_TCR3_TCE_SHIFT                       (16U)
44728 /*! TCE - Transmit Channel Enable */
44729 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 4), largest definition used */
44730 
44731 #define I2S_TCR3_CFR_MASK                        (0xF000000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
44732 #define I2S_TCR3_CFR_SHIFT                       (24U)
44733 /*! CFR - Channel FIFO Reset */
44734 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
44735 /*! @} */
44736 
44737 /*! @name TCR4 - Transmit Configuration 4 */
44738 /*! @{ */
44739 
44740 #define I2S_TCR4_FSD_MASK                        (0x1U)
44741 #define I2S_TCR4_FSD_SHIFT                       (0U)
44742 /*! FSD - Frame Sync Direction
44743  *  0b0..Frame sync is generated externally in Slave mode.
44744  *  0b1..Frame sync is generated internally in Master mode.
44745  */
44746 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
44747 
44748 #define I2S_TCR4_FSP_MASK                        (0x2U)
44749 #define I2S_TCR4_FSP_SHIFT                       (1U)
44750 /*! FSP - Frame Sync Polarity
44751  *  0b0..Frame sync is active high.
44752  *  0b1..Frame sync is active low.
44753  */
44754 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
44755 
44756 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
44757 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
44758 /*! ONDEM - On Demand Mode
44759  *  0b0..Internal frame sync is generated continuously.
44760  *  0b1..Internal frame sync is generated when the FIFO warning flag is 0.
44761  */
44762 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
44763 
44764 #define I2S_TCR4_FSE_MASK                        (0x8U)
44765 #define I2S_TCR4_FSE_SHIFT                       (3U)
44766 /*! FSE - Frame Sync Early
44767  *  0b0..Frame sync asserts with the first bit of the frame.
44768  *  0b1..Frame sync asserts one bit before the first bit of the frame.
44769  */
44770 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
44771 
44772 #define I2S_TCR4_MF_MASK                         (0x10U)
44773 #define I2S_TCR4_MF_SHIFT                        (4U)
44774 /*! MF - MSB First
44775  *  0b0..LSB is transmitted first.
44776  *  0b1..MSB is transmitted first.
44777  */
44778 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
44779 
44780 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
44781 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
44782 /*! CHMOD - Channel Mode
44783  *  0b0..TDM mode, transmit data pins are 3-stated when slots are masked or channels are disabled.
44784  *  0b1..Output mode, transmit data pins are never 3-stated and output zero when slots are masked or channels are disabled.
44785  */
44786 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
44787 
44788 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
44789 #define I2S_TCR4_SYWD_SHIFT                      (8U)
44790 /*! SYWD - Sync Width */
44791 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
44792 
44793 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
44794 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
44795 /*! FRSZ - Frame size */
44796 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
44797 
44798 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
44799 #define I2S_TCR4_FPACK_SHIFT                     (24U)
44800 /*! FPACK - FIFO Packing Mode
44801  *  0b00..FIFO packing is disabled.
44802  *  0b01..Reserved
44803  *  0b10..8-bit FIFO packing is enabled.
44804  *  0b11..16-bit FIFO packing is enabled.
44805  */
44806 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
44807 
44808 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
44809 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
44810 /*! FCOMB - FIFO Combine Mode
44811  *  0b00..FIFO Combine mode disabled.
44812  *  0b01..FIFO Combine mode enabled on FIFO reads (from transmit shift registers).
44813  *  0b10..FIFO Combine mode enabled on FIFO writes (by software).
44814  *  0b11..FIFO Combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
44815  */
44816 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
44817 
44818 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
44819 #define I2S_TCR4_FCONT_SHIFT                     (28U)
44820 /*! FCONT - FIFO Continue on Error
44821  *  0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag has been cleared.
44822  *  0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0.
44823  */
44824 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
44825 /*! @} */
44826 
44827 /*! @name TCR5 - Transmit Configuration 5 */
44828 /*! @{ */
44829 
44830 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
44831 #define I2S_TCR5_FBT_SHIFT                       (8U)
44832 /*! FBT - First Bit Shifted
44833  *  0b00000..Bit index is 0.
44834  *  0b00001-0b11110..Bit index is FBT value.
44835  *  0b11111..Bit index is 31.
44836  */
44837 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
44838 
44839 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
44840 #define I2S_TCR5_W0W_SHIFT                       (16U)
44841 /*! W0W - Word 0 Width
44842  *  0b00111..8 bits per word
44843  *  0b01000..9 bits per word
44844  *  0b01001-0b11110..(W0W value + 1) bits per word
44845  *  0b11111..32 bits per word
44846  */
44847 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
44848 
44849 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
44850 #define I2S_TCR5_WNW_SHIFT                       (24U)
44851 /*! WNW - Word N Width
44852  *  0b00111..8 bits per word
44853  *  0b01000..9 bits per word
44854  *  0b01001-0b11110..(WNW value + 1) bits per word
44855  *  0b11111..32 bits per word
44856  */
44857 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
44858 /*! @} */
44859 
44860 /*! @name TDR - Transmit Data */
44861 /*! @{ */
44862 
44863 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
44864 #define I2S_TDR_TDR_SHIFT                        (0U)
44865 /*! TDR - Transmit Data Register */
44866 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
44867 /*! @} */
44868 
44869 /* The count of I2S_TDR */
44870 #define I2S_TDR_COUNT                            (4U)
44871 
44872 /*! @name TFR - Transmit FIFO */
44873 /*! @{ */
44874 
44875 #define I2S_TFR_RFP_MASK                         (0x3FU)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
44876 #define I2S_TFR_RFP_SHIFT                        (0U)
44877 /*! RFP - Read FIFO Pointer */
44878 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
44879 
44880 #define I2S_TFR_WFP_MASK                         (0x3F0000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
44881 #define I2S_TFR_WFP_SHIFT                        (16U)
44882 /*! WFP - Write FIFO Pointer */
44883 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
44884 
44885 #define I2S_TFR_WCP_MASK                         (0x80000000U)
44886 #define I2S_TFR_WCP_SHIFT                        (31U)
44887 /*! WCP - Write Channel Pointer
44888  *  0b0..No effect
44889  *  0b1..FIFO Combine mode is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
44890  */
44891 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
44892 /*! @} */
44893 
44894 /* The count of I2S_TFR */
44895 #define I2S_TFR_COUNT                            (4U)
44896 
44897 /*! @name TMR - Transmit Mask */
44898 /*! @{ */
44899 
44900 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
44901 #define I2S_TMR_TWM_SHIFT                        (0U)
44902 /*! TWM - Transmit Word Mask
44903  *  0b00000000000000000000000000000000..Word N is enabled.
44904  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are 3-stated or drive zero when masked.
44905  */
44906 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
44907 /*! @} */
44908 
44909 /*! @name RCSR - Receive Control */
44910 /*! @{ */
44911 
44912 #define I2S_RCSR_FRDE_MASK                       (0x1U)
44913 #define I2S_RCSR_FRDE_SHIFT                      (0U)
44914 /*! FRDE - FIFO Request DMA Enable
44915  *  0b0..Disables the DMA request.
44916  *  0b1..Enables the DMA request.
44917  */
44918 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
44919 
44920 #define I2S_RCSR_FWDE_MASK                       (0x2U)
44921 #define I2S_RCSR_FWDE_SHIFT                      (1U)
44922 /*! FWDE - FIFO Warning DMA Enable
44923  *  0b0..Disables DMA warnings.
44924  *  0b1..Enables DMA warnings.
44925  */
44926 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
44927 
44928 #define I2S_RCSR_FRIE_MASK                       (0x100U)
44929 #define I2S_RCSR_FRIE_SHIFT                      (8U)
44930 /*! FRIE - FIFO Request Interrupt Enable
44931  *  0b0..Disables the interrupt.
44932  *  0b1..Enables the interrupt.
44933  */
44934 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
44935 
44936 #define I2S_RCSR_FWIE_MASK                       (0x200U)
44937 #define I2S_RCSR_FWIE_SHIFT                      (9U)
44938 /*! FWIE - FIFO Warning Interrupt Enable
44939  *  0b0..Disables the interrupt.
44940  *  0b1..Enables the interrupt.
44941  */
44942 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
44943 
44944 #define I2S_RCSR_FEIE_MASK                       (0x400U)
44945 #define I2S_RCSR_FEIE_SHIFT                      (10U)
44946 /*! FEIE - FIFO Error Interrupt Enable
44947  *  0b0..Disables the interrupt.
44948  *  0b1..Enables the interrupt.
44949  */
44950 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
44951 
44952 #define I2S_RCSR_SEIE_MASK                       (0x800U)
44953 #define I2S_RCSR_SEIE_SHIFT                      (11U)
44954 /*! SEIE - Sync Error Interrupt Enable
44955  *  0b0..Disables interrupt.
44956  *  0b1..Enables interrupt.
44957  */
44958 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
44959 
44960 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
44961 #define I2S_RCSR_WSIE_SHIFT                      (12U)
44962 /*! WSIE - Word Start Interrupt Enable
44963  *  0b0..Disables interrupt.
44964  *  0b1..Enables interrupt.
44965  */
44966 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
44967 
44968 #define I2S_RCSR_FRF_MASK                        (0x10000U)
44969 #define I2S_RCSR_FRF_SHIFT                       (16U)
44970 /*! FRF - FIFO Request Flag
44971  *  0b0..Receive FIFO watermark not reached.
44972  *  0b1..Receive FIFO watermark has been reached.
44973  */
44974 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
44975 
44976 #define I2S_RCSR_FWF_MASK                        (0x20000U)
44977 #define I2S_RCSR_FWF_SHIFT                       (17U)
44978 /*! FWF - FIFO Warning Flag
44979  *  0b0..No enabled receive FIFO is full.
44980  *  0b1..Enabled receive FIFO is full.
44981  */
44982 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
44983 
44984 #define I2S_RCSR_FEF_MASK                        (0x40000U)
44985 #define I2S_RCSR_FEF_SHIFT                       (18U)
44986 /*! FEF - FIFO Error Flag
44987  *  0b0..Receive overflow not detected.
44988  *  0b1..Receive overflow detected.
44989  */
44990 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
44991 
44992 #define I2S_RCSR_SEF_MASK                        (0x80000U)
44993 #define I2S_RCSR_SEF_SHIFT                       (19U)
44994 /*! SEF - Sync Error Flag
44995  *  0b0..Sync error not detected.
44996  *  0b1..Frame sync error detected.
44997  */
44998 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
44999 
45000 #define I2S_RCSR_WSF_MASK                        (0x100000U)
45001 #define I2S_RCSR_WSF_SHIFT                       (20U)
45002 /*! WSF - Word Start Flag
45003  *  0b0..Start of word not detected.
45004  *  0b1..Start of word detected.
45005  */
45006 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
45007 
45008 #define I2S_RCSR_SR_MASK                         (0x1000000U)
45009 #define I2S_RCSR_SR_SHIFT                        (24U)
45010 /*! SR - Software Reset
45011  *  0b0..No effect.
45012  *  0b1..Software reset.
45013  */
45014 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
45015 
45016 #define I2S_RCSR_FR_MASK                         (0x2000000U)
45017 #define I2S_RCSR_FR_SHIFT                        (25U)
45018 /*! FR - FIFO Reset
45019  *  0b0..No effect.
45020  *  0b1..FIFO reset.
45021  */
45022 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
45023 
45024 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
45025 #define I2S_RCSR_BCE_SHIFT                       (28U)
45026 /*! BCE - Bit Clock Enable
45027  *  0b0..Receive bit clock is disabled.
45028  *  0b1..Receive bit clock is enabled.
45029  */
45030 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
45031 
45032 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
45033 #define I2S_RCSR_DBGE_SHIFT                      (29U)
45034 /*! DBGE - Debug Enable
45035  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
45036  *  0b1..Receiver is enabled in Debug mode.
45037  */
45038 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
45039 
45040 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
45041 #define I2S_RCSR_STOPE_SHIFT                     (30U)
45042 /*! STOPE - Stop Enable
45043  *  0b0..Receiver disabled in Stop mode.
45044  *  0b1..Receiver enabled in Stop mode.
45045  */
45046 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
45047 
45048 #define I2S_RCSR_RE_MASK                         (0x80000000U)
45049 #define I2S_RCSR_RE_SHIFT                        (31U)
45050 /*! RE - Receiver Enable
45051  *  0b0..Receiver is disabled.
45052  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
45053  */
45054 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
45055 /*! @} */
45056 
45057 /*! @name RCR1 - Receive Configuration 1 */
45058 /*! @{ */
45059 
45060 #define I2S_RCR1_RFW_MASK                        (0x1FU)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
45061 #define I2S_RCR1_RFW_SHIFT                       (0U)
45062 /*! RFW - Receive FIFO Watermark
45063  *  0b00000..1 FIFO word
45064  *  0b00001..2 FIFO words
45065  *  0b00010-0b11110..(RFW value + 1) FIFO words
45066  *  0b11111..32 FIFO words
45067  */
45068 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)  /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
45069 /*! @} */
45070 
45071 /*! @name RCR2 - Receive Configuration 2 */
45072 /*! @{ */
45073 
45074 #define I2S_RCR2_DIV_MASK                        (0xFFU)
45075 #define I2S_RCR2_DIV_SHIFT                       (0U)
45076 /*! DIV - Bit Clock Divide */
45077 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
45078 
45079 #define I2S_RCR2_BYP_MASK                        (0x800000U)
45080 #define I2S_RCR2_BYP_SHIFT                       (23U)
45081 /*! BYP - Bit Clock Bypass
45082  *  0b0..Internal bit clock is generated from bit clock divider.
45083  *  0b1..Internal bit clock is divide-by-one of the audio master clock.
45084  */
45085 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
45086 
45087 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
45088 #define I2S_RCR2_BCD_SHIFT                       (24U)
45089 /*! BCD - Bit Clock Direction
45090  *  0b0..Bit clock is generated externally in Slave mode.
45091  *  0b1..Bit clock is generated internally in Master mode.
45092  */
45093 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
45094 
45095 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
45096 #define I2S_RCR2_BCP_SHIFT                       (25U)
45097 /*! BCP - Bit Clock Polarity
45098  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
45099  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
45100  */
45101 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
45102 
45103 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
45104 #define I2S_RCR2_MSEL_SHIFT                      (26U)
45105 /*! MSEL - MCLK Select
45106  *  0b00..Bus Clock selected.
45107  *  0b01..Master Clock (MCLK) 1 option selected.
45108  *  0b10..Master Clock (MCLK) 2 option selected.
45109  *  0b11..Master Clock (MCLK) 3 option selected.
45110  */
45111 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
45112 
45113 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
45114 #define I2S_RCR2_BCI_SHIFT                       (28U)
45115 /*! BCI - Bit Clock Input
45116  *  0b0..No effect.
45117  *  0b1..Internal logic is clocked as if bit clock was externally generated.
45118  */
45119 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
45120 
45121 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
45122 #define I2S_RCR2_BCS_SHIFT                       (29U)
45123 /*! BCS - Bit Clock Swap
45124  *  0b0..Use the normal bit clock source.
45125  *  0b1..Swap the bit clock source.
45126  */
45127 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
45128 
45129 #define I2S_RCR2_SYNC_MASK                       (0x40000000U)
45130 #define I2S_RCR2_SYNC_SHIFT                      (30U)
45131 /*! SYNC - Synchronous Mode
45132  *  0b0..Asynchronous mode
45133  *  0b1..Synchronous with transmitter
45134  */
45135 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
45136 /*! @} */
45137 
45138 /*! @name RCR3 - Receive Configuration 3 */
45139 /*! @{ */
45140 
45141 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
45142 #define I2S_RCR3_WDFL_SHIFT                      (0U)
45143 /*! WDFL - Word Flag Configuration
45144  *  0b00000..Word 1
45145  *  0b00001..Word 2
45146  *  0b00010-0b11110..Word (WDFL value + 1)
45147  *  0b11111..Word 32
45148  */
45149 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
45150 
45151 #define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 2, 4), largest definition used */
45152 #define I2S_RCR3_RCE_SHIFT                       (16U)
45153 /*! RCE - Receive Channel Enable */
45154 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 4), largest definition used */
45155 
45156 #define I2S_RCR3_CFR_MASK                        (0xF000000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
45157 #define I2S_RCR3_CFR_SHIFT                       (24U)
45158 /*! CFR - Channel FIFO Reset */
45159 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
45160 /*! @} */
45161 
45162 /*! @name RCR4 - Receive Configuration 4 */
45163 /*! @{ */
45164 
45165 #define I2S_RCR4_FSD_MASK                        (0x1U)
45166 #define I2S_RCR4_FSD_SHIFT                       (0U)
45167 /*! FSD - Frame Sync Direction
45168  *  0b0..Frame Sync is generated externally in Slave mode.
45169  *  0b1..Frame Sync is generated internally in Master mode.
45170  */
45171 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
45172 
45173 #define I2S_RCR4_FSP_MASK                        (0x2U)
45174 #define I2S_RCR4_FSP_SHIFT                       (1U)
45175 /*! FSP - Frame Sync Polarity
45176  *  0b0..Frame sync is active high.
45177  *  0b1..Frame sync is active low.
45178  */
45179 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
45180 
45181 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
45182 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
45183 /*! ONDEM - On Demand Mode
45184  *  0b0..Internal frame sync is generated continuously.
45185  *  0b1..Internal frame sync is generated when the FIFO warning flag is 0.
45186  */
45187 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
45188 
45189 #define I2S_RCR4_FSE_MASK                        (0x8U)
45190 #define I2S_RCR4_FSE_SHIFT                       (3U)
45191 /*! FSE - Frame Sync Early
45192  *  0b0..Frame sync asserts with the first bit of the frame.
45193  *  0b1..Frame sync asserts one bit before the first bit of the frame.
45194  */
45195 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
45196 
45197 #define I2S_RCR4_MF_MASK                         (0x10U)
45198 #define I2S_RCR4_MF_SHIFT                        (4U)
45199 /*! MF - MSB First
45200  *  0b0..LSB is received first.
45201  *  0b1..MSB is received first.
45202  */
45203 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
45204 
45205 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
45206 #define I2S_RCR4_SYWD_SHIFT                      (8U)
45207 /*! SYWD - Sync Width
45208  *  0b00000..1 bit-clock cycle
45209  *  0b00001..2 bit-clock cycle
45210  *  0b00010-0b11110..(SYWD value + 1) bit-clock cycle
45211  *  0b11111..32 bit-clock cycle
45212  */
45213 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
45214 
45215 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
45216 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
45217 /*! FRSZ - Frame Size
45218  *  0b00000..1 word per frame
45219  *  0b00001..2 words per frame
45220  *  0b00010-0b11110..(FRSZ value + 1) words per frame
45221  *  0b11111..32 words per frame
45222  */
45223 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
45224 
45225 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
45226 #define I2S_RCR4_FPACK_SHIFT                     (24U)
45227 /*! FPACK - FIFO Packing Mode
45228  *  0b00..FIFO packing is disabled
45229  *  0b01..Reserved
45230  *  0b10..8-bit FIFO packing is enabled
45231  *  0b11..16-bit FIFO packing is enabled
45232  */
45233 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
45234 
45235 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
45236 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
45237 /*! FCOMB - FIFO Combine Mode
45238  *  0b00..FIFO Combine mode disabled.
45239  *  0b01..FIFO Combine mode enabled on FIFO writes (from receive shift registers).
45240  *  0b10..FIFO Combine mode enabled on FIFO reads (by software).
45241  *  0b11..FIFO Combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
45242  */
45243 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
45244 
45245 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
45246 #define I2S_RCR4_FCONT_SHIFT                     (28U)
45247 /*! FCONT - FIFO Continue on Error
45248  *  0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag returns to 0.
45249  *  0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0.
45250  */
45251 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
45252 /*! @} */
45253 
45254 /*! @name RCR5 - Receive Configuration 5 */
45255 /*! @{ */
45256 
45257 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
45258 #define I2S_RCR5_FBT_SHIFT                       (8U)
45259 /*! FBT - First Bit Shifted
45260  *  0b00000..Bit index is 0.
45261  *  0b00001-0b11110..Bit index is FBT value.
45262  *  0b11111..Bit index is 31.
45263  */
45264 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
45265 
45266 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
45267 #define I2S_RCR5_W0W_SHIFT                       (16U)
45268 /*! W0W - Word 0 Width
45269  *  0b00000..1 bit per word
45270  *  0b00001..2 bits per word
45271  *  0b00010-0b11110..(W0W value + 1) bits per word
45272  *  0b11111..32 bits per word
45273  */
45274 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
45275 
45276 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
45277 #define I2S_RCR5_WNW_SHIFT                       (24U)
45278 /*! WNW - Word N Width
45279  *  0b00111..8 bits per word
45280  *  0b01000..9 bits per word
45281  *  0b01001-0b11110..(WNW value + 1) bits per word
45282  *  0b11111..32 bits per word
45283  */
45284 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
45285 /*! @} */
45286 
45287 /*! @name RDR - Receive Data */
45288 /*! @{ */
45289 
45290 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
45291 #define I2S_RDR_RDR_SHIFT                        (0U)
45292 /*! RDR - Receive Data Register */
45293 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
45294 /*! @} */
45295 
45296 /* The count of I2S_RDR */
45297 #define I2S_RDR_COUNT                            (4U)
45298 
45299 /*! @name RFR - Receive FIFO */
45300 /*! @{ */
45301 
45302 #define I2S_RFR_RFP_MASK                         (0x3FU)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
45303 #define I2S_RFR_RFP_SHIFT                        (0U)
45304 /*! RFP - Read FIFO Pointer */
45305 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
45306 
45307 #define I2S_RFR_RCP_MASK                         (0x8000U)
45308 #define I2S_RFR_RCP_SHIFT                        (15U)
45309 /*! RCP - Receive Channel Pointer
45310  *  0b0..No effect.
45311  *  0b1..FIFO Combine mode is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
45312  */
45313 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
45314 
45315 #define I2S_RFR_WFP_MASK                         (0x3F0000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
45316 #define I2S_RFR_WFP_SHIFT                        (16U)
45317 /*! WFP - Write FIFO Pointer */
45318 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
45319 /*! @} */
45320 
45321 /* The count of I2S_RFR */
45322 #define I2S_RFR_COUNT                            (4U)
45323 
45324 /*! @name RMR - Receive Mask */
45325 /*! @{ */
45326 
45327 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
45328 #define I2S_RMR_RWM_SHIFT                        (0U)
45329 /*! RWM - Receive Word Mask
45330  *  0b00000000000000000000000000000000..Word N is enabled.
45331  *  0b00000000000000000000000000000001..Word N is masked.
45332  */
45333 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
45334 /*! @} */
45335 
45336 
45337 /*!
45338  * @}
45339  */ /* end of group I2S_Register_Masks */
45340 
45341 
45342 /* I2S - Peripheral instance base addresses */
45343 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
45344   /** Peripheral SAI1 base address */
45345   #define SAI1_BASE                                (0x543B0000u)
45346   /** Peripheral SAI1 base address */
45347   #define SAI1_BASE_NS                             (0x443B0000u)
45348   /** Peripheral SAI1 base pointer */
45349   #define SAI1                                     ((I2S_Type *)SAI1_BASE)
45350   /** Peripheral SAI1 base pointer */
45351   #define SAI1_NS                                  ((I2S_Type *)SAI1_BASE_NS)
45352   /** Peripheral SAI2 base address */
45353   #define SAI2_BASE                                (0x52BB0000u)
45354   /** Peripheral SAI2 base address */
45355   #define SAI2_BASE_NS                             (0x42BB0000u)
45356   /** Peripheral SAI2 base pointer */
45357   #define SAI2                                     ((I2S_Type *)SAI2_BASE)
45358   /** Peripheral SAI2 base pointer */
45359   #define SAI2_NS                                  ((I2S_Type *)SAI2_BASE_NS)
45360   /** Peripheral SAI3 base address */
45361   #define SAI3_BASE                                (0x52BC0000u)
45362   /** Peripheral SAI3 base address */
45363   #define SAI3_BASE_NS                             (0x42BC0000u)
45364   /** Peripheral SAI3 base pointer */
45365   #define SAI3                                     ((I2S_Type *)SAI3_BASE)
45366   /** Peripheral SAI3 base pointer */
45367   #define SAI3_NS                                  ((I2S_Type *)SAI3_BASE_NS)
45368   /** Peripheral SAI4 base address */
45369   #define SAI4_BASE                                (0x52BD0000u)
45370   /** Peripheral SAI4 base address */
45371   #define SAI4_BASE_NS                             (0x42BD0000u)
45372   /** Peripheral SAI4 base pointer */
45373   #define SAI4                                     ((I2S_Type *)SAI4_BASE)
45374   /** Peripheral SAI4 base pointer */
45375   #define SAI4_NS                                  ((I2S_Type *)SAI4_BASE_NS)
45376   /** Array initializer of I2S peripheral base addresses */
45377   #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
45378   /** Array initializer of I2S peripheral base pointers */
45379   #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
45380   /** Array initializer of I2S peripheral base addresses */
45381   #define I2S_BASE_ADDRS_NS                        { 0u, SAI1_BASE_NS, SAI2_BASE_NS, SAI3_BASE_NS, SAI4_BASE_NS }
45382   /** Array initializer of I2S peripheral base pointers */
45383   #define I2S_BASE_PTRS_NS                         { (I2S_Type *)0u, SAI1_NS, SAI2_NS, SAI3_NS, SAI4_NS }
45384 #else
45385   /** Peripheral SAI1 base address */
45386   #define SAI1_BASE                                (0x443B0000u)
45387   /** Peripheral SAI1 base pointer */
45388   #define SAI1                                     ((I2S_Type *)SAI1_BASE)
45389   /** Peripheral SAI2 base address */
45390   #define SAI2_BASE                                (0x42BB0000u)
45391   /** Peripheral SAI2 base pointer */
45392   #define SAI2                                     ((I2S_Type *)SAI2_BASE)
45393   /** Peripheral SAI3 base address */
45394   #define SAI3_BASE                                (0x42BC0000u)
45395   /** Peripheral SAI3 base pointer */
45396   #define SAI3                                     ((I2S_Type *)SAI3_BASE)
45397   /** Peripheral SAI4 base address */
45398   #define SAI4_BASE                                (0x42BD0000u)
45399   /** Peripheral SAI4 base pointer */
45400   #define SAI4                                     ((I2S_Type *)SAI4_BASE)
45401   /** Array initializer of I2S peripheral base addresses */
45402   #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
45403   /** Array initializer of I2S peripheral base pointers */
45404   #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
45405 #endif
45406 /** Interrupt vectors for the I2S peripheral type */
45407 #define I2S_RX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn }
45408 #define I2S_TX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn }
45409 
45410 /*!
45411  * @}
45412  */ /* end of group I2S_Peripheral_Access_Layer */
45413 
45414 
45415 /* ----------------------------------------------------------------------------
45416    -- I3C Peripheral Access Layer
45417    ---------------------------------------------------------------------------- */
45418 
45419 /*!
45420  * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
45421  * @{
45422  */
45423 
45424 /** I3C - Register Layout Typedef */
45425 typedef struct {
45426   __IO uint32_t MCONFIG;                           /**< Controller Configuration, offset: 0x0 */
45427   __IO uint32_t SCONFIG;                           /**< Target Configuration, offset: 0x4 */
45428   __IO uint32_t SSTATUS;                           /**< Target Status, offset: 0x8 */
45429   __IO uint32_t SCTRL;                             /**< Target Control, offset: 0xC */
45430   __IO uint32_t SINTSET;                           /**< Target Interrupt Set, offset: 0x10 */
45431   __IO uint32_t SINTCLR;                           /**< Target Interrupt Clear, offset: 0x14 */
45432   __I  uint32_t SINTMASKED;                        /**< Target Interrupt Mask, offset: 0x18 */
45433   __IO uint32_t SERRWARN;                          /**< Target Errors and Warnings, offset: 0x1C */
45434   __IO uint32_t SDMACTRL;                          /**< Target DMA Control, offset: 0x20 */
45435        uint8_t RESERVED_0[8];
45436   __IO uint32_t SDATACTRL;                         /**< Target Data Control, offset: 0x2C */
45437   __O  uint32_t SWDATAB;                           /**< Target Write Data Byte, offset: 0x30 */
45438   __O  uint32_t SWDATABE;                          /**< Target Write Data Byte End, offset: 0x34 */
45439   __O  uint32_t SWDATAH;                           /**< Target Write Data Halfword, offset: 0x38 */
45440   __O  uint32_t SWDATAHE;                          /**< Target Write Data Halfword End, offset: 0x3C */
45441   __I  uint32_t SRDATAB;                           /**< Target Read Data Byte, offset: 0x40 */
45442        uint8_t RESERVED_1[4];
45443   __I  uint32_t SRDATAH;                           /**< Target Read Data Halfword, offset: 0x48 */
45444        uint8_t RESERVED_2[8];
45445   __O  uint32_t SWDATAB1;                          /**< Target Write Data Byte, offset: 0x54 */
45446        uint8_t RESERVED_3[4];
45447   __I  uint32_t SCAPABILITIES2;                    /**< Target Capabilities 2, offset: 0x5C */
45448   __I  uint32_t SCAPABILITIES;                     /**< Target Capabilities, offset: 0x60 */
45449        uint8_t RESERVED_4[4];
45450   __IO uint32_t SMAXLIMITS;                        /**< Target Maximum Limits, offset: 0x68 */
45451   __IO uint32_t SIDPARTNO;                         /**< Target ID Part Number, offset: 0x6C */
45452   __IO uint32_t SIDEXT;                            /**< Target ID Extension, offset: 0x70 */
45453   __IO uint32_t SVENDORID;                         /**< Target Vendor ID, offset: 0x74 */
45454   __IO uint32_t STCCLOCK;                          /**< Target Time Control Clock, offset: 0x78 */
45455   __I  uint32_t SMSGMAPADDR;                       /**< Target Message Map Address, offset: 0x7C */
45456        uint8_t RESERVED_5[4];
45457   __IO uint32_t MCTRL;                             /**< Controller Control, offset: 0x84 */
45458   __IO uint32_t MSTATUS;                           /**< Controller Status, offset: 0x88 */
45459   __IO uint32_t MIBIRULES;                         /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */
45460   __IO uint32_t MINTSET;                           /**< Controller Interrupt Set, offset: 0x90 */
45461   __IO uint32_t MINTCLR;                           /**< Controller Interrupt Clear, offset: 0x94 */
45462   __I  uint32_t MINTMASKED;                        /**< Controller Interrupt Mask, offset: 0x98 */
45463   __IO uint32_t MERRWARN;                          /**< Controller Errors and Warnings, offset: 0x9C */
45464   __IO uint32_t MDMACTRL;                          /**< Controller DMA Control, offset: 0xA0 */
45465        uint8_t RESERVED_6[8];
45466   __IO uint32_t MDATACTRL;                         /**< Controller Data Control, offset: 0xAC */
45467   __O  uint32_t MWDATAB;                           /**< Controller Write Data Byte, offset: 0xB0 */
45468   __O  uint32_t MWDATABE;                          /**< Controller Write Data Byte End, offset: 0xB4 */
45469   __O  uint32_t MWDATAH;                           /**< Controller Write Data Halfword, offset: 0xB8 */
45470   __O  uint32_t MWDATAHE;                          /**< Controller Write Data Halfword End, offset: 0xBC */
45471   __I  uint32_t MRDATAB;                           /**< Controller Read Data Byte, offset: 0xC0 */
45472        uint8_t RESERVED_7[4];
45473   __I  uint32_t MRDATAH;                           /**< Controller Read Data Halfword, offset: 0xC8 */
45474   __O  uint32_t MWDATAB1;                          /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */
45475   union {                                          /* offset: 0xD0 */
45476     __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Controller Write Message Control in SDR mode, offset: 0xD0 */
45477     __O  uint32_t MWMSG_SDR_DATA;                    /**< Controller Write Message Data in SDR mode, offset: 0xD0 */
45478   };
45479   __I  uint32_t MRMSG_SDR;                         /**< Controller Read Message in SDR mode, offset: 0xD4 */
45480   union {                                          /* offset: 0xD8 */
45481     __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */
45482     __O  uint32_t MWMSG_DDR_CONTROL2;                /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */
45483     __O  uint32_t MWMSG_DDR_DATA;                    /**< Controller Write Message Data in DDR mode, offset: 0xD8 */
45484   };
45485   __I  uint32_t MRMSG_DDR;                         /**< Controller Read Message in DDR mode, offset: 0xDC */
45486        uint8_t RESERVED_8[4];
45487   __IO uint32_t MDYNADDR;                          /**< Controller Dynamic Address, offset: 0xE4 */
45488        uint8_t RESERVED_9[24];
45489   __IO uint32_t SRSTACTTIME;                       /**< Timing Rules for Target Reset Recovery, offset: 0x100 */
45490        uint8_t RESERVED_10[8];
45491   __IO uint32_t SCCCMASK;                          /**< CCC Mask for Unhandled CCCs, offset: 0x10C */
45492   __IO uint32_t SERRWARNMASK;                      /**< Target Errors and Warnings Mask, offset: 0x110 */
45493        uint8_t RESERVED_11[8];
45494   __I  uint32_t SMAPCTRL0;                         /**< Map Feature Control 0, offset: 0x11C */
45495   __IO uint32_t SMAPCTRL1;                         /**< Map Feature Control 1, offset: 0x120 */
45496        uint8_t RESERVED_12[28];
45497   __IO uint32_t IBIEXT1;                           /**< Extended IBI Data 1, offset: 0x140 */
45498   __IO uint32_t IBIEXT2;                           /**< Extended IBI Data 2, offset: 0x144 */
45499 } I3C_Type;
45500 
45501 /* ----------------------------------------------------------------------------
45502    -- I3C Register Masks
45503    ---------------------------------------------------------------------------- */
45504 
45505 /*!
45506  * @addtogroup I3C_Register_Masks I3C Register Masks
45507  * @{
45508  */
45509 
45510 /*! @name MCONFIG - Controller Configuration */
45511 /*! @{ */
45512 
45513 #define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
45514 #define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
45515 /*! MSTENA - Controller Enable
45516  *  0b00..CONTROLLER_OFF
45517  *  0b01..CONTROLLER_ON
45518  *  0b10..CONTROLLER_CAPABLE
45519  *  0b11..
45520  */
45521 #define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
45522 
45523 #define I3C_MCONFIG_DISTO_MASK                   (0x8U)
45524 #define I3C_MCONFIG_DISTO_SHIFT                  (3U)
45525 /*! DISTO - Disable Timeout
45526  *  0b1..Disabled, if configured
45527  *  0b0..Enabled
45528  */
45529 #define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
45530 
45531 #define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
45532 #define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
45533 /*! HKEEP - High-Keeper
45534  *  0b00..None
45535  *  0b01..WIRED_IN
45536  *  0b10..PASSIVE_SDA
45537  *  0b11..PASSIVE_ON_SDA_SCL
45538  */
45539 #define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
45540 
45541 #define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
45542 #define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
45543 /*! ODSTOP - Open Drain Stop
45544  *  0b1..Enable
45545  *  0b0..Disable
45546  */
45547 #define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
45548 
45549 #define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
45550 #define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
45551 /*! PPBAUD - Push-Pull Baud Rate */
45552 #define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
45553 
45554 #define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
45555 #define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
45556 /*! PPLOW - Push-Pull Low */
45557 #define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
45558 
45559 #define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
45560 #define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
45561 /*! ODBAUD - Open Drain Baud Rate */
45562 #define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
45563 
45564 #define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
45565 #define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
45566 /*! ODHPP - Open Drain High Push-Pull
45567  *  0b1..Enable
45568  *  0b0..Disable
45569  */
45570 #define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
45571 
45572 #define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
45573 #define I3C_MCONFIG_SKEW_SHIFT                   (25U)
45574 /*! SKEW - Skew */
45575 #define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
45576 
45577 #define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
45578 #define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
45579 /*! I2CBAUD - I2C Baud Rate */
45580 #define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
45581 /*! @} */
45582 
45583 /*! @name SCONFIG - Target Configuration */
45584 /*! @{ */
45585 
45586 #define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
45587 #define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
45588 /*! SLVENA - Target Enable
45589  *  0b1..Enable
45590  *  0b0..Disable
45591  */
45592 #define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
45593 
45594 #define I3C_SCONFIG_NACK_MASK                    (0x2U)
45595 #define I3C_SCONFIG_NACK_SHIFT                   (1U)
45596 /*! NACK - Not Acknowledge
45597  *  0b1..Always enable NACK mode (works normally)
45598  *  0b0..Always disable NACK mode
45599  */
45600 #define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
45601 
45602 #define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
45603 #define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
45604 /*! MATCHSS - Match Start or Stop
45605  *  0b1..Enable
45606  *  0b0..Disable
45607  */
45608 #define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
45609 
45610 #define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
45611 #define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
45612 /*! S0IGNORE - Ignore TE0 or TE1 Errors
45613  *  0b1..Ignore TE0 or TE1 errors
45614  *  0b0..Do not ignore TE0 or TE1 errors
45615  */
45616 #define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
45617 
45618 #define I3C_SCONFIG_DDROK_MASK                   (0x10U)
45619 #define I3C_SCONFIG_DDROK_SHIFT                  (4U)
45620 /*! DDROK - Double Data Rate OK
45621  *  0b1..Allow HDR-DDR messaging
45622  *  0b0..Do not allow HDR-DDR messaging
45623  */
45624 #define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)
45625 
45626 #define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
45627 #define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
45628 /*! OFFLINE - Offline
45629  *  0b1..Enable
45630  *  0b0..Disable
45631  */
45632 #define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
45633 
45634 #define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
45635 #define I3C_SCONFIG_SADDR_SHIFT                  (25U)
45636 /*! SADDR - Static Address */
45637 #define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
45638 /*! @} */
45639 
45640 /*! @name SSTATUS - Target Status */
45641 /*! @{ */
45642 
45643 #define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
45644 #define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
45645 /*! STNOTSTOP - Status not Stop
45646  *  0b1..Busy
45647  *  0b0..In STOP condition
45648  */
45649 #define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
45650 
45651 #define I3C_SSTATUS_STMSG_MASK                   (0x2U)
45652 #define I3C_SSTATUS_STMSG_SHIFT                  (1U)
45653 /*! STMSG - Status Message
45654  *  0b1..Busy
45655  *  0b0..Idle
45656  */
45657 #define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
45658 
45659 #define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
45660 #define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
45661 /*! STCCCH - Status Common Command Code Handler
45662  *  0b1..Handled automatically
45663  *  0b0..No CCC message handled
45664  */
45665 #define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
45666 
45667 #define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
45668 #define I3C_SSTATUS_STREQRD_SHIFT                (3U)
45669 /*! STREQRD - Status Request Read
45670  *  0b1..SDR read from this target or an IBI is being pushed out
45671  *  0b0..Not an SDR read
45672  */
45673 #define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
45674 
45675 #define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
45676 #define I3C_SSTATUS_STREQWR_SHIFT                (4U)
45677 /*! STREQWR - Status Request Write
45678  *  0b1..SDR write data from the controller, but not in ENTDAA mode
45679  *  0b0..Not an SDR write
45680  */
45681 #define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
45682 
45683 #define I3C_SSTATUS_STDAA_MASK                   (0x20U)
45684 #define I3C_SSTATUS_STDAA_SHIFT                  (5U)
45685 /*! STDAA - Status Dynamic Address Assignment
45686  *  0b1..In ENTDAA mode
45687  *  0b0..Not in ENTDAA mode
45688  */
45689 #define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
45690 
45691 #define I3C_SSTATUS_STHDR_MASK                   (0x40U)
45692 #define I3C_SSTATUS_STHDR_SHIFT                  (6U)
45693 /*! STHDR - Status High Data Rate
45694  *  0b1..I3C bus in HDR-DDR mode
45695  *  0b0..I3C bus not in HDR-DDR mode
45696  */
45697 #define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
45698 
45699 #define I3C_SSTATUS_START_MASK                   (0x100U)
45700 #define I3C_SSTATUS_START_SHIFT                  (8U)
45701 /*! START - Start Flag
45702  *  0b1..Detected
45703  *  0b0..Not detected
45704  *  0b0..No effect
45705  *  0b1..Clear the flag
45706  */
45707 #define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
45708 
45709 #define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
45710 #define I3C_SSTATUS_MATCHED_SHIFT                (9U)
45711 /*! MATCHED - Matched Flag
45712  *  0b1..Header matched
45713  *  0b0..Header not matched
45714  *  0b0..No effect
45715  *  0b1..Clear the flag
45716  */
45717 #define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
45718 
45719 #define I3C_SSTATUS_STOP_MASK                    (0x400U)
45720 #define I3C_SSTATUS_STOP_SHIFT                   (10U)
45721 /*! STOP - Stop Flag
45722  *  0b1..Stopped state detected
45723  *  0b0..No Stopped state detected
45724  *  0b0..No effect
45725  *  0b1..Clear the flag
45726  */
45727 #define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
45728 
45729 #define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
45730 #define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
45731 /*! RX_PEND - Received Message Pending
45732  *  0b1..Received message pending
45733  *  0b0..No received message pending
45734  */
45735 #define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
45736 
45737 #define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
45738 #define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
45739 /*! TXNOTFULL - Transmit Buffer Not Full
45740  *  0b1..Transmit buffer not full
45741  *  0b0..Transmit buffer full
45742  */
45743 #define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
45744 
45745 #define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
45746 #define I3C_SSTATUS_DACHG_SHIFT                  (13U)
45747 /*! DACHG - Dynamic Address Change Flag
45748  *  0b1..DA change detected
45749  *  0b0..No DA change detected
45750  *  0b0..No effect
45751  *  0b1..Clear the flag
45752  */
45753 #define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
45754 
45755 #define I3C_SSTATUS_CCC_MASK                     (0x4000U)
45756 #define I3C_SSTATUS_CCC_SHIFT                    (14U)
45757 /*! CCC - Common Command Code Flag
45758  *  0b1..CCC received
45759  *  0b0..CCC not received
45760  *  0b0..No effect
45761  *  0b1..Clear the flag
45762  */
45763 #define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
45764 
45765 #define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
45766 #define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
45767 /*! ERRWARN - Error Warning */
45768 #define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
45769 
45770 #define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
45771 #define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
45772 /*! HDRMATCH - High Data Rate Command Match Flag
45773  *  0b1..Matched the I3C dynamic address
45774  *  0b0..Did not match
45775  *  0b0..No effect
45776  *  0b1..Clear the flag
45777  */
45778 #define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
45779 
45780 #define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
45781 #define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
45782 /*! CHANDLED - Common Command Code Handled Flag
45783  *  0b1..CCC handling in progress
45784  *  0b0..CCC handling not in progress
45785  *  0b0..No effect
45786  *  0b1..Clear the flag
45787  */
45788 #define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
45789 
45790 #define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
45791 #define I3C_SSTATUS_EVENT_SHIFT                  (18U)
45792 /*! EVENT - Event Flag
45793  *  0b1..IBI, CR, or HJ occurred
45794  *  0b0..No event occurred
45795  *  0b0..No effect
45796  *  0b1..Clear the flag
45797  */
45798 #define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
45799 
45800 #define I3C_SSTATUS_SLVRST_MASK                  (0x80000U)
45801 #define I3C_SSTATUS_SLVRST_SHIFT                 (19U)
45802 /*! SLVRST - Target Reset Flag */
45803 #define I3C_SSTATUS_SLVRST(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_SLVRST_SHIFT)) & I3C_SSTATUS_SLVRST_MASK)
45804 
45805 #define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
45806 #define I3C_SSTATUS_EVDET_SHIFT                  (20U)
45807 /*! EVDET - Event Details
45808  *  0b00..NONE (no event or no pending event)
45809  *  0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))
45810  *  0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again
45811  *  0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)
45812  */
45813 #define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
45814 
45815 #define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
45816 #define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
45817 /*! IBIDIS - In-Band Interrupts Disable
45818  *  0b1..Disabled
45819  *  0b0..Enabled
45820  */
45821 #define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
45822 
45823 #define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
45824 #define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
45825 /*! MRDIS - Controller Requests Disable
45826  *  0b1..Disabled
45827  *  0b0..Enabled
45828  */
45829 #define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
45830 
45831 #define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
45832 #define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
45833 /*! HJDIS - Hot-Join Disabled
45834  *  0b1..Disabled
45835  *  0b0..Enabled
45836  */
45837 #define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
45838 
45839 #define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
45840 #define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
45841 /*! ACTSTATE - Activity State from Common Command Codes (CCC)
45842  *  0b00..NO_LATENCY (normal bus operations)
45843  *  0b01..LATENCY_1MS (1 ms of latency)
45844  *  0b10..LATENCY_100MS (100 ms of latency)
45845  *  0b11..LATENCY_10S (10 seconds of latency)
45846  */
45847 #define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
45848 
45849 #define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
45850 #define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
45851 /*! TIMECTRL - Time Control
45852  *  0b00..NO_TIME_CONTROL (no time control is enabled)
45853  *  0b01..SYNC_MODE (Synchronous mode is enabled)
45854  *  0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)
45855  *  0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)
45856  */
45857 #define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
45858 /*! @} */
45859 
45860 /*! @name SCTRL - Target Control */
45861 /*! @{ */
45862 
45863 #define I3C_SCTRL_EVENT_MASK                     (0x3U)
45864 #define I3C_SCTRL_EVENT_SHIFT                    (0U)
45865 /*! EVENT - Event
45866  *  0b00..NORMAL_MODE
45867  *  0b01..IBI
45868  *  0b10..CONTROLLER_REQUEST
45869  *  0b11..HOT_JOIN_REQUEST
45870  */
45871 #define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
45872 
45873 #define I3C_SCTRL_EXTDATA_MASK                   (0x8U)
45874 #define I3C_SCTRL_EXTDATA_SHIFT                  (3U)
45875 /*! EXTDATA - Extended Data
45876  *  0b1..Enable
45877  *  0b0..Disable
45878  */
45879 #define I3C_SCTRL_EXTDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK)
45880 
45881 #define I3C_SCTRL_MAPIDX_MASK                    (0x10U)
45882 #define I3C_SCTRL_MAPIDX_SHIFT                   (4U)
45883 /*! MAPIDX - Map Index */
45884 #define I3C_SCTRL_MAPIDX(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_MAPIDX_SHIFT)) & I3C_SCTRL_MAPIDX_MASK)
45885 
45886 #define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
45887 #define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
45888 /*! IBIDATA - In-Band Interrupt Data */
45889 #define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
45890 
45891 #define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
45892 #define I3C_SCTRL_PENDINT_SHIFT                  (16U)
45893 /*! PENDINT - Pending Interrupt */
45894 #define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
45895 
45896 #define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
45897 #define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
45898 /*! ACTSTATE - Activity State of Target */
45899 #define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
45900 
45901 #define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
45902 #define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
45903 /*! VENDINFO - Vendor Information */
45904 #define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
45905 /*! @} */
45906 
45907 /*! @name SINTSET - Target Interrupt Set */
45908 /*! @{ */
45909 
45910 #define I3C_SINTSET_START_MASK                   (0x100U)
45911 #define I3C_SINTSET_START_SHIFT                  (8U)
45912 /*! START - Start Interrupt Enable
45913  *  0b1..Enable
45914  *  0b0..Disable
45915  */
45916 #define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
45917 
45918 #define I3C_SINTSET_MATCHED_MASK                 (0x200U)
45919 #define I3C_SINTSET_MATCHED_SHIFT                (9U)
45920 /*! MATCHED - Match Interrupt Enable
45921  *  0b1..Enable
45922  *  0b0..Disable
45923  */
45924 #define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
45925 
45926 #define I3C_SINTSET_STOP_MASK                    (0x400U)
45927 #define I3C_SINTSET_STOP_SHIFT                   (10U)
45928 /*! STOP - Stop Interrupt Enable
45929  *  0b1..Enable
45930  *  0b0..Disable
45931  */
45932 #define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
45933 
45934 #define I3C_SINTSET_RXPEND_MASK                  (0x800U)
45935 #define I3C_SINTSET_RXPEND_SHIFT                 (11U)
45936 /*! RXPEND - Receive Interrupt Enable
45937  *  0b1..Enable
45938  *  0b0..Disable
45939  */
45940 #define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
45941 
45942 #define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
45943 #define I3C_SINTSET_TXSEND_SHIFT                 (12U)
45944 /*! TXSEND - Transmit Interrupt Enable
45945  *  0b1..Enable
45946  *  0b0..Disable
45947  */
45948 #define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
45949 
45950 #define I3C_SINTSET_DACHG_MASK                   (0x2000U)
45951 #define I3C_SINTSET_DACHG_SHIFT                  (13U)
45952 /*! DACHG - Dynamic Address Change Interrupt Enable
45953  *  0b1..Enable
45954  *  0b0..Disable
45955  */
45956 #define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
45957 
45958 #define I3C_SINTSET_CCC_MASK                     (0x4000U)
45959 #define I3C_SINTSET_CCC_SHIFT                    (14U)
45960 /*! CCC - Common Command Code (CCC) Interrupt Enable
45961  *  0b1..Enable
45962  *  0b0..Disable
45963  */
45964 #define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
45965 
45966 #define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
45967 #define I3C_SINTSET_ERRWARN_SHIFT                (15U)
45968 /*! ERRWARN - Error or Warning Interrupt Enable
45969  *  0b1..Enable
45970  *  0b0..Disable
45971  */
45972 #define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
45973 
45974 #define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
45975 #define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
45976 /*! DDRMATCHED - Double Data Rate Interrupt Enable
45977  *  0b1..Enable
45978  *  0b0..Disable
45979  */
45980 #define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
45981 
45982 #define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
45983 #define I3C_SINTSET_CHANDLED_SHIFT               (17U)
45984 /*! CHANDLED - Common Command Code (CCC) Interrupt Enable
45985  *  0b1..Enable
45986  *  0b0..Disable
45987  */
45988 #define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
45989 
45990 #define I3C_SINTSET_EVENT_MASK                   (0x40000U)
45991 #define I3C_SINTSET_EVENT_SHIFT                  (18U)
45992 /*! EVENT - Event Interrupt Enable
45993  *  0b1..Enable
45994  *  0b0..Disable
45995  */
45996 #define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
45997 
45998 #define I3C_SINTSET_SLVRST_MASK                  (0x80000U)
45999 #define I3C_SINTSET_SLVRST_SHIFT                 (19U)
46000 /*! SLVRST - Target Reset
46001  *  0b1..Enable
46002  *  0b0..Disable
46003  */
46004 #define I3C_SINTSET_SLVRST(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_SLVRST_SHIFT)) & I3C_SINTSET_SLVRST_MASK)
46005 /*! @} */
46006 
46007 /*! @name SINTCLR - Target Interrupt Clear */
46008 /*! @{ */
46009 
46010 #define I3C_SINTCLR_START_MASK                   (0x100U)
46011 #define I3C_SINTCLR_START_SHIFT                  (8U)
46012 /*! START - START Interrupt Enable Clear Flag */
46013 #define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
46014 
46015 #define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
46016 #define I3C_SINTCLR_MATCHED_SHIFT                (9U)
46017 /*! MATCHED - Matched Interrupt Enable Clear Flag */
46018 #define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
46019 
46020 #define I3C_SINTCLR_STOP_MASK                    (0x400U)
46021 #define I3C_SINTCLR_STOP_SHIFT                   (10U)
46022 /*! STOP - STOP Interrupt Enable Clear Flag */
46023 #define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
46024 
46025 #define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
46026 #define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
46027 /*! RXPEND - RXPEND Interrupt Enable Clear Flag */
46028 #define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
46029 
46030 #define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
46031 #define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
46032 /*! TXSEND - TXSEND Interrupt Enable Clear Flag */
46033 #define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
46034 
46035 #define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
46036 #define I3C_SINTCLR_DACHG_SHIFT                  (13U)
46037 /*! DACHG - DACHG Interrupt Enable Clear Flag */
46038 #define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
46039 
46040 #define I3C_SINTCLR_CCC_MASK                     (0x4000U)
46041 #define I3C_SINTCLR_CCC_SHIFT                    (14U)
46042 /*! CCC - CCC Interrupt Enable Clear Flag */
46043 #define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
46044 
46045 #define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
46046 #define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
46047 /*! ERRWARN - ERRWARN Interrupt Enable Clear Flag */
46048 #define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
46049 
46050 #define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
46051 #define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
46052 /*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear Flag */
46053 #define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
46054 
46055 #define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
46056 #define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
46057 /*! CHANDLED - CHANDLED Interrupt Enable Clear Flag */
46058 #define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
46059 
46060 #define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
46061 #define I3C_SINTCLR_EVENT_SHIFT                  (18U)
46062 /*! EVENT - EVENT Interrupt Enable Clear Flag */
46063 #define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
46064 
46065 #define I3C_SINTCLR_SLVRST_MASK                  (0x80000U)
46066 #define I3C_SINTCLR_SLVRST_SHIFT                 (19U)
46067 /*! SLVRST - Target Reset Flag (SLVRST Interrupt Enable Clear) */
46068 #define I3C_SINTCLR_SLVRST(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_SLVRST_SHIFT)) & I3C_SINTCLR_SLVRST_MASK)
46069 /*! @} */
46070 
46071 /*! @name SINTMASKED - Target Interrupt Mask */
46072 /*! @{ */
46073 
46074 #define I3C_SINTMASKED_START_MASK                (0x100U)
46075 #define I3C_SINTMASKED_START_SHIFT               (8U)
46076 /*! START - START Interrupt Mask */
46077 #define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
46078 
46079 #define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
46080 #define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
46081 /*! MATCHED - MATCHED Interrupt Mask */
46082 #define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
46083 
46084 #define I3C_SINTMASKED_STOP_MASK                 (0x400U)
46085 #define I3C_SINTMASKED_STOP_SHIFT                (10U)
46086 /*! STOP - STOP Interrupt Mask */
46087 #define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
46088 
46089 #define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
46090 #define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
46091 /*! RXPEND - RXPEND Interrupt Mask */
46092 #define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
46093 
46094 #define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
46095 #define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
46096 /*! TXSEND - TXSEND Interrupt Mask */
46097 #define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
46098 
46099 #define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
46100 #define I3C_SINTMASKED_DACHG_SHIFT               (13U)
46101 /*! DACHG - DACHG Interrupt Mask */
46102 #define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
46103 
46104 #define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
46105 #define I3C_SINTMASKED_CCC_SHIFT                 (14U)
46106 /*! CCC - CCC Interrupt Mask */
46107 #define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
46108 
46109 #define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
46110 #define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
46111 /*! ERRWARN - ERRWARN Interrupt Mask */
46112 #define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
46113 
46114 #define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
46115 #define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
46116 /*! DDRMATCHED - DDRMATCHED Interrupt Mask */
46117 #define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
46118 
46119 #define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
46120 #define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
46121 /*! CHANDLED - CHANDLED Interrupt Mask */
46122 #define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
46123 
46124 #define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
46125 #define I3C_SINTMASKED_EVENT_SHIFT               (18U)
46126 /*! EVENT - EVENT Interrupt Mask */
46127 #define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
46128 
46129 #define I3C_SINTMASKED_SLVRST_MASK               (0x80000U)
46130 #define I3C_SINTMASKED_SLVRST_SHIFT              (19U)
46131 /*! SLVRST - Target Reset Interrupt Mask */
46132 #define I3C_SINTMASKED_SLVRST(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_SLVRST_SHIFT)) & I3C_SINTMASKED_SLVRST_MASK)
46133 /*! @} */
46134 
46135 /*! @name SERRWARN - Target Errors and Warnings */
46136 /*! @{ */
46137 
46138 #define I3C_SERRWARN_ORUN_MASK                   (0x1U)
46139 #define I3C_SERRWARN_ORUN_SHIFT                  (0U)
46140 /*! ORUN - Overrun Error Flag
46141  *  0b1..Overrun error
46142  *  0b0..No overrun error
46143  *  0b0..No effect
46144  *  0b1..Clear the flag
46145  */
46146 #define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
46147 
46148 #define I3C_SERRWARN_URUN_MASK                   (0x2U)
46149 #define I3C_SERRWARN_URUN_SHIFT                  (1U)
46150 /*! URUN - Underrun Error Flag
46151  *  0b1..Underrun error
46152  *  0b0..No underrun error
46153  *  0b0..No effect
46154  *  0b1..Clear the flag
46155  */
46156 #define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
46157 
46158 #define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
46159 #define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
46160 /*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag
46161  *  0b1..Underrun; not acknowledged error
46162  *  0b0..No underrun; not acknowledged error
46163  *  0b0..No effect
46164  *  0b1..Clear the flag
46165  */
46166 #define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
46167 
46168 #define I3C_SERRWARN_TERM_MASK                   (0x8U)
46169 #define I3C_SERRWARN_TERM_SHIFT                  (3U)
46170 /*! TERM - Terminated Error Flag
46171  *  0b1..Terminated error
46172  *  0b0..No terminated error
46173  *  0b0..No effect
46174  *  0b1..Clear the flag
46175  */
46176 #define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
46177 
46178 #define I3C_SERRWARN_INVSTART_MASK               (0x10U)
46179 #define I3C_SERRWARN_INVSTART_SHIFT              (4U)
46180 /*! INVSTART - Invalid Start Error Flag
46181  *  0b1..Invalid start error
46182  *  0b0..No invalid start error
46183  *  0b0..No effect
46184  *  0b1..Clear the flag
46185  */
46186 #define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
46187 
46188 #define I3C_SERRWARN_SPAR_MASK                   (0x100U)
46189 #define I3C_SERRWARN_SPAR_SHIFT                  (8U)
46190 /*! SPAR - SDR Parity Error Flag
46191  *  0b1..SDR parity error
46192  *  0b0..No SDR parity error
46193  *  0b0..No effect
46194  *  0b1..Clear the flag
46195  */
46196 #define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
46197 
46198 #define I3C_SERRWARN_HPAR_MASK                   (0x200U)
46199 #define I3C_SERRWARN_HPAR_SHIFT                  (9U)
46200 /*! HPAR - HDR Parity Error Flag
46201  *  0b1..HDR parity error
46202  *  0b0..No HDR parity error
46203  *  0b0..No effect
46204  *  0b1..Clear the flag
46205  */
46206 #define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
46207 
46208 #define I3C_SERRWARN_HCRC_MASK                   (0x400U)
46209 #define I3C_SERRWARN_HCRC_SHIFT                  (10U)
46210 /*! HCRC - HDR-DDR CRC Error Flag
46211  *  0b1..HDR-DDR CRC error occurred
46212  *  0b0..No HDR-DDR CRC error occurred
46213  *  0b0..No effect
46214  *  0b1..Clear the flag
46215  */
46216 #define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
46217 
46218 #define I3C_SERRWARN_S0S1_MASK                   (0x800U)
46219 #define I3C_SERRWARN_S0S1_SHIFT                  (11U)
46220 /*! S0S1 - TE0 or TE1 Error Flag
46221  *  0b1..TE0 or TE1 error occurred
46222  *  0b0..No TE0 or TE1 error occurred
46223  *  0b0..No effect
46224  *  0b1..Clear the flag
46225  */
46226 #define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
46227 
46228 #define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
46229 #define I3C_SERRWARN_OREAD_SHIFT                 (16U)
46230 /*! OREAD - Over-Read Error Flag
46231  *  0b1..Over-read error
46232  *  0b0..No over-read error
46233  *  0b0..No effect
46234  *  0b1..Clear the flag
46235  */
46236 #define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
46237 
46238 #define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
46239 #define I3C_SERRWARN_OWRITE_SHIFT                (17U)
46240 /*! OWRITE - Over-Write Error Flag
46241  *  0b1..Overwrite error
46242  *  0b0..No overwrite error
46243  *  0b0..No effect
46244  *  0b1..Clear the flag
46245  */
46246 #define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
46247 /*! @} */
46248 
46249 /*! @name SDMACTRL - Target DMA Control */
46250 /*! @{ */
46251 
46252 #define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
46253 #define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
46254 /*! DMAFB - DMA Read (From-Bus) Trigger
46255  *  0b00..DMA not used
46256  *  0b01..DMA enabled for one frame
46257  *  0b10..DMA enabled until turned off
46258  *  0b11..
46259  */
46260 #define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
46261 
46262 #define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
46263 #define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
46264 /*! DMATB - DMA Write (To-Bus) Trigger
46265  *  0b00..DMA not used
46266  *  0b01..DMA enabled for one frame
46267  *  0b10..DMA enabled until turned off
46268  *  0b11..
46269  */
46270 #define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
46271 
46272 #define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
46273 #define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
46274 /*! DMAWIDTH - Width of DMA Operations
46275  *  0b00, 0b01..Byte
46276  *  0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)
46277  *  0b11..
46278  */
46279 #define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
46280 /*! @} */
46281 
46282 /*! @name SDATACTRL - Target Data Control */
46283 /*! @{ */
46284 
46285 #define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
46286 #define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
46287 /*! FLUSHTB - Flush To-Bus Buffer or FIFO */
46288 #define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
46289 
46290 #define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
46291 #define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
46292 /*! FLUSHFB - Flush From-Bus Buffer or FIFO */
46293 #define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
46294 
46295 #define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
46296 #define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
46297 /*! UNLOCK - Unlock
46298  *  0b0..Cannot be changed
46299  *  0b1..Can be changed
46300  */
46301 #define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
46302 
46303 #define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
46304 #define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
46305 /*! TXTRIG - Transmit Trigger Level
46306  *  0b00..Trigger when empty
46307  *  0b01..Trigger when 1/4 full or less
46308  *  0b10..Trigger when 1/2 full or less
46309  *  0b11..Default (trigger when 1 less than full or less)
46310  */
46311 #define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
46312 
46313 #define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
46314 #define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
46315 /*! RXTRIG - Receive Trigger Level
46316  *  0b00..Trigger when not empty
46317  *  0b01..Trigger when 1/4 or more full
46318  *  0b10..Trigger when 1/2 or more full
46319  *  0b11..Trigger when 3/4 or more full
46320  */
46321 #define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
46322 
46323 #define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
46324 #define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
46325 /*! TXCOUNT - Count of Bytes in Transmit */
46326 #define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
46327 
46328 #define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
46329 #define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
46330 /*! RXCOUNT - Count of Bytes in Receive */
46331 #define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
46332 
46333 #define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
46334 #define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
46335 /*! TXFULL - Transmit is Full
46336  *  0b1..Full
46337  *  0b0..Not full
46338  */
46339 #define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
46340 
46341 #define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
46342 #define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
46343 /*! RXEMPTY - Receive is Empty
46344  *  0b1..Empty
46345  *  0b0..Not empty
46346  */
46347 #define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
46348 /*! @} */
46349 
46350 /*! @name SWDATAB - Target Write Data Byte */
46351 /*! @{ */
46352 
46353 #define I3C_SWDATAB_DATA_MASK                    (0xFFU)
46354 #define I3C_SWDATAB_DATA_SHIFT                   (0U)
46355 /*! DATA - Data */
46356 #define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
46357 
46358 #define I3C_SWDATAB_END_MASK                     (0x100U)
46359 #define I3C_SWDATAB_END_SHIFT                    (8U)
46360 /*! END - End
46361  *  0b1..End
46362  *  0b0..Not the end
46363  */
46364 #define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
46365 
46366 #define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
46367 #define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
46368 /*! END_ALSO - End Also
46369  *  0b1..End
46370  *  0b0..Not the end
46371  */
46372 #define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
46373 /*! @} */
46374 
46375 /*! @name SWDATABE - Target Write Data Byte End */
46376 /*! @{ */
46377 
46378 #define I3C_SWDATABE_DATA_MASK                   (0xFFU)
46379 #define I3C_SWDATABE_DATA_SHIFT                  (0U)
46380 /*! DATA - Data */
46381 #define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
46382 /*! @} */
46383 
46384 /*! @name SWDATAH - Target Write Data Halfword */
46385 /*! @{ */
46386 
46387 #define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
46388 #define I3C_SWDATAH_DATA0_SHIFT                  (0U)
46389 /*! DATA0 - Data 0 */
46390 #define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
46391 
46392 #define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
46393 #define I3C_SWDATAH_DATA1_SHIFT                  (8U)
46394 /*! DATA1 - Data 1 */
46395 #define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
46396 
46397 #define I3C_SWDATAH_END_MASK                     (0x10000U)
46398 #define I3C_SWDATAH_END_SHIFT                    (16U)
46399 /*! END - End of Message
46400  *  0b1..End
46401  *  0b0..Not the end
46402  */
46403 #define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
46404 /*! @} */
46405 
46406 /*! @name SWDATAHE - Target Write Data Halfword End */
46407 /*! @{ */
46408 
46409 #define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
46410 #define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
46411 /*! DATA0 - Data 0 */
46412 #define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
46413 
46414 #define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
46415 #define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
46416 /*! DATA1 - Data 1 */
46417 #define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
46418 /*! @} */
46419 
46420 /*! @name SRDATAB - Target Read Data Byte */
46421 /*! @{ */
46422 
46423 #define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
46424 #define I3C_SRDATAB_DATA0_SHIFT                  (0U)
46425 /*! DATA0 - Data 0 */
46426 #define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
46427 /*! @} */
46428 
46429 /*! @name SRDATAH - Target Read Data Halfword */
46430 /*! @{ */
46431 
46432 #define I3C_SRDATAH_LSB_MASK                     (0xFFU)
46433 #define I3C_SRDATAH_LSB_SHIFT                    (0U)
46434 /*! LSB - Low Byte */
46435 #define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
46436 
46437 #define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
46438 #define I3C_SRDATAH_MSB_SHIFT                    (8U)
46439 /*! MSB - High Byte */
46440 #define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
46441 /*! @} */
46442 
46443 /*! @name SWDATAB1 - Target Write Data Byte */
46444 /*! @{ */
46445 
46446 #define I3C_SWDATAB1_DATA_MASK                   (0xFFU)
46447 #define I3C_SWDATAB1_DATA_SHIFT                  (0U)
46448 /*! DATA - Data */
46449 #define I3C_SWDATAB1_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK)
46450 /*! @} */
46451 
46452 /*! @name SCAPABILITIES2 - Target Capabilities 2 */
46453 /*! @{ */
46454 
46455 #define I3C_SCAPABILITIES2_MAPCNT_MASK           (0xFU)
46456 #define I3C_SCAPABILITIES2_MAPCNT_SHIFT          (0U)
46457 /*! MAPCNT - Map Count */
46458 #define I3C_SCAPABILITIES2_MAPCNT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK)
46459 
46460 #define I3C_SCAPABILITIES2_I2C10B_MASK           (0x10U)
46461 #define I3C_SCAPABILITIES2_I2C10B_SHIFT          (4U)
46462 /*! I2C10B - I2C 10-bit Address
46463  *  0b0..Not supported
46464  *  0b1..Supported
46465  */
46466 #define I3C_SCAPABILITIES2_I2C10B(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK)
46467 
46468 #define I3C_SCAPABILITIES2_I2CDEVID_MASK         (0x40U)
46469 #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT        (6U)
46470 /*! I2CDEVID - I2C Device ID
46471  *  0b0..Not supported
46472  *  0b1..Supported
46473  */
46474 #define I3C_SCAPABILITIES2_I2CDEVID(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK)
46475 
46476 #define I3C_SCAPABILITIES2_IBIEXT_MASK           (0x100U)
46477 #define I3C_SCAPABILITIES2_IBIEXT_SHIFT          (8U)
46478 /*! IBIEXT - In-Band Interrupt EXTDATA
46479  *  0b0..Not supported
46480  *  0b1..Supported
46481  */
46482 #define I3C_SCAPABILITIES2_IBIEXT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK)
46483 
46484 #define I3C_SCAPABILITIES2_IBIXREG_MASK          (0x200U)
46485 #define I3C_SCAPABILITIES2_IBIXREG_SHIFT         (9U)
46486 /*! IBIXREG - In-Band Interrupt Extended Register
46487  *  0b0..Not supported
46488  *  0b1..Supported
46489  */
46490 #define I3C_SCAPABILITIES2_IBIXREG(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK)
46491 
46492 #define I3C_SCAPABILITIES2_V1_1_MASK             (0x10000U)
46493 #define I3C_SCAPABILITIES2_V1_1_SHIFT            (16U)
46494 /*! V1_1 - Version 1.1
46495  *  0b0..Not supported
46496  *  0b1..Supported
46497  */
46498 #define I3C_SCAPABILITIES2_V1_1(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_V1_1_SHIFT)) & I3C_SCAPABILITIES2_V1_1_MASK)
46499 
46500 #define I3C_SCAPABILITIES2_SLVRST_MASK           (0x20000U)
46501 #define I3C_SCAPABILITIES2_SLVRST_SHIFT          (17U)
46502 /*! SLVRST - Target Reset
46503  *  0b0..Not supported
46504  *  0b1..Supported
46505  */
46506 #define I3C_SCAPABILITIES2_SLVRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK)
46507 
46508 #define I3C_SCAPABILITIES2_GROUP_MASK            (0xC0000U)
46509 #define I3C_SCAPABILITIES2_GROUP_SHIFT           (18U)
46510 /*! GROUP - Group
46511  *  0b00..v1.1 group addressing not supported
46512  *  0b01..One group supported
46513  *  0b10..Two groups supported
46514  *  0b11..Three groups supported
46515  */
46516 #define I3C_SCAPABILITIES2_GROUP(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK)
46517 
46518 #define I3C_SCAPABILITIES2_AASA_MASK             (0x200000U)
46519 #define I3C_SCAPABILITIES2_AASA_SHIFT            (21U)
46520 /*! AASA - SETAASA
46521  *  0b1..SETAASA supported
46522  *  0b0..SETAASA not supported
46523  */
46524 #define I3C_SCAPABILITIES2_AASA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK)
46525 
46526 #define I3C_SCAPABILITIES2_SSTSUB_MASK           (0x400000U)
46527 #define I3C_SCAPABILITIES2_SSTSUB_SHIFT          (22U)
46528 /*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable
46529  *  0b1..Subscriber capable
46530  *  0b0..Not subscriber capable
46531  */
46532 #define I3C_SCAPABILITIES2_SSTSUB(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK)
46533 
46534 #define I3C_SCAPABILITIES2_SSTWR_MASK            (0x800000U)
46535 #define I3C_SCAPABILITIES2_SSTWR_SHIFT           (23U)
46536 /*! SSTWR - Target-Target(s)-Tunnel Write Capable
46537  *  0b1..Write capable
46538  *  0b0..Not write capable
46539  */
46540 #define I3C_SCAPABILITIES2_SSTWR(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK)
46541 /*! @} */
46542 
46543 /*! @name SCAPABILITIES - Target Capabilities */
46544 /*! @{ */
46545 
46546 #define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
46547 #define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
46548 /*! IDENA - ID 48b Handler
46549  *  0b00..Application
46550  *  0b01..Hardware
46551  *  0b10..Hardware, but the I3C module instance handles ID 48b
46552  *  0b11..A part number register (PARTNO)
46553  */
46554 #define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
46555 
46556 #define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
46557 #define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
46558 /*! IDREG - ID Register
46559  *  0b0000..All ID register features disabled
46560  *  0bxxx1..ID Instance is a register; used if there is no PARTNO register
46561  *  0bxx1x..An ID Random field is available
46562  *  0bx1xx..A Device Characteristic Register (DCR) is available
46563  *  0b1xxx..A Bus Characteristics Register (BCR) is available
46564  */
46565 #define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
46566 
46567 #define I3C_SCAPABILITIES_HDRSUPP_MASK           (0xC0U)
46568 #define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
46569 /*! HDRSUPP - High Data Rate Support
46570  *  0b00..No HDR modes supported
46571  *  0b01..DDR mode supported
46572  *  *..
46573  */
46574 #define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
46575 
46576 #define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
46577 #define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
46578 /*! MASTER - Controller
46579  *  0b0..Not supported
46580  *  0b1..Supported
46581  */
46582 #define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
46583 
46584 #define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
46585 #define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
46586 /*! SADDR - Static Address
46587  *  0b00..No static address
46588  *  0b01..Static address is fixed in hardware
46589  *  0b10..Hardware controls the static address dynamically (for example, from the pin strap)
46590  *  0b11..SCONFIG register supplies the static address
46591  */
46592 #define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
46593 
46594 #define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
46595 #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
46596 /*! CCCHANDLE - Common Command Codes Handling
46597  *  0b0000..All handling features disabled
46598  *  0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items
46599  *  0bxx1x..The I3C module manages maximum read and write lengths, and max data speed
46600  *  0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE]
46601  *  0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO]
46602  */
46603 #define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
46604 
46605 #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
46606 #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
46607 /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events
46608  *  0b00000..Application cannot generate IBI, CR, or HJ
46609  *  0bxxxx1..Application can generate an IBI
46610  *  0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register
46611  *  0bxx1xx..Application can generate a controller request for a secondary controller
46612  *  0bx1xxx..Application can generate a Hot-Join event
46613  *  0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing
46614  */
46615 #define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
46616 
46617 #define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
46618 #define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
46619 /*! TIMECTRL - Time Control
46620  *  0b0..No time control supported
46621  *  0b1..At least one time-control type supported
46622  */
46623 #define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
46624 
46625 #define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
46626 #define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
46627 /*! EXTFIFO - External FIFO
46628  *  0b000..No external FIFO available
46629  *  0b001..Standard available or free external FIFO
46630  *  0b010..Request track external FIFO
46631  *  *..
46632  */
46633 #define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
46634 
46635 #define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
46636 #define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
46637 /*! FIFOTX - FIFO Transmit
46638  *  0b00..Two
46639  *  0b01..Four
46640  *  0b10..Eight
46641  *  0b11..16 or larger
46642  */
46643 #define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
46644 
46645 #define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
46646 #define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
46647 /*! FIFORX - FIFO Receive
46648  *  0b00..Two or three
46649  *  0b01..Four
46650  *  0b10..Eight
46651  *  0b11..16 or larger
46652  */
46653 #define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
46654 
46655 #define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
46656 #define I3C_SCAPABILITIES_INT_SHIFT              (30U)
46657 /*! INT - Interrupts
46658  *  0b1..Supported
46659  *  0b0..Not supported
46660  */
46661 #define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
46662 
46663 #define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
46664 #define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
46665 /*! DMA - Direct Memory Access
46666  *  0b1..Supported
46667  *  0b0..Not supported
46668  */
46669 #define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
46670 /*! @} */
46671 
46672 /*! @name SMAXLIMITS - Target Maximum Limits */
46673 /*! @{ */
46674 
46675 #define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
46676 #define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
46677 /*! MAXRD - Maximum Read Length */
46678 #define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
46679 
46680 #define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
46681 #define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
46682 /*! MAXWR - Maximum Write Length */
46683 #define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
46684 /*! @} */
46685 
46686 /*! @name SIDPARTNO - Target ID Part Number */
46687 /*! @{ */
46688 
46689 #define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
46690 #define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
46691 /*! PARTNO - Part Number */
46692 #define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
46693 /*! @} */
46694 
46695 /*! @name SIDEXT - Target ID Extension */
46696 /*! @{ */
46697 
46698 #define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
46699 #define I3C_SIDEXT_DCR_SHIFT                     (8U)
46700 /*! DCR - Device Characteristic Register */
46701 #define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
46702 
46703 #define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
46704 #define I3C_SIDEXT_BCR_SHIFT                     (16U)
46705 /*! BCR - Bus Characteristics Register */
46706 #define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
46707 /*! @} */
46708 
46709 /*! @name SVENDORID - Target Vendor ID */
46710 /*! @{ */
46711 
46712 #define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
46713 #define I3C_SVENDORID_VID_SHIFT                  (0U)
46714 /*! VID - Vendor ID */
46715 #define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
46716 /*! @} */
46717 
46718 /*! @name STCCLOCK - Target Time Control Clock */
46719 /*! @{ */
46720 
46721 #define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
46722 #define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
46723 /*! ACCURACY - Clock Accuracy */
46724 #define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
46725 
46726 #define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
46727 #define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
46728 /*! FREQ - Clock Frequency */
46729 #define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
46730 /*! @} */
46731 
46732 /*! @name SMSGMAPADDR - Target Message Map Address */
46733 /*! @{ */
46734 
46735 #define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
46736 #define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
46737 /*! MAPLAST - Matched Address Index */
46738 #define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
46739 
46740 #define I3C_SMSGMAPADDR_LASTSTATIC_MASK          (0x10U)
46741 #define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT         (4U)
46742 /*! LASTSTATIC - Last Static Address Matched
46743  *  0b1..I2C static address
46744  *  0b0..I3C dynamic address
46745  */
46746 #define I3C_SMSGMAPADDR_LASTSTATIC(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK)
46747 
46748 #define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
46749 #define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
46750 /*! MAPLASTM1 - Matched Previous Address Index 1 */
46751 #define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
46752 
46753 #define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
46754 #define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
46755 /*! MAPLASTM2 - Matched Previous Index 2 */
46756 #define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
46757 /*! @} */
46758 
46759 /*! @name MCTRL - Controller Control */
46760 /*! @{ */
46761 
46762 #define I3C_MCTRL_REQUEST_MASK                   (0x7U)
46763 #define I3C_MCTRL_REQUEST_SHIFT                  (0U)
46764 /*! REQUEST - Request
46765  *  0b000..NONE
46766  *  0b001..EMITSTARTADDR
46767  *  0b010..EMITSTOP
46768  *  0b011..IBIACKNACK
46769  *  0b100..PROCESSDAA
46770  *  0b101..
46771  *  0b110..Force Exit and Target Reset
46772  *  0b111..AUTOIBI
46773  */
46774 #define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
46775 
46776 #define I3C_MCTRL_TYPE_MASK                      (0x30U)
46777 #define I3C_MCTRL_TYPE_SHIFT                     (4U)
46778 /*! TYPE - Bus Type with EmitStartAddr
46779  *  0b00..I3C
46780  *  0b01..I2C
46781  *  0b10..DDR
46782  *  0b11..
46783  */
46784 #define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
46785 
46786 #define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
46787 #define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
46788 /*! IBIRESP - In-Band Interrupt Response
46789  *  0b00..ACK (acknowledge)
46790  *  0b01..NACK (reject)
46791  *  0b10..Acknowledge with mandatory byte
46792  *  0b11..Manual
46793  */
46794 #define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
46795 
46796 #define I3C_MCTRL_DIR_MASK                       (0x100U)
46797 #define I3C_MCTRL_DIR_SHIFT                      (8U)
46798 /*! DIR - Direction
46799  *  0b0..Write
46800  *  0b1..Read
46801  */
46802 #define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
46803 
46804 #define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
46805 #define I3C_MCTRL_ADDR_SHIFT                     (9U)
46806 /*! ADDR - Address */
46807 #define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
46808 
46809 #define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
46810 #define I3C_MCTRL_RDTERM_SHIFT                   (16U)
46811 /*! RDTERM - Read Terminate Counter */
46812 #define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
46813 /*! @} */
46814 
46815 /*! @name MSTATUS - Controller Status */
46816 /*! @{ */
46817 
46818 #define I3C_MSTATUS_STATE_MASK                   (0x7U)
46819 #define I3C_MSTATUS_STATE_SHIFT                  (0U)
46820 /*! STATE - State of the Controller
46821  *  0b000..IDLE (bus has stopped)
46822  *  0b001..SLVREQ (target request)
46823  *  0b010..MSGSDR
46824  *  0b011..NORMACT
46825  *  0b100..MSGDDR
46826  *  0b101..DAA
46827  *  0b110..IBIACK
46828  *  0b111..IBIRCV
46829  */
46830 #define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
46831 
46832 #define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
46833 #define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
46834 /*! BETWEEN - Between
46835  *  0b0..Inactive (for other cases)
46836  *  0b1..Active
46837  */
46838 #define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
46839 
46840 #define I3C_MSTATUS_NACKED_MASK                  (0x20U)
46841 #define I3C_MSTATUS_NACKED_SHIFT                 (5U)
46842 /*! NACKED - Not Acknowledged
46843  *  0b1..NACKed (not acknowledged)
46844  *  0b0..Not NACKed
46845  */
46846 #define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
46847 
46848 #define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
46849 #define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
46850 /*! IBITYPE - In-Band Interrupt (IBI) Type
46851  *  0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0)
46852  *  0b01..IBI
46853  *  0b10..CR
46854  *  0b11..HJ
46855  */
46856 #define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
46857 
46858 #define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
46859 #define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
46860 /*! SLVSTART - Target Start Flag
46861  *  0b1..Target requesting START
46862  *  0b0..Target not requesting START
46863  *  0b0..No effect
46864  *  0b1..Clear the flag
46865  */
46866 #define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
46867 
46868 #define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
46869 #define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
46870 /*! MCTRLDONE - Controller Control Done Flag
46871  *  0b1..Done
46872  *  0b0..Not done
46873  *  0b0..No effect
46874  *  0b1..Clear the flag
46875  */
46876 #define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
46877 
46878 #define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
46879 #define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
46880 /*! COMPLETE - Complete Flag
46881  *  0b1..Complete
46882  *  0b0..Not complete
46883  *  0b0..No effect
46884  *  0b1..Clear the flag
46885  */
46886 #define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
46887 
46888 #define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
46889 #define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
46890 /*! RXPEND - RXPEND
46891  *  0b1..Receive message pending
46892  *  0b0..No receive message pending
46893  */
46894 #define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
46895 
46896 #define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
46897 #define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
46898 /*! TXNOTFULL - TX Buffer or FIFO Not Full
46899  *  0b1..Receive buffer or FIFO not full
46900  *  0b0..Receive buffer or FIFO full
46901  */
46902 #define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
46903 
46904 #define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
46905 #define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
46906 /*! IBIWON - In-Band Interrupt (IBI) Won Flag
46907  *  0b1..IBI arbitration won
46908  *  0b0..No IBI arbitration won
46909  *  0b0..No effect
46910  *  0b1..Clear the flag
46911  */
46912 #define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
46913 
46914 #define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
46915 #define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
46916 /*! ERRWARN - Error or Warning
46917  *  0b1..Error or warning
46918  *  0b0..No error or warning
46919  */
46920 #define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
46921 
46922 #define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
46923 #define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
46924 /*! NOWMASTER - Module is now Controller Flag
46925  *  0b1..Controller
46926  *  0b0..Not a controller
46927  *  0b0..No effect
46928  *  0b1..Clear the flag
46929  */
46930 #define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
46931 
46932 #define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
46933 #define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
46934 /*! IBIADDR - IBI Address */
46935 #define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
46936 /*! @} */
46937 
46938 /*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */
46939 /*! @{ */
46940 
46941 #define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
46942 #define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
46943 /*! ADDR0 - ADDR0 */
46944 #define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
46945 
46946 #define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
46947 #define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
46948 /*! ADDR1 - ADDR1 */
46949 #define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
46950 
46951 #define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
46952 #define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
46953 /*! ADDR2 - ADDR2 */
46954 #define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
46955 
46956 #define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
46957 #define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
46958 /*! ADDR3 - ADDR3 */
46959 #define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
46960 
46961 #define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
46962 #define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
46963 /*! ADDR4 - ADDR4 */
46964 #define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
46965 
46966 #define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
46967 #define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
46968 /*! MSB0 - Most Significant Address Bit is 0
46969  *  0b1..MSB is 0
46970  *  0b0..MSB is not 0
46971  */
46972 #define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
46973 
46974 #define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
46975 #define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
46976 /*! NOBYTE - No IBI byte
46977  *  0b1..Without mandatory IBI byte
46978  *  0b0..With mandatory IBI byte
46979  */
46980 #define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
46981 /*! @} */
46982 
46983 /*! @name MINTSET - Controller Interrupt Set */
46984 /*! @{ */
46985 
46986 #define I3C_MINTSET_SLVSTART_MASK                (0x100U)
46987 #define I3C_MINTSET_SLVSTART_SHIFT               (8U)
46988 /*! SLVSTART - Target Start Interrupt Enable
46989  *  0b1..Enable
46990  *  0b0..Disable
46991  */
46992 #define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
46993 
46994 #define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
46995 #define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
46996 /*! MCTRLDONE - Controller Control Done Interrupt Enable
46997  *  0b1..Enable
46998  *  0b0..Disable
46999  */
47000 #define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
47001 
47002 #define I3C_MINTSET_COMPLETE_MASK                (0x400U)
47003 #define I3C_MINTSET_COMPLETE_SHIFT               (10U)
47004 /*! COMPLETE - Completed Message Interrupt Enable
47005  *  0b1..Enable
47006  *  0b0..Disable
47007  */
47008 #define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
47009 
47010 #define I3C_MINTSET_RXPEND_MASK                  (0x800U)
47011 #define I3C_MINTSET_RXPEND_SHIFT                 (11U)
47012 /*! RXPEND - Receive Pending Interrupt Enable */
47013 #define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
47014 
47015 #define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
47016 #define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
47017 /*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable
47018  *  0b1..Enable
47019  *  0b0..Disable
47020  */
47021 #define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
47022 
47023 #define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
47024 #define I3C_MINTSET_IBIWON_SHIFT                 (13U)
47025 /*! IBIWON - IBI Won Interrupt Enable
47026  *  0b1..Enable
47027  *  0b0..Disable
47028  */
47029 #define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
47030 
47031 #define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
47032 #define I3C_MINTSET_ERRWARN_SHIFT                (15U)
47033 /*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable
47034  *  0b1..Enable
47035  *  0b0..Disable
47036  */
47037 #define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
47038 
47039 #define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
47040 #define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
47041 /*! NOWMASTER - Now Controller Interrupt Enable
47042  *  0b1..Enable
47043  *  0b0..Disable
47044  */
47045 #define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
47046 /*! @} */
47047 
47048 /*! @name MINTCLR - Controller Interrupt Clear */
47049 /*! @{ */
47050 
47051 #define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
47052 #define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
47053 /*! SLVSTART - SLVSTART Interrupt Enable Clear Flag
47054  *  0b1..Interrupt enable cleared
47055  *  0b0..No effect
47056  *  0b0..No effect
47057  *  0b1..Clear the flag
47058  */
47059 #define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
47060 
47061 #define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
47062 #define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
47063 /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag
47064  *  0b1..Interrupt enable cleared
47065  *  0b0..No effect
47066  *  0b0..No effect
47067  *  0b1..Clear the flag
47068  */
47069 #define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
47070 
47071 #define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
47072 #define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
47073 /*! COMPLETE - COMPLETE Interrupt Enable Clear Flag
47074  *  0b1..Interrupt enable cleared
47075  *  0b0..No effect
47076  *  0b0..No effect
47077  *  0b1..Clear the flag
47078  */
47079 #define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
47080 
47081 #define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
47082 #define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
47083 /*! RXPEND - RXPEND Interrupt Enable Clear Flag
47084  *  0b1..Interrupt enable cleared
47085  *  0b0..No effect
47086  *  0b0..No effect
47087  *  0b1..Clear the flag
47088  */
47089 #define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
47090 
47091 #define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
47092 #define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
47093 /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag
47094  *  0b1..Interrupt enable cleared
47095  *  0b0..No effect
47096  *  0b0..No effect
47097  *  0b1..Clear the flag
47098  */
47099 #define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
47100 
47101 #define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
47102 #define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
47103 /*! IBIWON - IBIWON Interrupt Enable Clear Flag
47104  *  0b1..Interrupt enable cleared
47105  *  0b0..No effect
47106  *  0b0..No effect
47107  *  0b1..Clear the flag
47108  */
47109 #define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
47110 
47111 #define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
47112 #define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
47113 /*! ERRWARN - ERRWARN Interrupt Enable Clear Flag
47114  *  0b1..Interrupt enable cleared
47115  *  0b0..No effect
47116  *  0b0..No effect
47117  *  0b1..Clear the flag
47118  */
47119 #define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
47120 
47121 #define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
47122 #define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
47123 /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag
47124  *  0b1..Interrupt enable cleared
47125  *  0b0..No effect
47126  *  0b0..No effect
47127  *  0b1..Clear the flag
47128  */
47129 #define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
47130 /*! @} */
47131 
47132 /*! @name MINTMASKED - Controller Interrupt Mask */
47133 /*! @{ */
47134 
47135 #define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
47136 #define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
47137 /*! SLVSTART - SLVSTART Interrupt Mask
47138  *  0b1..Enabled
47139  *  0b0..Disabled
47140  */
47141 #define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
47142 
47143 #define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
47144 #define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
47145 /*! MCTRLDONE - MCTRLDONE Interrupt Mask
47146  *  0b1..Enabled
47147  *  0b0..Disabled
47148  */
47149 #define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
47150 
47151 #define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
47152 #define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
47153 /*! COMPLETE - COMPLETE Interrupt Mask
47154  *  0b1..Enabled
47155  *  0b0..Disabled
47156  */
47157 #define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
47158 
47159 #define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
47160 #define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
47161 /*! RXPEND - RXPEND Interrupt Mask */
47162 #define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
47163 
47164 #define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
47165 #define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
47166 /*! TXNOTFULL - TXNOTFULL Interrupt Mask
47167  *  0b1..Enabled
47168  *  0b0..Disabled
47169  */
47170 #define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
47171 
47172 #define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
47173 #define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
47174 /*! IBIWON - IBIWON Interrupt Mask
47175  *  0b1..Enabled
47176  *  0b0..Disabled
47177  */
47178 #define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
47179 
47180 #define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
47181 #define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
47182 /*! ERRWARN - ERRWARN Interrupt Mask
47183  *  0b1..Enabled
47184  *  0b0..Disabled
47185  */
47186 #define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
47187 
47188 #define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
47189 #define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
47190 /*! NOWMASTER - NOWCONTROLLER Interrupt Mask
47191  *  0b1..Enabled
47192  *  0b0..Disabled
47193  */
47194 #define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
47195 /*! @} */
47196 
47197 /*! @name MERRWARN - Controller Errors and Warnings */
47198 /*! @{ */
47199 
47200 #define I3C_MERRWARN_NACK_MASK                   (0x4U)
47201 #define I3C_MERRWARN_NACK_SHIFT                  (2U)
47202 /*! NACK - Not Acknowledge Error Flag
47203  *  0b1..Error
47204  *  0b0..No error
47205  *  0b0..No effect
47206  *  0b1..Clear the flag
47207  */
47208 #define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
47209 
47210 #define I3C_MERRWARN_WRABT_MASK                  (0x8U)
47211 #define I3C_MERRWARN_WRABT_SHIFT                 (3U)
47212 /*! WRABT - Write Abort Error Flag
47213  *  0b1..Error
47214  *  0b0..No error
47215  *  0b0..No effect
47216  *  0b1..Clear the flag
47217  */
47218 #define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
47219 
47220 #define I3C_MERRWARN_HPAR_MASK                   (0x200U)
47221 #define I3C_MERRWARN_HPAR_SHIFT                  (9U)
47222 /*! HPAR - High Data Rate Parity Flag
47223  *  0b1..Error
47224  *  0b0..No error
47225  *  0b0..No effect
47226  *  0b1..Clear the flag
47227  */
47228 #define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
47229 
47230 #define I3C_MERRWARN_HCRC_MASK                   (0x400U)
47231 #define I3C_MERRWARN_HCRC_SHIFT                  (10U)
47232 /*! HCRC - High Data Rate CRC Error Flag
47233  *  0b1..Error
47234  *  0b0..No error
47235  *  0b0..No effect
47236  *  0b1..Clear the flag
47237  */
47238 #define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
47239 
47240 #define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
47241 #define I3C_MERRWARN_OREAD_SHIFT                 (16U)
47242 /*! OREAD - Overread Error Flag
47243  *  0b1..Error
47244  *  0b0..No error
47245  *  0b0..No effect
47246  *  0b1..Clear the flag
47247  */
47248 #define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
47249 
47250 #define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
47251 #define I3C_MERRWARN_OWRITE_SHIFT                (17U)
47252 /*! OWRITE - Overwrite Error Flag
47253  *  0b1..Error
47254  *  0b0..No error
47255  *  0b0..No effect
47256  *  0b1..Clear the flag
47257  */
47258 #define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
47259 
47260 #define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
47261 #define I3C_MERRWARN_MSGERR_SHIFT                (18U)
47262 /*! MSGERR - Message Error Flag
47263  *  0b1..Error
47264  *  0b0..No error
47265  *  0b0..No effect
47266  *  0b1..Clear the flag
47267  */
47268 #define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
47269 
47270 #define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
47271 #define I3C_MERRWARN_INVREQ_SHIFT                (19U)
47272 /*! INVREQ - Invalid Request Error Flag
47273  *  0b1..Error
47274  *  0b0..No error
47275  *  0b0..No effect
47276  *  0b1..Clear the flag
47277  */
47278 #define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
47279 
47280 #define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
47281 #define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
47282 /*! TIMEOUT - Timeout Error Flag
47283  *  0b1..Error
47284  *  0b0..No error
47285  *  0b0..No effect
47286  *  0b1..Clear the flag
47287  */
47288 #define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
47289 /*! @} */
47290 
47291 /*! @name MDMACTRL - Controller DMA Control */
47292 /*! @{ */
47293 
47294 #define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
47295 #define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
47296 /*! DMAFB - DMA from Bus
47297  *  0b00..DMA not used
47298  *  0b01..Enable DMA for one frame
47299  *  0b10..Enable DMA until DMA is turned off
47300  *  0b11..
47301  */
47302 #define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
47303 
47304 #define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
47305 #define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
47306 /*! DMATB - DMA to Bus
47307  *  0b00..DMA not used
47308  *  0b01..Enable DMA for one frame (ended by DMA or terminated)
47309  *  0b10..Enable DMA until DMA is turned off
47310  *  0b11..
47311  */
47312 #define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
47313 
47314 #define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
47315 #define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
47316 /*! DMAWIDTH - DMA Width
47317  *  0b00, 0b01..Byte
47318  *  0b10..Halfword (16 bits)
47319  *  0b11..
47320  */
47321 #define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
47322 /*! @} */
47323 
47324 /*! @name MDATACTRL - Controller Data Control */
47325 /*! @{ */
47326 
47327 #define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
47328 #define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
47329 /*! FLUSHTB - Flush To-Bus Buffer or FIFO
47330  *  0b1..Flush the buffer
47331  *  0b0..No action
47332  */
47333 #define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
47334 
47335 #define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
47336 #define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
47337 /*! FLUSHFB - Flush From-Bus Buffer or FIFO
47338  *  0b1..Flush the buffer
47339  *  0b0..No action
47340  */
47341 #define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
47342 
47343 #define I3C_MDATACTRL_UNLOCK_MASK                (0x8U)
47344 #define I3C_MDATACTRL_UNLOCK_SHIFT               (3U)
47345 /*! UNLOCK - Unlock
47346  *  0b0..Locked
47347  *  0b1..Unlocked
47348  */
47349 #define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
47350 
47351 #define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
47352 #define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
47353 /*! TXTRIG - Transmit Trigger Level
47354  *  0b00..Trigger when empty
47355  *  0b01..Trigger when 1/4 full or less
47356  *  0b10..Trigger when 1/2 full or less
47357  *  0b11..Trigger when 1 less than full or less (default)
47358  */
47359 #define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
47360 
47361 #define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
47362 #define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
47363 /*! RXTRIG - Receive Trigger Level
47364  *  0b00..Trigger when not empty
47365  *  0b01..Trigger when 1/4 full or more
47366  *  0b10..Trigger when 1/2 full or more
47367  *  0b11..Trigger when 3/4 full or more
47368  */
47369 #define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
47370 
47371 #define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
47372 #define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
47373 /*! TXCOUNT - Transmit Byte Count */
47374 #define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
47375 
47376 #define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
47377 #define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
47378 /*! RXCOUNT - Receive Byte Count */
47379 #define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
47380 
47381 #define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
47382 #define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
47383 /*! TXFULL - Transmit is Full
47384  *  0b0..Not full
47385  *  0b1..Full
47386  */
47387 #define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
47388 
47389 #define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
47390 #define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
47391 /*! RXEMPTY - Receive is Empty
47392  *  0b0..Not empty
47393  *  0b1..Empty
47394  */
47395 #define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
47396 /*! @} */
47397 
47398 /*! @name MWDATAB - Controller Write Data Byte */
47399 /*! @{ */
47400 
47401 #define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
47402 #define I3C_MWDATAB_VALUE_SHIFT                  (0U)
47403 /*! VALUE - Data Byte */
47404 #define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
47405 
47406 #define I3C_MWDATAB_END_MASK                     (0x100U)
47407 #define I3C_MWDATAB_END_SHIFT                    (8U)
47408 /*! END - End of Message
47409  *  0b0..Not the end
47410  *  0b1..End
47411  */
47412 #define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
47413 
47414 #define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
47415 #define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
47416 /*! END_ALSO - End of Message ALSO
47417  *  0b0..Not the end
47418  *  0b1..End
47419  */
47420 #define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
47421 /*! @} */
47422 
47423 /*! @name MWDATABE - Controller Write Data Byte End */
47424 /*! @{ */
47425 
47426 #define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
47427 #define I3C_MWDATABE_VALUE_SHIFT                 (0U)
47428 /*! VALUE - Data */
47429 #define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
47430 /*! @} */
47431 
47432 /*! @name MWDATAH - Controller Write Data Halfword */
47433 /*! @{ */
47434 
47435 #define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
47436 #define I3C_MWDATAH_DATA0_SHIFT                  (0U)
47437 /*! DATA0 - Data Byte 0 */
47438 #define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
47439 
47440 #define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
47441 #define I3C_MWDATAH_DATA1_SHIFT                  (8U)
47442 /*! DATA1 - Data Byte 1 */
47443 #define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
47444 
47445 #define I3C_MWDATAH_END_MASK                     (0x10000U)
47446 #define I3C_MWDATAH_END_SHIFT                    (16U)
47447 /*! END - End of Message
47448  *  0b0..Not the end
47449  *  0b1..End
47450  */
47451 #define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
47452 /*! @} */
47453 
47454 /*! @name MWDATAHE - Controller Write Data Halfword End */
47455 /*! @{ */
47456 
47457 #define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
47458 #define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
47459 /*! DATA0 - Data Byte 0 */
47460 #define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
47461 
47462 #define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
47463 #define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
47464 /*! DATA1 - Data Byte 1 */
47465 #define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
47466 /*! @} */
47467 
47468 /*! @name MRDATAB - Controller Read Data Byte */
47469 /*! @{ */
47470 
47471 #define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
47472 #define I3C_MRDATAB_VALUE_SHIFT                  (0U)
47473 /*! VALUE - Value */
47474 #define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
47475 /*! @} */
47476 
47477 /*! @name MRDATAH - Controller Read Data Halfword */
47478 /*! @{ */
47479 
47480 #define I3C_MRDATAH_LSB_MASK                     (0xFFU)
47481 #define I3C_MRDATAH_LSB_SHIFT                    (0U)
47482 /*! LSB - Low Byte */
47483 #define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
47484 
47485 #define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
47486 #define I3C_MRDATAH_MSB_SHIFT                    (8U)
47487 /*! MSB - High Byte */
47488 #define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
47489 /*! @} */
47490 
47491 /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */
47492 /*! @{ */
47493 
47494 #define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
47495 #define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
47496 /*! VALUE - Value */
47497 #define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
47498 /*! @} */
47499 
47500 /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */
47501 /*! @{ */
47502 
47503 #define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
47504 #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
47505 /*! DIR - Direction
47506  *  0b0..Write
47507  *  0b1..Read
47508  */
47509 #define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
47510 
47511 #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
47512 #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
47513 /*! ADDR - Address */
47514 #define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
47515 
47516 #define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
47517 #define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
47518 /*! END - End of SDR Message
47519  *  0b0..Not the end
47520  *  0b1..End
47521  */
47522 #define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
47523 
47524 #define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
47525 #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
47526 /*! I2C - I2C
47527  *  0b0..I3C message
47528  *  0b1..I2C message
47529  */
47530 #define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
47531 
47532 #define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
47533 #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
47534 /*! LEN - Length */
47535 #define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
47536 /*! @} */
47537 
47538 /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */
47539 /*! @{ */
47540 
47541 #define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
47542 #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
47543 /*! DATA16B - Data */
47544 #define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
47545 /*! @} */
47546 
47547 /*! @name MRMSG_SDR - Controller Read Message in SDR mode */
47548 /*! @{ */
47549 
47550 #define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
47551 #define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
47552 /*! DATA - Data */
47553 #define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
47554 /*! @} */
47555 
47556 /*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */
47557 /*! @{ */
47558 
47559 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK       (0xFFFFU)
47560 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT      (0U)
47561 /*! ADDRCMD - Address Command */
47562 #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x)         (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK)
47563 /*! @} */
47564 
47565 /*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */
47566 /*! @{ */
47567 
47568 #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK          (0x3FFU)
47569 #define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT         (0U)
47570 /*! LEN - Length of Message */
47571 #define I3C_MWMSG_DDR_CONTROL2_LEN(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK)
47572 
47573 #define I3C_MWMSG_DDR_CONTROL2_END_MASK          (0x4000U)
47574 #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT         (14U)
47575 /*! END - End of Message
47576  *  0b1..End
47577  *  0b0..Not the end
47578  */
47579 #define I3C_MWMSG_DDR_CONTROL2_END(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK)
47580 /*! @} */
47581 
47582 /*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */
47583 /*! @{ */
47584 
47585 #define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
47586 #define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
47587 /*! DATA16B - Data */
47588 #define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
47589 /*! @} */
47590 
47591 /*! @name MRMSG_DDR - Controller Read Message in DDR mode */
47592 /*! @{ */
47593 
47594 #define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
47595 #define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
47596 /*! DATA - Data */
47597 #define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
47598 /*! @} */
47599 
47600 /*! @name MDYNADDR - Controller Dynamic Address */
47601 /*! @{ */
47602 
47603 #define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
47604 #define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
47605 /*! DAVALID - Dynamic Address Valid
47606  *  0b1..Valid DA assigned
47607  *  0b0..No valid DA assigned
47608  */
47609 #define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
47610 
47611 #define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
47612 #define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
47613 /*! DADDR - Dynamic Address */
47614 #define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
47615 /*! @} */
47616 
47617 /*! @name SRSTACTTIME - Timing Rules for Target Reset Recovery */
47618 /*! @{ */
47619 
47620 #define I3C_SRSTACTTIME_PERRSTTIM_MASK           (0xFFU)
47621 #define I3C_SRSTACTTIME_PERRSTTIM_SHIFT          (0U)
47622 /*! PERRSTTIM - Time to Recover from the I3C Peripheral */
47623 #define I3C_SRSTACTTIME_PERRSTTIM(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_PERRSTTIM_SHIFT)) & I3C_SRSTACTTIME_PERRSTTIM_MASK)
47624 
47625 #define I3C_SRSTACTTIME_SYSRSTTIM_MASK           (0xFF00U)
47626 #define I3C_SRSTACTTIME_SYSRSTTIM_SHIFT          (8U)
47627 /*! SYSRSTTIM - Time to Recover from Chip Reset */
47628 #define I3C_SRSTACTTIME_SYSRSTTIM(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_SYSRSTTIM_SHIFT)) & I3C_SRSTACTTIME_SYSRSTTIM_MASK)
47629 /*! @} */
47630 
47631 /*! @name SCCCMASK - CCC Mask for Unhandled CCCs */
47632 /*! @{ */
47633 
47634 #define I3C_SCCCMASK_BASE_MASK                   (0x1U)
47635 #define I3C_SCCCMASK_BASE_SHIFT                  (0U)
47636 /*! BASE - Base
47637  *  0b0..Suppressed
47638  *  0b1..Passed to application
47639  */
47640 #define I3C_SCCCMASK_BASE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASE_SHIFT)) & I3C_SCCCMASK_BASE_MASK)
47641 
47642 #define I3C_SCCCMASK_BASEBX_MASK                 (0x2U)
47643 #define I3C_SCCCMASK_BASEBX_SHIFT                (1U)
47644 /*! BASEBX - BASEBX
47645  *  0b0..Suppressed
47646  *  0b1..Passed to application
47647  */
47648 #define I3C_SCCCMASK_BASEBX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEBX_SHIFT)) & I3C_SCCCMASK_BASEBX_MASK)
47649 
47650 #define I3C_SCCCMASK_BASEDX_MASK                 (0x4U)
47651 #define I3C_SCCCMASK_BASEDX_SHIFT                (2U)
47652 /*! BASEDX - BASEDX
47653  *  0b0..Suppressed
47654  *  0b1..Passed to application
47655  */
47656 #define I3C_SCCCMASK_BASEDX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEDX_SHIFT)) & I3C_SCCCMASK_BASEDX_MASK)
47657 
47658 #define I3C_SCCCMASK_MEXTB_MASK                  (0x8U)
47659 #define I3C_SCCCMASK_MEXTB_SHIFT                 (3U)
47660 /*! MEXTB - MEXTB
47661  *  0b0..Suppressed
47662  *  0b1..Passed to application
47663  */
47664 #define I3C_SCCCMASK_MEXTB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTB_SHIFT)) & I3C_SCCCMASK_MEXTB_MASK)
47665 
47666 #define I3C_SCCCMASK_MEXTD_MASK                  (0x10U)
47667 #define I3C_SCCCMASK_MEXTD_SHIFT                 (4U)
47668 /*! MEXTD - MEXTD
47669  *  0b0..Suppressed
47670  *  0b1..Passed to application
47671  */
47672 #define I3C_SCCCMASK_MEXTD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTD_SHIFT)) & I3C_SCCCMASK_MEXTD_MASK)
47673 
47674 #define I3C_SCCCMASK_VENDB_MASK                  (0x20U)
47675 #define I3C_SCCCMASK_VENDB_SHIFT                 (5U)
47676 /*! VENDB - VENDB
47677  *  0b0..Suppressed
47678  *  0b1..Passed to application
47679  */
47680 #define I3C_SCCCMASK_VENDB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDB_SHIFT)) & I3C_SCCCMASK_VENDB_MASK)
47681 
47682 #define I3C_SCCCMASK_VENDD_MASK                  (0x40U)
47683 #define I3C_SCCCMASK_VENDD_SHIFT                 (6U)
47684 /*! VENDD - VENDD
47685  *  0b0..Suppressed
47686  *  0b1..Passed to application
47687  */
47688 #define I3C_SCCCMASK_VENDD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDD_SHIFT)) & I3C_SCCCMASK_VENDD_MASK)
47689 /*! @} */
47690 
47691 /*! @name SERRWARNMASK - Target Errors and Warnings Mask */
47692 /*! @{ */
47693 
47694 #define I3C_SERRWARNMASK_ORUN_MASK               (0x1U)
47695 #define I3C_SERRWARNMASK_ORUN_SHIFT              (0U)
47696 /*! ORUN - ORUN Mask
47697  *  0b1..Allow
47698  *  0b0..Deny
47699  */
47700 #define I3C_SERRWARNMASK_ORUN(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_ORUN_SHIFT)) & I3C_SERRWARNMASK_ORUN_MASK)
47701 
47702 #define I3C_SERRWARNMASK_URUN_MASK               (0x2U)
47703 #define I3C_SERRWARNMASK_URUN_SHIFT              (1U)
47704 /*! URUN - URUN Mask
47705  *  0b1..Allow
47706  *  0b0..Deny
47707  */
47708 #define I3C_SERRWARNMASK_URUN(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUN_SHIFT)) & I3C_SERRWARNMASK_URUN_MASK)
47709 
47710 #define I3C_SERRWARNMASK_URUNNACK_MASK           (0x4U)
47711 #define I3C_SERRWARNMASK_URUNNACK_SHIFT          (2U)
47712 /*! URUNNACK - URUNNACK Mask
47713  *  0b1..Allow
47714  *  0b0..Deny
47715  */
47716 #define I3C_SERRWARNMASK_URUNNACK(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUNNACK_SHIFT)) & I3C_SERRWARNMASK_URUNNACK_MASK)
47717 
47718 #define I3C_SERRWARNMASK_TERM_MASK               (0x8U)
47719 #define I3C_SERRWARNMASK_TERM_SHIFT              (3U)
47720 /*! TERM - TERM Mask
47721  *  0b1..Allow
47722  *  0b0..Deny
47723  */
47724 #define I3C_SERRWARNMASK_TERM(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_TERM_SHIFT)) & I3C_SERRWARNMASK_TERM_MASK)
47725 
47726 #define I3C_SERRWARNMASK_INVSTART_MASK           (0x10U)
47727 #define I3C_SERRWARNMASK_INVSTART_SHIFT          (4U)
47728 /*! INVSTART - INVSTART Mask
47729  *  0b1..Allow
47730  *  0b0..Deny
47731  */
47732 #define I3C_SERRWARNMASK_INVSTART(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_INVSTART_SHIFT)) & I3C_SERRWARNMASK_INVSTART_MASK)
47733 
47734 #define I3C_SERRWARNMASK_SPAR_MASK               (0x100U)
47735 #define I3C_SERRWARNMASK_SPAR_SHIFT              (8U)
47736 /*! SPAR - SPAR Mask
47737  *  0b1..Allow
47738  *  0b0..Deny
47739  */
47740 #define I3C_SERRWARNMASK_SPAR(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_SPAR_SHIFT)) & I3C_SERRWARNMASK_SPAR_MASK)
47741 
47742 #define I3C_SERRWARNMASK_HPAR_MASK               (0x200U)
47743 #define I3C_SERRWARNMASK_HPAR_SHIFT              (9U)
47744 /*! HPAR - HPAR Mask
47745  *  0b1..Allow
47746  *  0b0..Deny
47747  */
47748 #define I3C_SERRWARNMASK_HPAR(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HPAR_SHIFT)) & I3C_SERRWARNMASK_HPAR_MASK)
47749 
47750 #define I3C_SERRWARNMASK_HCRC_MASK               (0x400U)
47751 #define I3C_SERRWARNMASK_HCRC_SHIFT              (10U)
47752 /*! HCRC - HCRC Mask
47753  *  0b1..Allow
47754  *  0b0..Deny
47755  */
47756 #define I3C_SERRWARNMASK_HCRC(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HCRC_SHIFT)) & I3C_SERRWARNMASK_HCRC_MASK)
47757 
47758 #define I3C_SERRWARNMASK_S0S1_MASK               (0x800U)
47759 #define I3C_SERRWARNMASK_S0S1_SHIFT              (11U)
47760 /*! S0S1 - S0S1 Mask
47761  *  0b1..Allow
47762  *  0b0..Deny
47763  */
47764 #define I3C_SERRWARNMASK_S0S1(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_S0S1_SHIFT)) & I3C_SERRWARNMASK_S0S1_MASK)
47765 /*! @} */
47766 
47767 /*! @name SMAPCTRL0 - Map Feature Control 0 */
47768 /*! @{ */
47769 
47770 #define I3C_SMAPCTRL0_ENA_MASK                   (0x1U)
47771 #define I3C_SMAPCTRL0_ENA_SHIFT                  (0U)
47772 /*! ENA - Enable Primary Dynamic Address
47773  *  0b0..Disabled
47774  *  0b1..Enabled
47775  */
47776 #define I3C_SMAPCTRL0_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK)
47777 
47778 #define I3C_SMAPCTRL0_DA_MASK                    (0xFEU)
47779 #define I3C_SMAPCTRL0_DA_SHIFT                   (1U)
47780 /*! DA - Dynamic Address */
47781 #define I3C_SMAPCTRL0_DA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK)
47782 
47783 #define I3C_SMAPCTRL0_CAUSE_MASK                 (0x700U)
47784 #define I3C_SMAPCTRL0_CAUSE_SHIFT                (8U)
47785 /*! CAUSE - Cause
47786  *  0b000..No information (this value occurs when not configured to write DA)
47787  *  0b001..Set using ENTDAA
47788  *  0b010..Set using SETDASA, SETAASA, or SETNEWDA
47789  *  0b011..Cleared using RSTDAA
47790  *  0b100..Auto MAP change happened last
47791  *  *..
47792  */
47793 #define I3C_SMAPCTRL0_CAUSE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK)
47794 /*! @} */
47795 
47796 /*! @name SMAPCTRL1 - Map Feature Control 1 */
47797 /*! @{ */
47798 
47799 #define I3C_SMAPCTRL1_ENA_MASK                   (0x1U)
47800 #define I3C_SMAPCTRL1_ENA_SHIFT                  (0U)
47801 /*! ENA - Enable
47802  *  0b0..Disable
47803  *  0b1..Enable
47804  */
47805 #define I3C_SMAPCTRL1_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK)
47806 
47807 #define I3C_SMAPCTRL1_ADDR_MASK                  (0xFEU)
47808 #define I3C_SMAPCTRL1_ADDR_SHIFT                 (1U)
47809 /*! ADDR - Address */
47810 #define I3C_SMAPCTRL1_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK)
47811 
47812 #define I3C_SMAPCTRL1_MAPSA_MASK                 (0x100U)
47813 #define I3C_SMAPCTRL1_MAPSA_SHIFT                (8U)
47814 /*! MAPSA - MAP Static Address
47815  *  0b0..I3C dynamic address
47816  *  0b1..Static address (I2C style)
47817  */
47818 #define I3C_SMAPCTRL1_MAPSA(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK)
47819 
47820 #define I3C_SMAPCTRL1_SA10B_MASK                 (0xE00U)
47821 #define I3C_SMAPCTRL1_SA10B_SHIFT                (9U)
47822 /*! SA10B - Static Address 10-Bit Extension */
47823 #define I3C_SMAPCTRL1_SA10B(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_SA10B_SHIFT)) & I3C_SMAPCTRL1_SA10B_MASK)
47824 
47825 #define I3C_SMAPCTRL1_NACK_MASK                  (0x1000U)
47826 #define I3C_SMAPCTRL1_NACK_SHIFT                 (12U)
47827 /*! NACK - Not Acknowledged
47828  *  0b0..Do not always NACK messages
47829  *  0b1..Always NACK messages
47830  */
47831 #define I3C_SMAPCTRL1_NACK(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK)
47832 /*! @} */
47833 
47834 /*! @name IBIEXT1 - Extended IBI Data 1 */
47835 /*! @{ */
47836 
47837 #define I3C_IBIEXT1_CNT_MASK                     (0x7U)
47838 #define I3C_IBIEXT1_CNT_SHIFT                    (0U)
47839 /*! CNT - Count */
47840 #define I3C_IBIEXT1_CNT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK)
47841 
47842 #define I3C_IBIEXT1_MAX_MASK                     (0x70U)
47843 #define I3C_IBIEXT1_MAX_SHIFT                    (4U)
47844 /*! MAX - Maximum */
47845 #define I3C_IBIEXT1_MAX(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK)
47846 
47847 #define I3C_IBIEXT1_EXT1_MASK                    (0xFF00U)
47848 #define I3C_IBIEXT1_EXT1_SHIFT                   (8U)
47849 /*! EXT1 - Extra Byte 1 */
47850 #define I3C_IBIEXT1_EXT1(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK)
47851 
47852 #define I3C_IBIEXT1_EXT2_MASK                    (0xFF0000U)
47853 #define I3C_IBIEXT1_EXT2_SHIFT                   (16U)
47854 /*! EXT2 - Extra Byte 2 */
47855 #define I3C_IBIEXT1_EXT2(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK)
47856 
47857 #define I3C_IBIEXT1_EXT3_MASK                    (0xFF000000U)
47858 #define I3C_IBIEXT1_EXT3_SHIFT                   (24U)
47859 /*! EXT3 - Extra Byte 3 */
47860 #define I3C_IBIEXT1_EXT3(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK)
47861 /*! @} */
47862 
47863 /*! @name IBIEXT2 - Extended IBI Data 2 */
47864 /*! @{ */
47865 
47866 #define I3C_IBIEXT2_EXT4_MASK                    (0xFFU)
47867 #define I3C_IBIEXT2_EXT4_SHIFT                   (0U)
47868 /*! EXT4 - Extra Byte 4 */
47869 #define I3C_IBIEXT2_EXT4(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK)
47870 
47871 #define I3C_IBIEXT2_EXT5_MASK                    (0xFF00U)
47872 #define I3C_IBIEXT2_EXT5_SHIFT                   (8U)
47873 /*! EXT5 - Extra Byte 5 */
47874 #define I3C_IBIEXT2_EXT5(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK)
47875 
47876 #define I3C_IBIEXT2_EXT6_MASK                    (0xFF0000U)
47877 #define I3C_IBIEXT2_EXT6_SHIFT                   (16U)
47878 /*! EXT6 - Extra Byte 6 */
47879 #define I3C_IBIEXT2_EXT6(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK)
47880 
47881 #define I3C_IBIEXT2_EXT7_MASK                    (0xFF000000U)
47882 #define I3C_IBIEXT2_EXT7_SHIFT                   (24U)
47883 /*! EXT7 - Extra Byte 7 */
47884 #define I3C_IBIEXT2_EXT7(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK)
47885 /*! @} */
47886 
47887 
47888 /*!
47889  * @}
47890  */ /* end of group I3C_Register_Masks */
47891 
47892 
47893 /* I3C - Peripheral instance base addresses */
47894 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
47895   /** Peripheral I3C1 base address */
47896   #define I3C1_BASE                                (0x54330000u)
47897   /** Peripheral I3C1 base address */
47898   #define I3C1_BASE_NS                             (0x44330000u)
47899   /** Peripheral I3C1 base pointer */
47900   #define I3C1                                     ((I3C_Type *)I3C1_BASE)
47901   /** Peripheral I3C1 base pointer */
47902   #define I3C1_NS                                  ((I3C_Type *)I3C1_BASE_NS)
47903   /** Peripheral I3C2 base address */
47904   #define I3C2_BASE                                (0x52520000u)
47905   /** Peripheral I3C2 base address */
47906   #define I3C2_BASE_NS                             (0x42520000u)
47907   /** Peripheral I3C2 base pointer */
47908   #define I3C2                                     ((I3C_Type *)I3C2_BASE)
47909   /** Peripheral I3C2 base pointer */
47910   #define I3C2_NS                                  ((I3C_Type *)I3C2_BASE_NS)
47911   /** Array initializer of I3C peripheral base addresses */
47912   #define I3C_BASE_ADDRS                           { 0u, I3C1_BASE, I3C2_BASE }
47913   /** Array initializer of I3C peripheral base pointers */
47914   #define I3C_BASE_PTRS                            { (I3C_Type *)0u, I3C1, I3C2 }
47915   /** Array initializer of I3C peripheral base addresses */
47916   #define I3C_BASE_ADDRS_NS                        { 0u, I3C1_BASE_NS, I3C2_BASE_NS }
47917   /** Array initializer of I3C peripheral base pointers */
47918   #define I3C_BASE_PTRS_NS                         { (I3C_Type *)0u, I3C1_NS, I3C2_NS }
47919 #else
47920   /** Peripheral I3C1 base address */
47921   #define I3C1_BASE                                (0x44330000u)
47922   /** Peripheral I3C1 base pointer */
47923   #define I3C1                                     ((I3C_Type *)I3C1_BASE)
47924   /** Peripheral I3C2 base address */
47925   #define I3C2_BASE                                (0x42520000u)
47926   /** Peripheral I3C2 base pointer */
47927   #define I3C2                                     ((I3C_Type *)I3C2_BASE)
47928   /** Array initializer of I3C peripheral base addresses */
47929   #define I3C_BASE_ADDRS                           { 0u, I3C1_BASE, I3C2_BASE }
47930   /** Array initializer of I3C peripheral base pointers */
47931   #define I3C_BASE_PTRS                            { (I3C_Type *)0u, I3C1, I3C2 }
47932 #endif
47933 /** Interrupt vectors for the I3C peripheral type */
47934 #define I3C_IRQS                                 { NotAvail_IRQn, I3C1_IRQn, I3C2_IRQn }
47935 
47936 /*!
47937  * @}
47938  */ /* end of group I3C_Peripheral_Access_Layer */
47939 
47940 
47941 /* ----------------------------------------------------------------------------
47942    -- IEE Peripheral Access Layer
47943    ---------------------------------------------------------------------------- */
47944 
47945 /*!
47946  * @addtogroup IEE_Peripheral_Access_Layer IEE Peripheral Access Layer
47947  * @{
47948  */
47949 
47950 /** IEE - Register Layout Typedef */
47951 typedef struct {
47952   __IO uint32_t GCFG;                              /**< IEE Global Configuration, offset: 0x0 */
47953   __I  uint32_t STA;                               /**< IEE Status, offset: 0x4 */
47954   __IO uint32_t TSTMD;                             /**< IEE Test Mode Register, offset: 0x8 */
47955   __O  uint32_t DPAMS;                             /**< AES Mask Generation Seed, offset: 0xC */
47956        uint8_t RESERVED_0[16];
47957   __IO uint32_t PC_S_LT;                           /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */
47958   __IO uint32_t PC_M_LT;                           /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */
47959        uint8_t RESERVED_1[24];
47960   __IO uint32_t PC_BLK_ENC;                        /**< Performance Counter, Number of AES Block Encryptions, offset: 0x40 */
47961   __IO uint32_t PC_BLK_DEC;                        /**< Performance Counter, Number of AES Block Decryptions, offset: 0x44 */
47962        uint8_t RESERVED_2[8];
47963   __IO uint32_t PC_SR_TRANS;                       /**< Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50 */
47964   __IO uint32_t PC_SW_TRANS;                       /**< Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54 */
47965   __IO uint32_t PC_MR_TRANS;                       /**< Performance Counter, Number of AXI Master Read Transactions, offset: 0x58 */
47966   __IO uint32_t PC_MW_TRANS;                       /**< Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C */
47967        uint8_t RESERVED_3[4];
47968   __IO uint32_t PC_M_MBR;                          /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */
47969        uint8_t RESERVED_4[8];
47970   __IO uint32_t PC_SR_TBC_U;                       /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */
47971   __IO uint32_t PC_SR_TBC_L;                       /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */
47972   __IO uint32_t PC_SW_TBC_U;                       /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */
47973   __IO uint32_t PC_SW_TBC_L;                       /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */
47974   __IO uint32_t PC_MR_TBC_U;                       /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */
47975   __IO uint32_t PC_MR_TBC_L;                       /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */
47976   __IO uint32_t PC_MW_TBC_U;                       /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */
47977   __IO uint32_t PC_MW_TBC_L;                       /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */
47978   __IO uint32_t PC_SR_TLGTT;                       /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */
47979   __IO uint32_t PC_SW_TLGTT;                       /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */
47980   __IO uint32_t PC_MR_TLGTT;                       /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */
47981   __IO uint32_t PC_MW_TLGTT;                       /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */
47982   __IO uint32_t PC_SR_TLAT_U;                      /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */
47983   __IO uint32_t PC_SR_TLAT_L;                      /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */
47984   __IO uint32_t PC_SW_TLAT_U;                      /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */
47985   __IO uint32_t PC_SW_TLAT_L;                      /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */
47986   __IO uint32_t PC_MR_TLAT_U;                      /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */
47987   __IO uint32_t PC_MR_TLAT_L;                      /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */
47988   __IO uint32_t PC_MW_TLAT_U;                      /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */
47989   __IO uint32_t PC_MW_TLAT_L;                      /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */
47990   __IO uint32_t PC_SR_TNRT_U;                      /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */
47991   __IO uint32_t PC_SR_TNRT_L;                      /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */
47992   __IO uint32_t PC_SW_TNRT_U;                      /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */
47993   __IO uint32_t PC_SW_TNRT_L;                      /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */
47994        uint8_t RESERVED_5[32];
47995   __I  uint32_t VIDR1;                             /**< IEE Version ID Register 1, offset: 0xF0 */
47996        uint8_t RESERVED_6[4];
47997   __I  uint32_t AESVID;                            /**< IEE AES Version ID Register, offset: 0xF8 */
47998        uint8_t RESERVED_7[4];
47999   struct {                                         /* offset: 0x100, array step: 0x100 */
48000     __IO uint32_t REGATTR;                           /**< IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100 */
48001          uint8_t RESERVED_0[4];
48002     __IO uint32_t REGPO;                             /**< IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100 */
48003          uint8_t RESERVED_1[52];
48004     __O  uint32_t REGKEY1[8];                        /**< IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4 */
48005          uint8_t RESERVED_2[32];
48006     __O  uint32_t REGKEY2[8];                        /**< IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4 */
48007          uint8_t RESERVED_3[96];
48008   } REGX[8];
48009        uint8_t RESERVED_8[1536];
48010   __IO uint32_t AES_TST_DB[32];                    /**< IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4 */
48011 } IEE_Type;
48012 
48013 /* ----------------------------------------------------------------------------
48014    -- IEE Register Masks
48015    ---------------------------------------------------------------------------- */
48016 
48017 /*!
48018  * @addtogroup IEE_Register_Masks IEE Register Masks
48019  * @{
48020  */
48021 
48022 /*! @name GCFG - IEE Global Configuration */
48023 /*! @{ */
48024 
48025 #define IEE_GCFG_RL0_MASK                        (0x1U)
48026 #define IEE_GCFG_RL0_SHIFT                       (0U)
48027 /*! RL0
48028  *  0b0..Unlocked.
48029  *  0b1..Key, Offset and Attribute registers are locked.
48030  */
48031 #define IEE_GCFG_RL0(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
48032 
48033 #define IEE_GCFG_RL1_MASK                        (0x2U)
48034 #define IEE_GCFG_RL1_SHIFT                       (1U)
48035 /*! RL1
48036  *  0b0..Unlocked.
48037  *  0b1..Key, Offset and Attribute registers are locked.
48038  */
48039 #define IEE_GCFG_RL1(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
48040 
48041 #define IEE_GCFG_RL2_MASK                        (0x4U)
48042 #define IEE_GCFG_RL2_SHIFT                       (2U)
48043 /*! RL2
48044  *  0b0..Unlocked.
48045  *  0b1..Key, Offset and Attribute registers are locked.
48046  */
48047 #define IEE_GCFG_RL2(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
48048 
48049 #define IEE_GCFG_RL3_MASK                        (0x8U)
48050 #define IEE_GCFG_RL3_SHIFT                       (3U)
48051 /*! RL3
48052  *  0b0..Unlocked.
48053  *  0b1..Key, Offset and Attribute registers are locked.
48054  */
48055 #define IEE_GCFG_RL3(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
48056 
48057 #define IEE_GCFG_RL4_MASK                        (0x10U)
48058 #define IEE_GCFG_RL4_SHIFT                       (4U)
48059 /*! RL4
48060  *  0b0..Unlocked.
48061  *  0b1..Key, Offset and Attribute registers are locked.
48062  */
48063 #define IEE_GCFG_RL4(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
48064 
48065 #define IEE_GCFG_RL5_MASK                        (0x20U)
48066 #define IEE_GCFG_RL5_SHIFT                       (5U)
48067 /*! RL5
48068  *  0b0..Unlocked.
48069  *  0b1..Key, Offset and Attribute registers are locked.
48070  */
48071 #define IEE_GCFG_RL5(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
48072 
48073 #define IEE_GCFG_RL6_MASK                        (0x40U)
48074 #define IEE_GCFG_RL6_SHIFT                       (6U)
48075 /*! RL6
48076  *  0b0..Unlocked.
48077  *  0b1..Key, Offset and Attribute registers are locked.
48078  */
48079 #define IEE_GCFG_RL6(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
48080 
48081 #define IEE_GCFG_RL7_MASK                        (0x80U)
48082 #define IEE_GCFG_RL7_SHIFT                       (7U)
48083 /*! RL7
48084  *  0b0..Unlocked.
48085  *  0b1..Key, Offset and Attribute registers are locked.
48086  */
48087 #define IEE_GCFG_RL7(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
48088 
48089 #define IEE_GCFG_TME_MASK                        (0x10000U)
48090 #define IEE_GCFG_TME_SHIFT                       (16U)
48091 /*! TME
48092  *  0b0..Disabled.
48093  *  0b1..Enabled.
48094  */
48095 #define IEE_GCFG_TME(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
48096 
48097 #define IEE_GCFG_TMD_MASK                        (0x20000U)
48098 #define IEE_GCFG_TMD_SHIFT                       (17U)
48099 /*! TMD
48100  *  0b0..Test mode is usable.
48101  *  0b1..Test mode is disabled.
48102  */
48103 #define IEE_GCFG_TMD(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
48104 
48105 #define IEE_GCFG_KEY_RD_DIS_MASK                 (0x2000000U)
48106 #define IEE_GCFG_KEY_RD_DIS_SHIFT                (25U)
48107 /*! KEY_RD_DIS
48108  *  0b0..Key read enabled. Reading the key registers is allowed.
48109  *  0b1..Key read disabled. Reading the key registers is disabled.
48110  */
48111 #define IEE_GCFG_KEY_RD_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
48112 
48113 #define IEE_GCFG_MON_EN_MASK                     (0x10000000U)
48114 #define IEE_GCFG_MON_EN_SHIFT                    (28U)
48115 /*! MON_EN
48116  *  0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled.
48117  *  0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.
48118  */
48119 #define IEE_GCFG_MON_EN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
48120 
48121 #define IEE_GCFG_CLR_MON_MASK                    (0x20000000U)
48122 #define IEE_GCFG_CLR_MON_SHIFT                   (29U)
48123 /*! CLR_MON
48124  *  0b0..Do not reset.
48125  *  0b1..Reset performance counters.
48126  */
48127 #define IEE_GCFG_CLR_MON(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
48128 
48129 #define IEE_GCFG_RST_MASK                        (0x80000000U)
48130 #define IEE_GCFG_RST_SHIFT                       (31U)
48131 /*! RST
48132  *  0b0..Do Not Reset.
48133  *  0b1..Reset IEE.
48134  */
48135 #define IEE_GCFG_RST(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
48136 /*! @} */
48137 
48138 /*! @name STA - IEE Status */
48139 /*! @{ */
48140 
48141 #define IEE_STA_DSR_MASK                         (0x1U)
48142 #define IEE_STA_DSR_SHIFT                        (0U)
48143 /*! DSR
48144  *  0b0..No seed request present
48145  *  0b1..Seed request present
48146  */
48147 #define IEE_STA_DSR(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
48148 
48149 #define IEE_STA_AFD_MASK                         (0x10U)
48150 #define IEE_STA_AFD_SHIFT                        (4U)
48151 /*! AFD
48152  *  0b0..No fault detected
48153  *  0b1..Fault detected
48154  */
48155 #define IEE_STA_AFD(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
48156 /*! @} */
48157 
48158 /*! @name TSTMD - IEE Test Mode Register */
48159 /*! @{ */
48160 
48161 #define IEE_TSTMD_TMRDY_MASK                     (0x1U)
48162 #define IEE_TSTMD_TMRDY_SHIFT                    (0U)
48163 /*! TMRDY
48164  *  0b0..Not Ready.
48165  *  0b1..Ready.
48166  */
48167 #define IEE_TSTMD_TMRDY(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
48168 
48169 #define IEE_TSTMD_TMR_MASK                       (0x2U)
48170 #define IEE_TSTMD_TMR_SHIFT                      (1U)
48171 /*! TMR
48172  *  0b0..Not running. May be written if IEE_GCFG[TME] = 1
48173  *  0b1..Run AES Test until TMDONE is indicated.
48174  */
48175 #define IEE_TSTMD_TMR(x)                         (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
48176 
48177 #define IEE_TSTMD_TMENCR_MASK                    (0x4U)
48178 #define IEE_TSTMD_TMENCR_SHIFT                   (2U)
48179 /*! TMENCR
48180  *  0b0..AES Test mode will do decryption.
48181  *  0b1..AES Test mode will do encryption.
48182  */
48183 #define IEE_TSTMD_TMENCR(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
48184 
48185 #define IEE_TSTMD_TMCONT_MASK                    (0x8U)
48186 #define IEE_TSTMD_TMCONT_SHIFT                   (3U)
48187 /*! TMCONT
48188  *  0b0..Do not continue. This is the last block of data for AES.
48189  *  0b1..Continue. Do not initialize AES after this block.
48190  */
48191 #define IEE_TSTMD_TMCONT(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
48192 
48193 #define IEE_TSTMD_TMDONE_MASK                    (0x10U)
48194 #define IEE_TSTMD_TMDONE_SHIFT                   (4U)
48195 /*! TMDONE
48196  *  0b0..Not Done.
48197  *  0b1..Test Done.
48198  */
48199 #define IEE_TSTMD_TMDONE(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
48200 
48201 #define IEE_TSTMD_TMLEN_MASK                     (0xF00U)
48202 #define IEE_TSTMD_TMLEN_SHIFT                    (8U)
48203 #define IEE_TSTMD_TMLEN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
48204 /*! @} */
48205 
48206 /*! @name DPAMS - AES Mask Generation Seed */
48207 /*! @{ */
48208 
48209 #define IEE_DPAMS_DPAMS_MASK                     (0xFFFFFFFFU)
48210 #define IEE_DPAMS_DPAMS_SHIFT                    (0U)
48211 #define IEE_DPAMS_DPAMS(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
48212 /*! @} */
48213 
48214 /*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */
48215 /*! @{ */
48216 
48217 #define IEE_PC_S_LT_SW_LT_MASK                   (0xFFFFU)
48218 #define IEE_PC_S_LT_SW_LT_SHIFT                  (0U)
48219 #define IEE_PC_S_LT_SW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
48220 
48221 #define IEE_PC_S_LT_SR_LT_MASK                   (0xFFFF0000U)
48222 #define IEE_PC_S_LT_SR_LT_SHIFT                  (16U)
48223 #define IEE_PC_S_LT_SR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
48224 /*! @} */
48225 
48226 /*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */
48227 /*! @{ */
48228 
48229 #define IEE_PC_M_LT_MW_LT_MASK                   (0xFFFU)
48230 #define IEE_PC_M_LT_MW_LT_SHIFT                  (0U)
48231 #define IEE_PC_M_LT_MW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
48232 
48233 #define IEE_PC_M_LT_MR_LT_MASK                   (0xFFF0000U)
48234 #define IEE_PC_M_LT_MR_LT_SHIFT                  (16U)
48235 #define IEE_PC_M_LT_MR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
48236 /*! @} */
48237 
48238 /*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */
48239 /*! @{ */
48240 
48241 #define IEE_PC_BLK_ENC_BLK_ENC_MASK              (0xFFFFFFFFU)
48242 #define IEE_PC_BLK_ENC_BLK_ENC_SHIFT             (0U)
48243 #define IEE_PC_BLK_ENC_BLK_ENC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
48244 /*! @} */
48245 
48246 /*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */
48247 /*! @{ */
48248 
48249 #define IEE_PC_BLK_DEC_BLK_DEC_MASK              (0xFFFFFFFFU)
48250 #define IEE_PC_BLK_DEC_BLK_DEC_SHIFT             (0U)
48251 #define IEE_PC_BLK_DEC_BLK_DEC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
48252 /*! @} */
48253 
48254 /*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */
48255 /*! @{ */
48256 
48257 #define IEE_PC_SR_TRANS_SR_TRANS_MASK            (0xFFFFFFFFU)
48258 #define IEE_PC_SR_TRANS_SR_TRANS_SHIFT           (0U)
48259 #define IEE_PC_SR_TRANS_SR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
48260 /*! @} */
48261 
48262 /*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */
48263 /*! @{ */
48264 
48265 #define IEE_PC_SW_TRANS_SW_TRANS_MASK            (0xFFFFFFFFU)
48266 #define IEE_PC_SW_TRANS_SW_TRANS_SHIFT           (0U)
48267 #define IEE_PC_SW_TRANS_SW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
48268 /*! @} */
48269 
48270 /*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */
48271 /*! @{ */
48272 
48273 #define IEE_PC_MR_TRANS_MR_TRANS_MASK            (0xFFFFFFFFU)
48274 #define IEE_PC_MR_TRANS_MR_TRANS_SHIFT           (0U)
48275 #define IEE_PC_MR_TRANS_MR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
48276 /*! @} */
48277 
48278 /*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */
48279 /*! @{ */
48280 
48281 #define IEE_PC_MW_TRANS_MW_TRANS_MASK            (0xFFFFFFFFU)
48282 #define IEE_PC_MW_TRANS_MW_TRANS_SHIFT           (0U)
48283 #define IEE_PC_MW_TRANS_MW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
48284 /*! @} */
48285 
48286 /*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */
48287 /*! @{ */
48288 
48289 #define IEE_PC_M_MBR_M_MBR_MASK                  (0xFFFFFFFFU)
48290 #define IEE_PC_M_MBR_M_MBR_SHIFT                 (0U)
48291 #define IEE_PC_M_MBR_M_MBR(x)                    (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
48292 /*! @} */
48293 
48294 /*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */
48295 /*! @{ */
48296 
48297 #define IEE_PC_SR_TBC_U_SR_TBC_MASK              (0xFFFFU)
48298 #define IEE_PC_SR_TBC_U_SR_TBC_SHIFT             (0U)
48299 #define IEE_PC_SR_TBC_U_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
48300 /*! @} */
48301 
48302 /*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */
48303 /*! @{ */
48304 
48305 #define IEE_PC_SR_TBC_L_SR_TBC_MASK              (0xFFFFFFFFU)
48306 #define IEE_PC_SR_TBC_L_SR_TBC_SHIFT             (0U)
48307 #define IEE_PC_SR_TBC_L_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
48308 /*! @} */
48309 
48310 /*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */
48311 /*! @{ */
48312 
48313 #define IEE_PC_SW_TBC_U_SW_TBC_MASK              (0xFFFFU)
48314 #define IEE_PC_SW_TBC_U_SW_TBC_SHIFT             (0U)
48315 #define IEE_PC_SW_TBC_U_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
48316 /*! @} */
48317 
48318 /*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */
48319 /*! @{ */
48320 
48321 #define IEE_PC_SW_TBC_L_SW_TBC_MASK              (0xFFFFFFFFU)
48322 #define IEE_PC_SW_TBC_L_SW_TBC_SHIFT             (0U)
48323 #define IEE_PC_SW_TBC_L_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
48324 /*! @} */
48325 
48326 /*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */
48327 /*! @{ */
48328 
48329 #define IEE_PC_MR_TBC_U_MR_TBC_MASK              (0xFFFFU)
48330 #define IEE_PC_MR_TBC_U_MR_TBC_SHIFT             (0U)
48331 #define IEE_PC_MR_TBC_U_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
48332 /*! @} */
48333 
48334 /*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */
48335 /*! @{ */
48336 
48337 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK          (0xFU)
48338 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT         (0U)
48339 #define IEE_PC_MR_TBC_L_MR_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
48340 
48341 #define IEE_PC_MR_TBC_L_MR_TBC_MASK              (0xFFFFFFF0U)
48342 #define IEE_PC_MR_TBC_L_MR_TBC_SHIFT             (4U)
48343 #define IEE_PC_MR_TBC_L_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
48344 /*! @} */
48345 
48346 /*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */
48347 /*! @{ */
48348 
48349 #define IEE_PC_MW_TBC_U_MW_TBC_MASK              (0xFFFFU)
48350 #define IEE_PC_MW_TBC_U_MW_TBC_SHIFT             (0U)
48351 #define IEE_PC_MW_TBC_U_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
48352 /*! @} */
48353 
48354 /*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */
48355 /*! @{ */
48356 
48357 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK          (0xFU)
48358 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT         (0U)
48359 #define IEE_PC_MW_TBC_L_MW_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
48360 
48361 #define IEE_PC_MW_TBC_L_MW_TBC_MASK              (0xFFFFFFF0U)
48362 #define IEE_PC_MW_TBC_L_MW_TBC_SHIFT             (4U)
48363 #define IEE_PC_MW_TBC_L_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
48364 /*! @} */
48365 
48366 /*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */
48367 /*! @{ */
48368 
48369 #define IEE_PC_SR_TLGTT_SR_TLGTT_MASK            (0xFFFFFFFFU)
48370 #define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT           (0U)
48371 #define IEE_PC_SR_TLGTT_SR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
48372 /*! @} */
48373 
48374 /*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */
48375 /*! @{ */
48376 
48377 #define IEE_PC_SW_TLGTT_SW_TLGTT_MASK            (0xFFFFFFFFU)
48378 #define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT           (0U)
48379 #define IEE_PC_SW_TLGTT_SW_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
48380 /*! @} */
48381 
48382 /*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */
48383 /*! @{ */
48384 
48385 #define IEE_PC_MR_TLGTT_MR_TLGTT_MASK            (0xFFFFFFFFU)
48386 #define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT           (0U)
48387 #define IEE_PC_MR_TLGTT_MR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
48388 /*! @} */
48389 
48390 /*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */
48391 /*! @{ */
48392 
48393 #define IEE_PC_MW_TLGTT_MW_TGTT_MASK             (0xFFFFFFFFU)
48394 #define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT            (0U)
48395 #define IEE_PC_MW_TLGTT_MW_TGTT(x)               (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
48396 /*! @} */
48397 
48398 /*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */
48399 /*! @{ */
48400 
48401 #define IEE_PC_SR_TLAT_U_SR_TLAT_MASK            (0xFFFFU)
48402 #define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT           (0U)
48403 #define IEE_PC_SR_TLAT_U_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
48404 /*! @} */
48405 
48406 /*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */
48407 /*! @{ */
48408 
48409 #define IEE_PC_SR_TLAT_L_SR_TLAT_MASK            (0xFFFFFFFFU)
48410 #define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT           (0U)
48411 #define IEE_PC_SR_TLAT_L_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
48412 /*! @} */
48413 
48414 /*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */
48415 /*! @{ */
48416 
48417 #define IEE_PC_SW_TLAT_U_SW_TLAT_MASK            (0xFFFFU)
48418 #define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT           (0U)
48419 #define IEE_PC_SW_TLAT_U_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
48420 /*! @} */
48421 
48422 /*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */
48423 /*! @{ */
48424 
48425 #define IEE_PC_SW_TLAT_L_SW_TLAT_MASK            (0xFFFFFFFFU)
48426 #define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT           (0U)
48427 #define IEE_PC_SW_TLAT_L_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
48428 /*! @} */
48429 
48430 /*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */
48431 /*! @{ */
48432 
48433 #define IEE_PC_MR_TLAT_U_MR_TLAT_MASK            (0xFFFFU)
48434 #define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT           (0U)
48435 #define IEE_PC_MR_TLAT_U_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
48436 /*! @} */
48437 
48438 /*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */
48439 /*! @{ */
48440 
48441 #define IEE_PC_MR_TLAT_L_MR_TLAT_MASK            (0xFFFFFFFFU)
48442 #define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT           (0U)
48443 #define IEE_PC_MR_TLAT_L_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
48444 /*! @} */
48445 
48446 /*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */
48447 /*! @{ */
48448 
48449 #define IEE_PC_MW_TLAT_U_MW_TLAT_MASK            (0xFFFFU)
48450 #define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT           (0U)
48451 #define IEE_PC_MW_TLAT_U_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
48452 /*! @} */
48453 
48454 /*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */
48455 /*! @{ */
48456 
48457 #define IEE_PC_MW_TLAT_L_MW_TLAT_MASK            (0xFFFFFFFFU)
48458 #define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT           (0U)
48459 #define IEE_PC_MW_TLAT_L_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
48460 /*! @} */
48461 
48462 /*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */
48463 /*! @{ */
48464 
48465 #define IEE_PC_SR_TNRT_U_SR_TNRT_MASK            (0xFFFFU)
48466 #define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT           (0U)
48467 #define IEE_PC_SR_TNRT_U_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
48468 /*! @} */
48469 
48470 /*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */
48471 /*! @{ */
48472 
48473 #define IEE_PC_SR_TNRT_L_SR_TNRT_MASK            (0xFFFFFFFFU)
48474 #define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT           (0U)
48475 #define IEE_PC_SR_TNRT_L_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
48476 /*! @} */
48477 
48478 /*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */
48479 /*! @{ */
48480 
48481 #define IEE_PC_SW_TNRT_U_SW_TNRT_MASK            (0xFFFFU)
48482 #define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT           (0U)
48483 #define IEE_PC_SW_TNRT_U_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
48484 /*! @} */
48485 
48486 /*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */
48487 /*! @{ */
48488 
48489 #define IEE_PC_SW_TNRT_L_SW_TNRT_MASK            (0xFFFFFFFFU)
48490 #define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT           (0U)
48491 #define IEE_PC_SW_TNRT_L_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
48492 /*! @} */
48493 
48494 /*! @name VIDR1 - IEE Version ID Register 1 */
48495 /*! @{ */
48496 
48497 #define IEE_VIDR1_MIN_REV_MASK                   (0xFFU)
48498 #define IEE_VIDR1_MIN_REV_SHIFT                  (0U)
48499 #define IEE_VIDR1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
48500 
48501 #define IEE_VIDR1_MAJ_REV_MASK                   (0xFF00U)
48502 #define IEE_VIDR1_MAJ_REV_SHIFT                  (8U)
48503 #define IEE_VIDR1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
48504 
48505 #define IEE_VIDR1_IP_ID_MASK                     (0xFFFF0000U)
48506 #define IEE_VIDR1_IP_ID_SHIFT                    (16U)
48507 #define IEE_VIDR1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
48508 /*! @} */
48509 
48510 /*! @name AESVID - IEE AES Version ID Register */
48511 /*! @{ */
48512 
48513 #define IEE_AESVID_AESRN_MASK                    (0xFU)
48514 #define IEE_AESVID_AESRN_SHIFT                   (0U)
48515 #define IEE_AESVID_AESRN(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
48516 
48517 #define IEE_AESVID_AESVID_MASK                   (0xF0U)
48518 #define IEE_AESVID_AESVID_SHIFT                  (4U)
48519 #define IEE_AESVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
48520 /*! @} */
48521 
48522 /*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */
48523 /*! @{ */
48524 
48525 #define IEE_REGATTR_KS_MASK                      (0x1U)
48526 #define IEE_REGATTR_KS_SHIFT                     (0U)
48527 /*! KS
48528  *  0b0..128 bits (CTR), 256 bits (XTS).
48529  *  0b1..256 bits (CTR), 512 bits (XTS).
48530  */
48531 #define IEE_REGATTR_KS(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
48532 
48533 #define IEE_REGATTR_MD_MASK                      (0x70U)
48534 #define IEE_REGATTR_MD_SHIFT                     (4U)
48535 /*! MD
48536  *  0b000..None (AXI error if accessed)
48537  *  0b001..XTS
48538  *  0b010..CTR w/ address binding
48539  *  0b011..CTR w/o address binding
48540  *  0b100..CTR keystream only
48541  *  0b101..Undefined, AXI error if used
48542  *  0b110..Undefined, AXI error if used
48543  *  0b111..Undefined, AXI error if used
48544  */
48545 #define IEE_REGATTR_MD(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
48546 
48547 #define IEE_REGATTR_BYP_MASK                     (0x80U)
48548 #define IEE_REGATTR_BYP_SHIFT                    (7U)
48549 /*! BYP
48550  *  0b0..use MD field
48551  *  0b1..Bypass AES, no encrypt/decrypt
48552  */
48553 #define IEE_REGATTR_BYP(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
48554 /*! @} */
48555 
48556 /* The count of IEE_REGATTR */
48557 #define IEE_REGATTR_COUNT                        (8U)
48558 
48559 /*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */
48560 /*! @{ */
48561 
48562 #define IEE_REGPO_PGOFF_MASK                     (0xFFFFFFU)
48563 #define IEE_REGPO_PGOFF_SHIFT                    (0U)
48564 #define IEE_REGPO_PGOFF(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
48565 /*! @} */
48566 
48567 /* The count of IEE_REGPO */
48568 #define IEE_REGPO_COUNT                          (8U)
48569 
48570 /*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */
48571 /*! @{ */
48572 
48573 #define IEE_REGKEY1_KEY1_MASK                    (0xFFFFFFFFU)
48574 #define IEE_REGKEY1_KEY1_SHIFT                   (0U)
48575 #define IEE_REGKEY1_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
48576 /*! @} */
48577 
48578 /* The count of IEE_REGKEY1 */
48579 #define IEE_REGKEY1_COUNT                        (8U)
48580 
48581 /* The count of IEE_REGKEY1 */
48582 #define IEE_REGKEY1_COUNT2                       (8U)
48583 
48584 /*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */
48585 /*! @{ */
48586 
48587 #define IEE_REGKEY2_KEY2_MASK                    (0xFFFFFFFFU)
48588 #define IEE_REGKEY2_KEY2_SHIFT                   (0U)
48589 #define IEE_REGKEY2_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
48590 /*! @} */
48591 
48592 /* The count of IEE_REGKEY2 */
48593 #define IEE_REGKEY2_COUNT                        (8U)
48594 
48595 /* The count of IEE_REGKEY2 */
48596 #define IEE_REGKEY2_COUNT2                       (8U)
48597 
48598 /*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */
48599 /*! @{ */
48600 
48601 #define IEE_AES_TST_DB_AES_TST_DB0_MASK          (0xFFFFFFFFU)
48602 #define IEE_AES_TST_DB_AES_TST_DB0_SHIFT         (0U)
48603 #define IEE_AES_TST_DB_AES_TST_DB0(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
48604 
48605 #define IEE_AES_TST_DB_AES_TST_DB1_MASK          (0xFFFFFFFFU)
48606 #define IEE_AES_TST_DB_AES_TST_DB1_SHIFT         (0U)
48607 #define IEE_AES_TST_DB_AES_TST_DB1(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
48608 
48609 #define IEE_AES_TST_DB_AES_TST_DB2_MASK          (0xFFFFFFFFU)
48610 #define IEE_AES_TST_DB_AES_TST_DB2_SHIFT         (0U)
48611 #define IEE_AES_TST_DB_AES_TST_DB2(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
48612 
48613 #define IEE_AES_TST_DB_AES_TST_DB3_MASK          (0xFFFFFFFFU)
48614 #define IEE_AES_TST_DB_AES_TST_DB3_SHIFT         (0U)
48615 #define IEE_AES_TST_DB_AES_TST_DB3(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
48616 
48617 #define IEE_AES_TST_DB_AES_TST_DB4_MASK          (0xFFFFFFFFU)
48618 #define IEE_AES_TST_DB_AES_TST_DB4_SHIFT         (0U)
48619 #define IEE_AES_TST_DB_AES_TST_DB4(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
48620 
48621 #define IEE_AES_TST_DB_AES_TST_DB5_MASK          (0xFFFFFFFFU)
48622 #define IEE_AES_TST_DB_AES_TST_DB5_SHIFT         (0U)
48623 #define IEE_AES_TST_DB_AES_TST_DB5(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
48624 
48625 #define IEE_AES_TST_DB_AES_TST_DB6_MASK          (0xFFFFFFFFU)
48626 #define IEE_AES_TST_DB_AES_TST_DB6_SHIFT         (0U)
48627 #define IEE_AES_TST_DB_AES_TST_DB6(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
48628 
48629 #define IEE_AES_TST_DB_AES_TST_DB7_MASK          (0xFFFFFFFFU)
48630 #define IEE_AES_TST_DB_AES_TST_DB7_SHIFT         (0U)
48631 #define IEE_AES_TST_DB_AES_TST_DB7(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
48632 
48633 #define IEE_AES_TST_DB_AES_TST_DB8_MASK          (0xFFFFFFFFU)
48634 #define IEE_AES_TST_DB_AES_TST_DB8_SHIFT         (0U)
48635 #define IEE_AES_TST_DB_AES_TST_DB8(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
48636 
48637 #define IEE_AES_TST_DB_AES_TST_DB9_MASK          (0xFFFFFFFFU)
48638 #define IEE_AES_TST_DB_AES_TST_DB9_SHIFT         (0U)
48639 #define IEE_AES_TST_DB_AES_TST_DB9(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
48640 
48641 #define IEE_AES_TST_DB_AES_TST_DB10_MASK         (0xFFFFFFFFU)
48642 #define IEE_AES_TST_DB_AES_TST_DB10_SHIFT        (0U)
48643 #define IEE_AES_TST_DB_AES_TST_DB10(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
48644 
48645 #define IEE_AES_TST_DB_AES_TST_DB11_MASK         (0xFFFFFFFFU)
48646 #define IEE_AES_TST_DB_AES_TST_DB11_SHIFT        (0U)
48647 #define IEE_AES_TST_DB_AES_TST_DB11(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
48648 
48649 #define IEE_AES_TST_DB_AES_TST_DB12_MASK         (0xFFFFFFFFU)
48650 #define IEE_AES_TST_DB_AES_TST_DB12_SHIFT        (0U)
48651 #define IEE_AES_TST_DB_AES_TST_DB12(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
48652 
48653 #define IEE_AES_TST_DB_AES_TST_DB13_MASK         (0xFFFFFFFFU)
48654 #define IEE_AES_TST_DB_AES_TST_DB13_SHIFT        (0U)
48655 #define IEE_AES_TST_DB_AES_TST_DB13(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
48656 
48657 #define IEE_AES_TST_DB_AES_TST_DB14_MASK         (0xFFFFFFFFU)
48658 #define IEE_AES_TST_DB_AES_TST_DB14_SHIFT        (0U)
48659 #define IEE_AES_TST_DB_AES_TST_DB14(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
48660 
48661 #define IEE_AES_TST_DB_AES_TST_DB15_MASK         (0xFFFFFFFFU)
48662 #define IEE_AES_TST_DB_AES_TST_DB15_SHIFT        (0U)
48663 #define IEE_AES_TST_DB_AES_TST_DB15(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
48664 
48665 #define IEE_AES_TST_DB_AES_TST_DB16_MASK         (0xFFFFFFFFU)
48666 #define IEE_AES_TST_DB_AES_TST_DB16_SHIFT        (0U)
48667 #define IEE_AES_TST_DB_AES_TST_DB16(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
48668 
48669 #define IEE_AES_TST_DB_AES_TST_DB17_MASK         (0xFFFFFFFFU)
48670 #define IEE_AES_TST_DB_AES_TST_DB17_SHIFT        (0U)
48671 #define IEE_AES_TST_DB_AES_TST_DB17(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
48672 
48673 #define IEE_AES_TST_DB_AES_TST_DB18_MASK         (0xFFFFFFFFU)
48674 #define IEE_AES_TST_DB_AES_TST_DB18_SHIFT        (0U)
48675 #define IEE_AES_TST_DB_AES_TST_DB18(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
48676 
48677 #define IEE_AES_TST_DB_AES_TST_DB19_MASK         (0xFFFFFFFFU)
48678 #define IEE_AES_TST_DB_AES_TST_DB19_SHIFT        (0U)
48679 #define IEE_AES_TST_DB_AES_TST_DB19(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
48680 
48681 #define IEE_AES_TST_DB_AES_TST_DB20_MASK         (0xFFFFFFFFU)
48682 #define IEE_AES_TST_DB_AES_TST_DB20_SHIFT        (0U)
48683 #define IEE_AES_TST_DB_AES_TST_DB20(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
48684 
48685 #define IEE_AES_TST_DB_AES_TST_DB21_MASK         (0xFFFFFFFFU)
48686 #define IEE_AES_TST_DB_AES_TST_DB21_SHIFT        (0U)
48687 #define IEE_AES_TST_DB_AES_TST_DB21(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
48688 
48689 #define IEE_AES_TST_DB_AES_TST_DB22_MASK         (0xFFFFFFFFU)
48690 #define IEE_AES_TST_DB_AES_TST_DB22_SHIFT        (0U)
48691 #define IEE_AES_TST_DB_AES_TST_DB22(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
48692 
48693 #define IEE_AES_TST_DB_AES_TST_DB23_MASK         (0xFFFFFFFFU)
48694 #define IEE_AES_TST_DB_AES_TST_DB23_SHIFT        (0U)
48695 #define IEE_AES_TST_DB_AES_TST_DB23(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
48696 
48697 #define IEE_AES_TST_DB_AES_TST_DB24_MASK         (0xFFFFFFFFU)
48698 #define IEE_AES_TST_DB_AES_TST_DB24_SHIFT        (0U)
48699 #define IEE_AES_TST_DB_AES_TST_DB24(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
48700 
48701 #define IEE_AES_TST_DB_AES_TST_DB25_MASK         (0xFFFFFFFFU)
48702 #define IEE_AES_TST_DB_AES_TST_DB25_SHIFT        (0U)
48703 #define IEE_AES_TST_DB_AES_TST_DB25(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
48704 
48705 #define IEE_AES_TST_DB_AES_TST_DB26_MASK         (0xFFFFFFFFU)
48706 #define IEE_AES_TST_DB_AES_TST_DB26_SHIFT        (0U)
48707 #define IEE_AES_TST_DB_AES_TST_DB26(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
48708 
48709 #define IEE_AES_TST_DB_AES_TST_DB27_MASK         (0xFFFFFFFFU)
48710 #define IEE_AES_TST_DB_AES_TST_DB27_SHIFT        (0U)
48711 #define IEE_AES_TST_DB_AES_TST_DB27(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
48712 
48713 #define IEE_AES_TST_DB_AES_TST_DB28_MASK         (0xFFFFFFFFU)
48714 #define IEE_AES_TST_DB_AES_TST_DB28_SHIFT        (0U)
48715 #define IEE_AES_TST_DB_AES_TST_DB28(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
48716 
48717 #define IEE_AES_TST_DB_AES_TST_DB29_MASK         (0xFFFFFFFFU)
48718 #define IEE_AES_TST_DB_AES_TST_DB29_SHIFT        (0U)
48719 #define IEE_AES_TST_DB_AES_TST_DB29(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
48720 
48721 #define IEE_AES_TST_DB_AES_TST_DB30_MASK         (0xFFFFFFFFU)
48722 #define IEE_AES_TST_DB_AES_TST_DB30_SHIFT        (0U)
48723 #define IEE_AES_TST_DB_AES_TST_DB30(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
48724 
48725 #define IEE_AES_TST_DB_AES_TST_DB31_MASK         (0xFFFFFFFFU)
48726 #define IEE_AES_TST_DB_AES_TST_DB31_SHIFT        (0U)
48727 #define IEE_AES_TST_DB_AES_TST_DB31(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
48728 /*! @} */
48729 
48730 /* The count of IEE_AES_TST_DB */
48731 #define IEE_AES_TST_DB_COUNT                     (32U)
48732 
48733 
48734 /*!
48735  * @}
48736  */ /* end of group IEE_Register_Masks */
48737 
48738 
48739 /* IEE - Peripheral instance base addresses */
48740 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
48741   /** Peripheral IEE base address */
48742   #define IEE_BASE                                 (0x52E40000u)
48743   /** Peripheral IEE base address */
48744   #define IEE_BASE_NS                              (0x42E40000u)
48745   /** Peripheral IEE base pointer */
48746   #define IEE                                      ((IEE_Type *)IEE_BASE)
48747   /** Peripheral IEE base pointer */
48748   #define IEE_NS                                   ((IEE_Type *)IEE_BASE_NS)
48749   /** Array initializer of IEE peripheral base addresses */
48750   #define IEE_BASE_ADDRS                           { IEE_BASE }
48751   /** Array initializer of IEE peripheral base pointers */
48752   #define IEE_BASE_PTRS                            { IEE }
48753   /** Array initializer of IEE peripheral base addresses */
48754   #define IEE_BASE_ADDRS_NS                        { IEE_BASE_NS }
48755   /** Array initializer of IEE peripheral base pointers */
48756   #define IEE_BASE_PTRS_NS                         { IEE_NS }
48757 #else
48758   /** Peripheral IEE base address */
48759   #define IEE_BASE                                 (0x42E40000u)
48760   /** Peripheral IEE base pointer */
48761   #define IEE                                      ((IEE_Type *)IEE_BASE)
48762   /** Array initializer of IEE peripheral base addresses */
48763   #define IEE_BASE_ADDRS                           { IEE_BASE }
48764   /** Array initializer of IEE peripheral base pointers */
48765   #define IEE_BASE_PTRS                            { IEE }
48766 #endif
48767 
48768 /*!
48769  * @}
48770  */ /* end of group IEE_Peripheral_Access_Layer */
48771 
48772 
48773 /* ----------------------------------------------------------------------------
48774    -- IEE_APC Peripheral Access Layer
48775    ---------------------------------------------------------------------------- */
48776 
48777 /*!
48778  * @addtogroup IEE_APC_Peripheral_Access_Layer IEE_APC Peripheral Access Layer
48779  * @{
48780  */
48781 
48782 /** IEE_APC - Register Layout Typedef */
48783 typedef struct {
48784   __IO uint32_t REGION0_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x0 */
48785   __IO uint32_t REGION0_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x4 */
48786   __IO uint32_t REGION0_ENA;                       /**< Region enable for region (n), offset: 0x8 */
48787   __IO uint32_t REGION0_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0xC */
48788   __IO uint32_t REGION1_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x10 */
48789   __IO uint32_t REGION1_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x14 */
48790   __IO uint32_t REGION1_ENA;                       /**< Region enable for region (n), offset: 0x18 */
48791   __IO uint32_t REGION1_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x1C */
48792   __IO uint32_t REGION2_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x20 */
48793   __IO uint32_t REGION2_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x24 */
48794   __IO uint32_t REGION2_ENA;                       /**< Region enable for region (n), offset: 0x28 */
48795   __IO uint32_t REGION2_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x2C */
48796   __IO uint32_t REGION3_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x30 */
48797   __IO uint32_t REGION3_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x34 */
48798   __IO uint32_t REGION3_ENA;                       /**< Region enable for region (n), offset: 0x38 */
48799   __IO uint32_t REGION3_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x3C */
48800   __IO uint32_t REGION4_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x40 */
48801   __IO uint32_t REGION4_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x44 */
48802   __IO uint32_t REGION4_ENA;                       /**< Region enable for region (n), offset: 0x48 */
48803   __IO uint32_t REGION4_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x4C */
48804   __IO uint32_t REGION5_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x50 */
48805   __IO uint32_t REGION5_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x54 */
48806   __IO uint32_t REGION5_ENA;                       /**< Region enable for region (n), offset: 0x58 */
48807   __IO uint32_t REGION5_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x5C */
48808   __IO uint32_t REGION6_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x60 */
48809   __IO uint32_t REGION6_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x64 */
48810   __IO uint32_t REGION6_ENA;                       /**< Region enable for region (n), offset: 0x68 */
48811   __IO uint32_t REGION6_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x6C */
48812   __IO uint32_t REGION7_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x70 */
48813   __IO uint32_t REGION7_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x74 */
48814   __IO uint32_t REGION7_ENA;                       /**< Region enable for region (n), offset: 0x78 */
48815   __IO uint32_t REGION7_ACC_CTL;                   /**< Access control for IEE APC registers of region (n), offset: 0x7C */
48816 } IEE_APC_Type;
48817 
48818 /* ----------------------------------------------------------------------------
48819    -- IEE_APC Register Masks
48820    ---------------------------------------------------------------------------- */
48821 
48822 /*!
48823  * @addtogroup IEE_APC_Register_Masks IEE_APC Register Masks
48824  * @{
48825  */
48826 
48827 /*! @name REGION0_TOP_ADDR - End address of IEE region (n) */
48828 /*! @{ */
48829 
48830 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
48831 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
48832 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48833 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
48834 /*! @} */
48835 
48836 /*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */
48837 /*! @{ */
48838 
48839 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
48840 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
48841 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48842 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
48843 /*! @} */
48844 
48845 /*! @name REGION0_ENA - Region enable for region (n) */
48846 /*! @{ */
48847 
48848 #define IEE_APC_REGION0_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
48849 #define IEE_APC_REGION0_ENA_ENCRYPT_ENABLE_SHIFT (0U)
48850 /*! ENCRYPT_ENABLE - Enable this region
48851  *  0b1..This region is enabled for IEE routing once hit
48852  *  0b0..This region is not enabled for IEE routing even hit
48853  */
48854 #define IEE_APC_REGION0_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION0_ENA_ENCRYPT_ENABLE_MASK)
48855 /*! @} */
48856 
48857 /*! @name REGION0_ACC_CTL - Access control for IEE APC registers of region (n) */
48858 /*! @{ */
48859 
48860 #define IEE_APC_REGION0_ACC_CTL_ALLOW_DID_MASK   (0xFU)
48861 #define IEE_APC_REGION0_ACC_CTL_ALLOW_DID_SHIFT  (0U)
48862 /*! ALLOW_DID - Allowed domain ID */
48863 #define IEE_APC_REGION0_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION0_ACC_CTL_ALLOW_DID_MASK)
48864 
48865 #define IEE_APC_REGION0_ACC_CTL_LOCK_L_MASK      (0x8000U)
48866 #define IEE_APC_REGION0_ACC_CTL_LOCK_L_SHIFT     (15U)
48867 /*! LOCK_L - Lock bit for the lower half word
48868  *  0b0..Lower half word is not locked
48869  *  0b1..Lower half word is locked
48870  */
48871 #define IEE_APC_REGION0_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION0_ACC_CTL_LOCK_L_MASK)
48872 
48873 #define IEE_APC_REGION0_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
48874 #define IEE_APC_REGION0_ACC_CTL_ALLOW_NS_SHIFT   (16U)
48875 /*! ALLOW_NS - Allow nonsecure mode access
48876  *  0b1..Secure and nonsecure access to this region's registers is allowed
48877  *  0b0..Only secure access to this region's registers is allowed
48878  */
48879 #define IEE_APC_REGION0_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION0_ACC_CTL_ALLOW_NS_MASK)
48880 
48881 #define IEE_APC_REGION0_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
48882 #define IEE_APC_REGION0_ACC_CTL_ALLOW_USER_SHIFT (17U)
48883 /*! ALLOW_USER - Allow user mode access
48884  *  0b1..User and privilege access to this region's registers is allowed
48885  *  0b0..Only privilege access to this region's registers is allowed
48886  */
48887 #define IEE_APC_REGION0_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION0_ACC_CTL_ALLOW_USER_MASK)
48888 
48889 #define IEE_APC_REGION0_ACC_CTL_LOCK_H_MASK      (0x80000000U)
48890 #define IEE_APC_REGION0_ACC_CTL_LOCK_H_SHIFT     (31U)
48891 /*! LOCK_H - Lock bit for the higher half word
48892  *  0b0..Higher half word is not locked
48893  *  0b1..Higher half word is locked
48894  */
48895 #define IEE_APC_REGION0_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION0_ACC_CTL_LOCK_H_MASK)
48896 /*! @} */
48897 
48898 /*! @name REGION1_TOP_ADDR - End address of IEE region (n) */
48899 /*! @{ */
48900 
48901 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
48902 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
48903 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48904 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
48905 /*! @} */
48906 
48907 /*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */
48908 /*! @{ */
48909 
48910 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
48911 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
48912 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48913 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
48914 /*! @} */
48915 
48916 /*! @name REGION1_ENA - Region enable for region (n) */
48917 /*! @{ */
48918 
48919 #define IEE_APC_REGION1_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
48920 #define IEE_APC_REGION1_ENA_ENCRYPT_ENABLE_SHIFT (0U)
48921 /*! ENCRYPT_ENABLE - Enable this region
48922  *  0b1..This region is enabled for IEE routing once hit
48923  *  0b0..This region is not enabled for IEE routing even hit
48924  */
48925 #define IEE_APC_REGION1_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION1_ENA_ENCRYPT_ENABLE_MASK)
48926 /*! @} */
48927 
48928 /*! @name REGION1_ACC_CTL - Access control for IEE APC registers of region (n) */
48929 /*! @{ */
48930 
48931 #define IEE_APC_REGION1_ACC_CTL_ALLOW_DID_MASK   (0xFU)
48932 #define IEE_APC_REGION1_ACC_CTL_ALLOW_DID_SHIFT  (0U)
48933 /*! ALLOW_DID - Allowed domain ID */
48934 #define IEE_APC_REGION1_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION1_ACC_CTL_ALLOW_DID_MASK)
48935 
48936 #define IEE_APC_REGION1_ACC_CTL_LOCK_L_MASK      (0x8000U)
48937 #define IEE_APC_REGION1_ACC_CTL_LOCK_L_SHIFT     (15U)
48938 /*! LOCK_L - Lock bit for the lower half word
48939  *  0b0..Lower half word is not locked
48940  *  0b1..Lower half word is locked
48941  */
48942 #define IEE_APC_REGION1_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION1_ACC_CTL_LOCK_L_MASK)
48943 
48944 #define IEE_APC_REGION1_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
48945 #define IEE_APC_REGION1_ACC_CTL_ALLOW_NS_SHIFT   (16U)
48946 /*! ALLOW_NS - Allow nonsecure mode access
48947  *  0b1..Secure and nonsecure access to this region's registers is allowed
48948  *  0b0..Only secure access to this region's registers is allowed
48949  */
48950 #define IEE_APC_REGION1_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION1_ACC_CTL_ALLOW_NS_MASK)
48951 
48952 #define IEE_APC_REGION1_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
48953 #define IEE_APC_REGION1_ACC_CTL_ALLOW_USER_SHIFT (17U)
48954 /*! ALLOW_USER - Allow user mode access
48955  *  0b1..User and privilege access to this region's registers is allowed
48956  *  0b0..Only privilege access to this region's registers is allowed
48957  */
48958 #define IEE_APC_REGION1_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION1_ACC_CTL_ALLOW_USER_MASK)
48959 
48960 #define IEE_APC_REGION1_ACC_CTL_LOCK_H_MASK      (0x80000000U)
48961 #define IEE_APC_REGION1_ACC_CTL_LOCK_H_SHIFT     (31U)
48962 /*! LOCK_H - Lock bit for the higher half word
48963  *  0b0..Higher half word is not locked
48964  *  0b1..Higher half word is locked
48965  */
48966 #define IEE_APC_REGION1_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION1_ACC_CTL_LOCK_H_MASK)
48967 /*! @} */
48968 
48969 /*! @name REGION2_TOP_ADDR - End address of IEE region (n) */
48970 /*! @{ */
48971 
48972 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
48973 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
48974 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48975 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
48976 /*! @} */
48977 
48978 /*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */
48979 /*! @{ */
48980 
48981 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
48982 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
48983 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
48984 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
48985 /*! @} */
48986 
48987 /*! @name REGION2_ENA - Region enable for region (n) */
48988 /*! @{ */
48989 
48990 #define IEE_APC_REGION2_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
48991 #define IEE_APC_REGION2_ENA_ENCRYPT_ENABLE_SHIFT (0U)
48992 /*! ENCRYPT_ENABLE - Enable this region
48993  *  0b1..This region is enabled for IEE routing once hit
48994  *  0b0..This region is not enabled for IEE routing even hit
48995  */
48996 #define IEE_APC_REGION2_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION2_ENA_ENCRYPT_ENABLE_MASK)
48997 /*! @} */
48998 
48999 /*! @name REGION2_ACC_CTL - Access control for IEE APC registers of region (n) */
49000 /*! @{ */
49001 
49002 #define IEE_APC_REGION2_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49003 #define IEE_APC_REGION2_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49004 /*! ALLOW_DID - Allowed domain ID */
49005 #define IEE_APC_REGION2_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION2_ACC_CTL_ALLOW_DID_MASK)
49006 
49007 #define IEE_APC_REGION2_ACC_CTL_LOCK_L_MASK      (0x8000U)
49008 #define IEE_APC_REGION2_ACC_CTL_LOCK_L_SHIFT     (15U)
49009 /*! LOCK_L - Lock bit for the lower half word
49010  *  0b0..Lower half word is not locked
49011  *  0b1..Lower half word is locked
49012  */
49013 #define IEE_APC_REGION2_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION2_ACC_CTL_LOCK_L_MASK)
49014 
49015 #define IEE_APC_REGION2_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49016 #define IEE_APC_REGION2_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49017 /*! ALLOW_NS - Allow nonsecure mode access
49018  *  0b1..Secure and nonsecure access to this region's registers is allowed
49019  *  0b0..Only secure access to this region's registers is allowed
49020  */
49021 #define IEE_APC_REGION2_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION2_ACC_CTL_ALLOW_NS_MASK)
49022 
49023 #define IEE_APC_REGION2_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49024 #define IEE_APC_REGION2_ACC_CTL_ALLOW_USER_SHIFT (17U)
49025 /*! ALLOW_USER - Allow user mode access
49026  *  0b1..User and privilege access to this region's registers is allowed
49027  *  0b0..Only privilege access to this region's registers is allowed
49028  */
49029 #define IEE_APC_REGION2_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION2_ACC_CTL_ALLOW_USER_MASK)
49030 
49031 #define IEE_APC_REGION2_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49032 #define IEE_APC_REGION2_ACC_CTL_LOCK_H_SHIFT     (31U)
49033 /*! LOCK_H - Lock bit for the higher half word
49034  *  0b0..Higher half word is not locked
49035  *  0b1..Higher half word is locked
49036  */
49037 #define IEE_APC_REGION2_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION2_ACC_CTL_LOCK_H_MASK)
49038 /*! @} */
49039 
49040 /*! @name REGION3_TOP_ADDR - End address of IEE region (n) */
49041 /*! @{ */
49042 
49043 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
49044 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
49045 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49046 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
49047 /*! @} */
49048 
49049 /*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */
49050 /*! @{ */
49051 
49052 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
49053 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
49054 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49055 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
49056 /*! @} */
49057 
49058 /*! @name REGION3_ENA - Region enable for region (n) */
49059 /*! @{ */
49060 
49061 #define IEE_APC_REGION3_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
49062 #define IEE_APC_REGION3_ENA_ENCRYPT_ENABLE_SHIFT (0U)
49063 /*! ENCRYPT_ENABLE - Enable this region
49064  *  0b1..This region is enabled for IEE routing once hit
49065  *  0b0..This region is not enabled for IEE routing even hit
49066  */
49067 #define IEE_APC_REGION3_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION3_ENA_ENCRYPT_ENABLE_MASK)
49068 /*! @} */
49069 
49070 /*! @name REGION3_ACC_CTL - Access control for IEE APC registers of region (n) */
49071 /*! @{ */
49072 
49073 #define IEE_APC_REGION3_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49074 #define IEE_APC_REGION3_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49075 /*! ALLOW_DID - Allowed domain ID */
49076 #define IEE_APC_REGION3_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION3_ACC_CTL_ALLOW_DID_MASK)
49077 
49078 #define IEE_APC_REGION3_ACC_CTL_LOCK_L_MASK      (0x8000U)
49079 #define IEE_APC_REGION3_ACC_CTL_LOCK_L_SHIFT     (15U)
49080 /*! LOCK_L - Lock bit for the lower half word
49081  *  0b0..Lower half word is not locked
49082  *  0b1..Lower half word is locked
49083  */
49084 #define IEE_APC_REGION3_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION3_ACC_CTL_LOCK_L_MASK)
49085 
49086 #define IEE_APC_REGION3_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49087 #define IEE_APC_REGION3_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49088 /*! ALLOW_NS - Allow nonsecure mode access
49089  *  0b1..Secure and nonsecure access to this region's registers is allowed
49090  *  0b0..Only secure access to this region's registers is allowed
49091  */
49092 #define IEE_APC_REGION3_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION3_ACC_CTL_ALLOW_NS_MASK)
49093 
49094 #define IEE_APC_REGION3_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49095 #define IEE_APC_REGION3_ACC_CTL_ALLOW_USER_SHIFT (17U)
49096 /*! ALLOW_USER - Allow user mode access
49097  *  0b1..User and privilege access to this region's registers is allowed
49098  *  0b0..Only privilege access to this region's registers is allowed
49099  */
49100 #define IEE_APC_REGION3_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION3_ACC_CTL_ALLOW_USER_MASK)
49101 
49102 #define IEE_APC_REGION3_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49103 #define IEE_APC_REGION3_ACC_CTL_LOCK_H_SHIFT     (31U)
49104 /*! LOCK_H - Lock bit for the higher half word
49105  *  0b0..Higher half word is not locked
49106  *  0b1..Higher half word is locked
49107  */
49108 #define IEE_APC_REGION3_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION3_ACC_CTL_LOCK_H_MASK)
49109 /*! @} */
49110 
49111 /*! @name REGION4_TOP_ADDR - End address of IEE region (n) */
49112 /*! @{ */
49113 
49114 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
49115 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
49116 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49117 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
49118 /*! @} */
49119 
49120 /*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */
49121 /*! @{ */
49122 
49123 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
49124 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
49125 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49126 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
49127 /*! @} */
49128 
49129 /*! @name REGION4_ENA - Region enable for region (n) */
49130 /*! @{ */
49131 
49132 #define IEE_APC_REGION4_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
49133 #define IEE_APC_REGION4_ENA_ENCRYPT_ENABLE_SHIFT (0U)
49134 /*! ENCRYPT_ENABLE - Enable this region
49135  *  0b1..This region is enabled for IEE routing once hit
49136  *  0b0..This region is not enabled for IEE routing even hit
49137  */
49138 #define IEE_APC_REGION4_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION4_ENA_ENCRYPT_ENABLE_MASK)
49139 /*! @} */
49140 
49141 /*! @name REGION4_ACC_CTL - Access control for IEE APC registers of region (n) */
49142 /*! @{ */
49143 
49144 #define IEE_APC_REGION4_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49145 #define IEE_APC_REGION4_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49146 /*! ALLOW_DID - Allowed domain ID */
49147 #define IEE_APC_REGION4_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION4_ACC_CTL_ALLOW_DID_MASK)
49148 
49149 #define IEE_APC_REGION4_ACC_CTL_LOCK_L_MASK      (0x8000U)
49150 #define IEE_APC_REGION4_ACC_CTL_LOCK_L_SHIFT     (15U)
49151 /*! LOCK_L - Lock bit for the lower half word
49152  *  0b0..Lower half word is not locked
49153  *  0b1..Lower half word is locked
49154  */
49155 #define IEE_APC_REGION4_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION4_ACC_CTL_LOCK_L_MASK)
49156 
49157 #define IEE_APC_REGION4_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49158 #define IEE_APC_REGION4_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49159 /*! ALLOW_NS - Allow nonsecure mode access
49160  *  0b1..Secure and nonsecure access to this region's registers is allowed
49161  *  0b0..Only secure access to this region's registers is allowed
49162  */
49163 #define IEE_APC_REGION4_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION4_ACC_CTL_ALLOW_NS_MASK)
49164 
49165 #define IEE_APC_REGION4_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49166 #define IEE_APC_REGION4_ACC_CTL_ALLOW_USER_SHIFT (17U)
49167 /*! ALLOW_USER - Allow user mode access
49168  *  0b1..User and privilege access to this region's registers is allowed
49169  *  0b0..Only privilege access to this region's registers is allowed
49170  */
49171 #define IEE_APC_REGION4_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION4_ACC_CTL_ALLOW_USER_MASK)
49172 
49173 #define IEE_APC_REGION4_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49174 #define IEE_APC_REGION4_ACC_CTL_LOCK_H_SHIFT     (31U)
49175 /*! LOCK_H - Lock bit for the higher half word
49176  *  0b0..Higher half word is not locked
49177  *  0b1..Higher half word is locked
49178  */
49179 #define IEE_APC_REGION4_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION4_ACC_CTL_LOCK_H_MASK)
49180 /*! @} */
49181 
49182 /*! @name REGION5_TOP_ADDR - End address of IEE region (n) */
49183 /*! @{ */
49184 
49185 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
49186 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
49187 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49188 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
49189 /*! @} */
49190 
49191 /*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */
49192 /*! @{ */
49193 
49194 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
49195 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
49196 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49197 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
49198 /*! @} */
49199 
49200 /*! @name REGION5_ENA - Region enable for region (n) */
49201 /*! @{ */
49202 
49203 #define IEE_APC_REGION5_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
49204 #define IEE_APC_REGION5_ENA_ENCRYPT_ENABLE_SHIFT (0U)
49205 /*! ENCRYPT_ENABLE - Enable this region
49206  *  0b1..This region is enabled for IEE routing once hit
49207  *  0b0..This region is not enabled for IEE routing even hit
49208  */
49209 #define IEE_APC_REGION5_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION5_ENA_ENCRYPT_ENABLE_MASK)
49210 /*! @} */
49211 
49212 /*! @name REGION5_ACC_CTL - Access control for IEE APC registers of region (n) */
49213 /*! @{ */
49214 
49215 #define IEE_APC_REGION5_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49216 #define IEE_APC_REGION5_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49217 /*! ALLOW_DID - Allowed domain ID */
49218 #define IEE_APC_REGION5_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION5_ACC_CTL_ALLOW_DID_MASK)
49219 
49220 #define IEE_APC_REGION5_ACC_CTL_LOCK_L_MASK      (0x8000U)
49221 #define IEE_APC_REGION5_ACC_CTL_LOCK_L_SHIFT     (15U)
49222 /*! LOCK_L - Lock bit for the lower half word
49223  *  0b0..Lower half word is not locked
49224  *  0b1..Lower half word is locked
49225  */
49226 #define IEE_APC_REGION5_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION5_ACC_CTL_LOCK_L_MASK)
49227 
49228 #define IEE_APC_REGION5_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49229 #define IEE_APC_REGION5_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49230 /*! ALLOW_NS - Allow nonsecure mode access
49231  *  0b1..Secure and nonsecure access to this region's registers is allowed
49232  *  0b0..Only secure access to this region's registers is allowed
49233  */
49234 #define IEE_APC_REGION5_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION5_ACC_CTL_ALLOW_NS_MASK)
49235 
49236 #define IEE_APC_REGION5_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49237 #define IEE_APC_REGION5_ACC_CTL_ALLOW_USER_SHIFT (17U)
49238 /*! ALLOW_USER - Allow user mode access
49239  *  0b1..User and privilege access to this region's registers is allowed
49240  *  0b0..Only privilege access to this region's registers is allowed
49241  */
49242 #define IEE_APC_REGION5_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION5_ACC_CTL_ALLOW_USER_MASK)
49243 
49244 #define IEE_APC_REGION5_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49245 #define IEE_APC_REGION5_ACC_CTL_LOCK_H_SHIFT     (31U)
49246 /*! LOCK_H - Lock bit for the higher half word
49247  *  0b0..Higher half word is not locked
49248  *  0b1..Higher half word is locked
49249  */
49250 #define IEE_APC_REGION5_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION5_ACC_CTL_LOCK_H_MASK)
49251 /*! @} */
49252 
49253 /*! @name REGION6_TOP_ADDR - End address of IEE region (n) */
49254 /*! @{ */
49255 
49256 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
49257 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
49258 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49259 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
49260 /*! @} */
49261 
49262 /*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */
49263 /*! @{ */
49264 
49265 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
49266 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
49267 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49268 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
49269 /*! @} */
49270 
49271 /*! @name REGION6_ENA - Region enable for region (n) */
49272 /*! @{ */
49273 
49274 #define IEE_APC_REGION6_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
49275 #define IEE_APC_REGION6_ENA_ENCRYPT_ENABLE_SHIFT (0U)
49276 /*! ENCRYPT_ENABLE - Enable this region
49277  *  0b1..This region is enabled for IEE routing once hit
49278  *  0b0..This region is not enabled for IEE routing even hit
49279  */
49280 #define IEE_APC_REGION6_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION6_ENA_ENCRYPT_ENABLE_MASK)
49281 /*! @} */
49282 
49283 /*! @name REGION6_ACC_CTL - Access control for IEE APC registers of region (n) */
49284 /*! @{ */
49285 
49286 #define IEE_APC_REGION6_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49287 #define IEE_APC_REGION6_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49288 /*! ALLOW_DID - Allowed domain ID */
49289 #define IEE_APC_REGION6_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION6_ACC_CTL_ALLOW_DID_MASK)
49290 
49291 #define IEE_APC_REGION6_ACC_CTL_LOCK_L_MASK      (0x8000U)
49292 #define IEE_APC_REGION6_ACC_CTL_LOCK_L_SHIFT     (15U)
49293 /*! LOCK_L - Lock bit for the lower half word
49294  *  0b0..Lower half word is not locked
49295  *  0b1..Lower half word is locked
49296  */
49297 #define IEE_APC_REGION6_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION6_ACC_CTL_LOCK_L_MASK)
49298 
49299 #define IEE_APC_REGION6_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49300 #define IEE_APC_REGION6_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49301 /*! ALLOW_NS - Allow nonsecure mode access
49302  *  0b1..Secure and nonsecure access to this region's registers is allowed
49303  *  0b0..Only secure access to this region's registers is allowed
49304  */
49305 #define IEE_APC_REGION6_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION6_ACC_CTL_ALLOW_NS_MASK)
49306 
49307 #define IEE_APC_REGION6_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49308 #define IEE_APC_REGION6_ACC_CTL_ALLOW_USER_SHIFT (17U)
49309 /*! ALLOW_USER - Allow user mode access
49310  *  0b1..User and privilege access to this region's registers is allowed
49311  *  0b0..Only privilege access to this region's registers is allowed
49312  */
49313 #define IEE_APC_REGION6_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION6_ACC_CTL_ALLOW_USER_MASK)
49314 
49315 #define IEE_APC_REGION6_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49316 #define IEE_APC_REGION6_ACC_CTL_LOCK_H_SHIFT     (31U)
49317 /*! LOCK_H - Lock bit for the higher half word
49318  *  0b0..Higher half word is not locked
49319  *  0b1..Higher half word is locked
49320  */
49321 #define IEE_APC_REGION6_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION6_ACC_CTL_LOCK_H_MASK)
49322 /*! @} */
49323 
49324 /*! @name REGION7_TOP_ADDR - End address of IEE region (n) */
49325 /*! @{ */
49326 
49327 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK   (0xFFFFFFC0U)
49328 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT  (6U)
49329 /*! TOP_ADDR - End address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49330 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
49331 /*! @} */
49332 
49333 /*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */
49334 /*! @{ */
49335 
49336 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK   (0xFFFFFFC0U)
49337 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT  (6U)
49338 /*! BOT_ADDR - Start address[31:6] of IEE region. The lower 6 address bits of IEE region is always 0. */
49339 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
49340 /*! @} */
49341 
49342 /*! @name REGION7_ENA - Region enable for region (n) */
49343 /*! @{ */
49344 
49345 #define IEE_APC_REGION7_ENA_ENCRYPT_ENABLE_MASK  (0x1U)
49346 #define IEE_APC_REGION7_ENA_ENCRYPT_ENABLE_SHIFT (0U)
49347 /*! ENCRYPT_ENABLE - Enable this region
49348  *  0b1..This region is enabled for IEE routing once hit
49349  *  0b0..This region is not enabled for IEE routing even hit
49350  */
49351 #define IEE_APC_REGION7_ENA_ENCRYPT_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ENA_ENCRYPT_ENABLE_SHIFT)) & IEE_APC_REGION7_ENA_ENCRYPT_ENABLE_MASK)
49352 /*! @} */
49353 
49354 /*! @name REGION7_ACC_CTL - Access control for IEE APC registers of region (n) */
49355 /*! @{ */
49356 
49357 #define IEE_APC_REGION7_ACC_CTL_ALLOW_DID_MASK   (0xFU)
49358 #define IEE_APC_REGION7_ACC_CTL_ALLOW_DID_SHIFT  (0U)
49359 /*! ALLOW_DID - Allowed domain ID */
49360 #define IEE_APC_REGION7_ACC_CTL_ALLOW_DID(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ACC_CTL_ALLOW_DID_SHIFT)) & IEE_APC_REGION7_ACC_CTL_ALLOW_DID_MASK)
49361 
49362 #define IEE_APC_REGION7_ACC_CTL_LOCK_L_MASK      (0x8000U)
49363 #define IEE_APC_REGION7_ACC_CTL_LOCK_L_SHIFT     (15U)
49364 /*! LOCK_L - Lock bit for the lower half word
49365  *  0b0..Lower half word is not locked
49366  *  0b1..Lower half word is locked
49367  */
49368 #define IEE_APC_REGION7_ACC_CTL_LOCK_L(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ACC_CTL_LOCK_L_SHIFT)) & IEE_APC_REGION7_ACC_CTL_LOCK_L_MASK)
49369 
49370 #define IEE_APC_REGION7_ACC_CTL_ALLOW_NS_MASK    (0x10000U)
49371 #define IEE_APC_REGION7_ACC_CTL_ALLOW_NS_SHIFT   (16U)
49372 /*! ALLOW_NS - Allow nonsecure mode access
49373  *  0b1..Secure and nonsecure access to this region's registers is allowed
49374  *  0b0..Only secure access to this region's registers is allowed
49375  */
49376 #define IEE_APC_REGION7_ACC_CTL_ALLOW_NS(x)      (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ACC_CTL_ALLOW_NS_SHIFT)) & IEE_APC_REGION7_ACC_CTL_ALLOW_NS_MASK)
49377 
49378 #define IEE_APC_REGION7_ACC_CTL_ALLOW_USER_MASK  (0x20000U)
49379 #define IEE_APC_REGION7_ACC_CTL_ALLOW_USER_SHIFT (17U)
49380 /*! ALLOW_USER - Allow user mode access
49381  *  0b1..User and privilege access to this region's registers is allowed
49382  *  0b0..Only privilege access to this region's registers is allowed
49383  */
49384 #define IEE_APC_REGION7_ACC_CTL_ALLOW_USER(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ACC_CTL_ALLOW_USER_SHIFT)) & IEE_APC_REGION7_ACC_CTL_ALLOW_USER_MASK)
49385 
49386 #define IEE_APC_REGION7_ACC_CTL_LOCK_H_MASK      (0x80000000U)
49387 #define IEE_APC_REGION7_ACC_CTL_LOCK_H_SHIFT     (31U)
49388 /*! LOCK_H - Lock bit for the higher half word
49389  *  0b0..Higher half word is not locked
49390  *  0b1..Higher half word is locked
49391  */
49392 #define IEE_APC_REGION7_ACC_CTL_LOCK_H(x)        (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_ACC_CTL_LOCK_H_SHIFT)) & IEE_APC_REGION7_ACC_CTL_LOCK_H_MASK)
49393 /*! @} */
49394 
49395 
49396 /*!
49397  * @}
49398  */ /* end of group IEE_APC_Register_Masks */
49399 
49400 
49401 /* IEE_APC - Peripheral instance base addresses */
49402 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
49403   /** Peripheral IEE_APC base address */
49404   #define IEE_APC_BASE                             (0x52E44000u)
49405   /** Peripheral IEE_APC base address */
49406   #define IEE_APC_BASE_NS                          (0x42E44000u)
49407   /** Peripheral IEE_APC base pointer */
49408   #define IEE_APC                                  ((IEE_APC_Type *)IEE_APC_BASE)
49409   /** Peripheral IEE_APC base pointer */
49410   #define IEE_APC_NS                               ((IEE_APC_Type *)IEE_APC_BASE_NS)
49411   /** Array initializer of IEE_APC peripheral base addresses */
49412   #define IEE_APC_BASE_ADDRS                       { IEE_APC_BASE }
49413   /** Array initializer of IEE_APC peripheral base pointers */
49414   #define IEE_APC_BASE_PTRS                        { IEE_APC }
49415   /** Array initializer of IEE_APC peripheral base addresses */
49416   #define IEE_APC_BASE_ADDRS_NS                    { IEE_APC_BASE_NS }
49417   /** Array initializer of IEE_APC peripheral base pointers */
49418   #define IEE_APC_BASE_PTRS_NS                     { IEE_APC_NS }
49419 #else
49420   /** Peripheral IEE_APC base address */
49421   #define IEE_APC_BASE                             (0x42E44000u)
49422   /** Peripheral IEE_APC base pointer */
49423   #define IEE_APC                                  ((IEE_APC_Type *)IEE_APC_BASE)
49424   /** Array initializer of IEE_APC peripheral base addresses */
49425   #define IEE_APC_BASE_ADDRS                       { IEE_APC_BASE }
49426   /** Array initializer of IEE_APC peripheral base pointers */
49427   #define IEE_APC_BASE_PTRS                        { IEE_APC }
49428 #endif
49429 
49430 /*!
49431  * @}
49432  */ /* end of group IEE_APC_Peripheral_Access_Layer */
49433 
49434 
49435 /* ----------------------------------------------------------------------------
49436    -- IERC_IERB Peripheral Access Layer
49437    ---------------------------------------------------------------------------- */
49438 
49439 /*!
49440  * @addtogroup IERC_IERB_Peripheral_Access_Layer IERC_IERB Peripheral Access Layer
49441  * @{
49442  */
49443 
49444 /** IERC_IERB - Register Layout Typedef */
49445 typedef struct {
49446   __IO uint32_t F0_EC_CFH_DIDVID;                  /**< Function 0 EC config header device ID and vendor ID register, offset: 0x0 */
49447   __IO uint32_t F0_EC_CFH_SIDSVID;                 /**< Function 0 EC config header subsystem ID and subsystem vendor ID register, offset: 0x4 */
49448 } IERC_IERB_Type;
49449 
49450 /* ----------------------------------------------------------------------------
49451    -- IERC_IERB Register Masks
49452    ---------------------------------------------------------------------------- */
49453 
49454 /*!
49455  * @addtogroup IERC_IERB_Register_Masks IERC_IERB Register Masks
49456  * @{
49457  */
49458 
49459 /*! @name F0_EC_CFH_DIDVID - Function 0 EC config header device ID and vendor ID register */
49460 /*! @{ */
49461 
49462 #define IERC_IERB_F0_EC_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU)
49463 #define IERC_IERB_F0_EC_CFH_DIDVID_VENDOR_ID_SHIFT (0U)
49464 #define IERC_IERB_F0_EC_CFH_DIDVID_VENDOR_ID(x)  (((uint32_t)(((uint32_t)(x)) << IERC_IERB_F0_EC_CFH_DIDVID_VENDOR_ID_SHIFT)) & IERC_IERB_F0_EC_CFH_DIDVID_VENDOR_ID_MASK)
49465 
49466 #define IERC_IERB_F0_EC_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U)
49467 #define IERC_IERB_F0_EC_CFH_DIDVID_DEVICE_ID_SHIFT (16U)
49468 #define IERC_IERB_F0_EC_CFH_DIDVID_DEVICE_ID(x)  (((uint32_t)(((uint32_t)(x)) << IERC_IERB_F0_EC_CFH_DIDVID_DEVICE_ID_SHIFT)) & IERC_IERB_F0_EC_CFH_DIDVID_DEVICE_ID_MASK)
49469 /*! @} */
49470 
49471 /*! @name F0_EC_CFH_SIDSVID - Function 0 EC config header subsystem ID and subsystem vendor ID register */
49472 /*! @{ */
49473 
49474 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
49475 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
49476 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK)
49477 
49478 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U)
49479 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U)
49480 #define IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & IERC_IERB_F0_EC_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK)
49481 /*! @} */
49482 
49483 
49484 /*!
49485  * @}
49486  */ /* end of group IERC_IERB_Register_Masks */
49487 
49488 
49489 /* IERC_IERB - Peripheral instance base addresses */
49490 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
49491   /** Peripheral IERC_IERB base address */
49492   #define IERC_IERB_BASE                           (0x70810000u)
49493   /** Peripheral IERC_IERB base address */
49494   #define IERC_IERB_BASE_NS                        (0x60810000u)
49495   /** Peripheral IERC_IERB base pointer */
49496   #define IERC_IERB                                ((IERC_IERB_Type *)IERC_IERB_BASE)
49497   /** Peripheral IERC_IERB base pointer */
49498   #define IERC_IERB_NS                             ((IERC_IERB_Type *)IERC_IERB_BASE_NS)
49499   /** Array initializer of IERC_IERB peripheral base addresses */
49500   #define IERC_IERB_BASE_ADDRS                     { IERC_IERB_BASE }
49501   /** Array initializer of IERC_IERB peripheral base pointers */
49502   #define IERC_IERB_BASE_PTRS                      { IERC_IERB }
49503   /** Array initializer of IERC_IERB peripheral base addresses */
49504   #define IERC_IERB_BASE_ADDRS_NS                  { IERC_IERB_BASE_NS }
49505   /** Array initializer of IERC_IERB peripheral base pointers */
49506   #define IERC_IERB_BASE_PTRS_NS                   { IERC_IERB_NS }
49507 #else
49508   /** Peripheral IERC_IERB base address */
49509   #define IERC_IERB_BASE                           (0x60810000u)
49510   /** Peripheral IERC_IERB base pointer */
49511   #define IERC_IERB                                ((IERC_IERB_Type *)IERC_IERB_BASE)
49512   /** Array initializer of IERC_IERB peripheral base addresses */
49513   #define IERC_IERB_BASE_ADDRS                     { IERC_IERB_BASE }
49514   /** Array initializer of IERC_IERB peripheral base pointers */
49515   #define IERC_IERB_BASE_PTRS                      { IERC_IERB }
49516 #endif
49517 
49518 /*!
49519  * @}
49520  */ /* end of group IERC_IERB_Peripheral_Access_Layer */
49521 
49522 
49523 /* ----------------------------------------------------------------------------
49524    -- IERC_PCI Peripheral Access Layer
49525    ---------------------------------------------------------------------------- */
49526 
49527 /*!
49528  * @addtogroup IERC_PCI_Peripheral_Access_Layer IERC_PCI Peripheral Access Layer
49529  * @{
49530  */
49531 
49532 /** IERC_PCI - Register Layout Typedef */
49533 typedef struct {
49534   __I  uint32_t PCI_CFH_DID_VID;                   /**< PCI device ID and vendor ID register, offset: 0x0 */
49535   __IO uint16_t PCI_CFH_CMD;                       /**< PCI command register, offset: 0x4 */
49536   __I  uint16_t PCI_CFH_STAT;                      /**< PCI status register, offset: 0x6 */
49537   __I  uint32_t PCI_CFH_REVID_CLASSCODE;           /**< PCI revision ID and classcode register, offset: 0x8 */
49538   __IO uint8_t PCI_CFH_CL_SIZE;                    /**< PCI cache line size register, offset: 0xC */
49539        uint8_t RESERVED_0[1];
49540   __I  uint8_t PCI_CFH_HDR_TYPE;                   /**< PCI header type register, offset: 0xE */
49541        uint8_t RESERVED_1[29];
49542   __I  uint16_t PCI_CFH_SUBSYS_VID;                /**< PCI subsystem vendor ID register, offset: 0x2C */
49543   __I  uint16_t PCI_CFH_SUBSYS_ID;                 /**< PCI subsystem ID register, offset: 0x2E */
49544        uint8_t RESERVED_2[4];
49545   __I  uint8_t PCI_CFH_CAP_PTR;                    /**< PCI capabilities pointer register, offset: 0x34 */
49546        uint8_t RESERVED_3[7];
49547   __IO uint8_t PCI_CFH_INT_LINE;                   /**< PCI interrupt line register, offset: 0x3C */
49548   __I  uint8_t PCI_CFH_INT_PIN;                    /**< PCI interrupt pin register, offset: 0x3D */
49549        uint8_t RESERVED_4[2];
49550   __I  uint16_t PCI_CFC_PCIE_CAP_LIST;             /**< PCI PCIe capabilities list register, offset: 0x40 */
49551   __I  uint16_t PCI_CFC_PCIE_CAP;                  /**< PCI PCIe capabilities register, offset: 0x42 */
49552   __I  uint32_t PCI_CFC_PCIE_DEV_CAP;              /**< PCI PCIe device capabilities register, offset: 0x44 */
49553        uint8_t RESERVED_5[2];
49554   __I  uint16_t PCI_CFC_PCIE_DEV_STAT;             /**< PCI PCIe device status register, offset: 0x4A */
49555        uint8_t RESERVED_6[16];
49556   __IO uint16_t PCI_CFC_PCIE_ROOT_CTL;             /**< PCI PCIe root control register, offset: 0x5C */
49557        uint8_t RESERVED_7[2];
49558   __IO uint32_t PCI_CFC_PCIE_ROOT_STAT;            /**< PCI PCIe root status register, offset: 0x60 */
49559        uint8_t RESERVED_8[28];
49560   __I  uint16_t PCI_CFC_PCIPM_CAP_LIST;            /**< PCI PCI-PM capabilities list register, offset: 0x80 */
49561   __I  uint16_t PCI_CFC_PCIPM_CAP;                 /**< PCI PCI-PM capabilities register, offset: 0x82 */
49562   __IO uint16_t PCI_CFC_PCIPM_CTL_STAT;            /**< PCI PCI-PM control and status register, offset: 0x84 */
49563        uint8_t RESERVED_9[1];
49564        uint8_t PCI_CFC_PCIPM_DATA;                 /**< PCI PCI-PM capabilities data register, offset: 0x87 */
49565        uint8_t RESERVED_10[120];
49566   __I  uint32_t PCIE_CFC_AER_EXT_CAP_HDR;          /**< PCIe AER extended capability header, offset: 0x100 */
49567        uint8_t RESERVED_11[40];
49568   __IO uint32_t PCIE_CFC_AER_ROOT_ERR_CMD;         /**< PCIe AER root error command register, offset: 0x12C */
49569   __IO uint32_t PCIE_CFC_AER_ROOT_ERR_STAT;        /**< PCIe AER root error status register, offset: 0x130 */
49570   __I  uint32_t PCIE_CFC_AER_ERR_SRC_ID;           /**< PCIe AER error source identification register, offset: 0x134 */
49571   __I  uint32_t PCIE_CFC_RCEC_EPA_EXT_CAP_HDR;     /**< PCIe RCEC Endpoint association extended capability header, offset: 0x138 */
49572   __I  uint32_t PCIE_CFC_RCEC_EPA_BITMAP;          /**< PCIe RCEC Endpoint association bitmap registerr, offset: 0x13C */
49573 } IERC_PCI_Type;
49574 
49575 /* ----------------------------------------------------------------------------
49576    -- IERC_PCI Register Masks
49577    ---------------------------------------------------------------------------- */
49578 
49579 /*!
49580  * @addtogroup IERC_PCI_Register_Masks IERC_PCI Register Masks
49581  * @{
49582  */
49583 
49584 /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */
49585 /*! @{ */
49586 
49587 #define IERC_PCI_PCI_CFH_DID_VID_VENDOR_ID_MASK  (0xFFFFU)
49588 #define IERC_PCI_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U)
49589 #define IERC_PCI_PCI_CFH_DID_VID_VENDOR_ID(x)    (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & IERC_PCI_PCI_CFH_DID_VID_VENDOR_ID_MASK)
49590 
49591 #define IERC_PCI_PCI_CFH_DID_VID_DEVICE_ID_MASK  (0xFFFF0000U)
49592 #define IERC_PCI_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U)
49593 #define IERC_PCI_PCI_CFH_DID_VID_DEVICE_ID(x)    (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & IERC_PCI_PCI_CFH_DID_VID_DEVICE_ID_MASK)
49594 /*! @} */
49595 
49596 /*! @name PCI_CFH_CMD - PCI command register */
49597 /*! @{ */
49598 
49599 #define IERC_PCI_PCI_CFH_CMD_INTR_DISABLE_MASK   (0x400U)
49600 #define IERC_PCI_PCI_CFH_CMD_INTR_DISABLE_SHIFT  (10U)
49601 #define IERC_PCI_PCI_CFH_CMD_INTR_DISABLE(x)     (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFH_CMD_INTR_DISABLE_SHIFT)) & IERC_PCI_PCI_CFH_CMD_INTR_DISABLE_MASK)
49602 /*! @} */
49603 
49604 /*! @name PCI_CFH_STAT - PCI status register */
49605 /*! @{ */
49606 
49607 #define IERC_PCI_PCI_CFH_STAT_INTR_STATUS_MASK   (0x8U)
49608 #define IERC_PCI_PCI_CFH_STAT_INTR_STATUS_SHIFT  (3U)
49609 #define IERC_PCI_PCI_CFH_STAT_INTR_STATUS(x)     (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFH_STAT_INTR_STATUS_SHIFT)) & IERC_PCI_PCI_CFH_STAT_INTR_STATUS_MASK)
49610 
49611 #define IERC_PCI_PCI_CFH_STAT_CAP_LIST_MASK      (0x10U)
49612 #define IERC_PCI_PCI_CFH_STAT_CAP_LIST_SHIFT     (4U)
49613 #define IERC_PCI_PCI_CFH_STAT_CAP_LIST(x)        (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFH_STAT_CAP_LIST_SHIFT)) & IERC_PCI_PCI_CFH_STAT_CAP_LIST_MASK)
49614 /*! @} */
49615 
49616 /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */
49617 /*! @{ */
49618 
49619 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU)
49620 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U)
49621 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & IERC_PCI_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK)
49622 
49623 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U)
49624 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U)
49625 #define IERC_PCI_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & IERC_PCI_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK)
49626 /*! @} */
49627 
49628 /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */
49629 /*! @{ */
49630 
49631 #define IERC_PCI_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU)
49632 #define IERC_PCI_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U)
49633 #define IERC_PCI_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & IERC_PCI_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK)
49634 /*! @} */
49635 
49636 /*! @name PCI_CFH_HDR_TYPE - PCI header type register */
49637 /*! @{ */
49638 
49639 #define IERC_PCI_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK  (0x7FU)
49640 #define IERC_PCI_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U)
49641 #define IERC_PCI_PCI_CFH_HDR_TYPE_HDR_TYPE(x)    (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & IERC_PCI_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK)
49642 
49643 #define IERC_PCI_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U)
49644 #define IERC_PCI_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U)
49645 #define IERC_PCI_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & IERC_PCI_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK)
49646 /*! @} */
49647 
49648 /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */
49649 /*! @{ */
49650 
49651 #define IERC_PCI_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
49652 #define IERC_PCI_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
49653 #define IERC_PCI_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT)) & IERC_PCI_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK)
49654 /*! @} */
49655 
49656 /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */
49657 /*! @{ */
49658 
49659 #define IERC_PCI_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK (0xFFFFU)
49660 #define IERC_PCI_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT (0U)
49661 #define IERC_PCI_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT)) & IERC_PCI_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK)
49662 /*! @} */
49663 
49664 /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */
49665 /*! @{ */
49666 
49667 #define IERC_PCI_PCI_CFH_CAP_PTR_CAP_PTR_MASK    (0xFFU)
49668 #define IERC_PCI_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT   (0U)
49669 #define IERC_PCI_PCI_CFH_CAP_PTR_CAP_PTR(x)      (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & IERC_PCI_PCI_CFH_CAP_PTR_CAP_PTR_MASK)
49670 /*! @} */
49671 
49672 /*! @name PCI_CFH_INT_LINE - PCI interrupt line register */
49673 /*! @{ */
49674 
49675 #define IERC_PCI_PCI_CFH_INT_LINE_INT_LINE_MASK  (0xFFU)
49676 #define IERC_PCI_PCI_CFH_INT_LINE_INT_LINE_SHIFT (0U)
49677 #define IERC_PCI_PCI_CFH_INT_LINE_INT_LINE(x)    (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_INT_LINE_INT_LINE_SHIFT)) & IERC_PCI_PCI_CFH_INT_LINE_INT_LINE_MASK)
49678 /*! @} */
49679 
49680 /*! @name PCI_CFH_INT_PIN - PCI interrupt pin register */
49681 /*! @{ */
49682 
49683 #define IERC_PCI_PCI_CFH_INT_PIN_INT_PIN_MASK    (0xFFU)
49684 #define IERC_PCI_PCI_CFH_INT_PIN_INT_PIN_SHIFT   (0U)
49685 #define IERC_PCI_PCI_CFH_INT_PIN_INT_PIN(x)      (((uint8_t)(((uint8_t)(x)) << IERC_PCI_PCI_CFH_INT_PIN_INT_PIN_SHIFT)) & IERC_PCI_PCI_CFH_INT_PIN_INT_PIN_MASK)
49686 /*! @} */
49687 
49688 /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */
49689 /*! @{ */
49690 
49691 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU)
49692 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U)
49693 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK)
49694 
49695 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_MASK (0xFF00U)
49696 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_SHIFT (8U)
49697 #define IERC_PCI_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_MASK)
49698 /*! @} */
49699 
49700 /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */
49701 /*! @{ */
49702 
49703 #define IERC_PCI_PCI_CFC_PCIE_CAP_CAP_VER_MASK   (0xFU)
49704 #define IERC_PCI_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT  (0U)
49705 #define IERC_PCI_PCI_CFC_PCIE_CAP_CAP_VER(x)     (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_CAP_CAP_VER_MASK)
49706 
49707 #define IERC_PCI_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U)
49708 #define IERC_PCI_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U)
49709 #define IERC_PCI_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK)
49710 
49711 #define IERC_PCI_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U)
49712 #define IERC_PCI_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U)
49713 #define IERC_PCI_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK)
49714 /*! @} */
49715 
49716 /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */
49717 /*! @{ */
49718 
49719 #define IERC_PCI_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U)
49720 #define IERC_PCI_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U)
49721 #define IERC_PCI_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK)
49722 /*! @} */
49723 
49724 /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */
49725 /*! @{ */
49726 
49727 #define IERC_PCI_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U)
49728 #define IERC_PCI_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U)
49729 #define IERC_PCI_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK)
49730 /*! @} */
49731 
49732 /*! @name PCI_CFC_PCIE_ROOT_CTL - PCI PCIe root control register */
49733 /*! @{ */
49734 
49735 #define IERC_PCI_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_MASK (0x8U)
49736 #define IERC_PCI_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_SHIFT (3U)
49737 #define IERC_PCI_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_MASK)
49738 /*! @} */
49739 
49740 /*! @name PCI_CFC_PCIE_ROOT_STAT - PCI PCIe root status register */
49741 /*! @{ */
49742 
49743 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_MASK (0xFFFFU)
49744 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_SHIFT (0U)
49745 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_MASK)
49746 
49747 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_MASK (0x10000U)
49748 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_SHIFT (16U)
49749 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_MASK)
49750 
49751 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_MASK (0x20000U)
49752 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_SHIFT (17U)
49753 #define IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_PEND(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_SHIFT)) & IERC_PCI_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_MASK)
49754 /*! @} */
49755 
49756 /*! @name PCI_CFC_PCIPM_CAP_LIST - PCI PCI-PM capabilities list register */
49757 /*! @{ */
49758 
49759 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK (0xFFU)
49760 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT (0U)
49761 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK)
49762 
49763 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_MASK (0xFF00U)
49764 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_SHIFT (8U)
49765 #define IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_MASK)
49766 /*! @} */
49767 
49768 /*! @name PCI_CFC_PCIPM_CAP - PCI PCI-PM capabilities register */
49769 /*! @{ */
49770 
49771 #define IERC_PCI_PCI_CFC_PCIPM_CAP_VERSION_MASK  (0x7U)
49772 #define IERC_PCI_PCI_CFC_PCIPM_CAP_VERSION_SHIFT (0U)
49773 #define IERC_PCI_PCI_CFC_PCIPM_CAP_VERSION(x)    (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CAP_VERSION_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CAP_VERSION_MASK)
49774 
49775 #define IERC_PCI_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK (0xF800U)
49776 #define IERC_PCI_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT (11U)
49777 #define IERC_PCI_PCI_CFC_PCIPM_CAP_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK)
49778 /*! @} */
49779 
49780 /*! @name PCI_CFC_PCIPM_CTL_STAT - PCI PCI-PM control and status register */
49781 /*! @{ */
49782 
49783 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK (0x3U)
49784 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT (0U)
49785 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK)
49786 
49787 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK (0x8U)
49788 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT (3U)
49789 #define IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST(x) (((uint16_t)(((uint16_t)(x)) << IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT)) & IERC_PCI_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK)
49790 /*! @} */
49791 
49792 /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */
49793 /*! @{ */
49794 
49795 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
49796 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
49797 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
49798 
49799 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U)
49800 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U)
49801 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK)
49802 
49803 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
49804 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
49805 #define IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & IERC_PCI_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK)
49806 /*! @} */
49807 
49808 /*! @name PCIE_CFC_AER_ROOT_ERR_CMD - PCIe AER root error command register */
49809 /*! @{ */
49810 
49811 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK (0x1U)
49812 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT (0U)
49813 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK)
49814 
49815 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK (0x2U)
49816 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT (1U)
49817 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK)
49818 
49819 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK (0x4U)
49820 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT (2U)
49821 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK)
49822 /*! @} */
49823 
49824 /*! @name PCIE_CFC_AER_ROOT_ERR_STAT - PCIe AER root error status register */
49825 /*! @{ */
49826 
49827 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK (0x1U)
49828 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT (0U)
49829 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK)
49830 
49831 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK (0x2U)
49832 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT (1U)
49833 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK)
49834 
49835 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK (0x4U)
49836 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT (2U)
49837 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK)
49838 
49839 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK (0x8U)
49840 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT (3U)
49841 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK)
49842 
49843 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK (0x10U)
49844 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT (4U)
49845 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK)
49846 
49847 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK (0x20U)
49848 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT (5U)
49849 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK)
49850 
49851 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK (0x40U)
49852 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT (6U)
49853 #define IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK)
49854 /*! @} */
49855 
49856 /*! @name PCIE_CFC_AER_ERR_SRC_ID - PCIe AER error source identification register */
49857 /*! @{ */
49858 
49859 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK (0xFFFFU)
49860 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT (0U)
49861 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK)
49862 
49863 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK (0xFFFF0000U)
49864 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT (16U)
49865 #define IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT)) & IERC_PCI_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK)
49866 /*! @} */
49867 
49868 /*! @name PCIE_CFC_RCEC_EPA_EXT_CAP_HDR - PCIe RCEC Endpoint association extended capability header */
49869 /*! @{ */
49870 
49871 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU)
49872 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U)
49873 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK)
49874 
49875 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U)
49876 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT (16U)
49877 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT)) & IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK)
49878 
49879 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U)
49880 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U)
49881 #define IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & IERC_PCI_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK)
49882 /*! @} */
49883 
49884 /*! @name PCIE_CFC_RCEC_EPA_BITMAP - PCIe RCEC Endpoint association bitmap registerr */
49885 /*! @{ */
49886 
49887 #define IERC_PCI_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK (0xFFFFFFFFU)
49888 #define IERC_PCI_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT (0U)
49889 #define IERC_PCI_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP(x) (((uint32_t)(((uint32_t)(x)) << IERC_PCI_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT)) & IERC_PCI_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK)
49890 /*! @} */
49891 
49892 
49893 /*!
49894  * @}
49895  */ /* end of group IERC_PCI_Register_Masks */
49896 
49897 
49898 /* IERC_PCI - Peripheral instance base addresses */
49899 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
49900   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base address */
49901   #define IERC_F0_PCI_HDR_TYPE0_BASE               (0x700F8000u)
49902   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base address */
49903   #define IERC_F0_PCI_HDR_TYPE0_BASE_NS            (0x600F8000u)
49904   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base pointer */
49905   #define IERC_F0_PCI_HDR_TYPE0                    ((IERC_PCI_Type *)IERC_F0_PCI_HDR_TYPE0_BASE)
49906   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base pointer */
49907   #define IERC_F0_PCI_HDR_TYPE0_NS                 ((IERC_PCI_Type *)IERC_F0_PCI_HDR_TYPE0_BASE_NS)
49908   /** Array initializer of IERC_PCI peripheral base addresses */
49909   #define IERC_PCI_BASE_ADDRS                      { IERC_F0_PCI_HDR_TYPE0_BASE }
49910   /** Array initializer of IERC_PCI peripheral base pointers */
49911   #define IERC_PCI_BASE_PTRS                       { IERC_F0_PCI_HDR_TYPE0 }
49912   /** Array initializer of IERC_PCI peripheral base addresses */
49913   #define IERC_PCI_BASE_ADDRS_NS                   { IERC_F0_PCI_HDR_TYPE0_BASE_NS }
49914   /** Array initializer of IERC_PCI peripheral base pointers */
49915   #define IERC_PCI_BASE_PTRS_NS                    { IERC_F0_PCI_HDR_TYPE0_NS }
49916 #else
49917   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base address */
49918   #define IERC_F0_PCI_HDR_TYPE0_BASE               (0x600F8000u)
49919   /** Peripheral IERC_F0_PCI_HDR_TYPE0 base pointer */
49920   #define IERC_F0_PCI_HDR_TYPE0                    ((IERC_PCI_Type *)IERC_F0_PCI_HDR_TYPE0_BASE)
49921   /** Array initializer of IERC_PCI peripheral base addresses */
49922   #define IERC_PCI_BASE_ADDRS                      { IERC_F0_PCI_HDR_TYPE0_BASE }
49923   /** Array initializer of IERC_PCI peripheral base pointers */
49924   #define IERC_PCI_BASE_PTRS                       { IERC_F0_PCI_HDR_TYPE0 }
49925 #endif
49926 
49927 /*!
49928  * @}
49929  */ /* end of group IERC_PCI_Peripheral_Access_Layer */
49930 
49931 
49932 /* ----------------------------------------------------------------------------
49933    -- IOMUXC Peripheral Access Layer
49934    ---------------------------------------------------------------------------- */
49935 
49936 /*!
49937  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
49938  * @{
49939  */
49940 
49941 /** IOMUXC - Register Layout Typedef */
49942 typedef struct {
49943        uint8_t RESERVED_0[16];
49944   __IO uint32_t SW_MUX_CTL_PAD[146];               /**< SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_B2_13 SW MUX Control Register, array offset: 0x10, array step: 0x4 */
49945   __IO uint32_t SW_PAD_CTL_PAD[146];               /**< SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_B2_13 SW PAD Control Register, array offset: 0x258, array step: 0x4 */
49946   __IO uint32_t SELECT_INPUT[355];                 /**< CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..XSPI_SLV_IPP_IND_SCK_SELECT_INPUT DAISY Register, array offset: 0x4A0, array step: 0x4, valid indices: [0-143, 190-266, 269-282, 285-315, 344-354] */
49947 } IOMUXC_Type;
49948 
49949 /* ----------------------------------------------------------------------------
49950    -- IOMUXC Register Masks
49951    ---------------------------------------------------------------------------- */
49952 
49953 /*!
49954  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
49955  * @{
49956  */
49957 
49958 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_B2_13 SW MUX Control Register */
49959 /*! @{ */
49960 
49961 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0xFU)  /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
49962 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
49963 /*! MUX_MODE - MUX Mode Select Field.
49964  *  0b1010..Select mux mode: ALT10 mux port: XSPI_SLV_DATA00 of instance: xspi_slv
49965  *  0b1011..Select mux mode: ALT11 mux port: NETC_PINMUX_ETH2_RXD00 of instance: netc_pinmux
49966  *  0b1100..Select mux mode: ALT12 mux port: ECAT_RX_DATA0_1 of instance: ecat
49967  *  0b0000..Select mux mode: ALT0 mux port: MIC_BITSTREAM00 of instance: mic
49968  *  0b0001..Select mux mode: ALT1 mux port: SINC2_EMCLK03 of instance: sinc2
49969  *  0b0010..Select mux mode: ALT2 mux port: CAN3_TX of instance: can3
49970  *  0b0011..Select mux mode: ALT3 mux port: LPUART8_CTS_B of instance: lpuart8
49971  *  0b0100..Select mux mode: ALT4 mux port: LPUART6_TX of instance: lpuart6
49972  *  0b0101..Select mux mode: ALT5 mux port: GPIO6_IO24 of instance: gpio6
49973  *  0b0110..Select mux mode: ALT6 mux port: LPI2C4_SCL of instance: lpi2c4
49974  *  0b0111..Select mux mode: ALT7 mux port: FLEXSPI1_BUS2BIT_A_DATA00 of instance: flexspi1_bus2bit
49975  *  0b1000..Select mux mode: ALT8 mux port: TPM4_CH00 of instance: tpm4
49976  *  0b1001..Select mux mode: ALT9 mux port: LPSPI4_SCK of instance: lpspi4
49977  */
49978 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)  /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
49979 
49980 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
49981 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
49982 /*! SION - Software Input On Field.
49983  *  0b1..Force input path of pad GPIO_SD_B2_12_DUMMY
49984  *  0b0..Input Path is determined by functionality
49985  */
49986 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
49987 /*! @} */
49988 
49989 /* The count of IOMUXC_SW_MUX_CTL_PAD */
49990 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (146U)
49991 
49992 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_B2_13 SW PAD Control Register */
49993 /*! @{ */
49994 
49995 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
49996 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
49997 /*! SRE - Slew Rate Field
49998  *  0b0..Fast Slew Rate
49999  *  0b1..Slow Slew Rate
50000  */
50001 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
50002 
50003 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x2U)
50004 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (1U)
50005 /*! DSE - Drive Strength Field
50006  *  0b0..normal driver
50007  *  0b1..high driver
50008  */
50009 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
50010 
50011 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK          (0x2U)
50012 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT         (1U)
50013 /*! PDRV - PDRV Field
50014  *  0b0..high driver
50015  *  0b1..normal driver
50016  */
50017 #define IOMUXC_SW_PAD_CTL_PAD_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
50018 
50019 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x4U)
50020 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (2U)
50021 /*! PUE - Pull / Keep Select Field
50022  *  0b0..Pull Disable, Highz
50023  *  0b1..Pull Enable
50024  */
50025 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
50026 
50027 #define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK          (0xCU)
50028 #define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT         (2U)
50029 /*! PULL - Pull Down Pull Up Field
50030  *  0b00..Forbidden
50031  *  0b01..PU
50032  *  0b10..PD
50033  *  0b11..No Pull
50034  */
50035 #define IOMUXC_SW_PAD_CTL_PAD_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
50036 
50037 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0x8U)
50038 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (3U)
50039 /*! PUS - Pull Up / Down Config. Field
50040  *  0b0..Weak pull down
50041  *  0b1..Weak pull up
50042  */
50043 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
50044 
50045 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x10U)
50046 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (4U)
50047 /*! ODE - Open Drain Field
50048  *  0b0..Disabled
50049  *  0b1..Enabled
50050  */
50051 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
50052 
50053 #define IOMUXC_SW_PAD_CTL_PAD_IBE_OFF_MASK       (0x80U)
50054 #define IOMUXC_SW_PAD_CTL_PAD_IBE_OFF_SHIFT      (7U)
50055 /*! IBE_OFF - Force Input Buffer Enable (IBE) off Field
50056  *  0b0..Disabled
50057  *  0b1..Enabled
50058  */
50059 #define IOMUXC_SW_PAD_CTL_PAD_IBE_OFF(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_IBE_OFF_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_IBE_OFF_MASK)
50060 
50061 #define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK           (0xF000000U)
50062 #define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT          (24U)
50063 /*! DWP - Domain write protection */
50064 #define IOMUXC_SW_PAD_CTL_PAD_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
50065 
50066 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK      (0xF0000000U)
50067 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT     (28U)
50068 /*! DWP_LOCK - Domain write protection lock */
50069 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
50070 /*! @} */
50071 
50072 /* The count of IOMUXC_SW_PAD_CTL_PAD */
50073 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (146U)
50074 
50075 /*! @name SELECT_INPUT - CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..XSPI_SLV_IPP_IND_SCK_SELECT_INPUT DAISY Register */
50076 /*! @{ */
50077 
50078 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x7U)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
50079 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
50080 /*! DAISY - Selecting Pads Involved in Daisy Chain.
50081  *  0b000..Selecting Pad: GPIO_EMC_B1_19 for Mode: ALT10
50082  *  0b001..Selecting Pad: GPIO_EMC_B1_41 for Mode: ALT1
50083  *  0b010..Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT3
50084  *  0b011..Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT4
50085  *  0b100..Selecting Pad: GPIO_AD_31 for Mode: ALT7
50086  *  0b101..Selecting Pad: GPIO_SD_B2_10 for Mode: ALT10
50087  *  0b110..Selecting Pad: GPIO_B1_12 for Mode: ALT1
50088  *  0b111..Selecting Pad: GPIO_B2_02 for Mode: ALT3
50089  */
50090 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
50091 /*! @} */
50092 
50093 /* The count of IOMUXC_SELECT_INPUT */
50094 #define IOMUXC_SELECT_INPUT_COUNT                (355U)
50095 
50096 
50097 /*!
50098  * @}
50099  */ /* end of group IOMUXC_Register_Masks */
50100 
50101 
50102 /* IOMUXC - Peripheral instance base addresses */
50103 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
50104   /** Peripheral IOMUXC base address */
50105   #define IOMUXC_BASE                              (0x52A10000u)
50106   /** Peripheral IOMUXC base address */
50107   #define IOMUXC_BASE_NS                           (0x42A10000u)
50108   /** Peripheral IOMUXC base pointer */
50109   #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
50110   /** Peripheral IOMUXC base pointer */
50111   #define IOMUXC_NS                                ((IOMUXC_Type *)IOMUXC_BASE_NS)
50112   /** Array initializer of IOMUXC peripheral base addresses */
50113   #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
50114   /** Array initializer of IOMUXC peripheral base pointers */
50115   #define IOMUXC_BASE_PTRS                         { IOMUXC }
50116   /** Array initializer of IOMUXC peripheral base addresses */
50117   #define IOMUXC_BASE_ADDRS_NS                     { IOMUXC_BASE_NS }
50118   /** Array initializer of IOMUXC peripheral base pointers */
50119   #define IOMUXC_BASE_PTRS_NS                      { IOMUXC_NS }
50120 #else
50121   /** Peripheral IOMUXC base address */
50122   #define IOMUXC_BASE                              (0x42A10000u)
50123   /** Peripheral IOMUXC base pointer */
50124   #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
50125   /** Array initializer of IOMUXC peripheral base addresses */
50126   #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
50127   /** Array initializer of IOMUXC peripheral base pointers */
50128   #define IOMUXC_BASE_PTRS                         { IOMUXC }
50129 #endif
50130 
50131 /*!
50132  * @}
50133  */ /* end of group IOMUXC_Peripheral_Access_Layer */
50134 
50135 
50136 /* ----------------------------------------------------------------------------
50137    -- IOMUXC_AON Peripheral Access Layer
50138    ---------------------------------------------------------------------------- */
50139 
50140 /*!
50141  * @addtogroup IOMUXC_AON_Peripheral_Access_Layer IOMUXC_AON Peripheral Access Layer
50142  * @{
50143  */
50144 
50145 /** IOMUXC_AON - Register Layout Typedef */
50146 typedef struct {
50147   __IO uint32_t SW_MUX_CTL_PAD[29];                /**< SW_MUX_CTL_PAD_GPIO_AON_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_AON_28_DUMMY SW MUX Control Register, array offset: 0x0, array step: 0x4 */
50148   __IO uint32_t SW_PAD_CTL_PAD[29];                /**< SW_PAD_CTL_PAD_GPIO_AON_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_AON_28_DUMMY SW PAD Control Register, array offset: 0x74, array step: 0x4 */
50149   __IO uint32_t SELECT_INPUT[39];                  /**< I3C1_PIN_SCL_IN_SELECT_INPUT DAISY Register..SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0xE8, array step: 0x4 */
50150 } IOMUXC_AON_Type;
50151 
50152 /* ----------------------------------------------------------------------------
50153    -- IOMUXC_AON Register Masks
50154    ---------------------------------------------------------------------------- */
50155 
50156 /*!
50157  * @addtogroup IOMUXC_AON_Register_Masks IOMUXC_AON Register Masks
50158  * @{
50159  */
50160 
50161 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_AON_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_AON_28_DUMMY SW MUX Control Register */
50162 /*! @{ */
50163 
50164 #define IOMUXC_AON_SW_MUX_CTL_PAD_MUX_MODE_MASK  (0xFU)  /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
50165 #define IOMUXC_AON_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
50166 /*! MUX_MODE - MUX Mode Select Field.
50167  *  0b0000..Select mux mode: ALT0 mux port: SRC_BOOT_MODE02 of instance: src
50168  *  0b0001..Select mux mode: ALT1 mux port: CAN3_TX of instance: can3
50169  *  0b0010..Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: lpspi2
50170  *  0b0011..Select mux mode: ALT3 mux port: LPSPI2_SDO of instance: lpspi2
50171  *  0b0100..Select mux mode: ALT4 mux port: LPTMR1_ALT3 of instance: lptmr1
50172  *  0b0101..Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1
50173  *  0b0110..Select mux mode: ALT6 mux port: LPUART2_RTS_B of instance: lpuart2
50174  *  0b1000..Select mux mode: ALT8 mux port: TPM1_CH01 of instance: tpm1
50175  *  0b1001..Reserved
50176  *  0b1010..Reserved
50177  *  0b1011..Reserved
50178  *  0b1100..Select mux mode: ALT12 mux port: ECAT_CLK_ECAT_CLK25 of instance: ecat
50179  */
50180 #define IOMUXC_AON_SW_MUX_CTL_PAD_MUX_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_AON_SW_MUX_CTL_PAD_MUX_MODE_MASK)  /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
50181 
50182 #define IOMUXC_AON_SW_MUX_CTL_PAD_SION_MASK      (0x10U)
50183 #define IOMUXC_AON_SW_MUX_CTL_PAD_SION_SHIFT     (4U)
50184 /*! SION - Software Input On Field.
50185  *  0b1..Force input path of pad GPIO_AON_28_DUMMY
50186  *  0b0..Input Path is determined by functionality
50187  */
50188 #define IOMUXC_AON_SW_MUX_CTL_PAD_SION(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_AON_SW_MUX_CTL_PAD_SION_MASK)
50189 /*! @} */
50190 
50191 /* The count of IOMUXC_AON_SW_MUX_CTL_PAD */
50192 #define IOMUXC_AON_SW_MUX_CTL_PAD_COUNT          (29U)
50193 
50194 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_AON_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_AON_28_DUMMY SW PAD Control Register */
50195 /*! @{ */
50196 
50197 #define IOMUXC_AON_SW_PAD_CTL_PAD_SRE_MASK       (0x1U)
50198 #define IOMUXC_AON_SW_PAD_CTL_PAD_SRE_SHIFT      (0U)
50199 /*! SRE - Slew Rate Field
50200  *  0b0..Fast Slew Rate
50201  *  0b1..Slow Slew Rate
50202  */
50203 #define IOMUXC_AON_SW_PAD_CTL_PAD_SRE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_SRE_MASK)
50204 
50205 #define IOMUXC_AON_SW_PAD_CTL_PAD_DSE_MASK       (0x2U)
50206 #define IOMUXC_AON_SW_PAD_CTL_PAD_DSE_SHIFT      (1U)
50207 /*! DSE - Drive Strength Field
50208  *  0b0..normal driver
50209  *  0b1..high driver
50210  */
50211 #define IOMUXC_AON_SW_PAD_CTL_PAD_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_DSE_MASK)
50212 
50213 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUE_MASK       (0x4U)
50214 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUE_SHIFT      (2U)
50215 /*! PUE - Pull / Keep Select Field
50216  *  0b0..Pull Disable, Highz
50217  *  0b1..Pull Enable
50218  */
50219 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_PUE_MASK)
50220 
50221 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUS_MASK       (0x8U)
50222 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUS_SHIFT      (3U)
50223 /*! PUS - Pull Up / Down Config. Field
50224  *  0b0..Weak pull down
50225  *  0b1..Weak pull up
50226  */
50227 #define IOMUXC_AON_SW_PAD_CTL_PAD_PUS(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_PUS_MASK)
50228 
50229 #define IOMUXC_AON_SW_PAD_CTL_PAD_ODE_MASK       (0x10U)
50230 #define IOMUXC_AON_SW_PAD_CTL_PAD_ODE_SHIFT      (4U)
50231 /*! ODE - Open Drain Field
50232  *  0b0..Disabled
50233  *  0b1..Enabled
50234  */
50235 #define IOMUXC_AON_SW_PAD_CTL_PAD_ODE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_ODE_MASK)
50236 
50237 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP_MASK       (0xF000000U)
50238 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP_SHIFT      (24U)
50239 /*! DWP - Domain write protection */
50240 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_DWP_MASK)
50241 
50242 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP_LOCK_MASK  (0xF0000000U)
50243 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (28U)
50244 /*! DWP_LOCK - Domain write protection lock */
50245 #define IOMUXC_AON_SW_PAD_CTL_PAD_DWP_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_AON_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
50246 /*! @} */
50247 
50248 /* The count of IOMUXC_AON_SW_PAD_CTL_PAD */
50249 #define IOMUXC_AON_SW_PAD_CTL_PAD_COUNT          (29U)
50250 
50251 /*! @name SELECT_INPUT - I3C1_PIN_SCL_IN_SELECT_INPUT DAISY Register..SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */
50252 /*! @{ */
50253 
50254 #define IOMUXC_AON_SELECT_INPUT_DAISY_MASK       (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
50255 #define IOMUXC_AON_SELECT_INPUT_DAISY_SHIFT      (0U)
50256 /*! DAISY - Selecting Pads Involved in Daisy Chain.
50257  *  0b00..Selecting Pad: GPIO_AON_06 for Mode: ALT3
50258  *  0b01..Selecting Pad: GPIO_AON_08 for Mode: ALT6
50259  *  0b10..Selecting Pad: GPIO_AON_20 for Mode: ALT2
50260  *  0b11..Selecting Pad: GPIO_AON_24 for Mode: ALT1
50261  */
50262 #define IOMUXC_AON_SELECT_INPUT_DAISY(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_AON_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_AON_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
50263 /*! @} */
50264 
50265 /* The count of IOMUXC_AON_SELECT_INPUT */
50266 #define IOMUXC_AON_SELECT_INPUT_COUNT            (39U)
50267 
50268 
50269 /*!
50270  * @}
50271  */ /* end of group IOMUXC_AON_Register_Masks */
50272 
50273 
50274 /* IOMUXC_AON - Peripheral instance base addresses */
50275 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
50276   /** Peripheral IOMUXC_AON base address */
50277   #define IOMUXC_AON_BASE                          (0x543C0000u)
50278   /** Peripheral IOMUXC_AON base address */
50279   #define IOMUXC_AON_BASE_NS                       (0x443C0000u)
50280   /** Peripheral IOMUXC_AON base pointer */
50281   #define IOMUXC_AON                               ((IOMUXC_AON_Type *)IOMUXC_AON_BASE)
50282   /** Peripheral IOMUXC_AON base pointer */
50283   #define IOMUXC_AON_NS                            ((IOMUXC_AON_Type *)IOMUXC_AON_BASE_NS)
50284   /** Array initializer of IOMUXC_AON peripheral base addresses */
50285   #define IOMUXC_AON_BASE_ADDRS                    { IOMUXC_AON_BASE }
50286   /** Array initializer of IOMUXC_AON peripheral base pointers */
50287   #define IOMUXC_AON_BASE_PTRS                     { IOMUXC_AON }
50288   /** Array initializer of IOMUXC_AON peripheral base addresses */
50289   #define IOMUXC_AON_BASE_ADDRS_NS                 { IOMUXC_AON_BASE_NS }
50290   /** Array initializer of IOMUXC_AON peripheral base pointers */
50291   #define IOMUXC_AON_BASE_PTRS_NS                  { IOMUXC_AON_NS }
50292 #else
50293   /** Peripheral IOMUXC_AON base address */
50294   #define IOMUXC_AON_BASE                          (0x443C0000u)
50295   /** Peripheral IOMUXC_AON base pointer */
50296   #define IOMUXC_AON                               ((IOMUXC_AON_Type *)IOMUXC_AON_BASE)
50297   /** Array initializer of IOMUXC_AON peripheral base addresses */
50298   #define IOMUXC_AON_BASE_ADDRS                    { IOMUXC_AON_BASE }
50299   /** Array initializer of IOMUXC_AON peripheral base pointers */
50300   #define IOMUXC_AON_BASE_PTRS                     { IOMUXC_AON }
50301 #endif
50302 
50303 /*!
50304  * @}
50305  */ /* end of group IOMUXC_AON_Peripheral_Access_Layer */
50306 
50307 
50308 /* ----------------------------------------------------------------------------
50309    -- KPP Peripheral Access Layer
50310    ---------------------------------------------------------------------------- */
50311 
50312 /*!
50313  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
50314  * @{
50315  */
50316 
50317 /** KPP - Register Layout Typedef */
50318 typedef struct {
50319   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
50320   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
50321   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
50322   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
50323 } KPP_Type;
50324 
50325 /* ----------------------------------------------------------------------------
50326    -- KPP Register Masks
50327    ---------------------------------------------------------------------------- */
50328 
50329 /*!
50330  * @addtogroup KPP_Register_Masks KPP Register Masks
50331  * @{
50332  */
50333 
50334 /*! @name KPCR - Keypad Control Register */
50335 /*! @{ */
50336 
50337 #define KPP_KPCR_KRE_MASK                        (0xFFU)
50338 #define KPP_KPCR_KRE_SHIFT                       (0U)
50339 /*! KRE - KRE
50340  *  0b00000000..Row is not included in the keypad key press detect.
50341  *  0b00000001..Row is included in the keypad key press detect.
50342  */
50343 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
50344 
50345 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
50346 #define KPP_KPCR_KCO_SHIFT                       (8U)
50347 /*! KCO - KCO
50348  *  0b00000000..Column strobe output is totem pole drive.
50349  *  0b00000001..Column strobe output is open drain.
50350  */
50351 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
50352 /*! @} */
50353 
50354 /*! @name KPSR - Keypad Status Register */
50355 /*! @{ */
50356 
50357 #define KPP_KPSR_KPKD_MASK                       (0x1U)
50358 #define KPP_KPSR_KPKD_SHIFT                      (0U)
50359 /*! KPKD - KPKD
50360  *  0b0..No key presses detected
50361  *  0b1..A key has been depressed
50362  */
50363 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
50364 
50365 #define KPP_KPSR_KPKR_MASK                       (0x2U)
50366 #define KPP_KPSR_KPKR_SHIFT                      (1U)
50367 /*! KPKR - KPKR
50368  *  0b0..No key release detected
50369  *  0b1..All keys have been released
50370  */
50371 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
50372 
50373 #define KPP_KPSR_KDSC_MASK                       (0x4U)
50374 #define KPP_KPSR_KDSC_SHIFT                      (2U)
50375 /*! KDSC - KDSC
50376  *  0b0..No effect
50377  *  0b1..Set bits that clear the keypad depress synchronizer chain
50378  */
50379 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
50380 
50381 #define KPP_KPSR_KRSS_MASK                       (0x8U)
50382 #define KPP_KPSR_KRSS_SHIFT                      (3U)
50383 /*! KRSS - KRSS
50384  *  0b0..No effect
50385  *  0b1..Set bits which sets keypad release synchronizer chain
50386  */
50387 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
50388 
50389 #define KPP_KPSR_KDIE_MASK                       (0x100U)
50390 #define KPP_KPSR_KDIE_SHIFT                      (8U)
50391 /*! KDIE - KDIE
50392  *  0b0..No interrupt request is generated when KPKD is set.
50393  *  0b1..An interrupt request is generated when KPKD is set.
50394  */
50395 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
50396 
50397 #define KPP_KPSR_KRIE_MASK                       (0x200U)
50398 #define KPP_KPSR_KRIE_SHIFT                      (9U)
50399 /*! KRIE - KRIE
50400  *  0b0..No interrupt request is generated when KPKR is set.
50401  *  0b1..An interrupt request is generated when KPKR is set.
50402  */
50403 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
50404 /*! @} */
50405 
50406 /*! @name KDDR - Keypad Data Direction Register */
50407 /*! @{ */
50408 
50409 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
50410 #define KPP_KDDR_KRDD_SHIFT                      (0U)
50411 /*! KRDD - KRDD
50412  *  0b00000000..ROWn pin configured as an input.
50413  *  0b00000001..ROWn pin configured as an output.
50414  */
50415 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
50416 
50417 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
50418 #define KPP_KDDR_KCDD_SHIFT                      (8U)
50419 /*! KCDD - KCDD
50420  *  0b00000000..COLn pin is configured as an input.
50421  *  0b00000001..COLn pin is configured as an output.
50422  */
50423 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
50424 /*! @} */
50425 
50426 /*! @name KPDR - Keypad Data Register */
50427 /*! @{ */
50428 
50429 #define KPP_KPDR_KRD_MASK                        (0xFFU)
50430 #define KPP_KPDR_KRD_SHIFT                       (0U)
50431 /*! KRD - KRD */
50432 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
50433 
50434 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
50435 #define KPP_KPDR_KCD_SHIFT                       (8U)
50436 /*! KCD - KCD */
50437 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
50438 /*! @} */
50439 
50440 
50441 /*!
50442  * @}
50443  */ /* end of group KPP_Register_Masks */
50444 
50445 
50446 /* KPP - Peripheral instance base addresses */
50447 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
50448   /** Peripheral KPP base address */
50449   #define KPP_BASE                                 (0x52A00000u)
50450   /** Peripheral KPP base address */
50451   #define KPP_BASE_NS                              (0x42A00000u)
50452   /** Peripheral KPP base pointer */
50453   #define KPP                                      ((KPP_Type *)KPP_BASE)
50454   /** Peripheral KPP base pointer */
50455   #define KPP_NS                                   ((KPP_Type *)KPP_BASE_NS)
50456   /** Array initializer of KPP peripheral base addresses */
50457   #define KPP_BASE_ADDRS                           { KPP_BASE }
50458   /** Array initializer of KPP peripheral base pointers */
50459   #define KPP_BASE_PTRS                            { KPP }
50460   /** Array initializer of KPP peripheral base addresses */
50461   #define KPP_BASE_ADDRS_NS                        { KPP_BASE_NS }
50462   /** Array initializer of KPP peripheral base pointers */
50463   #define KPP_BASE_PTRS_NS                         { KPP_NS }
50464 #else
50465   /** Peripheral KPP base address */
50466   #define KPP_BASE                                 (0x42A00000u)
50467   /** Peripheral KPP base pointer */
50468   #define KPP                                      ((KPP_Type *)KPP_BASE)
50469   /** Array initializer of KPP peripheral base addresses */
50470   #define KPP_BASE_ADDRS                           { KPP_BASE }
50471   /** Array initializer of KPP peripheral base pointers */
50472   #define KPP_BASE_PTRS                            { KPP }
50473 #endif
50474 /** Interrupt vectors for the KPP peripheral type */
50475 #define KPP_IRQS                                 { KPP_IRQn }
50476 
50477 /*!
50478  * @}
50479  */ /* end of group KPP_Peripheral_Access_Layer */
50480 
50481 
50482 /* ----------------------------------------------------------------------------
50483    -- LPI2C Peripheral Access Layer
50484    ---------------------------------------------------------------------------- */
50485 
50486 /*!
50487  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
50488  * @{
50489  */
50490 
50491 /** LPI2C - Register Layout Typedef */
50492 typedef struct {
50493   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
50494   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
50495        uint8_t RESERVED_0[8];
50496   __IO uint32_t MCR;                               /**< Controller Control, offset: 0x10 */
50497   __IO uint32_t MSR;                               /**< Controller Status, offset: 0x14 */
50498   __IO uint32_t MIER;                              /**< Controller Interrupt Enable, offset: 0x18 */
50499   __IO uint32_t MDER;                              /**< Controller DMA Enable, offset: 0x1C */
50500   __IO uint32_t MCFGR0;                            /**< Controller Configuration 0, offset: 0x20 */
50501   __IO uint32_t MCFGR1;                            /**< Controller Configuration 1, offset: 0x24 */
50502   __IO uint32_t MCFGR2;                            /**< Controller Configuration 2, offset: 0x28 */
50503   __IO uint32_t MCFGR3;                            /**< Controller Configuration 3, offset: 0x2C */
50504        uint8_t RESERVED_1[16];
50505   __IO uint32_t MDMR;                              /**< Controller Data Match, offset: 0x40 */
50506        uint8_t RESERVED_2[4];
50507   __IO uint32_t MCCR0;                             /**< Controller Clock Configuration 0, offset: 0x48 */
50508        uint8_t RESERVED_3[4];
50509   __IO uint32_t MCCR1;                             /**< Controller Clock Configuration 1, offset: 0x50 */
50510        uint8_t RESERVED_4[4];
50511   __IO uint32_t MFCR;                              /**< Controller FIFO Control, offset: 0x58 */
50512   __I  uint32_t MFSR;                              /**< Controller FIFO Status, offset: 0x5C */
50513   __O  uint32_t MTDR;                              /**< Controller Transmit Data, offset: 0x60 */
50514        uint8_t RESERVED_5[12];
50515   __I  uint32_t MRDR;                              /**< Controller Receive Data, offset: 0x70 */
50516        uint8_t RESERVED_6[4];
50517   __I  uint32_t MRDROR;                            /**< Controller Receive Data Read Only, offset: 0x78 */
50518        uint8_t RESERVED_7[148];
50519   __IO uint32_t SCR;                               /**< Target Control, offset: 0x110 */
50520   __IO uint32_t SSR;                               /**< Target Status, offset: 0x114 */
50521   __IO uint32_t SIER;                              /**< Target Interrupt Enable, offset: 0x118 */
50522   __IO uint32_t SDER;                              /**< Target DMA Enable, offset: 0x11C */
50523   __IO uint32_t SCFGR0;                            /**< Target Configuration 0, offset: 0x120 */
50524   __IO uint32_t SCFGR1;                            /**< Target Configuration 1, offset: 0x124 */
50525   __IO uint32_t SCFGR2;                            /**< Target Configuration 2, offset: 0x128 */
50526        uint8_t RESERVED_8[20];
50527   __IO uint32_t SAMR;                              /**< Target Address Match, offset: 0x140 */
50528        uint8_t RESERVED_9[12];
50529   __I  uint32_t SASR;                              /**< Target Address Status, offset: 0x150 */
50530   __IO uint32_t STAR;                              /**< Target Transmit ACK, offset: 0x154 */
50531        uint8_t RESERVED_10[8];
50532   __O  uint32_t STDR;                              /**< Target Transmit Data, offset: 0x160 */
50533        uint8_t RESERVED_11[12];
50534   __I  uint32_t SRDR;                              /**< Target Receive Data, offset: 0x170 */
50535        uint8_t RESERVED_12[4];
50536   __I  uint32_t SRDROR;                            /**< Target Receive Data Read Only, offset: 0x178 */
50537        uint8_t RESERVED_13[132];
50538   __O  uint32_t MTCBR[128];                        /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */
50539   __O  uint32_t MTDBR[256];                        /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
50540 } LPI2C_Type;
50541 
50542 /* ----------------------------------------------------------------------------
50543    -- LPI2C Register Masks
50544    ---------------------------------------------------------------------------- */
50545 
50546 /*!
50547  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
50548  * @{
50549  */
50550 
50551 /*! @name VERID - Version ID */
50552 /*! @{ */
50553 
50554 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
50555 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
50556 /*! FEATURE - Feature Specification Number
50557  *  0b0000000000000010..Controller only, with standard feature set
50558  *  0b0000000000000011..Controller and target, with standard feature set
50559  */
50560 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
50561 
50562 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
50563 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
50564 /*! MINOR - Minor Version Number */
50565 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
50566 
50567 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
50568 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
50569 /*! MAJOR - Major Version Number */
50570 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
50571 /*! @} */
50572 
50573 /*! @name PARAM - Parameter */
50574 /*! @{ */
50575 
50576 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
50577 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
50578 /*! MTXFIFO - Controller Transmit FIFO Size */
50579 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
50580 
50581 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
50582 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
50583 /*! MRXFIFO - Controller Receive FIFO Size */
50584 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
50585 /*! @} */
50586 
50587 /*! @name MCR - Controller Control */
50588 /*! @{ */
50589 
50590 #define LPI2C_MCR_MEN_MASK                       (0x1U)
50591 #define LPI2C_MCR_MEN_SHIFT                      (0U)
50592 /*! MEN - Controller Enable
50593  *  0b0..Disable
50594  *  0b1..Enable
50595  */
50596 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
50597 
50598 #define LPI2C_MCR_RST_MASK                       (0x2U)
50599 #define LPI2C_MCR_RST_SHIFT                      (1U)
50600 /*! RST - Software Reset
50601  *  0b0..No effect
50602  *  0b1..Reset
50603  */
50604 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
50605 
50606 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
50607 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
50608 /*! DOZEN - Doze Mode Enable
50609  *  0b0..Enable
50610  *  0b1..Disable
50611  */
50612 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
50613 
50614 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
50615 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
50616 /*! DBGEN - Debug Enable
50617  *  0b0..Disable
50618  *  0b1..Enable
50619  */
50620 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
50621 
50622 #define LPI2C_MCR_RTF_MASK                       (0x100U)
50623 #define LPI2C_MCR_RTF_SHIFT                      (8U)
50624 /*! RTF - Reset Transmit FIFO
50625  *  0b0..No effect
50626  *  0b1..Reset transmit FIFO
50627  */
50628 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
50629 
50630 #define LPI2C_MCR_RRF_MASK                       (0x200U)
50631 #define LPI2C_MCR_RRF_SHIFT                      (9U)
50632 /*! RRF - Reset Receive FIFO
50633  *  0b0..No effect
50634  *  0b1..Reset receive FIFO
50635  */
50636 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
50637 /*! @} */
50638 
50639 /*! @name MSR - Controller Status */
50640 /*! @{ */
50641 
50642 #define LPI2C_MSR_TDF_MASK                       (0x1U)
50643 #define LPI2C_MSR_TDF_SHIFT                      (0U)
50644 /*! TDF - Transmit Data Flag
50645  *  0b0..Transmit data not requested
50646  *  0b1..Transmit data requested
50647  */
50648 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
50649 
50650 #define LPI2C_MSR_RDF_MASK                       (0x2U)
50651 #define LPI2C_MSR_RDF_SHIFT                      (1U)
50652 /*! RDF - Receive Data Flag
50653  *  0b0..Receive data not ready
50654  *  0b1..Receive data ready
50655  */
50656 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
50657 
50658 #define LPI2C_MSR_EPF_MASK                       (0x100U)
50659 #define LPI2C_MSR_EPF_SHIFT                      (8U)
50660 /*! EPF - End Packet Flag
50661  *  0b0..No Stop or repeated Start generated
50662  *  0b1..Stop or repeated Start generated
50663  *  0b0..No effect
50664  *  0b1..Clear the flag
50665  */
50666 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
50667 
50668 #define LPI2C_MSR_SDF_MASK                       (0x200U)
50669 #define LPI2C_MSR_SDF_SHIFT                      (9U)
50670 /*! SDF - Stop Detect Flag
50671  *  0b0..No Stop condition generated
50672  *  0b1..Stop condition generated
50673  *  0b0..No effect
50674  *  0b1..Clear the flag
50675  */
50676 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
50677 
50678 #define LPI2C_MSR_NDF_MASK                       (0x400U)
50679 #define LPI2C_MSR_NDF_SHIFT                      (10U)
50680 /*! NDF - NACK Detect Flag
50681  *  0b0..No unexpected NACK detected
50682  *  0b1..Unexpected NACK detected
50683  *  0b0..No effect
50684  *  0b1..Clear the flag
50685  */
50686 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
50687 
50688 #define LPI2C_MSR_ALF_MASK                       (0x800U)
50689 #define LPI2C_MSR_ALF_SHIFT                      (11U)
50690 /*! ALF - Arbitration Lost Flag
50691  *  0b0..Controller did not lose arbitration
50692  *  0b1..Controller lost arbitration
50693  *  0b0..No effect
50694  *  0b1..Clear the flag
50695  */
50696 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
50697 
50698 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
50699 #define LPI2C_MSR_FEF_SHIFT                      (12U)
50700 /*! FEF - FIFO Error Flag
50701  *  0b0..No FIFO error
50702  *  0b1..FIFO error
50703  *  0b0..No effect
50704  *  0b1..Clear the flag
50705  */
50706 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
50707 
50708 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
50709 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
50710 /*! PLTF - Pin Low Timeout Flag
50711  *  0b0..Pin low timeout did not occur
50712  *  0b1..Pin low timeout occurred
50713  *  0b0..No effect
50714  *  0b1..Clear the flag
50715  */
50716 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
50717 
50718 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
50719 #define LPI2C_MSR_DMF_SHIFT                      (14U)
50720 /*! DMF - Data Match Flag
50721  *  0b0..Matching data not received
50722  *  0b1..Matching data received
50723  *  0b0..No effect
50724  *  0b1..Clear the flag
50725  */
50726 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
50727 
50728 #define LPI2C_MSR_STF_MASK                       (0x8000U)
50729 #define LPI2C_MSR_STF_SHIFT                      (15U)
50730 /*! STF - Start Flag
50731  *  0b0..Start condition not detected
50732  *  0b1..Start condition detected
50733  *  0b0..No effect
50734  *  0b1..Clear the flag
50735  */
50736 #define LPI2C_MSR_STF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)
50737 
50738 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
50739 #define LPI2C_MSR_MBF_SHIFT                      (24U)
50740 /*! MBF - Controller Busy Flag
50741  *  0b0..Idle
50742  *  0b1..Busy
50743  */
50744 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
50745 
50746 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
50747 #define LPI2C_MSR_BBF_SHIFT                      (25U)
50748 /*! BBF - Bus Busy Flag
50749  *  0b0..Idle
50750  *  0b1..Busy
50751  */
50752 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
50753 /*! @} */
50754 
50755 /*! @name MIER - Controller Interrupt Enable */
50756 /*! @{ */
50757 
50758 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
50759 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
50760 /*! TDIE - Transmit Data Interrupt Enable
50761  *  0b0..Disable
50762  *  0b1..Enable
50763  */
50764 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
50765 
50766 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
50767 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
50768 /*! RDIE - Receive Data Interrupt Enable
50769  *  0b0..Disable
50770  *  0b1..Enable
50771  */
50772 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
50773 
50774 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
50775 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
50776 /*! EPIE - End Packet Interrupt Enable
50777  *  0b0..Disable
50778  *  0b1..Enable
50779  */
50780 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
50781 
50782 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
50783 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
50784 /*! SDIE - Stop Detect Interrupt Enable
50785  *  0b0..Disable
50786  *  0b1..Enable
50787  */
50788 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
50789 
50790 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
50791 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
50792 /*! NDIE - NACK Detect Interrupt Enable
50793  *  0b0..Disable
50794  *  0b1..Enable
50795  */
50796 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
50797 
50798 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
50799 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
50800 /*! ALIE - Arbitration Lost Interrupt Enable
50801  *  0b0..Disable
50802  *  0b1..Enable
50803  */
50804 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
50805 
50806 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
50807 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
50808 /*! FEIE - FIFO Error Interrupt Enable
50809  *  0b0..Disable
50810  *  0b1..Enable
50811  */
50812 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
50813 
50814 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
50815 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
50816 /*! PLTIE - Pin Low Timeout Interrupt Enable
50817  *  0b0..Disable
50818  *  0b1..Enable
50819  */
50820 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
50821 
50822 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
50823 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
50824 /*! DMIE - Data Match Interrupt Enable
50825  *  0b0..Disable
50826  *  0b1..Enable
50827  */
50828 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
50829 
50830 #define LPI2C_MIER_STIE_MASK                     (0x8000U)
50831 #define LPI2C_MIER_STIE_SHIFT                    (15U)
50832 /*! STIE - Start Interrupt Enable
50833  *  0b0..Disable
50834  *  0b1..Enable
50835  */
50836 #define LPI2C_MIER_STIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
50837 /*! @} */
50838 
50839 /*! @name MDER - Controller DMA Enable */
50840 /*! @{ */
50841 
50842 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
50843 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
50844 /*! TDDE - Transmit Data DMA Enable
50845  *  0b0..Disable
50846  *  0b1..Enable
50847  */
50848 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
50849 
50850 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
50851 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
50852 /*! RDDE - Receive Data DMA Enable
50853  *  0b0..Disable
50854  *  0b1..Enable
50855  */
50856 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
50857 /*! @} */
50858 
50859 /*! @name MCFGR0 - Controller Configuration 0 */
50860 /*! @{ */
50861 
50862 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
50863 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
50864 /*! HREN - Host Request Enable
50865  *  0b0..Disable
50866  *  0b1..Enable
50867  */
50868 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
50869 
50870 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
50871 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
50872 /*! HRPOL - Host Request Polarity
50873  *  0b0..Active low
50874  *  0b1..Active high
50875  */
50876 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
50877 
50878 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
50879 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
50880 /*! HRSEL - Host Request Select
50881  *  0b0..Host request input is pin HREQ
50882  *  0b1..Host request input is input trigger
50883  */
50884 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
50885 
50886 #define LPI2C_MCFGR0_HRDIR_MASK                  (0x8U)
50887 #define LPI2C_MCFGR0_HRDIR_SHIFT                 (3U)
50888 /*! HRDIR - Host Request Direction
50889  *  0b0..HREQ pin is input (for LPI2C controller)
50890  *  0b1..HREQ pin is output (for LPI2C target)
50891  */
50892 #define LPI2C_MCFGR0_HRDIR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK)
50893 
50894 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
50895 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
50896 /*! CIRFIFO - Circular FIFO Enable
50897  *  0b0..Disable
50898  *  0b1..Enable
50899  */
50900 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
50901 
50902 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
50903 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
50904 /*! RDMO - Receive Data Match Only
50905  *  0b0..Received data is stored in the receive FIFO
50906  *  0b1..Received data is discarded unless MSR[DMF] is set
50907  */
50908 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
50909 
50910 #define LPI2C_MCFGR0_RELAX_MASK                  (0x10000U)
50911 #define LPI2C_MCFGR0_RELAX_SHIFT                 (16U)
50912 /*! RELAX - Relaxed Mode
50913  *  0b0..Normal transfer
50914  *  0b1..Relaxed transfer
50915  */
50916 #define LPI2C_MCFGR0_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)
50917 
50918 #define LPI2C_MCFGR0_ABORT_MASK                  (0x20000U)
50919 #define LPI2C_MCFGR0_ABORT_SHIFT                 (17U)
50920 /*! ABORT - Abort Transfer
50921  *  0b0..Normal transfer
50922  *  0b1..Abort existing transfer and do not start a new one
50923  */
50924 #define LPI2C_MCFGR0_ABORT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
50925 /*! @} */
50926 
50927 /*! @name MCFGR1 - Controller Configuration 1 */
50928 /*! @{ */
50929 
50930 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
50931 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
50932 /*! PRESCALE - Prescaler
50933  *  0b000..Divide by 1
50934  *  0b001..Divide by 2
50935  *  0b010..Divide by 4
50936  *  0b011..Divide by 8
50937  *  0b100..Divide by 16
50938  *  0b101..Divide by 32
50939  *  0b110..Divide by 64
50940  *  0b111..Divide by 128
50941  */
50942 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
50943 
50944 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
50945 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
50946 /*! AUTOSTOP - Automatic Stop Generation
50947  *  0b0..No effect
50948  *  0b1..Stop automatically generated
50949  */
50950 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
50951 
50952 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
50953 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
50954 /*! IGNACK - Ignore NACK
50955  *  0b0..No effect
50956  *  0b1..Treat a received NACK as an ACK
50957  */
50958 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
50959 
50960 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
50961 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
50962 /*! TIMECFG - Timeout Configuration
50963  *  0b0..SCL
50964  *  0b1..SCL or SDA
50965  */
50966 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
50967 
50968 #define LPI2C_MCFGR1_STOPCFG_MASK                (0x800U)
50969 #define LPI2C_MCFGR1_STOPCFG_SHIFT               (11U)
50970 /*! STOPCFG - Stop Configuration
50971  *  0b0..Any Stop condition
50972  *  0b1..Last Stop condition
50973  */
50974 #define LPI2C_MCFGR1_STOPCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)
50975 
50976 #define LPI2C_MCFGR1_STARTCFG_MASK               (0x1000U)
50977 #define LPI2C_MCFGR1_STARTCFG_SHIFT              (12U)
50978 /*! STARTCFG - Start Configuration
50979  *  0b0..Sets when both I2C bus and LPI2C controller are idle
50980  *  0b1..Sets when I2C bus is idle
50981  */
50982 #define LPI2C_MCFGR1_STARTCFG(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)
50983 
50984 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
50985 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
50986 /*! MATCFG - Match Configuration
50987  *  0b000..Match is disabled
50988  *  0b001..Reserved
50989  *  0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1]
50990  *  0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1]
50991  *  0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1)
50992  *  0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1)
50993  *  0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
50994  *  0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
50995  */
50996 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
50997 
50998 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
50999 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
51000 /*! PINCFG - Pin Configuration
51001  *  0b000..Two-pin open drain mode
51002  *  0b001..Two-pin output only mode (Ultra-Fast mode)
51003  *  0b010..Two-pin push-pull mode
51004  *  0b011..Four-pin push-pull mode
51005  *  0b100..Two-pin open-drain mode with separate LPI2C target
51006  *  0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target
51007  *  0b110..Two-pin push-pull mode with separate LPI2C target
51008  *  0b111..Four-pin push-pull mode (inverted outputs)
51009  */
51010 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
51011 /*! @} */
51012 
51013 /*! @name MCFGR2 - Controller Configuration 2 */
51014 /*! @{ */
51015 
51016 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
51017 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
51018 /*! BUSIDLE - Bus Idle Timeout */
51019 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
51020 
51021 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
51022 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
51023 /*! FILTSCL - Glitch Filter SCL */
51024 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
51025 
51026 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
51027 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
51028 /*! FILTSDA - Glitch Filter SDA */
51029 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
51030 /*! @} */
51031 
51032 /*! @name MCFGR3 - Controller Configuration 3 */
51033 /*! @{ */
51034 
51035 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
51036 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
51037 /*! PINLOW - Pin Low Timeout */
51038 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
51039 /*! @} */
51040 
51041 /*! @name MDMR - Controller Data Match */
51042 /*! @{ */
51043 
51044 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
51045 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
51046 /*! MATCH0 - Match 0 Value */
51047 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
51048 
51049 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
51050 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
51051 /*! MATCH1 - Match 1 Value */
51052 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
51053 /*! @} */
51054 
51055 /*! @name MCCR0 - Controller Clock Configuration 0 */
51056 /*! @{ */
51057 
51058 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
51059 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
51060 /*! CLKLO - Clock Low Period */
51061 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
51062 
51063 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
51064 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
51065 /*! CLKHI - Clock High Period */
51066 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
51067 
51068 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
51069 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
51070 /*! SETHOLD - Setup Hold Delay */
51071 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
51072 
51073 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
51074 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
51075 /*! DATAVD - Data Valid Delay */
51076 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
51077 /*! @} */
51078 
51079 /*! @name MCCR1 - Controller Clock Configuration 1 */
51080 /*! @{ */
51081 
51082 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
51083 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
51084 /*! CLKLO - Clock Low Period */
51085 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
51086 
51087 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
51088 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
51089 /*! CLKHI - Clock High Period */
51090 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
51091 
51092 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
51093 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
51094 /*! SETHOLD - Setup Hold Delay */
51095 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
51096 
51097 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
51098 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
51099 /*! DATAVD - Data Valid Delay */
51100 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
51101 /*! @} */
51102 
51103 /*! @name MFCR - Controller FIFO Control */
51104 /*! @{ */
51105 
51106 #define LPI2C_MFCR_TXWATER_MASK                  (0x7U)
51107 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
51108 /*! TXWATER - Transmit FIFO Watermark */
51109 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
51110 
51111 #define LPI2C_MFCR_RXWATER_MASK                  (0x70000U)
51112 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
51113 /*! RXWATER - Receive FIFO Watermark */
51114 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
51115 /*! @} */
51116 
51117 /*! @name MFSR - Controller FIFO Status */
51118 /*! @{ */
51119 
51120 #define LPI2C_MFSR_TXCOUNT_MASK                  (0xFU)
51121 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
51122 /*! TXCOUNT - Transmit FIFO Count */
51123 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
51124 
51125 #define LPI2C_MFSR_RXCOUNT_MASK                  (0xF0000U)
51126 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
51127 /*! RXCOUNT - Receive FIFO Count */
51128 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
51129 /*! @} */
51130 
51131 /*! @name MTDR - Controller Transmit Data */
51132 /*! @{ */
51133 
51134 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
51135 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
51136 /*! DATA - Transmit Data */
51137 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
51138 
51139 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
51140 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
51141 /*! CMD - Command Data
51142  *  0b000..Transmit the value in DATA[7:0]
51143  *  0b001..Receive (DATA[7:0] + 1) bytes
51144  *  0b010..Generate Stop condition on I2C bus
51145  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
51146  *  0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0]
51147  *  0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned)
51148  *  0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode
51149  *  0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
51150  */
51151 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
51152 /*! @} */
51153 
51154 /*! @name MRDR - Controller Receive Data */
51155 /*! @{ */
51156 
51157 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
51158 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
51159 /*! DATA - Receive Data */
51160 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
51161 
51162 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
51163 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
51164 /*! RXEMPTY - Receive Empty
51165  *  0b0..Not empty
51166  *  0b1..Empty
51167  */
51168 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
51169 /*! @} */
51170 
51171 /*! @name MRDROR - Controller Receive Data Read Only */
51172 /*! @{ */
51173 
51174 #define LPI2C_MRDROR_DATA_MASK                   (0xFFU)
51175 #define LPI2C_MRDROR_DATA_SHIFT                  (0U)
51176 /*! DATA - Receive Data */
51177 #define LPI2C_MRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)
51178 
51179 #define LPI2C_MRDROR_RXEMPTY_MASK                (0x4000U)
51180 #define LPI2C_MRDROR_RXEMPTY_SHIFT               (14U)
51181 /*! RXEMPTY - RX Empty
51182  *  0b0..Not empty
51183  *  0b1..Empty
51184  */
51185 #define LPI2C_MRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
51186 /*! @} */
51187 
51188 /*! @name SCR - Target Control */
51189 /*! @{ */
51190 
51191 #define LPI2C_SCR_SEN_MASK                       (0x1U)
51192 #define LPI2C_SCR_SEN_SHIFT                      (0U)
51193 /*! SEN - Target Enable
51194  *  0b0..Disable
51195  *  0b1..Enable
51196  */
51197 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
51198 
51199 #define LPI2C_SCR_RST_MASK                       (0x2U)
51200 #define LPI2C_SCR_RST_SHIFT                      (1U)
51201 /*! RST - Software Reset
51202  *  0b0..Not reset
51203  *  0b1..Reset
51204  */
51205 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
51206 
51207 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
51208 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
51209 /*! FILTEN - Filter Enable
51210  *  0b0..Disable
51211  *  0b1..Enable
51212  */
51213 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
51214 
51215 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
51216 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
51217 /*! FILTDZ - Filter Doze Enable
51218  *  0b0..Enable
51219  *  0b1..Disable
51220  */
51221 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
51222 
51223 #define LPI2C_SCR_RTF_MASK                       (0x100U)
51224 #define LPI2C_SCR_RTF_SHIFT                      (8U)
51225 /*! RTF - Reset Transmit FIFO
51226  *  0b0..No effect
51227  *  0b1..STDR is now empty
51228  */
51229 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
51230 
51231 #define LPI2C_SCR_RRF_MASK                       (0x200U)
51232 #define LPI2C_SCR_RRF_SHIFT                      (9U)
51233 /*! RRF - Reset Receive FIFO
51234  *  0b0..No effect
51235  *  0b1..SRDR is now empty
51236  */
51237 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
51238 /*! @} */
51239 
51240 /*! @name SSR - Target Status */
51241 /*! @{ */
51242 
51243 #define LPI2C_SSR_TDF_MASK                       (0x1U)
51244 #define LPI2C_SSR_TDF_SHIFT                      (0U)
51245 /*! TDF - Transmit Data Flag
51246  *  0b0..Transmit data not requested
51247  *  0b1..Transmit data is requested
51248  */
51249 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
51250 
51251 #define LPI2C_SSR_RDF_MASK                       (0x2U)
51252 #define LPI2C_SSR_RDF_SHIFT                      (1U)
51253 /*! RDF - Receive Data Flag
51254  *  0b0..Not ready
51255  *  0b1..Ready
51256  */
51257 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
51258 
51259 #define LPI2C_SSR_AVF_MASK                       (0x4U)
51260 #define LPI2C_SSR_AVF_SHIFT                      (2U)
51261 /*! AVF - Address Valid Flag
51262  *  0b0..Not valid
51263  *  0b1..Valid
51264  */
51265 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
51266 
51267 #define LPI2C_SSR_TAF_MASK                       (0x8U)
51268 #define LPI2C_SSR_TAF_SHIFT                      (3U)
51269 /*! TAF - Transmit ACK Flag
51270  *  0b0..Not required
51271  *  0b1..Required
51272  */
51273 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
51274 
51275 #define LPI2C_SSR_RSF_MASK                       (0x100U)
51276 #define LPI2C_SSR_RSF_SHIFT                      (8U)
51277 /*! RSF - Repeated Start Flag
51278  *  0b0..No repeated Start detected
51279  *  0b1..Repeated Start detected
51280  *  0b0..No effect
51281  *  0b1..Clear the flag
51282  */
51283 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
51284 
51285 #define LPI2C_SSR_SDF_MASK                       (0x200U)
51286 #define LPI2C_SSR_SDF_SHIFT                      (9U)
51287 /*! SDF - Stop Detect Flag
51288  *  0b0..No Stop detected
51289  *  0b1..Stop detected
51290  *  0b0..No effect
51291  *  0b1..Clear the flag
51292  */
51293 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
51294 
51295 #define LPI2C_SSR_BEF_MASK                       (0x400U)
51296 #define LPI2C_SSR_BEF_SHIFT                      (10U)
51297 /*! BEF - Bit Error Flag
51298  *  0b0..No bit error occurred
51299  *  0b1..Bit error occurred
51300  *  0b0..No effect
51301  *  0b1..Clear the flag
51302  */
51303 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
51304 
51305 #define LPI2C_SSR_FEF_MASK                       (0x800U)
51306 #define LPI2C_SSR_FEF_SHIFT                      (11U)
51307 /*! FEF - FIFO Error Flag
51308  *  0b0..No FIFO error
51309  *  0b1..FIFO error
51310  *  0b0..No effect
51311  *  0b1..Clear the flag
51312  */
51313 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
51314 
51315 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
51316 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
51317 /*! AM0F - Address Match 0 Flag
51318  *  0b0..ADDR0 matching address not received
51319  *  0b1..ADDR0 matching address received
51320  */
51321 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
51322 
51323 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
51324 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
51325 /*! AM1F - Address Match 1 Flag
51326  *  0b0..Matching address not received
51327  *  0b1..Matching address received
51328  */
51329 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
51330 
51331 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
51332 #define LPI2C_SSR_GCF_SHIFT                      (14U)
51333 /*! GCF - General Call Flag
51334  *  0b0..General call address disabled or not detected
51335  *  0b1..General call address detected
51336  */
51337 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
51338 
51339 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
51340 #define LPI2C_SSR_SARF_SHIFT                     (15U)
51341 /*! SARF - SMBus Alert Response Flag
51342  *  0b0..Disabled or not detected
51343  *  0b1..Enabled and detected
51344  */
51345 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
51346 
51347 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
51348 #define LPI2C_SSR_SBF_SHIFT                      (24U)
51349 /*! SBF - Target Busy Flag
51350  *  0b0..Idle
51351  *  0b1..Busy
51352  */
51353 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
51354 
51355 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
51356 #define LPI2C_SSR_BBF_SHIFT                      (25U)
51357 /*! BBF - Bus Busy Flag
51358  *  0b0..Idle
51359  *  0b1..Busy
51360  */
51361 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
51362 /*! @} */
51363 
51364 /*! @name SIER - Target Interrupt Enable */
51365 /*! @{ */
51366 
51367 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
51368 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
51369 /*! TDIE - Transmit Data Interrupt Enable
51370  *  0b0..Disable
51371  *  0b1..Enable
51372  */
51373 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
51374 
51375 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
51376 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
51377 /*! RDIE - Receive Data Interrupt Enable
51378  *  0b0..Disable
51379  *  0b1..Enable
51380  */
51381 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
51382 
51383 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
51384 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
51385 /*! AVIE - Address Valid Interrupt Enable
51386  *  0b0..Disable
51387  *  0b1..Enable
51388  */
51389 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
51390 
51391 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
51392 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
51393 /*! TAIE - Transmit ACK Interrupt Enable
51394  *  0b0..Disable
51395  *  0b1..Enable
51396  */
51397 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
51398 
51399 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
51400 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
51401 /*! RSIE - Repeated Start Interrupt Enable
51402  *  0b0..Disable
51403  *  0b1..Enable
51404  */
51405 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
51406 
51407 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
51408 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
51409 /*! SDIE - Stop Detect Interrupt Enable
51410  *  0b0..Disable
51411  *  0b1..Enable
51412  */
51413 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
51414 
51415 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
51416 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
51417 /*! BEIE - Bit Error Interrupt Enable
51418  *  0b0..Disable
51419  *  0b1..Enable
51420  */
51421 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
51422 
51423 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
51424 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
51425 /*! FEIE - FIFO Error Interrupt Enable
51426  *  0b0..Disable
51427  *  0b1..Enable
51428  */
51429 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
51430 
51431 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
51432 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
51433 /*! AM0IE - Address Match 0 Interrupt Enable
51434  *  0b0..Disable
51435  *  0b1..Enable
51436  */
51437 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
51438 
51439 #define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
51440 #define LPI2C_SIER_AM1IE_SHIFT                   (13U)
51441 /*! AM1IE - Address Match 1 Interrupt Enable
51442  *  0b0..Disable
51443  *  0b1..Enable
51444  */
51445 #define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
51446 
51447 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
51448 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
51449 /*! GCIE - General Call Interrupt Enable
51450  *  0b0..Disabled
51451  *  0b1..Enabled
51452  */
51453 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
51454 
51455 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
51456 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
51457 /*! SARIE - SMBus Alert Response Interrupt Enable
51458  *  0b0..Disable
51459  *  0b1..Enable
51460  */
51461 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
51462 /*! @} */
51463 
51464 /*! @name SDER - Target DMA Enable */
51465 /*! @{ */
51466 
51467 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
51468 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
51469 /*! TDDE - Transmit Data DMA Enable
51470  *  0b0..Disable
51471  *  0b1..Enable
51472  */
51473 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
51474 
51475 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
51476 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
51477 /*! RDDE - Receive Data DMA Enable
51478  *  0b0..Disable DMA request
51479  *  0b1..Enable DMA request
51480  */
51481 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
51482 
51483 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
51484 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
51485 /*! AVDE - Address Valid DMA Enable
51486  *  0b0..Disable
51487  *  0b1..Enable
51488  */
51489 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
51490 
51491 #define LPI2C_SDER_RSDE_MASK                     (0x100U)
51492 #define LPI2C_SDER_RSDE_SHIFT                    (8U)
51493 /*! RSDE - Repeated Start DMA Enable
51494  *  0b0..Disable
51495  *  0b1..Enable
51496  */
51497 #define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
51498 
51499 #define LPI2C_SDER_SDDE_MASK                     (0x200U)
51500 #define LPI2C_SDER_SDDE_SHIFT                    (9U)
51501 /*! SDDE - Stop Detect DMA Enable
51502  *  0b0..Disable
51503  *  0b1..Enable
51504  */
51505 #define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
51506 /*! @} */
51507 
51508 /*! @name SCFGR0 - Target Configuration 0 */
51509 /*! @{ */
51510 
51511 #define LPI2C_SCFGR0_RDREQ_MASK                  (0x1U)
51512 #define LPI2C_SCFGR0_RDREQ_SHIFT                 (0U)
51513 /*! RDREQ - Read Request
51514  *  0b0..Disable
51515  *  0b1..Enable
51516  */
51517 #define LPI2C_SCFGR0_RDREQ(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)
51518 
51519 #define LPI2C_SCFGR0_RDACK_MASK                  (0x2U)
51520 #define LPI2C_SCFGR0_RDACK_SHIFT                 (1U)
51521 /*! RDACK - Read Acknowledge Flag
51522  *  0b0..Read Request not acknowledged
51523  *  0b1..Read Request acknowledged
51524  */
51525 #define LPI2C_SCFGR0_RDACK(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
51526 /*! @} */
51527 
51528 /*! @name SCFGR1 - Target Configuration 1 */
51529 /*! @{ */
51530 
51531 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
51532 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
51533 /*! ADRSTALL - Address SCL Stall
51534  *  0b0..Disable
51535  *  0b1..Enable
51536  */
51537 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
51538 
51539 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
51540 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
51541 /*! RXSTALL - RX SCL Stall
51542  *  0b0..Disable
51543  *  0b1..Enable
51544  */
51545 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
51546 
51547 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
51548 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
51549 /*! TXDSTALL - Transmit Data SCL Stall
51550  *  0b0..Disable
51551  *  0b1..Enable
51552  */
51553 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
51554 
51555 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
51556 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
51557 /*! ACKSTALL - ACK SCL Stall
51558  *  0b0..Disable
51559  *  0b1..Enable
51560  */
51561 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
51562 
51563 #define LPI2C_SCFGR1_RXNACK_MASK                 (0x10U)
51564 #define LPI2C_SCFGR1_RXNACK_SHIFT                (4U)
51565 /*! RXNACK - Receive NACK
51566  *  0b0..ACK or NACK always determined by STAR[TXNACK]
51567  *  0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
51568  */
51569 #define LPI2C_SCFGR1_RXNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)
51570 
51571 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
51572 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
51573 /*! GCEN - General Call Enable
51574  *  0b0..Disable
51575  *  0b1..Enable
51576  */
51577 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
51578 
51579 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
51580 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
51581 /*! SAEN - SMBus Alert Enable
51582  *  0b0..Disable
51583  *  0b1..Enable
51584  */
51585 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
51586 
51587 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
51588 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
51589 /*! TXCFG - Transmit Flag Configuration
51590  *  0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty
51591  *  0b1..MSR[TDF] is set whenever STDR is empty
51592  */
51593 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
51594 
51595 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
51596 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
51597 /*! RXCFG - Receive Data Configuration
51598  *  0b0..Return received data, clear MSR[RDF]
51599  *  0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
51600  */
51601 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
51602 
51603 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
51604 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
51605 /*! IGNACK - Ignore NACK
51606  *  0b0..End transfer on NACK
51607  *  0b1..Do not end transfer on NACK
51608  */
51609 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
51610 
51611 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
51612 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
51613 /*! HSMEN - HS Mode Enable
51614  *  0b0..Disable
51615  *  0b1..Enable
51616  */
51617 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
51618 
51619 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
51620 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
51621 /*! ADDRCFG - Address Configuration
51622  *  0b000..Address match 0 (7-bit)
51623  *  0b001..Address match 0 (10-bit)
51624  *  0b010..Address match 0 (7-bit) or address match 1 (7-bit)
51625  *  0b011..Address match 0 (10-bit) or address match 1 (10-bit)
51626  *  0b100..Address match 0 (7-bit) or address match 1 (10-bit)
51627  *  0b101..Address match 0 (10-bit) or address match 1 (7-bit)
51628  *  0b110..From address match 0 (7-bit) to address match 1 (7-bit)
51629  *  0b111..From address match 0 (10-bit) to address match 1 (10-bit)
51630  */
51631 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
51632 
51633 #define LPI2C_SCFGR1_RXALL_MASK                  (0x1000000U)
51634 #define LPI2C_SCFGR1_RXALL_SHIFT                 (24U)
51635 /*! RXALL - Receive All
51636  *  0b0..Disable
51637  *  0b1..Enable
51638  */
51639 #define LPI2C_SCFGR1_RXALL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)
51640 
51641 #define LPI2C_SCFGR1_RSCFG_MASK                  (0x2000000U)
51642 #define LPI2C_SCFGR1_RSCFG_SHIFT                 (25U)
51643 /*! RSCFG - Repeated Start Configuration
51644  *  0b0..Any repeated Start condition following an address match
51645  *  0b1..Any repeated Start condition
51646  */
51647 #define LPI2C_SCFGR1_RSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)
51648 
51649 #define LPI2C_SCFGR1_SDCFG_MASK                  (0x4000000U)
51650 #define LPI2C_SCFGR1_SDCFG_SHIFT                 (26U)
51651 /*! SDCFG - Stop Detect Configuration
51652  *  0b0..Any Stop condition following an address match
51653  *  0b1..Any Stop condition
51654  */
51655 #define LPI2C_SCFGR1_SDCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
51656 /*! @} */
51657 
51658 /*! @name SCFGR2 - Target Configuration 2 */
51659 /*! @{ */
51660 
51661 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
51662 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
51663 /*! CLKHOLD - Clock Hold Time */
51664 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
51665 
51666 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
51667 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
51668 /*! DATAVD - Data Valid Delay */
51669 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
51670 
51671 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
51672 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
51673 /*! FILTSCL - Glitch Filter SCL */
51674 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
51675 
51676 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
51677 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
51678 /*! FILTSDA - Glitch Filter SDA */
51679 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
51680 /*! @} */
51681 
51682 /*! @name SAMR - Target Address Match */
51683 /*! @{ */
51684 
51685 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
51686 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
51687 /*! ADDR0 - Address 0 Value */
51688 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
51689 
51690 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
51691 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
51692 /*! ADDR1 - Address 1 Value */
51693 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
51694 /*! @} */
51695 
51696 /*! @name SASR - Target Address Status */
51697 /*! @{ */
51698 
51699 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
51700 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
51701 /*! RADDR - Received Address */
51702 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
51703 
51704 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
51705 #define LPI2C_SASR_ANV_SHIFT                     (14U)
51706 /*! ANV - Address Not Valid
51707  *  0b0..Valid
51708  *  0b1..Not valid
51709  */
51710 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
51711 /*! @} */
51712 
51713 /*! @name STAR - Target Transmit ACK */
51714 /*! @{ */
51715 
51716 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
51717 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
51718 /*! TXNACK - Transmit NACK
51719  *  0b0..Transmit ACK
51720  *  0b1..Transmit NACK
51721  */
51722 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
51723 /*! @} */
51724 
51725 /*! @name STDR - Target Transmit Data */
51726 /*! @{ */
51727 
51728 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
51729 #define LPI2C_STDR_DATA_SHIFT                    (0U)
51730 /*! DATA - Transmit Data */
51731 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
51732 /*! @} */
51733 
51734 /*! @name SRDR - Target Receive Data */
51735 /*! @{ */
51736 
51737 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
51738 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
51739 /*! DATA - Received Data */
51740 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
51741 
51742 #define LPI2C_SRDR_RADDR_MASK                    (0x700U)
51743 #define LPI2C_SRDR_RADDR_SHIFT                   (8U)
51744 /*! RADDR - Received Address */
51745 #define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)
51746 
51747 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
51748 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
51749 /*! RXEMPTY - Receive Empty
51750  *  0b0..Not empty
51751  *  0b1..Empty
51752  */
51753 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
51754 
51755 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
51756 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
51757 /*! SOF - Start of Frame
51758  *  0b0..Not first
51759  *  0b1..First
51760  */
51761 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
51762 /*! @} */
51763 
51764 /*! @name SRDROR - Target Receive Data Read Only */
51765 /*! @{ */
51766 
51767 #define LPI2C_SRDROR_DATA_MASK                   (0xFFU)
51768 #define LPI2C_SRDROR_DATA_SHIFT                  (0U)
51769 /*! DATA - Receive Data */
51770 #define LPI2C_SRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)
51771 
51772 #define LPI2C_SRDROR_RADDR_MASK                  (0x700U)
51773 #define LPI2C_SRDROR_RADDR_SHIFT                 (8U)
51774 /*! RADDR - Received Address */
51775 #define LPI2C_SRDROR_RADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)
51776 
51777 #define LPI2C_SRDROR_RXEMPTY_MASK                (0x4000U)
51778 #define LPI2C_SRDROR_RXEMPTY_SHIFT               (14U)
51779 /*! RXEMPTY - Receive Empty
51780  *  0b0..Not empty
51781  *  0b1..Empty
51782  */
51783 #define LPI2C_SRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)
51784 
51785 #define LPI2C_SRDROR_SOF_MASK                    (0x8000U)
51786 #define LPI2C_SRDROR_SOF_SHIFT                   (15U)
51787 /*! SOF - Start of Frame
51788  *  0b0..Not the first
51789  *  0b1..First
51790  */
51791 #define LPI2C_SRDROR_SOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
51792 /*! @} */
51793 
51794 /*! @name MTCBR - Controller Transmit Command Burst */
51795 /*! @{ */
51796 
51797 #define LPI2C_MTCBR_DATA_MASK                    (0xFFU)
51798 #define LPI2C_MTCBR_DATA_SHIFT                   (0U)
51799 /*! DATA - Data */
51800 #define LPI2C_MTCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK)
51801 
51802 #define LPI2C_MTCBR_CMD_MASK                     (0x700U)
51803 #define LPI2C_MTCBR_CMD_SHIFT                    (8U)
51804 /*! CMD - Command */
51805 #define LPI2C_MTCBR_CMD(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK)
51806 /*! @} */
51807 
51808 /* The count of LPI2C_MTCBR */
51809 #define LPI2C_MTCBR_COUNT                        (128U)
51810 
51811 /*! @name MTDBR - Transmit Data Burst */
51812 /*! @{ */
51813 
51814 #define LPI2C_MTDBR_DATA0_MASK                   (0xFFU)
51815 #define LPI2C_MTDBR_DATA0_SHIFT                  (0U)
51816 /*! DATA0 - Data */
51817 #define LPI2C_MTDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK)
51818 
51819 #define LPI2C_MTDBR_DATA1_MASK                   (0xFF00U)
51820 #define LPI2C_MTDBR_DATA1_SHIFT                  (8U)
51821 /*! DATA1 - Data */
51822 #define LPI2C_MTDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK)
51823 
51824 #define LPI2C_MTDBR_DATA2_MASK                   (0xFF0000U)
51825 #define LPI2C_MTDBR_DATA2_SHIFT                  (16U)
51826 /*! DATA2 - Data */
51827 #define LPI2C_MTDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK)
51828 
51829 #define LPI2C_MTDBR_DATA3_MASK                   (0xFF000000U)
51830 #define LPI2C_MTDBR_DATA3_SHIFT                  (24U)
51831 /*! DATA3 - Data */
51832 #define LPI2C_MTDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK)
51833 /*! @} */
51834 
51835 /* The count of LPI2C_MTDBR */
51836 #define LPI2C_MTDBR_COUNT                        (256U)
51837 
51838 
51839 /*!
51840  * @}
51841  */ /* end of group LPI2C_Register_Masks */
51842 
51843 
51844 /* LPI2C - Peripheral instance base addresses */
51845 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
51846   /** Peripheral LPI2C1 base address */
51847   #define LPI2C1_BASE                              (0x54340000u)
51848   /** Peripheral LPI2C1 base address */
51849   #define LPI2C1_BASE_NS                           (0x44340000u)
51850   /** Peripheral LPI2C1 base pointer */
51851   #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
51852   /** Peripheral LPI2C1 base pointer */
51853   #define LPI2C1_NS                                ((LPI2C_Type *)LPI2C1_BASE_NS)
51854   /** Peripheral LPI2C2 base address */
51855   #define LPI2C2_BASE                              (0x54350000u)
51856   /** Peripheral LPI2C2 base address */
51857   #define LPI2C2_BASE_NS                           (0x44350000u)
51858   /** Peripheral LPI2C2 base pointer */
51859   #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
51860   /** Peripheral LPI2C2 base pointer */
51861   #define LPI2C2_NS                                ((LPI2C_Type *)LPI2C2_BASE_NS)
51862   /** Peripheral LPI2C3 base address */
51863   #define LPI2C3_BASE                              (0x52530000u)
51864   /** Peripheral LPI2C3 base address */
51865   #define LPI2C3_BASE_NS                           (0x42530000u)
51866   /** Peripheral LPI2C3 base pointer */
51867   #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
51868   /** Peripheral LPI2C3 base pointer */
51869   #define LPI2C3_NS                                ((LPI2C_Type *)LPI2C3_BASE_NS)
51870   /** Array initializer of LPI2C peripheral base addresses */
51871   #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE }
51872   /** Array initializer of LPI2C peripheral base pointers */
51873   #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3 }
51874   /** Array initializer of LPI2C peripheral base addresses */
51875   #define LPI2C_BASE_ADDRS_NS                      { 0u, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS }
51876   /** Array initializer of LPI2C peripheral base pointers */
51877   #define LPI2C_BASE_PTRS_NS                       { (LPI2C_Type *)0u, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS }
51878 #else
51879   /** Peripheral LPI2C1 base address */
51880   #define LPI2C1_BASE                              (0x44340000u)
51881   /** Peripheral LPI2C1 base pointer */
51882   #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
51883   /** Peripheral LPI2C2 base address */
51884   #define LPI2C2_BASE                              (0x44350000u)
51885   /** Peripheral LPI2C2 base pointer */
51886   #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
51887   /** Peripheral LPI2C3 base address */
51888   #define LPI2C3_BASE                              (0x42530000u)
51889   /** Peripheral LPI2C3 base pointer */
51890   #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
51891   /** Array initializer of LPI2C peripheral base addresses */
51892   #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE }
51893   /** Array initializer of LPI2C peripheral base pointers */
51894   #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3 }
51895 #endif
51896 /** Interrupt vectors for the LPI2C peripheral type */
51897 #define LPI2C_IRQS                               { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn }
51898 
51899 /*!
51900  * @}
51901  */ /* end of group LPI2C_Peripheral_Access_Layer */
51902 
51903 
51904 /* ----------------------------------------------------------------------------
51905    -- LPIT Peripheral Access Layer
51906    ---------------------------------------------------------------------------- */
51907 
51908 /*!
51909  * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
51910  * @{
51911  */
51912 
51913 /** LPIT - Register Layout Typedef */
51914 typedef struct {
51915   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
51916   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
51917   __IO uint32_t MCR;                               /**< Module Control, offset: 0x8 */
51918   __IO uint32_t MSR;                               /**< Module Status, offset: 0xC */
51919   __IO uint32_t MIER;                              /**< Module Interrupt Enable, offset: 0x10 */
51920   __IO uint32_t SETTEN;                            /**< Set Timer Enable, offset: 0x14 */
51921   __O  uint32_t CLRTEN;                            /**< Clear Timer Enable, offset: 0x18 */
51922        uint8_t RESERVED_0[4];
51923   struct {                                         /* offset: 0x20, array step: 0x10 */
51924     __IO uint32_t TVAL;                              /**< Timer Value, array offset: 0x20, array step: 0x10 */
51925     __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
51926     __IO uint32_t TCTRL;                             /**< Timer Control, array offset: 0x28, array step: 0x10 */
51927          uint8_t RESERVED_0[4];
51928   } CHANNEL[4];
51929 } LPIT_Type;
51930 
51931 /* ----------------------------------------------------------------------------
51932    -- LPIT Register Masks
51933    ---------------------------------------------------------------------------- */
51934 
51935 /*!
51936  * @addtogroup LPIT_Register_Masks LPIT Register Masks
51937  * @{
51938  */
51939 
51940 /*! @name VERID - Version ID */
51941 /*! @{ */
51942 
51943 #define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
51944 #define LPIT_VERID_FEATURE_SHIFT                 (0U)
51945 /*! FEATURE - Feature Number */
51946 #define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
51947 
51948 #define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
51949 #define LPIT_VERID_MINOR_SHIFT                   (16U)
51950 /*! MINOR - Minor Version Number */
51951 #define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
51952 
51953 #define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
51954 #define LPIT_VERID_MAJOR_SHIFT                   (24U)
51955 /*! MAJOR - Major Version Number */
51956 #define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
51957 /*! @} */
51958 
51959 /*! @name PARAM - Parameter */
51960 /*! @{ */
51961 
51962 #define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
51963 #define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
51964 /*! CHANNEL - Number of Timer Channels */
51965 #define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
51966 
51967 #define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
51968 #define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
51969 /*! EXT_TRIG - Number of External Trigger Inputs */
51970 #define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
51971 /*! @} */
51972 
51973 /*! @name MCR - Module Control */
51974 /*! @{ */
51975 
51976 #define LPIT_MCR_M_CEN_MASK                      (0x1U)
51977 #define LPIT_MCR_M_CEN_SHIFT                     (0U)
51978 /*! M_CEN - Module Clock Enable
51979  *  0b0..Disable
51980  *  0b1..Enable
51981  */
51982 #define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
51983 
51984 #define LPIT_MCR_SW_RST_MASK                     (0x2U)
51985 #define LPIT_MCR_SW_RST_SHIFT                    (1U)
51986 /*! SW_RST - Software Reset
51987  *  0b0..Does not reset
51988  *  0b1..Resets
51989  */
51990 #define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
51991 
51992 #define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
51993 #define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
51994 /*! DOZE_EN - DOZE Mode Enable
51995  *  0b0..Stops timer channels
51996  *  0b1..Allows timer channels to continue running
51997  */
51998 #define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
51999 
52000 #define LPIT_MCR_DBG_EN_MASK                     (0x8U)
52001 #define LPIT_MCR_DBG_EN_SHIFT                    (3U)
52002 /*! DBG_EN - Debug Mode Enable
52003  *  0b0..Stops timer channels
52004  *  0b1..Allows timer channels to continue running
52005  */
52006 #define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
52007 /*! @} */
52008 
52009 /*! @name MSR - Module Status */
52010 /*! @{ */
52011 
52012 #define LPIT_MSR_TIF0_MASK                       (0x1U)
52013 #define LPIT_MSR_TIF0_SHIFT                      (0U)
52014 /*! TIF0 - Channel 0 Timer Interrupt Flag
52015  *  0b0..Not timed out
52016  *  0b1..Timed out
52017  *  0b0..No effect
52018  *  0b1..Clear the flag
52019  */
52020 #define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
52021 
52022 #define LPIT_MSR_TIF1_MASK                       (0x2U)
52023 #define LPIT_MSR_TIF1_SHIFT                      (1U)
52024 /*! TIF1 - Channel 1 Timer Interrupt Flag
52025  *  0b0..Not timed out
52026  *  0b1..Timed out
52027  *  0b0..No effect
52028  *  0b1..Clear the flag
52029  */
52030 #define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
52031 
52032 #define LPIT_MSR_TIF2_MASK                       (0x4U)
52033 #define LPIT_MSR_TIF2_SHIFT                      (2U)
52034 /*! TIF2 - Channel 2 Timer Interrupt Flag
52035  *  0b0..Not timed out
52036  *  0b1..Timed out
52037  *  0b0..No effect
52038  *  0b1..Clear the flag
52039  */
52040 #define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
52041 
52042 #define LPIT_MSR_TIF3_MASK                       (0x8U)
52043 #define LPIT_MSR_TIF3_SHIFT                      (3U)
52044 /*! TIF3 - Channel 3 Timer Interrupt Flag
52045  *  0b0..Not timed out
52046  *  0b1..Timed out
52047  *  0b0..No effect
52048  *  0b1..Clear the flag
52049  */
52050 #define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
52051 /*! @} */
52052 
52053 /*! @name MIER - Module Interrupt Enable */
52054 /*! @{ */
52055 
52056 #define LPIT_MIER_TIE0_MASK                      (0x1U)
52057 #define LPIT_MIER_TIE0_SHIFT                     (0U)
52058 /*! TIE0 - Channel 0 Timer Interrupt Enable
52059  *  0b0..Disable
52060  *  0b1..Enable
52061  */
52062 #define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
52063 
52064 #define LPIT_MIER_TIE1_MASK                      (0x2U)
52065 #define LPIT_MIER_TIE1_SHIFT                     (1U)
52066 /*! TIE1 - Channel 1 Timer Interrupt Enable
52067  *  0b0..Disable
52068  *  0b1..Enable
52069  */
52070 #define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
52071 
52072 #define LPIT_MIER_TIE2_MASK                      (0x4U)
52073 #define LPIT_MIER_TIE2_SHIFT                     (2U)
52074 /*! TIE2 - Channel 2 Timer Interrupt Enable
52075  *  0b0..Disable
52076  *  0b1..Enable
52077  */
52078 #define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
52079 
52080 #define LPIT_MIER_TIE3_MASK                      (0x8U)
52081 #define LPIT_MIER_TIE3_SHIFT                     (3U)
52082 /*! TIE3 - Channel 3 Timer Interrupt Enable
52083  *  0b0..Disable
52084  *  0b1..Enable
52085  */
52086 #define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
52087 /*! @} */
52088 
52089 /*! @name SETTEN - Set Timer Enable */
52090 /*! @{ */
52091 
52092 #define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
52093 #define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
52094 /*! SET_T_EN_0 - Set Timer 0 Enable
52095  *  0b0..No effect
52096  *  0b1..Enables timer channel 0
52097  */
52098 #define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
52099 
52100 #define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
52101 #define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
52102 /*! SET_T_EN_1 - Set Timer 1 Enable
52103  *  0b0..No Effect
52104  *  0b1..Enables timer channel 1
52105  */
52106 #define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
52107 
52108 #define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
52109 #define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
52110 /*! SET_T_EN_2 - Set Timer 2 Enable
52111  *  0b0..No Effect
52112  *  0b1..Enables timer channel 2
52113  */
52114 #define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
52115 
52116 #define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
52117 #define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
52118 /*! SET_T_EN_3 - Set Timer 3 Enable
52119  *  0b0..No effect
52120  *  0b1..Enables timer channel 3
52121  */
52122 #define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
52123 /*! @} */
52124 
52125 /*! @name CLRTEN - Clear Timer Enable */
52126 /*! @{ */
52127 
52128 #define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
52129 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
52130 /*! CLR_T_EN_0 - Clear Timer 0 Enable
52131  *  0b0..No action
52132  *  0b1..Turns TCTRL0[T_EN] = 0 for timer channel 0
52133  */
52134 #define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
52135 
52136 #define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
52137 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
52138 /*! CLR_T_EN_1 - Clear Timer 1 Enable
52139  *  0b0..No action
52140  *  0b1..Turns TCTRL1[T_EN] = 0 for timer channel 1
52141  */
52142 #define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
52143 
52144 #define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
52145 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
52146 /*! CLR_T_EN_2 - Clear Timer 2 Enable
52147  *  0b0..No action
52148  *  0b1..Turns TCTRL2[T_EN] = 0 for timer channel 2
52149  */
52150 #define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
52151 
52152 #define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
52153 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
52154 /*! CLR_T_EN_3 - Clear Timer 3 Enable
52155  *  0b0..No action
52156  *  0b1..Turns TCTRL3[T_EN] = 0 for timer channel 3
52157  */
52158 #define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
52159 /*! @} */
52160 
52161 /*! @name TVAL - Timer Value */
52162 /*! @{ */
52163 
52164 #define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
52165 #define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
52166 /*! TMR_VAL - Timer Value
52167  *  0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in Compare mode
52168  *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In Compare mode: the value to be loaded; in Capture mode, the value of the timer
52169  */
52170 #define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
52171 /*! @} */
52172 
52173 /* The count of LPIT_TVAL */
52174 #define LPIT_TVAL_COUNT                          (4U)
52175 
52176 /*! @name CVAL - Current Timer Value */
52177 /*! @{ */
52178 
52179 #define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
52180 #define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
52181 /*! TMR_CUR_VAL - Current Timer Value */
52182 #define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
52183 /*! @} */
52184 
52185 /* The count of LPIT_CVAL */
52186 #define LPIT_CVAL_COUNT                          (4U)
52187 
52188 /*! @name TCTRL - Timer Control */
52189 /*! @{ */
52190 
52191 #define LPIT_TCTRL_T_EN_MASK                     (0x1U)
52192 #define LPIT_TCTRL_T_EN_SHIFT                    (0U)
52193 /*! T_EN - Timer Enable
52194  *  0b0..Disable
52195  *  0b1..Enable
52196  */
52197 #define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
52198 
52199 #define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
52200 #define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
52201 /*! CHAIN - Chain Channel
52202  *  0b0..Disabled
52203  *  0b1..Enabled
52204  */
52205 #define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
52206 
52207 #define LPIT_TCTRL_MODE_MASK                     (0xCU)
52208 #define LPIT_TCTRL_MODE_SHIFT                    (2U)
52209 /*! MODE - Timer Operation Mode
52210  *  0b00..32-bit periodic counter
52211  *  0b01..Dual 16-bit periodic counter
52212  *  0b10..32-bit trigger accumulator
52213  *  0b11..32-bit trigger input capture
52214  */
52215 #define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
52216 
52217 #define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
52218 #define LPIT_TCTRL_TSOT_SHIFT                    (16U)
52219 /*! TSOT - Timer Start on Trigger
52220  *  0b0..Immediately
52221  *  0b1..When a rising edge is detected
52222  */
52223 #define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
52224 
52225 #define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
52226 #define LPIT_TCTRL_TSOI_SHIFT                    (17U)
52227 /*! TSOI - Timer Stop on Interrupt
52228  *  0b0..Does not stop
52229  *  0b1..Stops
52230  */
52231 #define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
52232 
52233 #define LPIT_TCTRL_TROT_MASK                     (0x40000U)
52234 #define LPIT_TCTRL_TROT_SHIFT                    (18U)
52235 /*! TROT - Timer Reload on Trigger
52236  *  0b0..Does not reload
52237  *  0b1..Reloads
52238  */
52239 #define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
52240 
52241 #define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
52242 #define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
52243 /*! TRG_SRC - Trigger Source
52244  *  0b0..External
52245  *  0b1..Internal
52246  */
52247 #define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
52248 
52249 #define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
52250 #define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
52251 /*! TRG_SEL - Trigger Select
52252  *  0b0000-0b0011..Timer channel 0-3 trigger source
52253  *  0b0100-0b1111..Reserved
52254  */
52255 #define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
52256 /*! @} */
52257 
52258 /* The count of LPIT_TCTRL */
52259 #define LPIT_TCTRL_COUNT                         (4U)
52260 
52261 
52262 /*!
52263  * @}
52264  */ /* end of group LPIT_Register_Masks */
52265 
52266 
52267 /* LPIT - Peripheral instance base addresses */
52268 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
52269   /** Peripheral LPIT1 base address */
52270   #define LPIT1_BASE                               (0x542F0000u)
52271   /** Peripheral LPIT1 base address */
52272   #define LPIT1_BASE_NS                            (0x442F0000u)
52273   /** Peripheral LPIT1 base pointer */
52274   #define LPIT1                                    ((LPIT_Type *)LPIT1_BASE)
52275   /** Peripheral LPIT1 base pointer */
52276   #define LPIT1_NS                                 ((LPIT_Type *)LPIT1_BASE_NS)
52277   /** Peripheral LPIT2 base address */
52278   #define LPIT2_BASE                               (0x524C0000u)
52279   /** Peripheral LPIT2 base address */
52280   #define LPIT2_BASE_NS                            (0x424C0000u)
52281   /** Peripheral LPIT2 base pointer */
52282   #define LPIT2                                    ((LPIT_Type *)LPIT2_BASE)
52283   /** Peripheral LPIT2 base pointer */
52284   #define LPIT2_NS                                 ((LPIT_Type *)LPIT2_BASE_NS)
52285   /** Peripheral LPIT3 base address */
52286   #define LPIT3_BASE                               (0x52CC0000u)
52287   /** Peripheral LPIT3 base address */
52288   #define LPIT3_BASE_NS                            (0x42CC0000u)
52289   /** Peripheral LPIT3 base pointer */
52290   #define LPIT3                                    ((LPIT_Type *)LPIT3_BASE)
52291   /** Peripheral LPIT3 base pointer */
52292   #define LPIT3_NS                                 ((LPIT_Type *)LPIT3_BASE_NS)
52293   /** Array initializer of LPIT peripheral base addresses */
52294   #define LPIT_BASE_ADDRS                          { 0u, LPIT1_BASE, LPIT2_BASE, LPIT3_BASE }
52295   /** Array initializer of LPIT peripheral base pointers */
52296   #define LPIT_BASE_PTRS                           { (LPIT_Type *)0u, LPIT1, LPIT2, LPIT3 }
52297   /** Array initializer of LPIT peripheral base addresses */
52298   #define LPIT_BASE_ADDRS_NS                       { 0u, LPIT1_BASE_NS, LPIT2_BASE_NS, LPIT3_BASE_NS }
52299   /** Array initializer of LPIT peripheral base pointers */
52300   #define LPIT_BASE_PTRS_NS                        { (LPIT_Type *)0u, LPIT1_NS, LPIT2_NS, LPIT3_NS }
52301 #else
52302   /** Peripheral LPIT1 base address */
52303   #define LPIT1_BASE                               (0x442F0000u)
52304   /** Peripheral LPIT1 base pointer */
52305   #define LPIT1                                    ((LPIT_Type *)LPIT1_BASE)
52306   /** Peripheral LPIT2 base address */
52307   #define LPIT2_BASE                               (0x424C0000u)
52308   /** Peripheral LPIT2 base pointer */
52309   #define LPIT2                                    ((LPIT_Type *)LPIT2_BASE)
52310   /** Peripheral LPIT3 base address */
52311   #define LPIT3_BASE                               (0x42CC0000u)
52312   /** Peripheral LPIT3 base pointer */
52313   #define LPIT3                                    ((LPIT_Type *)LPIT3_BASE)
52314   /** Array initializer of LPIT peripheral base addresses */
52315   #define LPIT_BASE_ADDRS                          { 0u, LPIT1_BASE, LPIT2_BASE, LPIT3_BASE }
52316   /** Array initializer of LPIT peripheral base pointers */
52317   #define LPIT_BASE_PTRS                           { (LPIT_Type *)0u, LPIT1, LPIT2, LPIT3 }
52318 #endif
52319 /** Interrupt vectors for the LPIT peripheral type */
52320 #define LPIT_IRQS                                { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn }, { LPIT2_IRQn, LPIT2_IRQn, LPIT2_IRQn, LPIT2_IRQn }, { LPIT3_IRQn, LPIT3_IRQn, LPIT3_IRQn, LPIT3_IRQn } }
52321 
52322 /*!
52323  * @}
52324  */ /* end of group LPIT_Peripheral_Access_Layer */
52325 
52326 
52327 /* ----------------------------------------------------------------------------
52328    -- LPSPI Peripheral Access Layer
52329    ---------------------------------------------------------------------------- */
52330 
52331 /*!
52332  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
52333  * @{
52334  */
52335 
52336 /** LPSPI - Register Layout Typedef */
52337 typedef struct {
52338   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
52339   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
52340        uint8_t RESERVED_0[8];
52341   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
52342   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
52343   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
52344   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
52345   __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
52346   __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
52347        uint8_t RESERVED_1[8];
52348   __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
52349   __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
52350        uint8_t RESERVED_2[8];
52351   __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
52352   __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
52353        uint8_t RESERVED_3[16];
52354   __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
52355   __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
52356   __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
52357   __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
52358        uint8_t RESERVED_4[8];
52359   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
52360   __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
52361   __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
52362        uint8_t RESERVED_5[896];
52363   __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
52364   __O  uint32_t TDBR[128];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
52365   __I  uint32_t RDBR[128];                         /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
52366 } LPSPI_Type;
52367 
52368 /* ----------------------------------------------------------------------------
52369    -- LPSPI Register Masks
52370    ---------------------------------------------------------------------------- */
52371 
52372 /*!
52373  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
52374  * @{
52375  */
52376 
52377 /*! @name VERID - Version ID */
52378 /*! @{ */
52379 
52380 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
52381 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
52382 /*! FEATURE - Module Identification Number
52383  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
52384  *  *..
52385  */
52386 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
52387 
52388 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
52389 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
52390 /*! MINOR - Minor Version Number */
52391 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
52392 
52393 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
52394 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
52395 /*! MAJOR - Major Version Number */
52396 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
52397 /*! @} */
52398 
52399 /*! @name PARAM - Parameter */
52400 /*! @{ */
52401 
52402 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
52403 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
52404 /*! TXFIFO - Transmit FIFO Size */
52405 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
52406 
52407 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
52408 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
52409 /*! RXFIFO - Receive FIFO Size */
52410 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
52411 
52412 #define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
52413 #define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
52414 /*! PCSNUM - PCS Number */
52415 #define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
52416 /*! @} */
52417 
52418 /*! @name CR - Control */
52419 /*! @{ */
52420 
52421 #define LPSPI_CR_MEN_MASK                        (0x1U)
52422 #define LPSPI_CR_MEN_SHIFT                       (0U)
52423 /*! MEN - Module Enable
52424  *  0b0..Disable
52425  *  0b1..Enable
52426  */
52427 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
52428 
52429 #define LPSPI_CR_RST_MASK                        (0x2U)
52430 #define LPSPI_CR_RST_SHIFT                       (1U)
52431 /*! RST - Software Reset
52432  *  0b0..Not reset
52433  *  0b1..Reset
52434  */
52435 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
52436 
52437 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
52438 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
52439 /*! DOZEN - Doze Mode Enable
52440  *  0b0..Enable
52441  *  0b1..Disable
52442  */
52443 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
52444 
52445 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
52446 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
52447 /*! DBGEN - Debug Enable
52448  *  0b0..Disable
52449  *  0b1..Enable
52450  */
52451 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
52452 
52453 #define LPSPI_CR_RTF_MASK                        (0x100U)
52454 #define LPSPI_CR_RTF_SHIFT                       (8U)
52455 /*! RTF - Reset Transmit FIFO
52456  *  0b0..No effect
52457  *  0b1..Reset
52458  */
52459 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
52460 
52461 #define LPSPI_CR_RRF_MASK                        (0x200U)
52462 #define LPSPI_CR_RRF_SHIFT                       (9U)
52463 /*! RRF - Reset Receive FIFO
52464  *  0b0..No effect
52465  *  0b1..Reset
52466  */
52467 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
52468 /*! @} */
52469 
52470 /*! @name SR - Status */
52471 /*! @{ */
52472 
52473 #define LPSPI_SR_TDF_MASK                        (0x1U)
52474 #define LPSPI_SR_TDF_SHIFT                       (0U)
52475 /*! TDF - Transmit Data Flag
52476  *  0b0..Transmit data not requested
52477  *  0b1..Transmit data is requested
52478  */
52479 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
52480 
52481 #define LPSPI_SR_RDF_MASK                        (0x2U)
52482 #define LPSPI_SR_RDF_SHIFT                       (1U)
52483 /*! RDF - Receive Data Flag
52484  *  0b0..Receive data not ready
52485  *  0b1..Receive data is ready
52486  */
52487 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
52488 
52489 #define LPSPI_SR_WCF_MASK                        (0x100U)
52490 #define LPSPI_SR_WCF_SHIFT                       (8U)
52491 /*! WCF - Word Complete Flag
52492  *  0b0..Not complete
52493  *  0b1..Complete
52494  */
52495 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
52496 
52497 #define LPSPI_SR_FCF_MASK                        (0x200U)
52498 #define LPSPI_SR_FCF_SHIFT                       (9U)
52499 /*! FCF - Frame Complete Flag
52500  *  0b0..Not complete
52501  *  0b1..Complete
52502  */
52503 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
52504 
52505 #define LPSPI_SR_TCF_MASK                        (0x400U)
52506 #define LPSPI_SR_TCF_SHIFT                       (10U)
52507 /*! TCF - Transfer Complete Flag
52508  *  0b0..Not complete
52509  *  0b1..Complete
52510  */
52511 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
52512 
52513 #define LPSPI_SR_TEF_MASK                        (0x800U)
52514 #define LPSPI_SR_TEF_SHIFT                       (11U)
52515 /*! TEF - Transmit Error Flag
52516  *  0b0..No underrun
52517  *  0b1..Underrun
52518  */
52519 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
52520 
52521 #define LPSPI_SR_REF_MASK                        (0x1000U)
52522 #define LPSPI_SR_REF_SHIFT                       (12U)
52523 /*! REF - Receive Error Flag
52524  *  0b0..No overflow
52525  *  0b1..Overflow
52526  */
52527 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
52528 
52529 #define LPSPI_SR_DMF_MASK                        (0x2000U)
52530 #define LPSPI_SR_DMF_SHIFT                       (13U)
52531 /*! DMF - Data Match Flag
52532  *  0b0..No match
52533  *  0b1..Match
52534  */
52535 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
52536 
52537 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
52538 #define LPSPI_SR_MBF_SHIFT                       (24U)
52539 /*! MBF - Module Busy Flag
52540  *  0b0..LPSPI is idle
52541  *  0b1..LPSPI is busy
52542  */
52543 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
52544 /*! @} */
52545 
52546 /*! @name IER - Interrupt Enable */
52547 /*! @{ */
52548 
52549 #define LPSPI_IER_TDIE_MASK                      (0x1U)
52550 #define LPSPI_IER_TDIE_SHIFT                     (0U)
52551 /*! TDIE - Transmit Data Interrupt Enable
52552  *  0b0..Disable
52553  *  0b1..Enable
52554  */
52555 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
52556 
52557 #define LPSPI_IER_RDIE_MASK                      (0x2U)
52558 #define LPSPI_IER_RDIE_SHIFT                     (1U)
52559 /*! RDIE - Receive Data Interrupt Enable
52560  *  0b0..Disable
52561  *  0b1..Enable
52562  */
52563 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
52564 
52565 #define LPSPI_IER_WCIE_MASK                      (0x100U)
52566 #define LPSPI_IER_WCIE_SHIFT                     (8U)
52567 /*! WCIE - Word Complete Interrupt Enable
52568  *  0b0..Disable
52569  *  0b1..Enable
52570  */
52571 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
52572 
52573 #define LPSPI_IER_FCIE_MASK                      (0x200U)
52574 #define LPSPI_IER_FCIE_SHIFT                     (9U)
52575 /*! FCIE - Frame Complete Interrupt Enable
52576  *  0b0..Disable
52577  *  0b1..Enable
52578  */
52579 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
52580 
52581 #define LPSPI_IER_TCIE_MASK                      (0x400U)
52582 #define LPSPI_IER_TCIE_SHIFT                     (10U)
52583 /*! TCIE - Transfer Complete Interrupt Enable
52584  *  0b0..Disable
52585  *  0b1..Enable
52586  */
52587 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
52588 
52589 #define LPSPI_IER_TEIE_MASK                      (0x800U)
52590 #define LPSPI_IER_TEIE_SHIFT                     (11U)
52591 /*! TEIE - Transmit Error Interrupt Enable
52592  *  0b0..Disable
52593  *  0b1..Enable
52594  */
52595 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
52596 
52597 #define LPSPI_IER_REIE_MASK                      (0x1000U)
52598 #define LPSPI_IER_REIE_SHIFT                     (12U)
52599 /*! REIE - Receive Error Interrupt Enable
52600  *  0b0..Disable
52601  *  0b1..Enable
52602  */
52603 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
52604 
52605 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
52606 #define LPSPI_IER_DMIE_SHIFT                     (13U)
52607 /*! DMIE - Data Match Interrupt Enable
52608  *  0b0..Disable
52609  *  0b1..Enable
52610  */
52611 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
52612 /*! @} */
52613 
52614 /*! @name DER - DMA Enable */
52615 /*! @{ */
52616 
52617 #define LPSPI_DER_TDDE_MASK                      (0x1U)
52618 #define LPSPI_DER_TDDE_SHIFT                     (0U)
52619 /*! TDDE - Transmit Data DMA Enable
52620  *  0b0..Disable
52621  *  0b1..Enable
52622  */
52623 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
52624 
52625 #define LPSPI_DER_RDDE_MASK                      (0x2U)
52626 #define LPSPI_DER_RDDE_SHIFT                     (1U)
52627 /*! RDDE - Receive Data DMA Enable
52628  *  0b0..Disable
52629  *  0b1..Enable
52630  */
52631 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
52632 
52633 #define LPSPI_DER_FCDE_MASK                      (0x200U)
52634 #define LPSPI_DER_FCDE_SHIFT                     (9U)
52635 /*! FCDE - Frame Complete DMA Enable
52636  *  0b0..Disable
52637  *  0b1..Enable
52638  */
52639 #define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
52640 /*! @} */
52641 
52642 /*! @name CFGR0 - Configuration 0 */
52643 /*! @{ */
52644 
52645 #define LPSPI_CFGR0_HREN_MASK                    (0x1U)
52646 #define LPSPI_CFGR0_HREN_SHIFT                   (0U)
52647 /*! HREN - Host Request Enable
52648  *  0b0..Disable
52649  *  0b1..Enable
52650  */
52651 #define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
52652 
52653 #define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
52654 #define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
52655 /*! HRPOL - Host Request Polarity
52656  *  0b0..Active high
52657  *  0b1..Active low
52658  */
52659 #define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
52660 
52661 #define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
52662 #define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
52663 /*! HRSEL - Host Request Select
52664  *  0b0..HREQ pin
52665  *  0b1..Input trigger
52666  */
52667 #define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
52668 
52669 #define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
52670 #define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
52671 /*! HRDIR - Host Request Direction
52672  *  0b0..Input
52673  *  0b1..Output
52674  */
52675 #define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)
52676 
52677 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
52678 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
52679 /*! CIRFIFO - Circular FIFO Enable
52680  *  0b0..Disable
52681  *  0b1..Enable
52682  */
52683 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
52684 
52685 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
52686 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
52687 /*! RDMO - Receive Data Match Only
52688  *  0b0..Disable
52689  *  0b1..Enable
52690  */
52691 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
52692 /*! @} */
52693 
52694 /*! @name CFGR1 - Configuration 1 */
52695 /*! @{ */
52696 
52697 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
52698 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
52699 /*! MASTER - Master Mode
52700  *  0b0..Slave mode
52701  *  0b1..Master mode
52702  */
52703 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
52704 
52705 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
52706 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
52707 /*! SAMPLE - Sample Point
52708  *  0b0..SCK edge
52709  *  0b1..Delayed SCK edge
52710  */
52711 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
52712 
52713 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
52714 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
52715 /*! AUTOPCS - Automatic PCS
52716  *  0b0..Disable
52717  *  0b1..Enable
52718  */
52719 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
52720 
52721 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
52722 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
52723 /*! NOSTALL - No Stall
52724  *  0b0..Disable
52725  *  0b1..Enable
52726  */
52727 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
52728 
52729 #define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
52730 #define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
52731 /*! PARTIAL - Partial Enable
52732  *  0b0..Discard
52733  *  0b1..Store
52734  */
52735 #define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)
52736 
52737 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
52738 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
52739 /*! PCSPOL - Peripheral Chip Select Polarity */
52740 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
52741 
52742 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
52743 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
52744 /*! MATCFG - Match Configuration
52745  *  0b000..Match is disabled
52746  *  0b001..
52747  *  0b010..Match first data word with compare word
52748  *  0b011..Match any data word with compare word
52749  *  0b100..Sequential match, first data word
52750  *  0b101..Sequential match, any data word
52751  *  0b110..Match first data word (masked) with compare word (masked)
52752  *  0b111..Match any data word (masked) with compare word (masked)
52753  */
52754 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
52755 
52756 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
52757 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
52758 /*! PINCFG - Pin Configuration
52759  *  0b00..SIN is used for input data; SOUT is used for output data.
52760  *  0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported.
52761  *  0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported.
52762  *  0b11..SOUT is used for input data; SIN is used for output data.
52763  */
52764 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
52765 
52766 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
52767 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
52768 /*! OUTCFG - Output Configuration
52769  *  0b0..Output data retains last value.
52770  *  0b1..Output data is 3-stated.
52771  */
52772 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
52773 
52774 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
52775 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
52776 /*! PCSCFG - Peripheral Chip Select Configuration
52777  *  0b0..PCS[3:2] are configured for chip select function
52778  *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
52779  */
52780 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
52781 /*! @} */
52782 
52783 /*! @name DMR0 - Data Match 0 */
52784 /*! @{ */
52785 
52786 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
52787 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
52788 /*! MATCH0 - Match 0 Value */
52789 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
52790 /*! @} */
52791 
52792 /*! @name DMR1 - Data Match 1 */
52793 /*! @{ */
52794 
52795 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
52796 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
52797 /*! MATCH1 - Match 1 Value */
52798 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
52799 /*! @} */
52800 
52801 /*! @name CCR - Clock Configuration */
52802 /*! @{ */
52803 
52804 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
52805 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
52806 /*! SCKDIV - SCK Divider */
52807 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
52808 
52809 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
52810 #define LPSPI_CCR_DBT_SHIFT                      (8U)
52811 /*! DBT - Delay Between Transfers */
52812 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
52813 
52814 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
52815 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
52816 /*! PCSSCK - PCS-to-SCK Delay */
52817 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
52818 
52819 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
52820 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
52821 /*! SCKPCS - SCK-to-PCS Delay */
52822 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
52823 /*! @} */
52824 
52825 /*! @name CCR1 - Clock Configuration 1 */
52826 /*! @{ */
52827 
52828 #define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
52829 #define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
52830 /*! SCKSET - SCK Setup */
52831 #define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)
52832 
52833 #define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
52834 #define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
52835 /*! SCKHLD - SCK Hold */
52836 #define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)
52837 
52838 #define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
52839 #define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
52840 /*! PCSPCS - PCS to PCS delay */
52841 #define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)
52842 
52843 #define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
52844 #define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
52845 /*! SCKSCK - SCK Inter-Frame Delay */
52846 #define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
52847 /*! @} */
52848 
52849 /*! @name FCR - FIFO Control */
52850 /*! @{ */
52851 
52852 #define LPSPI_FCR_TXWATER_MASK                   (0xFU)
52853 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
52854 /*! TXWATER - Transmit FIFO Watermark */
52855 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
52856 
52857 #define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)
52858 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
52859 /*! RXWATER - Receive FIFO Watermark */
52860 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
52861 /*! @} */
52862 
52863 /*! @name FSR - FIFO Status */
52864 /*! @{ */
52865 
52866 #define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)
52867 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
52868 /*! TXCOUNT - Transmit FIFO Count */
52869 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
52870 
52871 #define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)
52872 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
52873 /*! RXCOUNT - Receive FIFO Count */
52874 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
52875 /*! @} */
52876 
52877 /*! @name TCR - Transmit Command */
52878 /*! @{ */
52879 
52880 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
52881 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
52882 /*! FRAMESZ - Frame Size */
52883 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
52884 
52885 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
52886 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
52887 /*! WIDTH - Transfer Width
52888  *  0b00..1-bit transfer
52889  *  0b01..2-bit transfer
52890  *  0b10..4-bit transfer
52891  *  0b11..Reserved
52892  */
52893 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
52894 
52895 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
52896 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
52897 /*! TXMSK - Transmit Data Mask
52898  *  0b0..Normal transfer
52899  *  0b1..Mask transmit data
52900  */
52901 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
52902 
52903 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
52904 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
52905 /*! RXMSK - Receive Data Mask
52906  *  0b0..Normal transfer
52907  *  0b1..Receive data is masked
52908  */
52909 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
52910 
52911 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
52912 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
52913 /*! CONTC - Continuing Command
52914  *  0b0..Command word for start of new transfer
52915  *  0b1..Command word for continuing transfer
52916  */
52917 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
52918 
52919 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
52920 #define LPSPI_TCR_CONT_SHIFT                     (21U)
52921 /*! CONT - Continuous Transfer
52922  *  0b0..Continuous transfer is disabled
52923  *  0b1..Continuous transfer is enabled
52924  */
52925 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
52926 
52927 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
52928 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
52929 /*! BYSW - Byte Swap
52930  *  0b0..Disabled
52931  *  0b1..Enabled
52932  */
52933 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
52934 
52935 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
52936 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
52937 /*! LSBF - LSB First
52938  *  0b0..Data is transferred MSB first
52939  *  0b1..Data is transferred LSB first
52940  */
52941 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
52942 
52943 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
52944 #define LPSPI_TCR_PCS_SHIFT                      (24U)
52945 /*! PCS - Peripheral Chip Select
52946  *  0b00..Transfer using PCS[0]
52947  *  0b01..Transfer using PCS[1]
52948  *  0b10..Transfer using PCS[2]
52949  *  0b11..Transfer using PCS[3]
52950  */
52951 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
52952 
52953 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
52954 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
52955 /*! PRESCALE - Prescaler Value
52956  *  0b000..Divide by 1
52957  *  0b001..Divide by 2
52958  *  0b010..Divide by 4
52959  *  0b011..Divide by 8
52960  *  0b100..Divide by 16
52961  *  0b101..Divide by 32
52962  *  0b110..Divide by 64
52963  *  0b111..Divide by 128
52964  */
52965 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
52966 
52967 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
52968 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
52969 /*! CPHA - Clock Phase
52970  *  0b0..Captured
52971  *  0b1..Changed
52972  */
52973 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
52974 
52975 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
52976 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
52977 /*! CPOL - Clock Polarity
52978  *  0b0..Inactive low
52979  *  0b1..Inactive high
52980  */
52981 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
52982 /*! @} */
52983 
52984 /*! @name TDR - Transmit Data */
52985 /*! @{ */
52986 
52987 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
52988 #define LPSPI_TDR_DATA_SHIFT                     (0U)
52989 /*! DATA - Transmit Data */
52990 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
52991 /*! @} */
52992 
52993 /*! @name RSR - Receive Status */
52994 /*! @{ */
52995 
52996 #define LPSPI_RSR_SOF_MASK                       (0x1U)
52997 #define LPSPI_RSR_SOF_SHIFT                      (0U)
52998 /*! SOF - Start Of Frame
52999  *  0b0..Subsequent data word
53000  *  0b1..First data word
53001  */
53002 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
53003 
53004 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
53005 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
53006 /*! RXEMPTY - RX FIFO Empty
53007  *  0b0..Not empty
53008  *  0b1..Empty
53009  */
53010 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
53011 /*! @} */
53012 
53013 /*! @name RDR - Receive Data */
53014 /*! @{ */
53015 
53016 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
53017 #define LPSPI_RDR_DATA_SHIFT                     (0U)
53018 /*! DATA - Receive Data */
53019 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
53020 /*! @} */
53021 
53022 /*! @name RDROR - Receive Data Read Only */
53023 /*! @{ */
53024 
53025 #define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
53026 #define LPSPI_RDROR_DATA_SHIFT                   (0U)
53027 /*! DATA - Receive Data */
53028 #define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
53029 /*! @} */
53030 
53031 /*! @name TCBR - Transmit Command Burst */
53032 /*! @{ */
53033 
53034 #define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
53035 #define LPSPI_TCBR_DATA_SHIFT                    (0U)
53036 /*! DATA - Command Data */
53037 #define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
53038 /*! @} */
53039 
53040 /*! @name TDBR - Transmit Data Burst */
53041 /*! @{ */
53042 
53043 #define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
53044 #define LPSPI_TDBR_DATA_SHIFT                    (0U)
53045 /*! DATA - Data */
53046 #define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
53047 /*! @} */
53048 
53049 /* The count of LPSPI_TDBR */
53050 #define LPSPI_TDBR_COUNT                         (128U)
53051 
53052 /*! @name RDBR - Receive Data Burst */
53053 /*! @{ */
53054 
53055 #define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
53056 #define LPSPI_RDBR_DATA_SHIFT                    (0U)
53057 /*! DATA - Data */
53058 #define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
53059 /*! @} */
53060 
53061 /* The count of LPSPI_RDBR */
53062 #define LPSPI_RDBR_COUNT                         (128U)
53063 
53064 
53065 /*!
53066  * @}
53067  */ /* end of group LPSPI_Register_Masks */
53068 
53069 
53070 /* LPSPI - Peripheral instance base addresses */
53071 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
53072   /** Peripheral LPSPI1 base address */
53073   #define LPSPI1_BASE                              (0x54360000u)
53074   /** Peripheral LPSPI1 base address */
53075   #define LPSPI1_BASE_NS                           (0x44360000u)
53076   /** Peripheral LPSPI1 base pointer */
53077   #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
53078   /** Peripheral LPSPI1 base pointer */
53079   #define LPSPI1_NS                                ((LPSPI_Type *)LPSPI1_BASE_NS)
53080   /** Peripheral LPSPI2 base address */
53081   #define LPSPI2_BASE                              (0x54370000u)
53082   /** Peripheral LPSPI2 base address */
53083   #define LPSPI2_BASE_NS                           (0x44370000u)
53084   /** Peripheral LPSPI2 base pointer */
53085   #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
53086   /** Peripheral LPSPI2 base pointer */
53087   #define LPSPI2_NS                                ((LPSPI_Type *)LPSPI2_BASE_NS)
53088   /** Peripheral LPSPI3 base address */
53089   #define LPSPI3_BASE                              (0x52550000u)
53090   /** Peripheral LPSPI3 base address */
53091   #define LPSPI3_BASE_NS                           (0x42550000u)
53092   /** Peripheral LPSPI3 base pointer */
53093   #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
53094   /** Peripheral LPSPI3 base pointer */
53095   #define LPSPI3_NS                                ((LPSPI_Type *)LPSPI3_BASE_NS)
53096   /** Peripheral LPSPI4 base address */
53097   #define LPSPI4_BASE                              (0x52560000u)
53098   /** Peripheral LPSPI4 base address */
53099   #define LPSPI4_BASE_NS                           (0x42560000u)
53100   /** Peripheral LPSPI4 base pointer */
53101   #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
53102   /** Peripheral LPSPI4 base pointer */
53103   #define LPSPI4_NS                                ((LPSPI_Type *)LPSPI4_BASE_NS)
53104   /** Array initializer of LPSPI peripheral base addresses */
53105   #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
53106   /** Array initializer of LPSPI peripheral base pointers */
53107   #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
53108   /** Array initializer of LPSPI peripheral base addresses */
53109   #define LPSPI_BASE_ADDRS_NS                      { 0u, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS }
53110   /** Array initializer of LPSPI peripheral base pointers */
53111   #define LPSPI_BASE_PTRS_NS                       { (LPSPI_Type *)0u, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS }
53112 #else
53113   /** Peripheral LPSPI1 base address */
53114   #define LPSPI1_BASE                              (0x44360000u)
53115   /** Peripheral LPSPI1 base pointer */
53116   #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
53117   /** Peripheral LPSPI2 base address */
53118   #define LPSPI2_BASE                              (0x44370000u)
53119   /** Peripheral LPSPI2 base pointer */
53120   #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
53121   /** Peripheral LPSPI3 base address */
53122   #define LPSPI3_BASE                              (0x42550000u)
53123   /** Peripheral LPSPI3 base pointer */
53124   #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
53125   /** Peripheral LPSPI4 base address */
53126   #define LPSPI4_BASE                              (0x42560000u)
53127   /** Peripheral LPSPI4 base pointer */
53128   #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
53129   /** Array initializer of LPSPI peripheral base addresses */
53130   #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
53131   /** Array initializer of LPSPI peripheral base pointers */
53132   #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
53133 #endif
53134 /** Interrupt vectors for the LPSPI peripheral type */
53135 #define LPSPI_IRQS                               { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
53136 
53137 /*!
53138  * @}
53139  */ /* end of group LPSPI_Peripheral_Access_Layer */
53140 
53141 
53142 /* ----------------------------------------------------------------------------
53143    -- LPTMR Peripheral Access Layer
53144    ---------------------------------------------------------------------------- */
53145 
53146 /*!
53147  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
53148  * @{
53149  */
53150 
53151 /** LPTMR - Register Layout Typedef */
53152 typedef struct {
53153   __IO uint32_t CSR;                               /**< Control Status, offset: 0x0 */
53154   __IO uint32_t PSR;                               /**< Prescaler and Glitch Filter, offset: 0x4 */
53155   __IO uint32_t CMR;                               /**< Compare, offset: 0x8 */
53156   __IO uint32_t CNR;                               /**< Counter, offset: 0xC */
53157 } LPTMR_Type;
53158 
53159 /* ----------------------------------------------------------------------------
53160    -- LPTMR Register Masks
53161    ---------------------------------------------------------------------------- */
53162 
53163 /*!
53164  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
53165  * @{
53166  */
53167 
53168 /*! @name CSR - Control Status */
53169 /*! @{ */
53170 
53171 #define LPTMR_CSR_TEN_MASK                       (0x1U)
53172 #define LPTMR_CSR_TEN_SHIFT                      (0U)
53173 /*! TEN - Timer Enable
53174  *  0b0..Disable
53175  *  0b1..Enable
53176  */
53177 #define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
53178 
53179 #define LPTMR_CSR_TMS_MASK                       (0x2U)
53180 #define LPTMR_CSR_TMS_SHIFT                      (1U)
53181 /*! TMS - Timer Mode Select
53182  *  0b0..Time Counter
53183  *  0b1..Pulse Counter
53184  */
53185 #define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
53186 
53187 #define LPTMR_CSR_TFC_MASK                       (0x4U)
53188 #define LPTMR_CSR_TFC_SHIFT                      (2U)
53189 /*! TFC - Timer Free-Running Counter
53190  *  0b0..Reset when TCF asserts
53191  *  0b1..Reset on overflow
53192  */
53193 #define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
53194 
53195 #define LPTMR_CSR_TPP_MASK                       (0x8U)
53196 #define LPTMR_CSR_TPP_SHIFT                      (3U)
53197 /*! TPP - Timer Pin Polarity
53198  *  0b0..Active-high
53199  *  0b1..Active-low
53200  */
53201 #define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
53202 
53203 #define LPTMR_CSR_TPS_MASK                       (0x30U)
53204 #define LPTMR_CSR_TPS_SHIFT                      (4U)
53205 /*! TPS - Timer Pin Select
53206  *  0b00..Input 0
53207  *  0b01..Input 1
53208  *  0b10..Input 2
53209  *  0b11..Input 3
53210  */
53211 #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
53212 
53213 #define LPTMR_CSR_TIE_MASK                       (0x40U)
53214 #define LPTMR_CSR_TIE_SHIFT                      (6U)
53215 /*! TIE - Timer Interrupt Enable
53216  *  0b0..Disable
53217  *  0b1..Enable
53218  */
53219 #define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
53220 
53221 #define LPTMR_CSR_TCF_MASK                       (0x80U)
53222 #define LPTMR_CSR_TCF_SHIFT                      (7U)
53223 /*! TCF - Timer Compare Flag
53224  *  0b0..CNR != (CMR + 1)
53225  *  0b1..CNR = (CMR + 1)
53226  *  0b0..No effect
53227  *  0b1..Clear the flag
53228  */
53229 #define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
53230 
53231 #define LPTMR_CSR_TDRE_MASK                      (0x100U)
53232 #define LPTMR_CSR_TDRE_SHIFT                     (8U)
53233 /*! TDRE - Timer DMA Request Enable
53234  *  0b0..Disable
53235  *  0b1..Enable
53236  */
53237 #define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
53238 /*! @} */
53239 
53240 /*! @name PSR - Prescaler and Glitch Filter */
53241 /*! @{ */
53242 
53243 #define LPTMR_PSR_PCS_MASK                       (0x3U)
53244 #define LPTMR_PSR_PCS_SHIFT                      (0U)
53245 /*! PCS - Prescaler and Glitch Filter Clock Select
53246  *  0b00..Clock 0
53247  *  0b01..Clock 1
53248  *  0b10..Clock 2
53249  *  0b11..Clock 3
53250  */
53251 #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
53252 
53253 #define LPTMR_PSR_PBYP_MASK                      (0x4U)
53254 #define LPTMR_PSR_PBYP_SHIFT                     (2U)
53255 /*! PBYP - Prescaler and Glitch Filter Bypass
53256  *  0b0..Prescaler and glitch filter enable
53257  *  0b1..Prescaler and glitch filter bypass
53258  */
53259 #define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
53260 
53261 #define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
53262 #define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
53263 /*! PRESCALE - Prescaler and Glitch Filter Value
53264  *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration
53265  *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges
53266  *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges
53267  *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges
53268  *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges
53269  *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges
53270  *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges
53271  *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges
53272  *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges
53273  *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges
53274  *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges
53275  *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges
53276  *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges
53277  *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges
53278  *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges
53279  *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges
53280  */
53281 #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
53282 /*! @} */
53283 
53284 /*! @name CMR - Compare */
53285 /*! @{ */
53286 
53287 #define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
53288 #define LPTMR_CMR_COMPARE_SHIFT                  (0U)
53289 /*! COMPARE - Compare Value */
53290 #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
53291 /*! @} */
53292 
53293 /*! @name CNR - Counter */
53294 /*! @{ */
53295 
53296 #define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
53297 #define LPTMR_CNR_COUNTER_SHIFT                  (0U)
53298 /*! COUNTER - Counter Value */
53299 #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
53300 /*! @} */
53301 
53302 
53303 /*!
53304  * @}
53305  */ /* end of group LPTMR_Register_Masks */
53306 
53307 
53308 /* LPTMR - Peripheral instance base addresses */
53309 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
53310   /** Peripheral LPTMR1 base address */
53311   #define LPTMR1_BASE                              (0x54300000u)
53312   /** Peripheral LPTMR1 base address */
53313   #define LPTMR1_BASE_NS                           (0x44300000u)
53314   /** Peripheral LPTMR1 base pointer */
53315   #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
53316   /** Peripheral LPTMR1 base pointer */
53317   #define LPTMR1_NS                                ((LPTMR_Type *)LPTMR1_BASE_NS)
53318   /** Array initializer of LPTMR peripheral base addresses */
53319   #define LPTMR_BASE_ADDRS                         { 0u, LPTMR1_BASE }
53320   /** Array initializer of LPTMR peripheral base pointers */
53321   #define LPTMR_BASE_PTRS                          { (LPTMR_Type *)0u, LPTMR1 }
53322   /** Array initializer of LPTMR peripheral base addresses */
53323   #define LPTMR_BASE_ADDRS_NS                      { 0u, LPTMR1_BASE_NS }
53324   /** Array initializer of LPTMR peripheral base pointers */
53325   #define LPTMR_BASE_PTRS_NS                       { (LPTMR_Type *)0u, LPTMR1_NS }
53326 #else
53327   /** Peripheral LPTMR1 base address */
53328   #define LPTMR1_BASE                              (0x44300000u)
53329   /** Peripheral LPTMR1 base pointer */
53330   #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
53331   /** Array initializer of LPTMR peripheral base addresses */
53332   #define LPTMR_BASE_ADDRS                         { 0u, LPTMR1_BASE }
53333   /** Array initializer of LPTMR peripheral base pointers */
53334   #define LPTMR_BASE_PTRS                          { (LPTMR_Type *)0u, LPTMR1 }
53335 #endif
53336 /** Interrupt vectors for the LPTMR peripheral type */
53337 #define LPTMR_IRQS                               { NotAvail_IRQn, LPTMR1_IRQn }
53338 
53339 /*!
53340  * @}
53341  */ /* end of group LPTMR_Peripheral_Access_Layer */
53342 
53343 
53344 /* ----------------------------------------------------------------------------
53345    -- LPUART Peripheral Access Layer
53346    ---------------------------------------------------------------------------- */
53347 
53348 /*!
53349  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
53350  * @{
53351  */
53352 
53353 /** LPUART - Register Layout Typedef */
53354 typedef struct {
53355   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
53356   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
53357   __IO uint32_t GLOBAL;                            /**< Global, offset: 0x8 */
53358   __IO uint32_t PINCFG;                            /**< Pin Configuration, offset: 0xC */
53359   __IO uint32_t BAUD;                              /**< Baud Rate, offset: 0x10 */
53360   __IO uint32_t STAT;                              /**< Status, offset: 0x14 */
53361   __IO uint32_t CTRL;                              /**< Control, offset: 0x18 */
53362   __IO uint32_t DATA;                              /**< Data, offset: 0x1C */
53363   __IO uint32_t MATCH;                             /**< Match Address, offset: 0x20 */
53364   __IO uint32_t MODIR;                             /**< MODEM IrDA, offset: 0x24 */
53365   __IO uint32_t FIFO;                              /**< FIFO, offset: 0x28 */
53366   __IO uint32_t WATER;                             /**< Watermark, offset: 0x2C */
53367   __I  uint32_t DATARO;                            /**< Data Read-Only, offset: 0x30 */
53368        uint8_t RESERVED_0[12];
53369   __IO uint32_t MCR;                               /**< MODEM Control, offset: 0x40 */
53370   __IO uint32_t MSR;                               /**< MODEM Status, offset: 0x44 */
53371   __IO uint32_t REIR;                              /**< Receiver Extended Idle, offset: 0x48 */
53372   __IO uint32_t TEIR;                              /**< Transmitter Extended Idle, offset: 0x4C */
53373   __IO uint32_t HDCR;                              /**< Half Duplex Control, offset: 0x50 */
53374        uint8_t RESERVED_1[4];
53375   __IO uint32_t TOCR;                              /**< Timeout Control, offset: 0x58 */
53376   __IO uint32_t TOSR;                              /**< Timeout Status, offset: 0x5C */
53377   __IO uint32_t TIMEOUT[4];                        /**< Timeout N, array offset: 0x60, array step: 0x4 */
53378        uint8_t RESERVED_2[400];
53379   __O  uint32_t TCBR[128];                         /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */
53380   __O  uint32_t TDBR[256];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
53381 } LPUART_Type;
53382 
53383 /* ----------------------------------------------------------------------------
53384    -- LPUART Register Masks
53385    ---------------------------------------------------------------------------- */
53386 
53387 /*!
53388  * @addtogroup LPUART_Register_Masks LPUART Register Masks
53389  * @{
53390  */
53391 
53392 /*! @name VERID - Version ID */
53393 /*! @{ */
53394 
53395 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
53396 #define LPUART_VERID_FEATURE_SHIFT               (0U)
53397 /*! FEATURE - Feature Identification Number
53398  *  0b0000000000000001..Standard feature set
53399  *  0b0000000000000011..Standard feature set with MODEM and IrDA support
53400  *  0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection
53401  */
53402 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
53403 
53404 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
53405 #define LPUART_VERID_MINOR_SHIFT                 (16U)
53406 /*! MINOR - Minor Version Number */
53407 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
53408 
53409 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
53410 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
53411 /*! MAJOR - Major Version Number */
53412 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
53413 /*! @} */
53414 
53415 /*! @name PARAM - Parameter */
53416 /*! @{ */
53417 
53418 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
53419 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
53420 /*! TXFIFO - Transmit FIFO Size */
53421 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
53422 
53423 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
53424 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
53425 /*! RXFIFO - Receive FIFO Size */
53426 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
53427 /*! @} */
53428 
53429 /*! @name GLOBAL - Global */
53430 /*! @{ */
53431 
53432 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
53433 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
53434 /*! RST - Software Reset
53435  *  0b0..Not reset
53436  *  0b1..Reset
53437  */
53438 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
53439 /*! @} */
53440 
53441 /*! @name PINCFG - Pin Configuration */
53442 /*! @{ */
53443 
53444 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
53445 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
53446 /*! TRGSEL - Trigger Select
53447  *  0b00..Input trigger disabled
53448  *  0b01..Input trigger used instead of the RXD pin input
53449  *  0b10..Input trigger used instead of the CTS_B pin input
53450  *  0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
53451  */
53452 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
53453 /*! @} */
53454 
53455 /*! @name BAUD - Baud Rate */
53456 /*! @{ */
53457 
53458 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
53459 #define LPUART_BAUD_SBR_SHIFT                    (0U)
53460 /*! SBR - Baud Rate Modulo Divisor */
53461 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
53462 
53463 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
53464 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
53465 /*! SBNS - Stop Bit Number Select
53466  *  0b0..One stop bit
53467  *  0b1..Two stop bits
53468  */
53469 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
53470 
53471 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
53472 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
53473 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
53474  *  0b0..Disable
53475  *  0b1..Enable
53476  */
53477 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
53478 
53479 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
53480 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
53481 /*! LBKDIE - LIN Break Detect Interrupt Enable
53482  *  0b0..Disable
53483  *  0b1..Enable
53484  */
53485 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
53486 
53487 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
53488 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
53489 /*! RESYNCDIS - Resynchronization Disable
53490  *  0b0..Enable
53491  *  0b1..Disable
53492  */
53493 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
53494 
53495 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
53496 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
53497 /*! BOTHEDGE - Both Edge Sampling
53498  *  0b0..Rising edge
53499  *  0b1..Both rising and falling edges
53500  */
53501 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
53502 
53503 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
53504 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
53505 /*! MATCFG - Match Configuration
53506  *  0b00..Address match wake-up
53507  *  0b01..Idle match wake-up
53508  *  0b10..Match on and match off
53509  *  0b11..Enables RWU on data match and match on or off for the transmitter CTS input
53510  */
53511 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
53512 
53513 #define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
53514 #define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
53515 /*! RIDMAE - Receiver Idle DMA Enable
53516  *  0b0..Disable
53517  *  0b1..Enable
53518  */
53519 #define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
53520 
53521 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
53522 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
53523 /*! RDMAE - Receiver Full DMA Enable
53524  *  0b0..Disable
53525  *  0b1..Enable
53526  */
53527 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
53528 
53529 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
53530 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
53531 /*! TDMAE - Transmitter DMA Enable
53532  *  0b0..Disable
53533  *  0b1..Enable
53534  */
53535 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
53536 
53537 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
53538 #define LPUART_BAUD_OSR_SHIFT                    (24U)
53539 /*! OSR - Oversampling Ratio
53540  *  0b00000..Results in an OSR of 16
53541  *  0b00001..Reserved
53542  *  0b00010..Reserved
53543  *  0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1)
53544  *  0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1)
53545  *  0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1)
53546  *  0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1)
53547  *  0b00111..Results in an OSR of 8
53548  *  0b01000..Results in an OSR of 9
53549  *  0b01001..Results in an OSR of 10
53550  *  0b01010..Results in an OSR of 11
53551  *  0b01011..Results in an OSR of 12
53552  *  0b01100..Results in an OSR of 13
53553  *  0b01101..Results in an OSR of 14
53554  *  0b01110..Results in an OSR of 15
53555  *  0b01111..Results in an OSR of 16
53556  *  0b10000..Results in an OSR of 17
53557  *  0b10001..Results in an OSR of 18
53558  *  0b10010..Results in an OSR of 19
53559  *  0b10011..Results in an OSR of 20
53560  *  0b10100..Results in an OSR of 21
53561  *  0b10101..Results in an OSR of 22
53562  *  0b10110..Results in an OSR of 23
53563  *  0b10111..Results in an OSR of 24
53564  *  0b11000..Results in an OSR of 25
53565  *  0b11001..Results in an OSR of 26
53566  *  0b11010..Results in an OSR of 27
53567  *  0b11011..Results in an OSR of 28
53568  *  0b11100..Results in an OSR of 29
53569  *  0b11101..Results in an OSR of 30
53570  *  0b11110..Results in an OSR of 31
53571  *  0b11111..Results in an OSR of 32
53572  */
53573 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
53574 
53575 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
53576 #define LPUART_BAUD_M10_SHIFT                    (29U)
53577 /*! M10 - 10-Bit Mode Select
53578  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters
53579  *  0b1..Receiver and transmitter use 10-bit data characters
53580  */
53581 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
53582 
53583 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
53584 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
53585 /*! MAEN2 - Match Address Mode Enable 2
53586  *  0b0..Disable
53587  *  0b1..Enable
53588  */
53589 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
53590 
53591 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
53592 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
53593 /*! MAEN1 - Match Address Mode Enable 1
53594  *  0b0..Disable
53595  *  0b1..Enable
53596  */
53597 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
53598 /*! @} */
53599 
53600 /*! @name STAT - Status */
53601 /*! @{ */
53602 
53603 #define LPUART_STAT_LBKFE_MASK                   (0x1U)
53604 #define LPUART_STAT_LBKFE_SHIFT                  (0U)
53605 /*! LBKFE - LIN Break Flag Enable
53606  *  0b0..Disable
53607  *  0b1..Enable
53608  */
53609 #define LPUART_STAT_LBKFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)
53610 
53611 #define LPUART_STAT_AME_MASK                     (0x2U)
53612 #define LPUART_STAT_AME_SHIFT                    (1U)
53613 /*! AME - Address Mark Enable
53614  *  0b0..Disable
53615  *  0b1..Enable
53616  */
53617 #define LPUART_STAT_AME(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)
53618 
53619 #define LPUART_STAT_MSF_MASK                     (0x100U)
53620 #define LPUART_STAT_MSF_SHIFT                    (8U)
53621 /*! MSF - MODEM Status Flag
53622  *  0b0..Field is 0
53623  *  0b1..Field is 1
53624  */
53625 #define LPUART_STAT_MSF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK)
53626 
53627 #define LPUART_STAT_TSF_MASK                     (0x200U)
53628 #define LPUART_STAT_TSF_SHIFT                    (9U)
53629 /*! TSF - Timeout Status Flag
53630  *  0b0..Field is 0
53631  *  0b1..Field is 1
53632  */
53633 #define LPUART_STAT_TSF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK)
53634 
53635 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
53636 #define LPUART_STAT_MA2F_SHIFT                   (14U)
53637 /*! MA2F - Match 2 Flag
53638  *  0b0..Not equal to MA2
53639  *  0b1..Equal to MA2
53640  *  0b0..No effect
53641  *  0b1..Clear the flag
53642  */
53643 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
53644 
53645 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
53646 #define LPUART_STAT_MA1F_SHIFT                   (15U)
53647 /*! MA1F - Match 1 Flag
53648  *  0b0..Not equal to MA1
53649  *  0b1..Equal to MA1
53650  *  0b0..No effect
53651  *  0b1..Clear the flag
53652  */
53653 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
53654 
53655 #define LPUART_STAT_PF_MASK                      (0x10000U)
53656 #define LPUART_STAT_PF_SHIFT                     (16U)
53657 /*! PF - Parity Error Flag
53658  *  0b0..No parity error detected
53659  *  0b1..Parity error detected
53660  *  0b0..No effect
53661  *  0b1..Clear the flag
53662  */
53663 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
53664 
53665 #define LPUART_STAT_FE_MASK                      (0x20000U)
53666 #define LPUART_STAT_FE_SHIFT                     (17U)
53667 /*! FE - Framing Error Flag
53668  *  0b0..No framing error detected (this does not guarantee that the framing is correct)
53669  *  0b1..Framing error detected
53670  *  0b0..No effect
53671  *  0b1..Clear the flag
53672  */
53673 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
53674 
53675 #define LPUART_STAT_NF_MASK                      (0x40000U)
53676 #define LPUART_STAT_NF_SHIFT                     (18U)
53677 /*! NF - Noise Flag
53678  *  0b0..No noise detected
53679  *  0b1..Noise detected
53680  *  0b0..No effect
53681  *  0b1..Clear the flag
53682  */
53683 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
53684 
53685 #define LPUART_STAT_OR_MASK                      (0x80000U)
53686 #define LPUART_STAT_OR_SHIFT                     (19U)
53687 /*! OR - Receiver Overrun Flag
53688  *  0b0..No overrun
53689  *  0b1..Receive overrun (new LPUART data is lost)
53690  *  0b0..No effect
53691  *  0b1..Clear the flag
53692  */
53693 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
53694 
53695 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
53696 #define LPUART_STAT_IDLE_SHIFT                   (20U)
53697 /*! IDLE - Idle Line Flag
53698  *  0b0..Idle line detected
53699  *  0b1..Idle line not detected
53700  *  0b0..No effect
53701  *  0b1..Clear the flag
53702  */
53703 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
53704 
53705 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
53706 #define LPUART_STAT_RDRF_SHIFT                   (21U)
53707 /*! RDRF - Receive Data Register Full Flag
53708  *  0b0..Equal to or less than watermark
53709  *  0b1..Greater than watermark
53710  */
53711 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
53712 
53713 #define LPUART_STAT_TC_MASK                      (0x400000U)
53714 #define LPUART_STAT_TC_SHIFT                     (22U)
53715 /*! TC - Transmission Complete Flag
53716  *  0b0..Transmitter active
53717  *  0b1..Transmitter idle
53718  */
53719 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
53720 
53721 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
53722 #define LPUART_STAT_TDRE_SHIFT                   (23U)
53723 /*! TDRE - Transmit Data Register Empty Flag
53724  *  0b0..Greater than watermark
53725  *  0b1..Equal to or less than watermark
53726  */
53727 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
53728 
53729 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
53730 #define LPUART_STAT_RAF_SHIFT                    (24U)
53731 /*! RAF - Receiver Active Flag
53732  *  0b0..Idle, waiting for a start bit
53733  *  0b1..Receiver active (RXD pin input not idle)
53734  */
53735 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
53736 
53737 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
53738 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
53739 /*! LBKDE - LIN Break Detection Enable
53740  *  0b0..Disable
53741  *  0b1..Enable
53742  */
53743 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
53744 
53745 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
53746 #define LPUART_STAT_BRK13_SHIFT                  (26U)
53747 /*! BRK13 - Break Character Generation Length
53748  *  0b0..9 to 13 bit times
53749  *  0b1..12 to 15 bit times
53750  */
53751 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
53752 
53753 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
53754 #define LPUART_STAT_RWUID_SHIFT                  (27U)
53755 /*! RWUID - Receive Wake Up Idle Detect
53756  *  0b0..STAT[IDLE] does not become 1
53757  *  0b1..STAT[IDLE] becomes 1
53758  */
53759 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
53760 
53761 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
53762 #define LPUART_STAT_RXINV_SHIFT                  (28U)
53763 /*! RXINV - Receive Data Inversion
53764  *  0b0..Inverted
53765  *  0b1..Not inverted
53766  */
53767 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
53768 
53769 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
53770 #define LPUART_STAT_MSBF_SHIFT                   (29U)
53771 /*! MSBF - MSB First
53772  *  0b0..LSB
53773  *  0b1..MSB
53774  */
53775 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
53776 
53777 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
53778 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
53779 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
53780  *  0b0..Not occurred
53781  *  0b1..Occurred
53782  *  0b0..No effect
53783  *  0b1..Clear the flag
53784  */
53785 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
53786 
53787 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
53788 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
53789 /*! LBKDIF - LIN Break Detect Interrupt Flag
53790  *  0b0..Not detected
53791  *  0b1..Detected
53792  *  0b0..No effect
53793  *  0b1..Clear the flag
53794  */
53795 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
53796 /*! @} */
53797 
53798 /*! @name CTRL - Control */
53799 /*! @{ */
53800 
53801 #define LPUART_CTRL_PT_MASK                      (0x1U)
53802 #define LPUART_CTRL_PT_SHIFT                     (0U)
53803 /*! PT - Parity Type
53804  *  0b0..Even parity
53805  *  0b1..Odd parity
53806  */
53807 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
53808 
53809 #define LPUART_CTRL_PE_MASK                      (0x2U)
53810 #define LPUART_CTRL_PE_SHIFT                     (1U)
53811 /*! PE - Parity Enable
53812  *  0b0..Disable
53813  *  0b1..Enable
53814  */
53815 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
53816 
53817 #define LPUART_CTRL_ILT_MASK                     (0x4U)
53818 #define LPUART_CTRL_ILT_SHIFT                    (2U)
53819 /*! ILT - Idle Line Type Select
53820  *  0b0..After the start bit
53821  *  0b1..After the stop bit
53822  */
53823 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
53824 
53825 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
53826 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
53827 /*! WAKE - Receiver Wake-Up Method Select
53828  *  0b0..Idle
53829  *  0b1..Mark
53830  */
53831 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
53832 
53833 #define LPUART_CTRL_M_MASK                       (0x10U)
53834 #define LPUART_CTRL_M_SHIFT                      (4U)
53835 /*! M - 9-Bit Or 8-Bit Mode Select
53836  *  0b0..8-bit
53837  *  0b1..9-bit
53838  */
53839 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
53840 
53841 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
53842 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
53843 /*! RSRC - Receiver Source Select
53844  *  0b0..Internal Loopback mode
53845  *  0b1..Single-wire mode
53846  */
53847 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
53848 
53849 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
53850 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
53851 /*! DOZEEN - Doze Mode
53852  *  0b0..Enable
53853  *  0b1..Disable
53854  */
53855 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
53856 
53857 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
53858 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
53859 /*! LOOPS - Loop Mode Select
53860  *  0b0..Normal operation: RXD and TXD use separate pins
53861  *  0b1..Loop mode or Single-Wire mode
53862  */
53863 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
53864 
53865 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
53866 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
53867 /*! IDLECFG - Idle Configuration
53868  *  0b000..1
53869  *  0b001..2
53870  *  0b010..4
53871  *  0b011..8
53872  *  0b100..16
53873  *  0b101..32
53874  *  0b110..64
53875  *  0b111..128
53876  */
53877 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
53878 
53879 #define LPUART_CTRL_M7_MASK                      (0x800U)
53880 #define LPUART_CTRL_M7_SHIFT                     (11U)
53881 /*! M7 - 7-Bit Mode Select
53882  *  0b0..8-bit to 10-bit
53883  *  0b1..7-bit
53884  */
53885 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
53886 
53887 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
53888 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
53889 /*! MA2IE - Match 2 (MA2F) Interrupt Enable
53890  *  0b0..Disable
53891  *  0b1..Enable
53892  */
53893 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
53894 
53895 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
53896 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
53897 /*! MA1IE - Match 1 (MA1F) Interrupt Enable
53898  *  0b0..Disable
53899  *  0b1..Enable
53900  */
53901 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
53902 
53903 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
53904 #define LPUART_CTRL_SBK_SHIFT                    (16U)
53905 /*! SBK - Send Break
53906  *  0b0..Normal transmitter operation
53907  *  0b1..Queue break character(s) to be sent
53908  */
53909 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
53910 
53911 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
53912 #define LPUART_CTRL_RWU_SHIFT                    (17U)
53913 /*! RWU - Receiver Wake-Up Control
53914  *  0b0..Normal receiver operation
53915  *  0b1..LPUART receiver in standby, waiting for a wake-up condition
53916  */
53917 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
53918 
53919 #define LPUART_CTRL_RE_MASK                      (0x40000U)
53920 #define LPUART_CTRL_RE_SHIFT                     (18U)
53921 /*! RE - Receiver Enable
53922  *  0b0..Disable
53923  *  0b1..Enable
53924  */
53925 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
53926 
53927 #define LPUART_CTRL_TE_MASK                      (0x80000U)
53928 #define LPUART_CTRL_TE_SHIFT                     (19U)
53929 /*! TE - Transmitter Enable
53930  *  0b0..Disable
53931  *  0b1..Enable
53932  */
53933 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
53934 
53935 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
53936 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
53937 /*! ILIE - Idle Line Interrupt Enable
53938  *  0b0..Disable
53939  *  0b1..Enable
53940  */
53941 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
53942 
53943 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
53944 #define LPUART_CTRL_RIE_SHIFT                    (21U)
53945 /*! RIE - Receiver Interrupt Enable
53946  *  0b0..Disable
53947  *  0b1..Enable
53948  */
53949 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
53950 
53951 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
53952 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
53953 /*! TCIE - Transmission Complete Interrupt Enable
53954  *  0b0..Disable
53955  *  0b1..Enable
53956  */
53957 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
53958 
53959 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
53960 #define LPUART_CTRL_TIE_SHIFT                    (23U)
53961 /*! TIE - Transmit Interrupt Enable
53962  *  0b0..Disable
53963  *  0b1..Enable
53964  */
53965 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
53966 
53967 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
53968 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
53969 /*! PEIE - Parity Error Interrupt Enable
53970  *  0b0..Disable
53971  *  0b1..Enable
53972  */
53973 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
53974 
53975 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
53976 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
53977 /*! FEIE - Framing Error Interrupt Enable
53978  *  0b0..Disable
53979  *  0b1..Enable
53980  */
53981 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
53982 
53983 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
53984 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
53985 /*! NEIE - Noise Error Interrupt Enable
53986  *  0b0..Disable
53987  *  0b1..Enable
53988  */
53989 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
53990 
53991 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
53992 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
53993 /*! ORIE - Overrun Interrupt Enable
53994  *  0b0..Disable
53995  *  0b1..Enable
53996  */
53997 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
53998 
53999 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
54000 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
54001 /*! TXINV - Transmit Data Inversion
54002  *  0b0..Not inverted
54003  *  0b1..Inverted
54004  */
54005 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
54006 
54007 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
54008 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
54009 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
54010  *  0b0..Input
54011  *  0b1..Output
54012  */
54013 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
54014 
54015 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
54016 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
54017 /*! R9T8 - Receive Bit 9 Transmit Bit 8 */
54018 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
54019 
54020 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
54021 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
54022 /*! R8T9 - Receive Bit 8 Transmit Bit 9 */
54023 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
54024 /*! @} */
54025 
54026 /*! @name DATA - Data */
54027 /*! @{ */
54028 
54029 #define LPUART_DATA_R0T0_MASK                    (0x1U)
54030 #define LPUART_DATA_R0T0_SHIFT                   (0U)
54031 /*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */
54032 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
54033 
54034 #define LPUART_DATA_R1T1_MASK                    (0x2U)
54035 #define LPUART_DATA_R1T1_SHIFT                   (1U)
54036 /*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */
54037 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
54038 
54039 #define LPUART_DATA_R2T2_MASK                    (0x4U)
54040 #define LPUART_DATA_R2T2_SHIFT                   (2U)
54041 /*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */
54042 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
54043 
54044 #define LPUART_DATA_R3T3_MASK                    (0x8U)
54045 #define LPUART_DATA_R3T3_SHIFT                   (3U)
54046 /*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */
54047 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
54048 
54049 #define LPUART_DATA_R4T4_MASK                    (0x10U)
54050 #define LPUART_DATA_R4T4_SHIFT                   (4U)
54051 /*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */
54052 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
54053 
54054 #define LPUART_DATA_R5T5_MASK                    (0x20U)
54055 #define LPUART_DATA_R5T5_SHIFT                   (5U)
54056 /*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */
54057 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
54058 
54059 #define LPUART_DATA_R6T6_MASK                    (0x40U)
54060 #define LPUART_DATA_R6T6_SHIFT                   (6U)
54061 /*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */
54062 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
54063 
54064 #define LPUART_DATA_R7T7_MASK                    (0x80U)
54065 #define LPUART_DATA_R7T7_SHIFT                   (7U)
54066 /*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */
54067 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
54068 
54069 #define LPUART_DATA_R8T8_MASK                    (0x100U)
54070 #define LPUART_DATA_R8T8_SHIFT                   (8U)
54071 /*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */
54072 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
54073 
54074 #define LPUART_DATA_R9T9_MASK                    (0x200U)
54075 #define LPUART_DATA_R9T9_SHIFT                   (9U)
54076 /*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */
54077 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
54078 
54079 #define LPUART_DATA_LINBRK_MASK                  (0x400U)
54080 #define LPUART_DATA_LINBRK_SHIFT                 (10U)
54081 /*! LINBRK - LIN Break
54082  *  0b0..Not detected
54083  *  0b1..Detected
54084  */
54085 #define LPUART_DATA_LINBRK(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)
54086 
54087 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
54088 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
54089 /*! IDLINE - Idle Line
54090  *  0b0..Not idle
54091  *  0b1..Idle
54092  */
54093 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
54094 
54095 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
54096 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
54097 /*! RXEMPT - Receive Buffer Empty
54098  *  0b0..Valid data
54099  *  0b1..Invalid data and empty
54100  */
54101 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
54102 
54103 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
54104 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
54105 /*! FRETSC - Frame Error Transmit Special Character
54106  *  0b0..Received without a frame error on reads or transmits a normal character on writes
54107  *  0b1..Received with a frame error on reads or transmits an idle or break character on writes
54108  */
54109 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
54110 
54111 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
54112 #define LPUART_DATA_PARITYE_SHIFT                (14U)
54113 /*! PARITYE - Parity Error
54114  *  0b0..Received without a parity error
54115  *  0b1..Received with a parity error
54116  */
54117 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
54118 
54119 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
54120 #define LPUART_DATA_NOISY_SHIFT                  (15U)
54121 /*! NOISY - Noisy Data Received
54122  *  0b0..Received without noise
54123  *  0b1..Received with noise
54124  */
54125 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
54126 /*! @} */
54127 
54128 /*! @name MATCH - Match Address */
54129 /*! @{ */
54130 
54131 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
54132 #define LPUART_MATCH_MA1_SHIFT                   (0U)
54133 /*! MA1 - Match Address 1 */
54134 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
54135 
54136 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
54137 #define LPUART_MATCH_MA2_SHIFT                   (16U)
54138 /*! MA2 - Match Address 2 */
54139 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
54140 /*! @} */
54141 
54142 /*! @name MODIR - MODEM IrDA */
54143 /*! @{ */
54144 
54145 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
54146 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
54147 /*! TXCTSE - Transmitter CTS Enable
54148  *  0b0..Disable
54149  *  0b1..Enable
54150  */
54151 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
54152 
54153 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
54154 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
54155 /*! TXRTSE - Transmitter RTS Enable
54156  *  0b0..Disable
54157  *  0b1..Enable
54158  */
54159 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
54160 
54161 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
54162 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
54163 /*! TXRTSPOL - Transmitter RTS Polarity
54164  *  0b0..Active low
54165  *  0b1..Active high
54166  */
54167 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
54168 
54169 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
54170 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
54171 /*! RXRTSE - Receiver RTS Enable
54172  *  0b0..Disable
54173  *  0b1..Enable
54174  */
54175 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
54176 
54177 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
54178 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
54179 /*! TXCTSC - Transmit CTS Configuration
54180  *  0b0..Sampled at the start of each character
54181  *  0b1..Sampled when the transmitter is idle
54182  */
54183 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
54184 
54185 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
54186 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
54187 /*! TXCTSSRC - Transmit CTS Source
54188  *  0b0..The CTS_B pin
54189  *  0b1..An internal connection to the receiver address match result
54190  */
54191 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
54192 
54193 #define LPUART_MODIR_RTSWATER_MASK               (0xF00U)
54194 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
54195 /*! RTSWATER - Receive RTS Configuration */
54196 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
54197 
54198 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
54199 #define LPUART_MODIR_TNP_SHIFT                   (16U)
54200 /*! TNP - Transmitter Narrow Pulse
54201  *  0b00..1 / OSR
54202  *  0b01..2 / OSR
54203  *  0b10..3 / OSR
54204  *  0b11..4 / OSR
54205  */
54206 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
54207 
54208 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
54209 #define LPUART_MODIR_IREN_SHIFT                  (18U)
54210 /*! IREN - IR Enable
54211  *  0b0..Disable
54212  *  0b1..Enable
54213  */
54214 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
54215 /*! @} */
54216 
54217 /*! @name FIFO - FIFO */
54218 /*! @{ */
54219 
54220 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
54221 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
54222 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
54223  *  0b000..1
54224  *  0b001..4
54225  *  0b010..8
54226  *  0b011..16
54227  *  0b100..32
54228  *  0b101..64
54229  *  0b110..128
54230  *  0b111..256
54231  */
54232 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
54233 
54234 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
54235 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
54236 /*! RXFE - Receive FIFO Enable
54237  *  0b0..Disable
54238  *  0b1..Enable
54239  */
54240 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
54241 
54242 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
54243 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
54244 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
54245  *  0b000..1
54246  *  0b001..4
54247  *  0b010..8
54248  *  0b011..16
54249  *  0b100..32
54250  *  0b101..64
54251  *  0b110..128
54252  *  0b111..256
54253  */
54254 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
54255 
54256 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
54257 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
54258 /*! TXFE - Transmit FIFO Enable
54259  *  0b0..Disable
54260  *  0b1..Enable
54261  */
54262 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
54263 
54264 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
54265 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
54266 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
54267  *  0b0..Disable
54268  *  0b1..Enable
54269  */
54270 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
54271 
54272 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
54273 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
54274 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
54275  *  0b0..Disable
54276  *  0b1..Enable
54277  */
54278 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
54279 
54280 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
54281 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
54282 /*! RXIDEN - Receiver Idle Empty Enable
54283  *  0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle
54284  *  0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character
54285  *  0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters
54286  *  0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters
54287  *  0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters
54288  *  0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters
54289  *  0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters
54290  *  0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
54291  */
54292 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
54293 
54294 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
54295 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
54296 /*! RXFLUSH - Receive FIFO Flush
54297  *  0b0..No effect
54298  *  0b1..All data flushed out
54299  */
54300 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
54301 
54302 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
54303 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
54304 /*! TXFLUSH - Transmit FIFO Flush
54305  *  0b0..No effect
54306  *  0b1..All data flushed out
54307  */
54308 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
54309 
54310 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
54311 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
54312 /*! RXUF - Receiver FIFO Underflow Flag
54313  *  0b0..No underflow
54314  *  0b1..Underflow
54315  *  0b0..No effect
54316  *  0b1..Clear the flag
54317  */
54318 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
54319 
54320 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
54321 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
54322 /*! TXOF - Transmitter FIFO Overflow Flag
54323  *  0b0..No overflow
54324  *  0b1..Overflow
54325  *  0b0..No effect
54326  *  0b1..Clear the flag
54327  */
54328 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
54329 
54330 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
54331 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
54332 /*! RXEMPT - Receive FIFO Or Buffer Empty
54333  *  0b0..Not empty
54334  *  0b1..Empty
54335  */
54336 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
54337 
54338 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
54339 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
54340 /*! TXEMPT - Transmit FIFO Or Buffer Empty
54341  *  0b0..Not empty
54342  *  0b1..Empty
54343  */
54344 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
54345 /*! @} */
54346 
54347 /*! @name WATER - Watermark */
54348 /*! @{ */
54349 
54350 #define LPUART_WATER_TXWATER_MASK                (0xFU)
54351 #define LPUART_WATER_TXWATER_SHIFT               (0U)
54352 /*! TXWATER - Transmit Watermark */
54353 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
54354 
54355 #define LPUART_WATER_TXCOUNT_MASK                (0x1F00U)
54356 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
54357 /*! TXCOUNT - Transmit Counter */
54358 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
54359 
54360 #define LPUART_WATER_RXWATER_MASK                (0xF0000U)
54361 #define LPUART_WATER_RXWATER_SHIFT               (16U)
54362 /*! RXWATER - Receive Watermark */
54363 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
54364 
54365 #define LPUART_WATER_RXCOUNT_MASK                (0x1F000000U)
54366 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
54367 /*! RXCOUNT - Receive Counter */
54368 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
54369 /*! @} */
54370 
54371 /*! @name DATARO - Data Read-Only */
54372 /*! @{ */
54373 
54374 #define LPUART_DATARO_DATA_MASK                  (0xFFFFU)
54375 #define LPUART_DATARO_DATA_SHIFT                 (0U)
54376 /*! DATA - Receive Data */
54377 #define LPUART_DATARO_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
54378 /*! @} */
54379 
54380 /*! @name MCR - MODEM Control */
54381 /*! @{ */
54382 
54383 #define LPUART_MCR_CTS_MASK                      (0x1U)
54384 #define LPUART_MCR_CTS_SHIFT                     (0U)
54385 /*! CTS - Clear To Send
54386  *  0b0..Disable interrupt
54387  *  0b1..Enable interrupt
54388  */
54389 #define LPUART_MCR_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK)
54390 
54391 #define LPUART_MCR_DSR_MASK                      (0x2U)
54392 #define LPUART_MCR_DSR_SHIFT                     (1U)
54393 /*! DSR - Data Set Ready
54394  *  0b0..Disable interrupt
54395  *  0b1..Enable interrupt
54396  */
54397 #define LPUART_MCR_DSR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK)
54398 
54399 #define LPUART_MCR_RIN_MASK                      (0x4U)
54400 #define LPUART_MCR_RIN_SHIFT                     (2U)
54401 /*! RIN - Ring Indicator
54402  *  0b0..Disable interrupt
54403  *  0b1..Enable interrupt
54404  */
54405 #define LPUART_MCR_RIN(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK)
54406 
54407 #define LPUART_MCR_DCD_MASK                      (0x8U)
54408 #define LPUART_MCR_DCD_SHIFT                     (3U)
54409 /*! DCD - Data Carrier Detect
54410  *  0b0..Disable interrupt
54411  *  0b1..Enable interrupt
54412  */
54413 #define LPUART_MCR_DCD(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK)
54414 
54415 #define LPUART_MCR_DTR_MASK                      (0x100U)
54416 #define LPUART_MCR_DTR_SHIFT                     (8U)
54417 /*! DTR - Data Terminal Ready
54418  *  0b0..Logic one
54419  *  0b1..Logic zero
54420  */
54421 #define LPUART_MCR_DTR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK)
54422 
54423 #define LPUART_MCR_RTS_MASK                      (0x200U)
54424 #define LPUART_MCR_RTS_SHIFT                     (9U)
54425 /*! RTS - Request To Send
54426  *  0b0..Logic one
54427  *  0b1..Logic zero
54428  */
54429 #define LPUART_MCR_RTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK)
54430 /*! @} */
54431 
54432 /*! @name MSR - MODEM Status */
54433 /*! @{ */
54434 
54435 #define LPUART_MSR_DCTS_MASK                     (0x1U)
54436 #define LPUART_MSR_DCTS_SHIFT                    (0U)
54437 /*! DCTS - Delta Clear To Send
54438  *  0b0..Did not change state
54439  *  0b1..Changed state
54440  *  0b0..No effect
54441  *  0b1..Clear the flag
54442  */
54443 #define LPUART_MSR_DCTS(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK)
54444 
54445 #define LPUART_MSR_DDSR_MASK                     (0x2U)
54446 #define LPUART_MSR_DDSR_SHIFT                    (1U)
54447 /*! DDSR - Delta Data Set Ready
54448  *  0b0..Did not change state
54449  *  0b1..Changed state
54450  *  0b0..No effect
54451  *  0b1..Clear the flag
54452  */
54453 #define LPUART_MSR_DDSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK)
54454 
54455 #define LPUART_MSR_DRI_MASK                      (0x4U)
54456 #define LPUART_MSR_DRI_SHIFT                     (2U)
54457 /*! DRI - Delta Ring Indicator
54458  *  0b0..Did not change state
54459  *  0b1..Changed state
54460  *  0b0..No effect
54461  *  0b1..Clear the flag
54462  */
54463 #define LPUART_MSR_DRI(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK)
54464 
54465 #define LPUART_MSR_DDCD_MASK                     (0x8U)
54466 #define LPUART_MSR_DDCD_SHIFT                    (3U)
54467 /*! DDCD - Delta Data Carrier Detect
54468  *  0b0..Did not change state
54469  *  0b1..Changed state
54470  *  0b0..No effect
54471  *  0b1..Clear the flag
54472  */
54473 #define LPUART_MSR_DDCD(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK)
54474 
54475 #define LPUART_MSR_CTS_MASK                      (0x10U)
54476 #define LPUART_MSR_CTS_SHIFT                     (4U)
54477 /*! CTS - Clear To Send
54478  *  0b0..Logic one
54479  *  0b1..Logic zero
54480  */
54481 #define LPUART_MSR_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK)
54482 
54483 #define LPUART_MSR_DSR_MASK                      (0x20U)
54484 #define LPUART_MSR_DSR_SHIFT                     (5U)
54485 /*! DSR - Data Set Ready
54486  *  0b0..Logic one
54487  *  0b1..Logic zero
54488  */
54489 #define LPUART_MSR_DSR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK)
54490 
54491 #define LPUART_MSR_RIN_MASK                      (0x40U)
54492 #define LPUART_MSR_RIN_SHIFT                     (6U)
54493 /*! RIN - Ring Indicator
54494  *  0b0..Logic one
54495  *  0b1..Logic zero
54496  */
54497 #define LPUART_MSR_RIN(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK)
54498 
54499 #define LPUART_MSR_DCD_MASK                      (0x80U)
54500 #define LPUART_MSR_DCD_SHIFT                     (7U)
54501 /*! DCD - Data Carrier Detect
54502  *  0b0..Logic one
54503  *  0b1..Logic zero
54504  */
54505 #define LPUART_MSR_DCD(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK)
54506 /*! @} */
54507 
54508 /*! @name REIR - Receiver Extended Idle */
54509 /*! @{ */
54510 
54511 #define LPUART_REIR_IDTIME_MASK                  (0x3FFFU)
54512 #define LPUART_REIR_IDTIME_SHIFT                 (0U)
54513 /*! IDTIME - Idle Time */
54514 #define LPUART_REIR_IDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK)
54515 /*! @} */
54516 
54517 /*! @name TEIR - Transmitter Extended Idle */
54518 /*! @{ */
54519 
54520 #define LPUART_TEIR_IDTIME_MASK                  (0x3FFFU)
54521 #define LPUART_TEIR_IDTIME_SHIFT                 (0U)
54522 /*! IDTIME - Idle Time */
54523 #define LPUART_TEIR_IDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK)
54524 /*! @} */
54525 
54526 /*! @name HDCR - Half Duplex Control */
54527 /*! @{ */
54528 
54529 #define LPUART_HDCR_TXSTALL_MASK                 (0x1U)
54530 #define LPUART_HDCR_TXSTALL_SHIFT                (0U)
54531 /*! TXSTALL - Transmit Stall
54532  *  0b0..No effect
54533  *  0b1..Does not become busy
54534  */
54535 #define LPUART_HDCR_TXSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK)
54536 
54537 #define LPUART_HDCR_RXSEL_MASK                   (0x2U)
54538 #define LPUART_HDCR_RXSEL_SHIFT                  (1U)
54539 /*! RXSEL - Receive Select
54540  *  0b0..RXD
54541  *  0b1..TXD
54542  */
54543 #define LPUART_HDCR_RXSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK)
54544 
54545 #define LPUART_HDCR_RXWRMSK_MASK                 (0x4U)
54546 #define LPUART_HDCR_RXWRMSK_SHIFT                (2U)
54547 /*! RXWRMSK - Receive FIFO Write Mask
54548  *  0b0..Do not mask
54549  *  0b1..Mask
54550  */
54551 #define LPUART_HDCR_RXWRMSK(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK)
54552 
54553 #define LPUART_HDCR_RXMSK_MASK                   (0x8U)
54554 #define LPUART_HDCR_RXMSK_SHIFT                  (3U)
54555 /*! RXMSK - Receive Mask
54556  *  0b0..Do not mask
54557  *  0b1..Mask
54558  */
54559 #define LPUART_HDCR_RXMSK(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK)
54560 
54561 #define LPUART_HDCR_RTSEXT_MASK                  (0xFF00U)
54562 #define LPUART_HDCR_RTSEXT_SHIFT                 (8U)
54563 /*! RTSEXT - RTS Extended */
54564 #define LPUART_HDCR_RTSEXT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK)
54565 /*! @} */
54566 
54567 /*! @name TOCR - Timeout Control */
54568 /*! @{ */
54569 
54570 #define LPUART_TOCR_TOEN_MASK                    (0xFU)
54571 #define LPUART_TOCR_TOEN_SHIFT                   (0U)
54572 /*! TOEN - Timeout Enable */
54573 #define LPUART_TOCR_TOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK)
54574 
54575 #define LPUART_TOCR_TOIE_MASK                    (0xF00U)
54576 #define LPUART_TOCR_TOIE_SHIFT                   (8U)
54577 /*! TOIE - Timeout Interrupt Enable */
54578 #define LPUART_TOCR_TOIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK)
54579 /*! @} */
54580 
54581 /*! @name TOSR - Timeout Status */
54582 /*! @{ */
54583 
54584 #define LPUART_TOSR_TOZ_MASK                     (0xFU)
54585 #define LPUART_TOSR_TOZ_SHIFT                    (0U)
54586 /*! TOZ - Timeout Zero */
54587 #define LPUART_TOSR_TOZ(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK)
54588 
54589 #define LPUART_TOSR_TOF_MASK                     (0xF00U)
54590 #define LPUART_TOSR_TOF_SHIFT                    (8U)
54591 /*! TOF - Timeout Flag
54592  *  0b0000..Not occurred
54593  *  0b0001..Occurred
54594  *  0b0000..No effect
54595  *  0b0001..Clear the flag
54596  */
54597 #define LPUART_TOSR_TOF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK)
54598 /*! @} */
54599 
54600 /*! @name TIMEOUT - Timeout N */
54601 /*! @{ */
54602 
54603 #define LPUART_TIMEOUT_TIMEOUT_MASK              (0x3FFFU)
54604 #define LPUART_TIMEOUT_TIMEOUT_SHIFT             (0U)
54605 /*! TIMEOUT - Timeout Value */
54606 #define LPUART_TIMEOUT_TIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK)
54607 
54608 #define LPUART_TIMEOUT_CFG_MASK                  (0xC0000000U)
54609 #define LPUART_TIMEOUT_CFG_SHIFT                 (30U)
54610 /*! CFG - Idle Configuration
54611  *  0b00..Becomes 1 after timeout characters are received
54612  *  0b01..Becomes 1 when idle for timeout bit clocks
54613  *  0b10..Becomes 1 when idle for timeout bit clocks following the next character
54614  *  0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached
54615  */
54616 #define LPUART_TIMEOUT_CFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK)
54617 /*! @} */
54618 
54619 /* The count of LPUART_TIMEOUT */
54620 #define LPUART_TIMEOUT_COUNT                     (4U)
54621 
54622 /*! @name TCBR - Transmit Command Burst */
54623 /*! @{ */
54624 
54625 #define LPUART_TCBR_DATA_MASK                    (0xFFFFU)
54626 #define LPUART_TCBR_DATA_SHIFT                   (0U)
54627 /*! DATA - Data */
54628 #define LPUART_TCBR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK)
54629 /*! @} */
54630 
54631 /* The count of LPUART_TCBR */
54632 #define LPUART_TCBR_COUNT                        (128U)
54633 
54634 /*! @name TDBR - Transmit Data Burst */
54635 /*! @{ */
54636 
54637 #define LPUART_TDBR_DATA0_MASK                   (0xFFU)
54638 #define LPUART_TDBR_DATA0_SHIFT                  (0U)
54639 /*! DATA0 - Data0 */
54640 #define LPUART_TDBR_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK)
54641 
54642 #define LPUART_TDBR_DATA1_MASK                   (0xFF00U)
54643 #define LPUART_TDBR_DATA1_SHIFT                  (8U)
54644 /*! DATA1 - Data1 */
54645 #define LPUART_TDBR_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK)
54646 
54647 #define LPUART_TDBR_DATA2_MASK                   (0xFF0000U)
54648 #define LPUART_TDBR_DATA2_SHIFT                  (16U)
54649 /*! DATA2 - Data2 */
54650 #define LPUART_TDBR_DATA2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK)
54651 
54652 #define LPUART_TDBR_DATA3_MASK                   (0xFF000000U)
54653 #define LPUART_TDBR_DATA3_SHIFT                  (24U)
54654 /*! DATA3 - Data3 */
54655 #define LPUART_TDBR_DATA3(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK)
54656 /*! @} */
54657 
54658 /* The count of LPUART_TDBR */
54659 #define LPUART_TDBR_COUNT                        (256U)
54660 
54661 
54662 /*!
54663  * @}
54664  */ /* end of group LPUART_Register_Masks */
54665 
54666 
54667 /* LPUART - Peripheral instance base addresses */
54668 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
54669   /** Peripheral LPUART1 base address */
54670   #define LPUART1_BASE                             (0x54380000u)
54671   /** Peripheral LPUART1 base address */
54672   #define LPUART1_BASE_NS                          (0x44380000u)
54673   /** Peripheral LPUART1 base pointer */
54674   #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
54675   /** Peripheral LPUART1 base pointer */
54676   #define LPUART1_NS                               ((LPUART_Type *)LPUART1_BASE_NS)
54677   /** Peripheral LPUART2 base address */
54678   #define LPUART2_BASE                             (0x54390000u)
54679   /** Peripheral LPUART2 base address */
54680   #define LPUART2_BASE_NS                          (0x44390000u)
54681   /** Peripheral LPUART2 base pointer */
54682   #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
54683   /** Peripheral LPUART2 base pointer */
54684   #define LPUART2_NS                               ((LPUART_Type *)LPUART2_BASE_NS)
54685   /** Peripheral LPUART3 base address */
54686   #define LPUART3_BASE                             (0x52570000u)
54687   /** Peripheral LPUART3 base address */
54688   #define LPUART3_BASE_NS                          (0x42570000u)
54689   /** Peripheral LPUART3 base pointer */
54690   #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
54691   /** Peripheral LPUART3 base pointer */
54692   #define LPUART3_NS                               ((LPUART_Type *)LPUART3_BASE_NS)
54693   /** Peripheral LPUART4 base address */
54694   #define LPUART4_BASE                             (0x52580000u)
54695   /** Peripheral LPUART4 base address */
54696   #define LPUART4_BASE_NS                          (0x42580000u)
54697   /** Peripheral LPUART4 base pointer */
54698   #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
54699   /** Peripheral LPUART4 base pointer */
54700   #define LPUART4_NS                               ((LPUART_Type *)LPUART4_BASE_NS)
54701   /** Peripheral LPUART5 base address */
54702   #define LPUART5_BASE                             (0x52590000u)
54703   /** Peripheral LPUART5 base address */
54704   #define LPUART5_BASE_NS                          (0x42590000u)
54705   /** Peripheral LPUART5 base pointer */
54706   #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
54707   /** Peripheral LPUART5 base pointer */
54708   #define LPUART5_NS                               ((LPUART_Type *)LPUART5_BASE_NS)
54709   /** Peripheral LPUART6 base address */
54710   #define LPUART6_BASE                             (0x525A0000u)
54711   /** Peripheral LPUART6 base address */
54712   #define LPUART6_BASE_NS                          (0x425A0000u)
54713   /** Peripheral LPUART6 base pointer */
54714   #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
54715   /** Peripheral LPUART6 base pointer */
54716   #define LPUART6_NS                               ((LPUART_Type *)LPUART6_BASE_NS)
54717   /** Peripheral LPUART7 base address */
54718   #define LPUART7_BASE                             (0x54570000u)
54719   /** Peripheral LPUART7 base address */
54720   #define LPUART7_BASE_NS                          (0x44570000u)
54721   /** Peripheral LPUART7 base pointer */
54722   #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
54723   /** Peripheral LPUART7 base pointer */
54724   #define LPUART7_NS                               ((LPUART_Type *)LPUART7_BASE_NS)
54725   /** Peripheral LPUART8 base address */
54726   #define LPUART8_BASE                             (0x52DA0000u)
54727   /** Peripheral LPUART8 base address */
54728   #define LPUART8_BASE_NS                          (0x42DA0000u)
54729   /** Peripheral LPUART8 base pointer */
54730   #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
54731   /** Peripheral LPUART8 base pointer */
54732   #define LPUART8_NS                               ((LPUART_Type *)LPUART8_BASE_NS)
54733   /** Array initializer of LPUART peripheral base addresses */
54734   #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
54735   /** Array initializer of LPUART peripheral base pointers */
54736   #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
54737   /** Array initializer of LPUART peripheral base addresses */
54738   #define LPUART_BASE_ADDRS_NS                     { 0u, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS, LPUART8_BASE_NS }
54739   /** Array initializer of LPUART peripheral base pointers */
54740   #define LPUART_BASE_PTRS_NS                      { (LPUART_Type *)0u, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS, LPUART8_NS }
54741 #else
54742   /** Peripheral LPUART1 base address */
54743   #define LPUART1_BASE                             (0x44380000u)
54744   /** Peripheral LPUART1 base pointer */
54745   #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
54746   /** Peripheral LPUART2 base address */
54747   #define LPUART2_BASE                             (0x44390000u)
54748   /** Peripheral LPUART2 base pointer */
54749   #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
54750   /** Peripheral LPUART3 base address */
54751   #define LPUART3_BASE                             (0x42570000u)
54752   /** Peripheral LPUART3 base pointer */
54753   #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
54754   /** Peripheral LPUART4 base address */
54755   #define LPUART4_BASE                             (0x42580000u)
54756   /** Peripheral LPUART4 base pointer */
54757   #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
54758   /** Peripheral LPUART5 base address */
54759   #define LPUART5_BASE                             (0x42590000u)
54760   /** Peripheral LPUART5 base pointer */
54761   #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
54762   /** Peripheral LPUART6 base address */
54763   #define LPUART6_BASE                             (0x425A0000u)
54764   /** Peripheral LPUART6 base pointer */
54765   #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
54766   /** Peripheral LPUART7 base address */
54767   #define LPUART7_BASE                             (0x44570000u)
54768   /** Peripheral LPUART7 base pointer */
54769   #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
54770   /** Peripheral LPUART8 base address */
54771   #define LPUART8_BASE                             (0x42DA0000u)
54772   /** Peripheral LPUART8 base pointer */
54773   #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
54774   /** Array initializer of LPUART peripheral base addresses */
54775   #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
54776   /** Array initializer of LPUART peripheral base pointers */
54777   #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
54778 #endif
54779 /** Interrupt vectors for the LPUART peripheral type */
54780 #define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
54781 
54782 /*!
54783  * @}
54784  */ /* end of group LPUART_Peripheral_Access_Layer */
54785 
54786 
54787 /* ----------------------------------------------------------------------------
54788    -- MECC Peripheral Access Layer
54789    ---------------------------------------------------------------------------- */
54790 
54791 /*!
54792  * @addtogroup MECC_Peripheral_Access_Layer MECC Peripheral Access Layer
54793  * @{
54794  */
54795 
54796 /** MECC - Register Layout Typedef */
54797 typedef struct {
54798   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x0 */
54799   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x4 */
54800   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0x8 */
54801   __IO uint32_t ERR_DATA_INJ_LOW0;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */
54802   __IO uint32_t ERR_DATA_INJ_HIGH0;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */
54803   __IO uint32_t ERR_ECC_INJ0;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */
54804   __IO uint32_t ERR_DATA_INJ_LOW1;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */
54805   __IO uint32_t ERR_DATA_INJ_HIGH1;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */
54806   __IO uint32_t ERR_ECC_INJ1;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */
54807   __IO uint32_t ERR_DATA_INJ_LOW2;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */
54808   __IO uint32_t ERR_DATA_INJ_HIGH2;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */
54809   __IO uint32_t ERR_ECC_INJ2;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */
54810   __IO uint32_t ERR_DATA_INJ_LOW3;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */
54811   __IO uint32_t ERR_DATA_INJ_HIGH3;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */
54812   __IO uint32_t ERR_ECC_INJ3;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */
54813   __I  uint32_t SINGLE_ERR_ADDR_ECC0;              /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */
54814   __I  uint32_t SINGLE_ERR_DATA_LOW0;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */
54815   __I  uint32_t SINGLE_ERR_DATA_HIGH0;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */
54816   __I  uint32_t SINGLE_ERR_POS_LOW0;               /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */
54817   __I  uint32_t SINGLE_ERR_POS_HIGH0;              /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */
54818   __I  uint32_t SINGLE_ERR_ADDR_ECC1;              /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */
54819   __I  uint32_t SINGLE_ERR_DATA_LOW1;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */
54820   __I  uint32_t SINGLE_ERR_DATA_HIGH1;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */
54821   __I  uint32_t SINGLE_ERR_POS_LOW1;               /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */
54822   __I  uint32_t SINGLE_ERR_POS_HIGH1;              /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */
54823   __I  uint32_t SINGLE_ERR_ADDR_ECC2;              /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */
54824   __I  uint32_t SINGLE_ERR_DATA_LOW2;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */
54825   __I  uint32_t SINGLE_ERR_DATA_HIGH2;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */
54826   __I  uint32_t SINGLE_ERR_POS_LOW2;               /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */
54827   __I  uint32_t SINGLE_ERR_POS_HIGH2;              /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */
54828   __I  uint32_t SINGLE_ERR_ADDR_ECC3;              /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */
54829   __I  uint32_t SINGLE_ERR_DATA_LOW3;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */
54830   __I  uint32_t SINGLE_ERR_DATA_HIGH3;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */
54831   __I  uint32_t SINGLE_ERR_POS_LOW3;               /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */
54832   __I  uint32_t SINGLE_ERR_POS_HIGH3;              /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */
54833   __I  uint32_t MULTI_ERR_ADDR_ECC0;               /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */
54834   __I  uint32_t MULTI_ERR_DATA_LOW0;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */
54835   __I  uint32_t MULTI_ERR_DATA_HIGH0;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */
54836   __I  uint32_t MULTI_ERR_ADDR_ECC1;               /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */
54837   __I  uint32_t MULTI_ERR_DATA_LOW1;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */
54838   __I  uint32_t MULTI_ERR_DATA_HIGH1;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */
54839   __I  uint32_t MULTI_ERR_ADDR_ECC2;               /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */
54840   __I  uint32_t MULTI_ERR_DATA_LOW2;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */
54841   __I  uint32_t MULTI_ERR_DATA_HIGH2;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */
54842   __I  uint32_t MULTI_ERR_ADDR_ECC3;               /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */
54843   __I  uint32_t MULTI_ERR_DATA_LOW3;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */
54844   __I  uint32_t MULTI_ERR_DATA_HIGH3;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */
54845        uint8_t RESERVED_0[68];
54846   __IO uint32_t PIPE_ECC_EN;                       /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */
54847   __I  uint32_t PENDING_STAT;                      /**< Pending Status, offset: 0x104 */
54848 } MECC_Type;
54849 
54850 /* ----------------------------------------------------------------------------
54851    -- MECC Register Masks
54852    ---------------------------------------------------------------------------- */
54853 
54854 /*!
54855  * @addtogroup MECC_Register_Masks MECC Register Masks
54856  * @{
54857  */
54858 
54859 /*! @name ERR_STATUS - Error Interrupt Status Register */
54860 /*! @{ */
54861 
54862 #define MECC_ERR_STATUS_SINGLE_ERR0_MASK         (0x1U)
54863 #define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT        (0U)
54864 /*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0
54865  *  0b0..Single bit error does not happen on OCRAM bank0.
54866  *  0b1..Single bit error happens on OCRAM bank0.
54867  */
54868 #define MECC_ERR_STATUS_SINGLE_ERR0(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
54869 
54870 #define MECC_ERR_STATUS_SINGLE_ERR1_MASK         (0x2U)
54871 #define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT        (1U)
54872 /*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1
54873  *  0b0..Single bit error does not happen on OCRAM bank1.
54874  *  0b1..Single bit error happens on OCRAM bank1.
54875  */
54876 #define MECC_ERR_STATUS_SINGLE_ERR1(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
54877 
54878 #define MECC_ERR_STATUS_SINGLE_ERR2_MASK         (0x4U)
54879 #define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT        (2U)
54880 /*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2
54881  *  0b0..Single bit error does not happen on OCRAM bank2.
54882  *  0b1..Single bit error happens on OCRAM bank2.
54883  */
54884 #define MECC_ERR_STATUS_SINGLE_ERR2(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
54885 
54886 #define MECC_ERR_STATUS_SINGLE_ERR3_MASK         (0x8U)
54887 #define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT        (3U)
54888 /*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3
54889  *  0b0..Single bit error does not happen on OCRAM bank3.
54890  *  0b1..Single bit error happens on OCRAM bank3.
54891  */
54892 #define MECC_ERR_STATUS_SINGLE_ERR3(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
54893 
54894 #define MECC_ERR_STATUS_MULTI_ERR0_MASK          (0x10U)
54895 #define MECC_ERR_STATUS_MULTI_ERR0_SHIFT         (4U)
54896 /*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0
54897  *  0b0..Multiple bits error does not happen on OCRAM bank0.
54898  *  0b1..Multiple bits error happens on OCRAM bank0.
54899  */
54900 #define MECC_ERR_STATUS_MULTI_ERR0(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
54901 
54902 #define MECC_ERR_STATUS_MULTI_ERR1_MASK          (0x20U)
54903 #define MECC_ERR_STATUS_MULTI_ERR1_SHIFT         (5U)
54904 /*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1
54905  *  0b0..Multiple bits error does not happen on OCRAM bank1.
54906  *  0b1..Multiple bits error happens on OCRAM bank1.
54907  */
54908 #define MECC_ERR_STATUS_MULTI_ERR1(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
54909 
54910 #define MECC_ERR_STATUS_MULTI_ERR2_MASK          (0x40U)
54911 #define MECC_ERR_STATUS_MULTI_ERR2_SHIFT         (6U)
54912 /*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2
54913  *  0b0..Multiple bits error does not happen on OCRAM bank2.
54914  *  0b1..Multiple bits error happens on OCRAM bank2.
54915  */
54916 #define MECC_ERR_STATUS_MULTI_ERR2(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
54917 
54918 #define MECC_ERR_STATUS_MULTI_ERR3_MASK          (0x80U)
54919 #define MECC_ERR_STATUS_MULTI_ERR3_SHIFT         (7U)
54920 /*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3
54921  *  0b0..Multiple bits error does not happen on OCRAM bank3.
54922  *  0b1..Multiple bits error happens on OCRAM bank3.
54923  */
54924 #define MECC_ERR_STATUS_MULTI_ERR3(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
54925 
54926 #define MECC_ERR_STATUS_STRB_ERR0_MASK           (0x100U)
54927 #define MECC_ERR_STATUS_STRB_ERR0_SHIFT          (8U)
54928 /*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0
54929  *  0b0..AXI strobe error does not happen on OCRAM bank0.
54930  *  0b1..AXI strobe error happens on OCRAM bank0.
54931  */
54932 #define MECC_ERR_STATUS_STRB_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
54933 
54934 #define MECC_ERR_STATUS_STRB_ERR1_MASK           (0x200U)
54935 #define MECC_ERR_STATUS_STRB_ERR1_SHIFT          (9U)
54936 /*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1
54937  *  0b0..AXI strobe error does not happen on OCRAM bank1.
54938  *  0b1..AXI strobe error happens on OCRAM bank1.
54939  */
54940 #define MECC_ERR_STATUS_STRB_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
54941 
54942 #define MECC_ERR_STATUS_STRB_ERR2_MASK           (0x400U)
54943 #define MECC_ERR_STATUS_STRB_ERR2_SHIFT          (10U)
54944 /*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2
54945  *  0b0..AXI strobe error does not happen on OCRAM bank2.
54946  *  0b1..AXI strobe error happens on OCRAM bank2.
54947  */
54948 #define MECC_ERR_STATUS_STRB_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
54949 
54950 #define MECC_ERR_STATUS_STRB_ERR3_MASK           (0x800U)
54951 #define MECC_ERR_STATUS_STRB_ERR3_SHIFT          (11U)
54952 /*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3
54953  *  0b0..AXI strobe error does not happen on OCRAM bank3.
54954  *  0b1..AXI strobe error happens on OCRAM bank3.
54955  */
54956 #define MECC_ERR_STATUS_STRB_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
54957 
54958 #define MECC_ERR_STATUS_ADDR_ERR0_MASK           (0x1000U)
54959 #define MECC_ERR_STATUS_ADDR_ERR0_SHIFT          (12U)
54960 /*! ADDR_ERR0 - OCRAM Access Error On Bank0
54961  *  0b0..OCRAM access error does not happen on OCRAM bank0.
54962  *  0b1..OCRAM access error happens on OCRAM bank0.
54963  */
54964 #define MECC_ERR_STATUS_ADDR_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
54965 
54966 #define MECC_ERR_STATUS_ADDR_ERR1_MASK           (0x2000U)
54967 #define MECC_ERR_STATUS_ADDR_ERR1_SHIFT          (13U)
54968 /*! ADDR_ERR1 - OCRAM Access Error On Bank1
54969  *  0b0..OCRAM access error does not happen on OCRAM bank1.
54970  *  0b1..OCRAM access error happens on OCRAM bank1.
54971  */
54972 #define MECC_ERR_STATUS_ADDR_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
54973 
54974 #define MECC_ERR_STATUS_ADDR_ERR2_MASK           (0x4000U)
54975 #define MECC_ERR_STATUS_ADDR_ERR2_SHIFT          (14U)
54976 /*! ADDR_ERR2 - OCRAM Access Error On Bank2
54977  *  0b0..OCRAM access error does not happen on OCRAM bank2.
54978  *  0b1..OCRAM access error happens on OCRAM bank2.
54979  */
54980 #define MECC_ERR_STATUS_ADDR_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
54981 
54982 #define MECC_ERR_STATUS_ADDR_ERR3_MASK           (0x8000U)
54983 #define MECC_ERR_STATUS_ADDR_ERR3_SHIFT          (15U)
54984 /*! ADDR_ERR3 - OCRAM Access Error On Bank3
54985  *  0b0..OCRAM access error does not happen on OCRAM bank3.
54986  *  0b1..OCRAM access error happens on OCRAM bank3.
54987  */
54988 #define MECC_ERR_STATUS_ADDR_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
54989 /*! @} */
54990 
54991 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
54992 /*! @{ */
54993 
54994 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
54995 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
54996 /*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0
54997  *  0b0..Disabled
54998  *  0b1..Enabled
54999  */
55000 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
55001 
55002 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
55003 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
55004 /*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1
55005  *  0b0..Disabled
55006  *  0b1..Enabled
55007  */
55008 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
55009 
55010 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
55011 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
55012 /*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2
55013  *  0b0..Disabled
55014  *  0b1..Enabled
55015  */
55016 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
55017 
55018 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
55019 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
55020 /*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3
55021  *  0b0..Disabled
55022  *  0b1..Enabled
55023  */
55024 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
55025 
55026 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
55027 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
55028 /*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0
55029  *  0b0..Disabled
55030  *  0b1..Enabled
55031  */
55032 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
55033 
55034 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
55035 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
55036 /*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1
55037  *  0b0..Disabled
55038  *  0b1..Enabled
55039  */
55040 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
55041 
55042 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
55043 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
55044 /*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2
55045  *  0b0..Disabled
55046  *  0b1..Enabled
55047  */
55048 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
55049 
55050 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
55051 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
55052 /*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3
55053  *  0b0..Disabled
55054  *  0b1..Enabled
55055  */
55056 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
55057 
55058 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK  (0x100U)
55059 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
55060 /*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0
55061  *  0b0..Disabled
55062  *  0b1..Enabled
55063  */
55064 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
55065 
55066 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK  (0x200U)
55067 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
55068 /*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1
55069  *  0b0..Disabled
55070  *  0b1..Enabled
55071  */
55072 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
55073 
55074 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK  (0x400U)
55075 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
55076 /*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2
55077  *  0b0..Disabled
55078  *  0b1..Enabled
55079  */
55080 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
55081 
55082 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK  (0x800U)
55083 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
55084 /*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3
55085  *  0b0..Disabled
55086  *  0b1..Enabled
55087  */
55088 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
55089 
55090 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK  (0x1000U)
55091 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
55092 /*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0
55093  *  0b0..Disabled
55094  *  0b1..Enabled
55095  */
55096 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
55097 
55098 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK  (0x2000U)
55099 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
55100 /*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1
55101  *  0b0..Disabled
55102  *  0b1..Enabled
55103  */
55104 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
55105 
55106 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK  (0x4000U)
55107 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
55108 /*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2
55109  *  0b0..Disabled
55110  *  0b1..Enabled
55111  */
55112 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
55113 
55114 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK  (0x8000U)
55115 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
55116 /*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3
55117  *  0b0..Disabled
55118  *  0b1..Enabled
55119  */
55120 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
55121 /*! @} */
55122 
55123 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
55124 /*! @{ */
55125 
55126 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK  (0x1U)
55127 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
55128 /*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0
55129  *  0b0..Disabled
55130  *  0b1..Enabled
55131  */
55132 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
55133 
55134 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK  (0x2U)
55135 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
55136 /*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1
55137  *  0b0..Disabled
55138  *  0b1..Enabled
55139  */
55140 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
55141 
55142 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK  (0x4U)
55143 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
55144 /*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2
55145  *  0b0..Disabled
55146  *  0b1..Enabled
55147  */
55148 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
55149 
55150 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK  (0x8U)
55151 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
55152 /*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3
55153  *  0b0..Disabled
55154  *  0b1..Enabled
55155  */
55156 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
55157 
55158 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK   (0x10U)
55159 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT  (4U)
55160 /*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0
55161  *  0b0..Disabled
55162  *  0b1..Enabled
55163  */
55164 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
55165 
55166 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK   (0x20U)
55167 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT  (5U)
55168 /*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1
55169  *  0b0..Disabled
55170  *  0b1..Enabled
55171  */
55172 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
55173 
55174 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK   (0x40U)
55175 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT  (6U)
55176 /*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2
55177  *  0b0..Disabled
55178  *  0b1..Enabled
55179  */
55180 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
55181 
55182 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK   (0x80U)
55183 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT  (7U)
55184 /*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3
55185  *  0b0..Disabled
55186  *  0b1..Enabled
55187  */
55188 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
55189 
55190 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK    (0x100U)
55191 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT   (8U)
55192 /*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0
55193  *  0b0..Disabled
55194  *  0b1..Enabled
55195  */
55196 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
55197 
55198 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK    (0x200U)
55199 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT   (9U)
55200 /*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1
55201  *  0b0..Disabled
55202  *  0b1..Enabled
55203  */
55204 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
55205 
55206 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK    (0x400U)
55207 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT   (10U)
55208 /*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2
55209  *  0b0..Disabled
55210  *  0b1..Enabled
55211  */
55212 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
55213 
55214 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK    (0x800U)
55215 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT   (11U)
55216 /*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3
55217  *  0b0..Disabled
55218  *  0b1..Enabled
55219  */
55220 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
55221 
55222 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK    (0x1000U)
55223 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT   (12U)
55224 /*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0
55225  *  0b0..Disabled
55226  *  0b1..Enabled
55227  */
55228 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
55229 
55230 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK    (0x2000U)
55231 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT   (13U)
55232 /*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1
55233  *  0b0..Disabled
55234  *  0b1..Enabled
55235  */
55236 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
55237 
55238 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK    (0x4000U)
55239 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT   (14U)
55240 /*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2
55241  *  0b0..Disabled
55242  *  0b1..Enabled
55243  */
55244 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
55245 
55246 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK    (0x8000U)
55247 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT   (15U)
55248 /*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3
55249  *  0b0..Disabled
55250  *  0b1..Enabled
55251  */
55252 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
55253 /*! @} */
55254 
55255 /*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
55256 /*! @{ */
55257 
55258 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55259 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
55260 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
55261 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
55262 /*! @} */
55263 
55264 /*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
55265 /*! @{ */
55266 
55267 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55268 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
55269 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
55270 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
55271 /*! @} */
55272 
55273 /*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
55274 /*! @{ */
55275 
55276 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK       (0xFFU)
55277 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT      (0U)
55278 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
55279 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
55280 /*! @} */
55281 
55282 /*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
55283 /*! @{ */
55284 
55285 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55286 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
55287 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
55288 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
55289 /*! @} */
55290 
55291 /*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
55292 /*! @{ */
55293 
55294 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55295 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
55296 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
55297 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
55298 /*! @} */
55299 
55300 /*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
55301 /*! @{ */
55302 
55303 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK       (0xFFU)
55304 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT      (0U)
55305 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
55306 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
55307 /*! @} */
55308 
55309 /*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
55310 /*! @{ */
55311 
55312 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55313 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
55314 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
55315 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
55316 /*! @} */
55317 
55318 /*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
55319 /*! @{ */
55320 
55321 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55322 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
55323 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
55324 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
55325 /*! @} */
55326 
55327 /*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
55328 /*! @{ */
55329 
55330 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK       (0xFFU)
55331 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT      (0U)
55332 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
55333 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
55334 /*! @} */
55335 
55336 /*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
55337 /*! @{ */
55338 
55339 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55340 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
55341 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
55342 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
55343 /*! @} */
55344 
55345 /*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
55346 /*! @{ */
55347 
55348 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
55349 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
55350 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
55351 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
55352 /*! @} */
55353 
55354 /*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
55355 /*! @{ */
55356 
55357 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK       (0xFFU)
55358 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT      (0U)
55359 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
55360 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
55361 /*! @} */
55362 
55363 /*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */
55364 /*! @{ */
55365 
55366 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
55367 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
55368 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0 */
55369 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
55370 
55371 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55372 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
55373 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0 */
55374 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55375 /*! @} */
55376 
55377 /*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
55378 /*! @{ */
55379 
55380 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55381 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
55382 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
55383 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
55384 /*! @} */
55385 
55386 /*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
55387 /*! @{ */
55388 
55389 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55390 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
55391 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
55392 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
55393 /*! @} */
55394 
55395 /*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */
55396 /*! @{ */
55397 
55398 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55399 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
55400 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0 */
55401 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
55402 /*! @} */
55403 
55404 /*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */
55405 /*! @{ */
55406 
55407 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55408 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
55409 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0 */
55410 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
55411 /*! @} */
55412 
55413 /*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */
55414 /*! @{ */
55415 
55416 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
55417 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
55418 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1 */
55419 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
55420 
55421 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55422 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
55423 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1 */
55424 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55425 /*! @} */
55426 
55427 /*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
55428 /*! @{ */
55429 
55430 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55431 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
55432 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
55433 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
55434 /*! @} */
55435 
55436 /*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
55437 /*! @{ */
55438 
55439 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55440 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
55441 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
55442 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
55443 /*! @} */
55444 
55445 /*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */
55446 /*! @{ */
55447 
55448 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55449 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
55450 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1 */
55451 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
55452 /*! @} */
55453 
55454 /*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */
55455 /*! @{ */
55456 
55457 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55458 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
55459 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1 */
55460 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
55461 /*! @} */
55462 
55463 /*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */
55464 /*! @{ */
55465 
55466 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
55467 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
55468 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2 */
55469 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
55470 
55471 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55472 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
55473 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2 */
55474 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55475 /*! @} */
55476 
55477 /*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
55478 /*! @{ */
55479 
55480 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55481 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
55482 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
55483 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
55484 /*! @} */
55485 
55486 /*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
55487 /*! @{ */
55488 
55489 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55490 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
55491 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
55492 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
55493 /*! @} */
55494 
55495 /*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */
55496 /*! @{ */
55497 
55498 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55499 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
55500 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2 */
55501 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
55502 /*! @} */
55503 
55504 /*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */
55505 /*! @{ */
55506 
55507 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55508 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
55509 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2 */
55510 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
55511 /*! @} */
55512 
55513 /*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */
55514 /*! @{ */
55515 
55516 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
55517 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
55518 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3 */
55519 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
55520 
55521 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55522 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
55523 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3 */
55524 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55525 /*! @} */
55526 
55527 /*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
55528 /*! @{ */
55529 
55530 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55531 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
55532 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
55533 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
55534 /*! @} */
55535 
55536 /*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
55537 /*! @{ */
55538 
55539 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
55540 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
55541 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
55542 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
55543 /*! @} */
55544 
55545 /*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */
55546 /*! @{ */
55547 
55548 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55549 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
55550 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3 */
55551 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
55552 /*! @} */
55553 
55554 /*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */
55555 /*! @{ */
55556 
55557 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
55558 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
55559 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3 */
55560 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
55561 /*! @} */
55562 
55563 /*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */
55564 /*! @{ */
55565 
55566 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
55567 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
55568 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0 */
55569 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
55570 
55571 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55572 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
55573 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0 */
55574 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55575 /*! @} */
55576 
55577 /*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
55578 /*! @{ */
55579 
55580 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55581 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
55582 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
55583 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
55584 /*! @} */
55585 
55586 /*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
55587 /*! @{ */
55588 
55589 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55590 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
55591 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
55592 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
55593 /*! @} */
55594 
55595 /*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */
55596 /*! @{ */
55597 
55598 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
55599 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
55600 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1 */
55601 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
55602 
55603 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55604 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
55605 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1 */
55606 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55607 /*! @} */
55608 
55609 /*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
55610 /*! @{ */
55611 
55612 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55613 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
55614 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
55615 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
55616 /*! @} */
55617 
55618 /*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
55619 /*! @{ */
55620 
55621 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55622 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
55623 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
55624 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
55625 /*! @} */
55626 
55627 /*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */
55628 /*! @{ */
55629 
55630 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
55631 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
55632 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2 */
55633 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
55634 
55635 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55636 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
55637 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2 */
55638 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55639 /*! @} */
55640 
55641 /*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
55642 /*! @{ */
55643 
55644 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55645 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
55646 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
55647 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
55648 /*! @} */
55649 
55650 /*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
55651 /*! @{ */
55652 
55653 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55654 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
55655 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
55656 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
55657 /*! @} */
55658 
55659 /*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */
55660 /*! @{ */
55661 
55662 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
55663 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
55664 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3 */
55665 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
55666 
55667 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55668 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
55669 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3 */
55670 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)  /* Merged from fields with different position or width, of widths (18, 19), largest definition used */
55671 /*! @} */
55672 
55673 /*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
55674 /*! @{ */
55675 
55676 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55677 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
55678 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
55679 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
55680 /*! @} */
55681 
55682 /*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
55683 /*! @{ */
55684 
55685 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
55686 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
55687 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
55688 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
55689 /*! @} */
55690 
55691 /*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */
55692 /*! @{ */
55693 
55694 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK  (0x1U)
55695 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
55696 /*! READ_DATA_WAIT_EN - Read Data Wait Enable
55697  *  0b0..Disable.
55698  *  0b1..Enable.
55699  */
55700 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
55701 
55702 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK  (0x2U)
55703 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
55704 /*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable
55705  *  0b0..Disable.
55706  *  0b1..Enable.
55707  */
55708 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
55709 
55710 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
55711 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
55712 /*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable
55713  *  0b0..Disable.
55714  *  0b1..Enable.
55715  */
55716 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
55717 
55718 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
55719 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
55720 /*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable
55721  *  0b0..Disable.
55722  *  0b1..Enable.
55723  */
55724 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
55725 
55726 #define MECC_PIPE_ECC_EN_ECC_EN_MASK             (0x10U)
55727 #define MECC_PIPE_ECC_EN_ECC_EN_SHIFT            (4U)
55728 /*! ECC_EN - ECC Function Enable
55729  *  0b0..Disable.
55730  *  0b1..Enable.
55731  */
55732 #define MECC_PIPE_ECC_EN_ECC_EN(x)               (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
55733 /*! @} */
55734 
55735 /*! @name PENDING_STAT - Pending Status */
55736 /*! @{ */
55737 
55738 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
55739 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
55740 /*! READ_DATA_WAIT_PENDING - Read Data Wait Pending
55741  *  0b0..No update pending status for READ_DATA_WAIT_EN.
55742  *  0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
55743  */
55744 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
55745 
55746 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
55747 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
55748 /*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending
55749  *  0b0..No update pending status for READ_ADDR_PIPE_EN.
55750  *  0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
55751  */
55752 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
55753 
55754 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
55755 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
55756 /*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending
55757  *  0b0..No update pending status for WRITE_DATA_PIPE_EN.
55758  *  0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
55759  */
55760 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
55761 
55762 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
55763 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
55764 /*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending
55765  *  0b0..No update pending status for WRITE_ADDR_PIPE_EN.
55766  *  0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
55767  */
55768 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)
55769 /*! @} */
55770 
55771 
55772 /*!
55773  * @}
55774  */ /* end of group MECC_Register_Masks */
55775 
55776 
55777 /* MECC - Peripheral instance base addresses */
55778 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
55779   /** Peripheral MECC1 base address */
55780   #define MECC1_BASE                               (0x52920000u)
55781   /** Peripheral MECC1 base address */
55782   #define MECC1_BASE_NS                            (0x42920000u)
55783   /** Peripheral MECC1 base pointer */
55784   #define MECC1                                    ((MECC_Type *)MECC1_BASE)
55785   /** Peripheral MECC1 base pointer */
55786   #define MECC1_NS                                 ((MECC_Type *)MECC1_BASE_NS)
55787   /** Peripheral MECC2 base address */
55788   #define MECC2_BASE                               (0x52930000u)
55789   /** Peripheral MECC2 base address */
55790   #define MECC2_BASE_NS                            (0x42930000u)
55791   /** Peripheral MECC2 base pointer */
55792   #define MECC2                                    ((MECC_Type *)MECC2_BASE)
55793   /** Peripheral MECC2 base pointer */
55794   #define MECC2_NS                                 ((MECC_Type *)MECC2_BASE_NS)
55795   /** Array initializer of MECC peripheral base addresses */
55796   #define MECC_BASE_ADDRS                          { 0u, MECC1_BASE, MECC2_BASE }
55797   /** Array initializer of MECC peripheral base pointers */
55798   #define MECC_BASE_PTRS                           { (MECC_Type *)0u, MECC1, MECC2 }
55799   /** Array initializer of MECC peripheral base addresses */
55800   #define MECC_BASE_ADDRS_NS                       { 0u, MECC1_BASE_NS, MECC2_BASE_NS }
55801   /** Array initializer of MECC peripheral base pointers */
55802   #define MECC_BASE_PTRS_NS                        { (MECC_Type *)0u, MECC1_NS, MECC2_NS }
55803 #else
55804   /** Peripheral MECC1 base address */
55805   #define MECC1_BASE                               (0x42920000u)
55806   /** Peripheral MECC1 base pointer */
55807   #define MECC1                                    ((MECC_Type *)MECC1_BASE)
55808   /** Peripheral MECC2 base address */
55809   #define MECC2_BASE                               (0x42930000u)
55810   /** Peripheral MECC2 base pointer */
55811   #define MECC2                                    ((MECC_Type *)MECC2_BASE)
55812   /** Array initializer of MECC peripheral base addresses */
55813   #define MECC_BASE_ADDRS                          { 0u, MECC1_BASE, MECC2_BASE }
55814   /** Array initializer of MECC peripheral base pointers */
55815   #define MECC_BASE_PTRS                           { (MECC_Type *)0u, MECC1, MECC2 }
55816 #endif
55817 
55818 /*!
55819  * @}
55820  */ /* end of group MECC_Peripheral_Access_Layer */
55821 
55822 
55823 /* ----------------------------------------------------------------------------
55824    -- MSGINTR Peripheral Access Layer
55825    ---------------------------------------------------------------------------- */
55826 
55827 /*!
55828  * @addtogroup MSGINTR_Peripheral_Access_Layer MSGINTR Peripheral Access Layer
55829  * @{
55830  */
55831 
55832 /** MSGINTR - Register Layout Typedef */
55833 typedef struct {
55834   struct {                                         /* offset: 0x0, array step: 0x8 */
55835     __O  uint32_t MSIIR;                             /**< Message Signaled Interrupt Index Register 0..Message Signaled Interrupt Index Register 2, array offset: 0x0, array step: 0x8 */
55836     __I  uint32_t MSIR;                              /**< Message Signaled Interrupt Register 0..Message Signaled Interrupt Register 2, array offset: 0x4, array step: 0x8 */
55837   } MSI[3];
55838 } MSGINTR_Type;
55839 
55840 /* ----------------------------------------------------------------------------
55841    -- MSGINTR Register Masks
55842    ---------------------------------------------------------------------------- */
55843 
55844 /*!
55845  * @addtogroup MSGINTR_Register_Masks MSGINTR Register Masks
55846  * @{
55847  */
55848 
55849 /*! @name MSIIR - Message Signaled Interrupt Index Register 0..Message Signaled Interrupt Index Register 2 */
55850 /*! @{ */
55851 
55852 #define MSGINTR_MSIIR_IBS_MASK                   (0x1FU)
55853 #define MSGINTR_MSIIR_IBS_SHIFT                  (0U)
55854 #define MSGINTR_MSIIR_IBS(x)                     (((uint32_t)(((uint32_t)(x)) << MSGINTR_MSIIR_IBS_SHIFT)) & MSGINTR_MSIIR_IBS_MASK)
55855 /*! @} */
55856 
55857 /* The count of MSGINTR_MSIIR */
55858 #define MSGINTR_MSIIR_COUNT                      (3U)
55859 
55860 /*! @name MSIR - Message Signaled Interrupt Register 0..Message Signaled Interrupt Register 2 */
55861 /*! @{ */
55862 
55863 #define MSGINTR_MSIR_SHn_MASK                    (0xFFFFFFFFU)
55864 #define MSGINTR_MSIR_SHn_SHIFT                   (0U)
55865 #define MSGINTR_MSIR_SHn(x)                      (((uint32_t)(((uint32_t)(x)) << MSGINTR_MSIR_SHn_SHIFT)) & MSGINTR_MSIR_SHn_MASK)
55866 /*! @} */
55867 
55868 /* The count of MSGINTR_MSIR */
55869 #define MSGINTR_MSIR_COUNT                       (3U)
55870 
55871 
55872 /*!
55873  * @}
55874  */ /* end of group MSGINTR_Register_Masks */
55875 
55876 
55877 /* MSGINTR - Peripheral instance base addresses */
55878 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
55879   /** Peripheral MSGINTR1 base address */
55880   #define MSGINTR1_BASE                            (0x528A0000u)
55881   /** Peripheral MSGINTR1 base address */
55882   #define MSGINTR1_BASE_NS                         (0x428A0000u)
55883   /** Peripheral MSGINTR1 base pointer */
55884   #define MSGINTR1                                 ((MSGINTR_Type *)MSGINTR1_BASE)
55885   /** Peripheral MSGINTR1 base pointer */
55886   #define MSGINTR1_NS                              ((MSGINTR_Type *)MSGINTR1_BASE_NS)
55887   /** Peripheral MSGINTR2 base address */
55888   #define MSGINTR2_BASE                            (0x528B0000u)
55889   /** Peripheral MSGINTR2 base address */
55890   #define MSGINTR2_BASE_NS                         (0x428B0000u)
55891   /** Peripheral MSGINTR2 base pointer */
55892   #define MSGINTR2                                 ((MSGINTR_Type *)MSGINTR2_BASE)
55893   /** Peripheral MSGINTR2 base pointer */
55894   #define MSGINTR2_NS                              ((MSGINTR_Type *)MSGINTR2_BASE_NS)
55895   /** Peripheral MSGINTR3 base address */
55896   #define MSGINTR3_BASE                            (0x528C0000u)
55897   /** Peripheral MSGINTR3 base address */
55898   #define MSGINTR3_BASE_NS                         (0x428C0000u)
55899   /** Peripheral MSGINTR3 base pointer */
55900   #define MSGINTR3                                 ((MSGINTR_Type *)MSGINTR3_BASE)
55901   /** Peripheral MSGINTR3 base pointer */
55902   #define MSGINTR3_NS                              ((MSGINTR_Type *)MSGINTR3_BASE_NS)
55903   /** Peripheral MSGINTR4 base address */
55904   #define MSGINTR4_BASE                            (0x528D0000u)
55905   /** Peripheral MSGINTR4 base address */
55906   #define MSGINTR4_BASE_NS                         (0x428D0000u)
55907   /** Peripheral MSGINTR4 base pointer */
55908   #define MSGINTR4                                 ((MSGINTR_Type *)MSGINTR4_BASE)
55909   /** Peripheral MSGINTR4 base pointer */
55910   #define MSGINTR4_NS                              ((MSGINTR_Type *)MSGINTR4_BASE_NS)
55911   /** Peripheral MSGINTR5 base address */
55912   #define MSGINTR5_BASE                            (0x528E0000u)
55913   /** Peripheral MSGINTR5 base address */
55914   #define MSGINTR5_BASE_NS                         (0x428E0000u)
55915   /** Peripheral MSGINTR5 base pointer */
55916   #define MSGINTR5                                 ((MSGINTR_Type *)MSGINTR5_BASE)
55917   /** Peripheral MSGINTR5 base pointer */
55918   #define MSGINTR5_NS                              ((MSGINTR_Type *)MSGINTR5_BASE_NS)
55919   /** Peripheral MSGINTR6 base address */
55920   #define MSGINTR6_BASE                            (0x528F0000u)
55921   /** Peripheral MSGINTR6 base address */
55922   #define MSGINTR6_BASE_NS                         (0x428F0000u)
55923   /** Peripheral MSGINTR6 base pointer */
55924   #define MSGINTR6                                 ((MSGINTR_Type *)MSGINTR6_BASE)
55925   /** Peripheral MSGINTR6 base pointer */
55926   #define MSGINTR6_NS                              ((MSGINTR_Type *)MSGINTR6_BASE_NS)
55927   /** Array initializer of MSGINTR peripheral base addresses */
55928   #define MSGINTR_BASE_ADDRS                       { 0u, MSGINTR1_BASE, MSGINTR2_BASE, MSGINTR3_BASE, MSGINTR4_BASE, MSGINTR5_BASE, MSGINTR6_BASE }
55929   /** Array initializer of MSGINTR peripheral base pointers */
55930   #define MSGINTR_BASE_PTRS                        { (MSGINTR_Type *)0u, MSGINTR1, MSGINTR2, MSGINTR3, MSGINTR4, MSGINTR5, MSGINTR6 }
55931   /** Array initializer of MSGINTR peripheral base addresses */
55932   #define MSGINTR_BASE_ADDRS_NS                    { 0u, MSGINTR1_BASE_NS, MSGINTR2_BASE_NS, MSGINTR3_BASE_NS, MSGINTR4_BASE_NS, MSGINTR5_BASE_NS, MSGINTR6_BASE_NS }
55933   /** Array initializer of MSGINTR peripheral base pointers */
55934   #define MSGINTR_BASE_PTRS_NS                     { (MSGINTR_Type *)0u, MSGINTR1_NS, MSGINTR2_NS, MSGINTR3_NS, MSGINTR4_NS, MSGINTR5_NS, MSGINTR6_NS }
55935 #else
55936   /** Peripheral MSGINTR1 base address */
55937   #define MSGINTR1_BASE                            (0x428A0000u)
55938   /** Peripheral MSGINTR1 base pointer */
55939   #define MSGINTR1                                 ((MSGINTR_Type *)MSGINTR1_BASE)
55940   /** Peripheral MSGINTR2 base address */
55941   #define MSGINTR2_BASE                            (0x428B0000u)
55942   /** Peripheral MSGINTR2 base pointer */
55943   #define MSGINTR2                                 ((MSGINTR_Type *)MSGINTR2_BASE)
55944   /** Peripheral MSGINTR3 base address */
55945   #define MSGINTR3_BASE                            (0x428C0000u)
55946   /** Peripheral MSGINTR3 base pointer */
55947   #define MSGINTR3                                 ((MSGINTR_Type *)MSGINTR3_BASE)
55948   /** Peripheral MSGINTR4 base address */
55949   #define MSGINTR4_BASE                            (0x428D0000u)
55950   /** Peripheral MSGINTR4 base pointer */
55951   #define MSGINTR4                                 ((MSGINTR_Type *)MSGINTR4_BASE)
55952   /** Peripheral MSGINTR5 base address */
55953   #define MSGINTR5_BASE                            (0x428E0000u)
55954   /** Peripheral MSGINTR5 base pointer */
55955   #define MSGINTR5                                 ((MSGINTR_Type *)MSGINTR5_BASE)
55956   /** Peripheral MSGINTR6 base address */
55957   #define MSGINTR6_BASE                            (0x428F0000u)
55958   /** Peripheral MSGINTR6 base pointer */
55959   #define MSGINTR6                                 ((MSGINTR_Type *)MSGINTR6_BASE)
55960   /** Array initializer of MSGINTR peripheral base addresses */
55961   #define MSGINTR_BASE_ADDRS                       { 0u, MSGINTR1_BASE, MSGINTR2_BASE, MSGINTR3_BASE, MSGINTR4_BASE, MSGINTR5_BASE, MSGINTR6_BASE }
55962   /** Array initializer of MSGINTR peripheral base pointers */
55963   #define MSGINTR_BASE_PTRS                        { (MSGINTR_Type *)0u, MSGINTR1, MSGINTR2, MSGINTR3, MSGINTR4, MSGINTR5, MSGINTR6 }
55964 #endif
55965 
55966 /*!
55967  * @}
55968  */ /* end of group MSGINTR_Peripheral_Access_Layer */
55969 
55970 
55971 /* ----------------------------------------------------------------------------
55972    -- MU Peripheral Access Layer
55973    ---------------------------------------------------------------------------- */
55974 
55975 /*!
55976  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
55977  * @{
55978  */
55979 
55980 /** MU - Register Layout Typedef */
55981 typedef struct {
55982   __I  uint32_t VER;                               /**< Version ID, offset: 0x0 */
55983   __I  uint32_t PAR;                               /**< Parameter, offset: 0x4 */
55984   __IO uint32_t CR;                                /**< Control, offset: 0x8 */
55985   __IO uint32_t SR;                                /**< Status, offset: 0xC */
55986        uint32_t CCR0;                              /**< Core Control 0, offset: 0x10 */
55987        uint32_t CIER0;                             /**< Core Interrupt Enable 0, offset: 0x14 */
55988        uint8_t RESERVED_0[232];
55989   __IO uint32_t FCR;                               /**< Flag Control, offset: 0x100 */
55990   __I  uint32_t FSR;                               /**< Flag Status, offset: 0x104 */
55991        uint8_t RESERVED_1[8];
55992   __IO uint32_t GIER;                              /**< General-Purpose Interrupt Enable, offset: 0x110 */
55993   __IO uint32_t GCR;                               /**< General-Purpose Control, offset: 0x114 */
55994   __IO uint32_t GSR;                               /**< General-purpose Status, offset: 0x118 */
55995        uint8_t RESERVED_2[4];
55996   __IO uint32_t TCR;                               /**< Transmit Control, offset: 0x120 */
55997   __I  uint32_t TSR;                               /**< Transmit Status, offset: 0x124 */
55998   __IO uint32_t RCR;                               /**< Receive Control, offset: 0x128 */
55999   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x12C */
56000        uint8_t RESERVED_3[208];
56001   __O  uint32_t TR[4];                             /**< Transmit, array offset: 0x200, array step: 0x4 */
56002        uint8_t RESERVED_4[112];
56003   __I  uint32_t RR[4];                             /**< Receive, array offset: 0x280, array step: 0x4 */
56004 } MU_Type;
56005 
56006 /* ----------------------------------------------------------------------------
56007    -- MU Register Masks
56008    ---------------------------------------------------------------------------- */
56009 
56010 /*!
56011  * @addtogroup MU_Register_Masks MU Register Masks
56012  * @{
56013  */
56014 
56015 /*! @name VER - Version ID */
56016 /*! @{ */
56017 
56018 #define MU_VER_FEATURE_MASK                      (0xFFFFU)
56019 #define MU_VER_FEATURE_SHIFT                     (0U)
56020 /*! FEATURE - Feature Set Number */
56021 #define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
56022 
56023 #define MU_VER_MINOR_MASK                        (0xFF0000U)
56024 #define MU_VER_MINOR_SHIFT                       (16U)
56025 /*! MINOR - Minor Version Number */
56026 #define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
56027 
56028 #define MU_VER_MAJOR_MASK                        (0xFF000000U)
56029 #define MU_VER_MAJOR_SHIFT                       (24U)
56030 /*! MAJOR - Major Version Number */
56031 #define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
56032 /*! @} */
56033 
56034 /*! @name PAR - Parameter */
56035 /*! @{ */
56036 
56037 #define MU_PAR_TR_NUM_MASK                       (0xFFU)
56038 #define MU_PAR_TR_NUM_SHIFT                      (0U)
56039 /*! TR_NUM - Transmit Register Number */
56040 #define MU_PAR_TR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK)
56041 
56042 #define MU_PAR_RR_NUM_MASK                       (0xFF00U)
56043 #define MU_PAR_RR_NUM_SHIFT                      (8U)
56044 /*! RR_NUM - Receive Register Number */
56045 #define MU_PAR_RR_NUM(x)                         (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK)
56046 
56047 #define MU_PAR_GIR_NUM_MASK                      (0xFF0000U)
56048 #define MU_PAR_GIR_NUM_SHIFT                     (16U)
56049 /*! GIR_NUM - General-Purpose Interrupt Request Number */
56050 #define MU_PAR_GIR_NUM(x)                        (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK)
56051 
56052 #define MU_PAR_FLAG_WIDTH_MASK                   (0xFF000000U)
56053 #define MU_PAR_FLAG_WIDTH_SHIFT                  (24U)
56054 /*! FLAG_WIDTH - Flag Width */
56055 #define MU_PAR_FLAG_WIDTH(x)                     (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK)
56056 /*! @} */
56057 
56058 /*! @name CR - Control */
56059 /*! @{ */
56060 
56061 #define MU_CR_MUR_MASK                           (0x1U)
56062 #define MU_CR_MUR_SHIFT                          (0U)
56063 /*! MUR - MU Reset
56064  *  0b0..Idle
56065  *  0b1..Reset
56066  */
56067 #define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
56068 
56069 #define MU_CR_MURIE_MASK                         (0x2U)
56070 #define MU_CR_MURIE_SHIFT                        (1U)
56071 /*! MURIE - MUA Reset Interrupt Enable
56072  *  0b0..Disable
56073  *  0b1..Enable
56074  */
56075 #define MU_CR_MURIE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK)
56076 /*! @} */
56077 
56078 /*! @name SR - Status */
56079 /*! @{ */
56080 
56081 #define MU_SR_MURS_MASK                          (0x1U)
56082 #define MU_SR_MURS_SHIFT                         (0U)
56083 /*! MURS - MUA and MUB Reset State
56084  *  0b0..Out of reset
56085  *  0b1..In reset
56086  */
56087 #define MU_SR_MURS(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK)
56088 
56089 #define MU_SR_MURIP_MASK                         (0x2U)
56090 #define MU_SR_MURIP_SHIFT                        (1U)
56091 /*! MURIP - MU Reset Interrupt Pending Flag
56092  *  0b0..Reset not issued
56093  *  0b1..Reset issued
56094  *  0b0..No effect
56095  *  0b1..Clear the flag
56096  */
56097 #define MU_SR_MURIP(x)                           (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK)
56098 
56099 #define MU_SR_EP_MASK                            (0x4U)
56100 #define MU_SR_EP_SHIFT                           (2U)
56101 /*! EP - MUA Side Event Pending
56102  *  0b0..Not pending
56103  *  0b1..Pending
56104  */
56105 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
56106 
56107 #define MU_SR_FUP_MASK                           (0x8U)
56108 #define MU_SR_FUP_SHIFT                          (3U)
56109 /*! FUP - MUA Flag Update Pending
56110  *  0b0..No pending update flags (initiated by MUA)
56111  *  0b1..Pending update flags (initiated by MUA)
56112  */
56113 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
56114 
56115 #define MU_SR_GIRP_MASK                          (0x10U)
56116 #define MU_SR_GIRP_SHIFT                         (4U)
56117 /*! GIRP - MUA General-Purpose Interrupt Pending
56118  *  0b0..No request sent
56119  *  0b1..Request sent
56120  */
56121 #define MU_SR_GIRP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK)
56122 
56123 #define MU_SR_TEP_MASK                           (0x20U)
56124 #define MU_SR_TEP_SHIFT                          (5U)
56125 /*! TEP - MUA Transmit Empty Pending
56126  *  0b0..Not pending; MUB is reading no Receive (RRn) register
56127  *  0b1..Pending; MUB is reading a Receive (RRn) register
56128  */
56129 #define MU_SR_TEP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK)
56130 
56131 #define MU_SR_RFP_MASK                           (0x40U)
56132 #define MU_SR_RFP_SHIFT                          (6U)
56133 /*! RFP - MUA Receive Full Pending
56134  *  0b0..Not pending; MUB is not writing to a Transmit register
56135  *  0b1..Pending; MUB is writing to a Transmit register
56136  */
56137 #define MU_SR_RFP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK)
56138 /*! @} */
56139 
56140 /*! @name FCR - Flag Control */
56141 /*! @{ */
56142 
56143 #define MU_FCR_F0_MASK                           (0x1U)
56144 #define MU_FCR_F0_SHIFT                          (0U)
56145 /*! F0 - MUA to MUB Flag
56146  *  0b0..Clear MUB_FSR[Fn]
56147  *  0b1..Set MUB_FSR[Fn]
56148  */
56149 #define MU_FCR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK)
56150 
56151 #define MU_FCR_F1_MASK                           (0x2U)
56152 #define MU_FCR_F1_SHIFT                          (1U)
56153 /*! F1 - MUA to MUB Flag
56154  *  0b0..Clear MUB_FSR[Fn]
56155  *  0b1..Set MUB_FSR[Fn]
56156  */
56157 #define MU_FCR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK)
56158 
56159 #define MU_FCR_F2_MASK                           (0x4U)
56160 #define MU_FCR_F2_SHIFT                          (2U)
56161 /*! F2 - MUA to MUB Flag
56162  *  0b0..Clear MUB_FSR[Fn]
56163  *  0b1..Set MUB_FSR[Fn]
56164  */
56165 #define MU_FCR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK)
56166 /*! @} */
56167 
56168 /*! @name FSR - Flag Status */
56169 /*! @{ */
56170 
56171 #define MU_FSR_F0_MASK                           (0x1U)
56172 #define MU_FSR_F0_SHIFT                          (0U)
56173 /*! F0 - MUB to MUA-Side Flag
56174  *  0b0..MUB_FCR[Fn] = 0
56175  *  0b1..MUB_FCR[Fn] = 1
56176  */
56177 #define MU_FSR_F0(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK)
56178 
56179 #define MU_FSR_F1_MASK                           (0x2U)
56180 #define MU_FSR_F1_SHIFT                          (1U)
56181 /*! F1 - MUB to MUA-Side Flag
56182  *  0b0..MUB_FCR[Fn] = 0
56183  *  0b1..MUB_FCR[Fn] = 1
56184  */
56185 #define MU_FSR_F1(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK)
56186 
56187 #define MU_FSR_F2_MASK                           (0x4U)
56188 #define MU_FSR_F2_SHIFT                          (2U)
56189 /*! F2 - MUB to MUA-Side Flag
56190  *  0b0..MUB_FCR[Fn] = 0
56191  *  0b1..MUB_FCR[Fn] = 1
56192  */
56193 #define MU_FSR_F2(x)                             (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK)
56194 /*! @} */
56195 
56196 /*! @name GIER - General-Purpose Interrupt Enable */
56197 /*! @{ */
56198 
56199 #define MU_GIER_GIE0_MASK                        (0x1U)
56200 #define MU_GIER_GIE0_SHIFT                       (0U)
56201 /*! GIE0 - MUA General-purpose Interrupt Enable
56202  *  0b0..Disable
56203  *  0b1..Enable
56204  */
56205 #define MU_GIER_GIE0(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK)
56206 
56207 #define MU_GIER_GIE1_MASK                        (0x2U)
56208 #define MU_GIER_GIE1_SHIFT                       (1U)
56209 /*! GIE1 - MUA General-purpose Interrupt Enable
56210  *  0b0..Disable
56211  *  0b1..Enable
56212  */
56213 #define MU_GIER_GIE1(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK)
56214 
56215 #define MU_GIER_GIE2_MASK                        (0x4U)
56216 #define MU_GIER_GIE2_SHIFT                       (2U)
56217 /*! GIE2 - MUA General-purpose Interrupt Enable
56218  *  0b0..Disable
56219  *  0b1..Enable
56220  */
56221 #define MU_GIER_GIE2(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK)
56222 
56223 #define MU_GIER_GIE3_MASK                        (0x8U)
56224 #define MU_GIER_GIE3_SHIFT                       (3U)
56225 /*! GIE3 - MUA General-purpose Interrupt Enable
56226  *  0b0..Disable
56227  *  0b1..Enable
56228  */
56229 #define MU_GIER_GIE3(x)                          (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK)
56230 /*! @} */
56231 
56232 /*! @name GCR - General-Purpose Control */
56233 /*! @{ */
56234 
56235 #define MU_GCR_GIR0_MASK                         (0x1U)
56236 #define MU_GCR_GIR0_SHIFT                        (0U)
56237 /*! GIR0 - MUA General-Purpose Interrupt Request
56238  *  0b0..Not requested
56239  *  0b1..Requested
56240  */
56241 #define MU_GCR_GIR0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK)
56242 
56243 #define MU_GCR_GIR1_MASK                         (0x2U)
56244 #define MU_GCR_GIR1_SHIFT                        (1U)
56245 /*! GIR1 - MUA General-Purpose Interrupt Request
56246  *  0b0..Not requested
56247  *  0b1..Requested
56248  */
56249 #define MU_GCR_GIR1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK)
56250 
56251 #define MU_GCR_GIR2_MASK                         (0x4U)
56252 #define MU_GCR_GIR2_SHIFT                        (2U)
56253 /*! GIR2 - MUA General-Purpose Interrupt Request
56254  *  0b0..Not requested
56255  *  0b1..Requested
56256  */
56257 #define MU_GCR_GIR2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK)
56258 
56259 #define MU_GCR_GIR3_MASK                         (0x8U)
56260 #define MU_GCR_GIR3_SHIFT                        (3U)
56261 /*! GIR3 - MUA General-Purpose Interrupt Request
56262  *  0b0..Not requested
56263  *  0b1..Requested
56264  */
56265 #define MU_GCR_GIR3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK)
56266 /*! @} */
56267 
56268 /*! @name GSR - General-purpose Status */
56269 /*! @{ */
56270 
56271 #define MU_GSR_GIP0_MASK                         (0x1U)
56272 #define MU_GSR_GIP0_SHIFT                        (0U)
56273 /*! GIP0 - MUA General-Purpose Interrupt Request Pending
56274  *  0b0..Not pending
56275  *  0b1..Pending
56276  *  0b0..No effect
56277  *  0b1..Clear the flag
56278  */
56279 #define MU_GSR_GIP0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK)
56280 
56281 #define MU_GSR_GIP1_MASK                         (0x2U)
56282 #define MU_GSR_GIP1_SHIFT                        (1U)
56283 /*! GIP1 - MUA General-Purpose Interrupt Request Pending
56284  *  0b0..Not pending
56285  *  0b1..Pending
56286  *  0b0..No effect
56287  *  0b1..Clear the flag
56288  */
56289 #define MU_GSR_GIP1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK)
56290 
56291 #define MU_GSR_GIP2_MASK                         (0x4U)
56292 #define MU_GSR_GIP2_SHIFT                        (2U)
56293 /*! GIP2 - MUA General-Purpose Interrupt Request Pending
56294  *  0b0..Not pending
56295  *  0b1..Pending
56296  *  0b0..No effect
56297  *  0b1..Clear the flag
56298  */
56299 #define MU_GSR_GIP2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK)
56300 
56301 #define MU_GSR_GIP3_MASK                         (0x8U)
56302 #define MU_GSR_GIP3_SHIFT                        (3U)
56303 /*! GIP3 - MUA General-Purpose Interrupt Request Pending
56304  *  0b0..Not pending
56305  *  0b1..Pending
56306  *  0b0..No effect
56307  *  0b1..Clear the flag
56308  */
56309 #define MU_GSR_GIP3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK)
56310 /*! @} */
56311 
56312 /*! @name TCR - Transmit Control */
56313 /*! @{ */
56314 
56315 #define MU_TCR_TIE0_MASK                         (0x1U)
56316 #define MU_TCR_TIE0_SHIFT                        (0U)
56317 /*! TIE0 - MUA Transmit Interrupt Enable
56318  *  0b0..Disable
56319  *  0b1..Enable
56320  */
56321 #define MU_TCR_TIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK)
56322 
56323 #define MU_TCR_TIE1_MASK                         (0x2U)
56324 #define MU_TCR_TIE1_SHIFT                        (1U)
56325 /*! TIE1 - MUA Transmit Interrupt Enable
56326  *  0b0..Disable
56327  *  0b1..Enable
56328  */
56329 #define MU_TCR_TIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK)
56330 
56331 #define MU_TCR_TIE2_MASK                         (0x4U)
56332 #define MU_TCR_TIE2_SHIFT                        (2U)
56333 /*! TIE2 - MUA Transmit Interrupt Enable
56334  *  0b0..Disable
56335  *  0b1..Enable
56336  */
56337 #define MU_TCR_TIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK)
56338 
56339 #define MU_TCR_TIE3_MASK                         (0x8U)
56340 #define MU_TCR_TIE3_SHIFT                        (3U)
56341 /*! TIE3 - MUA Transmit Interrupt Enable
56342  *  0b0..Disable
56343  *  0b1..Enable
56344  */
56345 #define MU_TCR_TIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK)
56346 /*! @} */
56347 
56348 /*! @name TSR - Transmit Status */
56349 /*! @{ */
56350 
56351 #define MU_TSR_TE0_MASK                          (0x1U)
56352 #define MU_TSR_TE0_SHIFT                         (0U)
56353 /*! TE0 - MUA Transmit Empty
56354  *  0b0..Not empty
56355  *  0b1..Empty
56356  */
56357 #define MU_TSR_TE0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK)
56358 
56359 #define MU_TSR_TE1_MASK                          (0x2U)
56360 #define MU_TSR_TE1_SHIFT                         (1U)
56361 /*! TE1 - MUA Transmit Empty
56362  *  0b0..Not empty
56363  *  0b1..Empty
56364  */
56365 #define MU_TSR_TE1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK)
56366 
56367 #define MU_TSR_TE2_MASK                          (0x4U)
56368 #define MU_TSR_TE2_SHIFT                         (2U)
56369 /*! TE2 - MUA Transmit Empty
56370  *  0b0..Not empty
56371  *  0b1..Empty
56372  */
56373 #define MU_TSR_TE2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK)
56374 
56375 #define MU_TSR_TE3_MASK                          (0x8U)
56376 #define MU_TSR_TE3_SHIFT                         (3U)
56377 /*! TE3 - MUA Transmit Empty
56378  *  0b0..Not empty
56379  *  0b1..Empty
56380  */
56381 #define MU_TSR_TE3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK)
56382 /*! @} */
56383 
56384 /*! @name RCR - Receive Control */
56385 /*! @{ */
56386 
56387 #define MU_RCR_RIE0_MASK                         (0x1U)
56388 #define MU_RCR_RIE0_SHIFT                        (0U)
56389 /*! RIE0 - MUA Receive Interrupt Enable
56390  *  0b0..Disable
56391  *  0b1..Enable
56392  */
56393 #define MU_RCR_RIE0(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK)
56394 
56395 #define MU_RCR_RIE1_MASK                         (0x2U)
56396 #define MU_RCR_RIE1_SHIFT                        (1U)
56397 /*! RIE1 - MUA Receive Interrupt Enable
56398  *  0b0..Disable
56399  *  0b1..Enable
56400  */
56401 #define MU_RCR_RIE1(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK)
56402 
56403 #define MU_RCR_RIE2_MASK                         (0x4U)
56404 #define MU_RCR_RIE2_SHIFT                        (2U)
56405 /*! RIE2 - MUA Receive Interrupt Enable
56406  *  0b0..Disable
56407  *  0b1..Enable
56408  */
56409 #define MU_RCR_RIE2(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK)
56410 
56411 #define MU_RCR_RIE3_MASK                         (0x8U)
56412 #define MU_RCR_RIE3_SHIFT                        (3U)
56413 /*! RIE3 - MUA Receive Interrupt Enable
56414  *  0b0..Disable
56415  *  0b1..Enable
56416  */
56417 #define MU_RCR_RIE3(x)                           (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK)
56418 /*! @} */
56419 
56420 /*! @name RSR - Receive Status */
56421 /*! @{ */
56422 
56423 #define MU_RSR_RF0_MASK                          (0x1U)
56424 #define MU_RSR_RF0_SHIFT                         (0U)
56425 /*! RF0 - MUA Receive Register Full
56426  *  0b0..Not full
56427  *  0b1..Full
56428  */
56429 #define MU_RSR_RF0(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK)
56430 
56431 #define MU_RSR_RF1_MASK                          (0x2U)
56432 #define MU_RSR_RF1_SHIFT                         (1U)
56433 /*! RF1 - MUA Receive Register Full
56434  *  0b0..Not full
56435  *  0b1..Full
56436  */
56437 #define MU_RSR_RF1(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK)
56438 
56439 #define MU_RSR_RF2_MASK                          (0x4U)
56440 #define MU_RSR_RF2_SHIFT                         (2U)
56441 /*! RF2 - MUA Receive Register Full
56442  *  0b0..Not full
56443  *  0b1..Full
56444  */
56445 #define MU_RSR_RF2(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK)
56446 
56447 #define MU_RSR_RF3_MASK                          (0x8U)
56448 #define MU_RSR_RF3_SHIFT                         (3U)
56449 /*! RF3 - MUA Receive Register Full
56450  *  0b0..Not full
56451  *  0b1..Full
56452  */
56453 #define MU_RSR_RF3(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK)
56454 /*! @} */
56455 
56456 /*! @name TR - Transmit */
56457 /*! @{ */
56458 
56459 #define MU_TR_TR_DATA_MASK                       (0xFFFFFFFFU)
56460 #define MU_TR_TR_DATA_SHIFT                      (0U)
56461 /*! TR_DATA - MUA Transmit Data */
56462 #define MU_TR_TR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK)
56463 /*! @} */
56464 
56465 /* The count of MU_TR */
56466 #define MU_TR_COUNT                              (4U)
56467 
56468 /*! @name RR - Receive */
56469 /*! @{ */
56470 
56471 #define MU_RR_RR_DATA_MASK                       (0xFFFFFFFFU)
56472 #define MU_RR_RR_DATA_SHIFT                      (0U)
56473 /*! RR_DATA - MUA Receive Data */
56474 #define MU_RR_RR_DATA(x)                         (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK)
56475 /*! @} */
56476 
56477 /* The count of MU_RR */
56478 #define MU_RR_COUNT                              (4U)
56479 
56480 
56481 /*!
56482  * @}
56483  */ /* end of group MU_Register_Masks */
56484 
56485 
56486 /* MU - Peripheral instance base addresses */
56487 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
56488   /** Peripheral MU1_MUA base address */
56489   #define MU1_MUA_BASE                             (0x54220000u)
56490   /** Peripheral MU1_MUA base address */
56491   #define MU1_MUA_BASE_NS                          (0x44220000u)
56492   /** Peripheral MU1_MUA base pointer */
56493   #define MU1_MUA                                  ((MU_Type *)MU1_MUA_BASE)
56494   /** Peripheral MU1_MUA base pointer */
56495   #define MU1_MUA_NS                               ((MU_Type *)MU1_MUA_BASE_NS)
56496   /** Peripheral MU2_MUA base address */
56497   #define MU2_MUA_BASE                             (0x52430000u)
56498   /** Peripheral MU2_MUA base address */
56499   #define MU2_MUA_BASE_NS                          (0x42430000u)
56500   /** Peripheral MU2_MUA base pointer */
56501   #define MU2_MUA                                  ((MU_Type *)MU2_MUA_BASE)
56502   /** Peripheral MU2_MUA base pointer */
56503   #define MU2_MUA_NS                               ((MU_Type *)MU2_MUA_BASE_NS)
56504   /** Array initializer of MU peripheral base addresses */
56505   #define MU_BASE_ADDRS                            { MU1_MUA_BASE, MU2_MUA_BASE }
56506   /** Array initializer of MU peripheral base pointers */
56507   #define MU_BASE_PTRS                             { MU1_MUA, MU2_MUA }
56508   /** Array initializer of MU peripheral base addresses */
56509   #define MU_BASE_ADDRS_NS                         { MU1_MUA_BASE_NS, MU2_MUA_BASE_NS }
56510   /** Array initializer of MU peripheral base pointers */
56511   #define MU_BASE_PTRS_NS                          { MU1_MUA_NS, MU2_MUA_NS }
56512 #else
56513   /** Peripheral MU1_MUA base address */
56514   #define MU1_MUA_BASE                             (0x44220000u)
56515   /** Peripheral MU1_MUA base pointer */
56516   #define MU1_MUA                                  ((MU_Type *)MU1_MUA_BASE)
56517   /** Peripheral MU2_MUA base address */
56518   #define MU2_MUA_BASE                             (0x42430000u)
56519   /** Peripheral MU2_MUA base pointer */
56520   #define MU2_MUA                                  ((MU_Type *)MU2_MUA_BASE)
56521   /** Array initializer of MU peripheral base addresses */
56522   #define MU_BASE_ADDRS                            { MU1_MUA_BASE, MU2_MUA_BASE }
56523   /** Array initializer of MU peripheral base pointers */
56524   #define MU_BASE_PTRS                             { MU1_MUA, MU2_MUA }
56525 #endif
56526 /** Interrupt vectors for the MU peripheral type */
56527 #define MU_IRQS                                  { MU1_IRQn, MU2_IRQn }
56528 
56529 /*!
56530  * @}
56531  */ /* end of group MU_Peripheral_Access_Layer */
56532 
56533 
56534 /* ----------------------------------------------------------------------------
56535    -- NETC_ENETC Peripheral Access Layer
56536    ---------------------------------------------------------------------------- */
56537 
56538 /*!
56539  * @addtogroup NETC_ENETC_Peripheral_Access_Layer NETC_ENETC Peripheral Access Layer
56540  * @{
56541  */
56542 
56543 /** NETC_ENETC - Register Layout Typedef */
56544 typedef struct {
56545   __I  uint32_t ECAPR0;                            /**< ENETC capability register 0, offset: 0x0 */
56546   __I  uint32_t ECAPR1;                            /**< ENETC capability register 1, offset: 0x4 */
56547   __I  uint32_t ECAPR2;                            /**< ENETC capability register 2, offset: 0x8 */
56548        uint8_t RESERVED_0[4];
56549   __IO uint32_t PMR;                               /**< Port mode register, offset: 0x10 */
56550        uint8_t RESERVED_1[108];
56551   __IO uint32_t PONVLANR;                          /**< Port outer native VLAN register, offset: 0x80 */
56552   __IO uint32_t PINVLANR;                          /**< Port inner native VLAN register, offset: 0x84 */
56553   __IO uint32_t PVCLCTR;                           /**< Port VLAN classification control register, offset: 0x88 */
56554        uint8_t RESERVED_2[16];
56555   __IO uint32_t PARCSCR;                           /**< Parser checksum configuration register, offset: 0x9C */
56556   __IO uint32_t PARCECR[4];                        /**< Parser custom Ethertype 0 configuration register..Parser custom Ethertype 3 configuration register, array offset: 0xA0, array step: 0x4 */
56557        uint8_t RESERVED_3[88];
56558   __IO uint32_t PPAUONTR;                          /**< Port pause ON threshold register, offset: 0x108 */
56559   __IO uint32_t PPAUOFFTR;                         /**< Port pause OFF threshold register, offset: 0x10C */
56560        uint8_t RESERVED_4[16];
56561   __I  uint32_t PRXMBER;                           /**< Port receive memory buffer entitlement register, offset: 0x120 */
56562   __I  uint32_t PRXMBLR;                           /**< Port receive memory buffer limit register, offset: 0x124 */
56563   __I  uint32_t PRXBCR;                            /**< Port receive buffer count register, offset: 0x128 */
56564   __I  uint32_t PRXBCHWMR;                         /**< Port receive buffer count high watermark register, offset: 0x12C */
56565        uint8_t RESERVED_5[16];
56566   struct {                                         /* offset: 0x140, array step: 0x10 */
56567     __I  uint32_t PICDRDCR;                          /**< Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register, array offset: 0x140, array step: 0x10 */
56568          uint8_t RESERVED_0[4];
56569     __I  uint32_t PICDRDCRRR;                        /**< Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register, array offset: 0x148, array step: 0x10 */
56570          uint8_t RESERVED_1[4];
56571   } PICDRADCR[4];
56572   __IO uint32_t PICPDSR;                           /**< Port ingress congestion priority discard status register, offset: 0x180 */
56573        uint8_t RESERVED_6[124];
56574   __IO uint32_t PSIPMMR;                           /**< Port station interface promiscuous MAC mode register, offset: 0x200 */
56575   __IO uint32_t PSIPVMR;                           /**< Port station interface promiscuous VLAN mode register, offset: 0x204 */
56576   __I  uint32_t PBFDSIR;                           /**< Port broadcast frames dropped due to MAC filtering register, offset: 0x208 */
56577   __I  uint32_t PFDMSAPR;                          /**< Port frame drop MAC source address pruning register, offset: 0x20C */
56578        uint8_t RESERVED_7[112];
56579   __I  uint32_t PSIMAFCAPR;                        /**< Port station interface MAC address filtering capability register, offset: 0x280 */
56580   __I  uint32_t PUFDMFR;                           /**< Port unicast frames dropped due to MAC filtering register, offset: 0x284 */
56581   __I  uint32_t PMFDMFR;                           /**< Port multicast frames dropped due to MAC filtering register, offset: 0x288 */
56582        uint8_t RESERVED_8[52];
56583   __I  uint32_t PSIVLANFCAPR;                      /**< Port station interface VLAN filtering capability register, offset: 0x2C0 */
56584   __IO uint32_t PSIVLANFMR;                        /**< Port station interface VLAN filtering mode register, offset: 0x2C4 */
56585        uint8_t RESERVED_9[8];
56586   __I  uint32_t PUFDVFR;                           /**< Port unicast frames dropped VLAN filtering register, offset: 0x2D0 */
56587   __I  uint32_t PMFDVFR;                           /**< Port multicast frames dropped VLAN filtering register, offset: 0x2D4 */
56588   __I  uint32_t PBFDVFR;                           /**< Port broadcast frames dropped VLAN filtering register, offset: 0x2D8 */
56589        uint8_t RESERVED_10[100];
56590   __IO uint32_t PLPMR;                             /**< Port low power mode register, offset: 0x340, available only on: ENETC0_BASE (missing on ENETC1_BASE) */
56591   __I  uint32_t PWOSR;                             /**< Port wake-on status register, offset: 0x344, available only on: ENETC0_BASE (missing on ENETC1_BASE) */
56592        uint8_t RESERVED_11[40];
56593   __IO uint32_t IPV2ICMPMR0;                       /**< Receive IPV to ICM priority mapping register 0, offset: 0x370 */
56594        uint8_t RESERVED_12[12];
56595   __IO uint32_t PRIO2TCMR0;                        /**< Transmit priority to traffic class mapping register 0, offset: 0x380 */
56596        uint8_t RESERVED_13[12];
56597   __IO uint32_t PTCTSDR[8];                        /**< Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register, array offset: 0x390, array step: 0x4 */
56598        uint8_t RESERVED_14[1104];
56599   __I  uint32_t SMCAPR;                            /**< Switch management capability register, offset: 0x800 */
56600        uint8_t RESERVED_15[124];
56601   __IO uint32_t SMHRBDRMR[15];                     /**< Switch management host reason 1 receive BD ring mapping register..Switch management host reason 15 receive BD ring mapping register, array offset: 0x880, array step: 0x4, available only on: ENETC1_BASE (missing on ENETC0_BASE) */
56602        uint8_t RESERVED_16[5956];
56603   struct {                                         /* offset: 0x2000, array step: 0x80 */
56604     __IO uint32_t PSIPMAR0;                          /**< Port station interface 0 primary MAC address register 0..Port station interface 1 primary MAC address register 0, array offset: 0x2000, array step: 0x80, irregular array, not all indices are valid */
56605     __IO uint32_t PSIPMAR1;                          /**< Port station interface 0 primary MAC address register 1..Port station interface 1 primary MAC address register 1, array offset: 0x2004, array step: 0x80, irregular array, not all indices are valid */
56606     __IO uint32_t PSIVLANR;                          /**< Port station interface 0 VLAN register..Port station interface 1 VLAN register, array offset: 0x2008, array step: 0x80, irregular array, not all indices are valid */
56607          uint8_t RESERVED_0[4];
56608     __IO uint32_t PSICFGR0;                          /**< Port station interface 0 configuration register 0..Port station interface 1 configuration register 0, array offset: 0x2010, array step: 0x80, irregular array, not all indices are valid */
56609     __IO uint32_t PSICFGR1;                          /**< Port station interface 1 configuration register 1, array offset: 0x2014, array step: 0x80, available only on: ENETC1_BASE (missing on ENETC0_BASE), valid indices: [1] */
56610     __IO uint32_t PSICFGR2;                          /**< Port station interface 0 configuration register 2..Port station interface 1 configuration register 2, array offset: 0x2018, array step: 0x80, irregular array, not all indices are valid */
56611          uint8_t RESERVED_1[20];
56612     __IO uint32_t PSIVMAFCFGR;                       /**< Port station interface 0 VSI MAC address filtering configuration register..Port station interface 1 VSI MAC address filtering configuration register, array offset: 0x2030, array step: 0x80, irregular array, not all indices are valid */
56613     __IO uint32_t PSIVLANFCFGR;                      /**< Port station interface 0 VLAN filtering configuration register..Port station interface 1 VLAN filtering configuration register, array offset: 0x2034, array step: 0x80, irregular array, not all indices are valid */
56614          uint8_t RESERVED_2[24];
56615     __IO uint32_t PSIUMHFR0;                         /**< Port station interface 0 unicast MAC hash filter register 0..Port station interface 1 unicast MAC hash filter register 0, array offset: 0x2050, array step: 0x80, irregular array, not all indices are valid */
56616     __IO uint32_t PSIUMHFR1;                         /**< Port station interface 0 unicast MAC hash filter register 1..Port station interface 1 unicast MAC hash filter register 1, array offset: 0x2054, array step: 0x80, irregular array, not all indices are valid */
56617     __IO uint32_t PSIMMHFR0;                         /**< Port station interface 0 multicast MAC hash filter register 0..Port station interface 1 multicast MAC hash filter register 0, array offset: 0x2058, array step: 0x80, irregular array, not all indices are valid */
56618     __IO uint32_t PSIMMHFR1;                         /**< Port station interface 0 multicast MAC hash filter register 1..Port station interface 1 multicast MAC hash filter register 1, array offset: 0x205C, array step: 0x80, irregular array, not all indices are valid */
56619     __IO uint32_t PSIVHFR0;                          /**< Port station interface 0 VLAN hash filter register 0..Port station interface 1 VLAN hash filter register 0, array offset: 0x2060, array step: 0x80, irregular array, not all indices are valid */
56620     __IO uint32_t PSIVHFR1;                          /**< Port station interface 0 VLAN hash filter register 1..Port station interface 1 VLAN hash filter register 1, array offset: 0x2064, array step: 0x80, irregular array, not all indices are valid */
56621          uint8_t RESERVED_3[24];
56622   } NUM_SI[2];
56623 } NETC_ENETC_Type;
56624 
56625 /* ----------------------------------------------------------------------------
56626    -- NETC_ENETC Register Masks
56627    ---------------------------------------------------------------------------- */
56628 
56629 /*!
56630  * @addtogroup NETC_ENETC_Register_Masks NETC_ENETC Register Masks
56631  * @{
56632  */
56633 
56634 /*! @name ECAPR0 - ENETC capability register 0 */
56635 /*! @{ */
56636 
56637 #define NETC_ENETC_ECAPR0_RFS_MASK               (0x4U)
56638 #define NETC_ENETC_ECAPR0_RFS_SHIFT              (2U)
56639 #define NETC_ENETC_ECAPR0_RFS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_RFS_SHIFT)) & NETC_ENETC_ECAPR0_RFS_MASK)
56640 
56641 #define NETC_ENETC_ECAPR0_TSD_MASK               (0x20U)
56642 #define NETC_ENETC_ECAPR0_TSD_SHIFT              (5U)
56643 #define NETC_ENETC_ECAPR0_TSD(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_TSD_SHIFT)) & NETC_ENETC_ECAPR0_TSD_MASK)
56644 
56645 #define NETC_ENETC_ECAPR0_RSS_MASK               (0x100U)
56646 #define NETC_ENETC_ECAPR0_RSS_SHIFT              (8U)
56647 #define NETC_ENETC_ECAPR0_RSS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_RSS_SHIFT)) & NETC_ENETC_ECAPR0_RSS_MASK)
56648 
56649 #define NETC_ENETC_ECAPR0_WO_MASK                (0x2000U)
56650 #define NETC_ENETC_ECAPR0_WO_SHIFT               (13U)
56651 #define NETC_ENETC_ECAPR0_WO(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_WO_SHIFT)) & NETC_ENETC_ECAPR0_WO_MASK)
56652 
56653 #define NETC_ENETC_ECAPR0_FS_MASK                (0x10000U)
56654 #define NETC_ENETC_ECAPR0_FS_SHIFT               (16U)
56655 /*! FS - Functional safety capability supported. */
56656 #define NETC_ENETC_ECAPR0_FS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_FS_SHIFT)) & NETC_ENETC_ECAPR0_FS_MASK)
56657 /*! @} */
56658 
56659 /*! @name ECAPR1 - ENETC capability register 1 */
56660 /*! @{ */
56661 
56662 #define NETC_ENETC_ECAPR1_NUM_TCS_MASK           (0x70U)
56663 #define NETC_ENETC_ECAPR1_NUM_TCS_SHIFT          (4U)
56664 #define NETC_ENETC_ECAPR1_NUM_TCS(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_TCS_SHIFT)) & NETC_ENETC_ECAPR1_NUM_TCS_MASK)
56665 
56666 #define NETC_ENETC_ECAPR1_NUM_MCH_MASK           (0x300U)
56667 #define NETC_ENETC_ECAPR1_NUM_MCH_SHIFT          (8U)
56668 #define NETC_ENETC_ECAPR1_NUM_MCH(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_MCH_SHIFT)) & NETC_ENETC_ECAPR1_NUM_MCH_MASK)
56669 
56670 #define NETC_ENETC_ECAPR1_NUM_UCH_MASK           (0xC00U)
56671 #define NETC_ENETC_ECAPR1_NUM_UCH_SHIFT          (10U)
56672 #define NETC_ENETC_ECAPR1_NUM_UCH(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_UCH_SHIFT)) & NETC_ENETC_ECAPR1_NUM_UCH_MASK)
56673 
56674 #define NETC_ENETC_ECAPR1_NUM_MSIX_MASK          (0x7FF000U)
56675 #define NETC_ENETC_ECAPR1_NUM_MSIX_SHIFT         (12U)
56676 /*! NUM_MSIX - Number of MSI-X */
56677 #define NETC_ENETC_ECAPR1_NUM_MSIX(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_MSIX_SHIFT)) & NETC_ENETC_ECAPR1_NUM_MSIX_MASK)
56678 
56679 #define NETC_ENETC_ECAPR1_NUM_VSI_MASK           (0xF000000U)
56680 #define NETC_ENETC_ECAPR1_NUM_VSI_SHIFT          (24U)
56681 #define NETC_ENETC_ECAPR1_NUM_VSI(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_VSI_SHIFT)) & NETC_ENETC_ECAPR1_NUM_VSI_MASK)
56682 
56683 #define NETC_ENETC_ECAPR1_NUM_IPV_MASK           (0x80000000U)
56684 #define NETC_ENETC_ECAPR1_NUM_IPV_SHIFT          (31U)
56685 #define NETC_ENETC_ECAPR1_NUM_IPV(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_IPV_SHIFT)) & NETC_ENETC_ECAPR1_NUM_IPV_MASK)
56686 /*! @} */
56687 
56688 /*! @name ECAPR2 - ENETC capability register 2 */
56689 /*! @{ */
56690 
56691 #define NETC_ENETC_ECAPR2_NUM_TX_BDR_MASK        (0x3FFU)
56692 #define NETC_ENETC_ECAPR2_NUM_TX_BDR_SHIFT       (0U)
56693 #define NETC_ENETC_ECAPR2_NUM_TX_BDR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR2_NUM_TX_BDR_SHIFT)) & NETC_ENETC_ECAPR2_NUM_TX_BDR_MASK)
56694 
56695 #define NETC_ENETC_ECAPR2_NUM_RX_BDR_MASK        (0x3FF0000U)
56696 #define NETC_ENETC_ECAPR2_NUM_RX_BDR_SHIFT       (16U)
56697 #define NETC_ENETC_ECAPR2_NUM_RX_BDR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR2_NUM_RX_BDR_SHIFT)) & NETC_ENETC_ECAPR2_NUM_RX_BDR_MASK)
56698 /*! @} */
56699 
56700 /*! @name PMR - Port mode register */
56701 /*! @{ */
56702 
56703 #define NETC_ENETC_PMR_SI0EN_MASK                (0x10000U)
56704 #define NETC_ENETC_PMR_SI0EN_SHIFT               (16U)
56705 /*! SI0EN
56706  *  0b0..Disabled
56707  *  0b1..Enabled
56708  */
56709 #define NETC_ENETC_PMR_SI0EN(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMR_SI0EN_SHIFT)) & NETC_ENETC_PMR_SI0EN_MASK)
56710 
56711 #define NETC_ENETC_PMR_SI1EN_MASK                (0x20000U)
56712 #define NETC_ENETC_PMR_SI1EN_SHIFT               (17U)
56713 /*! SI1EN
56714  *  0b0..Disabled
56715  *  0b1..Enabled
56716  */
56717 #define NETC_ENETC_PMR_SI1EN(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMR_SI1EN_SHIFT)) & NETC_ENETC_PMR_SI1EN_MASK)
56718 /*! @} */
56719 
56720 /*! @name PONVLANR - Port outer native VLAN register */
56721 /*! @{ */
56722 
56723 #define NETC_ENETC_PONVLANR_VID_MASK             (0xFFFU)
56724 #define NETC_ENETC_PONVLANR_VID_SHIFT            (0U)
56725 #define NETC_ENETC_PONVLANR_VID(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_VID_SHIFT)) & NETC_ENETC_PONVLANR_VID_MASK)
56726 
56727 #define NETC_ENETC_PONVLANR_DEI_MASK             (0x1000U)
56728 #define NETC_ENETC_PONVLANR_DEI_SHIFT            (12U)
56729 #define NETC_ENETC_PONVLANR_DEI(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_DEI_SHIFT)) & NETC_ENETC_PONVLANR_DEI_MASK)
56730 
56731 #define NETC_ENETC_PONVLANR_PCP_MASK             (0xE000U)
56732 #define NETC_ENETC_PONVLANR_PCP_SHIFT            (13U)
56733 #define NETC_ENETC_PONVLANR_PCP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_PCP_SHIFT)) & NETC_ENETC_PONVLANR_PCP_MASK)
56734 
56735 #define NETC_ENETC_PONVLANR_TPID_MASK            (0x30000U)
56736 #define NETC_ENETC_PONVLANR_TPID_SHIFT           (16U)
56737 /*! TPID
56738  *  0b00..Standard C-VLAN 0x8100
56739  *  0b01..Standard S-VLAN 0x88A8
56740  *  0b10..Custom VLAN as defined by CVLANR1[ETYPE]
56741  *  0b11..Custom VLAN as defined by CVLANR2[ETYPE]
56742  */
56743 #define NETC_ENETC_PONVLANR_TPID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_TPID_SHIFT)) & NETC_ENETC_PONVLANR_TPID_MASK)
56744 
56745 #define NETC_ENETC_PONVLANR_PNE_MASK             (0x40000U)
56746 #define NETC_ENETC_PONVLANR_PNE_SHIFT            (18U)
56747 /*! PNE - Port Native VLAN Enable
56748  *  0b0..Disabled
56749  *  0b1..Enabled
56750  */
56751 #define NETC_ENETC_PONVLANR_PNE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_PNE_SHIFT)) & NETC_ENETC_PONVLANR_PNE_MASK)
56752 
56753 #define NETC_ENETC_PONVLANR_VZE_MASK             (0x80000U)
56754 #define NETC_ENETC_PONVLANR_VZE_SHIFT            (19U)
56755 /*! VZE - VID 0 Enable
56756  *  0b0..Disabled
56757  *  0b1..Enabled
56758  */
56759 #define NETC_ENETC_PONVLANR_VZE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_VZE_SHIFT)) & NETC_ENETC_PONVLANR_VZE_MASK)
56760 /*! @} */
56761 
56762 /*! @name PINVLANR - Port inner native VLAN register */
56763 /*! @{ */
56764 
56765 #define NETC_ENETC_PINVLANR_VID_MASK             (0xFFFU)
56766 #define NETC_ENETC_PINVLANR_VID_SHIFT            (0U)
56767 #define NETC_ENETC_PINVLANR_VID(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_VID_SHIFT)) & NETC_ENETC_PINVLANR_VID_MASK)
56768 
56769 #define NETC_ENETC_PINVLANR_DEI_MASK             (0x1000U)
56770 #define NETC_ENETC_PINVLANR_DEI_SHIFT            (12U)
56771 #define NETC_ENETC_PINVLANR_DEI(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_DEI_SHIFT)) & NETC_ENETC_PINVLANR_DEI_MASK)
56772 
56773 #define NETC_ENETC_PINVLANR_PCP_MASK             (0xE000U)
56774 #define NETC_ENETC_PINVLANR_PCP_SHIFT            (13U)
56775 #define NETC_ENETC_PINVLANR_PCP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_PCP_SHIFT)) & NETC_ENETC_PINVLANR_PCP_MASK)
56776 
56777 #define NETC_ENETC_PINVLANR_TPID_MASK            (0x30000U)
56778 #define NETC_ENETC_PINVLANR_TPID_SHIFT           (16U)
56779 /*! TPID
56780  *  0b00..Standard C-VLAN 0x8100
56781  *  0b01..Standard S-VLAN 0x88A8
56782  *  0b10..Custom VLAN as defined by CVLANR1[ETYPE]
56783  *  0b11..Custom VLAN as defined by CVLANR2[ETYPE]
56784  */
56785 #define NETC_ENETC_PINVLANR_TPID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_TPID_SHIFT)) & NETC_ENETC_PINVLANR_TPID_MASK)
56786 
56787 #define NETC_ENETC_PINVLANR_PNE_MASK             (0x40000U)
56788 #define NETC_ENETC_PINVLANR_PNE_SHIFT            (18U)
56789 /*! PNE - Port Native VLAN Enable
56790  *  0b0..Disabled
56791  *  0b1..Enabled
56792  */
56793 #define NETC_ENETC_PINVLANR_PNE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_PNE_SHIFT)) & NETC_ENETC_PINVLANR_PNE_MASK)
56794 
56795 #define NETC_ENETC_PINVLANR_VZE_MASK             (0x80000U)
56796 #define NETC_ENETC_PINVLANR_VZE_SHIFT            (19U)
56797 /*! VZE - VID 0 Enable
56798  *  0b0..Disabled
56799  *  0b1..Enabled
56800  */
56801 #define NETC_ENETC_PINVLANR_VZE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_VZE_SHIFT)) & NETC_ENETC_PINVLANR_VZE_MASK)
56802 /*! @} */
56803 
56804 /*! @name PVCLCTR - Port VLAN classification control register */
56805 /*! @{ */
56806 
56807 #define NETC_ENETC_PVCLCTR_OAI_MASK              (0x200U)
56808 #define NETC_ENETC_PVCLCTR_OAI_SHIFT             (9U)
56809 /*! OAI - Outer as Inner
56810  *  0b0..Indicates that the Inner is not valid if only one tag is found
56811  *  0b1..Indicates that the outer should be used as the Inner if only one tag is found
56812  */
56813 #define NETC_ENETC_PVCLCTR_OAI(x)                (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PVCLCTR_OAI_SHIFT)) & NETC_ENETC_PVCLCTR_OAI_MASK)
56814 /*! @} */
56815 
56816 /*! @name PARCSCR - Parser checksum configuration register */
56817 /*! @{ */
56818 
56819 #define NETC_ENETC_PARCSCR_L4CD_MASK             (0x1U)
56820 #define NETC_ENETC_PARCSCR_L4CD_SHIFT            (0U)
56821 /*! L4CD
56822  *  0b0..Enabled
56823  *  0b1..Disabled
56824  */
56825 #define NETC_ENETC_PARCSCR_L4CD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCSCR_L4CD_SHIFT)) & NETC_ENETC_PARCSCR_L4CD_MASK)
56826 
56827 #define NETC_ENETC_PARCSCR_L3CD_MASK             (0x2U)
56828 #define NETC_ENETC_PARCSCR_L3CD_SHIFT            (1U)
56829 /*! L3CD
56830  *  0b0..Enabled
56831  *  0b1..Disabled
56832  */
56833 #define NETC_ENETC_PARCSCR_L3CD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCSCR_L3CD_SHIFT)) & NETC_ENETC_PARCSCR_L3CD_MASK)
56834 /*! @} */
56835 
56836 /*! @name PARCECR - Parser custom Ethertype 0 configuration register..Parser custom Ethertype 3 configuration register */
56837 /*! @{ */
56838 
56839 #define NETC_ENETC_PARCECR_CP_MASK               (0xFU)
56840 #define NETC_ENETC_PARCECR_CP_SHIFT              (0U)
56841 /*! CP - Code Point */
56842 #define NETC_ENETC_PARCECR_CP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_CP_SHIFT)) & NETC_ENETC_PARCECR_CP_MASK)
56843 
56844 #define NETC_ENETC_PARCECR_EN_MASK               (0x20U)
56845 #define NETC_ENETC_PARCECR_EN_SHIFT              (5U)
56846 /*! EN - Enable
56847  *  0b0..Disabled
56848  *  0b1..Enabled
56849  */
56850 #define NETC_ENETC_PARCECR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_EN_SHIFT)) & NETC_ENETC_PARCECR_EN_MASK)
56851 
56852 #define NETC_ENETC_PARCECR_ETYPE_MASK            (0xFFFF0000U)
56853 #define NETC_ENETC_PARCECR_ETYPE_SHIFT           (16U)
56854 /*! ETYPE - ETYPE */
56855 #define NETC_ENETC_PARCECR_ETYPE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_ETYPE_SHIFT)) & NETC_ENETC_PARCECR_ETYPE_MASK)
56856 /*! @} */
56857 
56858 /* The count of NETC_ENETC_PARCECR */
56859 #define NETC_ENETC_PARCECR_COUNT                 (4U)
56860 
56861 /*! @name PPAUONTR - Port pause ON threshold register */
56862 /*! @{ */
56863 
56864 #define NETC_ENETC_PPAUONTR_THRESH_MASK          (0xFFFFFFU)
56865 #define NETC_ENETC_PPAUONTR_THRESH_SHIFT         (0U)
56866 #define NETC_ENETC_PPAUONTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PPAUONTR_THRESH_SHIFT)) & NETC_ENETC_PPAUONTR_THRESH_MASK)
56867 /*! @} */
56868 
56869 /*! @name PPAUOFFTR - Port pause OFF threshold register */
56870 /*! @{ */
56871 
56872 #define NETC_ENETC_PPAUOFFTR_THRESH_MASK         (0xFFFFFFU)
56873 #define NETC_ENETC_PPAUOFFTR_THRESH_SHIFT        (0U)
56874 #define NETC_ENETC_PPAUOFFTR_THRESH(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PPAUOFFTR_THRESH_SHIFT)) & NETC_ENETC_PPAUOFFTR_THRESH_MASK)
56875 /*! @} */
56876 
56877 /*! @name PRXMBER - Port receive memory buffer entitlement register */
56878 /*! @{ */
56879 
56880 #define NETC_ENETC_PRXMBER_AMOUNT_MASK           (0xFFFFFFU)
56881 #define NETC_ENETC_PRXMBER_AMOUNT_SHIFT          (0U)
56882 #define NETC_ENETC_PRXMBER_AMOUNT(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXMBER_AMOUNT_SHIFT)) & NETC_ENETC_PRXMBER_AMOUNT_MASK)
56883 /*! @} */
56884 
56885 /*! @name PRXMBLR - Port receive memory buffer limit register */
56886 /*! @{ */
56887 
56888 #define NETC_ENETC_PRXMBLR_LIMIT_MASK            (0xFFFFFFU)
56889 #define NETC_ENETC_PRXMBLR_LIMIT_SHIFT           (0U)
56890 #define NETC_ENETC_PRXMBLR_LIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXMBLR_LIMIT_SHIFT)) & NETC_ENETC_PRXMBLR_LIMIT_MASK)
56891 /*! @} */
56892 
56893 /*! @name PRXBCR - Port receive buffer count register */
56894 /*! @{ */
56895 
56896 #define NETC_ENETC_PRXBCR_COUNT_MASK             (0xFFFFFFU)
56897 #define NETC_ENETC_PRXBCR_COUNT_SHIFT            (0U)
56898 #define NETC_ENETC_PRXBCR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXBCR_COUNT_SHIFT)) & NETC_ENETC_PRXBCR_COUNT_MASK)
56899 /*! @} */
56900 
56901 /*! @name PRXBCHWMR - Port receive buffer count high watermark register */
56902 /*! @{ */
56903 
56904 #define NETC_ENETC_PRXBCHWMR_WATERMARK_MASK      (0xFFFFFFU)
56905 #define NETC_ENETC_PRXBCHWMR_WATERMARK_SHIFT     (0U)
56906 #define NETC_ENETC_PRXBCHWMR_WATERMARK(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXBCHWMR_WATERMARK_SHIFT)) & NETC_ENETC_PRXBCHWMR_WATERMARK_MASK)
56907 /*! @} */
56908 
56909 /*! @name PICDRDCR - Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register */
56910 /*! @{ */
56911 
56912 #define NETC_ENETC_PICDRDCR_COUNT_MASK           (0xFFFFFFFFU)
56913 #define NETC_ENETC_PICDRDCR_COUNT_SHIFT          (0U)
56914 #define NETC_ENETC_PICDRDCR_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICDRDCR_COUNT_SHIFT)) & NETC_ENETC_PICDRDCR_COUNT_MASK)
56915 /*! @} */
56916 
56917 /* The count of NETC_ENETC_PICDRDCR */
56918 #define NETC_ENETC_PICDRADCR_PICDRDCR_COUNT      (4U)
56919 
56920 /*! @name PICDRDCRRR - Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register */
56921 /*! @{ */
56922 
56923 #define NETC_ENETC_PICDRDCRRR_COUNT_MASK         (0xFFFFFFFFU)
56924 #define NETC_ENETC_PICDRDCRRR_COUNT_SHIFT        (0U)
56925 #define NETC_ENETC_PICDRDCRRR_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICDRDCRRR_COUNT_SHIFT)) & NETC_ENETC_PICDRDCRRR_COUNT_MASK)
56926 /*! @} */
56927 
56928 /* The count of NETC_ENETC_PICDRDCRRR */
56929 #define NETC_ENETC_PICDRADCR_PICDRDCRRR_COUNT    (4U)
56930 
56931 /*! @name PICPDSR - Port ingress congestion priority discard status register */
56932 /*! @{ */
56933 
56934 #define NETC_ENETC_PICPDSR_DR0_P0DS_MASK         (0x1U)
56935 #define NETC_ENETC_PICPDSR_DR0_P0DS_SHIFT        (0U)
56936 #define NETC_ENETC_PICPDSR_DR0_P0DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR0_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR0_P0DS_MASK)
56937 
56938 #define NETC_ENETC_PICPDSR_DR0_P1DS_MASK         (0x10U)
56939 #define NETC_ENETC_PICPDSR_DR0_P1DS_SHIFT        (4U)
56940 #define NETC_ENETC_PICPDSR_DR0_P1DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR0_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR0_P1DS_MASK)
56941 
56942 #define NETC_ENETC_PICPDSR_DR1_P0DS_MASK         (0x100U)
56943 #define NETC_ENETC_PICPDSR_DR1_P0DS_SHIFT        (8U)
56944 #define NETC_ENETC_PICPDSR_DR1_P0DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR1_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR1_P0DS_MASK)
56945 
56946 #define NETC_ENETC_PICPDSR_DR1_P1DS_MASK         (0x1000U)
56947 #define NETC_ENETC_PICPDSR_DR1_P1DS_SHIFT        (12U)
56948 #define NETC_ENETC_PICPDSR_DR1_P1DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR1_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR1_P1DS_MASK)
56949 
56950 #define NETC_ENETC_PICPDSR_DR2_P0DS_MASK         (0x10000U)
56951 #define NETC_ENETC_PICPDSR_DR2_P0DS_SHIFT        (16U)
56952 #define NETC_ENETC_PICPDSR_DR2_P0DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR2_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR2_P0DS_MASK)
56953 
56954 #define NETC_ENETC_PICPDSR_DR2_P1DS_MASK         (0x100000U)
56955 #define NETC_ENETC_PICPDSR_DR2_P1DS_SHIFT        (20U)
56956 #define NETC_ENETC_PICPDSR_DR2_P1DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR2_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR2_P1DS_MASK)
56957 
56958 #define NETC_ENETC_PICPDSR_DR3_P0DS_MASK         (0x1000000U)
56959 #define NETC_ENETC_PICPDSR_DR3_P0DS_SHIFT        (24U)
56960 #define NETC_ENETC_PICPDSR_DR3_P0DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR3_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR3_P0DS_MASK)
56961 
56962 #define NETC_ENETC_PICPDSR_DR3_P1DS_MASK         (0x10000000U)
56963 #define NETC_ENETC_PICPDSR_DR3_P1DS_SHIFT        (28U)
56964 #define NETC_ENETC_PICPDSR_DR3_P1DS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR3_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR3_P1DS_MASK)
56965 /*! @} */
56966 
56967 /*! @name PSIPMMR - Port station interface promiscuous MAC mode register */
56968 /*! @{ */
56969 
56970 #define NETC_ENETC_PSIPMMR_SI0_MAC_UP_MASK       (0x1U)
56971 #define NETC_ENETC_PSIPMMR_SI0_MAC_UP_SHIFT      (0U)
56972 /*! SI0_MAC_UP
56973  *  0b0..Disabled
56974  *  0b1..Enabled
56975  */
56976 #define NETC_ENETC_PSIPMMR_SI0_MAC_UP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI0_MAC_UP_SHIFT)) & NETC_ENETC_PSIPMMR_SI0_MAC_UP_MASK)
56977 
56978 #define NETC_ENETC_PSIPMMR_SI1_MAC_UP_MASK       (0x2U)
56979 #define NETC_ENETC_PSIPMMR_SI1_MAC_UP_SHIFT      (1U)
56980 /*! SI1_MAC_UP
56981  *  0b0..Disabled
56982  *  0b1..Enabled
56983  */
56984 #define NETC_ENETC_PSIPMMR_SI1_MAC_UP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI1_MAC_UP_SHIFT)) & NETC_ENETC_PSIPMMR_SI1_MAC_UP_MASK)
56985 
56986 #define NETC_ENETC_PSIPMMR_SI0_MAC_MP_MASK       (0x10000U)
56987 #define NETC_ENETC_PSIPMMR_SI0_MAC_MP_SHIFT      (16U)
56988 /*! SI0_MAC_MP
56989  *  0b0..Disabled
56990  *  0b1..Enabled
56991  */
56992 #define NETC_ENETC_PSIPMMR_SI0_MAC_MP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI0_MAC_MP_SHIFT)) & NETC_ENETC_PSIPMMR_SI0_MAC_MP_MASK)
56993 
56994 #define NETC_ENETC_PSIPMMR_SI1_MAC_MP_MASK       (0x20000U)
56995 #define NETC_ENETC_PSIPMMR_SI1_MAC_MP_SHIFT      (17U)
56996 /*! SI1_MAC_MP
56997  *  0b0..Disabled
56998  *  0b1..Enabled
56999  */
57000 #define NETC_ENETC_PSIPMMR_SI1_MAC_MP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI1_MAC_MP_SHIFT)) & NETC_ENETC_PSIPMMR_SI1_MAC_MP_MASK)
57001 /*! @} */
57002 
57003 /*! @name PSIPVMR - Port station interface promiscuous VLAN mode register */
57004 /*! @{ */
57005 
57006 #define NETC_ENETC_PSIPVMR_SI0_VLAN_P_MASK       (0x1U)
57007 #define NETC_ENETC_PSIPVMR_SI0_VLAN_P_SHIFT      (0U)
57008 /*! SI0_VLAN_P
57009  *  0b0..SI 0 does not qualify for the reception of all VLAN tags
57010  *  0b1..SI 0 does qualify for the reception of all VLAN tags
57011  */
57012 #define NETC_ENETC_PSIPVMR_SI0_VLAN_P(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI0_VLAN_P_SHIFT)) & NETC_ENETC_PSIPVMR_SI0_VLAN_P_MASK)
57013 
57014 #define NETC_ENETC_PSIPVMR_SI1_VLAN_P_MASK       (0x2U)
57015 #define NETC_ENETC_PSIPVMR_SI1_VLAN_P_SHIFT      (1U)
57016 /*! SI1_VLAN_P
57017  *  0b0..SI 1 does not qualify for the reception of all VLAN tags
57018  *  0b1..SI 1 does qualify for the reception of all VLAN tags
57019  */
57020 #define NETC_ENETC_PSIPVMR_SI1_VLAN_P(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI1_VLAN_P_SHIFT)) & NETC_ENETC_PSIPVMR_SI1_VLAN_P_MASK)
57021 
57022 #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_MASK     (0x10000U)
57023 #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_SHIFT    (16U)
57024 /*! SI0_VLAN_UTA
57025  *  0b0..SI 0 does not qualify for reception of untagged frames
57026  *  0b1..SI 0 does qualify for reception of untagged frames
57027  */
57028 #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_SHIFT)) & NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_MASK)
57029 
57030 #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_MASK     (0x20000U)
57031 #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_SHIFT    (17U)
57032 /*! SI1_VLAN_UTA
57033  *  0b0..SI 1 does not qualify for reception of untagged frames
57034  *  0b1..SI 1 does qualify for reception of untagged frames
57035  */
57036 #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_SHIFT)) & NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_MASK)
57037 /*! @} */
57038 
57039 /*! @name PBFDSIR - Port broadcast frames dropped due to MAC filtering register */
57040 /*! @{ */
57041 
57042 #define NETC_ENETC_PBFDSIR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57043 #define NETC_ENETC_PBFDSIR_FRAME_DROP_SHIFT      (0U)
57044 #define NETC_ENETC_PBFDSIR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PBFDSIR_FRAME_DROP_SHIFT)) & NETC_ENETC_PBFDSIR_FRAME_DROP_MASK)
57045 /*! @} */
57046 
57047 /*! @name PFDMSAPR - Port frame drop MAC source address pruning register */
57048 /*! @{ */
57049 
57050 #define NETC_ENETC_PFDMSAPR_FRAME_DROP_MASK      (0xFFFFFFFFU)
57051 #define NETC_ENETC_PFDMSAPR_FRAME_DROP_SHIFT     (0U)
57052 #define NETC_ENETC_PFDMSAPR_FRAME_DROP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PFDMSAPR_FRAME_DROP_SHIFT)) & NETC_ENETC_PFDMSAPR_FRAME_DROP_MASK)
57053 /*! @} */
57054 
57055 /*! @name PSIMAFCAPR - Port station interface MAC address filtering capability register */
57056 /*! @{ */
57057 
57058 #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_MASK  (0xFFFU)
57059 #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT (0U)
57060 #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT)) & NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_MASK)
57061 /*! @} */
57062 
57063 /*! @name PUFDMFR - Port unicast frames dropped due to MAC filtering register */
57064 /*! @{ */
57065 
57066 #define NETC_ENETC_PUFDMFR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57067 #define NETC_ENETC_PUFDMFR_FRAME_DROP_SHIFT      (0U)
57068 #define NETC_ENETC_PUFDMFR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PUFDMFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PUFDMFR_FRAME_DROP_MASK)
57069 /*! @} */
57070 
57071 /*! @name PMFDMFR - Port multicast frames dropped due to MAC filtering register */
57072 /*! @{ */
57073 
57074 #define NETC_ENETC_PMFDMFR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57075 #define NETC_ENETC_PMFDMFR_FRAME_DROP_SHIFT      (0U)
57076 #define NETC_ENETC_PMFDMFR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMFDMFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PMFDMFR_FRAME_DROP_MASK)
57077 /*! @} */
57078 
57079 /*! @name PSIVLANFCAPR - Port station interface VLAN filtering capability register */
57080 /*! @{ */
57081 
57082 #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_MASK (0xFFFU)
57083 #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT (0U)
57084 #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT)) & NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_MASK)
57085 /*! @} */
57086 
57087 /*! @name PSIVLANFMR - Port station interface VLAN filtering mode register */
57088 /*! @{ */
57089 
57090 #define NETC_ENETC_PSIVLANFMR_VS_MASK            (0x1U)
57091 #define NETC_ENETC_PSIVLANFMR_VS_SHIFT           (0U)
57092 /*! VS
57093  *  0b0..Inner VLAN tag will be used for VLAN filtering
57094  *  0b1..Outer VLAN tag will be used for VLAN filtering
57095  */
57096 #define NETC_ENETC_PSIVLANFMR_VS(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFMR_VS_SHIFT)) & NETC_ENETC_PSIVLANFMR_VS_MASK)
57097 /*! @} */
57098 
57099 /*! @name PUFDVFR - Port unicast frames dropped VLAN filtering register */
57100 /*! @{ */
57101 
57102 #define NETC_ENETC_PUFDVFR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57103 #define NETC_ENETC_PUFDVFR_FRAME_DROP_SHIFT      (0U)
57104 #define NETC_ENETC_PUFDVFR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PUFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PUFDVFR_FRAME_DROP_MASK)
57105 /*! @} */
57106 
57107 /*! @name PMFDVFR - Port multicast frames dropped VLAN filtering register */
57108 /*! @{ */
57109 
57110 #define NETC_ENETC_PMFDVFR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57111 #define NETC_ENETC_PMFDVFR_FRAME_DROP_SHIFT      (0U)
57112 #define NETC_ENETC_PMFDVFR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PMFDVFR_FRAME_DROP_MASK)
57113 /*! @} */
57114 
57115 /*! @name PBFDVFR - Port broadcast frames dropped VLAN filtering register */
57116 /*! @{ */
57117 
57118 #define NETC_ENETC_PBFDVFR_FRAME_DROP_MASK       (0xFFFFFFFFU)
57119 #define NETC_ENETC_PBFDVFR_FRAME_DROP_SHIFT      (0U)
57120 #define NETC_ENETC_PBFDVFR_FRAME_DROP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PBFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PBFDVFR_FRAME_DROP_MASK)
57121 /*! @} */
57122 
57123 /*! @name PLPMR - Port low power mode register */
57124 /*! @{ */
57125 
57126 #define NETC_ENETC_PLPMR_WME_MASK                (0x1U)
57127 #define NETC_ENETC_PLPMR_WME_SHIFT               (0U)
57128 /*! WME
57129  *  0b0..Disabled
57130  *  0b1..Enabled
57131  */
57132 #define NETC_ENETC_PLPMR_WME(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PLPMR_WME_SHIFT)) & NETC_ENETC_PLPMR_WME_MASK)
57133 /*! @} */
57134 
57135 /*! @name PWOSR - Port wake-on status register */
57136 /*! @{ */
57137 
57138 #define NETC_ENETC_PWOSR_WOLA_MASK               (0x1U)
57139 #define NETC_ENETC_PWOSR_WOLA_SHIFT              (0U)
57140 /*! WOLA
57141  *  0b0..Inactive
57142  *  0b1..Active. ENETC is actively searching for frames matching the Wake-on-LAN event criteria.
57143  */
57144 #define NETC_ENETC_PWOSR_WOLA(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PWOSR_WOLA_SHIFT)) & NETC_ENETC_PWOSR_WOLA_MASK)
57145 
57146 #define NETC_ENETC_PWOSR_ICMB_MASK               (0x2U)
57147 #define NETC_ENETC_PWOSR_ICMB_SHIFT              (1U)
57148 /*! ICMB
57149  *  0b0..Not blocked
57150  *  0b1..Blocked.
57151  */
57152 #define NETC_ENETC_PWOSR_ICMB(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PWOSR_ICMB_SHIFT)) & NETC_ENETC_PWOSR_ICMB_MASK)
57153 /*! @} */
57154 
57155 /*! @name IPV2ICMPMR0 - Receive IPV to ICM priority mapping register 0 */
57156 /*! @{ */
57157 
57158 #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM_MASK      (0x1U)
57159 #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM_SHIFT     (0U)
57160 #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV0ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV0ICM_MASK)
57161 
57162 #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM_MASK      (0x10U)
57163 #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM_SHIFT     (4U)
57164 #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV1ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV1ICM_MASK)
57165 
57166 #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM_MASK      (0x100U)
57167 #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM_SHIFT     (8U)
57168 #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV2ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV2ICM_MASK)
57169 
57170 #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM_MASK      (0x1000U)
57171 #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM_SHIFT     (12U)
57172 #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV3ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV3ICM_MASK)
57173 
57174 #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM_MASK      (0x10000U)
57175 #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM_SHIFT     (16U)
57176 #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV4ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV4ICM_MASK)
57177 
57178 #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM_MASK      (0x100000U)
57179 #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM_SHIFT     (20U)
57180 #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV5ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV5ICM_MASK)
57181 
57182 #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM_MASK      (0x1000000U)
57183 #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM_SHIFT     (24U)
57184 #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV6ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV6ICM_MASK)
57185 
57186 #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM_MASK      (0x10000000U)
57187 #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM_SHIFT     (28U)
57188 #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV7ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV7ICM_MASK)
57189 /*! @} */
57190 
57191 /*! @name PRIO2TCMR0 - Transmit priority to traffic class mapping register 0 */
57192 /*! @{ */
57193 
57194 #define NETC_ENETC_PRIO2TCMR0_PRIO0TC_MASK       (0x7U)
57195 #define NETC_ENETC_PRIO2TCMR0_PRIO0TC_SHIFT      (0U)
57196 #define NETC_ENETC_PRIO2TCMR0_PRIO0TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO0TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO0TC_MASK)
57197 
57198 #define NETC_ENETC_PRIO2TCMR0_PRIO1TC_MASK       (0x70U)
57199 #define NETC_ENETC_PRIO2TCMR0_PRIO1TC_SHIFT      (4U)
57200 #define NETC_ENETC_PRIO2TCMR0_PRIO1TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO1TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO1TC_MASK)
57201 
57202 #define NETC_ENETC_PRIO2TCMR0_PRIO2TC_MASK       (0x700U)
57203 #define NETC_ENETC_PRIO2TCMR0_PRIO2TC_SHIFT      (8U)
57204 #define NETC_ENETC_PRIO2TCMR0_PRIO2TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO2TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO2TC_MASK)
57205 
57206 #define NETC_ENETC_PRIO2TCMR0_PRIO3TC_MASK       (0x7000U)
57207 #define NETC_ENETC_PRIO2TCMR0_PRIO3TC_SHIFT      (12U)
57208 #define NETC_ENETC_PRIO2TCMR0_PRIO3TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO3TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO3TC_MASK)
57209 
57210 #define NETC_ENETC_PRIO2TCMR0_PRIO4TC_MASK       (0x70000U)
57211 #define NETC_ENETC_PRIO2TCMR0_PRIO4TC_SHIFT      (16U)
57212 #define NETC_ENETC_PRIO2TCMR0_PRIO4TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO4TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO4TC_MASK)
57213 
57214 #define NETC_ENETC_PRIO2TCMR0_PRIO5TC_MASK       (0x700000U)
57215 #define NETC_ENETC_PRIO2TCMR0_PRIO5TC_SHIFT      (20U)
57216 #define NETC_ENETC_PRIO2TCMR0_PRIO5TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO5TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO5TC_MASK)
57217 
57218 #define NETC_ENETC_PRIO2TCMR0_PRIO6TC_MASK       (0x7000000U)
57219 #define NETC_ENETC_PRIO2TCMR0_PRIO6TC_SHIFT      (24U)
57220 #define NETC_ENETC_PRIO2TCMR0_PRIO6TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO6TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO6TC_MASK)
57221 
57222 #define NETC_ENETC_PRIO2TCMR0_PRIO7TC_MASK       (0x70000000U)
57223 #define NETC_ENETC_PRIO2TCMR0_PRIO7TC_SHIFT      (28U)
57224 #define NETC_ENETC_PRIO2TCMR0_PRIO7TC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO7TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO7TC_MASK)
57225 /*! @} */
57226 
57227 /*! @name PTCTSDR - Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register */
57228 /*! @{ */
57229 
57230 #define NETC_ENETC_PTCTSDR_TSDE_MASK             (0x80000000U)
57231 #define NETC_ENETC_PTCTSDR_TSDE_SHIFT            (31U)
57232 /*! TSDE
57233  *  0b0..Disabled
57234  *  0b1..Enabled
57235  */
57236 #define NETC_ENETC_PTCTSDR_TSDE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PTCTSDR_TSDE_SHIFT)) & NETC_ENETC_PTCTSDR_TSDE_MASK)
57237 /*! @} */
57238 
57239 /* The count of NETC_ENETC_PTCTSDR */
57240 #define NETC_ENETC_PTCTSDR_COUNT                 (8U)
57241 
57242 /*! @name SMCAPR - Switch management capability register */
57243 /*! @{ */
57244 
57245 #define NETC_ENETC_SMCAPR_SM_MASK                (0x1U)
57246 #define NETC_ENETC_SMCAPR_SM_SHIFT               (0U)
57247 /*! SM - Switch Management
57248  *  0b0..ENETC instance has no switch management capability
57249  *  0b1..ENETC instance has switch management capability
57250  */
57251 #define NETC_ENETC_SMCAPR_SM(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_SMCAPR_SM_SHIFT)) & NETC_ENETC_SMCAPR_SM_MASK)
57252 /*! @} */
57253 
57254 /*! @name SMHRBDRMR - Switch management host reason 1 receive BD ring mapping register..Switch management host reason 15 receive BD ring mapping register */
57255 /*! @{ */
57256 
57257 #define NETC_ENETC_SMHRBDRMR_RXBDR_MASK          (0xFFU)
57258 #define NETC_ENETC_SMHRBDRMR_RXBDR_SHIFT         (0U)
57259 #define NETC_ENETC_SMHRBDRMR_RXBDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_SMHRBDRMR_RXBDR_SHIFT)) & NETC_ENETC_SMHRBDRMR_RXBDR_MASK)
57260 /*! @} */
57261 
57262 /* The count of NETC_ENETC_SMHRBDRMR */
57263 #define NETC_ENETC_SMHRBDRMR_COUNT               (15U)
57264 
57265 /*! @name PSIPMAR0 - Port station interface 0 primary MAC address register 0..Port station interface 1 primary MAC address register 0 */
57266 /*! @{ */
57267 
57268 #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_MASK   (0xFFFFFFFFU)
57269 #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_SHIFT  (0U)
57270 #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_MASK)
57271 /*! @} */
57272 
57273 /* The count of NETC_ENETC_PSIPMAR0 */
57274 #define NETC_ENETC_PSIPMAR0_COUNT                (2U)
57275 
57276 /*! @name PSIPMAR1 - Port station interface 0 primary MAC address register 1..Port station interface 1 primary MAC address register 1 */
57277 /*! @{ */
57278 
57279 #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_MASK   (0xFFFFU)
57280 #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_SHIFT  (0U)
57281 #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_MASK)
57282 /*! @} */
57283 
57284 /* The count of NETC_ENETC_PSIPMAR1 */
57285 #define NETC_ENETC_PSIPMAR1_COUNT                (2U)
57286 
57287 /*! @name PSIVLANR - Port station interface 0 VLAN register..Port station interface 1 VLAN register */
57288 /*! @{ */
57289 
57290 #define NETC_ENETC_PSIVLANR_VID_MASK             (0xFFFU)
57291 #define NETC_ENETC_PSIVLANR_VID_SHIFT            (0U)
57292 #define NETC_ENETC_PSIVLANR_VID(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_VID_SHIFT)) & NETC_ENETC_PSIVLANR_VID_MASK)
57293 
57294 #define NETC_ENETC_PSIVLANR_DEI_MASK             (0x1000U)
57295 #define NETC_ENETC_PSIVLANR_DEI_SHIFT            (12U)
57296 #define NETC_ENETC_PSIVLANR_DEI(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_DEI_SHIFT)) & NETC_ENETC_PSIVLANR_DEI_MASK)
57297 
57298 #define NETC_ENETC_PSIVLANR_PCP_MASK             (0xE000U)
57299 #define NETC_ENETC_PSIVLANR_PCP_SHIFT            (13U)
57300 #define NETC_ENETC_PSIVLANR_PCP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_PCP_SHIFT)) & NETC_ENETC_PSIVLANR_PCP_MASK)
57301 
57302 #define NETC_ENETC_PSIVLANR_TPID_MASK            (0x30000U)
57303 #define NETC_ENETC_PSIVLANR_TPID_SHIFT           (16U)
57304 /*! TPID
57305  *  0b00..Standard C-VLAN 0x8100
57306  *  0b01..Standard S-VLAN 0x88A8
57307  *  0b10..Custom VLAN as defined by CVLANR1[ETYPE]. Note that CVLANR1[V] is not checked for SI-based VLAN
57308  *        insertion; TPID value specified in CVLANR1[ETYPE] will be used to construct the VLAN header regardless of the
57309  *        value specified in CVLANR1[V].
57310  *  0b11..Custom VLAN as defined by CVLANR2[ETYPE]. Note that CVLANR2[V] is not checked for SI-based VLAN
57311  *        insertion; TPID value specified in CVLANR2[ETYPE] will be used to construct the VLAN header regardless of the
57312  *        value specified in CVLANR2[V].
57313  */
57314 #define NETC_ENETC_PSIVLANR_TPID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_TPID_SHIFT)) & NETC_ENETC_PSIVLANR_TPID_MASK)
57315 
57316 #define NETC_ENETC_PSIVLANR_E_MASK               (0x80000000U)
57317 #define NETC_ENETC_PSIVLANR_E_SHIFT              (31U)
57318 /*! E - Enable
57319  *  0b0..Disabled
57320  *  0b1..Enabled; SI-based VLAN information is added on transmit and removed on receive.
57321  */
57322 #define NETC_ENETC_PSIVLANR_E(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_E_SHIFT)) & NETC_ENETC_PSIVLANR_E_MASK)
57323 /*! @} */
57324 
57325 /* The count of NETC_ENETC_PSIVLANR */
57326 #define NETC_ENETC_PSIVLANR_COUNT                (2U)
57327 
57328 /*! @name PSICFGR0 - Port station interface 0 configuration register 0..Port station interface 1 configuration register 0 */
57329 /*! @{ */
57330 
57331 #define NETC_ENETC_PSICFGR0_NUM_TX_BDR_MASK      (0x7FU)
57332 #define NETC_ENETC_PSICFGR0_NUM_TX_BDR_SHIFT     (0U)
57333 #define NETC_ENETC_PSICFGR0_NUM_TX_BDR(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_NUM_TX_BDR_SHIFT)) & NETC_ENETC_PSICFGR0_NUM_TX_BDR_MASK)
57334 
57335 #define NETC_ENETC_PSICFGR0_SPE_MASK             (0x800U)
57336 #define NETC_ENETC_PSICFGR0_SPE_SHIFT            (11U)
57337 /*! SPE - Source Pruning Enable
57338  *  0b0..Disabled
57339  *  0b1..Enabled
57340  */
57341 #define NETC_ENETC_PSICFGR0_SPE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SPE_SHIFT)) & NETC_ENETC_PSICFGR0_SPE_MASK)
57342 
57343 #define NETC_ENETC_PSICFGR0_VTE_MASK             (0x1000U)
57344 #define NETC_ENETC_PSICFGR0_VTE_SHIFT            (12U)
57345 /*! VTE - VLAN Tag Extract
57346  *  0b0..SI-based VLAN removal disabled
57347  *  0b1..SI-based VLAN removal enabled
57348  */
57349 #define NETC_ENETC_PSICFGR0_VTE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_VTE_SHIFT)) & NETC_ENETC_PSICFGR0_VTE_MASK)
57350 
57351 #define NETC_ENETC_PSICFGR0_SIVIE_MASK           (0x4000U)
57352 #define NETC_ENETC_PSICFGR0_SIVIE_SHIFT          (14U)
57353 /*! SIVIE - SI-based VLAN Insertion Enable
57354  *  0b0..SI-based VLAN insertion disabled
57355  *  0b1..SI-based VLAN insertion enabled
57356  */
57357 #define NETC_ENETC_PSICFGR0_SIVIE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIVIE_SHIFT)) & NETC_ENETC_PSICFGR0_SIVIE_MASK)
57358 
57359 #define NETC_ENETC_PSICFGR0_ASE_MASK             (0x8000U)
57360 #define NETC_ENETC_PSICFGR0_ASE_SHIFT            (15U)
57361 /*! ASE - Anti-spoofing enable */
57362 #define NETC_ENETC_PSICFGR0_ASE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_ASE_SHIFT)) & NETC_ENETC_PSICFGR0_ASE_MASK)
57363 
57364 #define NETC_ENETC_PSICFGR0_NUM_RX_BDR_MASK      (0x7F0000U)
57365 #define NETC_ENETC_PSICFGR0_NUM_RX_BDR_SHIFT     (16U)
57366 #define NETC_ENETC_PSICFGR0_NUM_RX_BDR(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_NUM_RX_BDR_SHIFT)) & NETC_ENETC_PSICFGR0_NUM_RX_BDR_MASK)
57367 
57368 #define NETC_ENETC_PSICFGR0_SIVC_MASK            (0xF000000U)
57369 #define NETC_ENETC_PSICFGR0_SIVC_SHIFT           (24U)
57370 #define NETC_ENETC_PSICFGR0_SIVC(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIVC_SHIFT)) & NETC_ENETC_PSICFGR0_SIVC_MASK)
57371 
57372 #define NETC_ENETC_PSICFGR0_SIBW_MASK            (0xF0000000U)
57373 #define NETC_ENETC_PSICFGR0_SIBW_SHIFT           (28U)
57374 #define NETC_ENETC_PSICFGR0_SIBW(x)              (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIBW_SHIFT)) & NETC_ENETC_PSICFGR0_SIBW_MASK)
57375 /*! @} */
57376 
57377 /* The count of NETC_ENETC_PSICFGR0 */
57378 #define NETC_ENETC_PSICFGR0_COUNT                (2U)
57379 
57380 /*! @name PSICFGR1 - Port station interface 1 configuration register 1 */
57381 /*! @{ */
57382 
57383 #define NETC_ENETC_PSICFGR1_TC0_MAP_MASK         (0x7U)
57384 #define NETC_ENETC_PSICFGR1_TC0_MAP_SHIFT        (0U)
57385 #define NETC_ENETC_PSICFGR1_TC0_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC0_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC0_MAP_MASK)
57386 
57387 #define NETC_ENETC_PSICFGR1_TC1_MAP_MASK         (0x70U)
57388 #define NETC_ENETC_PSICFGR1_TC1_MAP_SHIFT        (4U)
57389 #define NETC_ENETC_PSICFGR1_TC1_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC1_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC1_MAP_MASK)
57390 
57391 #define NETC_ENETC_PSICFGR1_TC2_MAP_MASK         (0x700U)
57392 #define NETC_ENETC_PSICFGR1_TC2_MAP_SHIFT        (8U)
57393 #define NETC_ENETC_PSICFGR1_TC2_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC2_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC2_MAP_MASK)
57394 
57395 #define NETC_ENETC_PSICFGR1_TC3_MAP_MASK         (0x7000U)
57396 #define NETC_ENETC_PSICFGR1_TC3_MAP_SHIFT        (12U)
57397 #define NETC_ENETC_PSICFGR1_TC3_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC3_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC3_MAP_MASK)
57398 
57399 #define NETC_ENETC_PSICFGR1_TC4_MAP_MASK         (0x70000U)
57400 #define NETC_ENETC_PSICFGR1_TC4_MAP_SHIFT        (16U)
57401 #define NETC_ENETC_PSICFGR1_TC4_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC4_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC4_MAP_MASK)
57402 
57403 #define NETC_ENETC_PSICFGR1_TC5_MAP_MASK         (0x700000U)
57404 #define NETC_ENETC_PSICFGR1_TC5_MAP_SHIFT        (20U)
57405 #define NETC_ENETC_PSICFGR1_TC5_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC5_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC5_MAP_MASK)
57406 
57407 #define NETC_ENETC_PSICFGR1_TC6_MAP_MASK         (0x7000000U)
57408 #define NETC_ENETC_PSICFGR1_TC6_MAP_SHIFT        (24U)
57409 #define NETC_ENETC_PSICFGR1_TC6_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC6_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC6_MAP_MASK)
57410 
57411 #define NETC_ENETC_PSICFGR1_TC7_MAP_MASK         (0x70000000U)
57412 #define NETC_ENETC_PSICFGR1_TC7_MAP_SHIFT        (28U)
57413 #define NETC_ENETC_PSICFGR1_TC7_MAP(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC7_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC7_MAP_MASK)
57414 /*! @} */
57415 
57416 /* The count of NETC_ENETC_PSICFGR1 */
57417 #define NETC_ENETC_PSICFGR1_COUNT                (2U)
57418 
57419 /*! @name PSICFGR2 - Port station interface 0 configuration register 2..Port station interface 1 configuration register 2 */
57420 /*! @{ */
57421 
57422 #define NETC_ENETC_PSICFGR2_NUM_MSIX_MASK        (0x3FU)
57423 #define NETC_ENETC_PSICFGR2_NUM_MSIX_SHIFT       (0U)
57424 /*! NUM_MSIX - Number of MSI-X */
57425 #define NETC_ENETC_PSICFGR2_NUM_MSIX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR2_NUM_MSIX_SHIFT)) & NETC_ENETC_PSICFGR2_NUM_MSIX_MASK)
57426 /*! @} */
57427 
57428 /* The count of NETC_ENETC_PSICFGR2 */
57429 #define NETC_ENETC_PSICFGR2_COUNT                (2U)
57430 
57431 /*! @name PSIVMAFCFGR - Port station interface 0 VSI MAC address filtering configuration register..Port station interface 1 VSI MAC address filtering configuration register */
57432 /*! @{ */
57433 
57434 #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_MASK (0xFFU)
57435 #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT (0U)
57436 #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT)) & NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_MASK)
57437 /*! @} */
57438 
57439 /* The count of NETC_ENETC_PSIVMAFCFGR */
57440 #define NETC_ENETC_PSIVMAFCFGR_COUNT             (2U)
57441 
57442 /*! @name PSIVLANFCFGR - Port station interface 0 VLAN filtering configuration register..Port station interface 1 VLAN filtering configuration register */
57443 /*! @{ */
57444 
57445 #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_MASK (0xFFU)
57446 #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT (0U)
57447 #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT)) & NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_MASK)
57448 /*! @} */
57449 
57450 /* The count of NETC_ENETC_PSIVLANFCFGR */
57451 #define NETC_ENETC_PSIVLANFCFGR_COUNT            (2U)
57452 
57453 /*! @name PSIUMHFR0 - Port station interface 0 unicast MAC hash filter register 0..Port station interface 1 unicast MAC hash filter register 0 */
57454 /*! @{ */
57455 
57456 #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU)
57457 #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U)
57458 #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK)
57459 /*! @} */
57460 
57461 /* The count of NETC_ENETC_PSIUMHFR0 */
57462 #define NETC_ENETC_PSIUMHFR0_COUNT               (2U)
57463 
57464 /*! @name PSIUMHFR1 - Port station interface 0 unicast MAC hash filter register 1..Port station interface 1 unicast MAC hash filter register 1 */
57465 /*! @{ */
57466 
57467 #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU)
57468 #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U)
57469 #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK)
57470 /*! @} */
57471 
57472 /* The count of NETC_ENETC_PSIUMHFR1 */
57473 #define NETC_ENETC_PSIUMHFR1_COUNT               (2U)
57474 
57475 /*! @name PSIMMHFR0 - Port station interface 0 multicast MAC hash filter register 0..Port station interface 1 multicast MAC hash filter register 0 */
57476 /*! @{ */
57477 
57478 #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU)
57479 #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U)
57480 #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK)
57481 /*! @} */
57482 
57483 /* The count of NETC_ENETC_PSIMMHFR0 */
57484 #define NETC_ENETC_PSIMMHFR0_COUNT               (2U)
57485 
57486 /*! @name PSIMMHFR1 - Port station interface 0 multicast MAC hash filter register 1..Port station interface 1 multicast MAC hash filter register 1 */
57487 /*! @{ */
57488 
57489 #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU)
57490 #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U)
57491 #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK)
57492 /*! @} */
57493 
57494 /* The count of NETC_ENETC_PSIMMHFR1 */
57495 #define NETC_ENETC_PSIMMHFR1_COUNT               (2U)
57496 
57497 /*! @name PSIVHFR0 - Port station interface 0 VLAN hash filter register 0..Port station interface 1 VLAN hash filter register 0 */
57498 /*! @{ */
57499 
57500 #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK (0xFFFFFFFFU)
57501 #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT (0U)
57502 #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK)
57503 /*! @} */
57504 
57505 /* The count of NETC_ENETC_PSIVHFR0 */
57506 #define NETC_ENETC_PSIVHFR0_COUNT                (2U)
57507 
57508 /*! @name PSIVHFR1 - Port station interface 0 VLAN hash filter register 1..Port station interface 1 VLAN hash filter register 1 */
57509 /*! @{ */
57510 
57511 #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK (0xFFFFFFFFU)
57512 #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT (0U)
57513 #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK)
57514 /*! @} */
57515 
57516 /* The count of NETC_ENETC_PSIVHFR1 */
57517 #define NETC_ENETC_PSIVHFR1_COUNT                (2U)
57518 
57519 
57520 /*!
57521  * @}
57522  */ /* end of group NETC_ENETC_Register_Masks */
57523 
57524 
57525 /* NETC_ENETC - Peripheral instance base addresses */
57526 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
57527   /** Peripheral ENETC0_BASE base address */
57528   #define ENETC0_BASE_BASE                         (0x70B10000u)
57529   /** Peripheral ENETC0_BASE base address */
57530   #define ENETC0_BASE_BASE_NS                      (0x60B10000u)
57531   /** Peripheral ENETC0_BASE base pointer */
57532   #define ENETC0_BASE                              ((NETC_ENETC_Type *)ENETC0_BASE_BASE)
57533   /** Peripheral ENETC0_BASE base pointer */
57534   #define ENETC0_BASE_NS                           ((NETC_ENETC_Type *)ENETC0_BASE_BASE_NS)
57535   /** Peripheral ENETC1_BASE base address */
57536   #define ENETC1_BASE_BASE                         (0x70B50000u)
57537   /** Peripheral ENETC1_BASE base address */
57538   #define ENETC1_BASE_BASE_NS                      (0x60B50000u)
57539   /** Peripheral ENETC1_BASE base pointer */
57540   #define ENETC1_BASE                              ((NETC_ENETC_Type *)ENETC1_BASE_BASE)
57541   /** Peripheral ENETC1_BASE base pointer */
57542   #define ENETC1_BASE_NS                           ((NETC_ENETC_Type *)ENETC1_BASE_BASE_NS)
57543   /** Array initializer of NETC_ENETC peripheral base addresses */
57544   #define NETC_ENETC_BASE_ADDRS                    { ENETC0_BASE_BASE, ENETC1_BASE_BASE }
57545   /** Array initializer of NETC_ENETC peripheral base pointers */
57546   #define NETC_ENETC_BASE_PTRS                     { ENETC0_BASE, ENETC1_BASE }
57547   /** Array initializer of NETC_ENETC peripheral base addresses */
57548   #define NETC_ENETC_BASE_ADDRS_NS                 { ENETC0_BASE_BASE_NS, ENETC1_BASE_BASE_NS }
57549   /** Array initializer of NETC_ENETC peripheral base pointers */
57550   #define NETC_ENETC_BASE_PTRS_NS                  { ENETC0_BASE_NS, ENETC1_BASE_NS }
57551 #else
57552   /** Peripheral ENETC0_BASE base address */
57553   #define ENETC0_BASE_BASE                         (0x60B10000u)
57554   /** Peripheral ENETC0_BASE base pointer */
57555   #define ENETC0_BASE                              ((NETC_ENETC_Type *)ENETC0_BASE_BASE)
57556   /** Peripheral ENETC1_BASE base address */
57557   #define ENETC1_BASE_BASE                         (0x60B50000u)
57558   /** Peripheral ENETC1_BASE base pointer */
57559   #define ENETC1_BASE                              ((NETC_ENETC_Type *)ENETC1_BASE_BASE)
57560   /** Array initializer of NETC_ENETC peripheral base addresses */
57561   #define NETC_ENETC_BASE_ADDRS                    { ENETC0_BASE_BASE, ENETC1_BASE_BASE }
57562   /** Array initializer of NETC_ENETC peripheral base pointers */
57563   #define NETC_ENETC_BASE_PTRS                     { ENETC0_BASE, ENETC1_BASE }
57564 #endif
57565 
57566 /*!
57567  * @}
57568  */ /* end of group NETC_ENETC_Peripheral_Access_Layer */
57569 
57570 
57571 /* ----------------------------------------------------------------------------
57572    -- NETC_ETH_LINK Peripheral Access Layer
57573    ---------------------------------------------------------------------------- */
57574 
57575 /*!
57576  * @addtogroup NETC_ETH_LINK_Peripheral_Access_Layer NETC_ETH_LINK Peripheral Access Layer
57577  * @{
57578  */
57579 
57580 /** NETC_ETH_LINK - Register Layout Typedef */
57581 typedef struct {
57582        uint8_t RESERVED_0[8];
57583   __IO uint32_t PM0_COMMAND_CONFIG;                /**< Port MAC 0 Command and Configuration Register, offset: 0x8 */
57584   __I  uint32_t PM0_MAC_ADDR_0;                    /**< Port MAC 0 MAC Address Register 0, offset: 0xC */
57585   __I  uint32_t PM0_MAC_ADDR_1;                    /**< Port MAC 0 MAC Address Register 1, offset: 0x10 */
57586   __IO uint32_t PM0_MAXFRM;                        /**< Port MAC 0 Maximum Frame Length Register, offset: 0x14 */
57587   __IO uint32_t PM0_MINFRM;                        /**< Port MAC 0 Minimum Frame Length Register, offset: 0x18 */
57588        uint8_t RESERVED_1[20];
57589   __IO uint32_t PM0_MDIO_CFG;                      /**< Port MAC 0 Internal MDIO Configuration Register, offset: 0x30, not available in all instances (available on 6 out of 10) */
57590   __IO uint32_t PM0_MDIO_CTL;                      /**< Port MAC 0 Internal MDIO Interface Control Register, offset: 0x34, not available in all instances (available on 6 out of 10) */
57591   __IO uint32_t PM0_MDIO_DATA;                     /**< Port MAC 0 Internal MDIO Interface Data Register, offset: 0x38, not available in all instances (available on 6 out of 10) */
57592        uint8_t RESERVED_2[4];
57593   __IO uint32_t PM0_IEVENT;                        /**< Port MAC 0 Interrupt Event Register, offset: 0x40 */
57594   __IO uint32_t PM0_TX_IPG_PREAMBLE;               /**< Port MAC 0 Transmit Inter-Packet Gap Length and Flexible Preamble length Register, offset: 0x44 */
57595        uint8_t RESERVED_3[4];
57596   __IO uint32_t PM0_IMASK;                         /**< Port MAC 0 Interrupt Mask Register(INT_MASK), offset: 0x4C */
57597        uint8_t RESERVED_4[4];
57598   __IO uint32_t PM0_PAUSE_QUANTA;                  /**< Port MAC 0 Pause Quanta Register, offset: 0x54 */
57599        uint8_t RESERVED_5[12];
57600   __IO uint32_t PM0_PAUSE_THRESH;                  /**< Port MAC 0 Pause Quanta Threshold Register, offset: 0x64 */
57601        uint8_t RESERVED_6[12];
57602   __I  uint32_t PM0_RX_PAUSE_STATUS;               /**< Port MAC 0 Receive Pause Status Register, offset: 0x74 */
57603        uint8_t RESERVED_7[64];
57604   __IO uint32_t PM0_LPWAKE_TIMER;                  /**< Port MAC 0 EEE Low Power Wakeup Timer Register, offset: 0xB8 */
57605   __IO uint32_t PM0_SLEEP_TIMER;                   /**< Port MAC 0 Transmit EEE Low Power Timer Register, offset: 0xBC */
57606   __IO uint32_t PM0_SINGLE_STEP;                   /**< Port MAC 0 IEEE1588 Single-Step Control Register, offset: 0xC0 */
57607        uint8_t RESERVED_8[12];
57608   __IO uint32_t PM0_HD_BACKOFF_ENTROPY;            /**< Port MAC 0 half-duplex backoff entropy register, offset: 0xD0 */
57609   __IO uint32_t PM0_HD_FLOW_CTRL;                  /**< Port MAC 0 Half-Duplex Flow Control Register, offset: 0xD4 */
57610        uint8_t RESERVED_9[8];
57611   __IO uint32_t PM0_STATN_CONFIG;                  /**< Port MAC 0 Statistics Configuration Register, offset: 0xE0 */
57612        uint8_t RESERVED_10[28];
57613   __I  uint64_t PM0_REOCTN;                        /**< Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x100 */
57614   __I  uint64_t PM0_ROCTN;                         /**< Port MAC 0 Receive Octets Counter(iflnOctetsn), offset: 0x108 */
57615        uint8_t RESERVED_11[8];
57616   __I  uint64_t PM0_RXPFN;                         /**< Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x118 */
57617   __I  uint64_t PM0_RFRMN;                         /**< Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x120 */
57618   __I  uint64_t PM0_RFCSN;                         /**< Port MAC 0 Receive Frame Check Sequence Error Counter Register(), offset: 0x128 */
57619   __I  uint64_t PM0_RVLANN;                        /**< Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x130 */
57620   __I  uint64_t PM0_RERRN;                         /**< Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x138 */
57621   __I  uint64_t PM0_RUCAN;                         /**< Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x140 */
57622   __I  uint64_t PM0_RMCAN;                         /**< Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x148 */
57623   __I  uint64_t PM0_RBCAN;                         /**< Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x150 */
57624   __I  uint64_t PM0_RDRPN;                         /**< Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x158 */
57625   __I  uint64_t PM0_RPKTN;                         /**< Port MAC 0 Receive Packets Counter Register(etherStatsPktsn), offset: 0x160 */
57626   __I  uint64_t PM0_RUNDN;                         /**< Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x168 */
57627   __I  uint64_t PM0_R64N;                          /**< Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x170 */
57628   __I  uint64_t PM0_R127N;                         /**< Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x178 */
57629   __I  uint64_t PM0_R255N;                         /**< Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x180 */
57630   __I  uint64_t PM0_R511N;                         /**< Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x188 */
57631   __I  uint64_t PM0_R1023N;                        /**< Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x190 */
57632   __I  uint64_t PM0_R1522N;                        /**< Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x198 */
57633   __I  uint64_t PM0_R1523XN;                       /**< Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x1A0 */
57634   __I  uint64_t PM0_ROVRN;                         /**< Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x1A8 */
57635   __I  uint64_t PM0_RJBRN;                         /**< Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x1B0 */
57636   __I  uint64_t PM0_RFRGN;                         /**< Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x1B8 */
57637   __I  uint64_t PM0_RCNPN;                         /**< Port MAC 0 Receive Control Packet Counter Register, offset: 0x1C0 */
57638   __I  uint64_t PM0_RDRNTPN;                       /**< Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x1C8 */
57639   __I  uint64_t PM0_RMIN63N;                       /**< Port MAC 0 Receive Valid Small Packet Counter Register, offset: 0x1D0 */
57640        uint8_t RESERVED_12[40];
57641   __I  uint64_t PM0_TEOCTN;                        /**< Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x200 */
57642   __I  uint64_t PM0_TOCTN;                         /**< Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x208 */
57643        uint8_t RESERVED_13[8];
57644   __I  uint64_t PM0_TXPFN;                         /**< Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x218 */
57645   __I  uint64_t PM0_TFRMN;                         /**< Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x220 */
57646   __I  uint64_t PM0_TFCSN;                         /**< Port MAC 0 Transmit Frame Check Sequence Error Counter Register(), offset: 0x228 */
57647   __I  uint64_t PM0_TVLANN;                        /**< Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x230 */
57648   __I  uint64_t PM0_TERRN;                         /**< Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x238 */
57649   __I  uint64_t PM0_TUCAN;                         /**< Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x240 */
57650   __I  uint64_t PM0_TMCAN;                         /**< Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x248 */
57651   __I  uint64_t PM0_TBCAN;                         /**< Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x250 */
57652        uint8_t RESERVED_14[8];
57653   __I  uint64_t PM0_TPKTN;                         /**< Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x260 */
57654   __I  uint64_t PM0_TUNDN;                         /**< Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x268 */
57655   __I  uint64_t PM0_T64N;                          /**< Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x270 */
57656   __I  uint64_t PM0_T127N;                         /**< Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x278 */
57657   __I  uint64_t PM0_T255N;                         /**< Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x280 */
57658   __I  uint64_t PM0_T511N;                         /**< Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x288 */
57659   __I  uint64_t PM0_T1023N;                        /**< Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x290 */
57660   __I  uint64_t PM0_T1522N;                        /**< Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x298 */
57661   __I  uint64_t PM0_T1523XN;                       /**< Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x2A0 */
57662        uint8_t RESERVED_15[24];
57663   __I  uint64_t PM0_TCNPN;                         /**< Port MAC 0 Transmit Control Packet Counter Register, offset: 0x2C0 */
57664        uint8_t RESERVED_16[8];
57665   __I  uint64_t PM0_TDFRN;                         /**< Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x2D0 */
57666   __I  uint64_t PM0_TMCOLN;                        /**< Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x2D8 */
57667   __I  uint64_t PM0_TSCOLN;                        /**< Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x2E0 */
57668   __I  uint64_t PM0_TLCOLN;                        /**< Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x2E8 */
57669   __I  uint64_t PM0_TECOLN;                        /**< Port MAC 0 Transmit Excessive Collisions Counter Register, offset: 0x2F0 */
57670        uint8_t RESERVED_17[8];
57671   __IO uint32_t PM0_IF_MODE;                       /**< Port MAC 0 Interface Mode Control Register, offset: 0x300 */
57672        uint8_t RESERVED_18[260];
57673   __IO uint32_t PM1_COMMAND_CONFIG;                /**< Port MAC 1 Command and Configuration Register, offset: 0x408 */
57674   __I  uint32_t PM1_MAC_ADDR_0;                    /**< Port MAC 1 MAC Address Register 0, offset: 0x40C */
57675   __I  uint32_t PM1_MAC_ADDR_1;                    /**< Port MAC 1 MAC Address Register 1, offset: 0x410 */
57676   __IO uint32_t PM1_MAXFRM;                        /**< Port MAC 1 Maximum Frame Length Register, offset: 0x414 */
57677   __IO uint32_t PM1_MINFRM;                        /**< Port MAC 1 Minimum Frame Length Register, offset: 0x418 */
57678        uint8_t RESERVED_19[36];
57679   __IO uint32_t PM1_IEVENT;                        /**< Port MAC 1 Interrupt Event Register, offset: 0x440 */
57680   __IO uint32_t PM1_TX_IPG_PREAMBLE;               /**< Port MAC 1 Transmit Inter-Packet Gap Length and Flexible Preamble length Register, offset: 0x444 */
57681        uint8_t RESERVED_20[4];
57682   __IO uint32_t PM1_IMASK;                         /**< Port MAC 1 Interrupt Mask Register(INT_MASK), offset: 0x44C */
57683        uint8_t RESERVED_21[4];
57684   __IO uint32_t PM1_PAUSE_QUANTA;                  /**< Port MAC 1 Pause Quanta Register, offset: 0x454 */
57685        uint8_t RESERVED_22[12];
57686   __IO uint32_t PM1_PAUSE_THRESH;                  /**< Port MAC 1 Pause Quanta Threshold Register, offset: 0x464 */
57687        uint8_t RESERVED_23[12];
57688   __I  uint32_t PM1_RX_PAUSE_STATUS;               /**< Port MAC 1 Receive Pause Status Register, offset: 0x474 */
57689        uint8_t RESERVED_24[64];
57690   __IO uint32_t PM1_LPWAKE_TIMER;                  /**< Port MAC 1 EEE Low Power Wakeup Timer Register, offset: 0x4B8 */
57691   __IO uint32_t PM1_SLEEP_TIMER;                   /**< Port MAC 1 Transmit EEE Low Power Timer Register, offset: 0x4BC */
57692   __IO uint32_t PM1_SINGLE_STEP;                   /**< Port MAC 1 IEEE1588 Single-Step Control Register, offset: 0x4C0 */
57693        uint8_t RESERVED_25[12];
57694   __IO uint32_t PM1_HD_BACKOFF_ENTROPY;            /**< Port MAC 1 half-duplex backoff entropy register, offset: 0x4D0 */
57695   __IO uint32_t PM1_HD_FLOW_CTRL;                  /**< Port MAC 1 Half-Duplex Flow Control Register, offset: 0x4D4 */
57696        uint8_t RESERVED_26[8];
57697   __IO uint32_t PM1_STATN_CONFIG;                  /**< Port MAC 1 Statistics Configuration Register, offset: 0x4E0 */
57698        uint8_t RESERVED_27[28];
57699   __I  uint64_t PM1_REOCTN;                        /**< Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x500 */
57700   __I  uint64_t PM1_ROCTN;                         /**< Port MAC 1 Receive Octets Counter(iflnOctetsn), offset: 0x508 */
57701        uint8_t RESERVED_28[8];
57702   __I  uint64_t PM1_RXPFN;                         /**< Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x518 */
57703   __I  uint64_t PM1_RFRMN;                         /**< Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x520 */
57704   __I  uint64_t PM1_RFCSN;                         /**< Port MAC 1 Receive Frame Check Sequence Error Counter Register(), offset: 0x528 */
57705   __I  uint64_t PM1_RVLANN;                        /**< Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x530 */
57706   __I  uint64_t PM1_RERRN;                         /**< Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x538 */
57707   __I  uint64_t PM1_RUCAN;                         /**< Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x540 */
57708   __I  uint64_t PM1_RMCAN;                         /**< Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x548 */
57709   __I  uint64_t PM1_RBCAN;                         /**< Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x550 */
57710   __I  uint64_t PM1_RDRPN;                         /**< Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x558 */
57711   __I  uint64_t PM1_RPKTN;                         /**< Port MAC 1 Receive Packets Counter Register(etherStatsPktsn), offset: 0x560 */
57712   __I  uint64_t PM1_RUNDN;                         /**< Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x568 */
57713   __I  uint64_t PM1_R64N;                          /**< Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x570 */
57714   __I  uint64_t PM1_R127N;                         /**< Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x578 */
57715   __I  uint64_t PM1_R255N;                         /**< Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x580 */
57716   __I  uint64_t PM1_R511N;                         /**< Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x588 */
57717   __I  uint64_t PM1_R1023N;                        /**< Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x590 */
57718   __I  uint64_t PM1_R1522N;                        /**< Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x598 */
57719   __I  uint64_t PM1_R1523XN;                       /**< Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x5A0 */
57720   __I  uint64_t PM1_ROVRN;                         /**< Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x5A8 */
57721   __I  uint64_t PM1_RJBRN;                         /**< Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x5B0 */
57722   __I  uint64_t PM1_RFRGN;                         /**< Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x5B8 */
57723   __I  uint64_t PM1_RCNPN;                         /**< Port MAC 1 Receive Control Packet Counter Register, offset: 0x5C0 */
57724   __I  uint64_t PM1_RDRNTPN;                       /**< Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x5C8 */
57725   __I  uint64_t PM1_RMIN63N;                       /**< Port MAC 1 Receive Valid Small Packet Counter Register, offset: 0x5D0 */
57726        uint8_t RESERVED_29[40];
57727   __I  uint64_t PM1_TEOCTN;                        /**< Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x600 */
57728   __I  uint64_t PM1_TOCTN;                         /**< Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x608 */
57729        uint8_t RESERVED_30[8];
57730   __I  uint64_t PM1_TXPFN;                         /**< Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x618 */
57731   __I  uint64_t PM1_TFRMN;                         /**< Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x620 */
57732   __I  uint64_t PM1_TFCSN;                         /**< Port MAC 1 Transmit Frame Check Sequence Error Counter Register(), offset: 0x628 */
57733   __I  uint64_t PM1_TVLANN;                        /**< Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x630 */
57734   __I  uint64_t PM1_TERRN;                         /**< Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x638 */
57735   __I  uint64_t PM1_TUCAN;                         /**< Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x640 */
57736   __I  uint64_t PM1_TMCAN;                         /**< Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x648 */
57737   __I  uint64_t PM1_TBCAN;                         /**< Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x650 */
57738        uint8_t RESERVED_31[8];
57739   __I  uint64_t PM1_TPKTN;                         /**< Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x660 */
57740   __I  uint64_t PM1_TUNDN;                         /**< Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x668 */
57741   __I  uint64_t PM1_T64N;                          /**< Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x670 */
57742   __I  uint64_t PM1_T127N;                         /**< Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x678 */
57743   __I  uint64_t PM1_T255N;                         /**< Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x680 */
57744   __I  uint64_t PM1_T511N;                         /**< Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x688 */
57745   __I  uint64_t PM1_T1023N;                        /**< Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x690 */
57746   __I  uint64_t PM1_T1522N;                        /**< Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x698 */
57747   __I  uint64_t PM1_T1523XN;                       /**< Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x6A0 */
57748        uint8_t RESERVED_32[24];
57749   __I  uint64_t PM1_TCNPN;                         /**< Port MAC 1 Transmit Control Packet Counter Register, offset: 0x6C0 */
57750        uint8_t RESERVED_33[8];
57751   __I  uint64_t PM1_TDFRN;                         /**< Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x6D0 */
57752   __I  uint64_t PM1_TMCOLN;                        /**< Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x6D8 */
57753   __I  uint64_t PM1_TSCOLN;                        /**< Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x6E0 */
57754   __I  uint64_t PM1_TLCOLN;                        /**< Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x6E8 */
57755   __I  uint64_t PM1_TECOLN;                        /**< Port MAC 1 Transmit Excessive Collisions Counter Register, offset: 0x6F0 */
57756        uint8_t RESERVED_34[8];
57757   __IO uint32_t PM1_IF_MODE;                       /**< Port MAC 1 Interface Mode Control Register, offset: 0x700 */
57758        uint8_t RESERVED_35[252];
57759   __IO uint32_t MAC_MERGE_MMCSR;                   /**< Port MAC Merge Control and Status Register, offset: 0x800 */
57760        uint8_t RESERVED_36[4];
57761   __IO uint32_t MAC_MERGE_MMFAECR;                 /**< Port MAC Merge Frame Assembly Error Count Register, offset: 0x808 */
57762   __IO uint32_t MAC_MERGE_MMFSECR;                 /**< Port MAC Merge Frame SMD Error Count Register, offset: 0x80C */
57763   __IO uint32_t MAC_MERGE_MMFAOCR;                 /**< Port MAC Merge Frame Assembly OK Count Register, offset: 0x810 */
57764   __IO uint32_t MAC_MERGE_MMFCRXR;                 /**< Port MAC Merge Fragment Count RX Register, offset: 0x814 */
57765   __IO uint32_t MAC_MERGE_MMFCTXR;                 /**< Port MAC Merge Fragment Count TX Register, offset: 0x818 */
57766   __IO uint32_t MAC_MERGE_MMHCR;                   /**< Port MAC Merge Hold Count Register, offset: 0x81C */
57767        uint8_t RESERVED_37[992];
57768   __IO uint32_t PEMDIOCR;                          /**< Port external MDIO configuration register, offset: 0xC00 */
57769   __IO uint32_t PEMDIOICR;                         /**< Port external MDIO interface control register, offset: 0xC04 */
57770   __IO uint32_t PEMDIOIDR;                         /**< Port external MDIO interface data register, offset: 0xC08 */
57771   __IO uint32_t PEMDIORAR;                         /**< Port external MDIO register address register, offset: 0xC0C */
57772   __I  uint32_t PEMDIOSR;                          /**< Port external MDIO status register, offset: 0xC10 */
57773        uint8_t RESERVED_38[12];
57774   __IO uint32_t PPSCR;                             /**< PHY status configuration register, offset: 0xC20 */
57775   __IO uint32_t PPSCTRLR;                          /**< Port PHY status control register, offset: 0xC24 */
57776   __I  uint32_t PPSDR;                             /**< Port PHY status data register, offset: 0xC28 */
57777   __IO uint32_t PPSRAR;                            /**< Port PHY status register address register, offset: 0xC2C */
57778   __IO uint32_t PPSER;                             /**< Port PHY status event register, offset: 0xC30 */
57779   __IO uint32_t PPSMR;                             /**< Port PHY status mask register, offset: 0xC34 */
57780 } NETC_ETH_LINK_Type;
57781 
57782 /* ----------------------------------------------------------------------------
57783    -- NETC_ETH_LINK Register Masks
57784    ---------------------------------------------------------------------------- */
57785 
57786 /*!
57787  * @addtogroup NETC_ETH_LINK_Register_Masks NETC_ETH_LINK Register Masks
57788  * @{
57789  */
57790 
57791 /*! @name PM0_COMMAND_CONFIG - Port MAC 0 Command and Configuration Register */
57792 /*! @{ */
57793 
57794 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_MASK (0x1U)
57795 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_SHIFT (0U)
57796 /*! TX_EN - MAC transmit path enable */
57797 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_MASK)
57798 
57799 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_MASK (0x2U)
57800 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_SHIFT (1U)
57801 /*! RX_EN - MAC receive path enable */
57802 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_MASK)
57803 
57804 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U)
57805 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U)
57806 /*! PAUSE_FWD - Terminate/forward received PAUSE frames */
57807 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK)
57808 
57809 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U)
57810 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U)
57811 /*! PAUSE_IGN - Ignore PAUSE frame quanta */
57812 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK)
57813 
57814 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U)
57815 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U)
57816 /*! TX_ADDR_INS - Transmit source MAC address insertion */
57817 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_ADDR_INS_MASK)
57818 
57819 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U)
57820 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U)
57821 /*! LOOP_ENA - Loopback enable */
57822 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_MASK)
57823 
57824 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_MASK (0x1800U)
57825 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_SHIFT (11U)
57826 /*! LPBK_MODE - Loopback mode */
57827 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_MASK)
57828 
57829 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U)
57830 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U)
57831 /*! CNT_FRM_EN - Control frame reception enable */
57832 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK)
57833 
57834 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_MASK (0x4000U)
57835 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_SHIFT (14U)
57836 /*! TS_PNT - Timestamp Point */
57837 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_MASK)
57838 
57839 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_MASK (0x8000U)
57840 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_SHIFT (15U)
57841 /*! TXP - Enable padding of frames in transmit direction (1, default). */
57842 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_MASK)
57843 
57844 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN_MASK (0x40000U)
57845 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN_SHIFT (18U)
57846 /*! HD_FCEN - Half Duplex Flow Control Enable */
57847 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_HD_FCEN_MASK)
57848 
57849 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U)
57850 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U)
57851 /*! TX_FLUSH - Tx flush */
57852 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_MASK)
57853 
57854 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U)
57855 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U)
57856 /*! TX_LOWP_ENA - Transmit Low Power Idle Enable.
57857  *  0b0..(default), the MAC operates in normal mode.
57858  *  0b1..The MAC completes the transmission of the current Frame and generates Low Power Idle Sequences to the
57859  *       line. It is advised to inspect IEVENT[TX_EMPTY] is set before enabling the LPI.
57860  */
57861 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK)
57862 
57863 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_MASK (0x4000000U)
57864 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_SHIFT (26U)
57865 /*! SWR - Software Reset. Self clearing bit. */
57866 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_MASK)
57867 
57868 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_MASK (0x10000000U)
57869 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_SHIFT (28U)
57870 /*! RX_FLUSH - Ingress flush enable */
57871 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_MASK)
57872 
57873 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U)
57874 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_SHIFT (30U)
57875 /*! TS_MODE - Transmit timestamp mode */
57876 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_MASK)
57877 
57878 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_MASK (0x80000000U)
57879 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_SHIFT (31U)
57880 /*! MG - Magic Packet detection enable. */
57881 #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_MASK)
57882 /*! @} */
57883 
57884 /*! @name PM0_MAC_ADDR_0 - Port MAC 0 MAC Address Register 0 */
57885 /*! @{ */
57886 
57887 #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU)
57888 #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U)
57889 /*! MAC_ADDR_0 - MAC address 0 */
57890 #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK)
57891 /*! @} */
57892 
57893 /*! @name PM0_MAC_ADDR_1 - Port MAC 0 MAC Address Register 1 */
57894 /*! @{ */
57895 
57896 #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU)
57897 #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U)
57898 /*! MAC_ADDR_1 - MAC address 1 */
57899 #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK)
57900 /*! @} */
57901 
57902 /*! @name PM0_MAXFRM - Port MAC 0 Maximum Frame Length Register */
57903 /*! @{ */
57904 
57905 #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_MASK     (0xFFFFU)
57906 #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_SHIFT    (0U)
57907 /*! MAXFRM - Maximum supported received frame length. */
57908 #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_SHIFT)) & NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_MASK)
57909 
57910 #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_MASK     (0xFFFF0000U)
57911 #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_SHIFT    (16U)
57912 /*! TX_MTU - Maximum transmit frame length */
57913 #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_SHIFT)) & NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_MASK)
57914 /*! @} */
57915 
57916 /*! @name PM0_MINFRM - Port MAC 0 Minimum Frame Length Register */
57917 /*! @{ */
57918 
57919 #define NETC_ETH_LINK_PM0_MINFRM_NUM_BYTES_MASK  (0x7FU)
57920 #define NETC_ETH_LINK_PM0_MINFRM_NUM_BYTES_SHIFT (0U)
57921 /*! NUM_BYTES - Receive Minimum Frame Length size in bytes. */
57922 #define NETC_ETH_LINK_PM0_MINFRM_NUM_BYTES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MINFRM_NUM_BYTES_SHIFT)) & NETC_ETH_LINK_PM0_MINFRM_NUM_BYTES_MASK)
57923 /*! @} */
57924 
57925 /*! @name PM0_MDIO_CFG - Port MAC 0 Internal MDIO Configuration Register */
57926 /*! @{ */
57927 
57928 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_MASK     (0x1U)
57929 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_SHIFT    (0U)
57930 /*! BSY2 - MDIO busy (same as bit 31) */
57931 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_MASK)
57932 
57933 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_MASK (0x1CU)
57934 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_SHIFT (2U)
57935 /*! MDIO_HOLD - MDIO hold time */
57936 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_MASK)
57937 
57938 #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_MASK  (0x20U)
57939 #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_SHIFT (5U)
57940 /*! PRE_DIS - MDIO preamble disable. */
57941 #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_MASK)
57942 
57943 #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK    (0x40U)
57944 #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_SHIFT   (6U)
57945 /*! ENC45 - Enable Clause 45 support. */
57946 #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK)
57947 
57948 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_MASK (0xFF80U)
57949 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_SHIFT (7U)
57950 /*! MDIO_CLK_DIV - MDIO clock divisor. */
57951 #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_MASK)
57952 
57953 #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM_MASK      (0x20000000U)
57954 #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM_SHIFT     (29U)
57955 /*! CIM - MDIO command completion interrupt mask. */
57956 #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_CIM_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_CIM_MASK)
57957 
57958 #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP_MASK      (0x40000000U)
57959 #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP_SHIFT     (30U)
57960 /*! CMP - MDIO command completion event. Bit is cleared by writing `1'. */
57961 #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_CMP_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_CMP_MASK)
57962 
57963 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_MASK     (0x80000000U)
57964 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_SHIFT    (31U)
57965 /*! BSY1 - MDIO busy */
57966 #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_MASK)
57967 /*! @} */
57968 
57969 /*! @name PM0_MDIO_CTL - Port MAC 0 Internal MDIO Interface Control Register */
57970 /*! @{ */
57971 
57972 #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_MASK (0x1FU)
57973 #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_SHIFT (0U)
57974 /*! DEV_ADDR - MDIO register address (Clause 22) */
57975 #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_MASK)
57976 
57977 #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_MASK (0x3E0U)
57978 #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_SHIFT (5U)
57979 /*! PORT_ADDR - MDIO PHY address (Clause 22) */
57980 #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_MASK)
57981 
57982 #define NETC_ETH_LINK_PM0_MDIO_CTL_READ_MASK     (0x8000U)
57983 #define NETC_ETH_LINK_PM0_MDIO_CTL_READ_SHIFT    (15U)
57984 /*! READ - MDIO read initiation. */
57985 #define NETC_ETH_LINK_PM0_MDIO_CTL_READ(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_READ_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_READ_MASK)
57986 
57987 #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY_MASK      (0x80000000U)
57988 #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY_SHIFT     (31U)
57989 /*! BSY - MDIO busy */
57990 #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_BSY_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_BSY_MASK)
57991 /*! @} */
57992 
57993 /*! @name PM0_MDIO_DATA - Port MAC 0 Internal MDIO Interface Data Register */
57994 /*! @{ */
57995 
57996 #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_MASK (0xFFFFU)
57997 #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_SHIFT (0U)
57998 /*! MDIO_DATA - 16-bit MDIO data. */
57999 #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_MASK)
58000 
58001 #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_MASK    (0x80000000U)
58002 #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_SHIFT   (31U)
58003 /*! BUSY - MDIO busy bit. The state of this bit is also reflected in MDIO_CFG[BSY]. */
58004 #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_MASK)
58005 /*! @} */
58006 
58007 /*! @name PM0_IEVENT - Port MAC 0 Interrupt Event Register */
58008 /*! @{ */
58009 
58010 #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK   (0x20U)
58011 #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_SHIFT  (5U)
58012 /*! TX_EMPTY - Transmit fifo empty event */
58013 #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK)
58014 
58015 #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK   (0x40U)
58016 #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_SHIFT  (6U)
58017 /*! RX_EMPTY - Receive idle event */
58018 #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK)
58019 
58020 #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK    (0x400U)
58021 #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_SHIFT   (10U)
58022 /*! TX_OVFL - Transmit FIFO overflow event. */
58023 #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK)
58024 
58025 #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK    (0x800U)
58026 #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_SHIFT   (11U)
58027 /*! TX_UNFL - Transmit FIFO underflow event. */
58028 #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK)
58029 
58030 #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK    (0x1000U)
58031 #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_SHIFT   (12U)
58032 /*! RX_OVFL - Receive FIFO overflow event. */
58033 #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK)
58034 
58035 #define NETC_ETH_LINK_PM0_IEVENT_MGI_MASK        (0x4000U)
58036 #define NETC_ETH_LINK_PM0_IEVENT_MGI_SHIFT       (14U)
58037 /*! MGI - Magic packet detection indication event */
58038 #define NETC_ETH_LINK_PM0_IEVENT_MGI(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MGI_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MGI_MASK)
58039 
58040 #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK     (0x200000U)
58041 #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD_SHIFT    (21U)
58042 /*! TX_CSD - Tx Clock Stop Detection */
58043 #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK)
58044 
58045 #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK     (0x400000U)
58046 #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD_SHIFT    (22U)
58047 /*! RX_CSD - Rx Clock Stop Detection */
58048 #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK)
58049 
58050 #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK    (0x800000U)
58051 #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_SHIFT   (23U)
58052 /*! SPD_DUP - Speed/Duplex Change */
58053 #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK)
58054 
58055 #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK   (0x8000000U)
58056 #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_SHIFT  (27U)
58057 /*! MRG_SERR - MAC merge frame SMD error received event */
58058 #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK)
58059 
58060 #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK   (0x10000000U)
58061 #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_SHIFT  (28U)
58062 /*! MRG_AERR - MAC merge frame assembly error event */
58063 #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK)
58064 /*! @} */
58065 
58066 /*! @name PM0_TX_IPG_PREAMBLE - Port MAC 0 Transmit Inter-Packet Gap Length and Flexible Preamble length Register */
58067 /*! @{ */
58068 
58069 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_IPG_LEN_MASK (0x7FU)
58070 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_IPG_LEN_SHIFT (0U)
58071 /*! IPG_LEN - Transmit inter-packet gap value. */
58072 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_IPG_LEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_IPG_LEN_SHIFT)) & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_IPG_LEN_MASK)
58073 
58074 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK (0x700U)
58075 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT (8U)
58076 /*! FLEX_PREAMBLE_CNT - Flexible Preamble Count */
58077 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT)) & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK)
58078 
58079 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK (0x80000000U)
58080 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_SHIFT (31U)
58081 /*! FLEX_PREAMBLE_EN - Enable Flexible Preamble Count */
58082 #define NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_SHIFT)) & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK)
58083 /*! @} */
58084 
58085 /*! @name PM0_IMASK - Port MAC 0 Interrupt Mask Register(INT_MASK) */
58086 /*! @{ */
58087 
58088 #define NETC_ETH_LINK_PM0_IMASK_MGI_MASK         (0x4000U)
58089 #define NETC_ETH_LINK_PM0_IMASK_MGI_SHIFT        (14U)
58090 /*! MGI - Magic packet detection indication event mask. */
58091 #define NETC_ETH_LINK_PM0_IMASK_MGI(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MGI_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MGI_MASK)
58092 
58093 #define NETC_ETH_LINK_PM0_IMASK_TX_CSD_MASK      (0x200000U)
58094 #define NETC_ETH_LINK_PM0_IMASK_TX_CSD_SHIFT     (21U)
58095 /*! TX_CSD - Tx Clock Stop Detection */
58096 #define NETC_ETH_LINK_PM0_IMASK_TX_CSD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_TX_CSD_MASK)
58097 
58098 #define NETC_ETH_LINK_PM0_IMASK_RX_CSD_MASK      (0x400000U)
58099 #define NETC_ETH_LINK_PM0_IMASK_RX_CSD_SHIFT     (22U)
58100 /*! RX_CSD - Rx Clock Stop Detection */
58101 #define NETC_ETH_LINK_PM0_IMASK_RX_CSD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_RX_CSD_MASK)
58102 
58103 #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP_MASK     (0x800000U)
58104 #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP_SHIFT    (23U)
58105 /*! SPD_DUP - Speed/Duplex change event mask. */
58106 #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_SPD_DUP_MASK)
58107 
58108 #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR_MASK    (0x8000000U)
58109 #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR_SHIFT   (27U)
58110 /*! MRG_SERR - MAC merge frame SMD error received event interrupt mask */
58111 #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MRG_SERR_MASK)
58112 
58113 #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR_MASK    (0x10000000U)
58114 #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR_SHIFT   (28U)
58115 /*! MRG_AERR - MAC merge frame assembly error event interrupt mask */
58116 #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MRG_AERR_MASK)
58117 /*! @} */
58118 
58119 /*! @name PM0_PAUSE_QUANTA - Port MAC 0 Pause Quanta Register */
58120 /*! @{ */
58121 
58122 #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_MASK (0xFFFFU)
58123 #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_SHIFT (0U)
58124 /*! PQNT - Value to be used for the quanta value when XOFF is triggered. */
58125 #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_SHIFT)) & NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_MASK)
58126 /*! @} */
58127 
58128 /*! @name PM0_PAUSE_THRESH - Port MAC 0 Pause Quanta Threshold Register */
58129 /*! @{ */
58130 
58131 #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_MASK  (0xFFFFU)
58132 #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_SHIFT (0U)
58133 /*! QTH - Quanta threshold. */
58134 #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_SHIFT)) & NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_MASK)
58135 /*! @} */
58136 
58137 /*! @name PM0_RX_PAUSE_STATUS - Port MAC 0 Receive Pause Status Register */
58138 /*! @{ */
58139 
58140 #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_MASK (0x1U)
58141 #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT (0U)
58142 /*! PSTAT - Pause status. */
58143 #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT)) & NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_MASK)
58144 /*! @} */
58145 
58146 /*! @name PM0_LPWAKE_TIMER - Port MAC 0 EEE Low Power Wakeup Timer Register */
58147 /*! @{ */
58148 
58149 #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU)
58150 #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U)
58151 /*! TW_SYS_TX - EEE System transmit wait time */
58152 #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK)
58153 /*! @} */
58154 
58155 /*! @name PM0_SLEEP_TIMER - Port MAC 0 Transmit EEE Low Power Timer Register */
58156 /*! @{ */
58157 
58158 #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU)
58159 #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_SHIFT (0U)
58160 #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_SHIFT)) & NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_MASK)
58161 /*! @} */
58162 
58163 /*! @name PM0_SINGLE_STEP - Port MAC 0 IEEE1588 Single-Step Control Register */
58164 /*! @{ */
58165 
58166 #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH_MASK    (0x40U)
58167 #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH_SHIFT   (6U)
58168 /*! CH - Checksum update */
58169 #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_CH_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_CH_MASK)
58170 
58171 #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_MASK (0xFF80U)
58172 #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_SHIFT (7U)
58173 #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_MASK)
58174 
58175 #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN_MASK    (0x80000000U)
58176 #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN_SHIFT   (31U)
58177 /*! EN - IEEE-1588 Single-Step enable. */
58178 #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_EN_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_EN_MASK)
58179 /*! @} */
58180 
58181 /*! @name PM0_HD_BACKOFF_ENTROPY - Port MAC 0 half-duplex backoff entropy register */
58182 /*! @{ */
58183 
58184 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU)
58185 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U)
58186 /*! HD_BACKOFF_ENTROPY - Half duplex backoff entropy */
58187 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK)
58188 
58189 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U)
58190 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U)
58191 /*! SW_ENTROPY_VALID - SW programmable entropy valid */
58192 #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK)
58193 /*! @} */
58194 
58195 /*! @name PM0_HD_FLOW_CTRL - Port MAC 0 Half-Duplex Flow Control Register */
58196 /*! @{ */
58197 
58198 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK (0xFFFU)
58199 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT (0U)
58200 /*! HD_BP_OFF_MIN - Half-Duplex Back-Pressure Off Minimum */
58201 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT)) & NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK)
58202 
58203 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK (0xFFF0000U)
58204 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT (16U)
58205 /*! HD_BP_ON_MAX - Half-Duplex Back-Pressure On Maximum */
58206 #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT)) & NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK)
58207 /*! @} */
58208 
58209 /*! @name PM0_STATN_CONFIG - Port MAC 0 Statistics Configuration Register */
58210 /*! @{ */
58211 
58212 #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_MASK  (0x1U)
58213 #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_SHIFT (0U)
58214 #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_MASK)
58215 
58216 #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD_MASK  (0x2U)
58217 #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD_SHIFT (1U)
58218 #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_COD_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_COD_MASK)
58219 
58220 #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_MASK  (0x4U)
58221 #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_SHIFT (2U)
58222 #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_MASK)
58223 
58224 #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_MASK  (0x8U)
58225 #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_SHIFT (3U)
58226 /*! WEN - Write enable for Tx/Rx stats registers */
58227 #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_MASK)
58228 /*! @} */
58229 
58230 /*! @name PM0_REOCTN - Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn) */
58231 /*! @{ */
58232 
58233 #define NETC_ETH_LINK_PM0_REOCTN_REOCTn_MASK     (0xFFFFFFFFFFFFFFFFU)
58234 #define NETC_ETH_LINK_PM0_REOCTN_REOCTn_SHIFT    (0U)
58235 /*! REOCTn - Incremented for each octet received in both good and bad packets. */
58236 #define NETC_ETH_LINK_PM0_REOCTN_REOCTn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_REOCTN_REOCTn_SHIFT)) & NETC_ETH_LINK_PM0_REOCTN_REOCTn_MASK)
58237 /*! @} */
58238 
58239 /*! @name PM0_ROCTN - Port MAC 0 Receive Octets Counter(iflnOctetsn) */
58240 /*! @{ */
58241 
58242 #define NETC_ETH_LINK_PM0_ROCTN_ROCTn_MASK       (0xFFFFFFFFFFFFFFFFU)
58243 #define NETC_ETH_LINK_PM0_ROCTN_ROCTn_SHIFT      (0U)
58244 /*! ROCTn - Incremented for each octet received except preamble (that is, Header, Payload, Pad and
58245  *    FCS) for all valid frames and valid PAUSE frames received.
58246  */
58247 #define NETC_ETH_LINK_PM0_ROCTN_ROCTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_ROCTN_ROCTn_SHIFT)) & NETC_ETH_LINK_PM0_ROCTN_ROCTn_MASK)
58248 /*! @} */
58249 
58250 /*! @name PM0_RXPFN - Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */
58251 /*! @{ */
58252 
58253 #define NETC_ETH_LINK_PM0_RXPFN_RXPFn_MASK       (0xFFFFFFFFFFFFFFFFU)
58254 #define NETC_ETH_LINK_PM0_RXPFN_RXPFn_SHIFT      (0U)
58255 /*! RXPFn - Incremented for each valid PAUSE frame received . */
58256 #define NETC_ETH_LINK_PM0_RXPFN_RXPFn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RXPFN_RXPFn_SHIFT)) & NETC_ETH_LINK_PM0_RXPFN_RXPFn_MASK)
58257 /*! @} */
58258 
58259 /*! @name PM0_RFRMN - Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn) */
58260 /*! @{ */
58261 
58262 #define NETC_ETH_LINK_PM0_RFRMN_RFRMn_MASK       (0xFFFFFFFFFFFFFFFFU)
58263 #define NETC_ETH_LINK_PM0_RFRMN_RFRMn_SHIFT      (0U)
58264 /*! RFRMn - Incremented for each frame received without error, including PAUSE frames. */
58265 #define NETC_ETH_LINK_PM0_RFRMN_RFRMn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFRMN_RFRMn_SHIFT)) & NETC_ETH_LINK_PM0_RFRMN_RFRMn_MASK)
58266 /*! @} */
58267 
58268 /*! @name PM0_RFCSN - Port MAC 0 Receive Frame Check Sequence Error Counter Register() */
58269 /*! @{ */
58270 
58271 #define NETC_ETH_LINK_PM0_RFCSN_RFCSn_MASK       (0xFFFFFFFFFFFFFFFFU)
58272 #define NETC_ETH_LINK_PM0_RFCSN_RFCSn_SHIFT      (0U)
58273 /*! RFCSn - Incremented for each frame received with a CRC-32 error but the frame is otherwise of correct length. */
58274 #define NETC_ETH_LINK_PM0_RFCSN_RFCSn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFCSN_RFCSn_SHIFT)) & NETC_ETH_LINK_PM0_RFCSN_RFCSn_MASK)
58275 /*! @} */
58276 
58277 /*! @name PM0_RVLANN - Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn) */
58278 /*! @{ */
58279 
58280 #define NETC_ETH_LINK_PM0_RVLANN_RVLANn_MASK     (0xFFFFFFFFFFFFFFFFU)
58281 #define NETC_ETH_LINK_PM0_RVLANN_RVLANn_SHIFT    (0U)
58282 /*! RVLANn - Incremented for each valid VLAN tagged frame received with ethertype 0x8100 */
58283 #define NETC_ETH_LINK_PM0_RVLANN_RVLANn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RVLANN_RVLANn_SHIFT)) & NETC_ETH_LINK_PM0_RVLANN_RVLANn_MASK)
58284 /*! @} */
58285 
58286 /*! @name PM0_RERRN - Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn) */
58287 /*! @{ */
58288 
58289 #define NETC_ETH_LINK_PM0_RERRN_RERRn_MASK       (0xFFFFFFFFFFFFFFFFU)
58290 #define NETC_ETH_LINK_PM0_RERRN_RERRn_SHIFT      (0U)
58291 /*! RERRn - Incremented for each frame received with an error (except for undersized/fragment frame): */
58292 #define NETC_ETH_LINK_PM0_RERRN_RERRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RERRN_RERRn_SHIFT)) & NETC_ETH_LINK_PM0_RERRN_RERRn_MASK)
58293 /*! @} */
58294 
58295 /*! @name PM0_RUCAN - Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn) */
58296 /*! @{ */
58297 
58298 #define NETC_ETH_LINK_PM0_RUCAN_RUCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58299 #define NETC_ETH_LINK_PM0_RUCAN_RUCAn_SHIFT      (0U)
58300 /*! RUCAn - Incremented for each valid frame received (on the receive FIFO interface) in which bit 0
58301  *    of the destination address was 0 .
58302  */
58303 #define NETC_ETH_LINK_PM0_RUCAN_RUCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RUCAN_RUCAn_SHIFT)) & NETC_ETH_LINK_PM0_RUCAN_RUCAn_MASK)
58304 /*! @} */
58305 
58306 /*! @name PM0_RMCAN - Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */
58307 /*! @{ */
58308 
58309 #define NETC_ETH_LINK_PM0_RMCAN_RMCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58310 #define NETC_ETH_LINK_PM0_RMCAN_RMCAn_SHIFT      (0U)
58311 #define NETC_ETH_LINK_PM0_RMCAN_RMCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RMCAN_RMCAn_SHIFT)) & NETC_ETH_LINK_PM0_RMCAN_RMCAn_MASK)
58312 /*! @} */
58313 
58314 /*! @name PM0_RBCAN - Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */
58315 /*! @{ */
58316 
58317 #define NETC_ETH_LINK_PM0_RBCAN_RBCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58318 #define NETC_ETH_LINK_PM0_RBCAN_RBCAn_SHIFT      (0U)
58319 /*! RBCAn - Incremented for each valid frame received (on the receive FIFO interface) in which all
58320  *    bits of the destination address were 1 .
58321  */
58322 #define NETC_ETH_LINK_PM0_RBCAN_RBCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RBCAN_RBCAn_SHIFT)) & NETC_ETH_LINK_PM0_RBCAN_RBCAn_MASK)
58323 /*! @} */
58324 
58325 /*! @name PM0_RDRPN - Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */
58326 /*! @{ */
58327 
58328 #define NETC_ETH_LINK_PM0_RDRPN_RDRPn_MASK       (0xFFFFFFFFFFFFFFFFU)
58329 #define NETC_ETH_LINK_PM0_RDRPN_RDRPn_SHIFT      (0U)
58330 #define NETC_ETH_LINK_PM0_RDRPN_RDRPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RDRPN_RDRPn_SHIFT)) & NETC_ETH_LINK_PM0_RDRPN_RDRPn_MASK)
58331 /*! @} */
58332 
58333 /*! @name PM0_RPKTN - Port MAC 0 Receive Packets Counter Register(etherStatsPktsn) */
58334 /*! @{ */
58335 
58336 #define NETC_ETH_LINK_PM0_RPKTN_RPKTn_MASK       (0xFFFFFFFFFFFFFFFFU)
58337 #define NETC_ETH_LINK_PM0_RPKTN_RPKTn_SHIFT      (0U)
58338 /*! RPKTn - Incremented for each good or bad packet received. */
58339 #define NETC_ETH_LINK_PM0_RPKTN_RPKTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RPKTN_RPKTn_SHIFT)) & NETC_ETH_LINK_PM0_RPKTN_RPKTn_MASK)
58340 /*! @} */
58341 
58342 /*! @name PM0_RUNDN - Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */
58343 /*! @{ */
58344 
58345 #define NETC_ETH_LINK_PM0_RUNDN_RUNDn_MASK       (0xFFFFFFFFFFFFFFFFU)
58346 #define NETC_ETH_LINK_PM0_RUNDN_RUNDn_SHIFT      (0U)
58347 #define NETC_ETH_LINK_PM0_RUNDN_RUNDn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RUNDN_RUNDn_SHIFT)) & NETC_ETH_LINK_PM0_RUNDN_RUNDn_MASK)
58348 /*! @} */
58349 
58350 /*! @name PM0_R64N - Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */
58351 /*! @{ */
58352 
58353 #define NETC_ETH_LINK_PM0_R64N_R64n_MASK         (0xFFFFFFFFFFFFFFFFU)
58354 #define NETC_ETH_LINK_PM0_R64N_R64n_SHIFT        (0U)
58355 /*! R64n - Incremented for each 64-octet frame received, good or bad. */
58356 #define NETC_ETH_LINK_PM0_R64N_R64n(x)           (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R64N_R64n_SHIFT)) & NETC_ETH_LINK_PM0_R64N_R64n_MASK)
58357 /*! @} */
58358 
58359 /*! @name PM0_R127N - Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */
58360 /*! @{ */
58361 
58362 #define NETC_ETH_LINK_PM0_R127N_R127n_MASK       (0xFFFFFFFFFFFFFFFFU)
58363 #define NETC_ETH_LINK_PM0_R127N_R127n_SHIFT      (0U)
58364 /*! R127n - Incremented for each 65- to 127-octet frame received, good or bad. */
58365 #define NETC_ETH_LINK_PM0_R127N_R127n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R127N_R127n_SHIFT)) & NETC_ETH_LINK_PM0_R127N_R127n_MASK)
58366 /*! @} */
58367 
58368 /*! @name PM0_R255N - Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */
58369 /*! @{ */
58370 
58371 #define NETC_ETH_LINK_PM0_R255N_R255n_MASK       (0xFFFFFFFFFFFFFFFFU)
58372 #define NETC_ETH_LINK_PM0_R255N_R255n_SHIFT      (0U)
58373 /*! R255n - Incremented for each 128- to 255-octet frame received, good or bad. */
58374 #define NETC_ETH_LINK_PM0_R255N_R255n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R255N_R255n_SHIFT)) & NETC_ETH_LINK_PM0_R255N_R255n_MASK)
58375 /*! @} */
58376 
58377 /*! @name PM0_R511N - Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */
58378 /*! @{ */
58379 
58380 #define NETC_ETH_LINK_PM0_R511N_R511n_MASK       (0xFFFFFFFFFFFFFFFFU)
58381 #define NETC_ETH_LINK_PM0_R511N_R511n_SHIFT      (0U)
58382 /*! R511n - Incremented for each 256- to 511-octet frame received, good or bad. */
58383 #define NETC_ETH_LINK_PM0_R511N_R511n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R511N_R511n_SHIFT)) & NETC_ETH_LINK_PM0_R511N_R511n_MASK)
58384 /*! @} */
58385 
58386 /*! @name PM0_R1023N - Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */
58387 /*! @{ */
58388 
58389 #define NETC_ETH_LINK_PM0_R1023N_R1023n_MASK     (0xFFFFFFFFFFFFFFFFU)
58390 #define NETC_ETH_LINK_PM0_R1023N_R1023n_SHIFT    (0U)
58391 /*! R1023n - Incremented for each 512- to 1023-octet frame received, good or bad. */
58392 #define NETC_ETH_LINK_PM0_R1023N_R1023n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1023N_R1023n_SHIFT)) & NETC_ETH_LINK_PM0_R1023N_R1023n_MASK)
58393 /*! @} */
58394 
58395 /*! @name PM0_R1522N - Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */
58396 /*! @{ */
58397 
58398 #define NETC_ETH_LINK_PM0_R1522N_R1522n_MASK     (0xFFFFFFFFFFFFFFFFU)
58399 #define NETC_ETH_LINK_PM0_R1522N_R1522n_SHIFT    (0U)
58400 /*! R1522n - Incremented for each 1024- to 1522-octet frame received, good or bad. */
58401 #define NETC_ETH_LINK_PM0_R1522N_R1522n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1522N_R1522n_SHIFT)) & NETC_ETH_LINK_PM0_R1522N_R1522n_MASK)
58402 /*! @} */
58403 
58404 /*! @name PM0_R1523XN - Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */
58405 /*! @{ */
58406 
58407 #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn_MASK   (0xFFFFFFFFFFFFFFFFU)
58408 #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn_SHIFT  (0U)
58409 #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1523XN_R1523Xn_SHIFT)) & NETC_ETH_LINK_PM0_R1523XN_R1523Xn_MASK)
58410 /*! @} */
58411 
58412 /*! @name PM0_ROVRN - Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */
58413 /*! @{ */
58414 
58415 #define NETC_ETH_LINK_PM0_ROVRN_ROVRn_MASK       (0xFFFFFFFFFFFFFFFFU)
58416 #define NETC_ETH_LINK_PM0_ROVRN_ROVRn_SHIFT      (0U)
58417 #define NETC_ETH_LINK_PM0_ROVRN_ROVRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_ROVRN_ROVRn_SHIFT)) & NETC_ETH_LINK_PM0_ROVRN_ROVRn_MASK)
58418 /*! @} */
58419 
58420 /*! @name PM0_RJBRN - Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn) */
58421 /*! @{ */
58422 
58423 #define NETC_ETH_LINK_PM0_RJBRN_RJBRn_MASK       (0xFFFFFFFFFFFFFFFFU)
58424 #define NETC_ETH_LINK_PM0_RJBRN_RJBRn_SHIFT      (0U)
58425 #define NETC_ETH_LINK_PM0_RJBRN_RJBRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RJBRN_RJBRn_SHIFT)) & NETC_ETH_LINK_PM0_RJBRN_RJBRn_MASK)
58426 /*! @} */
58427 
58428 /*! @name PM0_RFRGN - Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn */
58429 /*! @{ */
58430 
58431 #define NETC_ETH_LINK_PM0_RFRGN_RFRGn_MASK       (0xFFFFFFFFFFFFFFFFU)
58432 #define NETC_ETH_LINK_PM0_RFRGN_RFRGn_SHIFT      (0U)
58433 #define NETC_ETH_LINK_PM0_RFRGN_RFRGn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFRGN_RFRGn_SHIFT)) & NETC_ETH_LINK_PM0_RFRGN_RFRGn_MASK)
58434 /*! @} */
58435 
58436 /*! @name PM0_RCNPN - Port MAC 0 Receive Control Packet Counter Register */
58437 /*! @{ */
58438 
58439 #define NETC_ETH_LINK_PM0_RCNPN_RCNPn_MASK       (0xFFFFFFFFFFFFFFFFU)
58440 #define NETC_ETH_LINK_PM0_RCNPN_RCNPn_SHIFT      (0U)
58441 /*! RCNPn - Incremented for each valid control packet (type 0x8808) but not for PAUSE packets */
58442 #define NETC_ETH_LINK_PM0_RCNPN_RCNPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RCNPN_RCNPn_SHIFT)) & NETC_ETH_LINK_PM0_RCNPN_RCNPn_MASK)
58443 /*! @} */
58444 
58445 /*! @name PM0_RDRNTPN - Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */
58446 /*! @{ */
58447 
58448 #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_MASK   (0xFFFFFFFFFFFFFFFFU)
58449 #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_SHIFT  (0U)
58450 /*! RDRNTPn - Incremented for each fully dropped packet (not truncated) due to internal errors of
58451  *    the MAC client. Occurs when a receive FIFO overflows.
58452  */
58453 #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_SHIFT)) & NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_MASK)
58454 /*! @} */
58455 
58456 /*! @name PM0_RMIN63N - Port MAC 0 Receive Valid Small Packet Counter Register */
58457 /*! @{ */
58458 
58459 #define NETC_ETH_LINK_PM0_RMIN63N_RMIN63n_MASK   (0xFFFFFFFFFFFFFFFFU)
58460 #define NETC_ETH_LINK_PM0_RMIN63N_RMIN63n_SHIFT  (0U)
58461 /*! RMIN63n - Incremented for each valid small packet less than 64B but greater or equal to the
58462  *    length programmed in PMa_MINFRM register
58463  */
58464 #define NETC_ETH_LINK_PM0_RMIN63N_RMIN63n(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RMIN63N_RMIN63n_SHIFT)) & NETC_ETH_LINK_PM0_RMIN63N_RMIN63n_MASK)
58465 /*! @} */
58466 
58467 /*! @name PM0_TEOCTN - Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn) */
58468 /*! @{ */
58469 
58470 #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_MASK     (0xFFFFFFFFFFFFFFFFU)
58471 #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_SHIFT    (0U)
58472 /*! TEOCTn - Incremented for each octet transmitted in both good and bad packets. */
58473 #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_SHIFT)) & NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_MASK)
58474 /*! @} */
58475 
58476 /*! @name PM0_TOCTN - Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn) */
58477 /*! @{ */
58478 
58479 #define NETC_ETH_LINK_PM0_TOCTN_TOCTn_MASK       (0xFFFFFFFFFFFFFFFFU)
58480 #define NETC_ETH_LINK_PM0_TOCTN_TOCTn_SHIFT      (0U)
58481 #define NETC_ETH_LINK_PM0_TOCTN_TOCTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TOCTN_TOCTn_SHIFT)) & NETC_ETH_LINK_PM0_TOCTN_TOCTn_MASK)
58482 /*! @} */
58483 
58484 /*! @name PM0_TXPFN - Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */
58485 /*! @{ */
58486 
58487 #define NETC_ETH_LINK_PM0_TXPFN_TXPFn_MASK       (0xFFFFFFFFFFFFFFFFU)
58488 #define NETC_ETH_LINK_PM0_TXPFN_TXPFn_SHIFT      (0U)
58489 /*! TXPFn - Incremented for each valid PAUSE frame transmitted . Note: Pause frames forwarded to the
58490  *    MAC from MAC Client are not counted by TXPFn.
58491  */
58492 #define NETC_ETH_LINK_PM0_TXPFN_TXPFn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TXPFN_TXPFn_SHIFT)) & NETC_ETH_LINK_PM0_TXPFN_TXPFn_MASK)
58493 /*! @} */
58494 
58495 /*! @name PM0_TFRMN - Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn) */
58496 /*! @{ */
58497 
58498 #define NETC_ETH_LINK_PM0_TFRMN_TFRMn_MASK       (0xFFFFFFFFFFFFFFFFU)
58499 #define NETC_ETH_LINK_PM0_TFRMN_TFRMn_SHIFT      (0U)
58500 /*! TFRMn - Incremented for each frame transmitted without error, including PAUSE frames. */
58501 #define NETC_ETH_LINK_PM0_TFRMN_TFRMn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TFRMN_TFRMn_SHIFT)) & NETC_ETH_LINK_PM0_TFRMN_TFRMn_MASK)
58502 /*! @} */
58503 
58504 /*! @name PM0_TFCSN - Port MAC 0 Transmit Frame Check Sequence Error Counter Register() */
58505 /*! @{ */
58506 
58507 #define NETC_ETH_LINK_PM0_TFCSN_TFCSn_MASK       (0xFFFFFFFFFFFFFFFFU)
58508 #define NETC_ETH_LINK_PM0_TFCSN_TFCSn_SHIFT      (0U)
58509 /*! TFCSn - Incremented for each frame transmitted with a CRC-32 error except for underflows. */
58510 #define NETC_ETH_LINK_PM0_TFCSN_TFCSn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TFCSN_TFCSn_SHIFT)) & NETC_ETH_LINK_PM0_TFCSN_TFCSn_MASK)
58511 /*! @} */
58512 
58513 /*! @name PM0_TVLANN - Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */
58514 /*! @{ */
58515 
58516 #define NETC_ETH_LINK_PM0_TVLANN_TVLANn_MASK     (0xFFFFFFFFFFFFFFFFU)
58517 #define NETC_ETH_LINK_PM0_TVLANN_TVLANn_SHIFT    (0U)
58518 /*! TVLANn - Incremented for each valid VLAN tagged frame transmitted with ethertype 0x8100. */
58519 #define NETC_ETH_LINK_PM0_TVLANN_TVLANn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TVLANN_TVLANn_SHIFT)) & NETC_ETH_LINK_PM0_TVLANN_TVLANn_MASK)
58520 /*! @} */
58521 
58522 /*! @name PM0_TERRN - Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn) */
58523 /*! @{ */
58524 
58525 #define NETC_ETH_LINK_PM0_TERRN_TERRn_MASK       (0xFFFFFFFFFFFFFFFFU)
58526 #define NETC_ETH_LINK_PM0_TERRN_TERRn_SHIFT      (0U)
58527 /*! TERRn - Transmit frame error count */
58528 #define NETC_ETH_LINK_PM0_TERRN_TERRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TERRN_TERRn_SHIFT)) & NETC_ETH_LINK_PM0_TERRN_TERRn_MASK)
58529 /*! @} */
58530 
58531 /*! @name PM0_TUCAN - Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */
58532 /*! @{ */
58533 
58534 #define NETC_ETH_LINK_PM0_TUCAN_TUCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58535 #define NETC_ETH_LINK_PM0_TUCAN_TUCAn_SHIFT      (0U)
58536 /*! TUCAn - Incremented for each valid frame transmitted (to the FIFO interface) in which bit 0 of the destination address was 0. */
58537 #define NETC_ETH_LINK_PM0_TUCAN_TUCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TUCAN_TUCAn_SHIFT)) & NETC_ETH_LINK_PM0_TUCAN_TUCAn_MASK)
58538 /*! @} */
58539 
58540 /*! @name PM0_TMCAN - Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */
58541 /*! @{ */
58542 
58543 #define NETC_ETH_LINK_PM0_TMCAN_TMCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58544 #define NETC_ETH_LINK_PM0_TMCAN_TMCAn_SHIFT      (0U)
58545 #define NETC_ETH_LINK_PM0_TMCAN_TMCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TMCAN_TMCAn_SHIFT)) & NETC_ETH_LINK_PM0_TMCAN_TMCAn_MASK)
58546 /*! @} */
58547 
58548 /*! @name PM0_TBCAN - Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */
58549 /*! @{ */
58550 
58551 #define NETC_ETH_LINK_PM0_TBCAN_TBCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
58552 #define NETC_ETH_LINK_PM0_TBCAN_TBCAn_SHIFT      (0U)
58553 /*! TBCAn - Incremented for each valid frame transmitted (to the FIFO interface) in which all bits
58554  *    of the destination address were 1 .
58555  */
58556 #define NETC_ETH_LINK_PM0_TBCAN_TBCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TBCAN_TBCAn_SHIFT)) & NETC_ETH_LINK_PM0_TBCAN_TBCAn_MASK)
58557 /*! @} */
58558 
58559 /*! @name PM0_TPKTN - Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn) */
58560 /*! @{ */
58561 
58562 #define NETC_ETH_LINK_PM0_TPKTN_TPKTn_MASK       (0xFFFFFFFFFFFFFFFFU)
58563 #define NETC_ETH_LINK_PM0_TPKTN_TPKTn_SHIFT      (0U)
58564 /*! TPKTn - Incremented for each good or bad packet transmitted. */
58565 #define NETC_ETH_LINK_PM0_TPKTN_TPKTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TPKTN_TPKTn_SHIFT)) & NETC_ETH_LINK_PM0_TPKTN_TPKTn_MASK)
58566 /*! @} */
58567 
58568 /*! @name PM0_TUNDN - Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */
58569 /*! @{ */
58570 
58571 #define NETC_ETH_LINK_PM0_TUNDN_TUNDn_MASK       (0xFFFFFFFFFFFFFFFFU)
58572 #define NETC_ETH_LINK_PM0_TUNDN_TUNDn_SHIFT      (0U)
58573 /*! TUNDn - Incremented for each packet transmitted that was less than 64 octets long with a good CRC. */
58574 #define NETC_ETH_LINK_PM0_TUNDN_TUNDn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TUNDN_TUNDn_SHIFT)) & NETC_ETH_LINK_PM0_TUNDN_TUNDn_MASK)
58575 /*! @} */
58576 
58577 /*! @name PM0_T64N - Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */
58578 /*! @{ */
58579 
58580 #define NETC_ETH_LINK_PM0_T64N_T64n_MASK         (0xFFFFFFFFFFFFFFFFU)
58581 #define NETC_ETH_LINK_PM0_T64N_T64n_SHIFT        (0U)
58582 /*! T64n - Incremented for each 64-octet frame transmitted, good or bad. */
58583 #define NETC_ETH_LINK_PM0_T64N_T64n(x)           (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T64N_T64n_SHIFT)) & NETC_ETH_LINK_PM0_T64N_T64n_MASK)
58584 /*! @} */
58585 
58586 /*! @name PM0_T127N - Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */
58587 /*! @{ */
58588 
58589 #define NETC_ETH_LINK_PM0_T127N_T127n_MASK       (0xFFFFFFFFFFFFFFFFU)
58590 #define NETC_ETH_LINK_PM0_T127N_T127n_SHIFT      (0U)
58591 /*! T127n - Incremented for each 65 to 127-octet frame transmitted, good or bad. */
58592 #define NETC_ETH_LINK_PM0_T127N_T127n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T127N_T127n_SHIFT)) & NETC_ETH_LINK_PM0_T127N_T127n_MASK)
58593 /*! @} */
58594 
58595 /*! @name PM0_T255N - Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */
58596 /*! @{ */
58597 
58598 #define NETC_ETH_LINK_PM0_T255N_T255n_MASK       (0xFFFFFFFFFFFFFFFFU)
58599 #define NETC_ETH_LINK_PM0_T255N_T255n_SHIFT      (0U)
58600 /*! T255n - Incremented for each 128 to 255-octet frame transmitted, good or bad. */
58601 #define NETC_ETH_LINK_PM0_T255N_T255n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T255N_T255n_SHIFT)) & NETC_ETH_LINK_PM0_T255N_T255n_MASK)
58602 /*! @} */
58603 
58604 /*! @name PM0_T511N - Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */
58605 /*! @{ */
58606 
58607 #define NETC_ETH_LINK_PM0_T511N_T511n_MASK       (0xFFFFFFFFFFFFFFFFU)
58608 #define NETC_ETH_LINK_PM0_T511N_T511n_SHIFT      (0U)
58609 /*! T511n - Incremented for each 256 to 511-octet frame transmitted, good or bad. */
58610 #define NETC_ETH_LINK_PM0_T511N_T511n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T511N_T511n_SHIFT)) & NETC_ETH_LINK_PM0_T511N_T511n_MASK)
58611 /*! @} */
58612 
58613 /*! @name PM0_T1023N - Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */
58614 /*! @{ */
58615 
58616 #define NETC_ETH_LINK_PM0_T1023N_T1023n_MASK     (0xFFFFFFFFFFFFFFFFU)
58617 #define NETC_ETH_LINK_PM0_T1023N_T1023n_SHIFT    (0U)
58618 /*! T1023n - Incremented for each 512 to 1023-octet frame transmitted, good or bad. */
58619 #define NETC_ETH_LINK_PM0_T1023N_T1023n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1023N_T1023n_SHIFT)) & NETC_ETH_LINK_PM0_T1023N_T1023n_MASK)
58620 /*! @} */
58621 
58622 /*! @name PM0_T1522N - Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */
58623 /*! @{ */
58624 
58625 #define NETC_ETH_LINK_PM0_T1522N_T1522n_MASK     (0xFFFFFFFFFFFFFFFFU)
58626 #define NETC_ETH_LINK_PM0_T1522N_T1522n_SHIFT    (0U)
58627 /*! T1522n - Incremented for each 1024- to 1522-octet frame transmitted, good or bad. */
58628 #define NETC_ETH_LINK_PM0_T1522N_T1522n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1522N_T1522n_SHIFT)) & NETC_ETH_LINK_PM0_T1522N_T1522n_MASK)
58629 /*! @} */
58630 
58631 /*! @name PM0_T1523XN - Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */
58632 /*! @{ */
58633 
58634 #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn_MASK   (0xFFFFFFFFFFFFFFFFU)
58635 #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn_SHIFT  (0U)
58636 #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1523XN_T1523Xn_SHIFT)) & NETC_ETH_LINK_PM0_T1523XN_T1523Xn_MASK)
58637 /*! @} */
58638 
58639 /*! @name PM0_TCNPN - Port MAC 0 Transmit Control Packet Counter Register */
58640 /*! @{ */
58641 
58642 #define NETC_ETH_LINK_PM0_TCNPN_TCNPn_MASK       (0xFFFFFFFFFFFFFFFFU)
58643 #define NETC_ETH_LINK_PM0_TCNPN_TCNPn_SHIFT      (0U)
58644 /*! TCNPn - Incremented for each valid control packet transmitted (type 0x8808) but not for PAUSE packets */
58645 #define NETC_ETH_LINK_PM0_TCNPN_TCNPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TCNPN_TCNPn_SHIFT)) & NETC_ETH_LINK_PM0_TCNPN_TCNPn_MASK)
58646 /*! @} */
58647 
58648 /*! @name PM0_TDFRN - Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */
58649 /*! @{ */
58650 
58651 #define NETC_ETH_LINK_PM0_TDFRN_TDFRn_MASK       (0xFFFFFFFFFFFFFFFFU)
58652 #define NETC_ETH_LINK_PM0_TDFRN_TDFRn_SHIFT      (0U)
58653 /*! TDFRn - Increments for successful transmissions, without retransmits, that were deferred (half-duplex only). */
58654 #define NETC_ETH_LINK_PM0_TDFRN_TDFRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TDFRN_TDFRn_SHIFT)) & NETC_ETH_LINK_PM0_TDFRN_TDFRn_MASK)
58655 /*! @} */
58656 
58657 /*! @name PM0_TMCOLN - Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */
58658 /*! @{ */
58659 
58660 #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
58661 #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_SHIFT    (0U)
58662 /*! TMCOLn - Increments for successful transmission after more than one retransmission (half-duplex only). */
58663 #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_MASK)
58664 /*! @} */
58665 
58666 /*! @name PM0_TSCOLN - Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register */
58667 /*! @{ */
58668 
58669 #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
58670 #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_SHIFT    (0U)
58671 /*! TSCOLn - Increments for successful transmission after one retransmission (half-duplex only). */
58672 #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_MASK)
58673 /*! @} */
58674 
58675 /*! @name PM0_TLCOLN - Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register */
58676 /*! @{ */
58677 
58678 #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
58679 #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_SHIFT    (0U)
58680 /*! TLCOLn - Late collision occurred. Frame corrupted / discarded (half-duplex only) */
58681 #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_MASK)
58682 /*! @} */
58683 
58684 /*! @name PM0_TECOLN - Port MAC 0 Transmit Excessive Collisions Counter Register */
58685 /*! @{ */
58686 
58687 #define NETC_ETH_LINK_PM0_TECOLN_TECOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
58688 #define NETC_ETH_LINK_PM0_TECOLN_TECOLn_SHIFT    (0U)
58689 /*! TECOLn - Excessive collisions occurred. Frame was discarded (half-duplex only) */
58690 #define NETC_ETH_LINK_PM0_TECOLN_TECOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TECOLN_TECOLn_SHIFT)) & NETC_ETH_LINK_PM0_TECOLN_TECOLn_MASK)
58691 /*! @} */
58692 
58693 /*! @name PM0_IF_MODE - Port MAC 0 Interface Mode Control Register */
58694 /*! @{ */
58695 
58696 #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE_MASK    (0x7U)
58697 #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE_SHIFT   (0U)
58698 /*! IFMODE - Interface mode */
58699 #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_IFMODE_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_IFMODE_MASK)
58700 
58701 #define NETC_ETH_LINK_PM0_IF_MODE_REVMII_MASK    (0x8U)
58702 #define NETC_ETH_LINK_PM0_IF_MODE_REVMII_SHIFT   (3U)
58703 /*! REVMII - Reverse Mode
58704  *  0b0..Reverse mode disabled - port is in MAC mode
58705  *  0b1..Reverse mode enabled - port is in PHY mode
58706  */
58707 #define NETC_ETH_LINK_PM0_IF_MODE_REVMII(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_REVMII_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_REVMII_MASK)
58708 
58709 #define NETC_ETH_LINK_PM0_IF_MODE_M10_MASK       (0x10U)
58710 #define NETC_ETH_LINK_PM0_IF_MODE_M10_SHIFT      (4U)
58711 /*! M10
58712  *  0b0..100 Mbps
58713  *  0b1..10 Mbps
58714  */
58715 #define NETC_ETH_LINK_PM0_IF_MODE_M10(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_M10_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_M10_MASK)
58716 
58717 #define NETC_ETH_LINK_PM0_IF_MODE_HD_MASK        (0x40U)
58718 #define NETC_ETH_LINK_PM0_IF_MODE_HD_SHIFT       (6U)
58719 /*! HD - Half-duplex
58720  *  0b0..full duplex
58721  *  0b1..half duplex
58722  */
58723 #define NETC_ETH_LINK_PM0_IF_MODE_HD(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_HD_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_HD_MASK)
58724 
58725 #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_MASK  (0x1000U)
58726 #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_SHIFT (12U)
58727 /*! CLK_STOP - Clock Stop
58728  *  0b0..Not stoppable
58729  *  0b1..Stoppable
58730  */
58731 #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_MASK)
58732 
58733 #define NETC_ETH_LINK_PM0_IF_MODE_SSP_MASK       (0x6000U)
58734 #define NETC_ETH_LINK_PM0_IF_MODE_SSP_SHIFT      (13U)
58735 /*! SSP - Set Speed
58736  *  0b00..100 Mbps
58737  *  0b01..10 Mbps
58738  *  0b10..1 Gbps
58739  *  0b11..reserved
58740  */
58741 #define NETC_ETH_LINK_PM0_IF_MODE_SSP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_SSP_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_SSP_MASK)
58742 /*! @} */
58743 
58744 /*! @name PM1_COMMAND_CONFIG - Port MAC 1 Command and Configuration Register */
58745 /*! @{ */
58746 
58747 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_MASK (0x1U)
58748 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_SHIFT (0U)
58749 /*! TX_EN - MAC transmit path enable */
58750 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_MASK)
58751 
58752 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_MASK (0x2U)
58753 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_SHIFT (1U)
58754 /*! RX_EN - MAC receive path enable */
58755 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_MASK)
58756 
58757 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U)
58758 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U)
58759 /*! PAUSE_FWD - Terminate/forward received PAUSE frames */
58760 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK)
58761 
58762 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U)
58763 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U)
58764 /*! PAUSE_IGN - Ignore PAUSE frame quanta */
58765 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK)
58766 
58767 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK (0x200U)
58768 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT (9U)
58769 /*! TX_ADDR_INS - Transmit source MAC address insertion */
58770 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_ADDR_INS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_ADDR_INS_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_ADDR_INS_MASK)
58771 
58772 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U)
58773 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U)
58774 /*! LOOP_ENA - Loopback enable */
58775 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_MASK)
58776 
58777 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_MASK (0x1800U)
58778 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_SHIFT (11U)
58779 /*! LPBK_MODE - Loopback mode */
58780 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_MASK)
58781 
58782 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U)
58783 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U)
58784 /*! CNT_FRM_EN - Control frame reception enable */
58785 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK)
58786 
58787 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_MASK (0x4000U)
58788 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_SHIFT (14U)
58789 /*! TS_PNT - Timestamp Point */
58790 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_MASK)
58791 
58792 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_MASK (0x8000U)
58793 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_SHIFT (15U)
58794 /*! TXP - Enable padding of frames in transmit direction (1, default). */
58795 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_MASK)
58796 
58797 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_HD_FCEN_MASK (0x40000U)
58798 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_HD_FCEN_SHIFT (18U)
58799 /*! HD_FCEN - Half Duplex Flow Control Enable */
58800 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_HD_FCEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_HD_FCEN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_HD_FCEN_MASK)
58801 
58802 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U)
58803 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U)
58804 /*! TX_FLUSH - Tx flush */
58805 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_MASK)
58806 
58807 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U)
58808 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U)
58809 /*! TX_LOWP_ENA - Transmit Low Power Idle Enable.
58810  *  0b0..(default), the MAC operates in normal mode.
58811  *  0b1..The MAC completes the transmission of the current Frame and generates Low Power Idle Sequences to the
58812  *       line. It is advised to inspect IEVENT[TX_EMPTY] is set before enabling the LPI.
58813  */
58814 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK)
58815 
58816 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_MASK (0x4000000U)
58817 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_SHIFT (26U)
58818 /*! SWR - Software Reset. Self clearing bit. */
58819 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_MASK)
58820 
58821 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_MASK (0x10000000U)
58822 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_SHIFT (28U)
58823 /*! RX_FLUSH - Ingress flush enable */
58824 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_MASK)
58825 
58826 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U)
58827 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_SHIFT (30U)
58828 /*! TS_MODE - Transmit timestamp mode */
58829 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_MASK)
58830 
58831 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_MASK (0x80000000U)
58832 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_SHIFT (31U)
58833 /*! MG - Magic Packet detection enable. */
58834 #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_MASK)
58835 /*! @} */
58836 
58837 /*! @name PM1_MAC_ADDR_0 - Port MAC 1 MAC Address Register 0 */
58838 /*! @{ */
58839 
58840 #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU)
58841 #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U)
58842 /*! MAC_ADDR_0 - MAC address 0 */
58843 #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK)
58844 /*! @} */
58845 
58846 /*! @name PM1_MAC_ADDR_1 - Port MAC 1 MAC Address Register 1 */
58847 /*! @{ */
58848 
58849 #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU)
58850 #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U)
58851 /*! MAC_ADDR_1 - MAC address 1 */
58852 #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK)
58853 /*! @} */
58854 
58855 /*! @name PM1_MAXFRM - Port MAC 1 Maximum Frame Length Register */
58856 /*! @{ */
58857 
58858 #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_MASK     (0xFFFFU)
58859 #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_SHIFT    (0U)
58860 /*! MAXFRM - Maximum supported received frame length. */
58861 #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_SHIFT)) & NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_MASK)
58862 
58863 #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_MASK     (0xFFFF0000U)
58864 #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_SHIFT    (16U)
58865 /*! TX_MTU - Maximum transmit frame length */
58866 #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_SHIFT)) & NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_MASK)
58867 /*! @} */
58868 
58869 /*! @name PM1_MINFRM - Port MAC 1 Minimum Frame Length Register */
58870 /*! @{ */
58871 
58872 #define NETC_ETH_LINK_PM1_MINFRM_NUM_BYTES_MASK  (0x7FU)
58873 #define NETC_ETH_LINK_PM1_MINFRM_NUM_BYTES_SHIFT (0U)
58874 /*! NUM_BYTES - Receive Minimum Frame Length size in bytes. */
58875 #define NETC_ETH_LINK_PM1_MINFRM_NUM_BYTES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MINFRM_NUM_BYTES_SHIFT)) & NETC_ETH_LINK_PM1_MINFRM_NUM_BYTES_MASK)
58876 /*! @} */
58877 
58878 /*! @name PM1_IEVENT - Port MAC 1 Interrupt Event Register */
58879 /*! @{ */
58880 
58881 #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_MASK   (0x20U)
58882 #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_SHIFT  (5U)
58883 /*! TX_EMPTY - Transmit fifo empty event */
58884 #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_MASK)
58885 
58886 #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_MASK   (0x40U)
58887 #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_SHIFT  (6U)
58888 /*! RX_EMPTY - Receive idle event */
58889 #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_MASK)
58890 
58891 #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_MASK    (0x400U)
58892 #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_SHIFT   (10U)
58893 /*! TX_OVFL - Transmit FIFO overflow event. */
58894 #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_MASK)
58895 
58896 #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_MASK    (0x800U)
58897 #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_SHIFT   (11U)
58898 /*! TX_UNFL - Transmit FIFO underflow event. */
58899 #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_MASK)
58900 
58901 #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_MASK    (0x1000U)
58902 #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_SHIFT   (12U)
58903 /*! RX_OVFL - Receive FIFO overflow event. */
58904 #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_MASK)
58905 
58906 #define NETC_ETH_LINK_PM1_IEVENT_MGI_MASK        (0x4000U)
58907 #define NETC_ETH_LINK_PM1_IEVENT_MGI_SHIFT       (14U)
58908 /*! MGI - Magic packet detection indication event */
58909 #define NETC_ETH_LINK_PM1_IEVENT_MGI(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MGI_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MGI_MASK)
58910 
58911 #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD_MASK     (0x200000U)
58912 #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD_SHIFT    (21U)
58913 /*! TX_CSD - Tx Clock Stop Detection */
58914 #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_CSD_MASK)
58915 
58916 #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD_MASK     (0x400000U)
58917 #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD_SHIFT    (22U)
58918 /*! RX_CSD - Rx Clock Stop Detection */
58919 #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_CSD_MASK)
58920 
58921 #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_MASK    (0x800000U)
58922 #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_SHIFT   (23U)
58923 /*! SPD_DUP - Speed/Duplex Change */
58924 #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_MASK)
58925 
58926 #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_MASK   (0x8000000U)
58927 #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_SHIFT  (27U)
58928 /*! MRG_SERR - MAC merge frame SMD error received event */
58929 #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_MASK)
58930 
58931 #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_MASK   (0x10000000U)
58932 #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_SHIFT  (28U)
58933 /*! MRG_AERR - MAC merge frame assembly error event */
58934 #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_MASK)
58935 /*! @} */
58936 
58937 /*! @name PM1_TX_IPG_PREAMBLE - Port MAC 1 Transmit Inter-Packet Gap Length and Flexible Preamble length Register */
58938 /*! @{ */
58939 
58940 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_IPG_LEN_MASK (0x7FU)
58941 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_IPG_LEN_SHIFT (0U)
58942 /*! IPG_LEN - Transmit inter-packet gap value. */
58943 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_IPG_LEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_IPG_LEN_SHIFT)) & NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_IPG_LEN_MASK)
58944 
58945 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK (0x700U)
58946 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT (8U)
58947 /*! FLEX_PREAMBLE_CNT - Flexible Preamble Count */
58948 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT)) & NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK)
58949 
58950 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK (0x80000000U)
58951 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_SHIFT (31U)
58952 /*! FLEX_PREAMBLE_EN - Enable Flexible Preamble Count */
58953 #define NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_SHIFT)) & NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK)
58954 /*! @} */
58955 
58956 /*! @name PM1_IMASK - Port MAC 1 Interrupt Mask Register(INT_MASK) */
58957 /*! @{ */
58958 
58959 #define NETC_ETH_LINK_PM1_IMASK_MGI_MASK         (0x4000U)
58960 #define NETC_ETH_LINK_PM1_IMASK_MGI_SHIFT        (14U)
58961 /*! MGI - Magic packet detection indication event mask. */
58962 #define NETC_ETH_LINK_PM1_IMASK_MGI(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MGI_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MGI_MASK)
58963 
58964 #define NETC_ETH_LINK_PM1_IMASK_TX_CSD_MASK      (0x200000U)
58965 #define NETC_ETH_LINK_PM1_IMASK_TX_CSD_SHIFT     (21U)
58966 /*! TX_CSD - Tx Clock Stop Detection */
58967 #define NETC_ETH_LINK_PM1_IMASK_TX_CSD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_TX_CSD_MASK)
58968 
58969 #define NETC_ETH_LINK_PM1_IMASK_RX_CSD_MASK      (0x400000U)
58970 #define NETC_ETH_LINK_PM1_IMASK_RX_CSD_SHIFT     (22U)
58971 /*! RX_CSD - Rx Clock Stop Detection */
58972 #define NETC_ETH_LINK_PM1_IMASK_RX_CSD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_RX_CSD_MASK)
58973 
58974 #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP_MASK     (0x800000U)
58975 #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP_SHIFT    (23U)
58976 /*! SPD_DUP - Speed/Duplex change event mask. */
58977 #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_SPD_DUP_MASK)
58978 
58979 #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR_MASK    (0x8000000U)
58980 #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR_SHIFT   (27U)
58981 /*! MRG_SERR - MAC merge frame SMD error received event interrupt mask */
58982 #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MRG_SERR_MASK)
58983 
58984 #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR_MASK    (0x10000000U)
58985 #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR_SHIFT   (28U)
58986 /*! MRG_AERR - MAC merge frame assembly error event interrupt mask */
58987 #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MRG_AERR_MASK)
58988 /*! @} */
58989 
58990 /*! @name PM1_PAUSE_QUANTA - Port MAC 1 Pause Quanta Register */
58991 /*! @{ */
58992 
58993 #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_MASK (0xFFFFU)
58994 #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_SHIFT (0U)
58995 /*! PQNT - Value to be used for the quanta value when XOFF is triggered. */
58996 #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_SHIFT)) & NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_MASK)
58997 /*! @} */
58998 
58999 /*! @name PM1_PAUSE_THRESH - Port MAC 1 Pause Quanta Threshold Register */
59000 /*! @{ */
59001 
59002 #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_MASK  (0xFFFFU)
59003 #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_SHIFT (0U)
59004 /*! QTH - Quanta threshold. */
59005 #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_SHIFT)) & NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_MASK)
59006 /*! @} */
59007 
59008 /*! @name PM1_RX_PAUSE_STATUS - Port MAC 1 Receive Pause Status Register */
59009 /*! @{ */
59010 
59011 #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_MASK (0x1U)
59012 #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT (0U)
59013 /*! PSTAT - Pause status. */
59014 #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT)) & NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_MASK)
59015 /*! @} */
59016 
59017 /*! @name PM1_LPWAKE_TIMER - Port MAC 1 EEE Low Power Wakeup Timer Register */
59018 /*! @{ */
59019 
59020 #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU)
59021 #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U)
59022 /*! TW_SYS_TX - EEE System transmit wait time */
59023 #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK)
59024 /*! @} */
59025 
59026 /*! @name PM1_SLEEP_TIMER - Port MAC 1 Transmit EEE Low Power Timer Register */
59027 /*! @{ */
59028 
59029 #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU)
59030 #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_SHIFT (0U)
59031 #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_SHIFT)) & NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_MASK)
59032 /*! @} */
59033 
59034 /*! @name PM1_SINGLE_STEP - Port MAC 1 IEEE1588 Single-Step Control Register */
59035 /*! @{ */
59036 
59037 #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH_MASK    (0x40U)
59038 #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH_SHIFT   (6U)
59039 /*! CH - Checksum update */
59040 #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_CH_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_CH_MASK)
59041 
59042 #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_MASK (0xFF80U)
59043 #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_SHIFT (7U)
59044 #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_MASK)
59045 
59046 #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN_MASK    (0x80000000U)
59047 #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN_SHIFT   (31U)
59048 /*! EN - IEEE-1588 Single-Step enable. */
59049 #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_EN_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_EN_MASK)
59050 /*! @} */
59051 
59052 /*! @name PM1_HD_BACKOFF_ENTROPY - Port MAC 1 half-duplex backoff entropy register */
59053 /*! @{ */
59054 
59055 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU)
59056 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U)
59057 /*! HD_BACKOFF_ENTROPY - Half duplex backoff entropy */
59058 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK)
59059 
59060 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U)
59061 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U)
59062 /*! SW_ENTROPY_VALID - SW programmable entropy valid */
59063 #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK)
59064 /*! @} */
59065 
59066 /*! @name PM1_HD_FLOW_CTRL - Port MAC 1 Half-Duplex Flow Control Register */
59067 /*! @{ */
59068 
59069 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK (0xFFFU)
59070 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT (0U)
59071 /*! HD_BP_OFF_MIN - Half-Duplex Back-Pressure Off Minimum */
59072 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT)) & NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK)
59073 
59074 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK (0xFFF0000U)
59075 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT (16U)
59076 /*! HD_BP_ON_MAX - Half-Duplex Back-Pressure On Maximum */
59077 #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT)) & NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK)
59078 /*! @} */
59079 
59080 /*! @name PM1_STATN_CONFIG - Port MAC 1 Statistics Configuration Register */
59081 /*! @{ */
59082 
59083 #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_MASK  (0x1U)
59084 #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_SHIFT (0U)
59085 #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_MASK)
59086 
59087 #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD_MASK  (0x2U)
59088 #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD_SHIFT (1U)
59089 #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_COD_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_COD_MASK)
59090 
59091 #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_MASK  (0x4U)
59092 #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_SHIFT (2U)
59093 #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_MASK)
59094 
59095 #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_MASK  (0x8U)
59096 #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_SHIFT (3U)
59097 /*! WEN - Write enable for Tx/Rx stats registers */
59098 #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_MASK)
59099 /*! @} */
59100 
59101 /*! @name PM1_REOCTN - Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn) */
59102 /*! @{ */
59103 
59104 #define NETC_ETH_LINK_PM1_REOCTN_REOCTn_MASK     (0xFFFFFFFFFFFFFFFFU)
59105 #define NETC_ETH_LINK_PM1_REOCTN_REOCTn_SHIFT    (0U)
59106 /*! REOCTn - Incremented for each octet received in both good and bad packets. */
59107 #define NETC_ETH_LINK_PM1_REOCTN_REOCTn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_REOCTN_REOCTn_SHIFT)) & NETC_ETH_LINK_PM1_REOCTN_REOCTn_MASK)
59108 /*! @} */
59109 
59110 /*! @name PM1_ROCTN - Port MAC 1 Receive Octets Counter(iflnOctetsn) */
59111 /*! @{ */
59112 
59113 #define NETC_ETH_LINK_PM1_ROCTN_ROCTn_MASK       (0xFFFFFFFFFFFFFFFFU)
59114 #define NETC_ETH_LINK_PM1_ROCTN_ROCTn_SHIFT      (0U)
59115 /*! ROCTn - Incremented for each octet received except preamble (that is, Header, Payload, Pad and
59116  *    FCS) for all valid frames and valid PAUSE frames received.
59117  */
59118 #define NETC_ETH_LINK_PM1_ROCTN_ROCTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_ROCTN_ROCTn_SHIFT)) & NETC_ETH_LINK_PM1_ROCTN_ROCTn_MASK)
59119 /*! @} */
59120 
59121 /*! @name PM1_RXPFN - Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */
59122 /*! @{ */
59123 
59124 #define NETC_ETH_LINK_PM1_RXPFN_RXPFn_MASK       (0xFFFFFFFFFFFFFFFFU)
59125 #define NETC_ETH_LINK_PM1_RXPFN_RXPFn_SHIFT      (0U)
59126 /*! RXPFn - Incremented for each valid PAUSE frame received . */
59127 #define NETC_ETH_LINK_PM1_RXPFN_RXPFn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RXPFN_RXPFn_SHIFT)) & NETC_ETH_LINK_PM1_RXPFN_RXPFn_MASK)
59128 /*! @} */
59129 
59130 /*! @name PM1_RFRMN - Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn) */
59131 /*! @{ */
59132 
59133 #define NETC_ETH_LINK_PM1_RFRMN_RFRMn_MASK       (0xFFFFFFFFFFFFFFFFU)
59134 #define NETC_ETH_LINK_PM1_RFRMN_RFRMn_SHIFT      (0U)
59135 /*! RFRMn - Incremented for each frame received without error, including PAUSE frames. */
59136 #define NETC_ETH_LINK_PM1_RFRMN_RFRMn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFRMN_RFRMn_SHIFT)) & NETC_ETH_LINK_PM1_RFRMN_RFRMn_MASK)
59137 /*! @} */
59138 
59139 /*! @name PM1_RFCSN - Port MAC 1 Receive Frame Check Sequence Error Counter Register() */
59140 /*! @{ */
59141 
59142 #define NETC_ETH_LINK_PM1_RFCSN_RFCSn_MASK       (0xFFFFFFFFFFFFFFFFU)
59143 #define NETC_ETH_LINK_PM1_RFCSN_RFCSn_SHIFT      (0U)
59144 /*! RFCSn - Incremented for each frame received with a CRC-32 error but the frame is otherwise of correct length. */
59145 #define NETC_ETH_LINK_PM1_RFCSN_RFCSn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFCSN_RFCSn_SHIFT)) & NETC_ETH_LINK_PM1_RFCSN_RFCSn_MASK)
59146 /*! @} */
59147 
59148 /*! @name PM1_RVLANN - Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn) */
59149 /*! @{ */
59150 
59151 #define NETC_ETH_LINK_PM1_RVLANN_RVLANn_MASK     (0xFFFFFFFFFFFFFFFFU)
59152 #define NETC_ETH_LINK_PM1_RVLANN_RVLANn_SHIFT    (0U)
59153 /*! RVLANn - Incremented for each valid VLAN tagged frame received with ethertype 0x8100 */
59154 #define NETC_ETH_LINK_PM1_RVLANN_RVLANn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RVLANN_RVLANn_SHIFT)) & NETC_ETH_LINK_PM1_RVLANN_RVLANn_MASK)
59155 /*! @} */
59156 
59157 /*! @name PM1_RERRN - Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn) */
59158 /*! @{ */
59159 
59160 #define NETC_ETH_LINK_PM1_RERRN_RERRn_MASK       (0xFFFFFFFFFFFFFFFFU)
59161 #define NETC_ETH_LINK_PM1_RERRN_RERRn_SHIFT      (0U)
59162 /*! RERRn - Incremented for each frame received with an error (except for undersized/fragment frame): */
59163 #define NETC_ETH_LINK_PM1_RERRN_RERRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RERRN_RERRn_SHIFT)) & NETC_ETH_LINK_PM1_RERRN_RERRn_MASK)
59164 /*! @} */
59165 
59166 /*! @name PM1_RUCAN - Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn) */
59167 /*! @{ */
59168 
59169 #define NETC_ETH_LINK_PM1_RUCAN_RUCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59170 #define NETC_ETH_LINK_PM1_RUCAN_RUCAn_SHIFT      (0U)
59171 /*! RUCAn - Incremented for each valid frame received (on the receive FIFO interface) in which bit 0
59172  *    of the destination address was 0 .
59173  */
59174 #define NETC_ETH_LINK_PM1_RUCAN_RUCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RUCAN_RUCAn_SHIFT)) & NETC_ETH_LINK_PM1_RUCAN_RUCAn_MASK)
59175 /*! @} */
59176 
59177 /*! @name PM1_RMCAN - Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */
59178 /*! @{ */
59179 
59180 #define NETC_ETH_LINK_PM1_RMCAN_RMCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59181 #define NETC_ETH_LINK_PM1_RMCAN_RMCAn_SHIFT      (0U)
59182 #define NETC_ETH_LINK_PM1_RMCAN_RMCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RMCAN_RMCAn_SHIFT)) & NETC_ETH_LINK_PM1_RMCAN_RMCAn_MASK)
59183 /*! @} */
59184 
59185 /*! @name PM1_RBCAN - Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */
59186 /*! @{ */
59187 
59188 #define NETC_ETH_LINK_PM1_RBCAN_RBCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59189 #define NETC_ETH_LINK_PM1_RBCAN_RBCAn_SHIFT      (0U)
59190 /*! RBCAn - Incremented for each valid frame received (on the receive FIFO interface) in which all
59191  *    bits of the destination address were 1 .
59192  */
59193 #define NETC_ETH_LINK_PM1_RBCAN_RBCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RBCAN_RBCAn_SHIFT)) & NETC_ETH_LINK_PM1_RBCAN_RBCAn_MASK)
59194 /*! @} */
59195 
59196 /*! @name PM1_RDRPN - Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */
59197 /*! @{ */
59198 
59199 #define NETC_ETH_LINK_PM1_RDRPN_RDRPn_MASK       (0xFFFFFFFFFFFFFFFFU)
59200 #define NETC_ETH_LINK_PM1_RDRPN_RDRPn_SHIFT      (0U)
59201 #define NETC_ETH_LINK_PM1_RDRPN_RDRPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RDRPN_RDRPn_SHIFT)) & NETC_ETH_LINK_PM1_RDRPN_RDRPn_MASK)
59202 /*! @} */
59203 
59204 /*! @name PM1_RPKTN - Port MAC 1 Receive Packets Counter Register(etherStatsPktsn) */
59205 /*! @{ */
59206 
59207 #define NETC_ETH_LINK_PM1_RPKTN_RPKTn_MASK       (0xFFFFFFFFFFFFFFFFU)
59208 #define NETC_ETH_LINK_PM1_RPKTN_RPKTn_SHIFT      (0U)
59209 /*! RPKTn - Incremented for each good or bad packet received. */
59210 #define NETC_ETH_LINK_PM1_RPKTN_RPKTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RPKTN_RPKTn_SHIFT)) & NETC_ETH_LINK_PM1_RPKTN_RPKTn_MASK)
59211 /*! @} */
59212 
59213 /*! @name PM1_RUNDN - Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */
59214 /*! @{ */
59215 
59216 #define NETC_ETH_LINK_PM1_RUNDN_RUNDn_MASK       (0xFFFFFFFFFFFFFFFFU)
59217 #define NETC_ETH_LINK_PM1_RUNDN_RUNDn_SHIFT      (0U)
59218 #define NETC_ETH_LINK_PM1_RUNDN_RUNDn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RUNDN_RUNDn_SHIFT)) & NETC_ETH_LINK_PM1_RUNDN_RUNDn_MASK)
59219 /*! @} */
59220 
59221 /*! @name PM1_R64N - Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */
59222 /*! @{ */
59223 
59224 #define NETC_ETH_LINK_PM1_R64N_R64n_MASK         (0xFFFFFFFFFFFFFFFFU)
59225 #define NETC_ETH_LINK_PM1_R64N_R64n_SHIFT        (0U)
59226 /*! R64n - Incremented for each 64-octet frame received, good or bad. */
59227 #define NETC_ETH_LINK_PM1_R64N_R64n(x)           (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R64N_R64n_SHIFT)) & NETC_ETH_LINK_PM1_R64N_R64n_MASK)
59228 /*! @} */
59229 
59230 /*! @name PM1_R127N - Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */
59231 /*! @{ */
59232 
59233 #define NETC_ETH_LINK_PM1_R127N_R127n_MASK       (0xFFFFFFFFFFFFFFFFU)
59234 #define NETC_ETH_LINK_PM1_R127N_R127n_SHIFT      (0U)
59235 /*! R127n - Incremented for each 65- to 127-octet frame received, good or bad. */
59236 #define NETC_ETH_LINK_PM1_R127N_R127n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R127N_R127n_SHIFT)) & NETC_ETH_LINK_PM1_R127N_R127n_MASK)
59237 /*! @} */
59238 
59239 /*! @name PM1_R255N - Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */
59240 /*! @{ */
59241 
59242 #define NETC_ETH_LINK_PM1_R255N_R255n_MASK       (0xFFFFFFFFFFFFFFFFU)
59243 #define NETC_ETH_LINK_PM1_R255N_R255n_SHIFT      (0U)
59244 /*! R255n - Incremented for each 128- to 255-octet frame received, good or bad. */
59245 #define NETC_ETH_LINK_PM1_R255N_R255n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R255N_R255n_SHIFT)) & NETC_ETH_LINK_PM1_R255N_R255n_MASK)
59246 /*! @} */
59247 
59248 /*! @name PM1_R511N - Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */
59249 /*! @{ */
59250 
59251 #define NETC_ETH_LINK_PM1_R511N_R511n_MASK       (0xFFFFFFFFFFFFFFFFU)
59252 #define NETC_ETH_LINK_PM1_R511N_R511n_SHIFT      (0U)
59253 /*! R511n - Incremented for each 256- to 511-octet frame received, good or bad. */
59254 #define NETC_ETH_LINK_PM1_R511N_R511n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R511N_R511n_SHIFT)) & NETC_ETH_LINK_PM1_R511N_R511n_MASK)
59255 /*! @} */
59256 
59257 /*! @name PM1_R1023N - Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */
59258 /*! @{ */
59259 
59260 #define NETC_ETH_LINK_PM1_R1023N_R1023n_MASK     (0xFFFFFFFFFFFFFFFFU)
59261 #define NETC_ETH_LINK_PM1_R1023N_R1023n_SHIFT    (0U)
59262 /*! R1023n - Incremented for each 512- to 1023-octet frame received, good or bad. */
59263 #define NETC_ETH_LINK_PM1_R1023N_R1023n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1023N_R1023n_SHIFT)) & NETC_ETH_LINK_PM1_R1023N_R1023n_MASK)
59264 /*! @} */
59265 
59266 /*! @name PM1_R1522N - Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */
59267 /*! @{ */
59268 
59269 #define NETC_ETH_LINK_PM1_R1522N_R1522n_MASK     (0xFFFFFFFFFFFFFFFFU)
59270 #define NETC_ETH_LINK_PM1_R1522N_R1522n_SHIFT    (0U)
59271 /*! R1522n - Incremented for each 1024- to 1522-octet frame received, good or bad. */
59272 #define NETC_ETH_LINK_PM1_R1522N_R1522n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1522N_R1522n_SHIFT)) & NETC_ETH_LINK_PM1_R1522N_R1522n_MASK)
59273 /*! @} */
59274 
59275 /*! @name PM1_R1523XN - Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */
59276 /*! @{ */
59277 
59278 #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn_MASK   (0xFFFFFFFFFFFFFFFFU)
59279 #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn_SHIFT  (0U)
59280 #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1523XN_R1523Xn_SHIFT)) & NETC_ETH_LINK_PM1_R1523XN_R1523Xn_MASK)
59281 /*! @} */
59282 
59283 /*! @name PM1_ROVRN - Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */
59284 /*! @{ */
59285 
59286 #define NETC_ETH_LINK_PM1_ROVRN_ROVRn_MASK       (0xFFFFFFFFFFFFFFFFU)
59287 #define NETC_ETH_LINK_PM1_ROVRN_ROVRn_SHIFT      (0U)
59288 #define NETC_ETH_LINK_PM1_ROVRN_ROVRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_ROVRN_ROVRn_SHIFT)) & NETC_ETH_LINK_PM1_ROVRN_ROVRn_MASK)
59289 /*! @} */
59290 
59291 /*! @name PM1_RJBRN - Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn) */
59292 /*! @{ */
59293 
59294 #define NETC_ETH_LINK_PM1_RJBRN_RJBRn_MASK       (0xFFFFFFFFFFFFFFFFU)
59295 #define NETC_ETH_LINK_PM1_RJBRN_RJBRn_SHIFT      (0U)
59296 #define NETC_ETH_LINK_PM1_RJBRN_RJBRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RJBRN_RJBRn_SHIFT)) & NETC_ETH_LINK_PM1_RJBRN_RJBRn_MASK)
59297 /*! @} */
59298 
59299 /*! @name PM1_RFRGN - Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn */
59300 /*! @{ */
59301 
59302 #define NETC_ETH_LINK_PM1_RFRGN_RFRGn_MASK       (0xFFFFFFFFFFFFFFFFU)
59303 #define NETC_ETH_LINK_PM1_RFRGN_RFRGn_SHIFT      (0U)
59304 #define NETC_ETH_LINK_PM1_RFRGN_RFRGn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFRGN_RFRGn_SHIFT)) & NETC_ETH_LINK_PM1_RFRGN_RFRGn_MASK)
59305 /*! @} */
59306 
59307 /*! @name PM1_RCNPN - Port MAC 1 Receive Control Packet Counter Register */
59308 /*! @{ */
59309 
59310 #define NETC_ETH_LINK_PM1_RCNPN_RCNPn_MASK       (0xFFFFFFFFFFFFFFFFU)
59311 #define NETC_ETH_LINK_PM1_RCNPN_RCNPn_SHIFT      (0U)
59312 /*! RCNPn - Incremented for each valid control packet (type 0x8808) but not for PAUSE packets */
59313 #define NETC_ETH_LINK_PM1_RCNPN_RCNPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RCNPN_RCNPn_SHIFT)) & NETC_ETH_LINK_PM1_RCNPN_RCNPn_MASK)
59314 /*! @} */
59315 
59316 /*! @name PM1_RDRNTPN - Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */
59317 /*! @{ */
59318 
59319 #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_MASK   (0xFFFFFFFFFFFFFFFFU)
59320 #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_SHIFT  (0U)
59321 /*! RDRNTPn - Incremented for each fully dropped packet (not truncated) due to internal errors of
59322  *    the MAC client. Occurs when a receive FIFO overflows.
59323  */
59324 #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_SHIFT)) & NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_MASK)
59325 /*! @} */
59326 
59327 /*! @name PM1_RMIN63N - Port MAC 1 Receive Valid Small Packet Counter Register */
59328 /*! @{ */
59329 
59330 #define NETC_ETH_LINK_PM1_RMIN63N_RMIN63n_MASK   (0xFFFFFFFFFFFFFFFFU)
59331 #define NETC_ETH_LINK_PM1_RMIN63N_RMIN63n_SHIFT  (0U)
59332 /*! RMIN63n - Incremented for each valid small packet less than 64B but greater or equal to the
59333  *    length programmed in PMa_MINFRM register
59334  */
59335 #define NETC_ETH_LINK_PM1_RMIN63N_RMIN63n(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RMIN63N_RMIN63n_SHIFT)) & NETC_ETH_LINK_PM1_RMIN63N_RMIN63n_MASK)
59336 /*! @} */
59337 
59338 /*! @name PM1_TEOCTN - Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn) */
59339 /*! @{ */
59340 
59341 #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_MASK     (0xFFFFFFFFFFFFFFFFU)
59342 #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_SHIFT    (0U)
59343 /*! TEOCTn - Incremented for each octet transmitted in both good and bad packets. */
59344 #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_SHIFT)) & NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_MASK)
59345 /*! @} */
59346 
59347 /*! @name PM1_TOCTN - Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn) */
59348 /*! @{ */
59349 
59350 #define NETC_ETH_LINK_PM1_TOCTN_TOCTn_MASK       (0xFFFFFFFFFFFFFFFFU)
59351 #define NETC_ETH_LINK_PM1_TOCTN_TOCTn_SHIFT      (0U)
59352 #define NETC_ETH_LINK_PM1_TOCTN_TOCTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TOCTN_TOCTn_SHIFT)) & NETC_ETH_LINK_PM1_TOCTN_TOCTn_MASK)
59353 /*! @} */
59354 
59355 /*! @name PM1_TXPFN - Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */
59356 /*! @{ */
59357 
59358 #define NETC_ETH_LINK_PM1_TXPFN_TXPFn_MASK       (0xFFFFFFFFFFFFFFFFU)
59359 #define NETC_ETH_LINK_PM1_TXPFN_TXPFn_SHIFT      (0U)
59360 /*! TXPFn - Incremented for each valid PAUSE frame transmitted . Note: Pause frames forwarded to the
59361  *    MAC from MAC Client are not counted by TXPFn.
59362  */
59363 #define NETC_ETH_LINK_PM1_TXPFN_TXPFn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TXPFN_TXPFn_SHIFT)) & NETC_ETH_LINK_PM1_TXPFN_TXPFn_MASK)
59364 /*! @} */
59365 
59366 /*! @name PM1_TFRMN - Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn) */
59367 /*! @{ */
59368 
59369 #define NETC_ETH_LINK_PM1_TFRMN_TFRMn_MASK       (0xFFFFFFFFFFFFFFFFU)
59370 #define NETC_ETH_LINK_PM1_TFRMN_TFRMn_SHIFT      (0U)
59371 /*! TFRMn - Incremented for each frame transmitted without error, including PAUSE frames. */
59372 #define NETC_ETH_LINK_PM1_TFRMN_TFRMn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TFRMN_TFRMn_SHIFT)) & NETC_ETH_LINK_PM1_TFRMN_TFRMn_MASK)
59373 /*! @} */
59374 
59375 /*! @name PM1_TFCSN - Port MAC 1 Transmit Frame Check Sequence Error Counter Register() */
59376 /*! @{ */
59377 
59378 #define NETC_ETH_LINK_PM1_TFCSN_TFCSn_MASK       (0xFFFFFFFFFFFFFFFFU)
59379 #define NETC_ETH_LINK_PM1_TFCSN_TFCSn_SHIFT      (0U)
59380 /*! TFCSn - Incremented for each frame transmitted with a CRC-32 error except for underflows. */
59381 #define NETC_ETH_LINK_PM1_TFCSN_TFCSn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TFCSN_TFCSn_SHIFT)) & NETC_ETH_LINK_PM1_TFCSN_TFCSn_MASK)
59382 /*! @} */
59383 
59384 /*! @name PM1_TVLANN - Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */
59385 /*! @{ */
59386 
59387 #define NETC_ETH_LINK_PM1_TVLANN_TVLANn_MASK     (0xFFFFFFFFFFFFFFFFU)
59388 #define NETC_ETH_LINK_PM1_TVLANN_TVLANn_SHIFT    (0U)
59389 /*! TVLANn - Incremented for each valid VLAN tagged frame transmitted with ethertype 0x8100. */
59390 #define NETC_ETH_LINK_PM1_TVLANN_TVLANn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TVLANN_TVLANn_SHIFT)) & NETC_ETH_LINK_PM1_TVLANN_TVLANn_MASK)
59391 /*! @} */
59392 
59393 /*! @name PM1_TERRN - Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn) */
59394 /*! @{ */
59395 
59396 #define NETC_ETH_LINK_PM1_TERRN_TERRn_MASK       (0xFFFFFFFFFFFFFFFFU)
59397 #define NETC_ETH_LINK_PM1_TERRN_TERRn_SHIFT      (0U)
59398 /*! TERRn - Transmit frame error count */
59399 #define NETC_ETH_LINK_PM1_TERRN_TERRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TERRN_TERRn_SHIFT)) & NETC_ETH_LINK_PM1_TERRN_TERRn_MASK)
59400 /*! @} */
59401 
59402 /*! @name PM1_TUCAN - Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */
59403 /*! @{ */
59404 
59405 #define NETC_ETH_LINK_PM1_TUCAN_TUCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59406 #define NETC_ETH_LINK_PM1_TUCAN_TUCAn_SHIFT      (0U)
59407 /*! TUCAn - Incremented for each valid frame transmitted (to the FIFO interface) in which bit 0 of the destination address was 0. */
59408 #define NETC_ETH_LINK_PM1_TUCAN_TUCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TUCAN_TUCAn_SHIFT)) & NETC_ETH_LINK_PM1_TUCAN_TUCAn_MASK)
59409 /*! @} */
59410 
59411 /*! @name PM1_TMCAN - Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */
59412 /*! @{ */
59413 
59414 #define NETC_ETH_LINK_PM1_TMCAN_TMCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59415 #define NETC_ETH_LINK_PM1_TMCAN_TMCAn_SHIFT      (0U)
59416 #define NETC_ETH_LINK_PM1_TMCAN_TMCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TMCAN_TMCAn_SHIFT)) & NETC_ETH_LINK_PM1_TMCAN_TMCAn_MASK)
59417 /*! @} */
59418 
59419 /*! @name PM1_TBCAN - Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */
59420 /*! @{ */
59421 
59422 #define NETC_ETH_LINK_PM1_TBCAN_TBCAn_MASK       (0xFFFFFFFFFFFFFFFFU)
59423 #define NETC_ETH_LINK_PM1_TBCAN_TBCAn_SHIFT      (0U)
59424 /*! TBCAn - Incremented for each valid frame transmitted (to the FIFO interface) in which all bits
59425  *    of the destination address were 1 .
59426  */
59427 #define NETC_ETH_LINK_PM1_TBCAN_TBCAn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TBCAN_TBCAn_SHIFT)) & NETC_ETH_LINK_PM1_TBCAN_TBCAn_MASK)
59428 /*! @} */
59429 
59430 /*! @name PM1_TPKTN - Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn) */
59431 /*! @{ */
59432 
59433 #define NETC_ETH_LINK_PM1_TPKTN_TPKTn_MASK       (0xFFFFFFFFFFFFFFFFU)
59434 #define NETC_ETH_LINK_PM1_TPKTN_TPKTn_SHIFT      (0U)
59435 /*! TPKTn - Incremented for each good or bad packet transmitted. */
59436 #define NETC_ETH_LINK_PM1_TPKTN_TPKTn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TPKTN_TPKTn_SHIFT)) & NETC_ETH_LINK_PM1_TPKTN_TPKTn_MASK)
59437 /*! @} */
59438 
59439 /*! @name PM1_TUNDN - Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */
59440 /*! @{ */
59441 
59442 #define NETC_ETH_LINK_PM1_TUNDN_TUNDn_MASK       (0xFFFFFFFFFFFFFFFFU)
59443 #define NETC_ETH_LINK_PM1_TUNDN_TUNDn_SHIFT      (0U)
59444 /*! TUNDn - Incremented for each packet transmitted that was less than 64 octets long with a good CRC. */
59445 #define NETC_ETH_LINK_PM1_TUNDN_TUNDn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TUNDN_TUNDn_SHIFT)) & NETC_ETH_LINK_PM1_TUNDN_TUNDn_MASK)
59446 /*! @} */
59447 
59448 /*! @name PM1_T64N - Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */
59449 /*! @{ */
59450 
59451 #define NETC_ETH_LINK_PM1_T64N_T64n_MASK         (0xFFFFFFFFFFFFFFFFU)
59452 #define NETC_ETH_LINK_PM1_T64N_T64n_SHIFT        (0U)
59453 /*! T64n - Incremented for each 64-octet frame transmitted, good or bad. */
59454 #define NETC_ETH_LINK_PM1_T64N_T64n(x)           (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T64N_T64n_SHIFT)) & NETC_ETH_LINK_PM1_T64N_T64n_MASK)
59455 /*! @} */
59456 
59457 /*! @name PM1_T127N - Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */
59458 /*! @{ */
59459 
59460 #define NETC_ETH_LINK_PM1_T127N_T127n_MASK       (0xFFFFFFFFFFFFFFFFU)
59461 #define NETC_ETH_LINK_PM1_T127N_T127n_SHIFT      (0U)
59462 /*! T127n - Incremented for each 65 to 127-octet frame transmitted, good or bad. */
59463 #define NETC_ETH_LINK_PM1_T127N_T127n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T127N_T127n_SHIFT)) & NETC_ETH_LINK_PM1_T127N_T127n_MASK)
59464 /*! @} */
59465 
59466 /*! @name PM1_T255N - Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */
59467 /*! @{ */
59468 
59469 #define NETC_ETH_LINK_PM1_T255N_T255n_MASK       (0xFFFFFFFFFFFFFFFFU)
59470 #define NETC_ETH_LINK_PM1_T255N_T255n_SHIFT      (0U)
59471 /*! T255n - Incremented for each 128 to 255-octet frame transmitted, good or bad. */
59472 #define NETC_ETH_LINK_PM1_T255N_T255n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T255N_T255n_SHIFT)) & NETC_ETH_LINK_PM1_T255N_T255n_MASK)
59473 /*! @} */
59474 
59475 /*! @name PM1_T511N - Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */
59476 /*! @{ */
59477 
59478 #define NETC_ETH_LINK_PM1_T511N_T511n_MASK       (0xFFFFFFFFFFFFFFFFU)
59479 #define NETC_ETH_LINK_PM1_T511N_T511n_SHIFT      (0U)
59480 /*! T511n - Incremented for each 256 to 511-octet frame transmitted, good or bad. */
59481 #define NETC_ETH_LINK_PM1_T511N_T511n(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T511N_T511n_SHIFT)) & NETC_ETH_LINK_PM1_T511N_T511n_MASK)
59482 /*! @} */
59483 
59484 /*! @name PM1_T1023N - Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */
59485 /*! @{ */
59486 
59487 #define NETC_ETH_LINK_PM1_T1023N_T1023n_MASK     (0xFFFFFFFFFFFFFFFFU)
59488 #define NETC_ETH_LINK_PM1_T1023N_T1023n_SHIFT    (0U)
59489 /*! T1023n - Incremented for each 512 to 1023-octet frame transmitted, good or bad. */
59490 #define NETC_ETH_LINK_PM1_T1023N_T1023n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1023N_T1023n_SHIFT)) & NETC_ETH_LINK_PM1_T1023N_T1023n_MASK)
59491 /*! @} */
59492 
59493 /*! @name PM1_T1522N - Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */
59494 /*! @{ */
59495 
59496 #define NETC_ETH_LINK_PM1_T1522N_T1522n_MASK     (0xFFFFFFFFFFFFFFFFU)
59497 #define NETC_ETH_LINK_PM1_T1522N_T1522n_SHIFT    (0U)
59498 /*! T1522n - Incremented for each 1024- to 1522-octet frame transmitted, good or bad. */
59499 #define NETC_ETH_LINK_PM1_T1522N_T1522n(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1522N_T1522n_SHIFT)) & NETC_ETH_LINK_PM1_T1522N_T1522n_MASK)
59500 /*! @} */
59501 
59502 /*! @name PM1_T1523XN - Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */
59503 /*! @{ */
59504 
59505 #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn_MASK   (0xFFFFFFFFFFFFFFFFU)
59506 #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn_SHIFT  (0U)
59507 #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn(x)     (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1523XN_T1523Xn_SHIFT)) & NETC_ETH_LINK_PM1_T1523XN_T1523Xn_MASK)
59508 /*! @} */
59509 
59510 /*! @name PM1_TCNPN - Port MAC 1 Transmit Control Packet Counter Register */
59511 /*! @{ */
59512 
59513 #define NETC_ETH_LINK_PM1_TCNPN_TCNPn_MASK       (0xFFFFFFFFFFFFFFFFU)
59514 #define NETC_ETH_LINK_PM1_TCNPN_TCNPn_SHIFT      (0U)
59515 /*! TCNPn - Incremented for each valid control packet transmitted (type 0x8808) but not for PAUSE packets */
59516 #define NETC_ETH_LINK_PM1_TCNPN_TCNPn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TCNPN_TCNPn_SHIFT)) & NETC_ETH_LINK_PM1_TCNPN_TCNPn_MASK)
59517 /*! @} */
59518 
59519 /*! @name PM1_TDFRN - Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */
59520 /*! @{ */
59521 
59522 #define NETC_ETH_LINK_PM1_TDFRN_TDFRn_MASK       (0xFFFFFFFFFFFFFFFFU)
59523 #define NETC_ETH_LINK_PM1_TDFRN_TDFRn_SHIFT      (0U)
59524 /*! TDFRn - Increments for successful transmissions, without retransmits, that were deferred (half-duplex only). */
59525 #define NETC_ETH_LINK_PM1_TDFRN_TDFRn(x)         (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TDFRN_TDFRn_SHIFT)) & NETC_ETH_LINK_PM1_TDFRN_TDFRn_MASK)
59526 /*! @} */
59527 
59528 /*! @name PM1_TMCOLN - Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */
59529 /*! @{ */
59530 
59531 #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
59532 #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_SHIFT    (0U)
59533 /*! TMCOLn - Increments for successful transmission after more than one retransmission (half-duplex only). */
59534 #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_MASK)
59535 /*! @} */
59536 
59537 /*! @name PM1_TSCOLN - Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register */
59538 /*! @{ */
59539 
59540 #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
59541 #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_SHIFT    (0U)
59542 /*! TSCOLn - Increments for successful transmission after one retransmission (half-duplex only). */
59543 #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_MASK)
59544 /*! @} */
59545 
59546 /*! @name PM1_TLCOLN - Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register */
59547 /*! @{ */
59548 
59549 #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
59550 #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_SHIFT    (0U)
59551 /*! TLCOLn - Late collision occurred. Frame corrupted / discarded (half-duplex only) */
59552 #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_MASK)
59553 /*! @} */
59554 
59555 /*! @name PM1_TECOLN - Port MAC 1 Transmit Excessive Collisions Counter Register */
59556 /*! @{ */
59557 
59558 #define NETC_ETH_LINK_PM1_TECOLN_TECOLn_MASK     (0xFFFFFFFFFFFFFFFFU)
59559 #define NETC_ETH_LINK_PM1_TECOLN_TECOLn_SHIFT    (0U)
59560 /*! TECOLn - Excessive collisions occurred. Frame was discarded (half-duplex only) */
59561 #define NETC_ETH_LINK_PM1_TECOLN_TECOLn(x)       (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TECOLN_TECOLn_SHIFT)) & NETC_ETH_LINK_PM1_TECOLN_TECOLn_MASK)
59562 /*! @} */
59563 
59564 /*! @name PM1_IF_MODE - Port MAC 1 Interface Mode Control Register */
59565 /*! @{ */
59566 
59567 #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE_MASK    (0x7U)
59568 #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE_SHIFT   (0U)
59569 /*! IFMODE - Interface mode */
59570 #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_IFMODE_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_IFMODE_MASK)
59571 
59572 #define NETC_ETH_LINK_PM1_IF_MODE_REVMII_MASK    (0x8U)
59573 #define NETC_ETH_LINK_PM1_IF_MODE_REVMII_SHIFT   (3U)
59574 /*! REVMII - Reverse Mode
59575  *  0b0..Reverse mode disabled - port is in MAC mode
59576  *  0b1..Reverse mode enabled - port is in PHY mode
59577  */
59578 #define NETC_ETH_LINK_PM1_IF_MODE_REVMII(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_REVMII_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_REVMII_MASK)
59579 
59580 #define NETC_ETH_LINK_PM1_IF_MODE_M10_MASK       (0x10U)
59581 #define NETC_ETH_LINK_PM1_IF_MODE_M10_SHIFT      (4U)
59582 /*! M10
59583  *  0b0..100 Mbps
59584  *  0b1..10 Mbps
59585  */
59586 #define NETC_ETH_LINK_PM1_IF_MODE_M10(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_M10_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_M10_MASK)
59587 
59588 #define NETC_ETH_LINK_PM1_IF_MODE_HD_MASK        (0x40U)
59589 #define NETC_ETH_LINK_PM1_IF_MODE_HD_SHIFT       (6U)
59590 /*! HD - Half-duplex
59591  *  0b0..full duplex
59592  *  0b1..half duplex
59593  */
59594 #define NETC_ETH_LINK_PM1_IF_MODE_HD(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_HD_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_HD_MASK)
59595 
59596 #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_MASK  (0x1000U)
59597 #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_SHIFT (12U)
59598 /*! CLK_STOP - Clock Stop
59599  *  0b0..Not stoppable
59600  *  0b1..Stoppable
59601  */
59602 #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_MASK)
59603 
59604 #define NETC_ETH_LINK_PM1_IF_MODE_SSP_MASK       (0x6000U)
59605 #define NETC_ETH_LINK_PM1_IF_MODE_SSP_SHIFT      (13U)
59606 /*! SSP - Set Speed
59607  *  0b00..100 Mbps
59608  *  0b01..10 Mbps
59609  *  0b10..1 Gbps
59610  *  0b11..reserved
59611  */
59612 #define NETC_ETH_LINK_PM1_IF_MODE_SSP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_SSP_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_SSP_MASK)
59613 /*! @} */
59614 
59615 /*! @name MAC_MERGE_MMCSR - Port MAC Merge Control and Status Register */
59616 /*! @{ */
59617 
59618 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_MASK   (0x1U)
59619 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_SHIFT  (0U)
59620 /*! LPS - Local preemption supported */
59621 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_MASK)
59622 
59623 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_MASK   (0x2U)
59624 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_SHIFT  (1U)
59625 /*! LPE - Local preemption enabled */
59626 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_MASK)
59627 
59628 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_MASK   (0x4U)
59629 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_SHIFT  (2U)
59630 /*! LPA - Local preemption active */
59631 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_MASK)
59632 
59633 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_MASK  (0x18U)
59634 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_SHIFT (3U)
59635 /*! LAFS - Local additional fragment size */
59636 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_MASK)
59637 
59638 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_MASK   (0x20U)
59639 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_SHIFT  (5U)
59640 /*! RPS - Remote preemption supported */
59641 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_MASK)
59642 
59643 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_MASK   (0x40U)
59644 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_SHIFT  (6U)
59645 /*! RPE - Remote preemption enabled */
59646 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_MASK)
59647 
59648 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_MASK   (0x80U)
59649 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_SHIFT  (7U)
59650 /*! RPA - Remote preemption active */
59651 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_MASK)
59652 
59653 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_MASK  (0x300U)
59654 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_SHIFT (8U)
59655 /*! RAFS - Remote additional fragment size */
59656 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_MASK)
59657 
59658 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_MASK    (0x18000U)
59659 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_SHIFT   (15U)
59660 /*! ME - Merge enabled */
59661 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_MASK)
59662 
59663 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_MASK  (0x20000U)
59664 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_SHIFT (17U)
59665 /*! VDIS - Verify disabled */
59666 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_MASK)
59667 
59668 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK  (0x1C0000U)
59669 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT (18U)
59670 /*! VSTS - Verify status */
59671 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK)
59672 
59673 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK (0x600000U)
59674 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_SHIFT (21U)
59675 /*! TXSTS - Merge status */
59676 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK)
59677 
59678 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_MASK    (0x3F800000U)
59679 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_SHIFT   (23U)
59680 /*! VT - Verify Time */
59681 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_MASK)
59682 
59683 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_MASK (0x80000000U)
59684 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT (31U)
59685 /*! LINK_FAIL - Link Fail */
59686 #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_MASK)
59687 /*! @} */
59688 
59689 /*! @name MAC_MERGE_MMFAECR - Port MAC Merge Frame Assembly Error Count Register */
59690 /*! @{ */
59691 
59692 #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_MASK (0xFFFFFFFFU)
59693 #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_SHIFT (0U)
59694 #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_MASK)
59695 /*! @} */
59696 
59697 /*! @name MAC_MERGE_MMFSECR - Port MAC Merge Frame SMD Error Count Register */
59698 /*! @{ */
59699 
59700 #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_MASK (0xFFFFFFFFU)
59701 #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_SHIFT (0U)
59702 #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_MASK)
59703 /*! @} */
59704 
59705 /*! @name MAC_MERGE_MMFAOCR - Port MAC Merge Frame Assembly OK Count Register */
59706 /*! @{ */
59707 
59708 #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_MASK (0xFFFFFFFFU)
59709 #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT (0U)
59710 #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_MASK)
59711 /*! @} */
59712 
59713 /*! @name MAC_MERGE_MMFCRXR - Port MAC Merge Fragment Count RX Register */
59714 /*! @{ */
59715 
59716 #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_MASK (0xFFFFFFFFU)
59717 #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT (0U)
59718 #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_MASK)
59719 /*! @} */
59720 
59721 /*! @name MAC_MERGE_MMFCTXR - Port MAC Merge Fragment Count TX Register */
59722 /*! @{ */
59723 
59724 #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_MASK (0xFFFFFFFFU)
59725 #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT (0U)
59726 #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_MASK)
59727 /*! @} */
59728 
59729 /*! @name MAC_MERGE_MMHCR - Port MAC Merge Hold Count Register */
59730 /*! @{ */
59731 
59732 #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_MASK  (0xFFFFFFFFU)
59733 #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_SHIFT (0U)
59734 #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_MASK)
59735 /*! @} */
59736 
59737 /*! @name PEMDIOCR - Port external MDIO configuration register */
59738 /*! @{ */
59739 
59740 #define NETC_ETH_LINK_PEMDIOCR_BSY2_MASK         (0x1U)
59741 #define NETC_ETH_LINK_PEMDIOCR_BSY2_SHIFT        (0U)
59742 /*! BSY2 - Busy 2 (same as bit 31)
59743  *  0b0..An MDIO transaction is not occurring; software may access other MDIO registers.
59744  *  0b1..An MDIO transaction is occurring.
59745  */
59746 #define NETC_ETH_LINK_PEMDIOCR_BSY2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_BSY2_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_BSY2_MASK)
59747 
59748 #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_MASK   (0x2U)
59749 #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_SHIFT  (1U)
59750 /*! MDIO_RD_ER
59751  *  0b0..No error on last MDIO transaction (read or write).
59752  *  0b1..An error was detected on the last MDIO transaction (read or write). Errors on internal MDIO accesses can
59753  *       be triggered by an access to an invalid device, or by a write to a shared on-die PHY device that has not
59754  *       been locked.
59755  */
59756 #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_MASK)
59757 
59758 #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_MASK    (0x1CU)
59759 #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_SHIFT   (2U)
59760 /*! MDIO_HOLD - MDIO Hold Time
59761  *  0b000..1 NETC cycle
59762  *  0b001..3 NETC cycles
59763  *  0b010..5 NETC cycles (default - recommended value)
59764  *  0b011..7 NETC cycles
59765  *  0b100..9 NETC cycles
59766  *  0b101..11 NETC cycles
59767  *  0b110..13 NETC cycles
59768  *  0b111..15 NETC cycles
59769  */
59770 #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_MASK)
59771 
59772 #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS_MASK      (0x20U)
59773 #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS_SHIFT     (5U)
59774 /*! PRE_DIS - MDIO Preamble Disable
59775  *  0b0..Generation of MDIO preamble is enabled (default operation).
59776  *  0b1..Generation of MDIO preamble is disabled.
59777  */
59778 #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_PRE_DIS_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_PRE_DIS_MASK)
59779 
59780 #define NETC_ETH_LINK_PEMDIOCR_ENC45_MASK        (0x40U)
59781 #define NETC_ETH_LINK_PEMDIOCR_ENC45_SHIFT       (6U)
59782 /*! ENC45 - Enable Clause 45 Support
59783  *  0b0..Clause 22 transactions are used.
59784  *  0b1..Clause 45 transactions are used.
59785  */
59786 #define NETC_ETH_LINK_PEMDIOCR_ENC45(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_ENC45_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_ENC45_MASK)
59787 
59788 #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_MASK (0xFF80U)
59789 #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_SHIFT (7U)
59790 /*! MDIO_CLK_DIV - MDIO Clock Divisor */
59791 #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_MASK)
59792 
59793 #define NETC_ETH_LINK_PEMDIOCR_WHOAMI_MASK       (0x70000U)
59794 #define NETC_ETH_LINK_PEMDIOCR_WHOAMI_SHIFT      (16U)
59795 /*! WHOAMI - Returns the link ID */
59796 #define NETC_ETH_LINK_PEMDIOCR_WHOAMI(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_WHOAMI_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_WHOAMI_MASK)
59797 
59798 #define NETC_ETH_LINK_PEMDIOCR_EHOLD_MASK        (0x400000U)
59799 #define NETC_ETH_LINK_PEMDIOCR_EHOLD_SHIFT       (22U)
59800 /*! EHOLD - Extended HOLD
59801  *  0b0..Normal operation, MDIO hold time is as specified in PEMDIOCR[MDIO_HOLD].
59802  *  0b1..Extended operation
59803  */
59804 #define NETC_ETH_LINK_PEMDIOCR_EHOLD(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_EHOLD_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_EHOLD_MASK)
59805 
59806 #define NETC_ETH_LINK_PEMDIOCR_NEG_MASK          (0x800000U)
59807 #define NETC_ETH_LINK_PEMDIOCR_NEG_SHIFT         (23U)
59808 /*! NEG
59809  *  0b0..normal operation - positive edge
59810  *  0b1..MDIO is driven by master on MDC negative edge (default for external MDIOs)
59811  */
59812 #define NETC_ETH_LINK_PEMDIOCR_NEG(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_NEG_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_NEG_MASK)
59813 
59814 #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_MASK     (0x10000000U)
59815 #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_SHIFT    (28U)
59816 /*! ADDR_ERR - Address Error
59817  *  0b0..Normal
59818  *  0b1..Error. An access control violation has occurred. The request address used does not match the MDIO PHY's
59819  *       address (clause 22) or MDIO port address (clause 45) assigned.
59820  */
59821 #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_MASK)
59822 
59823 #define NETC_ETH_LINK_PEMDIOCR_CIM_MASK          (0x20000000U)
59824 #define NETC_ETH_LINK_PEMDIOCR_CIM_SHIFT         (29U)
59825 /*! CIM
59826  *  0b0..Masked
59827  *  0b1..Enabled
59828  */
59829 #define NETC_ETH_LINK_PEMDIOCR_CIM(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_CIM_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_CIM_MASK)
59830 
59831 #define NETC_ETH_LINK_PEMDIOCR_CMP_MASK          (0x40000000U)
59832 #define NETC_ETH_LINK_PEMDIOCR_CMP_SHIFT         (30U)
59833 /*! CMP - MDIO Command Completion
59834  *  0b0..An MDIO command completion did not occur.
59835  *  0b1..An MDIO command completion occurred.
59836  */
59837 #define NETC_ETH_LINK_PEMDIOCR_CMP(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_CMP_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_CMP_MASK)
59838 
59839 #define NETC_ETH_LINK_PEMDIOCR_BSY1_MASK         (0x80000000U)
59840 #define NETC_ETH_LINK_PEMDIOCR_BSY1_SHIFT        (31U)
59841 /*! BSY1 - Busy 1
59842  *  0b0..An MDIO transaction is not occurring; software may access other MDIO registers.
59843  *  0b1..An MDIO transaction is occurring.
59844  */
59845 #define NETC_ETH_LINK_PEMDIOCR_BSY1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_BSY1_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_BSY1_MASK)
59846 /*! @} */
59847 
59848 /*! @name PEMDIOICR - Port external MDIO interface control register */
59849 /*! @{ */
59850 
59851 #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_MASK    (0x1FU)
59852 #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_SHIFT   (0U)
59853 /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */
59854 #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_MASK)
59855 
59856 #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_MASK   (0x3E0U)
59857 #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_SHIFT  (5U)
59858 /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */
59859 #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_MASK)
59860 
59861 #define NETC_ETH_LINK_PEMDIOICR_POST_INC_MASK    (0x4000U)
59862 #define NETC_ETH_LINK_PEMDIOICR_POST_INC_SHIFT   (14U)
59863 /*! POST_INC - MDIO read with address post-increment initiation. Self-clearing once transaction is complete. */
59864 #define NETC_ETH_LINK_PEMDIOICR_POST_INC(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_POST_INC_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_POST_INC_MASK)
59865 
59866 #define NETC_ETH_LINK_PEMDIOICR_READ_MASK        (0x8000U)
59867 #define NETC_ETH_LINK_PEMDIOICR_READ_SHIFT       (15U)
59868 /*! READ - MDIO read initiation. */
59869 #define NETC_ETH_LINK_PEMDIOICR_READ(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_READ_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_READ_MASK)
59870 
59871 #define NETC_ETH_LINK_PEMDIOICR_BSY_MASK         (0x80000000U)
59872 #define NETC_ETH_LINK_PEMDIOICR_BSY_SHIFT        (31U)
59873 /*! BSY - MDIO busy */
59874 #define NETC_ETH_LINK_PEMDIOICR_BSY(x)           (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_BSY_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_BSY_MASK)
59875 /*! @} */
59876 
59877 /*! @name PEMDIOIDR - Port external MDIO interface data register */
59878 /*! @{ */
59879 
59880 #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_MASK   (0xFFFFU)
59881 #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_SHIFT  (0U)
59882 /*! MDIO_DATA - 16-bit MDIO data. */
59883 #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA(x)     (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_MASK)
59884 /*! @} */
59885 
59886 /*! @name PEMDIORAR - Port external MDIO register address register */
59887 /*! @{ */
59888 
59889 #define NETC_ETH_LINK_PEMDIORAR_REGADDR_MASK     (0xFFFFU)
59890 #define NETC_ETH_LINK_PEMDIORAR_REGADDR_SHIFT    (0U)
59891 /*! REGADDR - MDIO PHY register address. */
59892 #define NETC_ETH_LINK_PEMDIORAR_REGADDR(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIORAR_REGADDR_SHIFT)) & NETC_ETH_LINK_PEMDIORAR_REGADDR_MASK)
59893 /*! @} */
59894 
59895 /*! @name PEMDIOSR - Port external MDIO status register */
59896 /*! @{ */
59897 
59898 #define NETC_ETH_LINK_PEMDIOSR_BSY_MASK          (0x1U)
59899 #define NETC_ETH_LINK_PEMDIOSR_BSY_SHIFT         (0U)
59900 /*! BSY - Global MDIO busy */
59901 #define NETC_ETH_LINK_PEMDIOSR_BSY(x)            (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_BSY_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_BSY_MASK)
59902 
59903 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_MASK     (0x1F00U)
59904 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_SHIFT    (8U)
59905 /*! WHT_LIST - PHY white list */
59906 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_WHT_LIST_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_WHT_LIST_MASK)
59907 
59908 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_MASK (0x8000U)
59909 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_SHIFT (15U)
59910 /*! WHT_LIST_ENA - PHY white list enable */
59911 #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_MASK)
59912 
59913 #define NETC_ETH_LINK_PEMDIOSR_PORT_ID_MASK      (0x70000U)
59914 #define NETC_ETH_LINK_PEMDIOSR_PORT_ID_SHIFT     (16U)
59915 /*! PORT_ID - Port ID */
59916 #define NETC_ETH_LINK_PEMDIOSR_PORT_ID(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_PORT_ID_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_PORT_ID_MASK)
59917 
59918 #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_MASK     (0x80000U)
59919 #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_SHIFT    (19U)
59920 /*! REQ_TYPE - Port ID */
59921 #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_MASK)
59922 /*! @} */
59923 
59924 /*! @name PPSCR - PHY status configuration register */
59925 /*! @{ */
59926 
59927 #define NETC_ETH_LINK_PPSCR_BSY_MASK             (0x1U)
59928 #define NETC_ETH_LINK_PPSCR_BSY_SHIFT            (0U)
59929 /*! BSY - MDIO busy */
59930 #define NETC_ETH_LINK_PPSCR_BSY(x)               (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_BSY_SHIFT)) & NETC_ETH_LINK_PPSCR_BSY_MASK)
59931 
59932 #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER_MASK      (0x2U)
59933 #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER_SHIFT     (1U)
59934 /*! MDIO_RD_ER - MDIO read error */
59935 #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER(x)        (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_MDIO_RD_ER_SHIFT)) & NETC_ETH_LINK_PPSCR_MDIO_RD_ER_MASK)
59936 
59937 #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_MASK (0xFFFF0000U)
59938 #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_SHIFT (16U)
59939 /*! STATUS_INTERVAL - PHY status read interval */
59940 #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_SHIFT)) & NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_MASK)
59941 /*! @} */
59942 
59943 /*! @name PPSCTRLR - Port PHY status control register */
59944 /*! @{ */
59945 
59946 #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_MASK     (0x1FU)
59947 #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_SHIFT    (0U)
59948 /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */
59949 #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_MASK)
59950 
59951 #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_MASK    (0x3E0U)
59952 #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_SHIFT   (5U)
59953 /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */
59954 #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_MASK)
59955 /*! @} */
59956 
59957 /*! @name PPSDR - Port PHY status data register */
59958 /*! @{ */
59959 
59960 #define NETC_ETH_LINK_PPSDR_MDIO_DATA_MASK       (0xFFFFU)
59961 #define NETC_ETH_LINK_PPSDR_MDIO_DATA_SHIFT      (0U)
59962 /*! MDIO_DATA - 16-bit MDIO data */
59963 #define NETC_ETH_LINK_PPSDR_MDIO_DATA(x)         (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSDR_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PPSDR_MDIO_DATA_MASK)
59964 
59965 #define NETC_ETH_LINK_PPSDR_CURR_CNT_MASK        (0xFFFF0000U)
59966 #define NETC_ETH_LINK_PPSDR_CURR_CNT_SHIFT       (16U)
59967 /*! CURR_CNT - Current count */
59968 #define NETC_ETH_LINK_PPSDR_CURR_CNT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSDR_CURR_CNT_SHIFT)) & NETC_ETH_LINK_PPSDR_CURR_CNT_MASK)
59969 /*! @} */
59970 
59971 /*! @name PPSRAR - Port PHY status register address register */
59972 /*! @{ */
59973 
59974 #define NETC_ETH_LINK_PPSRAR_REGADDR_MASK        (0xFFFFU)
59975 #define NETC_ETH_LINK_PPSRAR_REGADDR_SHIFT       (0U)
59976 /*! REGADDR - MDIO PHY register address. Address of the register within the Clause 45 PHY device from which data is to be read. */
59977 #define NETC_ETH_LINK_PPSRAR_REGADDR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSRAR_REGADDR_SHIFT)) & NETC_ETH_LINK_PPSRAR_REGADDR_MASK)
59978 /*! @} */
59979 
59980 /*! @name PPSER - Port PHY status event register */
59981 /*! @{ */
59982 
59983 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_MASK (0xFFFFU)
59984 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_SHIFT (0U)
59985 /*! STATUS_EVENT_HL - Status event high-to-low. Set to 1 if a 1->0 transition on a corresponding data bit has occurred. Write 1 to clear. */
59986 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_SHIFT)) & NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_MASK)
59987 
59988 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_MASK (0xFFFF0000U)
59989 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_SHIFT (16U)
59990 /*! STATUS_EVENT_LH - Status event low-to-high. Set to 1 if a 0->1 transition on a corresponding data bit has occurred. Write 1 to clear. */
59991 #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_SHIFT)) & NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_MASK)
59992 /*! @} */
59993 
59994 /*! @name PPSMR - Port PHY status mask register */
59995 /*! @{ */
59996 
59997 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_MASK  (0xFFFFU)
59998 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_SHIFT (0U)
59999 /*! STATUS_MASK_HL - Status high-to-low mask. If set to 1, assert an interrupt if the corresponding event bit is set. */
60000 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_SHIFT)) & NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_MASK)
60001 
60002 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_MASK  (0xFFFF0000U)
60003 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_SHIFT (16U)
60004 /*! STATUS_MASK_LH - Status mask low-to-high. If set to 1, assert an interrupt if the corresponding event bit is set. */
60005 #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_SHIFT)) & NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_MASK)
60006 /*! @} */
60007 
60008 
60009 /*!
60010  * @}
60011  */ /* end of group NETC_ETH_LINK_Register_Masks */
60012 
60013 
60014 /* NETC_ETH_LINK - Peripheral instance base addresses */
60015 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
60016   /** Peripheral ENETC0_ETH_MAC_PORT base address */
60017   #define ENETC0_ETH_MAC_PORT_BASE                 (0x70B15000u)
60018   /** Peripheral ENETC0_ETH_MAC_PORT base address */
60019   #define ENETC0_ETH_MAC_PORT_BASE_NS              (0x60B15000u)
60020   /** Peripheral ENETC0_ETH_MAC_PORT base pointer */
60021   #define ENETC0_ETH_MAC_PORT                      ((NETC_ETH_LINK_Type *)ENETC0_ETH_MAC_PORT_BASE)
60022   /** Peripheral ENETC0_ETH_MAC_PORT base pointer */
60023   #define ENETC0_ETH_MAC_PORT_NS                   ((NETC_ETH_LINK_Type *)ENETC0_ETH_MAC_PORT_BASE_NS)
60024   /** Peripheral SW0_ETH_MAC_PORT0 base address */
60025   #define SW0_ETH_MAC_PORT0_BASE                   (0x70A05000u)
60026   /** Peripheral SW0_ETH_MAC_PORT0 base address */
60027   #define SW0_ETH_MAC_PORT0_BASE_NS                (0x60A05000u)
60028   /** Peripheral SW0_ETH_MAC_PORT0 base pointer */
60029   #define SW0_ETH_MAC_PORT0                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT0_BASE)
60030   /** Peripheral SW0_ETH_MAC_PORT0 base pointer */
60031   #define SW0_ETH_MAC_PORT0_NS                     ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT0_BASE_NS)
60032   /** Peripheral SW0_ETH_MAC_PORT1 base address */
60033   #define SW0_ETH_MAC_PORT1_BASE                   (0x70A09000u)
60034   /** Peripheral SW0_ETH_MAC_PORT1 base address */
60035   #define SW0_ETH_MAC_PORT1_BASE_NS                (0x60A09000u)
60036   /** Peripheral SW0_ETH_MAC_PORT1 base pointer */
60037   #define SW0_ETH_MAC_PORT1                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT1_BASE)
60038   /** Peripheral SW0_ETH_MAC_PORT1 base pointer */
60039   #define SW0_ETH_MAC_PORT1_NS                     ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT1_BASE_NS)
60040   /** Peripheral SW0_ETH_MAC_PORT2 base address */
60041   #define SW0_ETH_MAC_PORT2_BASE                   (0x70A0D000u)
60042   /** Peripheral SW0_ETH_MAC_PORT2 base address */
60043   #define SW0_ETH_MAC_PORT2_BASE_NS                (0x60A0D000u)
60044   /** Peripheral SW0_ETH_MAC_PORT2 base pointer */
60045   #define SW0_ETH_MAC_PORT2                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT2_BASE)
60046   /** Peripheral SW0_ETH_MAC_PORT2 base pointer */
60047   #define SW0_ETH_MAC_PORT2_NS                     ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT2_BASE_NS)
60048   /** Peripheral SW0_ETH_MAC_PORT3 base address */
60049   #define SW0_ETH_MAC_PORT3_BASE                   (0x70A11000u)
60050   /** Peripheral SW0_ETH_MAC_PORT3 base address */
60051   #define SW0_ETH_MAC_PORT3_BASE_NS                (0x60A11000u)
60052   /** Peripheral SW0_ETH_MAC_PORT3 base pointer */
60053   #define SW0_ETH_MAC_PORT3                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT3_BASE)
60054   /** Peripheral SW0_ETH_MAC_PORT3 base pointer */
60055   #define SW0_ETH_MAC_PORT3_NS                     ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT3_BASE_NS)
60056   /** Array initializer of NETC_ETH_LINK peripheral base addresses */
60057   #define NETC_ETH_LINK_BASE_ADDRS                 { ENETC0_ETH_MAC_PORT_BASE, SW0_ETH_MAC_PORT0_BASE, SW0_ETH_MAC_PORT1_BASE, SW0_ETH_MAC_PORT2_BASE, SW0_ETH_MAC_PORT3_BASE }
60058   /** Array initializer of NETC_ETH_LINK peripheral base pointers */
60059   #define NETC_ETH_LINK_BASE_PTRS                  { ENETC0_ETH_MAC_PORT, SW0_ETH_MAC_PORT0, SW0_ETH_MAC_PORT1, SW0_ETH_MAC_PORT2, SW0_ETH_MAC_PORT3 }
60060   /** Array initializer of NETC_ETH_LINK peripheral base addresses */
60061   #define NETC_ETH_LINK_BASE_ADDRS_NS              { ENETC0_ETH_MAC_PORT_BASE_NS, SW0_ETH_MAC_PORT0_BASE_NS, SW0_ETH_MAC_PORT1_BASE_NS, SW0_ETH_MAC_PORT2_BASE_NS, SW0_ETH_MAC_PORT3_BASE_NS }
60062   /** Array initializer of NETC_ETH_LINK peripheral base pointers */
60063   #define NETC_ETH_LINK_BASE_PTRS_NS               { ENETC0_ETH_MAC_PORT_NS, SW0_ETH_MAC_PORT0_NS, SW0_ETH_MAC_PORT1_NS, SW0_ETH_MAC_PORT2_NS, SW0_ETH_MAC_PORT3_NS }
60064 #else
60065   /** Peripheral ENETC0_ETH_MAC_PORT base address */
60066   #define ENETC0_ETH_MAC_PORT_BASE                 (0x60B15000u)
60067   /** Peripheral ENETC0_ETH_MAC_PORT base pointer */
60068   #define ENETC0_ETH_MAC_PORT                      ((NETC_ETH_LINK_Type *)ENETC0_ETH_MAC_PORT_BASE)
60069   /** Peripheral SW0_ETH_MAC_PORT0 base address */
60070   #define SW0_ETH_MAC_PORT0_BASE                   (0x60A05000u)
60071   /** Peripheral SW0_ETH_MAC_PORT0 base pointer */
60072   #define SW0_ETH_MAC_PORT0                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT0_BASE)
60073   /** Peripheral SW0_ETH_MAC_PORT1 base address */
60074   #define SW0_ETH_MAC_PORT1_BASE                   (0x60A09000u)
60075   /** Peripheral SW0_ETH_MAC_PORT1 base pointer */
60076   #define SW0_ETH_MAC_PORT1                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT1_BASE)
60077   /** Peripheral SW0_ETH_MAC_PORT2 base address */
60078   #define SW0_ETH_MAC_PORT2_BASE                   (0x60A0D000u)
60079   /** Peripheral SW0_ETH_MAC_PORT2 base pointer */
60080   #define SW0_ETH_MAC_PORT2                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT2_BASE)
60081   /** Peripheral SW0_ETH_MAC_PORT3 base address */
60082   #define SW0_ETH_MAC_PORT3_BASE                   (0x60A11000u)
60083   /** Peripheral SW0_ETH_MAC_PORT3 base pointer */
60084   #define SW0_ETH_MAC_PORT3                        ((NETC_ETH_LINK_Type *)SW0_ETH_MAC_PORT3_BASE)
60085   /** Array initializer of NETC_ETH_LINK peripheral base addresses */
60086   #define NETC_ETH_LINK_BASE_ADDRS                 { ENETC0_ETH_MAC_PORT_BASE, SW0_ETH_MAC_PORT0_BASE, SW0_ETH_MAC_PORT1_BASE, SW0_ETH_MAC_PORT2_BASE, SW0_ETH_MAC_PORT3_BASE }
60087   /** Array initializer of NETC_ETH_LINK peripheral base pointers */
60088   #define NETC_ETH_LINK_BASE_PTRS                  { ENETC0_ETH_MAC_PORT, SW0_ETH_MAC_PORT0, SW0_ETH_MAC_PORT1, SW0_ETH_MAC_PORT2, SW0_ETH_MAC_PORT3 }
60089 #endif
60090 
60091 /*!
60092  * @}
60093  */ /* end of group NETC_ETH_LINK_Peripheral_Access_Layer */
60094 
60095 
60096 /* ----------------------------------------------------------------------------
60097    -- NETC_IERB Peripheral Access Layer
60098    ---------------------------------------------------------------------------- */
60099 
60100 /*!
60101  * @addtogroup NETC_IERB_Peripheral_Access_Layer NETC_IERB Peripheral Access Layer
60102  * @{
60103  */
60104 
60105 /** NETC_IERB - Register Layout Typedef */
60106 typedef struct {
60107   __I  uint32_t CAPR0;                             /**< Capability register 0, offset: 0x0 */
60108   __I  uint32_t CAPR1;                             /**< Capability register 1, offset: 0x4 */
60109   __I  uint32_t CAPR2;                             /**< Capability register 2, offset: 0x8 */
60110   __I  uint32_t CAPR3;                             /**< Capability register 3, offset: 0xC */
60111        uint8_t RESERVED_0[16];
60112   __I  uint32_t CMCAPR;                            /**< Common memory capability register, offset: 0x20 */
60113        uint8_t RESERVED_1[12];
60114   __I  uint32_t IPFTMCAPR;                         /**< Ingress port filter ternary memory capability register, offset: 0x30 */
60115        uint8_t RESERVED_2[16];
60116   __I  uint32_t TGSMCAPR;                          /**< Time gate scheduling memory capability register, offset: 0x44 */
60117        uint8_t RESERVED_3[56];
60118   __IO uint32_t SMDTR;                             /**< Shared memory depletion threshold register, offset: 0x80 */
60119   __IO uint32_t ERSMBAR;                           /**< ENETC receive shared memory buffer allotment register, offset: 0x84 */
60120        uint8_t RESERVED_4[56];
60121   struct {                                         /* offset: 0xC0, array step: 0x8 */
60122     __IO uint32_t HTAHPCR;                           /**< HTA 0 HP configuration register, array offset: 0xC0, array step: 0x8 */
60123     __IO uint32_t HTALPCR;                           /**< HTA 0 LP configuration register, array offset: 0xC4, array step: 0x8 */
60124   } HTA_NUM[1];
60125        uint8_t RESERVED_5[56];
60126   __IO uint32_t HBTMAR;                            /**< Hash bucket table memory allocation register, offset: 0x100 */
60127   __IO uint32_t HBTCR;                             /**< Hash bucket table configuration register, offset: 0x104 */
60128   __I  uint32_t GHTEMCAPR;                         /**< Guaranteed hash table entry memory capability register, offset: 0x108 */
60129        uint8_t RESERVED_6[100];
60130   __IO uint32_t NETCFLRCR;                         /**< NETC FLR configuration register, offset: 0x170 */
60131        uint8_t RESERVED_7[4];
60132   __IO uint32_t NETCCLKFR;                         /**< NETC clock period fractional register, offset: 0x178 */
60133   __IO uint32_t NETCCLKCR;                         /**< NETC clock configuration register, offset: 0x17C */
60134   __IO uint32_t SBCR;                              /**< System bus configuration register, offset: 0x180 */
60135   __IO uint32_t SBOTCR;                            /**< System bus outstanding transaction control register, offset: 0x184 */
60136        uint8_t RESERVED_8[8];
60137   __IO uint32_t SGLTTR;                            /**< Stream gating lag time for refresh register, offset: 0x190 */
60138        uint8_t RESERVED_9[108];
60139   struct {                                         /* offset: 0x200, array step: 0x10 */
60140     __I  uint32_t RBCR;                              /**< Root complex 0 binding configuration register, array offset: 0x200, array step: 0x10 */
60141          uint8_t RESERVED_0[4];
60142     __IO uint32_t RCMSICAR;                          /**< Root complex 0 MSI-X cache attribute register, array offset: 0x208, array step: 0x10 */
60143     __IO uint32_t RCMSIAMQR;                         /**< Root complex 0 MSI access management qualifier register, array offset: 0x20C, array step: 0x10 */
60144   } ARRAY_NUM_RC[1];
60145        uint8_t RESERVED_10[240];
60146   __I  uint32_t EMDIOBCR;                          /**< EMDIO binding configuration register, offset: 0x300 */
60147        uint8_t RESERVED_11[16];
60148   __I  uint32_t EMDIOMCR;                          /**< EMDIO MSI-X configuration register, offset: 0x314 */
60149        uint8_t RESERVED_12[8];
60150   __IO uint32_t EMDIO_CFH_DIDVID;                  /**< EMDIO config header device ID and vendor ID register, offset: 0x320 */
60151   __IO uint32_t EMDIO_CFH_SIDSVID;                 /**< EMDIO config header subsystem ID and subsystem vendor ID register, offset: 0x324 */
60152        uint8_t RESERVED_13[32];
60153   __IO uint32_t EMDIOBLPR[2];                      /**< EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1, array offset: 0x348, array step: 0x4 */
60154   __IO uint32_t EMDIO_CFG;                         /**< EMDIO configuration register, offset: 0x350 */
60155        uint8_t RESERVED_14[172];
60156   struct {                                         /* offset: 0x400, array step: 0x50 */
60157     __I  uint32_t TBCR;                              /**< Timer 0 binding configuration register, array offset: 0x400, array step: 0x50 */
60158          uint8_t RESERVED_0[16];
60159     __IO uint32_t TMCR;                              /**< Timer 0 MSI-X configuration register, array offset: 0x414, array step: 0x50 */
60160          uint8_t RESERVED_1[8];
60161     __IO uint32_t T_CFH_DIDVID;                      /**< Timer 0 config header device ID and vendor ID register, array offset: 0x420, array step: 0x50 */
60162     __IO uint32_t T_CFH_SIDSVID;                     /**< Timer 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x424, array step: 0x50 */
60163          uint8_t RESERVED_2[32];
60164     __IO uint32_t TBLPR[2];                          /**< Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1, array offset: 0x448, array step: index*0x50, index2*0x4 */
60165   } NUM_TMR_ARRAY[1];
60166        uint8_t RESERVED_15[2992];
60167   __I  uint32_t L0CAPR;                            /**< Link 0 capability register, offset: 0x1000 */
60168   __I  uint32_t L0MCAPR;                           /**< Link 0 MAC capability register, offset: 0x1004 */
60169   __I  uint32_t L0IOCAPR;                          /**< Link 0 I/O capability register, offset: 0x1008 */
60170        uint8_t RESERVED_16[4];
60171   __IO uint32_t L0BCR;                             /**< Link 0 binding configuration register, offset: 0x1010 */
60172   __IO uint32_t L0TXBCCTR;                         /**< Link 0 transmit byte credit comfort threshold register, offset: 0x1014 */
60173        uint8_t RESERVED_17[8];
60174   __IO uint32_t L0E0MAR0;                          /**< Link 0 end 0 MAC address register 0, offset: 0x1020 */
60175   __IO uint32_t L0E0MAR1;                          /**< Link 0 end 0 MAC address register 1, offset: 0x1024 */
60176        uint8_t RESERVED_18[24];
60177   __I  uint32_t L1CAPR;                            /**< Link 1 capability register, offset: 0x1040 */
60178   __I  uint32_t L1MCAPR;                           /**< Link 1 MAC capability register, offset: 0x1044 */
60179   __I  uint32_t L1IOCAPR;                          /**< Link 1 I/O capability register, offset: 0x1048 */
60180        uint8_t RESERVED_19[4];
60181   __IO uint32_t L1BCR;                             /**< Link 1 binding configuration register, offset: 0x1050 */
60182   __IO uint32_t L1TXBCCTR;                         /**< Link 1 transmit byte credit comfort threshold register, offset: 0x1054 */
60183        uint8_t RESERVED_20[8];
60184   __IO uint32_t L1E0MAR0;                          /**< Link 1 end 0 MAC address register 0, offset: 0x1060 */
60185   __IO uint32_t L1E0MAR1;                          /**< Link 1 end 0 MAC address register 1, offset: 0x1064 */
60186        uint8_t RESERVED_21[24];
60187   __I  uint32_t L2CAPR;                            /**< Link 2 capability register, offset: 0x1080 */
60188   __I  uint32_t L2MCAPR;                           /**< Link 2 MAC capability register, offset: 0x1084 */
60189   __I  uint32_t L2IOCAPR;                          /**< Link 2 I/O capability register, offset: 0x1088 */
60190        uint8_t RESERVED_22[4];
60191   __IO uint32_t L2BCR;                             /**< Link 2 binding configuration register, offset: 0x1090 */
60192   __IO uint32_t L2TXBCCTR;                         /**< Link 2 transmit byte credit comfort threshold register, offset: 0x1094 */
60193        uint8_t RESERVED_23[8];
60194   __IO uint32_t L2E0MAR0;                          /**< Link 2 end 0 MAC address register 0, offset: 0x10A0 */
60195   __IO uint32_t L2E0MAR1;                          /**< Link 2 end 0 MAC address register 1, offset: 0x10A4 */
60196        uint8_t RESERVED_24[24];
60197   __I  uint32_t L3CAPR;                            /**< Link 3 capability register, offset: 0x10C0 */
60198   __I  uint32_t L3MCAPR;                           /**< Link 3 MAC capability register, offset: 0x10C4 */
60199   __I  uint32_t L3IOCAPR;                          /**< Link 3 I/O capability register, offset: 0x10C8 */
60200        uint8_t RESERVED_25[4];
60201   __IO uint32_t L3BCR;                             /**< Link 3 binding configuration register, offset: 0x10D0 */
60202   __IO uint32_t L3TXBCCTR;                         /**< Link 3 transmit byte credit comfort threshold register, offset: 0x10D4 */
60203        uint8_t RESERVED_26[8];
60204   __IO uint32_t L3E0MAR0;                          /**< Link 3 end 0 MAC address register 0, offset: 0x10E0 */
60205   __IO uint32_t L3E0MAR1;                          /**< Link 3 end 0 MAC address register 1, offset: 0x10E4 */
60206        uint8_t RESERVED_27[24];
60207   __I  uint32_t L4CAPR;                            /**< Link 4 capability register, offset: 0x1100 */
60208   __I  uint32_t L4MCAPR;                           /**< Link 4 MAC capability register, offset: 0x1104 */
60209   __I  uint32_t L4IOCAPR;                          /**< Link 4 I/O capability register, offset: 0x1108 */
60210        uint8_t RESERVED_28[4];
60211   __IO uint32_t L4BCR;                             /**< Link 4 binding configuration register, offset: 0x1110 */
60212   __IO uint32_t L4TXBCCTR;                         /**< Link 4 transmit byte credit comfort threshold register, offset: 0x1114 */
60213        uint8_t RESERVED_29[8];
60214   __IO uint32_t L4E0MAR0;                          /**< Link 4 end 0 MAC address register 0, offset: 0x1120 */
60215   __IO uint32_t L4E0MAR1;                          /**< Link 4 end 0 MAC address register 1, offset: 0x1124 */
60216        uint8_t RESERVED_30[24];
60217   __I  uint32_t L5CAPR;                            /**< Link 5 capability register, offset: 0x1140 */
60218   __I  uint32_t L5MCAPR;                           /**< Link 5 MAC capability register, offset: 0x1144 */
60219        uint8_t RESERVED_31[8];
60220   __I  uint32_t L5BCR;                             /**< Link 5 binding configuration register, offset: 0x1150 */
60221   __IO uint32_t L5TXBCCTR;                         /**< Link 5 transmit byte credit comfort threshold register, offset: 0x1154 */
60222        uint8_t RESERVED_32[8];
60223   __IO uint32_t L5E0MAR0;                          /**< Link 5 end 0 MAC address register 0, offset: 0x1160 */
60224   __IO uint32_t L5E0MAR1;                          /**< Link 5 end 0 MAC address register 1, offset: 0x1164 */
60225   __IO uint32_t L5E1MAR0;                          /**< Link 5 end 1 MAC address register 0, offset: 0x1168 */
60226   __IO uint32_t L5E1MAR1;                          /**< Link 5 end 1 MAC address register 1, offset: 0x116C */
60227        uint8_t RESERVED_33[3728];
60228   struct {                                         /* offset: 0x2000, array step: 0x21C */
60229     __I  uint32_t SBCR;                              /**< Switch 0 binding configuration register, array offset: 0x2000, array step: 0x21C */
60230          uint8_t RESERVED_0[16];
60231     __IO uint32_t SMCR;                              /**< Switch 0 MSI-X configuration register, array offset: 0x2014, array step: 0x21C */
60232          uint8_t RESERVED_1[8];
60233     __IO uint32_t S_CFH_DIDVID;                      /**< Switch 0 config header device ID and vendor ID register, array offset: 0x2020, array step: 0x21C */
60234     __IO uint32_t S_CFH_SIDSVID;                     /**< Switch 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x2024, array step: 0x21C */
60235          uint8_t RESERVED_2[16];
60236     __IO uint32_t SCCAR;                             /**< Switch 0 command cache attribute register, array offset: 0x2038, array step: 0x21C */
60237          uint8_t RESERVED_3[4];
60238     __IO uint32_t SAMQR;                             /**< Switch 0 access management qualifier register, array offset: 0x2040, array step: 0x21C */
60239          uint8_t RESERVED_4[4];
60240     __IO uint32_t SBLPR[2];                          /**< Switch 0 boot loader parameter register 0..Switch 0 boot loader parameter register 1, array offset: 0x2048, array step: index*0x21C, index2*0x4 */
60241          uint8_t RESERVED_5[16];
60242     __IO uint32_t SSMBAR;                            /**< Switch 0 shared memory buffer allotment register, array offset: 0x2060, array step: 0x21C */
60243          uint8_t RESERVED_6[28];
60244     __IO uint32_t SHTMAR;                            /**< Switch 0 hash table memory allotment register, array offset: 0x2080, array step: 0x21C */
60245     __IO uint32_t SITMAR;                            /**< Switch 0 index table memory allocation register, array offset: 0x2084, array step: 0x21C */
60246     __IO uint32_t SIPFTMAR;                          /**< Switch 0 ingress port filter table memory allocation register, array offset: 0x2088, array step: 0x21C */
60247          uint8_t RESERVED_7[20];
60248     __IO uint32_t SRPITMAR;                          /**< Switch 0 rate policer index table memory allocation register, array offset: 0x20A0, array step: 0x21C */
60249     __IO uint32_t SISCITMAR;                         /**< Switch 0 ingress stream counter index table memory allocation register, array offset: 0x20A4, array step: 0x21C */
60250     __IO uint32_t SISITMAR;                          /**< Switch 0 ingress stream index table memory allocation register, array offset: 0x20A8, array step: 0x21C */
60251     __IO uint32_t SISQGITMAR;                        /**< Switch 0 ingress sequence generation index table memory allocation register, array offset: 0x20AC, array step: 0x21C */
60252          uint8_t RESERVED_8[4];
60253     __IO uint32_t SSGIITMAR;                         /**< Switch 0 stream gate instance index table memory allocation register, array offset: 0x20B4, array step: 0x21C */
60254     __IO uint32_t SSGCLITMAR;                        /**< Switch 0 stream gate control list index table memory allocation register, array offset: 0x20B8, array step: 0x21C */
60255     __IO uint32_t SFMITMAR;                          /**< Switch 0 frame modification index table memory allocation register, array offset: 0x20BC, array step: 0x21C */
60256     __IO uint32_t SFMDITMAR;                         /**< Switch 0 frame modification data index table memory allocation register, array offset: 0x20C0, array step: 0x21C */
60257          uint8_t RESERVED_9[44];
60258     __IO uint32_t STGSTAR;                           /**< Switch 0 time gate scheduling table allocation register, array offset: 0x20F0, array step: 0x21C */
60259     __IO uint32_t STGSLR;                            /**< Switch 0 time gate scheduling lookahead register, array offset: 0x20F4, array step: 0x21C */
60260          uint8_t RESERVED_10[268];
60261     __I  uint32_t SMPCR;                             /**< Switch 0 management port configuration register, array offset: 0x2204, array step: 0x21C */
60262          uint8_t RESERVED_11[8];
60263     __IO uint32_t SVFHTDECR0;                        /**< Switch 0 VLAN Filter (hash) table default entry configuration registers 0, array offset: 0x2210, array step: 0x21C */
60264     __IO uint32_t SVFHTDECR1;                        /**< Switch 0 VLAN filter hash table default entry configuration registers 1, array offset: 0x2214, array step: 0x21C */
60265     __IO uint32_t SVFHTDECR2;                        /**< Switch 0 VLAN filter hash table default entry configuration registers 2, array offset: 0x2218, array step: 0x21C */
60266   } CFG_SW_INST[1];
60267        uint8_t RESERVED_34[3556];
60268   struct {                                         /* offset: 0x3000, array step: 0x100 */
60269     __I  uint32_t EBCR0;                             /**< ENETC 0 binding configuration register 0..ENETC 1 binding configuration register 0, array offset: 0x3000, array step: 0x100 */
60270     __I  uint32_t EBCR1;                             /**< ENETC 0 binding configuration register 1..ENETC 1 binding configuration register 1, array offset: 0x3004, array step: 0x100 */
60271     __I  uint32_t EBCR2;                             /**< ENETC 0 binding configuration register 2..ENETC 1 binding configuration register 2, array offset: 0x3008, array step: 0x100 */
60272          uint8_t RESERVED_0[4];
60273     __I  uint32_t EVBCR;                             /**< ENETC 0 VSI binding configuration register..ENETC 1 VSI binding configuration register, array offset: 0x3010, array step: 0x100 */
60274     __IO uint32_t EMCR;                              /**< ENETC 0 MSI-X configuration register..ENETC 1 MSI-X configuration register, array offset: 0x3014, array step: 0x100 */
60275          uint8_t RESERVED_1[8];
60276     __IO uint32_t E_CFH_DIDVID;                      /**< ENETC 0 config header device ID and vendor ID register..ENETC 1 config header device ID and vendor ID register, array offset: 0x3020, array step: 0x100 */
60277     __IO uint32_t E_CFH_SIDSVID;                     /**< ENETC 0 config header subsystem ID and subsystem vendor ID register..ENETC 1 config header subsystem ID and subsystem vendor ID register, array offset: 0x3024, array step: 0x100 */
60278     __IO uint32_t E_CFC_VFDID;                       /**< ENETC 0 config capability VF device ID register..ENETC 1 config capability VF device ID register, array offset: 0x3028, array step: 0x100 */
60279          uint8_t RESERVED_2[4];
60280     __IO uint32_t EBCAR;                             /**< ENETC 0 buffer cache attribute register 0..ENETC 1 buffer cache attribute register 0, array offset: 0x3030, array step: 0x100 */
60281     __IO uint32_t EMCAR;                             /**< ENETC 0 message cache attribute register..ENETC 1 message cache attribute register, array offset: 0x3034, array step: 0x100 */
60282     __IO uint32_t ECAR;                              /**< ENETC 0 command cache attribute register..ENETC 1 command cache attribute register, array offset: 0x3038, array step: 0x100 */
60283          uint8_t RESERVED_3[4];
60284     __IO uint32_t EAMQR;                             /**< ENETC 0 access management qualifier register..ENETC 1 access management qualifier register, array offset: 0x3040, array step: 0x100 */
60285          uint8_t RESERVED_4[4];
60286     __IO uint32_t EBLPR[2];                          /**< ENETC 0 boot loader parameter register 0..ENETC 1 boot loader parameter register 1, array offset: 0x3048, array step: index*0x100, index2*0x4 */
60287     __IO uint32_t ERXMBER;                           /**< ENETC 0 receive memory buffer entitlement register..ENETC 1 receive memory buffer entitlement register, array offset: 0x3050, array step: 0x100 */
60288     __IO uint32_t ERXMBLR;                           /**< ENETC 0 receive memory buffer limit register..ENETC 1 receive memory buffer limit register, array offset: 0x3054, array step: 0x100 */
60289          uint8_t RESERVED_5[24];
60290     __IO uint32_t ETXHPTBCR;                         /**< ENETC 0 transmit high priority tier byte credit register..ENETC 1 transmit high priority tier byte credit register, array offset: 0x3070, array step: 0x100 */
60291     __IO uint32_t ETXLPTBCR;                         /**< ENETC 0 transmit low priority tier byte credit register..ENETC 1 transmit low priority tier byte credit register, array offset: 0x3074, array step: 0x100 */
60292          uint8_t RESERVED_6[8];
60293     __IO uint32_t EHTMAR;                            /**< ENETC 0 hash table memory allotment register..ENETC 1 hash table memory allotment register, array offset: 0x3080, array step: 0x100 */
60294     __IO uint32_t EITMAR;                            /**< ENETC 0 index table memory allocation register..ENETC 1 index table memory allocation register, array offset: 0x3084, array step: 0x100 */
60295     __IO uint32_t EIPFTMAR;                          /**< ENETC 0 ingress port filter table memory allocation register..ENETC 1 ingress port filter table memory allocation register, array offset: 0x3088, array step: 0x100 */
60296          uint8_t RESERVED_7[20];
60297     __IO uint32_t ERPITMAR;                          /**< ENETC 0 rate policer index table memory allocation register..ENETC 1 rate policer index table memory allocation register, array offset: 0x30A0, array step: 0x100 */
60298     __IO uint32_t EISCITMAR;                         /**< ENETC 0 ingress stream counter index table memory allocation register..ENETC 1 ingress stream counter index table memory allocation register, array offset: 0x30A4, array step: 0x100 */
60299     __IO uint32_t EISITMAR;                          /**< ENETC 0 ingress stream index table memory allocation register..ENETC 1 ingress stream index table memory allocation register, array offset: 0x30A8, array step: 0x100 */
60300          uint8_t RESERVED_8[8];
60301     __IO uint32_t ESGIITMAR;                         /**< ENETC 0 stream gate instance index table memory allocation register..ENETC 1 stream gate instance index table memory allocation register, array offset: 0x30B4, array step: 0x100 */
60302     __IO uint32_t ESGCLITMAR;                        /**< ENETC 0 stream gate control list index table memory allocation register..ENETC 1 stream gate control list index table memory allocation register, array offset: 0x30B8, array step: 0x100 */
60303          uint8_t RESERVED_9[52];
60304     __IO uint32_t ETGSTAR;                           /**< ENETC 0 time gate scheduling table allocation register..ENETC 1 time gate scheduling table allocation register, array offset: 0x30F0, array step: 0x100 */
60305     __IO uint32_t ETGSLR;                            /**< ENETC 0 time gate scheduling lookahead register..ENETC 1 time gate scheduling lookahead register, array offset: 0x30F4, array step: 0x100 */
60306          uint8_t RESERVED_10[8];
60307   } CFG_ENETC_INST[2];
60308        uint8_t RESERVED_35[3584];
60309   struct {                                         /* offset: 0x4000, array step: 0x18 */
60310     __IO uint32_t VAMQR;                             /**< VSI 0 access management qualifier register, array offset: 0x4000, array step: 0x18 */
60311          uint8_t RESERVED_0[4];
60312     __IO uint32_t VBLPR[2];                          /**< VSI 0 boot loader parameter register 0..VSI 0 boot loader parameter register 1, array offset: 0x4008, array step: index*0x18, index2*0x4 */
60313     __IO uint32_t VPMAR0;                            /**< VSI 0 primary MAC address register 0, array offset: 0x4010, array step: 0x18 */
60314     __IO uint32_t VPMAR1;                            /**< VSI 0 primary MAC address register 1, array offset: 0x4014, array step: 0x18 */
60315   } CFG_VSI_INST[1];
60316 } NETC_IERB_Type;
60317 
60318 /* ----------------------------------------------------------------------------
60319    -- NETC_IERB Register Masks
60320    ---------------------------------------------------------------------------- */
60321 
60322 /*!
60323  * @addtogroup NETC_IERB_Register_Masks NETC_IERB Register Masks
60324  * @{
60325  */
60326 
60327 /*! @name CAPR0 - Capability register 0 */
60328 /*! @{ */
60329 
60330 #define NETC_IERB_CAPR0_NUM_RC_MASK              (0xFU)
60331 #define NETC_IERB_CAPR0_NUM_RC_SHIFT             (0U)
60332 #define NETC_IERB_CAPR0_NUM_RC(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_RC_SHIFT)) & NETC_IERB_CAPR0_NUM_RC_MASK)
60333 
60334 #define NETC_IERB_CAPR0_NUM_EMDIO_MASK           (0x10U)
60335 #define NETC_IERB_CAPR0_NUM_EMDIO_SHIFT          (4U)
60336 #define NETC_IERB_CAPR0_NUM_EMDIO(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_EMDIO_SHIFT)) & NETC_IERB_CAPR0_NUM_EMDIO_MASK)
60337 
60338 #define NETC_IERB_CAPR0_NUM_TMR_MASK             (0xC0U)
60339 #define NETC_IERB_CAPR0_NUM_TMR_SHIFT            (6U)
60340 #define NETC_IERB_CAPR0_NUM_TMR(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_TMR_SHIFT)) & NETC_IERB_CAPR0_NUM_TMR_MASK)
60341 
60342 #define NETC_IERB_CAPR0_NUM_LINKS_MASK           (0x1F00U)
60343 #define NETC_IERB_CAPR0_NUM_LINKS_SHIFT          (8U)
60344 #define NETC_IERB_CAPR0_NUM_LINKS(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_LINKS_SHIFT)) & NETC_IERB_CAPR0_NUM_LINKS_MASK)
60345 
60346 #define NETC_IERB_CAPR0_NUM_SW_MASK              (0x30000U)
60347 #define NETC_IERB_CAPR0_NUM_SW_SHIFT             (16U)
60348 #define NETC_IERB_CAPR0_NUM_SW(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_SW_SHIFT)) & NETC_IERB_CAPR0_NUM_SW_MASK)
60349 
60350 #define NETC_IERB_CAPR0_NUM_ENETC_MASK           (0xF80000U)
60351 #define NETC_IERB_CAPR0_NUM_ENETC_SHIFT          (19U)
60352 #define NETC_IERB_CAPR0_NUM_ENETC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_ENETC_SHIFT)) & NETC_IERB_CAPR0_NUM_ENETC_MASK)
60353 
60354 #define NETC_IERB_CAPR0_NUM_VSI_MASK             (0x7F000000U)
60355 #define NETC_IERB_CAPR0_NUM_VSI_SHIFT            (24U)
60356 #define NETC_IERB_CAPR0_NUM_VSI(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_VSI_SHIFT)) & NETC_IERB_CAPR0_NUM_VSI_MASK)
60357 /*! @} */
60358 
60359 /*! @name CAPR1 - Capability register 1 */
60360 /*! @{ */
60361 
60362 #define NETC_IERB_CAPR1_NUM_RX_BDR_MASK          (0x3FFU)
60363 #define NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT         (0U)
60364 #define NETC_IERB_CAPR1_NUM_RX_BDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_RX_BDR_MASK)
60365 
60366 #define NETC_IERB_CAPR1_NUM_TX_BDR_MASK          (0x3FF0000U)
60367 #define NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT         (16U)
60368 #define NETC_IERB_CAPR1_NUM_TX_BDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_TX_BDR_MASK)
60369 /*! @} */
60370 
60371 /*! @name CAPR2 - Capability register 2 */
60372 /*! @{ */
60373 
60374 #define NETC_IERB_CAPR2_NUM_MSIX_MASK            (0x7FFU)
60375 #define NETC_IERB_CAPR2_NUM_MSIX_SHIFT           (0U)
60376 #define NETC_IERB_CAPR2_NUM_MSIX(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR2_NUM_MSIX_SHIFT)) & NETC_IERB_CAPR2_NUM_MSIX_MASK)
60377 /*! @} */
60378 
60379 /*! @name CAPR3 - Capability register 3 */
60380 /*! @{ */
60381 
60382 #define NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK        (0xFFFU)
60383 #define NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT       (0U)
60384 #define NETC_IERB_CAPR3_NUM_MAC_AFTE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK)
60385 
60386 #define NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK        (0xFFF0000U)
60387 #define NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT       (16U)
60388 #define NETC_IERB_CAPR3_NUM_VLAN_FTE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK)
60389 /*! @} */
60390 
60391 /*! @name CMCAPR - Common memory capability register */
60392 /*! @{ */
60393 
60394 #define NETC_IERB_CMCAPR_NUM_WORDS_MASK          (0xFFFFFFU)
60395 #define NETC_IERB_CMCAPR_NUM_WORDS_SHIFT         (0U)
60396 #define NETC_IERB_CMCAPR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_CMCAPR_NUM_WORDS_MASK)
60397 
60398 #define NETC_IERB_CMCAPR_WORD_SIZE_MASK          (0x30000000U)
60399 #define NETC_IERB_CMCAPR_WORD_SIZE_SHIFT         (28U)
60400 #define NETC_IERB_CMCAPR_WORD_SIZE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_CMCAPR_WORD_SIZE_MASK)
60401 /*! @} */
60402 
60403 /*! @name IPFTMCAPR - Ingress port filter ternary memory capability register */
60404 /*! @{ */
60405 
60406 #define NETC_IERB_IPFTMCAPR_NUM_WORDS_MASK       (0xFFFFU)
60407 #define NETC_IERB_IPFTMCAPR_NUM_WORDS_SHIFT      (0U)
60408 #define NETC_IERB_IPFTMCAPR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_IPFTMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_IPFTMCAPR_NUM_WORDS_MASK)
60409 
60410 #define NETC_IERB_IPFTMCAPR_WORD_SIZE_MASK       (0x30000000U)
60411 #define NETC_IERB_IPFTMCAPR_WORD_SIZE_SHIFT      (28U)
60412 #define NETC_IERB_IPFTMCAPR_WORD_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_IPFTMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_IPFTMCAPR_WORD_SIZE_MASK)
60413 /*! @} */
60414 
60415 /*! @name TGSMCAPR - Time gate scheduling memory capability register */
60416 /*! @{ */
60417 
60418 #define NETC_IERB_TGSMCAPR_NUM_WORDS_MASK        (0xFFFFU)
60419 #define NETC_IERB_TGSMCAPR_NUM_WORDS_SHIFT       (0U)
60420 #define NETC_IERB_TGSMCAPR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TGSMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_TGSMCAPR_NUM_WORDS_MASK)
60421 /*! @} */
60422 
60423 /*! @name SMDTR - Shared memory depletion threshold register */
60424 /*! @{ */
60425 
60426 #define NETC_IERB_SMDTR_THRESH_MASK              (0xFFFFFFU)
60427 #define NETC_IERB_SMDTR_THRESH_SHIFT             (0U)
60428 #define NETC_IERB_SMDTR_THRESH(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMDTR_THRESH_SHIFT)) & NETC_IERB_SMDTR_THRESH_MASK)
60429 /*! @} */
60430 
60431 /*! @name ERSMBAR - ENETC receive shared memory buffer allotment register */
60432 /*! @{ */
60433 
60434 #define NETC_IERB_ERSMBAR_THRESH_MASK            (0xFFFFFFU)
60435 #define NETC_IERB_ERSMBAR_THRESH_SHIFT           (0U)
60436 #define NETC_IERB_ERSMBAR_THRESH(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERSMBAR_THRESH_SHIFT)) & NETC_IERB_ERSMBAR_THRESH_MASK)
60437 /*! @} */
60438 
60439 /*! @name HTAHPCR - HTA 0 HP configuration register */
60440 /*! @{ */
60441 
60442 #define NETC_IERB_HTAHPCR_BLIMIT_MASK            (0xFFFFU)
60443 #define NETC_IERB_HTAHPCR_BLIMIT_SHIFT           (0U)
60444 #define NETC_IERB_HTAHPCR_BLIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_BLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_BLIMIT_MASK)
60445 
60446 #define NETC_IERB_HTAHPCR_FLIMIT_MASK            (0xFF000000U)
60447 #define NETC_IERB_HTAHPCR_FLIMIT_SHIFT           (24U)
60448 #define NETC_IERB_HTAHPCR_FLIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_FLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_FLIMIT_MASK)
60449 /*! @} */
60450 
60451 /* The count of NETC_IERB_HTAHPCR */
60452 #define NETC_IERB_HTAHPCR_COUNT                  (1U)
60453 
60454 /*! @name HTALPCR - HTA 0 LP configuration register */
60455 /*! @{ */
60456 
60457 #define NETC_IERB_HTALPCR_BLIMIT_MASK            (0xFFFFU)
60458 #define NETC_IERB_HTALPCR_BLIMIT_SHIFT           (0U)
60459 #define NETC_IERB_HTALPCR_BLIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_BLIMIT_SHIFT)) & NETC_IERB_HTALPCR_BLIMIT_MASK)
60460 
60461 #define NETC_IERB_HTALPCR_FLIMIT_MASK            (0xFF000000U)
60462 #define NETC_IERB_HTALPCR_FLIMIT_SHIFT           (24U)
60463 #define NETC_IERB_HTALPCR_FLIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_FLIMIT_SHIFT)) & NETC_IERB_HTALPCR_FLIMIT_MASK)
60464 /*! @} */
60465 
60466 /* The count of NETC_IERB_HTALPCR */
60467 #define NETC_IERB_HTALPCR_COUNT                  (1U)
60468 
60469 /*! @name HBTMAR - Hash bucket table memory allocation register */
60470 /*! @{ */
60471 
60472 #define NETC_IERB_HBTMAR_NUM_WORDS_MASK          (0x3FFFU)
60473 #define NETC_IERB_HBTMAR_NUM_WORDS_SHIFT         (0U)
60474 #define NETC_IERB_HBTMAR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_HBTMAR_NUM_WORDS_MASK)
60475 
60476 #define NETC_IERB_HBTMAR_MIN_WORDS_MASK          (0xFF0000U)
60477 #define NETC_IERB_HBTMAR_MIN_WORDS_SHIFT         (16U)
60478 #define NETC_IERB_HBTMAR_MIN_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MIN_WORDS_SHIFT)) & NETC_IERB_HBTMAR_MIN_WORDS_MASK)
60479 
60480 #define NETC_IERB_HBTMAR_NEPW_MASK               (0x7000000U)
60481 #define NETC_IERB_HBTMAR_NEPW_SHIFT              (24U)
60482 #define NETC_IERB_HBTMAR_NEPW(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NEPW_SHIFT)) & NETC_IERB_HBTMAR_NEPW_MASK)
60483 
60484 #define NETC_IERB_HBTMAR_MLOC_MASK               (0xC0000000U)
60485 #define NETC_IERB_HBTMAR_MLOC_SHIFT              (30U)
60486 #define NETC_IERB_HBTMAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MLOC_SHIFT)) & NETC_IERB_HBTMAR_MLOC_MASK)
60487 /*! @} */
60488 
60489 /*! @name HBTCR - Hash bucket table configuration register */
60490 /*! @{ */
60491 
60492 #define NETC_IERB_HBTCR_MAX_COL_MASK             (0x7U)
60493 #define NETC_IERB_HBTCR_MAX_COL_SHIFT            (0U)
60494 #define NETC_IERB_HBTCR_MAX_COL(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_COL_SHIFT)) & NETC_IERB_HBTCR_MAX_COL_MASK)
60495 
60496 #define NETC_IERB_HBTCR_MAX_VISITS_MASK          (0xF0U)
60497 #define NETC_IERB_HBTCR_MAX_VISITS_SHIFT         (4U)
60498 #define NETC_IERB_HBTCR_MAX_VISITS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_VISITS_SHIFT)) & NETC_IERB_HBTCR_MAX_VISITS_MASK)
60499 /*! @} */
60500 
60501 /*! @name GHTEMCAPR - Guaranteed hash table entry memory capability register */
60502 /*! @{ */
60503 
60504 #define NETC_IERB_GHTEMCAPR_NUM_WORDS_MASK       (0x1FFU)
60505 #define NETC_IERB_GHTEMCAPR_NUM_WORDS_SHIFT      (0U)
60506 #define NETC_IERB_GHTEMCAPR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_GHTEMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_GHTEMCAPR_NUM_WORDS_MASK)
60507 
60508 #define NETC_IERB_GHTEMCAPR_MLOC_MASK            (0xC0000000U)
60509 #define NETC_IERB_GHTEMCAPR_MLOC_SHIFT           (30U)
60510 #define NETC_IERB_GHTEMCAPR_MLOC(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_GHTEMCAPR_MLOC_SHIFT)) & NETC_IERB_GHTEMCAPR_MLOC_MASK)
60511 /*! @} */
60512 
60513 /*! @name NETCFLRCR - NETC FLR configuration register */
60514 /*! @{ */
60515 
60516 #define NETC_IERB_NETCFLRCR_VALUE_MASK           (0x1FFU)
60517 #define NETC_IERB_NETCFLRCR_VALUE_SHIFT          (0U)
60518 #define NETC_IERB_NETCFLRCR_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_VALUE_SHIFT)) & NETC_IERB_NETCFLRCR_VALUE_MASK)
60519 
60520 #define NETC_IERB_NETCFLRCR_SCALE_MASK           (0xE00U)
60521 #define NETC_IERB_NETCFLRCR_SCALE_SHIFT          (9U)
60522 /*! SCALE - Scale */
60523 #define NETC_IERB_NETCFLRCR_SCALE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_SCALE_SHIFT)) & NETC_IERB_NETCFLRCR_SCALE_MASK)
60524 /*! @} */
60525 
60526 /*! @name NETCCLKFR - NETC clock period fractional register */
60527 /*! @{ */
60528 
60529 #define NETC_IERB_NETCCLKFR_FRAC_MASK            (0xFFFFFFFFU)
60530 #define NETC_IERB_NETCCLKFR_FRAC_SHIFT           (0U)
60531 #define NETC_IERB_NETCCLKFR_FRAC(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKFR_FRAC_SHIFT)) & NETC_IERB_NETCCLKFR_FRAC_MASK)
60532 /*! @} */
60533 
60534 /*! @name NETCCLKCR - NETC clock configuration register */
60535 /*! @{ */
60536 
60537 #define NETC_IERB_NETCCLKCR_FREQ_MASK            (0x7FFU)
60538 #define NETC_IERB_NETCCLKCR_FREQ_SHIFT           (0U)
60539 /*! FREQ - Frequency */
60540 #define NETC_IERB_NETCCLKCR_FREQ(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_FREQ_SHIFT)) & NETC_IERB_NETCCLKCR_FREQ_MASK)
60541 
60542 #define NETC_IERB_NETCCLKCR_PERIOD_MASK          (0x3FF0000U)
60543 #define NETC_IERB_NETCCLKCR_PERIOD_SHIFT         (16U)
60544 /*! PERIOD - Period */
60545 #define NETC_IERB_NETCCLKCR_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_PERIOD_SHIFT)) & NETC_IERB_NETCCLKCR_PERIOD_MASK)
60546 /*! @} */
60547 
60548 /*! @name SBCR - System bus configuration register */
60549 /*! @{ */
60550 
60551 #define NETC_IERB_SBCR_WBS_MASK                  (0x3U)
60552 #define NETC_IERB_SBCR_WBS_SHIFT                 (0U)
60553 #define NETC_IERB_SBCR_WBS(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_WBS_SHIFT)) & NETC_IERB_SBCR_WBS_MASK)
60554 
60555 #define NETC_IERB_SBCR_RBS_MASK                  (0xCU)
60556 #define NETC_IERB_SBCR_RBS_SHIFT                 (2U)
60557 #define NETC_IERB_SBCR_RBS(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_RBS_SHIFT)) & NETC_IERB_SBCR_RBS_MASK)
60558 /*! @} */
60559 
60560 /*! @name SBOTCR - System bus outstanding transaction control register */
60561 /*! @{ */
60562 
60563 #define NETC_IERB_SBOTCR_OT_LIMIT_MASK           (0xFFFFFFFFU)
60564 #define NETC_IERB_SBOTCR_OT_LIMIT_SHIFT          (0U)
60565 #define NETC_IERB_SBOTCR_OT_LIMIT(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBOTCR_OT_LIMIT_SHIFT)) & NETC_IERB_SBOTCR_OT_LIMIT_MASK)
60566 /*! @} */
60567 
60568 /*! @name SGLTTR - Stream gating lag time for refresh register */
60569 /*! @{ */
60570 
60571 #define NETC_IERB_SGLTTR_LAG_TIME_MASK           (0x1FU)
60572 #define NETC_IERB_SGLTTR_LAG_TIME_SHIFT          (0U)
60573 #define NETC_IERB_SGLTTR_LAG_TIME(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SGLTTR_LAG_TIME_SHIFT)) & NETC_IERB_SGLTTR_LAG_TIME_MASK)
60574 /*! @} */
60575 
60576 /*! @name RBCR - Root complex 0 binding configuration register */
60577 /*! @{ */
60578 
60579 #define NETC_IERB_RBCR_TYPE_MASK                 (0x1U)
60580 #define NETC_IERB_RBCR_TYPE_SHIFT                (0U)
60581 #define NETC_IERB_RBCR_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RBCR_TYPE_SHIFT)) & NETC_IERB_RBCR_TYPE_MASK)
60582 
60583 #define NETC_IERB_RBCR_PORT_MASK                 (0xF0U)
60584 #define NETC_IERB_RBCR_PORT_SHIFT                (4U)
60585 #define NETC_IERB_RBCR_PORT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RBCR_PORT_SHIFT)) & NETC_IERB_RBCR_PORT_MASK)
60586 /*! @} */
60587 
60588 /* The count of NETC_IERB_RBCR */
60589 #define NETC_IERB_RBCR_COUNT                     (1U)
60590 
60591 /*! @name RCMSICAR - Root complex 0 MSI-X cache attribute register */
60592 /*! @{ */
60593 
60594 #define NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK      (0xFU)
60595 #define NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT     (0U)
60596 #define NETC_IERB_RCMSICAR_MSI_WRCACHE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK)
60597 
60598 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK     (0x30U)
60599 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT    (4U)
60600 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN(x)       (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK)
60601 
60602 #define NETC_IERB_RCMSICAR_MSI_WRSNP_MASK        (0x40U)
60603 #define NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT       (6U)
60604 #define NETC_IERB_RCMSICAR_MSI_WRSNP(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRSNP_MASK)
60605 /*! @} */
60606 
60607 /* The count of NETC_IERB_RCMSICAR */
60608 #define NETC_IERB_RCMSICAR_COUNT                 (1U)
60609 
60610 /*! @name RCMSIAMQR - Root complex 0 MSI access management qualifier register */
60611 /*! @{ */
60612 
60613 #define NETC_IERB_RCMSIAMQR_AWQOS_MASK           (0xF00000U)
60614 #define NETC_IERB_RCMSIAMQR_AWQOS_SHIFT          (20U)
60615 #define NETC_IERB_RCMSIAMQR_AWQOS(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSIAMQR_AWQOS_SHIFT)) & NETC_IERB_RCMSIAMQR_AWQOS_MASK)
60616 
60617 #define NETC_IERB_RCMSIAMQR_BMT_MASK             (0x80000000U)
60618 #define NETC_IERB_RCMSIAMQR_BMT_SHIFT            (31U)
60619 #define NETC_IERB_RCMSIAMQR_BMT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSIAMQR_BMT_SHIFT)) & NETC_IERB_RCMSIAMQR_BMT_MASK)
60620 /*! @} */
60621 
60622 /* The count of NETC_IERB_RCMSIAMQR */
60623 #define NETC_IERB_RCMSIAMQR_COUNT                (1U)
60624 
60625 /*! @name EMDIOBCR - EMDIO binding configuration register */
60626 /*! @{ */
60627 
60628 #define NETC_IERB_EMDIOBCR_RC_INST_MASK          (0xFU)
60629 #define NETC_IERB_EMDIOBCR_RC_INST_SHIFT         (0U)
60630 #define NETC_IERB_EMDIOBCR_RC_INST(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_RC_INST_SHIFT)) & NETC_IERB_EMDIOBCR_RC_INST_MASK)
60631 
60632 #define NETC_IERB_EMDIOBCR_FN_MASK               (0xF00U)
60633 #define NETC_IERB_EMDIOBCR_FN_SHIFT              (8U)
60634 #define NETC_IERB_EMDIOBCR_FN(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_FN_SHIFT)) & NETC_IERB_EMDIOBCR_FN_MASK)
60635 
60636 #define NETC_IERB_EMDIOBCR_VALID_MASK            (0x80000000U)
60637 #define NETC_IERB_EMDIOBCR_VALID_SHIFT           (31U)
60638 #define NETC_IERB_EMDIOBCR_VALID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_VALID_SHIFT)) & NETC_IERB_EMDIOBCR_VALID_MASK)
60639 /*! @} */
60640 
60641 /*! @name EMDIOMCR - EMDIO MSI-X configuration register */
60642 /*! @{ */
60643 
60644 #define NETC_IERB_EMDIOMCR_NUM_MSIX_MASK         (0x1U)
60645 #define NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT        (0U)
60646 #define NETC_IERB_EMDIOMCR_NUM_MSIX(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMDIOMCR_NUM_MSIX_MASK)
60647 /*! @} */
60648 
60649 /*! @name EMDIO_CFH_DIDVID - EMDIO config header device ID and vendor ID register */
60650 /*! @{ */
60651 
60652 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU)
60653 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT (0U)
60654 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID(x)  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK)
60655 
60656 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U)
60657 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT (16U)
60658 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID(x)  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK)
60659 /*! @} */
60660 
60661 /*! @name EMDIO_CFH_SIDSVID - EMDIO config header subsystem ID and subsystem vendor ID register */
60662 /*! @{ */
60663 
60664 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
60665 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
60666 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK)
60667 
60668 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U)
60669 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U)
60670 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK)
60671 /*! @} */
60672 
60673 /*! @name EMDIOBLPR - EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1 */
60674 /*! @{ */
60675 
60676 #define NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK       (0xFFFFFFFFU)
60677 #define NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT      (0U)
60678 #define NETC_IERB_EMDIOBLPR_PARAM_VAL(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK)
60679 /*! @} */
60680 
60681 /* The count of NETC_IERB_EMDIOBLPR */
60682 #define NETC_IERB_EMDIOBLPR_COUNT                (2U)
60683 
60684 /*! @name EMDIO_CFG - EMDIO configuration register */
60685 /*! @{ */
60686 
60687 #define NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK       (0x10U)
60688 #define NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT      (4U)
60689 #define NETC_IERB_EMDIO_CFG_MDIO_MODE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK)
60690 
60691 #define NETC_IERB_EMDIO_CFG_MDC_MODE_MASK        (0x20U)
60692 #define NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT       (5U)
60693 #define NETC_IERB_EMDIO_CFG_MDC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDC_MODE_MASK)
60694 /*! @} */
60695 
60696 /*! @name TBCR - Timer 0 binding configuration register */
60697 /*! @{ */
60698 
60699 #define NETC_IERB_TBCR_RC_INST_MASK              (0xFU)
60700 #define NETC_IERB_TBCR_RC_INST_SHIFT             (0U)
60701 #define NETC_IERB_TBCR_RC_INST(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_RC_INST_SHIFT)) & NETC_IERB_TBCR_RC_INST_MASK)
60702 
60703 #define NETC_IERB_TBCR_FN_MASK                   (0xF00U)
60704 #define NETC_IERB_TBCR_FN_SHIFT                  (8U)
60705 #define NETC_IERB_TBCR_FN(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_FN_SHIFT)) & NETC_IERB_TBCR_FN_MASK)
60706 
60707 #define NETC_IERB_TBCR_VALID_MASK                (0x80000000U)
60708 #define NETC_IERB_TBCR_VALID_SHIFT               (31U)
60709 #define NETC_IERB_TBCR_VALID(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_VALID_SHIFT)) & NETC_IERB_TBCR_VALID_MASK)
60710 /*! @} */
60711 
60712 /* The count of NETC_IERB_TBCR */
60713 #define NETC_IERB_TBCR_COUNT                     (1U)
60714 
60715 /*! @name TMCR - Timer 0 MSI-X configuration register */
60716 /*! @{ */
60717 
60718 #define NETC_IERB_TMCR_NUM_MSIX_MASK             (0x1U)
60719 #define NETC_IERB_TMCR_NUM_MSIX_SHIFT            (0U)
60720 #define NETC_IERB_TMCR_NUM_MSIX(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TMCR_NUM_MSIX_SHIFT)) & NETC_IERB_TMCR_NUM_MSIX_MASK)
60721 /*! @} */
60722 
60723 /* The count of NETC_IERB_TMCR */
60724 #define NETC_IERB_TMCR_COUNT                     (1U)
60725 
60726 /*! @name T_CFH_DIDVID - Timer 0 config header device ID and vendor ID register */
60727 /*! @{ */
60728 
60729 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK    (0xFFFFU)
60730 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT   (0U)
60731 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK)
60732 
60733 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK    (0xFFFF0000U)
60734 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT   (16U)
60735 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK)
60736 /*! @} */
60737 
60738 /* The count of NETC_IERB_T_CFH_DIDVID */
60739 #define NETC_IERB_T_CFH_DIDVID_COUNT             (1U)
60740 
60741 /*! @name T_CFH_SIDSVID - Timer 0 config header subsystem ID and subsystem vendor ID register */
60742 /*! @{ */
60743 
60744 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
60745 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
60746 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK)
60747 
60748 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U)
60749 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U)
60750 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK)
60751 /*! @} */
60752 
60753 /* The count of NETC_IERB_T_CFH_SIDSVID */
60754 #define NETC_IERB_T_CFH_SIDSVID_COUNT            (1U)
60755 
60756 /*! @name TBLPR - Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1 */
60757 /*! @{ */
60758 
60759 #define NETC_IERB_TBLPR_PARAM_VAL_MASK           (0xFFFFFFFFU)
60760 #define NETC_IERB_TBLPR_PARAM_VAL_SHIFT          (0U)
60761 #define NETC_IERB_TBLPR_PARAM_VAL(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_TBLPR_PARAM_VAL_MASK)
60762 /*! @} */
60763 
60764 /* The count of NETC_IERB_TBLPR */
60765 #define NETC_IERB_TBLPR_COUNT                    (1U)
60766 
60767 /* The count of NETC_IERB_TBLPR */
60768 #define NETC_IERB_TBLPR_COUNT2                   (2U)
60769 
60770 /*! @name L0CAPR - Link 0 capability register */
60771 /*! @{ */
60772 
60773 #define NETC_IERB_L0CAPR_LINK_TYPE_MASK          (0x10U)
60774 #define NETC_IERB_L0CAPR_LINK_TYPE_SHIFT         (4U)
60775 #define NETC_IERB_L0CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L0CAPR_LINK_TYPE_MASK)
60776 
60777 #define NETC_IERB_L0CAPR_NUM_TC_MASK             (0xF000U)
60778 #define NETC_IERB_L0CAPR_NUM_TC_SHIFT            (12U)
60779 #define NETC_IERB_L0CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_TC_SHIFT)) & NETC_IERB_L0CAPR_NUM_TC_MASK)
60780 
60781 #define NETC_IERB_L0CAPR_NUM_Q_MASK              (0xF0000U)
60782 #define NETC_IERB_L0CAPR_NUM_Q_SHIFT             (16U)
60783 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
60784 #define NETC_IERB_L0CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_Q_SHIFT)) & NETC_IERB_L0CAPR_NUM_Q_MASK)
60785 
60786 #define NETC_IERB_L0CAPR_NUM_CG_MASK             (0xF000000U)
60787 #define NETC_IERB_L0CAPR_NUM_CG_SHIFT            (24U)
60788 /*! NUM_CG - Number of congestion groups supported */
60789 #define NETC_IERB_L0CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_CG_SHIFT)) & NETC_IERB_L0CAPR_NUM_CG_MASK)
60790 
60791 #define NETC_IERB_L0CAPR_TGS_MASK                (0x10000000U)
60792 #define NETC_IERB_L0CAPR_TGS_SHIFT               (28U)
60793 /*! TGS - Time Gate Scheduling */
60794 #define NETC_IERB_L0CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_TGS_SHIFT)) & NETC_IERB_L0CAPR_TGS_MASK)
60795 
60796 #define NETC_IERB_L0CAPR_CBS_MASK                (0x20000000U)
60797 #define NETC_IERB_L0CAPR_CBS_SHIFT               (29U)
60798 /*! CBS - Credit Based Shaping */
60799 #define NETC_IERB_L0CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_CBS_SHIFT)) & NETC_IERB_L0CAPR_CBS_MASK)
60800 /*! @} */
60801 
60802 /*! @name L0MCAPR - Link 0 MAC capability register */
60803 /*! @{ */
60804 
60805 #define NETC_IERB_L0MCAPR_MAC_VAR_MASK           (0x7U)
60806 #define NETC_IERB_L0MCAPR_MAC_VAR_SHIFT          (0U)
60807 /*! MAC_VAR - MAC Variant */
60808 #define NETC_IERB_L0MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L0MCAPR_MAC_VAR_MASK)
60809 
60810 #define NETC_IERB_L0MCAPR_EFPAD_MASK             (0x30U)
60811 #define NETC_IERB_L0MCAPR_EFPAD_SHIFT            (4U)
60812 /*! EFPAD - Egress frame padding capability */
60813 #define NETC_IERB_L0MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_EFPAD_SHIFT)) & NETC_IERB_L0MCAPR_EFPAD_MASK)
60814 
60815 #define NETC_IERB_L0MCAPR_PIPG_MASK              (0x40U)
60816 #define NETC_IERB_L0MCAPR_PIPG_SHIFT             (6U)
60817 /*! PIPG - Configurable preamble/IPG capability */
60818 #define NETC_IERB_L0MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_PIPG_SHIFT)) & NETC_IERB_L0MCAPR_PIPG_MASK)
60819 
60820 #define NETC_IERB_L0MCAPR_HD_MASK                (0x100U)
60821 #define NETC_IERB_L0MCAPR_HD_SHIFT               (8U)
60822 /*! HD - Half Duplex capability */
60823 #define NETC_IERB_L0MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_HD_SHIFT)) & NETC_IERB_L0MCAPR_HD_MASK)
60824 
60825 #define NETC_IERB_L0MCAPR_FP_MASK                (0x600U)
60826 #define NETC_IERB_L0MCAPR_FP_SHIFT               (9U)
60827 /*! FP - Indicates if frame preemption is supported */
60828 #define NETC_IERB_L0MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_FP_SHIFT)) & NETC_IERB_L0MCAPR_FP_MASK)
60829 
60830 #define NETC_IERB_L0MCAPR_MIN_MPDU_MASK          (0x1000U)
60831 #define NETC_IERB_L0MCAPR_MIN_MPDU_SHIFT         (12U)
60832 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
60833 #define NETC_IERB_L0MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L0MCAPR_MIN_MPDU_MASK)
60834 
60835 #define NETC_IERB_L0MCAPR_MII_PROT_MASK          (0xF000000U)
60836 #define NETC_IERB_L0MCAPR_MII_PROT_SHIFT         (24U)
60837 /*! MII_PROT - Indicates the MII protocol supported */
60838 #define NETC_IERB_L0MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L0MCAPR_MII_PROT_MASK)
60839 /*! @} */
60840 
60841 /*! @name L0IOCAPR - Link 0 I/O capability register */
60842 /*! @{ */
60843 
60844 #define NETC_IERB_L0IOCAPR_PCS_PROT_MASK         (0xFFFFU)
60845 #define NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT        (0U)
60846 /*! PCS_PROT - PCS protocols supported */
60847 #define NETC_IERB_L0IOCAPR_PCS_PROT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L0IOCAPR_PCS_PROT_MASK)
60848 
60849 #define NETC_IERB_L0IOCAPR_IO_VAR_MASK           (0xF000000U)
60850 #define NETC_IERB_L0IOCAPR_IO_VAR_SHIFT          (24U)
60851 /*! IO_VAR - IO Variants supported */
60852 #define NETC_IERB_L0IOCAPR_IO_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L0IOCAPR_IO_VAR_MASK)
60853 
60854 #define NETC_IERB_L0IOCAPR_EMDIO_MASK            (0x10000000U)
60855 #define NETC_IERB_L0IOCAPR_EMDIO_SHIFT           (28U)
60856 /*! EMDIO - External MDIO supported. */
60857 #define NETC_IERB_L0IOCAPR_EMDIO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L0IOCAPR_EMDIO_MASK)
60858 
60859 #define NETC_IERB_L0IOCAPR_REVMII_RATE_MASK      (0x40000000U)
60860 #define NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT     (30U)
60861 /*! REVMII_RATE - RevMII MII rate */
60862 #define NETC_IERB_L0IOCAPR_REVMII_RATE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_RATE_MASK)
60863 
60864 #define NETC_IERB_L0IOCAPR_REVMII_MASK           (0x80000000U)
60865 #define NETC_IERB_L0IOCAPR_REVMII_SHIFT          (31U)
60866 /*! REVMII - Reverse Mode Device Configuration */
60867 #define NETC_IERB_L0IOCAPR_REVMII(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_MASK)
60868 /*! @} */
60869 
60870 /*! @name L0BCR - Link 0 binding configuration register */
60871 /*! @{ */
60872 
60873 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
60874 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT (0U)
60875 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK)
60876 
60877 #define NETC_IERB_L0BCR_NETC_FUNC_MASK           (0x40U)
60878 #define NETC_IERB_L0BCR_NETC_FUNC_SHIFT          (6U)
60879 #define NETC_IERB_L0BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L0BCR_NETC_FUNC_MASK)
60880 
60881 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK    (0x1F00U)
60882 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT   (8U)
60883 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK)
60884 
60885 #define NETC_IERB_L0BCR_SPL_SW_PORT_MASK         (0x1F0000U)
60886 #define NETC_IERB_L0BCR_SPL_SW_PORT_SHIFT        (16U)
60887 #define NETC_IERB_L0BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L0BCR_SPL_SW_PORT_MASK)
60888 /*! @} */
60889 
60890 /*! @name L0TXBCCTR - Link 0 transmit byte credit comfort threshold register */
60891 /*! @{ */
60892 
60893 #define NETC_IERB_L0TXBCCTR_THRESH_MASK          (0xFFFFU)
60894 #define NETC_IERB_L0TXBCCTR_THRESH_SHIFT         (0U)
60895 #define NETC_IERB_L0TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L0TXBCCTR_THRESH_MASK)
60896 /*! @} */
60897 
60898 /*! @name L0E0MAR0 - Link 0 end 0 MAC address register 0 */
60899 /*! @{ */
60900 
60901 #define NETC_IERB_L0E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
60902 #define NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT        (0U)
60903 #define NETC_IERB_L0E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR0_MAC_ADDR_MASK)
60904 /*! @} */
60905 
60906 /*! @name L0E0MAR1 - Link 0 end 0 MAC address register 1 */
60907 /*! @{ */
60908 
60909 #define NETC_IERB_L0E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
60910 #define NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT        (0U)
60911 #define NETC_IERB_L0E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR1_MAC_ADDR_MASK)
60912 /*! @} */
60913 
60914 /*! @name L1CAPR - Link 1 capability register */
60915 /*! @{ */
60916 
60917 #define NETC_IERB_L1CAPR_LINK_TYPE_MASK          (0x10U)
60918 #define NETC_IERB_L1CAPR_LINK_TYPE_SHIFT         (4U)
60919 #define NETC_IERB_L1CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L1CAPR_LINK_TYPE_MASK)
60920 
60921 #define NETC_IERB_L1CAPR_NUM_TC_MASK             (0xF000U)
60922 #define NETC_IERB_L1CAPR_NUM_TC_SHIFT            (12U)
60923 #define NETC_IERB_L1CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_TC_SHIFT)) & NETC_IERB_L1CAPR_NUM_TC_MASK)
60924 
60925 #define NETC_IERB_L1CAPR_NUM_Q_MASK              (0xF0000U)
60926 #define NETC_IERB_L1CAPR_NUM_Q_SHIFT             (16U)
60927 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
60928 #define NETC_IERB_L1CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_Q_SHIFT)) & NETC_IERB_L1CAPR_NUM_Q_MASK)
60929 
60930 #define NETC_IERB_L1CAPR_NUM_CG_MASK             (0xF000000U)
60931 #define NETC_IERB_L1CAPR_NUM_CG_SHIFT            (24U)
60932 /*! NUM_CG - Number of congestion groups supported */
60933 #define NETC_IERB_L1CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_CG_SHIFT)) & NETC_IERB_L1CAPR_NUM_CG_MASK)
60934 
60935 #define NETC_IERB_L1CAPR_TGS_MASK                (0x10000000U)
60936 #define NETC_IERB_L1CAPR_TGS_SHIFT               (28U)
60937 /*! TGS - Time Gate Scheduling */
60938 #define NETC_IERB_L1CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_TGS_SHIFT)) & NETC_IERB_L1CAPR_TGS_MASK)
60939 
60940 #define NETC_IERB_L1CAPR_CBS_MASK                (0x20000000U)
60941 #define NETC_IERB_L1CAPR_CBS_SHIFT               (29U)
60942 /*! CBS - Credit Based Shaping */
60943 #define NETC_IERB_L1CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_CBS_SHIFT)) & NETC_IERB_L1CAPR_CBS_MASK)
60944 /*! @} */
60945 
60946 /*! @name L1MCAPR - Link 1 MAC capability register */
60947 /*! @{ */
60948 
60949 #define NETC_IERB_L1MCAPR_MAC_VAR_MASK           (0x7U)
60950 #define NETC_IERB_L1MCAPR_MAC_VAR_SHIFT          (0U)
60951 /*! MAC_VAR - MAC Variant */
60952 #define NETC_IERB_L1MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L1MCAPR_MAC_VAR_MASK)
60953 
60954 #define NETC_IERB_L1MCAPR_EFPAD_MASK             (0x30U)
60955 #define NETC_IERB_L1MCAPR_EFPAD_SHIFT            (4U)
60956 /*! EFPAD - Egress frame padding capability */
60957 #define NETC_IERB_L1MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_EFPAD_SHIFT)) & NETC_IERB_L1MCAPR_EFPAD_MASK)
60958 
60959 #define NETC_IERB_L1MCAPR_PIPG_MASK              (0x40U)
60960 #define NETC_IERB_L1MCAPR_PIPG_SHIFT             (6U)
60961 /*! PIPG - Configurable preamble/IPG capability */
60962 #define NETC_IERB_L1MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_PIPG_SHIFT)) & NETC_IERB_L1MCAPR_PIPG_MASK)
60963 
60964 #define NETC_IERB_L1MCAPR_HD_MASK                (0x100U)
60965 #define NETC_IERB_L1MCAPR_HD_SHIFT               (8U)
60966 /*! HD - Half Duplex capability */
60967 #define NETC_IERB_L1MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_HD_SHIFT)) & NETC_IERB_L1MCAPR_HD_MASK)
60968 
60969 #define NETC_IERB_L1MCAPR_FP_MASK                (0x600U)
60970 #define NETC_IERB_L1MCAPR_FP_SHIFT               (9U)
60971 /*! FP - Indicates if frame preemption is supported */
60972 #define NETC_IERB_L1MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_FP_SHIFT)) & NETC_IERB_L1MCAPR_FP_MASK)
60973 
60974 #define NETC_IERB_L1MCAPR_MIN_MPDU_MASK          (0x1000U)
60975 #define NETC_IERB_L1MCAPR_MIN_MPDU_SHIFT         (12U)
60976 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
60977 #define NETC_IERB_L1MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L1MCAPR_MIN_MPDU_MASK)
60978 
60979 #define NETC_IERB_L1MCAPR_MII_PROT_MASK          (0xF000000U)
60980 #define NETC_IERB_L1MCAPR_MII_PROT_SHIFT         (24U)
60981 /*! MII_PROT - Indicates the MII protocol supported */
60982 #define NETC_IERB_L1MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L1MCAPR_MII_PROT_MASK)
60983 /*! @} */
60984 
60985 /*! @name L1IOCAPR - Link 1 I/O capability register */
60986 /*! @{ */
60987 
60988 #define NETC_IERB_L1IOCAPR_PCS_PROT_MASK         (0xFFFFU)
60989 #define NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT        (0U)
60990 /*! PCS_PROT - PCS protocols supported */
60991 #define NETC_IERB_L1IOCAPR_PCS_PROT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L1IOCAPR_PCS_PROT_MASK)
60992 
60993 #define NETC_IERB_L1IOCAPR_IO_VAR_MASK           (0xF000000U)
60994 #define NETC_IERB_L1IOCAPR_IO_VAR_SHIFT          (24U)
60995 /*! IO_VAR - IO Variants supported */
60996 #define NETC_IERB_L1IOCAPR_IO_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L1IOCAPR_IO_VAR_MASK)
60997 
60998 #define NETC_IERB_L1IOCAPR_EMDIO_MASK            (0x10000000U)
60999 #define NETC_IERB_L1IOCAPR_EMDIO_SHIFT           (28U)
61000 /*! EMDIO - External MDIO supported. */
61001 #define NETC_IERB_L1IOCAPR_EMDIO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L1IOCAPR_EMDIO_MASK)
61002 
61003 #define NETC_IERB_L1IOCAPR_REVMII_RATE_MASK      (0x40000000U)
61004 #define NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT     (30U)
61005 /*! REVMII_RATE - RevMII MII rate */
61006 #define NETC_IERB_L1IOCAPR_REVMII_RATE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_RATE_MASK)
61007 
61008 #define NETC_IERB_L1IOCAPR_REVMII_MASK           (0x80000000U)
61009 #define NETC_IERB_L1IOCAPR_REVMII_SHIFT          (31U)
61010 /*! REVMII - Reverse Mode Device Configuration */
61011 #define NETC_IERB_L1IOCAPR_REVMII(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_MASK)
61012 /*! @} */
61013 
61014 /*! @name L1BCR - Link 1 binding configuration register */
61015 /*! @{ */
61016 
61017 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
61018 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT (0U)
61019 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK)
61020 
61021 #define NETC_IERB_L1BCR_NETC_FUNC_MASK           (0x40U)
61022 #define NETC_IERB_L1BCR_NETC_FUNC_SHIFT          (6U)
61023 #define NETC_IERB_L1BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L1BCR_NETC_FUNC_MASK)
61024 
61025 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK    (0x1F00U)
61026 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT   (8U)
61027 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK)
61028 
61029 #define NETC_IERB_L1BCR_SPL_SW_PORT_MASK         (0x1F0000U)
61030 #define NETC_IERB_L1BCR_SPL_SW_PORT_SHIFT        (16U)
61031 #define NETC_IERB_L1BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L1BCR_SPL_SW_PORT_MASK)
61032 /*! @} */
61033 
61034 /*! @name L1TXBCCTR - Link 1 transmit byte credit comfort threshold register */
61035 /*! @{ */
61036 
61037 #define NETC_IERB_L1TXBCCTR_THRESH_MASK          (0xFFFFU)
61038 #define NETC_IERB_L1TXBCCTR_THRESH_SHIFT         (0U)
61039 #define NETC_IERB_L1TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L1TXBCCTR_THRESH_MASK)
61040 /*! @} */
61041 
61042 /*! @name L1E0MAR0 - Link 1 end 0 MAC address register 0 */
61043 /*! @{ */
61044 
61045 #define NETC_IERB_L1E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61046 #define NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT        (0U)
61047 #define NETC_IERB_L1E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR0_MAC_ADDR_MASK)
61048 /*! @} */
61049 
61050 /*! @name L1E0MAR1 - Link 1 end 0 MAC address register 1 */
61051 /*! @{ */
61052 
61053 #define NETC_IERB_L1E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
61054 #define NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT        (0U)
61055 #define NETC_IERB_L1E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR1_MAC_ADDR_MASK)
61056 /*! @} */
61057 
61058 /*! @name L2CAPR - Link 2 capability register */
61059 /*! @{ */
61060 
61061 #define NETC_IERB_L2CAPR_LINK_TYPE_MASK          (0x10U)
61062 #define NETC_IERB_L2CAPR_LINK_TYPE_SHIFT         (4U)
61063 #define NETC_IERB_L2CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L2CAPR_LINK_TYPE_MASK)
61064 
61065 #define NETC_IERB_L2CAPR_NUM_TC_MASK             (0xF000U)
61066 #define NETC_IERB_L2CAPR_NUM_TC_SHIFT            (12U)
61067 #define NETC_IERB_L2CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_TC_SHIFT)) & NETC_IERB_L2CAPR_NUM_TC_MASK)
61068 
61069 #define NETC_IERB_L2CAPR_NUM_Q_MASK              (0xF0000U)
61070 #define NETC_IERB_L2CAPR_NUM_Q_SHIFT             (16U)
61071 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
61072 #define NETC_IERB_L2CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_Q_SHIFT)) & NETC_IERB_L2CAPR_NUM_Q_MASK)
61073 
61074 #define NETC_IERB_L2CAPR_NUM_CG_MASK             (0xF000000U)
61075 #define NETC_IERB_L2CAPR_NUM_CG_SHIFT            (24U)
61076 /*! NUM_CG - Number of congestion groups supported */
61077 #define NETC_IERB_L2CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_CG_SHIFT)) & NETC_IERB_L2CAPR_NUM_CG_MASK)
61078 
61079 #define NETC_IERB_L2CAPR_TGS_MASK                (0x10000000U)
61080 #define NETC_IERB_L2CAPR_TGS_SHIFT               (28U)
61081 /*! TGS - Time Gate Scheduling */
61082 #define NETC_IERB_L2CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_TGS_SHIFT)) & NETC_IERB_L2CAPR_TGS_MASK)
61083 
61084 #define NETC_IERB_L2CAPR_CBS_MASK                (0x20000000U)
61085 #define NETC_IERB_L2CAPR_CBS_SHIFT               (29U)
61086 /*! CBS - Credit Based Shaping */
61087 #define NETC_IERB_L2CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_CBS_SHIFT)) & NETC_IERB_L2CAPR_CBS_MASK)
61088 /*! @} */
61089 
61090 /*! @name L2MCAPR - Link 2 MAC capability register */
61091 /*! @{ */
61092 
61093 #define NETC_IERB_L2MCAPR_MAC_VAR_MASK           (0x7U)
61094 #define NETC_IERB_L2MCAPR_MAC_VAR_SHIFT          (0U)
61095 /*! MAC_VAR - MAC Variant */
61096 #define NETC_IERB_L2MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L2MCAPR_MAC_VAR_MASK)
61097 
61098 #define NETC_IERB_L2MCAPR_EFPAD_MASK             (0x30U)
61099 #define NETC_IERB_L2MCAPR_EFPAD_SHIFT            (4U)
61100 /*! EFPAD - Egress frame padding capability */
61101 #define NETC_IERB_L2MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_EFPAD_SHIFT)) & NETC_IERB_L2MCAPR_EFPAD_MASK)
61102 
61103 #define NETC_IERB_L2MCAPR_PIPG_MASK              (0x40U)
61104 #define NETC_IERB_L2MCAPR_PIPG_SHIFT             (6U)
61105 /*! PIPG - Configurable preamble/IPG capability */
61106 #define NETC_IERB_L2MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_PIPG_SHIFT)) & NETC_IERB_L2MCAPR_PIPG_MASK)
61107 
61108 #define NETC_IERB_L2MCAPR_HD_MASK                (0x100U)
61109 #define NETC_IERB_L2MCAPR_HD_SHIFT               (8U)
61110 /*! HD - Half Duplex capability */
61111 #define NETC_IERB_L2MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_HD_SHIFT)) & NETC_IERB_L2MCAPR_HD_MASK)
61112 
61113 #define NETC_IERB_L2MCAPR_FP_MASK                (0x600U)
61114 #define NETC_IERB_L2MCAPR_FP_SHIFT               (9U)
61115 /*! FP - Indicates if frame preemption is supported */
61116 #define NETC_IERB_L2MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_FP_SHIFT)) & NETC_IERB_L2MCAPR_FP_MASK)
61117 
61118 #define NETC_IERB_L2MCAPR_MIN_MPDU_MASK          (0x1000U)
61119 #define NETC_IERB_L2MCAPR_MIN_MPDU_SHIFT         (12U)
61120 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
61121 #define NETC_IERB_L2MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L2MCAPR_MIN_MPDU_MASK)
61122 
61123 #define NETC_IERB_L2MCAPR_MII_PROT_MASK          (0xF000000U)
61124 #define NETC_IERB_L2MCAPR_MII_PROT_SHIFT         (24U)
61125 /*! MII_PROT - Indicates the MII protocol supported */
61126 #define NETC_IERB_L2MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L2MCAPR_MII_PROT_MASK)
61127 /*! @} */
61128 
61129 /*! @name L2IOCAPR - Link 2 I/O capability register */
61130 /*! @{ */
61131 
61132 #define NETC_IERB_L2IOCAPR_PCS_PROT_MASK         (0xFFFFU)
61133 #define NETC_IERB_L2IOCAPR_PCS_PROT_SHIFT        (0U)
61134 /*! PCS_PROT - PCS protocols supported */
61135 #define NETC_IERB_L2IOCAPR_PCS_PROT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L2IOCAPR_PCS_PROT_MASK)
61136 
61137 #define NETC_IERB_L2IOCAPR_IO_VAR_MASK           (0xF000000U)
61138 #define NETC_IERB_L2IOCAPR_IO_VAR_SHIFT          (24U)
61139 /*! IO_VAR - IO Variants supported */
61140 #define NETC_IERB_L2IOCAPR_IO_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L2IOCAPR_IO_VAR_MASK)
61141 
61142 #define NETC_IERB_L2IOCAPR_EMDIO_MASK            (0x10000000U)
61143 #define NETC_IERB_L2IOCAPR_EMDIO_SHIFT           (28U)
61144 /*! EMDIO - External MDIO supported. */
61145 #define NETC_IERB_L2IOCAPR_EMDIO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L2IOCAPR_EMDIO_MASK)
61146 
61147 #define NETC_IERB_L2IOCAPR_REVMII_RATE_MASK      (0x40000000U)
61148 #define NETC_IERB_L2IOCAPR_REVMII_RATE_SHIFT     (30U)
61149 /*! REVMII_RATE - RevMII MII rate */
61150 #define NETC_IERB_L2IOCAPR_REVMII_RATE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L2IOCAPR_REVMII_RATE_MASK)
61151 
61152 #define NETC_IERB_L2IOCAPR_REVMII_MASK           (0x80000000U)
61153 #define NETC_IERB_L2IOCAPR_REVMII_SHIFT          (31U)
61154 /*! REVMII - Reverse Mode Device Configuration */
61155 #define NETC_IERB_L2IOCAPR_REVMII(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_REVMII_SHIFT)) & NETC_IERB_L2IOCAPR_REVMII_MASK)
61156 /*! @} */
61157 
61158 /*! @name L2BCR - Link 2 binding configuration register */
61159 /*! @{ */
61160 
61161 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
61162 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT (0U)
61163 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK)
61164 
61165 #define NETC_IERB_L2BCR_NETC_FUNC_MASK           (0x40U)
61166 #define NETC_IERB_L2BCR_NETC_FUNC_SHIFT          (6U)
61167 #define NETC_IERB_L2BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L2BCR_NETC_FUNC_MASK)
61168 
61169 #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_MASK    (0x1F00U)
61170 #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_SHIFT   (8U)
61171 #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_MASK)
61172 
61173 #define NETC_IERB_L2BCR_SPL_SW_PORT_MASK         (0x1F0000U)
61174 #define NETC_IERB_L2BCR_SPL_SW_PORT_SHIFT        (16U)
61175 #define NETC_IERB_L2BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L2BCR_SPL_SW_PORT_MASK)
61176 /*! @} */
61177 
61178 /*! @name L2TXBCCTR - Link 2 transmit byte credit comfort threshold register */
61179 /*! @{ */
61180 
61181 #define NETC_IERB_L2TXBCCTR_THRESH_MASK          (0xFFFFU)
61182 #define NETC_IERB_L2TXBCCTR_THRESH_SHIFT         (0U)
61183 #define NETC_IERB_L2TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L2TXBCCTR_THRESH_MASK)
61184 /*! @} */
61185 
61186 /*! @name L2E0MAR0 - Link 2 end 0 MAC address register 0 */
61187 /*! @{ */
61188 
61189 #define NETC_IERB_L2E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61190 #define NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT        (0U)
61191 #define NETC_IERB_L2E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR0_MAC_ADDR_MASK)
61192 /*! @} */
61193 
61194 /*! @name L2E0MAR1 - Link 2 end 0 MAC address register 1 */
61195 /*! @{ */
61196 
61197 #define NETC_IERB_L2E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
61198 #define NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT        (0U)
61199 #define NETC_IERB_L2E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR1_MAC_ADDR_MASK)
61200 /*! @} */
61201 
61202 /*! @name L3CAPR - Link 3 capability register */
61203 /*! @{ */
61204 
61205 #define NETC_IERB_L3CAPR_LINK_TYPE_MASK          (0x10U)
61206 #define NETC_IERB_L3CAPR_LINK_TYPE_SHIFT         (4U)
61207 #define NETC_IERB_L3CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L3CAPR_LINK_TYPE_MASK)
61208 
61209 #define NETC_IERB_L3CAPR_NUM_TC_MASK             (0xF000U)
61210 #define NETC_IERB_L3CAPR_NUM_TC_SHIFT            (12U)
61211 #define NETC_IERB_L3CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_NUM_TC_SHIFT)) & NETC_IERB_L3CAPR_NUM_TC_MASK)
61212 
61213 #define NETC_IERB_L3CAPR_NUM_Q_MASK              (0xF0000U)
61214 #define NETC_IERB_L3CAPR_NUM_Q_SHIFT             (16U)
61215 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
61216 #define NETC_IERB_L3CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_NUM_Q_SHIFT)) & NETC_IERB_L3CAPR_NUM_Q_MASK)
61217 
61218 #define NETC_IERB_L3CAPR_NUM_CG_MASK             (0xF000000U)
61219 #define NETC_IERB_L3CAPR_NUM_CG_SHIFT            (24U)
61220 /*! NUM_CG - Number of congestion groups supported */
61221 #define NETC_IERB_L3CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_NUM_CG_SHIFT)) & NETC_IERB_L3CAPR_NUM_CG_MASK)
61222 
61223 #define NETC_IERB_L3CAPR_TGS_MASK                (0x10000000U)
61224 #define NETC_IERB_L3CAPR_TGS_SHIFT               (28U)
61225 /*! TGS - Time Gate Scheduling */
61226 #define NETC_IERB_L3CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_TGS_SHIFT)) & NETC_IERB_L3CAPR_TGS_MASK)
61227 
61228 #define NETC_IERB_L3CAPR_CBS_MASK                (0x20000000U)
61229 #define NETC_IERB_L3CAPR_CBS_SHIFT               (29U)
61230 /*! CBS - Credit Based Shaping */
61231 #define NETC_IERB_L3CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3CAPR_CBS_SHIFT)) & NETC_IERB_L3CAPR_CBS_MASK)
61232 /*! @} */
61233 
61234 /*! @name L3MCAPR - Link 3 MAC capability register */
61235 /*! @{ */
61236 
61237 #define NETC_IERB_L3MCAPR_MAC_VAR_MASK           (0x7U)
61238 #define NETC_IERB_L3MCAPR_MAC_VAR_SHIFT          (0U)
61239 /*! MAC_VAR - MAC Variant */
61240 #define NETC_IERB_L3MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L3MCAPR_MAC_VAR_MASK)
61241 
61242 #define NETC_IERB_L3MCAPR_EFPAD_MASK             (0x30U)
61243 #define NETC_IERB_L3MCAPR_EFPAD_SHIFT            (4U)
61244 /*! EFPAD - Egress frame padding capability */
61245 #define NETC_IERB_L3MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_EFPAD_SHIFT)) & NETC_IERB_L3MCAPR_EFPAD_MASK)
61246 
61247 #define NETC_IERB_L3MCAPR_PIPG_MASK              (0x40U)
61248 #define NETC_IERB_L3MCAPR_PIPG_SHIFT             (6U)
61249 /*! PIPG - Configurable preamble/IPG capability */
61250 #define NETC_IERB_L3MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_PIPG_SHIFT)) & NETC_IERB_L3MCAPR_PIPG_MASK)
61251 
61252 #define NETC_IERB_L3MCAPR_HD_MASK                (0x100U)
61253 #define NETC_IERB_L3MCAPR_HD_SHIFT               (8U)
61254 /*! HD - Half Duplex capability */
61255 #define NETC_IERB_L3MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_HD_SHIFT)) & NETC_IERB_L3MCAPR_HD_MASK)
61256 
61257 #define NETC_IERB_L3MCAPR_FP_MASK                (0x600U)
61258 #define NETC_IERB_L3MCAPR_FP_SHIFT               (9U)
61259 /*! FP - Indicates if frame preemption is supported */
61260 #define NETC_IERB_L3MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_FP_SHIFT)) & NETC_IERB_L3MCAPR_FP_MASK)
61261 
61262 #define NETC_IERB_L3MCAPR_MIN_MPDU_MASK          (0x1000U)
61263 #define NETC_IERB_L3MCAPR_MIN_MPDU_SHIFT         (12U)
61264 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
61265 #define NETC_IERB_L3MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L3MCAPR_MIN_MPDU_MASK)
61266 
61267 #define NETC_IERB_L3MCAPR_MII_PROT_MASK          (0xF000000U)
61268 #define NETC_IERB_L3MCAPR_MII_PROT_SHIFT         (24U)
61269 /*! MII_PROT - Indicates the MII protocol supported */
61270 #define NETC_IERB_L3MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L3MCAPR_MII_PROT_MASK)
61271 /*! @} */
61272 
61273 /*! @name L3IOCAPR - Link 3 I/O capability register */
61274 /*! @{ */
61275 
61276 #define NETC_IERB_L3IOCAPR_PCS_PROT_MASK         (0xFFFFU)
61277 #define NETC_IERB_L3IOCAPR_PCS_PROT_SHIFT        (0U)
61278 /*! PCS_PROT - PCS protocols supported */
61279 #define NETC_IERB_L3IOCAPR_PCS_PROT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L3IOCAPR_PCS_PROT_MASK)
61280 
61281 #define NETC_IERB_L3IOCAPR_IO_VAR_MASK           (0xF000000U)
61282 #define NETC_IERB_L3IOCAPR_IO_VAR_SHIFT          (24U)
61283 /*! IO_VAR - IO Variants supported */
61284 #define NETC_IERB_L3IOCAPR_IO_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L3IOCAPR_IO_VAR_MASK)
61285 
61286 #define NETC_IERB_L3IOCAPR_EMDIO_MASK            (0x10000000U)
61287 #define NETC_IERB_L3IOCAPR_EMDIO_SHIFT           (28U)
61288 /*! EMDIO - External MDIO supported. */
61289 #define NETC_IERB_L3IOCAPR_EMDIO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L3IOCAPR_EMDIO_MASK)
61290 
61291 #define NETC_IERB_L3IOCAPR_REVMII_RATE_MASK      (0x40000000U)
61292 #define NETC_IERB_L3IOCAPR_REVMII_RATE_SHIFT     (30U)
61293 /*! REVMII_RATE - RevMII MII rate */
61294 #define NETC_IERB_L3IOCAPR_REVMII_RATE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L3IOCAPR_REVMII_RATE_MASK)
61295 
61296 #define NETC_IERB_L3IOCAPR_REVMII_MASK           (0x80000000U)
61297 #define NETC_IERB_L3IOCAPR_REVMII_SHIFT          (31U)
61298 /*! REVMII - Reverse Mode Device Configuration */
61299 #define NETC_IERB_L3IOCAPR_REVMII(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3IOCAPR_REVMII_SHIFT)) & NETC_IERB_L3IOCAPR_REVMII_MASK)
61300 /*! @} */
61301 
61302 /*! @name L3BCR - Link 3 binding configuration register */
61303 /*! @{ */
61304 
61305 #define NETC_IERB_L3BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
61306 #define NETC_IERB_L3BCR_SW_PORT_ENETC_INST_SHIFT (0U)
61307 #define NETC_IERB_L3BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L3BCR_SW_PORT_ENETC_INST_MASK)
61308 
61309 #define NETC_IERB_L3BCR_NETC_FUNC_MASK           (0x40U)
61310 #define NETC_IERB_L3BCR_NETC_FUNC_SHIFT          (6U)
61311 #define NETC_IERB_L3BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L3BCR_NETC_FUNC_MASK)
61312 
61313 #define NETC_IERB_L3BCR_MDIO_PHYAD_PRTAD_MASK    (0x1F00U)
61314 #define NETC_IERB_L3BCR_MDIO_PHYAD_PRTAD_SHIFT   (8U)
61315 #define NETC_IERB_L3BCR_MDIO_PHYAD_PRTAD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L3BCR_MDIO_PHYAD_PRTAD_MASK)
61316 
61317 #define NETC_IERB_L3BCR_SPL_SW_PORT_MASK         (0x1F0000U)
61318 #define NETC_IERB_L3BCR_SPL_SW_PORT_SHIFT        (16U)
61319 #define NETC_IERB_L3BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L3BCR_SPL_SW_PORT_MASK)
61320 /*! @} */
61321 
61322 /*! @name L3TXBCCTR - Link 3 transmit byte credit comfort threshold register */
61323 /*! @{ */
61324 
61325 #define NETC_IERB_L3TXBCCTR_THRESH_MASK          (0xFFFFU)
61326 #define NETC_IERB_L3TXBCCTR_THRESH_SHIFT         (0U)
61327 #define NETC_IERB_L3TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L3TXBCCTR_THRESH_MASK)
61328 /*! @} */
61329 
61330 /*! @name L3E0MAR0 - Link 3 end 0 MAC address register 0 */
61331 /*! @{ */
61332 
61333 #define NETC_IERB_L3E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61334 #define NETC_IERB_L3E0MAR0_MAC_ADDR_SHIFT        (0U)
61335 #define NETC_IERB_L3E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L3E0MAR0_MAC_ADDR_MASK)
61336 /*! @} */
61337 
61338 /*! @name L3E0MAR1 - Link 3 end 0 MAC address register 1 */
61339 /*! @{ */
61340 
61341 #define NETC_IERB_L3E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
61342 #define NETC_IERB_L3E0MAR1_MAC_ADDR_SHIFT        (0U)
61343 #define NETC_IERB_L3E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L3E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L3E0MAR1_MAC_ADDR_MASK)
61344 /*! @} */
61345 
61346 /*! @name L4CAPR - Link 4 capability register */
61347 /*! @{ */
61348 
61349 #define NETC_IERB_L4CAPR_LINK_TYPE_MASK          (0x10U)
61350 #define NETC_IERB_L4CAPR_LINK_TYPE_SHIFT         (4U)
61351 #define NETC_IERB_L4CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L4CAPR_LINK_TYPE_MASK)
61352 
61353 #define NETC_IERB_L4CAPR_NUM_TC_MASK             (0xF000U)
61354 #define NETC_IERB_L4CAPR_NUM_TC_SHIFT            (12U)
61355 #define NETC_IERB_L4CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_NUM_TC_SHIFT)) & NETC_IERB_L4CAPR_NUM_TC_MASK)
61356 
61357 #define NETC_IERB_L4CAPR_NUM_Q_MASK              (0xF0000U)
61358 #define NETC_IERB_L4CAPR_NUM_Q_SHIFT             (16U)
61359 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
61360 #define NETC_IERB_L4CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_NUM_Q_SHIFT)) & NETC_IERB_L4CAPR_NUM_Q_MASK)
61361 
61362 #define NETC_IERB_L4CAPR_NUM_CG_MASK             (0xF000000U)
61363 #define NETC_IERB_L4CAPR_NUM_CG_SHIFT            (24U)
61364 /*! NUM_CG - Number of congestion groups supported */
61365 #define NETC_IERB_L4CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_NUM_CG_SHIFT)) & NETC_IERB_L4CAPR_NUM_CG_MASK)
61366 
61367 #define NETC_IERB_L4CAPR_TGS_MASK                (0x10000000U)
61368 #define NETC_IERB_L4CAPR_TGS_SHIFT               (28U)
61369 /*! TGS - Time Gate Scheduling */
61370 #define NETC_IERB_L4CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_TGS_SHIFT)) & NETC_IERB_L4CAPR_TGS_MASK)
61371 
61372 #define NETC_IERB_L4CAPR_CBS_MASK                (0x20000000U)
61373 #define NETC_IERB_L4CAPR_CBS_SHIFT               (29U)
61374 /*! CBS - Credit Based Shaping */
61375 #define NETC_IERB_L4CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4CAPR_CBS_SHIFT)) & NETC_IERB_L4CAPR_CBS_MASK)
61376 /*! @} */
61377 
61378 /*! @name L4MCAPR - Link 4 MAC capability register */
61379 /*! @{ */
61380 
61381 #define NETC_IERB_L4MCAPR_MAC_VAR_MASK           (0x7U)
61382 #define NETC_IERB_L4MCAPR_MAC_VAR_SHIFT          (0U)
61383 /*! MAC_VAR - MAC Variant */
61384 #define NETC_IERB_L4MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L4MCAPR_MAC_VAR_MASK)
61385 
61386 #define NETC_IERB_L4MCAPR_EFPAD_MASK             (0x30U)
61387 #define NETC_IERB_L4MCAPR_EFPAD_SHIFT            (4U)
61388 /*! EFPAD - Egress frame padding capability */
61389 #define NETC_IERB_L4MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_EFPAD_SHIFT)) & NETC_IERB_L4MCAPR_EFPAD_MASK)
61390 
61391 #define NETC_IERB_L4MCAPR_PIPG_MASK              (0x40U)
61392 #define NETC_IERB_L4MCAPR_PIPG_SHIFT             (6U)
61393 /*! PIPG - Configurable preamble/IPG capability */
61394 #define NETC_IERB_L4MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_PIPG_SHIFT)) & NETC_IERB_L4MCAPR_PIPG_MASK)
61395 
61396 #define NETC_IERB_L4MCAPR_HD_MASK                (0x100U)
61397 #define NETC_IERB_L4MCAPR_HD_SHIFT               (8U)
61398 /*! HD - Half Duplex capability */
61399 #define NETC_IERB_L4MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_HD_SHIFT)) & NETC_IERB_L4MCAPR_HD_MASK)
61400 
61401 #define NETC_IERB_L4MCAPR_FP_MASK                (0x600U)
61402 #define NETC_IERB_L4MCAPR_FP_SHIFT               (9U)
61403 /*! FP - Indicates if frame preemption is supported */
61404 #define NETC_IERB_L4MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_FP_SHIFT)) & NETC_IERB_L4MCAPR_FP_MASK)
61405 
61406 #define NETC_IERB_L4MCAPR_MIN_MPDU_MASK          (0x1000U)
61407 #define NETC_IERB_L4MCAPR_MIN_MPDU_SHIFT         (12U)
61408 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
61409 #define NETC_IERB_L4MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L4MCAPR_MIN_MPDU_MASK)
61410 
61411 #define NETC_IERB_L4MCAPR_MII_PROT_MASK          (0xF000000U)
61412 #define NETC_IERB_L4MCAPR_MII_PROT_SHIFT         (24U)
61413 /*! MII_PROT - Indicates the MII protocol supported */
61414 #define NETC_IERB_L4MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L4MCAPR_MII_PROT_MASK)
61415 /*! @} */
61416 
61417 /*! @name L4IOCAPR - Link 4 I/O capability register */
61418 /*! @{ */
61419 
61420 #define NETC_IERB_L4IOCAPR_PCS_PROT_MASK         (0xFFFFU)
61421 #define NETC_IERB_L4IOCAPR_PCS_PROT_SHIFT        (0U)
61422 /*! PCS_PROT - PCS protocols supported */
61423 #define NETC_IERB_L4IOCAPR_PCS_PROT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L4IOCAPR_PCS_PROT_MASK)
61424 
61425 #define NETC_IERB_L4IOCAPR_IO_VAR_MASK           (0xF000000U)
61426 #define NETC_IERB_L4IOCAPR_IO_VAR_SHIFT          (24U)
61427 /*! IO_VAR - IO Variants supported */
61428 #define NETC_IERB_L4IOCAPR_IO_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L4IOCAPR_IO_VAR_MASK)
61429 
61430 #define NETC_IERB_L4IOCAPR_EMDIO_MASK            (0x10000000U)
61431 #define NETC_IERB_L4IOCAPR_EMDIO_SHIFT           (28U)
61432 /*! EMDIO - External MDIO supported. */
61433 #define NETC_IERB_L4IOCAPR_EMDIO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L4IOCAPR_EMDIO_MASK)
61434 
61435 #define NETC_IERB_L4IOCAPR_REVMII_RATE_MASK      (0x40000000U)
61436 #define NETC_IERB_L4IOCAPR_REVMII_RATE_SHIFT     (30U)
61437 /*! REVMII_RATE - RevMII MII rate */
61438 #define NETC_IERB_L4IOCAPR_REVMII_RATE(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L4IOCAPR_REVMII_RATE_MASK)
61439 
61440 #define NETC_IERB_L4IOCAPR_REVMII_MASK           (0x80000000U)
61441 #define NETC_IERB_L4IOCAPR_REVMII_SHIFT          (31U)
61442 /*! REVMII - Reverse Mode Device Configuration */
61443 #define NETC_IERB_L4IOCAPR_REVMII(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4IOCAPR_REVMII_SHIFT)) & NETC_IERB_L4IOCAPR_REVMII_MASK)
61444 /*! @} */
61445 
61446 /*! @name L4BCR - Link 4 binding configuration register */
61447 /*! @{ */
61448 
61449 #define NETC_IERB_L4BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
61450 #define NETC_IERB_L4BCR_SW_PORT_ENETC_INST_SHIFT (0U)
61451 #define NETC_IERB_L4BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L4BCR_SW_PORT_ENETC_INST_MASK)
61452 
61453 #define NETC_IERB_L4BCR_NETC_FUNC_MASK           (0x40U)
61454 #define NETC_IERB_L4BCR_NETC_FUNC_SHIFT          (6U)
61455 #define NETC_IERB_L4BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L4BCR_NETC_FUNC_MASK)
61456 
61457 #define NETC_IERB_L4BCR_MDIO_PHYAD_PRTAD_MASK    (0x1F00U)
61458 #define NETC_IERB_L4BCR_MDIO_PHYAD_PRTAD_SHIFT   (8U)
61459 #define NETC_IERB_L4BCR_MDIO_PHYAD_PRTAD(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L4BCR_MDIO_PHYAD_PRTAD_MASK)
61460 
61461 #define NETC_IERB_L4BCR_SPL_SW_PORT_MASK         (0x1F0000U)
61462 #define NETC_IERB_L4BCR_SPL_SW_PORT_SHIFT        (16U)
61463 #define NETC_IERB_L4BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L4BCR_SPL_SW_PORT_MASK)
61464 /*! @} */
61465 
61466 /*! @name L4TXBCCTR - Link 4 transmit byte credit comfort threshold register */
61467 /*! @{ */
61468 
61469 #define NETC_IERB_L4TXBCCTR_THRESH_MASK          (0xFFFFU)
61470 #define NETC_IERB_L4TXBCCTR_THRESH_SHIFT         (0U)
61471 #define NETC_IERB_L4TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L4TXBCCTR_THRESH_MASK)
61472 /*! @} */
61473 
61474 /*! @name L4E0MAR0 - Link 4 end 0 MAC address register 0 */
61475 /*! @{ */
61476 
61477 #define NETC_IERB_L4E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61478 #define NETC_IERB_L4E0MAR0_MAC_ADDR_SHIFT        (0U)
61479 #define NETC_IERB_L4E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L4E0MAR0_MAC_ADDR_MASK)
61480 /*! @} */
61481 
61482 /*! @name L4E0MAR1 - Link 4 end 0 MAC address register 1 */
61483 /*! @{ */
61484 
61485 #define NETC_IERB_L4E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
61486 #define NETC_IERB_L4E0MAR1_MAC_ADDR_SHIFT        (0U)
61487 #define NETC_IERB_L4E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L4E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L4E0MAR1_MAC_ADDR_MASK)
61488 /*! @} */
61489 
61490 /*! @name L5CAPR - Link 5 capability register */
61491 /*! @{ */
61492 
61493 #define NETC_IERB_L5CAPR_LINK_TYPE_MASK          (0x10U)
61494 #define NETC_IERB_L5CAPR_LINK_TYPE_SHIFT         (4U)
61495 #define NETC_IERB_L5CAPR_LINK_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L5CAPR_LINK_TYPE_MASK)
61496 
61497 #define NETC_IERB_L5CAPR_NUM_TC_MASK             (0xF000U)
61498 #define NETC_IERB_L5CAPR_NUM_TC_SHIFT            (12U)
61499 #define NETC_IERB_L5CAPR_NUM_TC(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_NUM_TC_SHIFT)) & NETC_IERB_L5CAPR_NUM_TC_MASK)
61500 
61501 #define NETC_IERB_L5CAPR_NUM_Q_MASK              (0xF0000U)
61502 #define NETC_IERB_L5CAPR_NUM_Q_SHIFT             (16U)
61503 /*! NUM_Q - Number of Egress Traffic Management (ETM) class queues supported */
61504 #define NETC_IERB_L5CAPR_NUM_Q(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_NUM_Q_SHIFT)) & NETC_IERB_L5CAPR_NUM_Q_MASK)
61505 
61506 #define NETC_IERB_L5CAPR_NUM_CG_MASK             (0xF000000U)
61507 #define NETC_IERB_L5CAPR_NUM_CG_SHIFT            (24U)
61508 /*! NUM_CG - Number of congestion groups supported */
61509 #define NETC_IERB_L5CAPR_NUM_CG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_NUM_CG_SHIFT)) & NETC_IERB_L5CAPR_NUM_CG_MASK)
61510 
61511 #define NETC_IERB_L5CAPR_TGS_MASK                (0x10000000U)
61512 #define NETC_IERB_L5CAPR_TGS_SHIFT               (28U)
61513 /*! TGS - Time Gate Scheduling */
61514 #define NETC_IERB_L5CAPR_TGS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_TGS_SHIFT)) & NETC_IERB_L5CAPR_TGS_MASK)
61515 
61516 #define NETC_IERB_L5CAPR_CBS_MASK                (0x20000000U)
61517 #define NETC_IERB_L5CAPR_CBS_SHIFT               (29U)
61518 /*! CBS - Credit Based Shaping */
61519 #define NETC_IERB_L5CAPR_CBS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5CAPR_CBS_SHIFT)) & NETC_IERB_L5CAPR_CBS_MASK)
61520 /*! @} */
61521 
61522 /*! @name L5MCAPR - Link 5 MAC capability register */
61523 /*! @{ */
61524 
61525 #define NETC_IERB_L5MCAPR_MAC_VAR_MASK           (0x7U)
61526 #define NETC_IERB_L5MCAPR_MAC_VAR_SHIFT          (0U)
61527 /*! MAC_VAR - MAC Variant */
61528 #define NETC_IERB_L5MCAPR_MAC_VAR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L5MCAPR_MAC_VAR_MASK)
61529 
61530 #define NETC_IERB_L5MCAPR_EFPAD_MASK             (0x30U)
61531 #define NETC_IERB_L5MCAPR_EFPAD_SHIFT            (4U)
61532 /*! EFPAD - Egress frame padding capability */
61533 #define NETC_IERB_L5MCAPR_EFPAD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_EFPAD_SHIFT)) & NETC_IERB_L5MCAPR_EFPAD_MASK)
61534 
61535 #define NETC_IERB_L5MCAPR_PIPG_MASK              (0x40U)
61536 #define NETC_IERB_L5MCAPR_PIPG_SHIFT             (6U)
61537 /*! PIPG - Configurable preamble/IPG capability */
61538 #define NETC_IERB_L5MCAPR_PIPG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_PIPG_SHIFT)) & NETC_IERB_L5MCAPR_PIPG_MASK)
61539 
61540 #define NETC_IERB_L5MCAPR_HD_MASK                (0x100U)
61541 #define NETC_IERB_L5MCAPR_HD_SHIFT               (8U)
61542 /*! HD - Half Duplex capability */
61543 #define NETC_IERB_L5MCAPR_HD(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_HD_SHIFT)) & NETC_IERB_L5MCAPR_HD_MASK)
61544 
61545 #define NETC_IERB_L5MCAPR_FP_MASK                (0x600U)
61546 #define NETC_IERB_L5MCAPR_FP_SHIFT               (9U)
61547 /*! FP - Indicates if frame preemption is supported */
61548 #define NETC_IERB_L5MCAPR_FP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_FP_SHIFT)) & NETC_IERB_L5MCAPR_FP_MASK)
61549 
61550 #define NETC_IERB_L5MCAPR_MIN_MPDU_MASK          (0x1000U)
61551 #define NETC_IERB_L5MCAPR_MIN_MPDU_SHIFT         (12U)
61552 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
61553 #define NETC_IERB_L5MCAPR_MIN_MPDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_MIN_MPDU_SHIFT)) & NETC_IERB_L5MCAPR_MIN_MPDU_MASK)
61554 
61555 #define NETC_IERB_L5MCAPR_MII_PROT_MASK          (0xF000000U)
61556 #define NETC_IERB_L5MCAPR_MII_PROT_SHIFT         (24U)
61557 /*! MII_PROT - Indicates the MII protocol supported */
61558 #define NETC_IERB_L5MCAPR_MII_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L5MCAPR_MII_PROT_MASK)
61559 /*! @} */
61560 
61561 /*! @name L5BCR - Link 5 binding configuration register */
61562 /*! @{ */
61563 
61564 #define NETC_IERB_L5BCR_SW_PORT_ENETC_INST_MASK  (0x1FU)
61565 #define NETC_IERB_L5BCR_SW_PORT_ENETC_INST_SHIFT (0U)
61566 #define NETC_IERB_L5BCR_SW_PORT_ENETC_INST(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L5BCR_SW_PORT_ENETC_INST_MASK)
61567 
61568 #define NETC_IERB_L5BCR_NETC_FUNC_MASK           (0x40U)
61569 #define NETC_IERB_L5BCR_NETC_FUNC_SHIFT          (6U)
61570 #define NETC_IERB_L5BCR_NETC_FUNC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L5BCR_NETC_FUNC_MASK)
61571 
61572 #define NETC_IERB_L5BCR_SPL_SW_PORT_MASK         (0x1F0000U)
61573 #define NETC_IERB_L5BCR_SPL_SW_PORT_SHIFT        (16U)
61574 #define NETC_IERB_L5BCR_SPL_SW_PORT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L5BCR_SPL_SW_PORT_MASK)
61575 /*! @} */
61576 
61577 /*! @name L5TXBCCTR - Link 5 transmit byte credit comfort threshold register */
61578 /*! @{ */
61579 
61580 #define NETC_IERB_L5TXBCCTR_THRESH_MASK          (0xFFFFU)
61581 #define NETC_IERB_L5TXBCCTR_THRESH_SHIFT         (0U)
61582 #define NETC_IERB_L5TXBCCTR_THRESH(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L5TXBCCTR_THRESH_MASK)
61583 /*! @} */
61584 
61585 /*! @name L5E0MAR0 - Link 5 end 0 MAC address register 0 */
61586 /*! @{ */
61587 
61588 #define NETC_IERB_L5E0MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61589 #define NETC_IERB_L5E0MAR0_MAC_ADDR_SHIFT        (0U)
61590 #define NETC_IERB_L5E0MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L5E0MAR0_MAC_ADDR_MASK)
61591 /*! @} */
61592 
61593 /*! @name L5E0MAR1 - Link 5 end 0 MAC address register 1 */
61594 /*! @{ */
61595 
61596 #define NETC_IERB_L5E0MAR1_MAC_ADDR_MASK         (0xFFFFU)
61597 #define NETC_IERB_L5E0MAR1_MAC_ADDR_SHIFT        (0U)
61598 #define NETC_IERB_L5E0MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L5E0MAR1_MAC_ADDR_MASK)
61599 /*! @} */
61600 
61601 /*! @name L5E1MAR0 - Link 5 end 1 MAC address register 0 */
61602 /*! @{ */
61603 
61604 #define NETC_IERB_L5E1MAR0_MAC_ADDR_MASK         (0xFFFFFFFFU)
61605 #define NETC_IERB_L5E1MAR0_MAC_ADDR_SHIFT        (0U)
61606 #define NETC_IERB_L5E1MAR0_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5E1MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L5E1MAR0_MAC_ADDR_MASK)
61607 /*! @} */
61608 
61609 /*! @name L5E1MAR1 - Link 5 end 1 MAC address register 1 */
61610 /*! @{ */
61611 
61612 #define NETC_IERB_L5E1MAR1_MAC_ADDR_MASK         (0xFFFFU)
61613 #define NETC_IERB_L5E1MAR1_MAC_ADDR_SHIFT        (0U)
61614 #define NETC_IERB_L5E1MAR1_MAC_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L5E1MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L5E1MAR1_MAC_ADDR_MASK)
61615 /*! @} */
61616 
61617 /*! @name SBCR - Switch 0 binding configuration register */
61618 /*! @{ */
61619 
61620 #define NETC_IERB_SBCR_RC_INST_MASK              (0xFU)
61621 #define NETC_IERB_SBCR_RC_INST_SHIFT             (0U)
61622 #define NETC_IERB_SBCR_RC_INST(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_RC_INST_SHIFT)) & NETC_IERB_SBCR_RC_INST_MASK)
61623 
61624 #define NETC_IERB_SBCR_FN_MASK                   (0xF00U)
61625 #define NETC_IERB_SBCR_FN_SHIFT                  (8U)
61626 #define NETC_IERB_SBCR_FN(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_FN_SHIFT)) & NETC_IERB_SBCR_FN_MASK)
61627 
61628 #define NETC_IERB_SBCR_VALID_MASK                (0x80000000U)
61629 #define NETC_IERB_SBCR_VALID_SHIFT               (31U)
61630 #define NETC_IERB_SBCR_VALID(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_VALID_SHIFT)) & NETC_IERB_SBCR_VALID_MASK)
61631 /*! @} */
61632 
61633 /* The count of NETC_IERB_SBCR */
61634 #define NETC_IERB_SBCR_COUNT                     (1U)
61635 
61636 /*! @name SMCR - Switch 0 MSI-X configuration register */
61637 /*! @{ */
61638 
61639 #define NETC_IERB_SMCR_NUM_MSIX_MASK             (0xFU)
61640 #define NETC_IERB_SMCR_NUM_MSIX_SHIFT            (0U)
61641 #define NETC_IERB_SMCR_NUM_MSIX(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMCR_NUM_MSIX_SHIFT)) & NETC_IERB_SMCR_NUM_MSIX_MASK)
61642 /*! @} */
61643 
61644 /* The count of NETC_IERB_SMCR */
61645 #define NETC_IERB_SMCR_COUNT                     (1U)
61646 
61647 /*! @name S_CFH_DIDVID - Switch 0 config header device ID and vendor ID register */
61648 /*! @{ */
61649 
61650 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID_MASK    (0xFFFFU)
61651 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID_SHIFT   (0U)
61652 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_S_CFH_DIDVID_VENDOR_ID_MASK)
61653 
61654 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID_MASK    (0xFFFF0000U)
61655 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID_SHIFT   (16U)
61656 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_S_CFH_DIDVID_DEVICE_ID_MASK)
61657 /*! @} */
61658 
61659 /* The count of NETC_IERB_S_CFH_DIDVID */
61660 #define NETC_IERB_S_CFH_DIDVID_COUNT             (1U)
61661 
61662 /*! @name S_CFH_SIDSVID - Switch 0 config header subsystem ID and subsystem vendor ID register */
61663 /*! @{ */
61664 
61665 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
61666 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
61667 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK)
61668 
61669 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U)
61670 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U)
61671 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK)
61672 /*! @} */
61673 
61674 /* The count of NETC_IERB_S_CFH_SIDSVID */
61675 #define NETC_IERB_S_CFH_SIDSVID_COUNT            (1U)
61676 
61677 /*! @name SCCAR - Switch 0 command cache attribute register */
61678 /*! @{ */
61679 
61680 #define NETC_IERB_SCCAR_CBD_WRCACHE_MASK         (0xFU)
61681 #define NETC_IERB_SCCAR_CBD_WRCACHE_SHIFT        (0U)
61682 #define NETC_IERB_SCCAR_CBD_WRCACHE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRCACHE_SHIFT)) & NETC_IERB_SCCAR_CBD_WRCACHE_MASK)
61683 
61684 #define NETC_IERB_SCCAR_CBD_WRDOMAIN_MASK        (0x30U)
61685 #define NETC_IERB_SCCAR_CBD_WRDOMAIN_SHIFT       (4U)
61686 #define NETC_IERB_SCCAR_CBD_WRDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CBD_WRDOMAIN_MASK)
61687 
61688 #define NETC_IERB_SCCAR_CBD_WRSNP_MASK           (0x40U)
61689 #define NETC_IERB_SCCAR_CBD_WRSNP_SHIFT          (6U)
61690 #define NETC_IERB_SCCAR_CBD_WRSNP(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRSNP_SHIFT)) & NETC_IERB_SCCAR_CBD_WRSNP_MASK)
61691 
61692 #define NETC_IERB_SCCAR_CWRCACHE_MASK            (0xF00U)
61693 #define NETC_IERB_SCCAR_CWRCACHE_SHIFT           (8U)
61694 #define NETC_IERB_SCCAR_CWRCACHE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRCACHE_SHIFT)) & NETC_IERB_SCCAR_CWRCACHE_MASK)
61695 
61696 #define NETC_IERB_SCCAR_CWRDOMAIN_MASK           (0x3000U)
61697 #define NETC_IERB_SCCAR_CWRDOMAIN_SHIFT          (12U)
61698 #define NETC_IERB_SCCAR_CWRDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CWRDOMAIN_MASK)
61699 
61700 #define NETC_IERB_SCCAR_CWRSNP_MASK              (0x4000U)
61701 #define NETC_IERB_SCCAR_CWRSNP_SHIFT             (14U)
61702 #define NETC_IERB_SCCAR_CWRSNP(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRSNP_SHIFT)) & NETC_IERB_SCCAR_CWRSNP_MASK)
61703 
61704 #define NETC_IERB_SCCAR_CBD_RDCACHE_MASK         (0xF0000U)
61705 #define NETC_IERB_SCCAR_CBD_RDCACHE_SHIFT        (16U)
61706 #define NETC_IERB_SCCAR_CBD_RDCACHE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDCACHE_SHIFT)) & NETC_IERB_SCCAR_CBD_RDCACHE_MASK)
61707 
61708 #define NETC_IERB_SCCAR_CBD_RDDOMAIN_MASK        (0x300000U)
61709 #define NETC_IERB_SCCAR_CBD_RDDOMAIN_SHIFT       (20U)
61710 #define NETC_IERB_SCCAR_CBD_RDDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CBD_RDDOMAIN_MASK)
61711 
61712 #define NETC_IERB_SCCAR_CBD_RDSNP_MASK           (0x400000U)
61713 #define NETC_IERB_SCCAR_CBD_RDSNP_SHIFT          (22U)
61714 #define NETC_IERB_SCCAR_CBD_RDSNP(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDSNP_SHIFT)) & NETC_IERB_SCCAR_CBD_RDSNP_MASK)
61715 
61716 #define NETC_IERB_SCCAR_CRDCACHE_MASK            (0xF000000U)
61717 #define NETC_IERB_SCCAR_CRDCACHE_SHIFT           (24U)
61718 #define NETC_IERB_SCCAR_CRDCACHE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDCACHE_SHIFT)) & NETC_IERB_SCCAR_CRDCACHE_MASK)
61719 
61720 #define NETC_IERB_SCCAR_CRDDOMAIN_MASK           (0x30000000U)
61721 #define NETC_IERB_SCCAR_CRDDOMAIN_SHIFT          (28U)
61722 #define NETC_IERB_SCCAR_CRDDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CRDDOMAIN_MASK)
61723 
61724 #define NETC_IERB_SCCAR_CRDSNP_MASK              (0x40000000U)
61725 #define NETC_IERB_SCCAR_CRDSNP_SHIFT             (30U)
61726 #define NETC_IERB_SCCAR_CRDSNP(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDSNP_SHIFT)) & NETC_IERB_SCCAR_CRDSNP_MASK)
61727 /*! @} */
61728 
61729 /* The count of NETC_IERB_SCCAR */
61730 #define NETC_IERB_SCCAR_COUNT                    (1U)
61731 
61732 /*! @name SAMQR - Switch 0 access management qualifier register */
61733 /*! @{ */
61734 
61735 #define NETC_IERB_SAMQR_ARQOS_MASK               (0xF0000U)
61736 #define NETC_IERB_SAMQR_ARQOS_SHIFT              (16U)
61737 #define NETC_IERB_SAMQR_ARQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_ARQOS_SHIFT)) & NETC_IERB_SAMQR_ARQOS_MASK)
61738 
61739 #define NETC_IERB_SAMQR_AWQOS_MASK               (0xF00000U)
61740 #define NETC_IERB_SAMQR_AWQOS_SHIFT              (20U)
61741 #define NETC_IERB_SAMQR_AWQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_AWQOS_SHIFT)) & NETC_IERB_SAMQR_AWQOS_MASK)
61742 
61743 #define NETC_IERB_SAMQR_BMT_MASK                 (0x80000000U)
61744 #define NETC_IERB_SAMQR_BMT_SHIFT                (31U)
61745 #define NETC_IERB_SAMQR_BMT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_BMT_SHIFT)) & NETC_IERB_SAMQR_BMT_MASK)
61746 /*! @} */
61747 
61748 /* The count of NETC_IERB_SAMQR */
61749 #define NETC_IERB_SAMQR_COUNT                    (1U)
61750 
61751 /*! @name SBLPR - Switch 0 boot loader parameter register 0..Switch 0 boot loader parameter register 1 */
61752 /*! @{ */
61753 
61754 #define NETC_IERB_SBLPR_PARAM_VAL_MASK           (0xFFFFFFFFU)
61755 #define NETC_IERB_SBLPR_PARAM_VAL_SHIFT          (0U)
61756 #define NETC_IERB_SBLPR_PARAM_VAL(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_SBLPR_PARAM_VAL_MASK)
61757 /*! @} */
61758 
61759 /* The count of NETC_IERB_SBLPR */
61760 #define NETC_IERB_SBLPR_COUNT                    (1U)
61761 
61762 /* The count of NETC_IERB_SBLPR */
61763 #define NETC_IERB_SBLPR_COUNT2                   (2U)
61764 
61765 /*! @name SSMBAR - Switch 0 shared memory buffer allotment register */
61766 /*! @{ */
61767 
61768 #define NETC_IERB_SSMBAR_ALLOC_MASK              (0xFFFFFFU)
61769 #define NETC_IERB_SSMBAR_ALLOC_SHIFT             (0U)
61770 #define NETC_IERB_SSMBAR_ALLOC(x)                (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSMBAR_ALLOC_SHIFT)) & NETC_IERB_SSMBAR_ALLOC_MASK)
61771 
61772 #define NETC_IERB_SSMBAR_MLOC_MASK               (0xC0000000U)
61773 #define NETC_IERB_SSMBAR_MLOC_SHIFT              (30U)
61774 #define NETC_IERB_SSMBAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSMBAR_MLOC_SHIFT)) & NETC_IERB_SSMBAR_MLOC_MASK)
61775 /*! @} */
61776 
61777 /* The count of NETC_IERB_SSMBAR */
61778 #define NETC_IERB_SSMBAR_COUNT                   (1U)
61779 
61780 /*! @name SHTMAR - Switch 0 hash table memory allotment register */
61781 /*! @{ */
61782 
61783 #define NETC_IERB_SHTMAR_NUM_WORDS_MASK          (0xFFFFU)
61784 #define NETC_IERB_SHTMAR_NUM_WORDS_SHIFT         (0U)
61785 #define NETC_IERB_SHTMAR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SHTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SHTMAR_NUM_WORDS_MASK)
61786 
61787 #define NETC_IERB_SHTMAR_MLOC_MASK               (0xC0000000U)
61788 #define NETC_IERB_SHTMAR_MLOC_SHIFT              (30U)
61789 #define NETC_IERB_SHTMAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SHTMAR_MLOC_SHIFT)) & NETC_IERB_SHTMAR_MLOC_MASK)
61790 /*! @} */
61791 
61792 /* The count of NETC_IERB_SHTMAR */
61793 #define NETC_IERB_SHTMAR_COUNT                   (1U)
61794 
61795 /*! @name SITMAR - Switch 0 index table memory allocation register */
61796 /*! @{ */
61797 
61798 #define NETC_IERB_SITMAR_NUM_WORDS_MASK          (0xFFFFU)
61799 #define NETC_IERB_SITMAR_NUM_WORDS_SHIFT         (0U)
61800 #define NETC_IERB_SITMAR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SITMAR_NUM_WORDS_MASK)
61801 
61802 #define NETC_IERB_SITMAR_MLOC_MASK               (0xC0000000U)
61803 #define NETC_IERB_SITMAR_MLOC_SHIFT              (30U)
61804 #define NETC_IERB_SITMAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SITMAR_MLOC_SHIFT)) & NETC_IERB_SITMAR_MLOC_MASK)
61805 /*! @} */
61806 
61807 /* The count of NETC_IERB_SITMAR */
61808 #define NETC_IERB_SITMAR_COUNT                   (1U)
61809 
61810 /*! @name SIPFTMAR - Switch 0 ingress port filter table memory allocation register */
61811 /*! @{ */
61812 
61813 #define NETC_IERB_SIPFTMAR_ALLOC_MASK            (0xFFFFU)
61814 #define NETC_IERB_SIPFTMAR_ALLOC_SHIFT           (0U)
61815 #define NETC_IERB_SIPFTMAR_ALLOC(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SIPFTMAR_ALLOC_SHIFT)) & NETC_IERB_SIPFTMAR_ALLOC_MASK)
61816 /*! @} */
61817 
61818 /* The count of NETC_IERB_SIPFTMAR */
61819 #define NETC_IERB_SIPFTMAR_COUNT                 (1U)
61820 
61821 /*! @name SRPITMAR - Switch 0 rate policer index table memory allocation register */
61822 /*! @{ */
61823 
61824 #define NETC_IERB_SRPITMAR_NUM_WORDS_MASK        (0xFFFFU)
61825 #define NETC_IERB_SRPITMAR_NUM_WORDS_SHIFT       (0U)
61826 #define NETC_IERB_SRPITMAR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SRPITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SRPITMAR_NUM_WORDS_MASK)
61827 /*! @} */
61828 
61829 /* The count of NETC_IERB_SRPITMAR */
61830 #define NETC_IERB_SRPITMAR_COUNT                 (1U)
61831 
61832 /*! @name SISCITMAR - Switch 0 ingress stream counter index table memory allocation register */
61833 /*! @{ */
61834 
61835 #define NETC_IERB_SISCITMAR_NUM_WORDS_MASK       (0xFFFFU)
61836 #define NETC_IERB_SISCITMAR_NUM_WORDS_SHIFT      (0U)
61837 #define NETC_IERB_SISCITMAR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISCITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISCITMAR_NUM_WORDS_MASK)
61838 /*! @} */
61839 
61840 /* The count of NETC_IERB_SISCITMAR */
61841 #define NETC_IERB_SISCITMAR_COUNT                (1U)
61842 
61843 /*! @name SISITMAR - Switch 0 ingress stream index table memory allocation register */
61844 /*! @{ */
61845 
61846 #define NETC_IERB_SISITMAR_NUM_WORDS_MASK        (0xFFFFU)
61847 #define NETC_IERB_SISITMAR_NUM_WORDS_SHIFT       (0U)
61848 #define NETC_IERB_SISITMAR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISITMAR_NUM_WORDS_MASK)
61849 /*! @} */
61850 
61851 /* The count of NETC_IERB_SISITMAR */
61852 #define NETC_IERB_SISITMAR_COUNT                 (1U)
61853 
61854 /*! @name SISQGITMAR - Switch 0 ingress sequence generation index table memory allocation register */
61855 /*! @{ */
61856 
61857 #define NETC_IERB_SISQGITMAR_NUM_WORDS_MASK      (0x1FFFU)
61858 #define NETC_IERB_SISQGITMAR_NUM_WORDS_SHIFT     (0U)
61859 #define NETC_IERB_SISQGITMAR_NUM_WORDS(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISQGITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISQGITMAR_NUM_WORDS_MASK)
61860 /*! @} */
61861 
61862 /* The count of NETC_IERB_SISQGITMAR */
61863 #define NETC_IERB_SISQGITMAR_COUNT               (1U)
61864 
61865 /*! @name SSGIITMAR - Switch 0 stream gate instance index table memory allocation register */
61866 /*! @{ */
61867 
61868 #define NETC_IERB_SSGIITMAR_NUM_WORDS_MASK       (0xFFFFU)
61869 #define NETC_IERB_SSGIITMAR_NUM_WORDS_SHIFT      (0U)
61870 #define NETC_IERB_SSGIITMAR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSGIITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SSGIITMAR_NUM_WORDS_MASK)
61871 /*! @} */
61872 
61873 /* The count of NETC_IERB_SSGIITMAR */
61874 #define NETC_IERB_SSGIITMAR_COUNT                (1U)
61875 
61876 /*! @name SSGCLITMAR - Switch 0 stream gate control list index table memory allocation register */
61877 /*! @{ */
61878 
61879 #define NETC_IERB_SSGCLITMAR_NUM_WORDS_MASK      (0xFFFFU)
61880 #define NETC_IERB_SSGCLITMAR_NUM_WORDS_SHIFT     (0U)
61881 #define NETC_IERB_SSGCLITMAR_NUM_WORDS(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSGCLITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SSGCLITMAR_NUM_WORDS_MASK)
61882 /*! @} */
61883 
61884 /* The count of NETC_IERB_SSGCLITMAR */
61885 #define NETC_IERB_SSGCLITMAR_COUNT               (1U)
61886 
61887 /*! @name SFMITMAR - Switch 0 frame modification index table memory allocation register */
61888 /*! @{ */
61889 
61890 #define NETC_IERB_SFMITMAR_NUM_WORDS_MASK        (0x1FFFU)
61891 #define NETC_IERB_SFMITMAR_NUM_WORDS_SHIFT       (0U)
61892 #define NETC_IERB_SFMITMAR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SFMITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SFMITMAR_NUM_WORDS_MASK)
61893 /*! @} */
61894 
61895 /* The count of NETC_IERB_SFMITMAR */
61896 #define NETC_IERB_SFMITMAR_COUNT                 (1U)
61897 
61898 /*! @name SFMDITMAR - Switch 0 frame modification data index table memory allocation register */
61899 /*! @{ */
61900 
61901 #define NETC_IERB_SFMDITMAR_NUM_WORDS_MASK       (0xFFFFU)
61902 #define NETC_IERB_SFMDITMAR_NUM_WORDS_SHIFT      (0U)
61903 #define NETC_IERB_SFMDITMAR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SFMDITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SFMDITMAR_NUM_WORDS_MASK)
61904 /*! @} */
61905 
61906 /* The count of NETC_IERB_SFMDITMAR */
61907 #define NETC_IERB_SFMDITMAR_COUNT                (1U)
61908 
61909 /*! @name STGSTAR - Switch 0 time gate scheduling table allocation register */
61910 /*! @{ */
61911 
61912 #define NETC_IERB_STGSTAR_NUM_WORDS_MASK         (0xFFFU)
61913 #define NETC_IERB_STGSTAR_NUM_WORDS_SHIFT        (0U)
61914 #define NETC_IERB_STGSTAR_NUM_WORDS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_STGSTAR_NUM_WORDS_SHIFT)) & NETC_IERB_STGSTAR_NUM_WORDS_MASK)
61915 /*! @} */
61916 
61917 /* The count of NETC_IERB_STGSTAR */
61918 #define NETC_IERB_STGSTAR_COUNT                  (1U)
61919 
61920 /*! @name STGSLR - Switch 0 time gate scheduling lookahead register */
61921 /*! @{ */
61922 
61923 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD_MASK      (0xFFFFFU)
61924 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD_SHIFT     (0U)
61925 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_STGSLR_MIN_LOOKAHEAD_SHIFT)) & NETC_IERB_STGSLR_MIN_LOOKAHEAD_MASK)
61926 /*! @} */
61927 
61928 /* The count of NETC_IERB_STGSLR */
61929 #define NETC_IERB_STGSLR_COUNT                   (1U)
61930 
61931 /*! @name SMPCR - Switch 0 management port configuration register */
61932 /*! @{ */
61933 
61934 #define NETC_IERB_SMPCR_PORT_MASK                (0x1FU)
61935 #define NETC_IERB_SMPCR_PORT_SHIFT               (0U)
61936 #define NETC_IERB_SMPCR_PORT(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMPCR_PORT_SHIFT)) & NETC_IERB_SMPCR_PORT_MASK)
61937 /*! @} */
61938 
61939 /* The count of NETC_IERB_SMPCR */
61940 #define NETC_IERB_SMPCR_COUNT                    (1U)
61941 
61942 /*! @name SVFHTDECR0 - Switch 0 VLAN Filter (hash) table default entry configuration registers 0 */
61943 /*! @{ */
61944 
61945 #define NETC_IERB_SVFHTDECR0_PORT0_MASK          (0x1U)
61946 #define NETC_IERB_SVFHTDECR0_PORT0_SHIFT         (0U)
61947 /*! PORT0 - Port n.
61948  *  0b0..Port n is not a member of this VLAN.
61949  *  0b1..Port n is a member of this VLAN.
61950  */
61951 #define NETC_IERB_SVFHTDECR0_PORT0(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT0_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT0_MASK)
61952 
61953 #define NETC_IERB_SVFHTDECR0_PORT1_MASK          (0x2U)
61954 #define NETC_IERB_SVFHTDECR0_PORT1_SHIFT         (1U)
61955 /*! PORT1 - Port n.
61956  *  0b0..Port n is not a member of this VLAN.
61957  *  0b1..Port n is a member of this VLAN.
61958  */
61959 #define NETC_IERB_SVFHTDECR0_PORT1(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT1_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT1_MASK)
61960 
61961 #define NETC_IERB_SVFHTDECR0_PORT2_MASK          (0x4U)
61962 #define NETC_IERB_SVFHTDECR0_PORT2_SHIFT         (2U)
61963 /*! PORT2 - Port n.
61964  *  0b0..Port n is not a member of this VLAN.
61965  *  0b1..Port n is a member of this VLAN.
61966  */
61967 #define NETC_IERB_SVFHTDECR0_PORT2(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT2_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT2_MASK)
61968 
61969 #define NETC_IERB_SVFHTDECR0_PORT3_MASK          (0x8U)
61970 #define NETC_IERB_SVFHTDECR0_PORT3_SHIFT         (3U)
61971 /*! PORT3 - Port n.
61972  *  0b0..Port n is not a member of this VLAN.
61973  *  0b1..Port n is a member of this VLAN.
61974  */
61975 #define NETC_IERB_SVFHTDECR0_PORT3(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT3_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT3_MASK)
61976 
61977 #define NETC_IERB_SVFHTDECR0_PORT4_MASK          (0x10U)
61978 #define NETC_IERB_SVFHTDECR0_PORT4_SHIFT         (4U)
61979 /*! PORT4 - Port n.
61980  *  0b0..Port n is not a member of this VLAN.
61981  *  0b1..Port n is a member of this VLAN.
61982  */
61983 #define NETC_IERB_SVFHTDECR0_PORT4(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT4_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT4_MASK)
61984 
61985 #define NETC_IERB_SVFHTDECR0_STG_ID_MASK         (0xF000000U)
61986 #define NETC_IERB_SVFHTDECR0_STG_ID_SHIFT        (24U)
61987 #define NETC_IERB_SVFHTDECR0_STG_ID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_STG_ID_SHIFT)) & NETC_IERB_SVFHTDECR0_STG_ID_MASK)
61988 
61989 #define NETC_IERB_SVFHTDECR0_IPMFE_MASK          (0x20000000U)
61990 #define NETC_IERB_SVFHTDECR0_IPMFE_SHIFT         (29U)
61991 /*! IPMFE
61992  *  0b0..No IP multicast filtering is performed.
61993  *  0b1..If the frame is identified as a multicast IP packet, then IP multicast filtering is performed. If the
61994  *       frame is not identified as an IP multicast packet, the IP multicast filtering is not performed.
61995  */
61996 #define NETC_IERB_SVFHTDECR0_IPMFE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_IPMFE_SHIFT)) & NETC_IERB_SVFHTDECR0_IPMFE_MASK)
61997 
61998 #define NETC_IERB_SVFHTDECR0_IPMFLE_MASK         (0x40000000U)
61999 #define NETC_IERB_SVFHTDECR0_IPMFLE_SHIFT        (30U)
62000 /*! IPMFLE
62001  *  0b0..IP Multicast Flooding disabled, the frame is discarded.
62002  *  0b1..IP Multicast Flooding enabled, the frame is flooded.
62003  */
62004 #define NETC_IERB_SVFHTDECR0_IPMFLE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_IPMFLE_SHIFT)) & NETC_IERB_SVFHTDECR0_IPMFLE_MASK)
62005 /*! @} */
62006 
62007 /* The count of NETC_IERB_SVFHTDECR0 */
62008 #define NETC_IERB_SVFHTDECR0_COUNT               (1U)
62009 
62010 /*! @name SVFHTDECR1 - Switch 0 VLAN filter hash table default entry configuration registers 1 */
62011 /*! @{ */
62012 
62013 #define NETC_IERB_SVFHTDECR1_FID_MASK            (0xFFFU)
62014 #define NETC_IERB_SVFHTDECR1_FID_SHIFT           (0U)
62015 #define NETC_IERB_SVFHTDECR1_FID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_FID_SHIFT)) & NETC_IERB_SVFHTDECR1_FID_MASK)
62016 
62017 #define NETC_IERB_SVFHTDECR1_VL_MODE_MASK        (0x1000U)
62018 #define NETC_IERB_SVFHTDECR1_VL_MODE_SHIFT       (12U)
62019 #define NETC_IERB_SVFHTDECR1_VL_MODE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_VL_MODE_SHIFT)) & NETC_IERB_SVFHTDECR1_VL_MODE_MASK)
62020 
62021 #define NETC_IERB_SVFHTDECR1_BASE_ETEID_MASK     (0xFFFF0000U)
62022 #define NETC_IERB_SVFHTDECR1_BASE_ETEID_SHIFT    (16U)
62023 #define NETC_IERB_SVFHTDECR1_BASE_ETEID(x)       (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_BASE_ETEID_SHIFT)) & NETC_IERB_SVFHTDECR1_BASE_ETEID_MASK)
62024 /*! @} */
62025 
62026 /* The count of NETC_IERB_SVFHTDECR1 */
62027 #define NETC_IERB_SVFHTDECR1_COUNT               (1U)
62028 
62029 /*! @name SVFHTDECR2 - Switch 0 VLAN filter hash table default entry configuration registers 2 */
62030 /*! @{ */
62031 
62032 #define NETC_IERB_SVFHTDECR2_ES_PORT0_MASK       (0x1U)
62033 #define NETC_IERB_SVFHTDECR2_ES_PORT0_SHIFT      (0U)
62034 #define NETC_IERB_SVFHTDECR2_ES_PORT0(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT0_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT0_MASK)
62035 
62036 #define NETC_IERB_SVFHTDECR2_ES_PORT1_MASK       (0x2U)
62037 #define NETC_IERB_SVFHTDECR2_ES_PORT1_SHIFT      (1U)
62038 #define NETC_IERB_SVFHTDECR2_ES_PORT1(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT1_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT1_MASK)
62039 
62040 #define NETC_IERB_SVFHTDECR2_ES_PORT2_MASK       (0x4U)
62041 #define NETC_IERB_SVFHTDECR2_ES_PORT2_SHIFT      (2U)
62042 #define NETC_IERB_SVFHTDECR2_ES_PORT2(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT2_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT2_MASK)
62043 
62044 #define NETC_IERB_SVFHTDECR2_ES_PORT3_MASK       (0x8U)
62045 #define NETC_IERB_SVFHTDECR2_ES_PORT3_SHIFT      (3U)
62046 #define NETC_IERB_SVFHTDECR2_ES_PORT3(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT3_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT3_MASK)
62047 
62048 #define NETC_IERB_SVFHTDECR2_ES_PORT4_MASK       (0x10U)
62049 #define NETC_IERB_SVFHTDECR2_ES_PORT4_SHIFT      (4U)
62050 #define NETC_IERB_SVFHTDECR2_ES_PORT4(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT4_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT4_MASK)
62051 
62052 #define NETC_IERB_SVFHTDECR2_MLO_MASK            (0x7000000U)
62053 #define NETC_IERB_SVFHTDECR2_MLO_SHIFT           (24U)
62054 #define NETC_IERB_SVFHTDECR2_MLO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_MLO_SHIFT)) & NETC_IERB_SVFHTDECR2_MLO_MASK)
62055 
62056 #define NETC_IERB_SVFHTDECR2_MFO_MASK            (0x18000000U)
62057 #define NETC_IERB_SVFHTDECR2_MFO_SHIFT           (27U)
62058 #define NETC_IERB_SVFHTDECR2_MFO(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_MFO_SHIFT)) & NETC_IERB_SVFHTDECR2_MFO_MASK)
62059 /*! @} */
62060 
62061 /* The count of NETC_IERB_SVFHTDECR2 */
62062 #define NETC_IERB_SVFHTDECR2_COUNT               (1U)
62063 
62064 /*! @name EBCR0 - ENETC 0 binding configuration register 0..ENETC 1 binding configuration register 0 */
62065 /*! @{ */
62066 
62067 #define NETC_IERB_EBCR0_RC_INST_MASK             (0xFU)
62068 #define NETC_IERB_EBCR0_RC_INST_SHIFT            (0U)
62069 #define NETC_IERB_EBCR0_RC_INST(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_RC_INST_SHIFT)) & NETC_IERB_EBCR0_RC_INST_MASK)
62070 
62071 #define NETC_IERB_EBCR0_FN_MASK                  (0xF00U)
62072 #define NETC_IERB_EBCR0_FN_SHIFT                 (8U)
62073 #define NETC_IERB_EBCR0_FN(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_FN_SHIFT)) & NETC_IERB_EBCR0_FN_MASK)
62074 
62075 #define NETC_IERB_EBCR0_VALID_MASK               (0x80000000U)
62076 #define NETC_IERB_EBCR0_VALID_SHIFT              (31U)
62077 #define NETC_IERB_EBCR0_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_VALID_SHIFT)) & NETC_IERB_EBCR0_VALID_MASK)
62078 /*! @} */
62079 
62080 /* The count of NETC_IERB_EBCR0 */
62081 #define NETC_IERB_EBCR0_COUNT                    (2U)
62082 
62083 /*! @name EBCR1 - ENETC 0 binding configuration register 1..ENETC 1 binding configuration register 1 */
62084 /*! @{ */
62085 
62086 #define NETC_IERB_EBCR1_NUM_RX_BDR_MASK          (0x3FFU)
62087 #define NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT         (0U)
62088 #define NETC_IERB_EBCR1_NUM_RX_BDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_RX_BDR_MASK)
62089 
62090 #define NETC_IERB_EBCR1_NUM_TX_BDR_MASK          (0x3FF0000U)
62091 #define NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT         (16U)
62092 #define NETC_IERB_EBCR1_NUM_TX_BDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_TX_BDR_MASK)
62093 /*! @} */
62094 
62095 /* The count of NETC_IERB_EBCR1 */
62096 #define NETC_IERB_EBCR1_COUNT                    (2U)
62097 
62098 /*! @name EBCR2 - ENETC 0 binding configuration register 2..ENETC 1 binding configuration register 2 */
62099 /*! @{ */
62100 
62101 #define NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK        (0xFFFU)
62102 #define NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT       (0U)
62103 #define NETC_IERB_EBCR2_NUM_MAC_AFTE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK)
62104 
62105 #define NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK        (0xFFF0000U)
62106 #define NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT       (16U)
62107 #define NETC_IERB_EBCR2_NUM_VLAN_FTE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK)
62108 /*! @} */
62109 
62110 /* The count of NETC_IERB_EBCR2 */
62111 #define NETC_IERB_EBCR2_COUNT                    (2U)
62112 
62113 /*! @name EVBCR - ENETC 0 VSI binding configuration register..ENETC 1 VSI binding configuration register */
62114 /*! @{ */
62115 
62116 #define NETC_IERB_EVBCR_NUM_VSI_MASK             (0xFU)
62117 #define NETC_IERB_EVBCR_NUM_VSI_SHIFT            (0U)
62118 #define NETC_IERB_EVBCR_NUM_VSI(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EVBCR_NUM_VSI_SHIFT)) & NETC_IERB_EVBCR_NUM_VSI_MASK)
62119 /*! @} */
62120 
62121 /* The count of NETC_IERB_EVBCR */
62122 #define NETC_IERB_EVBCR_COUNT                    (2U)
62123 
62124 /*! @name EMCR - ENETC 0 MSI-X configuration register..ENETC 1 MSI-X configuration register */
62125 /*! @{ */
62126 
62127 #define NETC_IERB_EMCR_NUM_MSIX_MASK             (0x7FFU)
62128 #define NETC_IERB_EMCR_NUM_MSIX_SHIFT            (0U)
62129 #define NETC_IERB_EMCR_NUM_MSIX(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMCR_NUM_MSIX_MASK)
62130 /*! @} */
62131 
62132 /* The count of NETC_IERB_EMCR */
62133 #define NETC_IERB_EMCR_COUNT                     (2U)
62134 
62135 /*! @name E_CFH_DIDVID - ENETC 0 config header device ID and vendor ID register..ENETC 1 config header device ID and vendor ID register */
62136 /*! @{ */
62137 
62138 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK    (0xFFFFU)
62139 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT   (0U)
62140 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK)
62141 
62142 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK    (0xFFFF0000U)
62143 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT   (16U)
62144 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID(x)      (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK)
62145 /*! @} */
62146 
62147 /* The count of NETC_IERB_E_CFH_DIDVID */
62148 #define NETC_IERB_E_CFH_DIDVID_COUNT             (2U)
62149 
62150 /*! @name E_CFH_SIDSVID - ENETC 0 config header subsystem ID and subsystem vendor ID register..ENETC 1 config header subsystem ID and subsystem vendor ID register */
62151 /*! @{ */
62152 
62153 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU)
62154 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U)
62155 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK)
62156 
62157 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U)
62158 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U)
62159 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK)
62160 /*! @} */
62161 
62162 /* The count of NETC_IERB_E_CFH_SIDSVID */
62163 #define NETC_IERB_E_CFH_SIDSVID_COUNT            (2U)
62164 
62165 /*! @name E_CFC_VFDID - ENETC 0 config capability VF device ID register..ENETC 1 config capability VF device ID register */
62166 /*! @{ */
62167 
62168 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK  (0xFFFF0000U)
62169 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT (16U)
62170 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID(x)    (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK)
62171 /*! @} */
62172 
62173 /* The count of NETC_IERB_E_CFC_VFDID */
62174 #define NETC_IERB_E_CFC_VFDID_COUNT              (2U)
62175 
62176 /*! @name EBCAR - ENETC 0 buffer cache attribute register 0..ENETC 1 buffer cache attribute register 0 */
62177 /*! @{ */
62178 
62179 #define NETC_IERB_EBCAR_BD_WRCACHE_MASK          (0xFU)
62180 #define NETC_IERB_EBCAR_BD_WRCACHE_SHIFT         (0U)
62181 #define NETC_IERB_EBCAR_BD_WRCACHE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_WRCACHE_MASK)
62182 
62183 #define NETC_IERB_EBCAR_BD_WRDOMAIN_MASK         (0x30U)
62184 #define NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT        (4U)
62185 #define NETC_IERB_EBCAR_BD_WRDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_WRDOMAIN_MASK)
62186 
62187 #define NETC_IERB_EBCAR_BD_WRSNP_MASK            (0x40U)
62188 #define NETC_IERB_EBCAR_BD_WRSNP_SHIFT           (6U)
62189 #define NETC_IERB_EBCAR_BD_WRSNP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRSNP_SHIFT)) & NETC_IERB_EBCAR_BD_WRSNP_MASK)
62190 
62191 #define NETC_IERB_EBCAR_WRCACHE_MASK             (0xF00U)
62192 #define NETC_IERB_EBCAR_WRCACHE_SHIFT            (8U)
62193 #define NETC_IERB_EBCAR_WRCACHE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_WRCACHE_MASK)
62194 
62195 #define NETC_IERB_EBCAR_WRDOMAIN_MASK            (0x3000U)
62196 #define NETC_IERB_EBCAR_WRDOMAIN_SHIFT           (12U)
62197 #define NETC_IERB_EBCAR_WRDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_WRDOMAIN_MASK)
62198 
62199 #define NETC_IERB_EBCAR_WRSNP_MASK               (0x4000U)
62200 #define NETC_IERB_EBCAR_WRSNP_SHIFT              (14U)
62201 #define NETC_IERB_EBCAR_WRSNP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRSNP_SHIFT)) & NETC_IERB_EBCAR_WRSNP_MASK)
62202 
62203 #define NETC_IERB_EBCAR_BD_RDCACHE_MASK          (0xF0000U)
62204 #define NETC_IERB_EBCAR_BD_RDCACHE_SHIFT         (16U)
62205 #define NETC_IERB_EBCAR_BD_RDCACHE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_RDCACHE_MASK)
62206 
62207 #define NETC_IERB_EBCAR_BD_RDDOMAIN_MASK         (0x300000U)
62208 #define NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT        (20U)
62209 #define NETC_IERB_EBCAR_BD_RDDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_RDDOMAIN_MASK)
62210 
62211 #define NETC_IERB_EBCAR_BD_RDSNP_MASK            (0x400000U)
62212 #define NETC_IERB_EBCAR_BD_RDSNP_SHIFT           (22U)
62213 #define NETC_IERB_EBCAR_BD_RDSNP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDSNP_SHIFT)) & NETC_IERB_EBCAR_BD_RDSNP_MASK)
62214 
62215 #define NETC_IERB_EBCAR_RDCACHE_MASK             (0xF000000U)
62216 #define NETC_IERB_EBCAR_RDCACHE_SHIFT            (24U)
62217 #define NETC_IERB_EBCAR_RDCACHE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_RDCACHE_MASK)
62218 
62219 #define NETC_IERB_EBCAR_RDDOMAIN_MASK            (0x30000000U)
62220 #define NETC_IERB_EBCAR_RDDOMAIN_SHIFT           (28U)
62221 #define NETC_IERB_EBCAR_RDDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_RDDOMAIN_MASK)
62222 
62223 #define NETC_IERB_EBCAR_RDSNP_MASK               (0x40000000U)
62224 #define NETC_IERB_EBCAR_RDSNP_SHIFT              (30U)
62225 #define NETC_IERB_EBCAR_RDSNP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDSNP_SHIFT)) & NETC_IERB_EBCAR_RDSNP_MASK)
62226 /*! @} */
62227 
62228 /* The count of NETC_IERB_EBCAR */
62229 #define NETC_IERB_EBCAR_COUNT                    (2U)
62230 
62231 /*! @name EMCAR - ENETC 0 message cache attribute register..ENETC 1 message cache attribute register */
62232 /*! @{ */
62233 
62234 #define NETC_IERB_EMCAR_MSG_WRCACHE_MASK         (0xFU)
62235 #define NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT        (0U)
62236 #define NETC_IERB_EMCAR_MSG_WRCACHE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_WRCACHE_MASK)
62237 
62238 #define NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK        (0x30U)
62239 #define NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT       (4U)
62240 #define NETC_IERB_EMCAR_MSG_WRDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK)
62241 
62242 #define NETC_IERB_EMCAR_MSG_WRSNP_MASK           (0x40U)
62243 #define NETC_IERB_EMCAR_MSG_WRSNP_SHIFT          (6U)
62244 #define NETC_IERB_EMCAR_MSG_WRSNP(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_WRSNP_MASK)
62245 
62246 #define NETC_IERB_EMCAR_MSG_RDCACHE_MASK         (0xF0000U)
62247 #define NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT        (16U)
62248 #define NETC_IERB_EMCAR_MSG_RDCACHE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_RDCACHE_MASK)
62249 
62250 #define NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK        (0x300000U)
62251 #define NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT       (20U)
62252 #define NETC_IERB_EMCAR_MSG_RDDOMAIN(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK)
62253 
62254 #define NETC_IERB_EMCAR_MSG_RDSNP_MASK           (0x400000U)
62255 #define NETC_IERB_EMCAR_MSG_RDSNP_SHIFT          (22U)
62256 #define NETC_IERB_EMCAR_MSG_RDSNP(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_RDSNP_MASK)
62257 /*! @} */
62258 
62259 /* The count of NETC_IERB_EMCAR */
62260 #define NETC_IERB_EMCAR_COUNT                    (2U)
62261 
62262 /*! @name ECAR - ENETC 0 command cache attribute register..ENETC 1 command cache attribute register */
62263 /*! @{ */
62264 
62265 #define NETC_IERB_ECAR_CBD_WRCACHE_MASK          (0xFU)
62266 #define NETC_IERB_ECAR_CBD_WRCACHE_SHIFT         (0U)
62267 #define NETC_IERB_ECAR_CBD_WRCACHE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_WRCACHE_MASK)
62268 
62269 #define NETC_IERB_ECAR_CBD_WRDOMAIN_MASK         (0x30U)
62270 #define NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT        (4U)
62271 #define NETC_IERB_ECAR_CBD_WRDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_WRDOMAIN_MASK)
62272 
62273 #define NETC_IERB_ECAR_CBD_WRSNP_MASK            (0x40U)
62274 #define NETC_IERB_ECAR_CBD_WRSNP_SHIFT           (6U)
62275 #define NETC_IERB_ECAR_CBD_WRSNP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRSNP_SHIFT)) & NETC_IERB_ECAR_CBD_WRSNP_MASK)
62276 
62277 #define NETC_IERB_ECAR_CWRCACHE_MASK             (0xF00U)
62278 #define NETC_IERB_ECAR_CWRCACHE_SHIFT            (8U)
62279 #define NETC_IERB_ECAR_CWRCACHE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRCACHE_SHIFT)) & NETC_IERB_ECAR_CWRCACHE_MASK)
62280 
62281 #define NETC_IERB_ECAR_CWRDOMAIN_MASK            (0x3000U)
62282 #define NETC_IERB_ECAR_CWRDOMAIN_SHIFT           (12U)
62283 #define NETC_IERB_ECAR_CWRDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CWRDOMAIN_MASK)
62284 
62285 #define NETC_IERB_ECAR_CWRSNP_MASK               (0x4000U)
62286 #define NETC_IERB_ECAR_CWRSNP_SHIFT              (14U)
62287 #define NETC_IERB_ECAR_CWRSNP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRSNP_SHIFT)) & NETC_IERB_ECAR_CWRSNP_MASK)
62288 
62289 #define NETC_IERB_ECAR_CBD_RDCACHE_MASK          (0xF0000U)
62290 #define NETC_IERB_ECAR_CBD_RDCACHE_SHIFT         (16U)
62291 #define NETC_IERB_ECAR_CBD_RDCACHE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_RDCACHE_MASK)
62292 
62293 #define NETC_IERB_ECAR_CBD_RDDOMAIN_MASK         (0x300000U)
62294 #define NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT        (20U)
62295 #define NETC_IERB_ECAR_CBD_RDDOMAIN(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_RDDOMAIN_MASK)
62296 
62297 #define NETC_IERB_ECAR_CBD_RDSNP_MASK            (0x400000U)
62298 #define NETC_IERB_ECAR_CBD_RDSNP_SHIFT           (22U)
62299 #define NETC_IERB_ECAR_CBD_RDSNP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDSNP_SHIFT)) & NETC_IERB_ECAR_CBD_RDSNP_MASK)
62300 
62301 #define NETC_IERB_ECAR_CRDCACHE_MASK             (0xF000000U)
62302 #define NETC_IERB_ECAR_CRDCACHE_SHIFT            (24U)
62303 #define NETC_IERB_ECAR_CRDCACHE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDCACHE_SHIFT)) & NETC_IERB_ECAR_CRDCACHE_MASK)
62304 
62305 #define NETC_IERB_ECAR_CRDDOMAIN_MASK            (0x30000000U)
62306 #define NETC_IERB_ECAR_CRDDOMAIN_SHIFT           (28U)
62307 #define NETC_IERB_ECAR_CRDDOMAIN(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CRDDOMAIN_MASK)
62308 
62309 #define NETC_IERB_ECAR_CRDSNP_MASK               (0x40000000U)
62310 #define NETC_IERB_ECAR_CRDSNP_SHIFT              (30U)
62311 #define NETC_IERB_ECAR_CRDSNP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDSNP_SHIFT)) & NETC_IERB_ECAR_CRDSNP_MASK)
62312 /*! @} */
62313 
62314 /* The count of NETC_IERB_ECAR */
62315 #define NETC_IERB_ECAR_COUNT                     (2U)
62316 
62317 /*! @name EAMQR - ENETC 0 access management qualifier register..ENETC 1 access management qualifier register */
62318 /*! @{ */
62319 
62320 #define NETC_IERB_EAMQR_ARQOS_MASK               (0xF0000U)
62321 #define NETC_IERB_EAMQR_ARQOS_SHIFT              (16U)
62322 #define NETC_IERB_EAMQR_ARQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_ARQOS_SHIFT)) & NETC_IERB_EAMQR_ARQOS_MASK)
62323 
62324 #define NETC_IERB_EAMQR_AWQOS_MASK               (0xF00000U)
62325 #define NETC_IERB_EAMQR_AWQOS_SHIFT              (20U)
62326 #define NETC_IERB_EAMQR_AWQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_AWQOS_SHIFT)) & NETC_IERB_EAMQR_AWQOS_MASK)
62327 
62328 #define NETC_IERB_EAMQR_BMT_MASK                 (0x80000000U)
62329 #define NETC_IERB_EAMQR_BMT_SHIFT                (31U)
62330 #define NETC_IERB_EAMQR_BMT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_BMT_SHIFT)) & NETC_IERB_EAMQR_BMT_MASK)
62331 /*! @} */
62332 
62333 /* The count of NETC_IERB_EAMQR */
62334 #define NETC_IERB_EAMQR_COUNT                    (2U)
62335 
62336 /*! @name EBLPR - ENETC 0 boot loader parameter register 0..ENETC 1 boot loader parameter register 1 */
62337 /*! @{ */
62338 
62339 #define NETC_IERB_EBLPR_PARAM_VAL_MASK           (0xFFFFFFFFU)
62340 #define NETC_IERB_EBLPR_PARAM_VAL_SHIFT          (0U)
62341 #define NETC_IERB_EBLPR_PARAM_VAL(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EBLPR_PARAM_VAL_MASK)
62342 /*! @} */
62343 
62344 /* The count of NETC_IERB_EBLPR */
62345 #define NETC_IERB_EBLPR_COUNT                    (2U)
62346 
62347 /* The count of NETC_IERB_EBLPR */
62348 #define NETC_IERB_EBLPR_COUNT2                   (2U)
62349 
62350 /*! @name ERXMBER - ENETC 0 receive memory buffer entitlement register..ENETC 1 receive memory buffer entitlement register */
62351 /*! @{ */
62352 
62353 #define NETC_IERB_ERXMBER_AMOUNT_MASK            (0xFFFFFFU)
62354 #define NETC_IERB_ERXMBER_AMOUNT_SHIFT           (0U)
62355 #define NETC_IERB_ERXMBER_AMOUNT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBER_AMOUNT_SHIFT)) & NETC_IERB_ERXMBER_AMOUNT_MASK)
62356 /*! @} */
62357 
62358 /* The count of NETC_IERB_ERXMBER */
62359 #define NETC_IERB_ERXMBER_COUNT                  (2U)
62360 
62361 /*! @name ERXMBLR - ENETC 0 receive memory buffer limit register..ENETC 1 receive memory buffer limit register */
62362 /*! @{ */
62363 
62364 #define NETC_IERB_ERXMBLR_LIMIT_MASK             (0xFFFFFFU)
62365 #define NETC_IERB_ERXMBLR_LIMIT_SHIFT            (0U)
62366 #define NETC_IERB_ERXMBLR_LIMIT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBLR_LIMIT_SHIFT)) & NETC_IERB_ERXMBLR_LIMIT_MASK)
62367 /*! @} */
62368 
62369 /* The count of NETC_IERB_ERXMBLR */
62370 #define NETC_IERB_ERXMBLR_COUNT                  (2U)
62371 
62372 /*! @name ETXHPTBCR - ENETC 0 transmit high priority tier byte credit register..ENETC 1 transmit high priority tier byte credit register */
62373 /*! @{ */
62374 
62375 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK     (0xFFFFU)
62376 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT    (0U)
62377 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT(x)       (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK)
62378 /*! @} */
62379 
62380 /* The count of NETC_IERB_ETXHPTBCR */
62381 #define NETC_IERB_ETXHPTBCR_COUNT                (2U)
62382 
62383 /*! @name ETXLPTBCR - ENETC 0 transmit low priority tier byte credit register..ENETC 1 transmit low priority tier byte credit register */
62384 /*! @{ */
62385 
62386 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK     (0xFFFFU)
62387 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT    (0U)
62388 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT(x)       (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK)
62389 /*! @} */
62390 
62391 /* The count of NETC_IERB_ETXLPTBCR */
62392 #define NETC_IERB_ETXLPTBCR_COUNT                (2U)
62393 
62394 /*! @name EHTMAR - ENETC 0 hash table memory allotment register..ENETC 1 hash table memory allotment register */
62395 /*! @{ */
62396 
62397 #define NETC_IERB_EHTMAR_NUM_WORDS_MASK          (0xFFFFU)
62398 #define NETC_IERB_EHTMAR_NUM_WORDS_SHIFT         (0U)
62399 #define NETC_IERB_EHTMAR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EHTMAR_NUM_WORDS_MASK)
62400 
62401 #define NETC_IERB_EHTMAR_MLOC_MASK               (0xC0000000U)
62402 #define NETC_IERB_EHTMAR_MLOC_SHIFT              (30U)
62403 #define NETC_IERB_EHTMAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_MLOC_SHIFT)) & NETC_IERB_EHTMAR_MLOC_MASK)
62404 /*! @} */
62405 
62406 /* The count of NETC_IERB_EHTMAR */
62407 #define NETC_IERB_EHTMAR_COUNT                   (2U)
62408 
62409 /*! @name EITMAR - ENETC 0 index table memory allocation register..ENETC 1 index table memory allocation register */
62410 /*! @{ */
62411 
62412 #define NETC_IERB_EITMAR_NUM_WORDS_MASK          (0xFFFFU)
62413 #define NETC_IERB_EITMAR_NUM_WORDS_SHIFT         (0U)
62414 #define NETC_IERB_EITMAR_NUM_WORDS(x)            (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EITMAR_NUM_WORDS_MASK)
62415 
62416 #define NETC_IERB_EITMAR_MLOC_MASK               (0xC0000000U)
62417 #define NETC_IERB_EITMAR_MLOC_SHIFT              (30U)
62418 #define NETC_IERB_EITMAR_MLOC(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_MLOC_SHIFT)) & NETC_IERB_EITMAR_MLOC_MASK)
62419 /*! @} */
62420 
62421 /* The count of NETC_IERB_EITMAR */
62422 #define NETC_IERB_EITMAR_COUNT                   (2U)
62423 
62424 /*! @name EIPFTMAR - ENETC 0 ingress port filter table memory allocation register..ENETC 1 ingress port filter table memory allocation register */
62425 /*! @{ */
62426 
62427 #define NETC_IERB_EIPFTMAR_ALLOC_MASK            (0xFFFFU)
62428 #define NETC_IERB_EIPFTMAR_ALLOC_SHIFT           (0U)
62429 #define NETC_IERB_EIPFTMAR_ALLOC(x)              (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EIPFTMAR_ALLOC_SHIFT)) & NETC_IERB_EIPFTMAR_ALLOC_MASK)
62430 /*! @} */
62431 
62432 /* The count of NETC_IERB_EIPFTMAR */
62433 #define NETC_IERB_EIPFTMAR_COUNT                 (2U)
62434 
62435 /*! @name ERPITMAR - ENETC 0 rate policer index table memory allocation register..ENETC 1 rate policer index table memory allocation register */
62436 /*! @{ */
62437 
62438 #define NETC_IERB_ERPITMAR_NUM_WORDS_MASK        (0xFFFFU)
62439 #define NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT       (0U)
62440 #define NETC_IERB_ERPITMAR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ERPITMAR_NUM_WORDS_MASK)
62441 /*! @} */
62442 
62443 /* The count of NETC_IERB_ERPITMAR */
62444 #define NETC_IERB_ERPITMAR_COUNT                 (2U)
62445 
62446 /*! @name EISCITMAR - ENETC 0 ingress stream counter index table memory allocation register..ENETC 1 ingress stream counter index table memory allocation register */
62447 /*! @{ */
62448 
62449 #define NETC_IERB_EISCITMAR_NUM_WORDS_MASK       (0xFFFFU)
62450 #define NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT      (0U)
62451 #define NETC_IERB_EISCITMAR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISCITMAR_NUM_WORDS_MASK)
62452 /*! @} */
62453 
62454 /* The count of NETC_IERB_EISCITMAR */
62455 #define NETC_IERB_EISCITMAR_COUNT                (2U)
62456 
62457 /*! @name EISITMAR - ENETC 0 ingress stream index table memory allocation register..ENETC 1 ingress stream index table memory allocation register */
62458 /*! @{ */
62459 
62460 #define NETC_IERB_EISITMAR_NUM_WORDS_MASK        (0xFFFFU)
62461 #define NETC_IERB_EISITMAR_NUM_WORDS_SHIFT       (0U)
62462 #define NETC_IERB_EISITMAR_NUM_WORDS(x)          (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISITMAR_NUM_WORDS_MASK)
62463 /*! @} */
62464 
62465 /* The count of NETC_IERB_EISITMAR */
62466 #define NETC_IERB_EISITMAR_COUNT                 (2U)
62467 
62468 /*! @name ESGIITMAR - ENETC 0 stream gate instance index table memory allocation register..ENETC 1 stream gate instance index table memory allocation register */
62469 /*! @{ */
62470 
62471 #define NETC_IERB_ESGIITMAR_NUM_WORDS_MASK       (0xFFFFU)
62472 #define NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT      (0U)
62473 #define NETC_IERB_ESGIITMAR_NUM_WORDS(x)         (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGIITMAR_NUM_WORDS_MASK)
62474 /*! @} */
62475 
62476 /* The count of NETC_IERB_ESGIITMAR */
62477 #define NETC_IERB_ESGIITMAR_COUNT                (2U)
62478 
62479 /*! @name ESGCLITMAR - ENETC 0 stream gate control list index table memory allocation register..ENETC 1 stream gate control list index table memory allocation register */
62480 /*! @{ */
62481 
62482 #define NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK      (0xFFFFU)
62483 #define NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT     (0U)
62484 #define NETC_IERB_ESGCLITMAR_NUM_WORDS(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK)
62485 /*! @} */
62486 
62487 /* The count of NETC_IERB_ESGCLITMAR */
62488 #define NETC_IERB_ESGCLITMAR_COUNT               (2U)
62489 
62490 /*! @name ETGSTAR - ENETC 0 time gate scheduling table allocation register..ENETC 1 time gate scheduling table allocation register */
62491 /*! @{ */
62492 
62493 #define NETC_IERB_ETGSTAR_NUM_WORDS_MASK         (0xFFFU)
62494 #define NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT        (0U)
62495 #define NETC_IERB_ETGSTAR_NUM_WORDS(x)           (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT)) & NETC_IERB_ETGSTAR_NUM_WORDS_MASK)
62496 /*! @} */
62497 
62498 /* The count of NETC_IERB_ETGSTAR */
62499 #define NETC_IERB_ETGSTAR_COUNT                  (2U)
62500 
62501 /*! @name ETGSLR - ENETC 0 time gate scheduling lookahead register..ENETC 1 time gate scheduling lookahead register */
62502 /*! @{ */
62503 
62504 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK      (0xFFFFFU)
62505 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT     (0U)
62506 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK)
62507 
62508 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK     (0x80000000U)
62509 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT    (31U)
62510 /*! ZERO_LOOKAHEAD - Zero Lookahead
62511  *  0b0..Use MIN_LOOKAHEAD value
62512  *  0b1..If a gate control list is configured or when time specific departure is enabled on any traffic class
62513  *       (PTCaTSDR[TSDE] set to 1, where a corresponds to the traffic class number), use MIN_LOOKAHEAD value, otherwise
62514  *       use value of zero
62515  */
62516 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK)
62517 /*! @} */
62518 
62519 /* The count of NETC_IERB_ETGSLR */
62520 #define NETC_IERB_ETGSLR_COUNT                   (2U)
62521 
62522 /*! @name VAMQR - VSI 0 access management qualifier register */
62523 /*! @{ */
62524 
62525 #define NETC_IERB_VAMQR_ARQOS_MASK               (0xF0000U)
62526 #define NETC_IERB_VAMQR_ARQOS_SHIFT              (16U)
62527 #define NETC_IERB_VAMQR_ARQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_ARQOS_SHIFT)) & NETC_IERB_VAMQR_ARQOS_MASK)
62528 
62529 #define NETC_IERB_VAMQR_AWQOS_MASK               (0xF00000U)
62530 #define NETC_IERB_VAMQR_AWQOS_SHIFT              (20U)
62531 #define NETC_IERB_VAMQR_AWQOS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_AWQOS_SHIFT)) & NETC_IERB_VAMQR_AWQOS_MASK)
62532 
62533 #define NETC_IERB_VAMQR_BMT_MASK                 (0x80000000U)
62534 #define NETC_IERB_VAMQR_BMT_SHIFT                (31U)
62535 #define NETC_IERB_VAMQR_BMT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_BMT_SHIFT)) & NETC_IERB_VAMQR_BMT_MASK)
62536 /*! @} */
62537 
62538 /* The count of NETC_IERB_VAMQR */
62539 #define NETC_IERB_VAMQR_COUNT                    (1U)
62540 
62541 /*! @name VBLPR - VSI 0 boot loader parameter register 0..VSI 0 boot loader parameter register 1 */
62542 /*! @{ */
62543 
62544 #define NETC_IERB_VBLPR_PARAM_VAL_MASK           (0xFFFFFFFFU)
62545 #define NETC_IERB_VBLPR_PARAM_VAL_SHIFT          (0U)
62546 #define NETC_IERB_VBLPR_PARAM_VAL(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_VBLPR_PARAM_VAL_MASK)
62547 /*! @} */
62548 
62549 /* The count of NETC_IERB_VBLPR */
62550 #define NETC_IERB_VBLPR_COUNT                    (1U)
62551 
62552 /* The count of NETC_IERB_VBLPR */
62553 #define NETC_IERB_VBLPR_COUNT2                   (2U)
62554 
62555 /*! @name VPMAR0 - VSI 0 primary MAC address register 0 */
62556 /*! @{ */
62557 
62558 #define NETC_IERB_VPMAR0_MAC_ADDR_MASK           (0xFFFFFFFFU)
62559 #define NETC_IERB_VPMAR0_MAC_ADDR_SHIFT          (0U)
62560 #define NETC_IERB_VPMAR0_MAC_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR0_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR0_MAC_ADDR_MASK)
62561 /*! @} */
62562 
62563 /* The count of NETC_IERB_VPMAR0 */
62564 #define NETC_IERB_VPMAR0_COUNT                   (1U)
62565 
62566 /*! @name VPMAR1 - VSI 0 primary MAC address register 1 */
62567 /*! @{ */
62568 
62569 #define NETC_IERB_VPMAR1_MAC_ADDR_MASK           (0xFFFFU)
62570 #define NETC_IERB_VPMAR1_MAC_ADDR_SHIFT          (0U)
62571 #define NETC_IERB_VPMAR1_MAC_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR1_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR1_MAC_ADDR_MASK)
62572 /*! @} */
62573 
62574 /* The count of NETC_IERB_VPMAR1 */
62575 #define NETC_IERB_VPMAR1_COUNT                   (1U)
62576 
62577 
62578 /*!
62579  * @}
62580  */ /* end of group NETC_IERB_Register_Masks */
62581 
62582 
62583 /* NETC_IERB - Peripheral instance base addresses */
62584 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
62585   /** Peripheral NETC_IERB base address */
62586   #define NETC_IERB_BASE                           (0x70800000u)
62587   /** Peripheral NETC_IERB base address */
62588   #define NETC_IERB_BASE_NS                        (0x60800000u)
62589   /** Peripheral NETC_IERB base pointer */
62590   #define NETC_IERB                                ((NETC_IERB_Type *)NETC_IERB_BASE)
62591   /** Peripheral NETC_IERB base pointer */
62592   #define NETC_IERB_NS                             ((NETC_IERB_Type *)NETC_IERB_BASE_NS)
62593   /** Array initializer of NETC_IERB peripheral base addresses */
62594   #define NETC_IERB_BASE_ADDRS                     { NETC_IERB_BASE }
62595   /** Array initializer of NETC_IERB peripheral base pointers */
62596   #define NETC_IERB_BASE_PTRS                      { NETC_IERB }
62597   /** Array initializer of NETC_IERB peripheral base addresses */
62598   #define NETC_IERB_BASE_ADDRS_NS                  { NETC_IERB_BASE_NS }
62599   /** Array initializer of NETC_IERB peripheral base pointers */
62600   #define NETC_IERB_BASE_PTRS_NS                   { NETC_IERB_NS }
62601 #else
62602   /** Peripheral NETC_IERB base address */
62603   #define NETC_IERB_BASE                           (0x60800000u)
62604   /** Peripheral NETC_IERB base pointer */
62605   #define NETC_IERB                                ((NETC_IERB_Type *)NETC_IERB_BASE)
62606   /** Array initializer of NETC_IERB peripheral base addresses */
62607   #define NETC_IERB_BASE_ADDRS                     { NETC_IERB_BASE }
62608   /** Array initializer of NETC_IERB peripheral base pointers */
62609   #define NETC_IERB_BASE_PTRS                      { NETC_IERB }
62610 #endif
62611 
62612 /*!
62613  * @}
62614  */ /* end of group NETC_IERB_Peripheral_Access_Layer */
62615 
62616 
62617 /* ----------------------------------------------------------------------------
62618    -- NETC_PORT Peripheral Access Layer
62619    ---------------------------------------------------------------------------- */
62620 
62621 /*!
62622  * @addtogroup NETC_PORT_Peripheral_Access_Layer NETC_PORT Peripheral Access Layer
62623  * @{
62624  */
62625 
62626 /** NETC_PORT - Register Layout Typedef */
62627 typedef struct {
62628   __I  uint32_t PCAPR;                             /**< Port capability register, offset: 0x0 */
62629   __I  uint32_t PMCAPR;                            /**< Port MAC capability register, offset: 0x4 */
62630   __I  uint32_t PIOCAPR;                           /**< Port I/O capability register, offset: 0x8 */
62631        uint8_t RESERVED_0[4];
62632   __IO uint32_t PCR;                               /**< Port configuration register, offset: 0x10 */
62633        uint8_t RESERVED_1[12];
62634   __IO uint32_t PMAR0;                             /**< Port MAC address register 0, offset: 0x20 */
62635   __IO uint32_t PMAR1;                             /**< Port MAC address register 1, offset: 0x24 */
62636        uint8_t RESERVED_2[40];
62637   __IO uint32_t PTAR;                              /**< Port TPID acceptance register, offset: 0x50 */
62638   __IO uint32_t PQOSMR;                            /**< Port QoS mode register, offset: 0x54 */
62639        uint8_t RESERVED_3[8];
62640   __I  uint32_t PQOR;                              /**< Port Queue Operational register, offset: 0x60, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62641        uint8_t RESERVED_4[28];
62642   __IO uint32_t PPCR;                              /**< Port parser configuration register, offset: 0x80 */
62643   __IO uint32_t PIPFCR;                            /**< Port ingress port filter configuration register, offset: 0x84 */
62644        uint8_t RESERVED_5[24];
62645   __IO uint32_t PSGCR;                             /**< Port stream gate configuration register, offset: 0xA0 */
62646        uint8_t RESERVED_6[92];
62647   __IO uint32_t POR;                               /**< Port operational register, offset: 0x100 */
62648   __I  uint32_t PSR;                               /**< Port status register, offset: 0x104 */
62649   __IO uint32_t PRXSDUOR;                          /**< Port receive SDU overhead register, offset: 0x108 */
62650   __IO uint32_t PTXSDUOR;                          /**< Port transmit SDU overhead register, offset: 0x10C */
62651   __IO uint32_t PTGSCR;                            /**< Port time gate scheduling control register, offset: 0x110 */
62652   __I  uint32_t PTGAGLSR;                          /**< Port time gate scheduling admin gate list status register, offset: 0x114 */
62653   __I  uint32_t PTGAGLLR;                          /**< Port time gate scheduling admin gate list length register, offset: 0x118 */
62654   __I  uint32_t PTGOGLLR;                          /**< Port time gating operational gate list length register, offset: 0x11C */
62655   __IO uint32_t PTGSATOR;                          /**< Port time gate scheduling advance time offset register, offset: 0x120, available only on: ENETC0_PORT, ENETC1_PORT (missing on SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4) */
62656   __I  uint32_t PTGSHAR;                           /**< Port time gate scheduling hold advance register, offset: 0x124, available only on: ENETC0_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3 (missing on ENETC1_PORT, SW0_PORT4) */
62657   __I  uint32_t PTGSRAR;                           /**< Port time gate scheduling release advance register, offset: 0x128, available only on: ENETC0_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3 (missing on ENETC1_PORT, SW0_PORT4) */
62658   __IO uint32_t PTGSHCR;                           /**< Port time gate scheduling hold configuration register, offset: 0x12C, available only on: ENETC0_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3 (missing on ENETC1_PORT, SW0_PORT4) */
62659        uint8_t RESERVED_7[4];
62660   __IO uint32_t PFPCR;                             /**< Port frame preemption configuration register, offset: 0x134, available only on: ENETC0_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3 (missing on ENETC1_PORT, SW0_PORT4) */
62661   __IO uint32_t PDGSR;                             /**< Port default gate state register, offset: 0x138 */
62662        uint8_t RESERVED_8[132];
62663   __I  uint32_t PRXDCR;                            /**< Port Rx discard count register, offset: 0x1C0 */
62664        uint8_t RESERVED_9[4];
62665   __IO uint32_t PRXDCRR0;                          /**< Port Rx discard count reason register 0, offset: 0x1C8 */
62666   __IO uint32_t PRXDCRR1;                          /**< Port Rx discard count reason register 1, offset: 0x1CC */
62667        uint8_t RESERVED_10[16];
62668   __I  uint32_t PTXDCR;                            /**< Port Tx discard count register, offset: 0x1E0, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62669        uint8_t RESERVED_11[4];
62670   __IO uint32_t PTXDCRR0;                          /**< Port Tx discard count reason register 0, offset: 0x1E8, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62671   __IO uint32_t PTXDCRR1;                          /**< Port Tx discard count reason register 1, offset: 0x1EC, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62672        uint8_t RESERVED_12[16];
62673   struct {                                         /* offset: 0x200, array step: 0x20 */
62674     __I  uint32_t PTGSTCSR;                          /**< Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register, array offset: 0x200, array step: 0x20 */
62675          uint8_t RESERVED_0[4];
62676     __IO uint32_t PTCTMSDUR;                         /**< Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register, array offset: 0x208, array step: 0x20 */
62677          uint8_t RESERVED_1[4];
62678     __IO uint32_t PTCCBSR0;                          /**< Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0, array offset: 0x210, array step: 0x20 */
62679     __IO uint32_t PTCCBSR1;                          /**< Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1, array offset: 0x214, array step: 0x20 */
62680          uint8_t RESERVED_2[8];
62681   } TCT_NUM[8];
62682        uint8_t RESERVED_13[256];
62683   __IO uint32_t PBPMCR0;                           /**< Port buffer pool mapping configuration register 0, offset: 0x400, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62684   __IO uint32_t PBPMCR1;                           /**< Port buffer pool mapping configuration register 1, offset: 0x404, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62685        uint8_t RESERVED_14[48];
62686   __IO uint32_t PPCPDEIMR;                         /**< Port PCP DEI mapping register, offset: 0x438 */
62687        uint8_t RESERVED_15[4];
62688   __IO uint32_t PMCR;                              /**< Port mirror configuration register, offset: 0x440, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62689        uint8_t RESERVED_16[12];
62690   __IO uint32_t PCTFCR;                            /**< Port cut through forwarding configuration register, offset: 0x450, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3 (missing on ENETC0_PORT, ENETC1_PORT, SW0_PORT4) */
62691        uint8_t RESERVED_17[4];
62692   __IO uint32_t PLANIDCR;                          /**< Port LANID configuration register, offset: 0x458, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62693        uint8_t RESERVED_18[4];
62694   __IO uint32_t PISIDCR;                           /**< Port ingress stream identification configuration register, offset: 0x460 */
62695   __IO uint32_t PFMCR;                             /**< Port frame modification configuration register, offset: 0x464, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62696        uint8_t RESERVED_19[8];
62697   __IO uint32_t PIPV2QMR0;                         /**< Port IPV to queue mapping register 0, offset: 0x470, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62698        uint8_t RESERVED_20[60];
62699   __I  uint32_t PTCMINLR;                          /**< Port time capture minimum latency register, offset: 0x4B0, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62700   __I  uint32_t PTCMAXLR;                          /**< Port time capture maximum latency register, offset: 0x4B4, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62701        uint8_t RESERVED_21[72];
62702   __IO uint32_t BPCR;                              /**< Bridge port configuration register, offset: 0x500, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62703        uint8_t RESERVED_22[12];
62704   __IO uint32_t BPDVR;                             /**< Bridge port default VLAN register, offset: 0x510, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62705        uint8_t RESERVED_23[12];
62706   __IO uint32_t BPSTGSR;                           /**< Bridge port spanning tree group state register, offset: 0x520, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62707        uint8_t RESERVED_24[4];
62708   __IO uint32_t BPSCR0;                            /**< Bridge port storm control register 0, offset: 0x528, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62709   __IO uint32_t BPSCR1;                            /**< Bridge port storm control register 1, offset: 0x52C, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62710   __I  uint32_t BPOR;                              /**< Bridge port operational register, offset: 0x530, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62711        uint8_t RESERVED_25[76];
62712   __I  uint32_t BPDCR;                             /**< Bridge port discard count register, offset: 0x580, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62713        uint8_t RESERVED_26[4];
62714   __IO uint32_t BPDCRR0;                           /**< Bridge port discard count reason register 0, offset: 0x588, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62715   __IO uint32_t BPDCRR1;                           /**< Bridge port discard count reason register 1, offset: 0x58C, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62716   __IO uint32_t BPMLFSR;                           /**< Bridge port MAC learning failure status register, offset: 0x590, available only on: SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 (missing on ENETC0_PORT, ENETC1_PORT) */
62717 } NETC_PORT_Type;
62718 
62719 /* ----------------------------------------------------------------------------
62720    -- NETC_PORT Register Masks
62721    ---------------------------------------------------------------------------- */
62722 
62723 /*!
62724  * @addtogroup NETC_PORT_Register_Masks NETC_PORT Register Masks
62725  * @{
62726  */
62727 
62728 /*! @name PCAPR - Port capability register */
62729 /*! @{ */
62730 
62731 #define NETC_PORT_PCAPR_LINK_TYPE_MASK           (0x10U)
62732 #define NETC_PORT_PCAPR_LINK_TYPE_SHIFT          (4U)
62733 #define NETC_PORT_PCAPR_LINK_TYPE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_LINK_TYPE_SHIFT)) & NETC_PORT_PCAPR_LINK_TYPE_MASK)
62734 
62735 #define NETC_PORT_PCAPR_NUM_TC_MASK              (0xF000U)
62736 #define NETC_PORT_PCAPR_NUM_TC_SHIFT             (12U)
62737 #define NETC_PORT_PCAPR_NUM_TC(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_NUM_TC_SHIFT)) & NETC_PORT_PCAPR_NUM_TC_MASK)
62738 
62739 #define NETC_PORT_PCAPR_NUM_Q_MASK               (0xF0000U)
62740 #define NETC_PORT_PCAPR_NUM_Q_SHIFT              (16U)
62741 #define NETC_PORT_PCAPR_NUM_Q(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_NUM_Q_SHIFT)) & NETC_PORT_PCAPR_NUM_Q_MASK)
62742 
62743 #define NETC_PORT_PCAPR_NUM_CG_MASK              (0xF000000U)
62744 #define NETC_PORT_PCAPR_NUM_CG_SHIFT             (24U)
62745 #define NETC_PORT_PCAPR_NUM_CG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_NUM_CG_SHIFT)) & NETC_PORT_PCAPR_NUM_CG_MASK)
62746 
62747 #define NETC_PORT_PCAPR_TGS_MASK                 (0x10000000U)
62748 #define NETC_PORT_PCAPR_TGS_SHIFT                (28U)
62749 /*! TGS - Time Gate Scheduling */
62750 #define NETC_PORT_PCAPR_TGS(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_TGS_SHIFT)) & NETC_PORT_PCAPR_TGS_MASK)
62751 
62752 #define NETC_PORT_PCAPR_CBS_MASK                 (0x20000000U)
62753 #define NETC_PORT_PCAPR_CBS_SHIFT                (29U)
62754 /*! CBS - Credit Based Shaping */
62755 #define NETC_PORT_PCAPR_CBS(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_CBS_SHIFT)) & NETC_PORT_PCAPR_CBS_MASK)
62756 /*! @} */
62757 
62758 /*! @name PMCAPR - Port MAC capability register */
62759 /*! @{ */
62760 
62761 #define NETC_PORT_PMCAPR_MAC_VAR_MASK            (0x7U)
62762 #define NETC_PORT_PMCAPR_MAC_VAR_SHIFT           (0U)
62763 /*! MAC_VAR - MAC Variant */
62764 #define NETC_PORT_PMCAPR_MAC_VAR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_MAC_VAR_SHIFT)) & NETC_PORT_PMCAPR_MAC_VAR_MASK)
62765 
62766 #define NETC_PORT_PMCAPR_EFPAD_MASK              (0x30U)
62767 #define NETC_PORT_PMCAPR_EFPAD_SHIFT             (4U)
62768 #define NETC_PORT_PMCAPR_EFPAD(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_EFPAD_SHIFT)) & NETC_PORT_PMCAPR_EFPAD_MASK)
62769 
62770 #define NETC_PORT_PMCAPR_PIPG_MASK               (0x40U)
62771 #define NETC_PORT_PMCAPR_PIPG_SHIFT              (6U)
62772 #define NETC_PORT_PMCAPR_PIPG(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_PIPG_SHIFT)) & NETC_PORT_PMCAPR_PIPG_MASK)
62773 
62774 #define NETC_PORT_PMCAPR_HD_MASK                 (0x100U)
62775 #define NETC_PORT_PMCAPR_HD_SHIFT                (8U)
62776 #define NETC_PORT_PMCAPR_HD(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_HD_SHIFT)) & NETC_PORT_PMCAPR_HD_MASK)
62777 
62778 #define NETC_PORT_PMCAPR_FP_MASK                 (0x600U)
62779 #define NETC_PORT_PMCAPR_FP_SHIFT                (9U)
62780 /*! FP - Indicates if frame preemption is supported */
62781 #define NETC_PORT_PMCAPR_FP(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_FP_SHIFT)) & NETC_PORT_PMCAPR_FP_MASK)
62782 
62783 #define NETC_PORT_PMCAPR_MIN_MPDU_MASK           (0x1000U)
62784 #define NETC_PORT_PMCAPR_MIN_MPDU_SHIFT          (12U)
62785 /*! MIN_MPDU - Minimum MAC Protocol Data Unit (PDU) size check */
62786 #define NETC_PORT_PMCAPR_MIN_MPDU(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_MIN_MPDU_SHIFT)) & NETC_PORT_PMCAPR_MIN_MPDU_MASK)
62787 
62788 #define NETC_PORT_PMCAPR_MII_PROT_MASK           (0xF000000U)
62789 #define NETC_PORT_PMCAPR_MII_PROT_SHIFT          (24U)
62790 /*! MII_PROT - Indicates the MII protocol supported */
62791 #define NETC_PORT_PMCAPR_MII_PROT(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_MII_PROT_SHIFT)) & NETC_PORT_PMCAPR_MII_PROT_MASK)
62792 /*! @} */
62793 
62794 /*! @name PIOCAPR - Port I/O capability register */
62795 /*! @{ */
62796 
62797 #define NETC_PORT_PIOCAPR_PCS_PROT_MASK          (0xFFFFU)
62798 #define NETC_PORT_PIOCAPR_PCS_PROT_SHIFT         (0U)
62799 /*! PCS_PROT - PCS protocols supported */
62800 #define NETC_PORT_PIOCAPR_PCS_PROT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_PCS_PROT_SHIFT)) & NETC_PORT_PIOCAPR_PCS_PROT_MASK)
62801 
62802 #define NETC_PORT_PIOCAPR_IO_VAR_MASK            (0xF000000U)
62803 #define NETC_PORT_PIOCAPR_IO_VAR_SHIFT           (24U)
62804 /*! IO_VAR - IO Variants supported */
62805 #define NETC_PORT_PIOCAPR_IO_VAR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_IO_VAR_SHIFT)) & NETC_PORT_PIOCAPR_IO_VAR_MASK)
62806 
62807 #define NETC_PORT_PIOCAPR_EMDIO_MASK             (0x10000000U)
62808 #define NETC_PORT_PIOCAPR_EMDIO_SHIFT            (28U)
62809 #define NETC_PORT_PIOCAPR_EMDIO(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_EMDIO_SHIFT)) & NETC_PORT_PIOCAPR_EMDIO_MASK)
62810 
62811 #define NETC_PORT_PIOCAPR_REVMII_RATE_MASK       (0x40000000U)
62812 #define NETC_PORT_PIOCAPR_REVMII_RATE_SHIFT      (30U)
62813 /*! REVMII_RATE - RevMII MII rate */
62814 #define NETC_PORT_PIOCAPR_REVMII_RATE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_REVMII_RATE_SHIFT)) & NETC_PORT_PIOCAPR_REVMII_RATE_MASK)
62815 
62816 #define NETC_PORT_PIOCAPR_REVMII_MASK            (0x80000000U)
62817 #define NETC_PORT_PIOCAPR_REVMII_SHIFT           (31U)
62818 /*! REVMII - Reverse Mode Device Configuration */
62819 #define NETC_PORT_PIOCAPR_REVMII(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_REVMII_SHIFT)) & NETC_PORT_PIOCAPR_REVMII_MASK)
62820 /*! @} */
62821 
62822 /*! @name PCR - Port configuration register */
62823 /*! @{ */
62824 
62825 #define NETC_PORT_PCR_HDR_FMT_MASK               (0x1U)
62826 #define NETC_PORT_PCR_HDR_FMT_SHIFT              (0U)
62827 #define NETC_PORT_PCR_HDR_FMT(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_HDR_FMT_SHIFT)) & NETC_PORT_PCR_HDR_FMT_MASK)
62828 
62829 #define NETC_PORT_PCR_L2DOSE_MASK                (0x10U)
62830 #define NETC_PORT_PCR_L2DOSE_SHIFT               (4U)
62831 #define NETC_PORT_PCR_L2DOSE(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_L2DOSE_SHIFT)) & NETC_PORT_PCR_L2DOSE_MASK)
62832 
62833 #define NETC_PORT_PCR_TIMER_CS_MASK              (0x100U)
62834 #define NETC_PORT_PCR_TIMER_CS_SHIFT             (8U)
62835 #define NETC_PORT_PCR_TIMER_CS(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_TIMER_CS_SHIFT)) & NETC_PORT_PCR_TIMER_CS_MASK)
62836 
62837 #define NETC_PORT_PCR_PSPEED_MASK                (0x3FFF0000U)
62838 #define NETC_PORT_PCR_PSPEED_SHIFT               (16U)
62839 #define NETC_PORT_PCR_PSPEED(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_PSPEED_SHIFT)) & NETC_PORT_PCR_PSPEED_MASK)
62840 /*! @} */
62841 
62842 /*! @name PMAR0 - Port MAC address register 0 */
62843 /*! @{ */
62844 
62845 #define NETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK       (0xFFFFFFFFU)
62846 #define NETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT      (0U)
62847 #define NETC_PORT_PMAR0_PRIM_MAC_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK)
62848 /*! @} */
62849 
62850 /*! @name PMAR1 - Port MAC address register 1 */
62851 /*! @{ */
62852 
62853 #define NETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK       (0xFFFFU)
62854 #define NETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT      (0U)
62855 #define NETC_PORT_PMAR1_PRIM_MAC_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK)
62856 /*! @} */
62857 
62858 /*! @name PTAR - Port TPID acceptance register */
62859 /*! @{ */
62860 
62861 #define NETC_PORT_PTAR_OVTPIDL_MASK              (0xFU)
62862 #define NETC_PORT_PTAR_OVTPIDL_SHIFT             (0U)
62863 #define NETC_PORT_PTAR_OVTPIDL(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTAR_OVTPIDL_SHIFT)) & NETC_PORT_PTAR_OVTPIDL_MASK)
62864 
62865 #define NETC_PORT_PTAR_IVTPIDL_MASK              (0xF0U)
62866 #define NETC_PORT_PTAR_IVTPIDL_SHIFT             (4U)
62867 #define NETC_PORT_PTAR_IVTPIDL(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTAR_IVTPIDL_SHIFT)) & NETC_PORT_PTAR_IVTPIDL_MASK)
62868 /*! @} */
62869 
62870 /*! @name PQOSMR - Port QoS mode register */
62871 /*! @{ */
62872 
62873 #define NETC_PORT_PQOSMR_VS_MASK                 (0x1U)
62874 #define NETC_PORT_PQOSMR_VS_SHIFT                (0U)
62875 #define NETC_PORT_PQOSMR_VS(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VS_SHIFT)) & NETC_PORT_PQOSMR_VS_MASK)
62876 
62877 #define NETC_PORT_PQOSMR_VE_MASK                 (0x2U)
62878 #define NETC_PORT_PQOSMR_VE_SHIFT                (1U)
62879 #define NETC_PORT_PQOSMR_VE(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VE_SHIFT)) & NETC_PORT_PQOSMR_VE_MASK)
62880 
62881 #define NETC_PORT_PQOSMR_DDR_MASK                (0xCU)
62882 #define NETC_PORT_PQOSMR_DDR_SHIFT               (2U)
62883 #define NETC_PORT_PQOSMR_DDR(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_DDR_SHIFT)) & NETC_PORT_PQOSMR_DDR_MASK)
62884 
62885 #define NETC_PORT_PQOSMR_DIPV_MASK               (0x70U)
62886 #define NETC_PORT_PQOSMR_DIPV_SHIFT              (4U)
62887 #define NETC_PORT_PQOSMR_DIPV(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_DIPV_SHIFT)) & NETC_PORT_PQOSMR_DIPV_MASK)
62888 
62889 #define NETC_PORT_PQOSMR_VQMP_MASK               (0xF0000U)
62890 #define NETC_PORT_PQOSMR_VQMP_SHIFT              (16U)
62891 /*! VQMP - Mapping profile index */
62892 #define NETC_PORT_PQOSMR_VQMP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VQMP_SHIFT)) & NETC_PORT_PQOSMR_VQMP_MASK)
62893 
62894 #define NETC_PORT_PQOSMR_QVMP_MASK               (0xF00000U)
62895 #define NETC_PORT_PQOSMR_QVMP_SHIFT              (20U)
62896 /*! QVMP - Mapping profile index */
62897 #define NETC_PORT_PQOSMR_QVMP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_QVMP_SHIFT)) & NETC_PORT_PQOSMR_QVMP_MASK)
62898 /*! @} */
62899 
62900 /*! @name PQOR - Port Queue Operational register */
62901 /*! @{ */
62902 
62903 #define NETC_PORT_PQOR_Q0S_MASK                  (0x1U)
62904 #define NETC_PORT_PQOR_Q0S_SHIFT                 (0U)
62905 #define NETC_PORT_PQOR_Q0S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q0S_SHIFT)) & NETC_PORT_PQOR_Q0S_MASK)
62906 
62907 #define NETC_PORT_PQOR_Q1S_MASK                  (0x2U)
62908 #define NETC_PORT_PQOR_Q1S_SHIFT                 (1U)
62909 #define NETC_PORT_PQOR_Q1S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q1S_SHIFT)) & NETC_PORT_PQOR_Q1S_MASK)
62910 
62911 #define NETC_PORT_PQOR_Q2S_MASK                  (0x4U)
62912 #define NETC_PORT_PQOR_Q2S_SHIFT                 (2U)
62913 #define NETC_PORT_PQOR_Q2S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q2S_SHIFT)) & NETC_PORT_PQOR_Q2S_MASK)
62914 
62915 #define NETC_PORT_PQOR_Q3S_MASK                  (0x8U)
62916 #define NETC_PORT_PQOR_Q3S_SHIFT                 (3U)
62917 #define NETC_PORT_PQOR_Q3S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q3S_SHIFT)) & NETC_PORT_PQOR_Q3S_MASK)
62918 
62919 #define NETC_PORT_PQOR_Q4S_MASK                  (0x10U)
62920 #define NETC_PORT_PQOR_Q4S_SHIFT                 (4U)
62921 #define NETC_PORT_PQOR_Q4S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q4S_SHIFT)) & NETC_PORT_PQOR_Q4S_MASK)
62922 
62923 #define NETC_PORT_PQOR_Q5S_MASK                  (0x20U)
62924 #define NETC_PORT_PQOR_Q5S_SHIFT                 (5U)
62925 #define NETC_PORT_PQOR_Q5S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q5S_SHIFT)) & NETC_PORT_PQOR_Q5S_MASK)
62926 
62927 #define NETC_PORT_PQOR_Q6S_MASK                  (0x40U)
62928 #define NETC_PORT_PQOR_Q6S_SHIFT                 (6U)
62929 #define NETC_PORT_PQOR_Q6S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q6S_SHIFT)) & NETC_PORT_PQOR_Q6S_MASK)
62930 
62931 #define NETC_PORT_PQOR_Q7S_MASK                  (0x80U)
62932 #define NETC_PORT_PQOR_Q7S_SHIFT                 (7U)
62933 #define NETC_PORT_PQOR_Q7S(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOR_Q7S_SHIFT)) & NETC_PORT_PQOR_Q7S_MASK)
62934 /*! @} */
62935 
62936 /*! @name PPCR - Port parser configuration register */
62937 /*! @{ */
62938 
62939 #define NETC_PORT_PPCR_L1PFS_MASK                (0x3EU)
62940 #define NETC_PORT_PPCR_L1PFS_SHIFT               (1U)
62941 #define NETC_PORT_PPCR_L1PFS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L1PFS_SHIFT)) & NETC_PORT_PPCR_L1PFS_MASK)
62942 
62943 #define NETC_PORT_PPCR_L2PFS_MASK                (0x3E00U)
62944 #define NETC_PORT_PPCR_L2PFS_SHIFT               (9U)
62945 #define NETC_PORT_PPCR_L2PFS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L2PFS_SHIFT)) & NETC_PORT_PPCR_L2PFS_MASK)
62946 
62947 #define NETC_PORT_PPCR_L3HFP_MASK                (0x10000U)
62948 #define NETC_PORT_PPCR_L3HFP_SHIFT               (16U)
62949 /*! L3HFP - L3 header fields present
62950  *  0b0..No L3 header present. Indicates to the parser of not parsing the L3 header. Parsing in this case would go
62951  *       as far as the L2 header regardless of whether or not there is an L3 header in the frame. This option
62952  *       should not be used if there are any table lookup entries that contain L3/L4 key fields that could be matched
62953  *       against a frame.
62954  *  0b1..Parse L3 header if present in the frame.
62955  */
62956 #define NETC_PORT_PPCR_L3HFP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L3HFP_SHIFT)) & NETC_PORT_PPCR_L3HFP_MASK)
62957 
62958 #define NETC_PORT_PPCR_L3PFS_MASK                (0x3E0000U)
62959 #define NETC_PORT_PPCR_L3PFS_SHIFT               (17U)
62960 /*! L3PFS - L3 payload fields size in bytes */
62961 #define NETC_PORT_PPCR_L3PFS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L3PFS_SHIFT)) & NETC_PORT_PPCR_L3PFS_MASK)
62962 
62963 #define NETC_PORT_PPCR_L4HFP_MASK                (0x1000000U)
62964 #define NETC_PORT_PPCR_L4HFP_SHIFT               (24U)
62965 /*! L4HFP - L4 Header fields present
62966  *  0b0..No L4 header present. Indicates to the parser of not parsing the L4 header. Parsing in this case would go
62967  *       as far as the L3 header if configured to parse it (L3HFP=1) regardless of whether or not there is an L4
62968  *       header in the frame. This option should not be used if there are any table lookup entries that contain L4
62969  *       key fields that could be matched against a frame.
62970  *  0b1..Parse L4 header if present in the frame
62971  */
62972 #define NETC_PORT_PPCR_L4HFP(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L4HFP_SHIFT)) & NETC_PORT_PPCR_L4HFP_MASK)
62973 
62974 #define NETC_PORT_PPCR_L4PFS_MASK                (0x3E000000U)
62975 #define NETC_PORT_PPCR_L4PFS_SHIFT               (25U)
62976 /*! L4PFS - L4 payload fields size in bytes */
62977 #define NETC_PORT_PPCR_L4PFS(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L4PFS_SHIFT)) & NETC_PORT_PPCR_L4PFS_MASK)
62978 /*! @} */
62979 
62980 /*! @name PIPFCR - Port ingress port filter configuration register */
62981 /*! @{ */
62982 
62983 #define NETC_PORT_PIPFCR_EN_MASK                 (0x1U)
62984 #define NETC_PORT_PIPFCR_EN_SHIFT                (0U)
62985 #define NETC_PORT_PIPFCR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPFCR_EN_SHIFT)) & NETC_PORT_PIPFCR_EN_MASK)
62986 /*! @} */
62987 
62988 /*! @name PSGCR - Port stream gate configuration register */
62989 /*! @{ */
62990 
62991 #define NETC_PORT_PSGCR_PDELAY_MASK              (0xFFFFFFU)
62992 #define NETC_PORT_PSGCR_PDELAY_SHIFT             (0U)
62993 #define NETC_PORT_PSGCR_PDELAY(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSGCR_PDELAY_SHIFT)) & NETC_PORT_PSGCR_PDELAY_MASK)
62994 
62995 #define NETC_PORT_PSGCR_OGC_MASK                 (0x80000000U)
62996 #define NETC_PORT_PSGCR_OGC_SHIFT                (31U)
62997 /*! OGC - Stream Gate Open Gate Check mode */
62998 #define NETC_PORT_PSGCR_OGC(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSGCR_OGC_SHIFT)) & NETC_PORT_PSGCR_OGC_MASK)
62999 /*! @} */
63000 
63001 /*! @name POR - Port operational register */
63002 /*! @{ */
63003 
63004 #define NETC_PORT_POR_TXDIS_MASK                 (0x1U)
63005 #define NETC_PORT_POR_TXDIS_SHIFT                (0U)
63006 /*! TXDIS - Tx Disable.
63007  *  0b0..Tx path is enabled
63008  *  0b1..Tx path is disabled.
63009  */
63010 #define NETC_PORT_POR_TXDIS(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_POR_TXDIS_SHIFT)) & NETC_PORT_POR_TXDIS_MASK)
63011 
63012 #define NETC_PORT_POR_RXDIS_MASK                 (0x2U)
63013 #define NETC_PORT_POR_RXDIS_SHIFT                (1U)
63014 /*! RXDIS - Rx Disable.
63015  *  0b0..Rx path is enabled.
63016  *  0b1..Rx path is disabled.
63017  */
63018 #define NETC_PORT_POR_RXDIS(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_POR_RXDIS_SHIFT)) & NETC_PORT_POR_RXDIS_MASK)
63019 /*! @} */
63020 
63021 /*! @name PSR - Port status register */
63022 /*! @{ */
63023 
63024 #define NETC_PORT_PSR_TX_BUSY_MASK               (0x1U)
63025 #define NETC_PORT_PSR_TX_BUSY_SHIFT              (0U)
63026 /*! TX_BUSY - Transmit busy.
63027  *  0b0..Idle
63028  *  0b1..Busy
63029  */
63030 #define NETC_PORT_PSR_TX_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSR_TX_BUSY_SHIFT)) & NETC_PORT_PSR_TX_BUSY_MASK)
63031 
63032 #define NETC_PORT_PSR_RX_BUSY_MASK               (0x2U)
63033 #define NETC_PORT_PSR_RX_BUSY_SHIFT              (1U)
63034 /*! RX_BUSY - Receive busy.
63035  *  0b0..Idle
63036  *  0b1..Busy
63037  */
63038 #define NETC_PORT_PSR_RX_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSR_RX_BUSY_SHIFT)) & NETC_PORT_PSR_RX_BUSY_MASK)
63039 /*! @} */
63040 
63041 /*! @name PRXSDUOR - Port receive SDU overhead register */
63042 /*! @{ */
63043 
63044 #define NETC_PORT_PRXSDUOR_PPDU_BCO_MASK         (0x1FU)
63045 #define NETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT        (0U)
63046 /*! PPDU_BCO - PPDU Byte count overhead */
63047 #define NETC_PORT_PRXSDUOR_PPDU_BCO(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT)) & NETC_PORT_PRXSDUOR_PPDU_BCO_MASK)
63048 
63049 #define NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK       (0x1F00U)
63050 #define NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT      (8U)
63051 /*! MACSEC_BCO - MACSec byte count overhead */
63052 #define NETC_PORT_PRXSDUOR_MACSEC_BCO(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK)
63053 /*! @} */
63054 
63055 /*! @name PTXSDUOR - Port transmit SDU overhead register */
63056 /*! @{ */
63057 
63058 #define NETC_PORT_PTXSDUOR_PPDU_BCO_MASK         (0x1FU)
63059 #define NETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT        (0U)
63060 /*! PPDU_BCO - PPDU Byte count overhead */
63061 #define NETC_PORT_PTXSDUOR_PPDU_BCO(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT)) & NETC_PORT_PTXSDUOR_PPDU_BCO_MASK)
63062 
63063 #define NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK       (0x1F00U)
63064 #define NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT      (8U)
63065 /*! MACSEC_BCO - MACSec byte count overhead */
63066 #define NETC_PORT_PTXSDUOR_MACSEC_BCO(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK)
63067 /*! @} */
63068 
63069 /*! @name PTGSCR - Port time gate scheduling control register */
63070 /*! @{ */
63071 
63072 #define NETC_PORT_PTGSCR_TGE_MASK                (0x80000000U)
63073 #define NETC_PORT_PTGSCR_TGE_SHIFT               (31U)
63074 /*! TGE - Time Gating Enable
63075  *  0b0..Time gating disabled.
63076  *  0b1..Time gating enabled.
63077  */
63078 #define NETC_PORT_PTGSCR_TGE(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSCR_TGE_SHIFT)) & NETC_PORT_PTGSCR_TGE_MASK)
63079 /*! @} */
63080 
63081 /*! @name PTGAGLSR - Port time gate scheduling admin gate list status register */
63082 /*! @{ */
63083 
63084 #define NETC_PORT_PTGAGLSR_TG_MASK               (0x1U)
63085 #define NETC_PORT_PTGAGLSR_TG_SHIFT              (0U)
63086 #define NETC_PORT_PTGAGLSR_TG(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLSR_TG_SHIFT)) & NETC_PORT_PTGAGLSR_TG_MASK)
63087 
63088 #define NETC_PORT_PTGAGLSR_CFG_PEND_MASK         (0x2U)
63089 #define NETC_PORT_PTGAGLSR_CFG_PEND_SHIFT        (1U)
63090 #define NETC_PORT_PTGAGLSR_CFG_PEND(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLSR_CFG_PEND_SHIFT)) & NETC_PORT_PTGAGLSR_CFG_PEND_MASK)
63091 /*! @} */
63092 
63093 /*! @name PTGAGLLR - Port time gate scheduling admin gate list length register */
63094 /*! @{ */
63095 
63096 #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK (0xFFFFU)
63097 #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT (0U)
63098 #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT)) & NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK)
63099 /*! @} */
63100 
63101 /*! @name PTGOGLLR - Port time gating operational gate list length register */
63102 /*! @{ */
63103 
63104 #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK (0xFFFFU)
63105 #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT (0U)
63106 #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT)) & NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK)
63107 /*! @} */
63108 
63109 /*! @name PTGSATOR - Port time gate scheduling advance time offset register */
63110 /*! @{ */
63111 
63112 #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK  (0xFFFFU)
63113 #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT (0U)
63114 #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET(x)    (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT)) & NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK)
63115 /*! @} */
63116 
63117 /*! @name PTGSHAR - Port time gate scheduling hold advance register */
63118 /*! @{ */
63119 
63120 #define NETC_PORT_PTGSHAR_HOLDADVANCE_MASK       (0xFFFFU)
63121 #define NETC_PORT_PTGSHAR_HOLDADVANCE_SHIFT      (0U)
63122 #define NETC_PORT_PTGSHAR_HOLDADVANCE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSHAR_HOLDADVANCE_SHIFT)) & NETC_PORT_PTGSHAR_HOLDADVANCE_MASK)
63123 /*! @} */
63124 
63125 /*! @name PTGSRAR - Port time gate scheduling release advance register */
63126 /*! @{ */
63127 
63128 #define NETC_PORT_PTGSRAR_RELEASEADVANCE_MASK    (0xFFFFU)
63129 #define NETC_PORT_PTGSRAR_RELEASEADVANCE_SHIFT   (0U)
63130 #define NETC_PORT_PTGSRAR_RELEASEADVANCE(x)      (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSRAR_RELEASEADVANCE_SHIFT)) & NETC_PORT_PTGSRAR_RELEASEADVANCE_MASK)
63131 /*! @} */
63132 
63133 /*! @name PTGSHCR - Port time gate scheduling hold configuration register */
63134 /*! @{ */
63135 
63136 #define NETC_PORT_PTGSHCR_HOLD_SKEW_MASK         (0xFFFFFU)
63137 #define NETC_PORT_PTGSHCR_HOLD_SKEW_SHIFT        (0U)
63138 #define NETC_PORT_PTGSHCR_HOLD_SKEW(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSHCR_HOLD_SKEW_SHIFT)) & NETC_PORT_PTGSHCR_HOLD_SKEW_MASK)
63139 /*! @} */
63140 
63141 /*! @name PFPCR - Port frame preemption configuration register */
63142 /*! @{ */
63143 
63144 #define NETC_PORT_PFPCR_FPE_TC0_MASK             (0x1U)
63145 #define NETC_PORT_PFPCR_FPE_TC0_SHIFT            (0U)
63146 #define NETC_PORT_PFPCR_FPE_TC0(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC0_SHIFT)) & NETC_PORT_PFPCR_FPE_TC0_MASK)
63147 
63148 #define NETC_PORT_PFPCR_FPE_TC1_MASK             (0x2U)
63149 #define NETC_PORT_PFPCR_FPE_TC1_SHIFT            (1U)
63150 #define NETC_PORT_PFPCR_FPE_TC1(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC1_SHIFT)) & NETC_PORT_PFPCR_FPE_TC1_MASK)
63151 
63152 #define NETC_PORT_PFPCR_FPE_TC2_MASK             (0x4U)
63153 #define NETC_PORT_PFPCR_FPE_TC2_SHIFT            (2U)
63154 #define NETC_PORT_PFPCR_FPE_TC2(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC2_SHIFT)) & NETC_PORT_PFPCR_FPE_TC2_MASK)
63155 
63156 #define NETC_PORT_PFPCR_FPE_TC3_MASK             (0x8U)
63157 #define NETC_PORT_PFPCR_FPE_TC3_SHIFT            (3U)
63158 #define NETC_PORT_PFPCR_FPE_TC3(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC3_SHIFT)) & NETC_PORT_PFPCR_FPE_TC3_MASK)
63159 
63160 #define NETC_PORT_PFPCR_FPE_TC4_MASK             (0x10U)
63161 #define NETC_PORT_PFPCR_FPE_TC4_SHIFT            (4U)
63162 #define NETC_PORT_PFPCR_FPE_TC4(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC4_SHIFT)) & NETC_PORT_PFPCR_FPE_TC4_MASK)
63163 
63164 #define NETC_PORT_PFPCR_FPE_TC5_MASK             (0x20U)
63165 #define NETC_PORT_PFPCR_FPE_TC5_SHIFT            (5U)
63166 #define NETC_PORT_PFPCR_FPE_TC5(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC5_SHIFT)) & NETC_PORT_PFPCR_FPE_TC5_MASK)
63167 
63168 #define NETC_PORT_PFPCR_FPE_TC6_MASK             (0x40U)
63169 #define NETC_PORT_PFPCR_FPE_TC6_SHIFT            (6U)
63170 #define NETC_PORT_PFPCR_FPE_TC6(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC6_SHIFT)) & NETC_PORT_PFPCR_FPE_TC6_MASK)
63171 
63172 #define NETC_PORT_PFPCR_FPE_TC7_MASK             (0x80U)
63173 #define NETC_PORT_PFPCR_FPE_TC7_SHIFT            (7U)
63174 #define NETC_PORT_PFPCR_FPE_TC7(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC7_SHIFT)) & NETC_PORT_PFPCR_FPE_TC7_MASK)
63175 /*! @} */
63176 
63177 /*! @name PDGSR - Port default gate state register */
63178 /*! @{ */
63179 
63180 #define NETC_PORT_PDGSR_DGS_TC0_MASK             (0x1U)
63181 #define NETC_PORT_PDGSR_DGS_TC0_SHIFT            (0U)
63182 /*! DGS_TC0
63183  *  0b0..Closed
63184  *  0b1..Open
63185  */
63186 #define NETC_PORT_PDGSR_DGS_TC0(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC0_SHIFT)) & NETC_PORT_PDGSR_DGS_TC0_MASK)
63187 
63188 #define NETC_PORT_PDGSR_DGS_TC1_MASK             (0x2U)
63189 #define NETC_PORT_PDGSR_DGS_TC1_SHIFT            (1U)
63190 /*! DGS_TC1
63191  *  0b0..Closed
63192  *  0b1..Open
63193  */
63194 #define NETC_PORT_PDGSR_DGS_TC1(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC1_SHIFT)) & NETC_PORT_PDGSR_DGS_TC1_MASK)
63195 
63196 #define NETC_PORT_PDGSR_DGS_TC2_MASK             (0x4U)
63197 #define NETC_PORT_PDGSR_DGS_TC2_SHIFT            (2U)
63198 /*! DGS_TC2
63199  *  0b0..Closed
63200  *  0b1..Open
63201  */
63202 #define NETC_PORT_PDGSR_DGS_TC2(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC2_SHIFT)) & NETC_PORT_PDGSR_DGS_TC2_MASK)
63203 
63204 #define NETC_PORT_PDGSR_DGS_TC3_MASK             (0x8U)
63205 #define NETC_PORT_PDGSR_DGS_TC3_SHIFT            (3U)
63206 /*! DGS_TC3
63207  *  0b0..Closed
63208  *  0b1..Open
63209  */
63210 #define NETC_PORT_PDGSR_DGS_TC3(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC3_SHIFT)) & NETC_PORT_PDGSR_DGS_TC3_MASK)
63211 
63212 #define NETC_PORT_PDGSR_DGS_TC4_MASK             (0x10U)
63213 #define NETC_PORT_PDGSR_DGS_TC4_SHIFT            (4U)
63214 /*! DGS_TC4
63215  *  0b0..Closed
63216  *  0b1..Open
63217  */
63218 #define NETC_PORT_PDGSR_DGS_TC4(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC4_SHIFT)) & NETC_PORT_PDGSR_DGS_TC4_MASK)
63219 
63220 #define NETC_PORT_PDGSR_DGS_TC5_MASK             (0x20U)
63221 #define NETC_PORT_PDGSR_DGS_TC5_SHIFT            (5U)
63222 /*! DGS_TC5
63223  *  0b0..Closed
63224  *  0b1..Open
63225  */
63226 #define NETC_PORT_PDGSR_DGS_TC5(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC5_SHIFT)) & NETC_PORT_PDGSR_DGS_TC5_MASK)
63227 
63228 #define NETC_PORT_PDGSR_DGS_TC6_MASK             (0x40U)
63229 #define NETC_PORT_PDGSR_DGS_TC6_SHIFT            (6U)
63230 /*! DGS_TC6
63231  *  0b0..Closed
63232  *  0b1..Open
63233  */
63234 #define NETC_PORT_PDGSR_DGS_TC6(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC6_SHIFT)) & NETC_PORT_PDGSR_DGS_TC6_MASK)
63235 
63236 #define NETC_PORT_PDGSR_DGS_TC7_MASK             (0x80U)
63237 #define NETC_PORT_PDGSR_DGS_TC7_SHIFT            (7U)
63238 /*! DGS_TC7
63239  *  0b0..Closed
63240  *  0b1..Open
63241  */
63242 #define NETC_PORT_PDGSR_DGS_TC7(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC7_SHIFT)) & NETC_PORT_PDGSR_DGS_TC7_MASK)
63243 /*! @} */
63244 
63245 /*! @name PRXDCR - Port Rx discard count register */
63246 /*! @{ */
63247 
63248 #define NETC_PORT_PRXDCR_COUNT_MASK              (0xFFFFFFFFU)
63249 #define NETC_PORT_PRXDCR_COUNT_SHIFT             (0U)
63250 #define NETC_PORT_PRXDCR_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCR_COUNT_SHIFT)) & NETC_PORT_PRXDCR_COUNT_MASK)
63251 /*! @} */
63252 
63253 /*! @name PRXDCRR0 - Port Rx discard count reason register 0 */
63254 /*! @{ */
63255 
63256 #define NETC_PORT_PRXDCRR0_PCDR_MASK             (0x1U)
63257 #define NETC_PORT_PRXDCRR0_PCDR_SHIFT            (0U)
63258 #define NETC_PORT_PRXDCRR0_PCDR(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_PCDR_SHIFT)) & NETC_PORT_PRXDCRR0_PCDR_MASK)
63259 
63260 #define NETC_PORT_PRXDCRR0_SMREDR_MASK           (0x2U)
63261 #define NETC_PORT_PRXDCRR0_SMREDR_SHIFT          (1U)
63262 #define NETC_PORT_PRXDCRR0_SMREDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SMREDR_SHIFT)) & NETC_PORT_PRXDCRR0_SMREDR_MASK)
63263 
63264 #define NETC_PORT_PRXDCRR0_RXDISDR_MASK          (0x4U)
63265 #define NETC_PORT_PRXDCRR0_RXDISDR_SHIFT         (2U)
63266 #define NETC_PORT_PRXDCRR0_RXDISDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_RXDISDR_SHIFT)) & NETC_PORT_PRXDCRR0_RXDISDR_MASK)
63267 
63268 #define NETC_PORT_PRXDCRR0_IPFDR_MASK            (0x8U)
63269 #define NETC_PORT_PRXDCRR0_IPFDR_SHIFT           (3U)
63270 #define NETC_PORT_PRXDCRR0_IPFDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_IPFDR_SHIFT)) & NETC_PORT_PRXDCRR0_IPFDR_MASK)
63271 
63272 #define NETC_PORT_PRXDCRR0_RPDR_MASK             (0x10U)
63273 #define NETC_PORT_PRXDCRR0_RPDR_SHIFT            (4U)
63274 #define NETC_PORT_PRXDCRR0_RPDR(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_RPDR_SHIFT)) & NETC_PORT_PRXDCRR0_RPDR_MASK)
63275 
63276 #define NETC_PORT_PRXDCRR0_ISFDR_MASK            (0x20U)
63277 #define NETC_PORT_PRXDCRR0_ISFDR_SHIFT           (5U)
63278 #define NETC_PORT_PRXDCRR0_ISFDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ISFDR_SHIFT)) & NETC_PORT_PRXDCRR0_ISFDR_MASK)
63279 
63280 #define NETC_PORT_PRXDCRR0_SGCDR_MASK            (0x40U)
63281 #define NETC_PORT_PRXDCRR0_SGCDR_SHIFT           (6U)
63282 #define NETC_PORT_PRXDCRR0_SGCDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SGCDR_SHIFT)) & NETC_PORT_PRXDCRR0_SGCDR_MASK)
63283 
63284 #define NETC_PORT_PRXDCRR0_SGOEDR_MASK           (0x80U)
63285 #define NETC_PORT_PRXDCRR0_SGOEDR_SHIFT          (7U)
63286 #define NETC_PORT_PRXDCRR0_SGOEDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SGOEDR_SHIFT)) & NETC_PORT_PRXDCRR0_SGOEDR_MASK)
63287 
63288 #define NETC_PORT_PRXDCRR0_MSDUEDR_MASK          (0x100U)
63289 #define NETC_PORT_PRXDCRR0_MSDUEDR_SHIFT         (8U)
63290 #define NETC_PORT_PRXDCRR0_MSDUEDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_MSDUEDR_SHIFT)) & NETC_PORT_PRXDCRR0_MSDUEDR_MASK)
63291 
63292 #define NETC_PORT_PRXDCRR0_FMMEDR_MASK           (0x200U)
63293 #define NETC_PORT_PRXDCRR0_FMMEDR_SHIFT          (9U)
63294 #define NETC_PORT_PRXDCRR0_FMMEDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_FMMEDR_SHIFT)) & NETC_PORT_PRXDCRR0_FMMEDR_MASK)
63295 
63296 #define NETC_PORT_PRXDCRR0_CMDR_MASK             (0x400U)
63297 #define NETC_PORT_PRXDCRR0_CMDR_SHIFT            (10U)
63298 #define NETC_PORT_PRXDCRR0_CMDR(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_CMDR_SHIFT)) & NETC_PORT_PRXDCRR0_CMDR_MASK)
63299 
63300 #define NETC_PORT_PRXDCRR0_ITEDR_MASK            (0x800U)
63301 #define NETC_PORT_PRXDCRR0_ITEDR_SHIFT           (11U)
63302 #define NETC_PORT_PRXDCRR0_ITEDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ITEDR_SHIFT)) & NETC_PORT_PRXDCRR0_ITEDR_MASK)
63303 
63304 #define NETC_PORT_PRXDCRR0_ECCEDR_MASK           (0x1000U)
63305 #define NETC_PORT_PRXDCRR0_ECCEDR_SHIFT          (12U)
63306 #define NETC_PORT_PRXDCRR0_ECCEDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ECCEDR_SHIFT)) & NETC_PORT_PRXDCRR0_ECCEDR_MASK)
63307 
63308 #define NETC_PORT_PRXDCRR0_SIFDR_MASK            (0x2000U)
63309 #define NETC_PORT_PRXDCRR0_SIFDR_SHIFT           (13U)
63310 #define NETC_PORT_PRXDCRR0_SIFDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SIFDR_SHIFT)) & NETC_PORT_PRXDCRR0_SIFDR_MASK)
63311 
63312 #define NETC_PORT_PRXDCRR0_L2DOSDR_MASK          (0x4000U)
63313 #define NETC_PORT_PRXDCRR0_L2DOSDR_SHIFT         (14U)
63314 #define NETC_PORT_PRXDCRR0_L2DOSDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_L2DOSDR_SHIFT)) & NETC_PORT_PRXDCRR0_L2DOSDR_MASK)
63315 
63316 #define NETC_PORT_PRXDCRR0_NODESTDR_MASK         (0x20000U)
63317 #define NETC_PORT_PRXDCRR0_NODESTDR_SHIFT        (17U)
63318 /*! NODESTDR - No Destination Discard Reason */
63319 #define NETC_PORT_PRXDCRR0_NODESTDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_NODESTDR_SHIFT)) & NETC_PORT_PRXDCRR0_NODESTDR_MASK)
63320 /*! @} */
63321 
63322 /*! @name PRXDCRR1 - Port Rx discard count reason register 1 */
63323 /*! @{ */
63324 
63325 #define NETC_PORT_PRXDCRR1_ENTRYID_MASK          (0xFFFFU)
63326 #define NETC_PORT_PRXDCRR1_ENTRYID_SHIFT         (0U)
63327 #define NETC_PORT_PRXDCRR1_ENTRYID(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR1_ENTRYID_SHIFT)) & NETC_PORT_PRXDCRR1_ENTRYID_MASK)
63328 
63329 #define NETC_PORT_PRXDCRR1_TT_MASK               (0xF0000000U)
63330 #define NETC_PORT_PRXDCRR1_TT_SHIFT              (28U)
63331 #define NETC_PORT_PRXDCRR1_TT(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR1_TT_SHIFT)) & NETC_PORT_PRXDCRR1_TT_MASK)
63332 /*! @} */
63333 
63334 /*! @name PTXDCR - Port Tx discard count register */
63335 /*! @{ */
63336 
63337 #define NETC_PORT_PTXDCR_COUNT_MASK              (0xFFFFFFFFU)
63338 #define NETC_PORT_PTXDCR_COUNT_SHIFT             (0U)
63339 #define NETC_PORT_PTXDCR_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCR_COUNT_SHIFT)) & NETC_PORT_PTXDCR_COUNT_MASK)
63340 /*! @} */
63341 
63342 /*! @name PTXDCRR0 - Port Tx discard count reason register 0 */
63343 /*! @{ */
63344 
63345 #define NETC_PORT_PTXDCRR0_TXDISDR_MASK          (0x1U)
63346 #define NETC_PORT_PTXDCRR0_TXDISDR_SHIFT         (0U)
63347 #define NETC_PORT_PTXDCRR0_TXDISDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_TXDISDR_SHIFT)) & NETC_PORT_PTXDCRR0_TXDISDR_MASK)
63348 
63349 #define NETC_PORT_PTXDCRR0_ECCEDR_MASK           (0x2U)
63350 #define NETC_PORT_PTXDCRR0_ECCEDR_SHIFT          (1U)
63351 /*! ECCEDR - ECC Error Discard Reason */
63352 #define NETC_PORT_PTXDCRR0_ECCEDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_ECCEDR_SHIFT)) & NETC_PORT_PTXDCRR0_ECCEDR_MASK)
63353 
63354 #define NETC_PORT_PTXDCRR0_PEDR_MASK             (0x4U)
63355 #define NETC_PORT_PTXDCRR0_PEDR_SHIFT            (2U)
63356 /*! PEDR - Parity Error Discard Reason */
63357 #define NETC_PORT_PTXDCRR0_PEDR(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_PEDR_SHIFT)) & NETC_PORT_PTXDCRR0_PEDR_MASK)
63358 
63359 #define NETC_PORT_PTXDCRR0_TGSFTLDR_MASK         (0x10U)
63360 #define NETC_PORT_PTXDCRR0_TGSFTLDR_SHIFT        (4U)
63361 #define NETC_PORT_PTXDCRR0_TGSFTLDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_TGSFTLDR_SHIFT)) & NETC_PORT_PTXDCRR0_TGSFTLDR_MASK)
63362 
63363 #define NETC_PORT_PTXDCRR0_FMMDR_MASK            (0x20U)
63364 #define NETC_PORT_PTXDCRR0_FMMDR_SHIFT           (5U)
63365 #define NETC_PORT_PTXDCRR0_FMMDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_FMMDR_SHIFT)) & NETC_PORT_PTXDCRR0_FMMDR_MASK)
63366 
63367 #define NETC_PORT_PTXDCRR0_TXDISEDR_MASK         (0x40U)
63368 #define NETC_PORT_PTXDCRR0_TXDISEDR_SHIFT        (6U)
63369 #define NETC_PORT_PTXDCRR0_TXDISEDR(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_TXDISEDR_SHIFT)) & NETC_PORT_PTXDCRR0_TXDISEDR_MASK)
63370 
63371 #define NETC_PORT_PTXDCRR0_MSDUEDR_MASK          (0x80U)
63372 #define NETC_PORT_PTXDCRR0_MSDUEDR_SHIFT         (7U)
63373 #define NETC_PORT_PTXDCRR0_MSDUEDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_MSDUEDR_SHIFT)) & NETC_PORT_PTXDCRR0_MSDUEDR_MASK)
63374 
63375 #define NETC_PORT_PTXDCRR0_QCONGDR_MASK          (0x100U)
63376 #define NETC_PORT_PTXDCRR0_QCONGDR_SHIFT         (8U)
63377 #define NETC_PORT_PTXDCRR0_QCONGDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_QCONGDR_SHIFT)) & NETC_PORT_PTXDCRR0_QCONGDR_MASK)
63378 
63379 #define NETC_PORT_PTXDCRR0_ITEDR_MASK            (0x200U)
63380 #define NETC_PORT_PTXDCRR0_ITEDR_SHIFT           (9U)
63381 #define NETC_PORT_PTXDCRR0_ITEDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_ITEDR_SHIFT)) & NETC_PORT_PTXDCRR0_ITEDR_MASK)
63382 
63383 #define NETC_PORT_PTXDCRR0_INVEQDR_MASK          (0x400U)
63384 #define NETC_PORT_PTXDCRR0_INVEQDR_SHIFT         (10U)
63385 #define NETC_PORT_PTXDCRR0_INVEQDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_INVEQDR_SHIFT)) & NETC_PORT_PTXDCRR0_INVEQDR_MASK)
63386 
63387 #define NETC_PORT_PTXDCRR0_SQRTNSQDR_MASK        (0x800U)
63388 #define NETC_PORT_PTXDCRR0_SQRTNSQDR_SHIFT       (11U)
63389 #define NETC_PORT_PTXDCRR0_SQRTNSQDR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_SQRTNSQDR_SHIFT)) & NETC_PORT_PTXDCRR0_SQRTNSQDR_MASK)
63390 
63391 #define NETC_PORT_PTXDCRR0_SQRRDR_MASK           (0x2000U)
63392 #define NETC_PORT_PTXDCRR0_SQRRDR_SHIFT          (13U)
63393 #define NETC_PORT_PTXDCRR0_SQRRDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_SQRRDR_SHIFT)) & NETC_PORT_PTXDCRR0_SQRRDR_MASK)
63394 
63395 #define NETC_PORT_PTXDCRR0_SQRDDR_MASK           (0x4000U)
63396 #define NETC_PORT_PTXDCRR0_SQRDDR_SHIFT          (14U)
63397 #define NETC_PORT_PTXDCRR0_SQRDDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_SQRDDR_SHIFT)) & NETC_PORT_PTXDCRR0_SQRDDR_MASK)
63398 
63399 #define NETC_PORT_PTXDCRR0_SMREDR_MASK           (0x8000U)
63400 #define NETC_PORT_PTXDCRR0_SMREDR_SHIFT          (15U)
63401 #define NETC_PORT_PTXDCRR0_SMREDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR0_SMREDR_SHIFT)) & NETC_PORT_PTXDCRR0_SMREDR_MASK)
63402 /*! @} */
63403 
63404 /*! @name PTXDCRR1 - Port Tx discard count reason register 1 */
63405 /*! @{ */
63406 
63407 #define NETC_PORT_PTXDCRR1_ENTRYID_MASK          (0xFFFFU)
63408 #define NETC_PORT_PTXDCRR1_ENTRYID_SHIFT         (0U)
63409 #define NETC_PORT_PTXDCRR1_ENTRYID(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR1_ENTRYID_SHIFT)) & NETC_PORT_PTXDCRR1_ENTRYID_MASK)
63410 
63411 #define NETC_PORT_PTXDCRR1_TT_MASK               (0xF0000000U)
63412 #define NETC_PORT_PTXDCRR1_TT_SHIFT              (28U)
63413 #define NETC_PORT_PTXDCRR1_TT(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXDCRR1_TT_SHIFT)) & NETC_PORT_PTXDCRR1_TT_MASK)
63414 /*! @} */
63415 
63416 /*! @name PTGSTCSR - Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register */
63417 /*! @{ */
63418 
63419 #define NETC_PORT_PTGSTCSR_LH_STATE_MASK         (0x10000U)
63420 #define NETC_PORT_PTGSTCSR_LH_STATE_SHIFT        (16U)
63421 #define NETC_PORT_PTGSTCSR_LH_STATE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSTCSR_LH_STATE_SHIFT)) & NETC_PORT_PTGSTCSR_LH_STATE_MASK)
63422 /*! @} */
63423 
63424 /* The count of NETC_PORT_PTGSTCSR */
63425 #define NETC_PORT_PTGSTCSR_COUNT                 (8U)
63426 
63427 /*! @name PTCTMSDUR - Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register */
63428 /*! @{ */
63429 
63430 #define NETC_PORT_PTCTMSDUR_MAXSDU_MASK          (0xFFFFU)
63431 #define NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT         (0U)
63432 #define NETC_PORT_PTCTMSDUR_MAXSDU(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT)) & NETC_PORT_PTCTMSDUR_MAXSDU_MASK)
63433 
63434 #define NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK        (0x30000U)
63435 #define NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT       (16U)
63436 #define NETC_PORT_PTCTMSDUR_SDU_TYPE(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT)) & NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK)
63437 
63438 #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK   (0x1000000U)
63439 #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT  (24U)
63440 #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK)
63441 /*! @} */
63442 
63443 /* The count of NETC_PORT_PTCTMSDUR */
63444 #define NETC_PORT_PTCTMSDUR_COUNT                (8U)
63445 
63446 /*! @name PTCCBSR0 - Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0 */
63447 /*! @{ */
63448 
63449 #define NETC_PORT_PTCCBSR0_BW_MASK               (0x7FU)
63450 #define NETC_PORT_PTCCBSR0_BW_SHIFT              (0U)
63451 /*! BW - Bandwidth */
63452 #define NETC_PORT_PTCCBSR0_BW(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR0_BW_SHIFT)) & NETC_PORT_PTCCBSR0_BW_MASK)
63453 
63454 #define NETC_PORT_PTCCBSR0_CBSE_MASK             (0x80000000U)
63455 #define NETC_PORT_PTCCBSR0_CBSE_SHIFT            (31U)
63456 /*! CBSE - Credit Based Shaper Enable
63457  *  0b0..Disabled
63458  *  0b1..Enabled
63459  */
63460 #define NETC_PORT_PTCCBSR0_CBSE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR0_CBSE_SHIFT)) & NETC_PORT_PTCCBSR0_CBSE_MASK)
63461 /*! @} */
63462 
63463 /* The count of NETC_PORT_PTCCBSR0 */
63464 #define NETC_PORT_PTCCBSR0_COUNT                 (8U)
63465 
63466 /*! @name PTCCBSR1 - Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1 */
63467 /*! @{ */
63468 
63469 #define NETC_PORT_PTCCBSR1_HI_CREDIT_MASK        (0xFFFFFFFFU)
63470 #define NETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT       (0U)
63471 /*! HI_CREDIT - hicredit (in credit units) */
63472 #define NETC_PORT_PTCCBSR1_HI_CREDIT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT)) & NETC_PORT_PTCCBSR1_HI_CREDIT_MASK)
63473 /*! @} */
63474 
63475 /* The count of NETC_PORT_PTCCBSR1 */
63476 #define NETC_PORT_PTCCBSR1_COUNT                 (8U)
63477 
63478 /*! @name PBPMCR0 - Port buffer pool mapping configuration register 0 */
63479 /*! @{ */
63480 
63481 #define NETC_PORT_PBPMCR0_IPV0_INDEX_MASK        (0xFFU)
63482 #define NETC_PORT_PBPMCR0_IPV0_INDEX_SHIFT       (0U)
63483 #define NETC_PORT_PBPMCR0_IPV0_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR0_IPV0_INDEX_SHIFT)) & NETC_PORT_PBPMCR0_IPV0_INDEX_MASK)
63484 
63485 #define NETC_PORT_PBPMCR0_IPV1_INDEX_MASK        (0xFF00U)
63486 #define NETC_PORT_PBPMCR0_IPV1_INDEX_SHIFT       (8U)
63487 #define NETC_PORT_PBPMCR0_IPV1_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR0_IPV1_INDEX_SHIFT)) & NETC_PORT_PBPMCR0_IPV1_INDEX_MASK)
63488 
63489 #define NETC_PORT_PBPMCR0_IPV2_INDEX_MASK        (0xFF0000U)
63490 #define NETC_PORT_PBPMCR0_IPV2_INDEX_SHIFT       (16U)
63491 #define NETC_PORT_PBPMCR0_IPV2_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR0_IPV2_INDEX_SHIFT)) & NETC_PORT_PBPMCR0_IPV2_INDEX_MASK)
63492 
63493 #define NETC_PORT_PBPMCR0_IPV3_INDEX_MASK        (0xFF000000U)
63494 #define NETC_PORT_PBPMCR0_IPV3_INDEX_SHIFT       (24U)
63495 #define NETC_PORT_PBPMCR0_IPV3_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR0_IPV3_INDEX_SHIFT)) & NETC_PORT_PBPMCR0_IPV3_INDEX_MASK)
63496 /*! @} */
63497 
63498 /*! @name PBPMCR1 - Port buffer pool mapping configuration register 1 */
63499 /*! @{ */
63500 
63501 #define NETC_PORT_PBPMCR1_IPV4_INDEX_MASK        (0xFFU)
63502 #define NETC_PORT_PBPMCR1_IPV4_INDEX_SHIFT       (0U)
63503 #define NETC_PORT_PBPMCR1_IPV4_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR1_IPV4_INDEX_SHIFT)) & NETC_PORT_PBPMCR1_IPV4_INDEX_MASK)
63504 
63505 #define NETC_PORT_PBPMCR1_IPV5_INDEX_MASK        (0xFF00U)
63506 #define NETC_PORT_PBPMCR1_IPV5_INDEX_SHIFT       (8U)
63507 #define NETC_PORT_PBPMCR1_IPV5_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR1_IPV5_INDEX_SHIFT)) & NETC_PORT_PBPMCR1_IPV5_INDEX_MASK)
63508 
63509 #define NETC_PORT_PBPMCR1_IPV6_INDEX_MASK        (0xFF0000U)
63510 #define NETC_PORT_PBPMCR1_IPV6_INDEX_SHIFT       (16U)
63511 #define NETC_PORT_PBPMCR1_IPV6_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR1_IPV6_INDEX_SHIFT)) & NETC_PORT_PBPMCR1_IPV6_INDEX_MASK)
63512 
63513 #define NETC_PORT_PBPMCR1_IPV7_INDEX_MASK        (0xFF000000U)
63514 #define NETC_PORT_PBPMCR1_IPV7_INDEX_SHIFT       (24U)
63515 #define NETC_PORT_PBPMCR1_IPV7_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PBPMCR1_IPV7_INDEX_SHIFT)) & NETC_PORT_PBPMCR1_IPV7_INDEX_MASK)
63516 /*! @} */
63517 
63518 /*! @name PPCPDEIMR - Port PCP DEI mapping register */
63519 /*! @{ */
63520 
63521 #define NETC_PORT_PPCPDEIMR_IPCPMP_MASK          (0xFU)
63522 #define NETC_PORT_PPCPDEIMR_IPCPMP_SHIFT         (0U)
63523 #define NETC_PORT_PPCPDEIMR_IPCPMP(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_IPCPMP_SHIFT)) & NETC_PORT_PPCPDEIMR_IPCPMP_MASK)
63524 
63525 #define NETC_PORT_PPCPDEIMR_IPCPMPV_MASK         (0x80U)
63526 #define NETC_PORT_PPCPDEIMR_IPCPMPV_SHIFT        (7U)
63527 /*! IPCPMPV
63528  *  0b0..Ingress PCP to PCP Mapping Profile is not valid.
63529  *  0b1..Ingress frame modification of outer VLAN tag's PCP value is mapped to a new value based on IPCPMP instance
63530  */
63531 #define NETC_PORT_PPCPDEIMR_IPCPMPV(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_IPCPMPV_SHIFT)) & NETC_PORT_PPCPDEIMR_IPCPMPV_MASK)
63532 
63533 #define NETC_PORT_PPCPDEIMR_EPCPMP_MASK          (0xF00U)
63534 #define NETC_PORT_PPCPDEIMR_EPCPMP_SHIFT         (8U)
63535 #define NETC_PORT_PPCPDEIMR_EPCPMP(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_EPCPMP_SHIFT)) & NETC_PORT_PPCPDEIMR_EPCPMP_MASK)
63536 
63537 #define NETC_PORT_PPCPDEIMR_EPCPMPV_MASK         (0x8000U)
63538 #define NETC_PORT_PPCPDEIMR_EPCPMPV_SHIFT        (15U)
63539 /*! EPCPMPV
63540  *  0b0..Egress PCP to PCP Mapping Profile is not valid.
63541  *  0b1..Egress frame modification of outer VLAN tag's PCP value is mapped to a new value based on EPCPMP instance.
63542  */
63543 #define NETC_PORT_PPCPDEIMR_EPCPMPV(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_EPCPMPV_SHIFT)) & NETC_PORT_PPCPDEIMR_EPCPMPV_MASK)
63544 
63545 #define NETC_PORT_PPCPDEIMR_DR0DEI_MASK          (0x10000U)
63546 #define NETC_PORT_PPCPDEIMR_DR0DEI_SHIFT         (16U)
63547 #define NETC_PORT_PPCPDEIMR_DR0DEI(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DR0DEI_SHIFT)) & NETC_PORT_PPCPDEIMR_DR0DEI_MASK)
63548 
63549 #define NETC_PORT_PPCPDEIMR_DR1DEI_MASK          (0x20000U)
63550 #define NETC_PORT_PPCPDEIMR_DR1DEI_SHIFT         (17U)
63551 #define NETC_PORT_PPCPDEIMR_DR1DEI(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DR1DEI_SHIFT)) & NETC_PORT_PPCPDEIMR_DR1DEI_MASK)
63552 
63553 #define NETC_PORT_PPCPDEIMR_DR2DEI_MASK          (0x40000U)
63554 #define NETC_PORT_PPCPDEIMR_DR2DEI_SHIFT         (18U)
63555 #define NETC_PORT_PPCPDEIMR_DR2DEI(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DR2DEI_SHIFT)) & NETC_PORT_PPCPDEIMR_DR2DEI_MASK)
63556 
63557 #define NETC_PORT_PPCPDEIMR_DR3DEI_MASK          (0x80000U)
63558 #define NETC_PORT_PPCPDEIMR_DR3DEI_SHIFT         (19U)
63559 #define NETC_PORT_PPCPDEIMR_DR3DEI(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DR3DEI_SHIFT)) & NETC_PORT_PPCPDEIMR_DR3DEI_MASK)
63560 
63561 #define NETC_PORT_PPCPDEIMR_DRME_MASK            (0x100000U)
63562 #define NETC_PORT_PPCPDEIMR_DRME_SHIFT           (20U)
63563 /*! DRME
63564  *  0b0..Preserve the DR value in the outer VLAN.
63565  *  0b1..Update DR value in the outer VLAN based on DEnDEI field.
63566  */
63567 #define NETC_PORT_PPCPDEIMR_DRME(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCPDEIMR_DRME_SHIFT)) & NETC_PORT_PPCPDEIMR_DRME_MASK)
63568 /*! @} */
63569 
63570 /*! @name PMCR - Port mirror configuration register */
63571 /*! @{ */
63572 
63573 #define NETC_PORT_PMCR_IMIRE_MASK                (0x1U)
63574 #define NETC_PORT_PMCR_IMIRE_SHIFT               (0U)
63575 #define NETC_PORT_PMCR_IMIRE(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCR_IMIRE_SHIFT)) & NETC_PORT_PMCR_IMIRE_MASK)
63576 /*! @} */
63577 
63578 /*! @name PCTFCR - Port cut through forwarding configuration register */
63579 /*! @{ */
63580 
63581 #define NETC_PORT_PCTFCR_ICTS_MASK               (0x1U)
63582 #define NETC_PORT_PCTFCR_ICTS_SHIFT              (0U)
63583 #define NETC_PORT_PCTFCR_ICTS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCTFCR_ICTS_SHIFT)) & NETC_PORT_PCTFCR_ICTS_MASK)
63584 
63585 #define NETC_PORT_PCTFCR_ECTS_MASK               (0x2U)
63586 #define NETC_PORT_PCTFCR_ECTS_SHIFT              (1U)
63587 #define NETC_PORT_PCTFCR_ECTS(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCTFCR_ECTS_SHIFT)) & NETC_PORT_PCTFCR_ECTS_MASK)
63588 /*! @} */
63589 
63590 /*! @name PLANIDCR - Port LANID configuration register */
63591 /*! @{ */
63592 
63593 #define NETC_PORT_PLANIDCR_LANID_MASK            (0xFU)
63594 #define NETC_PORT_PLANIDCR_LANID_SHIFT           (0U)
63595 /*! LANID - LAN Identifier */
63596 #define NETC_PORT_PLANIDCR_LANID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PLANIDCR_LANID_SHIFT)) & NETC_PORT_PLANIDCR_LANID_MASK)
63597 /*! @} */
63598 
63599 /*! @name PISIDCR - Port ingress stream identification configuration register */
63600 /*! @{ */
63601 
63602 #define NETC_PORT_PISIDCR_KCPAIR_MASK            (0x1U)
63603 #define NETC_PORT_PISIDCR_KCPAIR_SHIFT           (0U)
63604 #define NETC_PORT_PISIDCR_KCPAIR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KCPAIR_SHIFT)) & NETC_PORT_PISIDCR_KCPAIR_MASK)
63605 
63606 #define NETC_PORT_PISIDCR_KC0EN_MASK             (0x2U)
63607 #define NETC_PORT_PISIDCR_KC0EN_SHIFT            (1U)
63608 /*! KC0EN - Key Construction 0 Enable */
63609 #define NETC_PORT_PISIDCR_KC0EN(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KC0EN_SHIFT)) & NETC_PORT_PISIDCR_KC0EN_MASK)
63610 
63611 #define NETC_PORT_PISIDCR_KC1EN_MASK             (0x4U)
63612 #define NETC_PORT_PISIDCR_KC1EN_SHIFT            (2U)
63613 /*! KC1EN - Key Construction 1 Enable */
63614 #define NETC_PORT_PISIDCR_KC1EN(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KC1EN_SHIFT)) & NETC_PORT_PISIDCR_KC1EN_MASK)
63615 
63616 #define NETC_PORT_PISIDCR_ISEID_MASK             (0xFFFF0000U)
63617 #define NETC_PORT_PISIDCR_ISEID_SHIFT            (16U)
63618 #define NETC_PORT_PISIDCR_ISEID(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_ISEID_SHIFT)) & NETC_PORT_PISIDCR_ISEID_MASK)
63619 /*! @} */
63620 
63621 /*! @name PFMCR - Port frame modification configuration register */
63622 /*! @{ */
63623 
63624 #define NETC_PORT_PFMCR_FMMA_MASK                (0x1U)
63625 #define NETC_PORT_PFMCR_FMMA_SHIFT               (0U)
63626 /*! FMMA - Frame Modification Misconfiguration Action
63627  *  0b0..Discard the frame and counted against the port's Tx discard count register (PTXDCR) along with the
63628  *       setting of the Frame Modification Misconfiguration Discard Reason (FMMDR) flag to 1 in the port's Tx discard
63629  *       count reason register 0 (PTXDCRR0).
63630  *  0b1..Transmit the frame without performing any of the ingress and egress frame modification actions specified.
63631  */
63632 #define NETC_PORT_PFMCR_FMMA(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFMCR_FMMA_SHIFT)) & NETC_PORT_PFMCR_FMMA_MASK)
63633 /*! @} */
63634 
63635 /*! @name PIPV2QMR0 - Port IPV to queue mapping register 0 */
63636 /*! @{ */
63637 
63638 #define NETC_PORT_PIPV2QMR0_IPV0_Q_MASK          (0xFU)
63639 #define NETC_PORT_PIPV2QMR0_IPV0_Q_SHIFT         (0U)
63640 #define NETC_PORT_PIPV2QMR0_IPV0_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV0_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV0_Q_MASK)
63641 
63642 #define NETC_PORT_PIPV2QMR0_IPV1_Q_MASK          (0xF0U)
63643 #define NETC_PORT_PIPV2QMR0_IPV1_Q_SHIFT         (4U)
63644 #define NETC_PORT_PIPV2QMR0_IPV1_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV1_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV1_Q_MASK)
63645 
63646 #define NETC_PORT_PIPV2QMR0_IPV2_Q_MASK          (0xF00U)
63647 #define NETC_PORT_PIPV2QMR0_IPV2_Q_SHIFT         (8U)
63648 #define NETC_PORT_PIPV2QMR0_IPV2_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV2_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV2_Q_MASK)
63649 
63650 #define NETC_PORT_PIPV2QMR0_IPV3_Q_MASK          (0xF000U)
63651 #define NETC_PORT_PIPV2QMR0_IPV3_Q_SHIFT         (12U)
63652 #define NETC_PORT_PIPV2QMR0_IPV3_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV3_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV3_Q_MASK)
63653 
63654 #define NETC_PORT_PIPV2QMR0_IPV4_Q_MASK          (0xF0000U)
63655 #define NETC_PORT_PIPV2QMR0_IPV4_Q_SHIFT         (16U)
63656 #define NETC_PORT_PIPV2QMR0_IPV4_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV4_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV4_Q_MASK)
63657 
63658 #define NETC_PORT_PIPV2QMR0_IPV5_Q_MASK          (0xF00000U)
63659 #define NETC_PORT_PIPV2QMR0_IPV5_Q_SHIFT         (20U)
63660 #define NETC_PORT_PIPV2QMR0_IPV5_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV5_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV5_Q_MASK)
63661 
63662 #define NETC_PORT_PIPV2QMR0_IPV6_Q_MASK          (0xF000000U)
63663 #define NETC_PORT_PIPV2QMR0_IPV6_Q_SHIFT         (24U)
63664 #define NETC_PORT_PIPV2QMR0_IPV6_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV6_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV6_Q_MASK)
63665 
63666 #define NETC_PORT_PIPV2QMR0_IPV7_Q_MASK          (0xF0000000U)
63667 #define NETC_PORT_PIPV2QMR0_IPV7_Q_SHIFT         (28U)
63668 #define NETC_PORT_PIPV2QMR0_IPV7_Q(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPV2QMR0_IPV7_Q_SHIFT)) & NETC_PORT_PIPV2QMR0_IPV7_Q_MASK)
63669 /*! @} */
63670 
63671 /*! @name PTCMINLR - Port time capture minimum latency register */
63672 /*! @{ */
63673 
63674 #define NETC_PORT_PTCMINLR_LATENCY_MASK          (0x3FFFFFFFU)
63675 #define NETC_PORT_PTCMINLR_LATENCY_SHIFT         (0U)
63676 #define NETC_PORT_PTCMINLR_LATENCY(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCMINLR_LATENCY_SHIFT)) & NETC_PORT_PTCMINLR_LATENCY_MASK)
63677 
63678 #define NETC_PORT_PTCMINLR_COUNT_MASK            (0xC0000000U)
63679 #define NETC_PORT_PTCMINLR_COUNT_SHIFT           (30U)
63680 #define NETC_PORT_PTCMINLR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCMINLR_COUNT_SHIFT)) & NETC_PORT_PTCMINLR_COUNT_MASK)
63681 /*! @} */
63682 
63683 /*! @name PTCMAXLR - Port time capture maximum latency register */
63684 /*! @{ */
63685 
63686 #define NETC_PORT_PTCMAXLR_LATENCY_MASK          (0x3FFFFFFFU)
63687 #define NETC_PORT_PTCMAXLR_LATENCY_SHIFT         (0U)
63688 #define NETC_PORT_PTCMAXLR_LATENCY(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCMAXLR_LATENCY_SHIFT)) & NETC_PORT_PTCMAXLR_LATENCY_MASK)
63689 /*! @} */
63690 
63691 /*! @name BPCR - Bridge port configuration register */
63692 /*! @{ */
63693 
63694 #define NETC_PORT_BPCR_DYN_LIMIT_MASK            (0xFFFFU)
63695 #define NETC_PORT_BPCR_DYN_LIMIT_SHIFT           (0U)
63696 /*! DYN_LIMIT - Dynamic Limit */
63697 #define NETC_PORT_BPCR_DYN_LIMIT(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_DYN_LIMIT_SHIFT)) & NETC_PORT_BPCR_DYN_LIMIT_MASK)
63698 
63699 #define NETC_PORT_BPCR_UUCASTE_MASK              (0x1000000U)
63700 #define NETC_PORT_BPCR_UUCASTE_SHIFT             (24U)
63701 /*! UUCASTE - Unknown Unicast Storm Control Enable
63702  *  0b0..Disabled
63703  *  0b1..Enabled
63704  */
63705 #define NETC_PORT_BPCR_UUCASTE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_UUCASTE_SHIFT)) & NETC_PORT_BPCR_UUCASTE_MASK)
63706 
63707 #define NETC_PORT_BPCR_UMCASTE_MASK              (0x2000000U)
63708 #define NETC_PORT_BPCR_UMCASTE_SHIFT             (25U)
63709 /*! UMCASTE - Unknown Multicast Storm Control Enable
63710  *  0b0..Disabled
63711  *  0b1..Enabled
63712  */
63713 #define NETC_PORT_BPCR_UMCASTE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_UMCASTE_SHIFT)) & NETC_PORT_BPCR_UMCASTE_MASK)
63714 
63715 #define NETC_PORT_BPCR_MCASTE_MASK               (0x4000000U)
63716 #define NETC_PORT_BPCR_MCASTE_SHIFT              (26U)
63717 /*! MCASTE - Multicast Storm Control Enable
63718  *  0b0..Disabled
63719  *  0b1..Enabled
63720  */
63721 #define NETC_PORT_BPCR_MCASTE(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_MCASTE_SHIFT)) & NETC_PORT_BPCR_MCASTE_MASK)
63722 
63723 #define NETC_PORT_BPCR_BCASTE_MASK               (0x8000000U)
63724 #define NETC_PORT_BPCR_BCASTE_SHIFT              (27U)
63725 /*! BCASTE - Broadcast Storm Control Enable
63726  *  0b0..Disabled
63727  *  0b1..Enabled
63728  */
63729 #define NETC_PORT_BPCR_BCASTE(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_BCASTE_SHIFT)) & NETC_PORT_BPCR_BCASTE_MASK)
63730 
63731 #define NETC_PORT_BPCR_STAMVD_MASK               (0x10000000U)
63732 #define NETC_PORT_BPCR_STAMVD_SHIFT              (28U)
63733 /*! STAMVD - Station Move Disallow
63734  *  0b0..Allowed
63735  *  0b1..Disallowed. A received frame for which a MAC station move is detected, will be discarded.
63736  */
63737 #define NETC_PORT_BPCR_STAMVD(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_STAMVD_SHIFT)) & NETC_PORT_BPCR_STAMVD_MASK)
63738 
63739 #define NETC_PORT_BPCR_SRCPRND_MASK              (0x20000000U)
63740 #define NETC_PORT_BPCR_SRCPRND_SHIFT             (29U)
63741 /*! SRCPRND - Source Port Pruning Disable
63742  *  0b0..Enabled
63743  *  0b1..Disabled
63744  */
63745 #define NETC_PORT_BPCR_SRCPRND(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPCR_SRCPRND_SHIFT)) & NETC_PORT_BPCR_SRCPRND_MASK)
63746 /*! @} */
63747 
63748 /*! @name BPDVR - Bridge port default VLAN register */
63749 /*! @{ */
63750 
63751 #define NETC_PORT_BPDVR_VID_MASK                 (0xFFFU)
63752 #define NETC_PORT_BPDVR_VID_SHIFT                (0U)
63753 #define NETC_PORT_BPDVR_VID(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_VID_SHIFT)) & NETC_PORT_BPDVR_VID_MASK)
63754 
63755 #define NETC_PORT_BPDVR_DEI_MASK                 (0x1000U)
63756 #define NETC_PORT_BPDVR_DEI_SHIFT                (12U)
63757 #define NETC_PORT_BPDVR_DEI(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_DEI_SHIFT)) & NETC_PORT_BPDVR_DEI_MASK)
63758 
63759 #define NETC_PORT_BPDVR_PCP_MASK                 (0xE000U)
63760 #define NETC_PORT_BPDVR_PCP_SHIFT                (13U)
63761 #define NETC_PORT_BPDVR_PCP(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_PCP_SHIFT)) & NETC_PORT_BPDVR_PCP_MASK)
63762 
63763 #define NETC_PORT_BPDVR_TPID_MASK                (0x10000U)
63764 #define NETC_PORT_BPDVR_TPID_SHIFT               (16U)
63765 #define NETC_PORT_BPDVR_TPID(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_TPID_SHIFT)) & NETC_PORT_BPDVR_TPID_MASK)
63766 
63767 #define NETC_PORT_BPDVR_RXTAGA_MASK              (0xF00000U)
63768 #define NETC_PORT_BPDVR_RXTAGA_SHIFT             (20U)
63769 #define NETC_PORT_BPDVR_RXTAGA(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_RXTAGA_SHIFT)) & NETC_PORT_BPDVR_RXTAGA_MASK)
63770 
63771 #define NETC_PORT_BPDVR_RXVAM_MASK               (0x1000000U)
63772 #define NETC_PORT_BPDVR_RXVAM_SHIFT              (24U)
63773 #define NETC_PORT_BPDVR_RXVAM(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_RXVAM_SHIFT)) & NETC_PORT_BPDVR_RXVAM_MASK)
63774 
63775 #define NETC_PORT_BPDVR_TXTAGA_MASK              (0x6000000U)
63776 #define NETC_PORT_BPDVR_TXTAGA_SHIFT             (25U)
63777 #define NETC_PORT_BPDVR_TXTAGA(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDVR_TXTAGA_SHIFT)) & NETC_PORT_BPDVR_TXTAGA_MASK)
63778 /*! @} */
63779 
63780 /*! @name BPSTGSR - Bridge port spanning tree group state register */
63781 /*! @{ */
63782 
63783 #define NETC_PORT_BPSTGSR_STG_STATE0_MASK        (0x3U)
63784 #define NETC_PORT_BPSTGSR_STG_STATE0_SHIFT       (0U)
63785 #define NETC_PORT_BPSTGSR_STG_STATE0(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE0_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE0_MASK)
63786 
63787 #define NETC_PORT_BPSTGSR_STG_STATE1_MASK        (0xCU)
63788 #define NETC_PORT_BPSTGSR_STG_STATE1_SHIFT       (2U)
63789 #define NETC_PORT_BPSTGSR_STG_STATE1(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE1_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE1_MASK)
63790 
63791 #define NETC_PORT_BPSTGSR_STG_STATE2_MASK        (0x30U)
63792 #define NETC_PORT_BPSTGSR_STG_STATE2_SHIFT       (4U)
63793 #define NETC_PORT_BPSTGSR_STG_STATE2(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE2_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE2_MASK)
63794 
63795 #define NETC_PORT_BPSTGSR_STG_STATE3_MASK        (0xC0U)
63796 #define NETC_PORT_BPSTGSR_STG_STATE3_SHIFT       (6U)
63797 #define NETC_PORT_BPSTGSR_STG_STATE3(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE3_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE3_MASK)
63798 
63799 #define NETC_PORT_BPSTGSR_STG_STATE4_MASK        (0x300U)
63800 #define NETC_PORT_BPSTGSR_STG_STATE4_SHIFT       (8U)
63801 #define NETC_PORT_BPSTGSR_STG_STATE4(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE4_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE4_MASK)
63802 
63803 #define NETC_PORT_BPSTGSR_STG_STATE5_MASK        (0xC00U)
63804 #define NETC_PORT_BPSTGSR_STG_STATE5_SHIFT       (10U)
63805 #define NETC_PORT_BPSTGSR_STG_STATE5(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE5_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE5_MASK)
63806 
63807 #define NETC_PORT_BPSTGSR_STG_STATE6_MASK        (0x3000U)
63808 #define NETC_PORT_BPSTGSR_STG_STATE6_SHIFT       (12U)
63809 #define NETC_PORT_BPSTGSR_STG_STATE6(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE6_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE6_MASK)
63810 
63811 #define NETC_PORT_BPSTGSR_STG_STATE7_MASK        (0xC000U)
63812 #define NETC_PORT_BPSTGSR_STG_STATE7_SHIFT       (14U)
63813 #define NETC_PORT_BPSTGSR_STG_STATE7(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE7_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE7_MASK)
63814 
63815 #define NETC_PORT_BPSTGSR_STG_STATE8_MASK        (0x30000U)
63816 #define NETC_PORT_BPSTGSR_STG_STATE8_SHIFT       (16U)
63817 #define NETC_PORT_BPSTGSR_STG_STATE8(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE8_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE8_MASK)
63818 
63819 #define NETC_PORT_BPSTGSR_STG_STATE9_MASK        (0xC0000U)
63820 #define NETC_PORT_BPSTGSR_STG_STATE9_SHIFT       (18U)
63821 #define NETC_PORT_BPSTGSR_STG_STATE9(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE9_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE9_MASK)
63822 
63823 #define NETC_PORT_BPSTGSR_STG_STATE10_MASK       (0x300000U)
63824 #define NETC_PORT_BPSTGSR_STG_STATE10_SHIFT      (20U)
63825 #define NETC_PORT_BPSTGSR_STG_STATE10(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE10_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE10_MASK)
63826 
63827 #define NETC_PORT_BPSTGSR_STG_STATE11_MASK       (0xC00000U)
63828 #define NETC_PORT_BPSTGSR_STG_STATE11_SHIFT      (22U)
63829 #define NETC_PORT_BPSTGSR_STG_STATE11(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE11_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE11_MASK)
63830 
63831 #define NETC_PORT_BPSTGSR_STG_STATE12_MASK       (0x3000000U)
63832 #define NETC_PORT_BPSTGSR_STG_STATE12_SHIFT      (24U)
63833 #define NETC_PORT_BPSTGSR_STG_STATE12(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE12_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE12_MASK)
63834 
63835 #define NETC_PORT_BPSTGSR_STG_STATE13_MASK       (0xC000000U)
63836 #define NETC_PORT_BPSTGSR_STG_STATE13_SHIFT      (26U)
63837 #define NETC_PORT_BPSTGSR_STG_STATE13(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE13_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE13_MASK)
63838 
63839 #define NETC_PORT_BPSTGSR_STG_STATE14_MASK       (0x30000000U)
63840 #define NETC_PORT_BPSTGSR_STG_STATE14_SHIFT      (28U)
63841 #define NETC_PORT_BPSTGSR_STG_STATE14(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE14_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE14_MASK)
63842 
63843 #define NETC_PORT_BPSTGSR_STG_STATE15_MASK       (0xC0000000U)
63844 #define NETC_PORT_BPSTGSR_STG_STATE15_SHIFT      (30U)
63845 #define NETC_PORT_BPSTGSR_STG_STATE15(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSTGSR_STG_STATE15_SHIFT)) & NETC_PORT_BPSTGSR_STG_STATE15_MASK)
63846 /*! @} */
63847 
63848 /*! @name BPSCR0 - Bridge port storm control register 0 */
63849 /*! @{ */
63850 
63851 #define NETC_PORT_BPSCR0_UUCASTRPEID_MASK        (0xFFFU)
63852 #define NETC_PORT_BPSCR0_UUCASTRPEID_SHIFT       (0U)
63853 #define NETC_PORT_BPSCR0_UUCASTRPEID(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSCR0_UUCASTRPEID_SHIFT)) & NETC_PORT_BPSCR0_UUCASTRPEID_MASK)
63854 
63855 #define NETC_PORT_BPSCR0_BCASTRPEID_MASK         (0xFFF0000U)
63856 #define NETC_PORT_BPSCR0_BCASTRPEID_SHIFT        (16U)
63857 #define NETC_PORT_BPSCR0_BCASTRPEID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSCR0_BCASTRPEID_SHIFT)) & NETC_PORT_BPSCR0_BCASTRPEID_MASK)
63858 /*! @} */
63859 
63860 /*! @name BPSCR1 - Bridge port storm control register 1 */
63861 /*! @{ */
63862 
63863 #define NETC_PORT_BPSCR1_MCASTRPEID_MASK         (0xFFFU)
63864 #define NETC_PORT_BPSCR1_MCASTRPEID_SHIFT        (0U)
63865 #define NETC_PORT_BPSCR1_MCASTRPEID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSCR1_MCASTRPEID_SHIFT)) & NETC_PORT_BPSCR1_MCASTRPEID_MASK)
63866 
63867 #define NETC_PORT_BPSCR1_UMCASTRPEID_MASK        (0xFFF0000U)
63868 #define NETC_PORT_BPSCR1_UMCASTRPEID_SHIFT       (16U)
63869 #define NETC_PORT_BPSCR1_UMCASTRPEID(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPSCR1_UMCASTRPEID_SHIFT)) & NETC_PORT_BPSCR1_UMCASTRPEID_MASK)
63870 /*! @} */
63871 
63872 /*! @name BPOR - Bridge port operational register */
63873 /*! @{ */
63874 
63875 #define NETC_PORT_BPOR_NUM_DYN_MASK              (0xFFFFU)
63876 #define NETC_PORT_BPOR_NUM_DYN_SHIFT             (0U)
63877 #define NETC_PORT_BPOR_NUM_DYN(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPOR_NUM_DYN_SHIFT)) & NETC_PORT_BPOR_NUM_DYN_MASK)
63878 /*! @} */
63879 
63880 /*! @name BPDCR - Bridge port discard count register */
63881 /*! @{ */
63882 
63883 #define NETC_PORT_BPDCR_COUNT_MASK               (0xFFFFFFFFU)
63884 #define NETC_PORT_BPDCR_COUNT_SHIFT              (0U)
63885 #define NETC_PORT_BPDCR_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCR_COUNT_SHIFT)) & NETC_PORT_BPDCR_COUNT_MASK)
63886 /*! @} */
63887 
63888 /*! @name BPDCRR0 - Bridge port discard count reason register 0 */
63889 /*! @{ */
63890 
63891 #define NETC_PORT_BPDCRR0_BPACDR_MASK            (0x1U)
63892 #define NETC_PORT_BPDCRR0_BPACDR_SHIFT           (0U)
63893 #define NETC_PORT_BPDCRR0_BPACDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_BPACDR_SHIFT)) & NETC_PORT_BPDCRR0_BPACDR_MASK)
63894 
63895 #define NETC_PORT_BPDCRR0_ISTGSDR_MASK           (0x2U)
63896 #define NETC_PORT_BPDCRR0_ISTGSDR_SHIFT          (1U)
63897 #define NETC_PORT_BPDCRR0_ISTGSDR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_ISTGSDR_SHIFT)) & NETC_PORT_BPDCRR0_ISTGSDR_MASK)
63898 
63899 #define NETC_PORT_BPDCRR0_BPVFLTDR_MASK          (0x4U)
63900 #define NETC_PORT_BPDCRR0_BPVFLTDR_SHIFT         (2U)
63901 #define NETC_PORT_BPDCRR0_BPVFLTDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_BPVFLTDR_SHIFT)) & NETC_PORT_BPDCRR0_BPVFLTDR_MASK)
63902 
63903 #define NETC_PORT_BPDCRR0_MACLNFDR_MASK          (0x8U)
63904 #define NETC_PORT_BPDCRR0_MACLNFDR_SHIFT         (3U)
63905 #define NETC_PORT_BPDCRR0_MACLNFDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_MACLNFDR_SHIFT)) & NETC_PORT_BPDCRR0_MACLNFDR_MASK)
63906 
63907 #define NETC_PORT_BPDCRR0_STAMVDDR_MASK          (0x80U)
63908 #define NETC_PORT_BPDCRR0_STAMVDDR_SHIFT         (7U)
63909 #define NETC_PORT_BPDCRR0_STAMVDDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_STAMVDDR_SHIFT)) & NETC_PORT_BPDCRR0_STAMVDDR_MASK)
63910 
63911 #define NETC_PORT_BPDCRR0_MACFDDDR_MASK          (0x100U)
63912 #define NETC_PORT_BPDCRR0_MACFDDDR_SHIFT         (8U)
63913 #define NETC_PORT_BPDCRR0_MACFDDDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_MACFDDDR_SHIFT)) & NETC_PORT_BPDCRR0_MACFDDDR_MASK)
63914 
63915 #define NETC_PORT_BPDCRR0_NODESTDR_MASK          (0x200U)
63916 #define NETC_PORT_BPDCRR0_NODESTDR_SHIFT         (9U)
63917 #define NETC_PORT_BPDCRR0_NODESTDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_NODESTDR_SHIFT)) & NETC_PORT_BPDCRR0_NODESTDR_MASK)
63918 
63919 #define NETC_PORT_BPDCRR0_IPMFDR_MASK            (0x400U)
63920 #define NETC_PORT_BPDCRR0_IPMFDR_SHIFT           (10U)
63921 #define NETC_PORT_BPDCRR0_IPMFDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_IPMFDR_SHIFT)) & NETC_PORT_BPDCRR0_IPMFDR_MASK)
63922 
63923 #define NETC_PORT_BPDCRR0_UFMMDR_MASK            (0x800U)
63924 #define NETC_PORT_BPDCRR0_UFMMDR_SHIFT           (11U)
63925 #define NETC_PORT_BPDCRR0_UFMMDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_UFMMDR_SHIFT)) & NETC_PORT_BPDCRR0_UFMMDR_MASK)
63926 
63927 #define NETC_PORT_BPDCRR0_MISCDR_MASK            (0x1000U)
63928 #define NETC_PORT_BPDCRR0_MISCDR_SHIFT           (12U)
63929 #define NETC_PORT_BPDCRR0_MISCDR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_MISCDR_SHIFT)) & NETC_PORT_BPDCRR0_MISCDR_MASK)
63930 
63931 #define NETC_PORT_BPDCRR0_STRMCTRLDR_MASK        (0x2000U)
63932 #define NETC_PORT_BPDCRR0_STRMCTRLDR_SHIFT       (13U)
63933 /*! STRMCTRLDR - Discard due to Storm Control Policer Discard Reason */
63934 #define NETC_PORT_BPDCRR0_STRMCTRLDR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR0_STRMCTRLDR_SHIFT)) & NETC_PORT_BPDCRR0_STRMCTRLDR_MASK)
63935 /*! @} */
63936 
63937 /*! @name BPDCRR1 - Bridge port discard count reason register 1 */
63938 /*! @{ */
63939 
63940 #define NETC_PORT_BPDCRR1_ENTRYID_MASK           (0x7FFFFFFU)
63941 #define NETC_PORT_BPDCRR1_ENTRYID_SHIFT          (0U)
63942 #define NETC_PORT_BPDCRR1_ENTRYID(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR1_ENTRYID_SHIFT)) & NETC_PORT_BPDCRR1_ENTRYID_MASK)
63943 
63944 #define NETC_PORT_BPDCRR1_TT_MASK                (0xF0000000U)
63945 #define NETC_PORT_BPDCRR1_TT_SHIFT               (28U)
63946 #define NETC_PORT_BPDCRR1_TT(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPDCRR1_TT_SHIFT)) & NETC_PORT_BPDCRR1_TT_MASK)
63947 /*! @} */
63948 
63949 /*! @name BPMLFSR - Bridge port MAC learning failure status register */
63950 /*! @{ */
63951 
63952 #define NETC_PORT_BPMLFSR_BPMLLRFR_MASK          (0x1U)
63953 #define NETC_PORT_BPMLFSR_BPMLLRFR_SHIFT         (0U)
63954 /*! BPMLLRFR - Bridge Port MAC Learn Limit Reached Failure Reason */
63955 #define NETC_PORT_BPMLFSR_BPMLLRFR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPMLFSR_BPMLLRFR_SHIFT)) & NETC_PORT_BPMLFSR_BPMLLRFR_MASK)
63956 
63957 #define NETC_PORT_BPMLFSR_FFDBTRFR_MASK          (0x2U)
63958 #define NETC_PORT_BPMLFSR_FFDBTRFR_SHIFT         (1U)
63959 /*! FFDBTRFR - Full FDB Table Reached Failure Reason */
63960 #define NETC_PORT_BPMLFSR_FFDBTRFR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPMLFSR_FFDBTRFR_SHIFT)) & NETC_PORT_BPMLFSR_FFDBTRFR_MASK)
63961 
63962 #define NETC_PORT_BPMLFSR_HCCLRFR_MASK           (0x4U)
63963 #define NETC_PORT_BPMLFSR_HCCLRFR_SHIFT          (2U)
63964 /*! HCCLRFR - Hash Collision chain limit Reached Failure Reason */
63965 #define NETC_PORT_BPMLFSR_HCCLRFR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PORT_BPMLFSR_HCCLRFR_SHIFT)) & NETC_PORT_BPMLFSR_HCCLRFR_MASK)
63966 /*! @} */
63967 
63968 
63969 /*!
63970  * @}
63971  */ /* end of group NETC_PORT_Register_Masks */
63972 
63973 
63974 /* NETC_PORT - Peripheral instance base addresses */
63975 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
63976   /** Peripheral ENETC0_PORT base address */
63977   #define ENETC0_PORT_BASE                         (0x70B14000u)
63978   /** Peripheral ENETC0_PORT base address */
63979   #define ENETC0_PORT_BASE_NS                      (0x60B14000u)
63980   /** Peripheral ENETC0_PORT base pointer */
63981   #define ENETC0_PORT                              ((NETC_PORT_Type *)ENETC0_PORT_BASE)
63982   /** Peripheral ENETC0_PORT base pointer */
63983   #define ENETC0_PORT_NS                           ((NETC_PORT_Type *)ENETC0_PORT_BASE_NS)
63984   /** Peripheral ENETC1_PORT base address */
63985   #define ENETC1_PORT_BASE                         (0x70B54000u)
63986   /** Peripheral ENETC1_PORT base address */
63987   #define ENETC1_PORT_BASE_NS                      (0x60B54000u)
63988   /** Peripheral ENETC1_PORT base pointer */
63989   #define ENETC1_PORT                              ((NETC_PORT_Type *)ENETC1_PORT_BASE)
63990   /** Peripheral ENETC1_PORT base pointer */
63991   #define ENETC1_PORT_NS                           ((NETC_PORT_Type *)ENETC1_PORT_BASE_NS)
63992   /** Peripheral SW0_PORT0 base address */
63993   #define SW0_PORT0_BASE                           (0x70A04000u)
63994   /** Peripheral SW0_PORT0 base address */
63995   #define SW0_PORT0_BASE_NS                        (0x60A04000u)
63996   /** Peripheral SW0_PORT0 base pointer */
63997   #define SW0_PORT0                                ((NETC_PORT_Type *)SW0_PORT0_BASE)
63998   /** Peripheral SW0_PORT0 base pointer */
63999   #define SW0_PORT0_NS                             ((NETC_PORT_Type *)SW0_PORT0_BASE_NS)
64000   /** Peripheral SW0_PORT1 base address */
64001   #define SW0_PORT1_BASE                           (0x70A08000u)
64002   /** Peripheral SW0_PORT1 base address */
64003   #define SW0_PORT1_BASE_NS                        (0x60A08000u)
64004   /** Peripheral SW0_PORT1 base pointer */
64005   #define SW0_PORT1                                ((NETC_PORT_Type *)SW0_PORT1_BASE)
64006   /** Peripheral SW0_PORT1 base pointer */
64007   #define SW0_PORT1_NS                             ((NETC_PORT_Type *)SW0_PORT1_BASE_NS)
64008   /** Peripheral SW0_PORT2 base address */
64009   #define SW0_PORT2_BASE                           (0x70A0C000u)
64010   /** Peripheral SW0_PORT2 base address */
64011   #define SW0_PORT2_BASE_NS                        (0x60A0C000u)
64012   /** Peripheral SW0_PORT2 base pointer */
64013   #define SW0_PORT2                                ((NETC_PORT_Type *)SW0_PORT2_BASE)
64014   /** Peripheral SW0_PORT2 base pointer */
64015   #define SW0_PORT2_NS                             ((NETC_PORT_Type *)SW0_PORT2_BASE_NS)
64016   /** Peripheral SW0_PORT3 base address */
64017   #define SW0_PORT3_BASE                           (0x70A10000u)
64018   /** Peripheral SW0_PORT3 base address */
64019   #define SW0_PORT3_BASE_NS                        (0x60A10000u)
64020   /** Peripheral SW0_PORT3 base pointer */
64021   #define SW0_PORT3                                ((NETC_PORT_Type *)SW0_PORT3_BASE)
64022   /** Peripheral SW0_PORT3 base pointer */
64023   #define SW0_PORT3_NS                             ((NETC_PORT_Type *)SW0_PORT3_BASE_NS)
64024   /** Peripheral SW0_PORT4 base address */
64025   #define SW0_PORT4_BASE                           (0x70A14000u)
64026   /** Peripheral SW0_PORT4 base address */
64027   #define SW0_PORT4_BASE_NS                        (0x60A14000u)
64028   /** Peripheral SW0_PORT4 base pointer */
64029   #define SW0_PORT4                                ((NETC_PORT_Type *)SW0_PORT4_BASE)
64030   /** Peripheral SW0_PORT4 base pointer */
64031   #define SW0_PORT4_NS                             ((NETC_PORT_Type *)SW0_PORT4_BASE_NS)
64032   /** Array initializer of NETC_PORT peripheral base addresses */
64033   #define NETC_PORT_BASE_ADDRS                     { ENETC0_PORT_BASE, ENETC1_PORT_BASE, SW0_PORT0_BASE, SW0_PORT1_BASE, SW0_PORT2_BASE, SW0_PORT3_BASE, SW0_PORT4_BASE }
64034   /** Array initializer of NETC_PORT peripheral base pointers */
64035   #define NETC_PORT_BASE_PTRS                      { ENETC0_PORT, ENETC1_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 }
64036   /** Array initializer of NETC_PORT peripheral base addresses */
64037   #define NETC_PORT_BASE_ADDRS_NS                  { ENETC0_PORT_BASE_NS, ENETC1_PORT_BASE_NS, SW0_PORT0_BASE_NS, SW0_PORT1_BASE_NS, SW0_PORT2_BASE_NS, SW0_PORT3_BASE_NS, SW0_PORT4_BASE_NS }
64038   /** Array initializer of NETC_PORT peripheral base pointers */
64039   #define NETC_PORT_BASE_PTRS_NS                   { ENETC0_PORT_NS, ENETC1_PORT_NS, SW0_PORT0_NS, SW0_PORT1_NS, SW0_PORT2_NS, SW0_PORT3_NS, SW0_PORT4_NS }
64040 #else
64041   /** Peripheral ENETC0_PORT base address */
64042   #define ENETC0_PORT_BASE                         (0x60B14000u)
64043   /** Peripheral ENETC0_PORT base pointer */
64044   #define ENETC0_PORT                              ((NETC_PORT_Type *)ENETC0_PORT_BASE)
64045   /** Peripheral ENETC1_PORT base address */
64046   #define ENETC1_PORT_BASE                         (0x60B54000u)
64047   /** Peripheral ENETC1_PORT base pointer */
64048   #define ENETC1_PORT                              ((NETC_PORT_Type *)ENETC1_PORT_BASE)
64049   /** Peripheral SW0_PORT0 base address */
64050   #define SW0_PORT0_BASE                           (0x60A04000u)
64051   /** Peripheral SW0_PORT0 base pointer */
64052   #define SW0_PORT0                                ((NETC_PORT_Type *)SW0_PORT0_BASE)
64053   /** Peripheral SW0_PORT1 base address */
64054   #define SW0_PORT1_BASE                           (0x60A08000u)
64055   /** Peripheral SW0_PORT1 base pointer */
64056   #define SW0_PORT1                                ((NETC_PORT_Type *)SW0_PORT1_BASE)
64057   /** Peripheral SW0_PORT2 base address */
64058   #define SW0_PORT2_BASE                           (0x60A0C000u)
64059   /** Peripheral SW0_PORT2 base pointer */
64060   #define SW0_PORT2                                ((NETC_PORT_Type *)SW0_PORT2_BASE)
64061   /** Peripheral SW0_PORT3 base address */
64062   #define SW0_PORT3_BASE                           (0x60A10000u)
64063   /** Peripheral SW0_PORT3 base pointer */
64064   #define SW0_PORT3                                ((NETC_PORT_Type *)SW0_PORT3_BASE)
64065   /** Peripheral SW0_PORT4 base address */
64066   #define SW0_PORT4_BASE                           (0x60A14000u)
64067   /** Peripheral SW0_PORT4 base pointer */
64068   #define SW0_PORT4                                ((NETC_PORT_Type *)SW0_PORT4_BASE)
64069   /** Array initializer of NETC_PORT peripheral base addresses */
64070   #define NETC_PORT_BASE_ADDRS                     { ENETC0_PORT_BASE, ENETC1_PORT_BASE, SW0_PORT0_BASE, SW0_PORT1_BASE, SW0_PORT2_BASE, SW0_PORT3_BASE, SW0_PORT4_BASE }
64071   /** Array initializer of NETC_PORT peripheral base pointers */
64072   #define NETC_PORT_BASE_PTRS                      { ENETC0_PORT, ENETC1_PORT, SW0_PORT0, SW0_PORT1, SW0_PORT2, SW0_PORT3, SW0_PORT4 }
64073 #endif
64074 
64075 /*!
64076  * @}
64077  */ /* end of group NETC_PORT_Peripheral_Access_Layer */
64078 
64079 
64080 /* ----------------------------------------------------------------------------
64081    -- NETC_PRIV Peripheral Access Layer
64082    ---------------------------------------------------------------------------- */
64083 
64084 /*!
64085  * @addtogroup NETC_PRIV_Peripheral_Access_Layer NETC_PRIV Peripheral Access Layer
64086  * @{
64087  */
64088 
64089 /** NETC_PRIV - Register Layout Typedef */
64090 typedef struct {
64091        uint8_t RESERVED_0[256];
64092   __IO uint32_t NETCRR;                            /**< NETC reset register, offset: 0x100 */
64093   __I  uint32_t NETCSR;                            /**< NETC status register, offset: 0x104 */
64094        uint8_t RESERVED_1[256];
64095   __IO uint32_t MEICR;                             /**< Memory Error Injection Config Register, offset: 0x208 */
64096        uint8_t RESERVED_2[3060];
64097   __IO uint32_t CMECR;                             /**< Correctable memory error configuration register, offset: 0xE00 */
64098   __IO uint32_t CMESR;                             /**< Correctable memory error status register, offset: 0xE04 */
64099        uint8_t RESERVED_3[4];
64100   __I  uint32_t CMECTR;                            /**< Correctable memory error count register, offset: 0xE0C */
64101        uint8_t RESERVED_4[32];
64102   __IO uint32_t UNMECR;                            /**< Uncorrectable non-fatal memory error configuration register, offset: 0xE30 */
64103   __IO uint32_t UNMESR0;                           /**< Uncorrectable non-fatal memory error status register 0, offset: 0xE34 */
64104   __I  uint32_t UNMESR1;                           /**< Uncorrectable non-fatal memory error status register 1, offset: 0xE38 */
64105   __I  uint32_t UNMECTR;                           /**< Uncorrectable non-fatal memory error count register, offset: 0xE3C */
64106   __IO uint32_t UFMECR;                            /**< Uncorrectable fatal memory error configuration register, offset: 0xE40 */
64107   __IO uint32_t UFMESR0;                           /**< Uncorrectable fatal memory error status register 0, offset: 0xE44 */
64108   __I  uint32_t UFMESR1;                           /**< Uncorrectable fatal memory error status register 1, offset: 0xE48 */
64109 } NETC_PRIV_Type;
64110 
64111 /* ----------------------------------------------------------------------------
64112    -- NETC_PRIV Register Masks
64113    ---------------------------------------------------------------------------- */
64114 
64115 /*!
64116  * @addtogroup NETC_PRIV_Register_Masks NETC_PRIV Register Masks
64117  * @{
64118  */
64119 
64120 /*! @name NETCRR - NETC reset register */
64121 /*! @{ */
64122 
64123 #define NETC_PRIV_NETCRR_SR_MASK                 (0x1U)
64124 #define NETC_PRIV_NETCRR_SR_SHIFT                (0U)
64125 /*! SR - Soft reset */
64126 #define NETC_PRIV_NETCRR_SR(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_SR_SHIFT)) & NETC_PRIV_NETCRR_SR_MASK)
64127 
64128 #define NETC_PRIV_NETCRR_LOCK_MASK               (0x2U)
64129 #define NETC_PRIV_NETCRR_LOCK_SHIFT              (1U)
64130 /*! LOCK - Lock */
64131 #define NETC_PRIV_NETCRR_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_LOCK_SHIFT)) & NETC_PRIV_NETCRR_LOCK_MASK)
64132 /*! @} */
64133 
64134 /*! @name NETCSR - NETC status register */
64135 /*! @{ */
64136 
64137 #define NETC_PRIV_NETCSR_ERROR_MASK              (0x1U)
64138 #define NETC_PRIV_NETCSR_ERROR_SHIFT             (0U)
64139 /*! ERROR - Error */
64140 #define NETC_PRIV_NETCSR_ERROR(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_ERROR_SHIFT)) & NETC_PRIV_NETCSR_ERROR_MASK)
64141 
64142 #define NETC_PRIV_NETCSR_STATE_MASK              (0x2U)
64143 #define NETC_PRIV_NETCSR_STATE_SHIFT             (1U)
64144 /*! STATE - Indicates NETC's global operational state */
64145 #define NETC_PRIV_NETCSR_STATE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_STATE_SHIFT)) & NETC_PRIV_NETCSR_STATE_MASK)
64146 /*! @} */
64147 
64148 /*! @name MEICR - Memory Error Injection Config Register */
64149 /*! @{ */
64150 
64151 #define NETC_PRIV_MEICR_MEM_ID_MASK              (0x1FU)
64152 #define NETC_PRIV_MEICR_MEM_ID_SHIFT             (0U)
64153 /*! MEM_ID - Memory ID */
64154 #define NETC_PRIV_MEICR_MEM_ID(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_MEM_ID_SHIFT)) & NETC_PRIV_MEICR_MEM_ID_MASK)
64155 
64156 #define NETC_PRIV_MEICR_ARM_MASK                 (0xC00000U)
64157 #define NETC_PRIV_MEICR_ARM_SHIFT                (22U)
64158 /*! ARM - Armed */
64159 #define NETC_PRIV_MEICR_ARM(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_ARM_SHIFT)) & NETC_PRIV_MEICR_ARM_MASK)
64160 
64161 #define NETC_PRIV_MEICR_EN_MASK                  (0xFF000000U)
64162 #define NETC_PRIV_MEICR_EN_SHIFT                 (24U)
64163 /*! EN - Enable */
64164 #define NETC_PRIV_MEICR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_EN_SHIFT)) & NETC_PRIV_MEICR_EN_MASK)
64165 /*! @} */
64166 
64167 /*! @name CMECR - Correctable memory error configuration register */
64168 /*! @{ */
64169 
64170 #define NETC_PRIV_CMECR_THRESHOLD_MASK           (0xFFU)
64171 #define NETC_PRIV_CMECR_THRESHOLD_SHIFT          (0U)
64172 /*! THRESHOLD - Threshold */
64173 #define NETC_PRIV_CMECR_THRESHOLD(x)             (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECR_THRESHOLD_SHIFT)) & NETC_PRIV_CMECR_THRESHOLD_MASK)
64174 /*! @} */
64175 
64176 /*! @name CMESR - Correctable memory error status register */
64177 /*! @{ */
64178 
64179 #define NETC_PRIV_CMESR_MEM_ID_MASK              (0x1F0000U)
64180 #define NETC_PRIV_CMESR_MEM_ID_SHIFT             (16U)
64181 /*! MEM_ID - Memory ID */
64182 #define NETC_PRIV_CMESR_MEM_ID(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_MEM_ID_SHIFT)) & NETC_PRIV_CMESR_MEM_ID_MASK)
64183 
64184 #define NETC_PRIV_CMESR_SBEE_MASK                (0x80000000U)
64185 #define NETC_PRIV_CMESR_SBEE_SHIFT               (31U)
64186 /*! SBEE - Single-bit ECC error */
64187 #define NETC_PRIV_CMESR_SBEE(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_SBEE_SHIFT)) & NETC_PRIV_CMESR_SBEE_MASK)
64188 /*! @} */
64189 
64190 /*! @name CMECTR - Correctable memory error count register */
64191 /*! @{ */
64192 
64193 #define NETC_PRIV_CMECTR_COUNT_MASK              (0xFFU)
64194 #define NETC_PRIV_CMECTR_COUNT_SHIFT             (0U)
64195 /*! COUNT - Count */
64196 #define NETC_PRIV_CMECTR_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECTR_COUNT_SHIFT)) & NETC_PRIV_CMECTR_COUNT_MASK)
64197 /*! @} */
64198 
64199 /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */
64200 /*! @{ */
64201 
64202 #define NETC_PRIV_UNMECR_THRESHOLD_MASK          (0xFFU)
64203 #define NETC_PRIV_UNMECR_THRESHOLD_SHIFT         (0U)
64204 /*! THRESHOLD - Threshold */
64205 #define NETC_PRIV_UNMECR_THRESHOLD(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_THRESHOLD_SHIFT)) & NETC_PRIV_UNMECR_THRESHOLD_MASK)
64206 
64207 #define NETC_PRIV_UNMECR_RD_MASK                 (0x80000000U)
64208 #define NETC_PRIV_UNMECR_RD_SHIFT                (31U)
64209 /*! RD - Report disable */
64210 #define NETC_PRIV_UNMECR_RD(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_RD_SHIFT)) & NETC_PRIV_UNMECR_RD_MASK)
64211 /*! @} */
64212 
64213 /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */
64214 /*! @{ */
64215 
64216 #define NETC_PRIV_UNMESR0_SYNDROME_MASK          (0x7FFU)
64217 #define NETC_PRIV_UNMESR0_SYNDROME_SHIFT         (0U)
64218 /*! SYNDROME - Syndrome */
64219 #define NETC_PRIV_UNMESR0_SYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UNMESR0_SYNDROME_MASK)
64220 
64221 #define NETC_PRIV_UNMESR0_MEM_ID_MASK            (0x1F0000U)
64222 #define NETC_PRIV_UNMESR0_MEM_ID_SHIFT           (16U)
64223 /*! MEM_ID - Memory ID */
64224 #define NETC_PRIV_UNMESR0_MEM_ID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UNMESR0_MEM_ID_MASK)
64225 
64226 #define NETC_PRIV_UNMESR0_MBEE_MASK              (0x80000000U)
64227 #define NETC_PRIV_UNMESR0_MBEE_SHIFT             (31U)
64228 /*! MBEE - Multi-bit ECC error */
64229 #define NETC_PRIV_UNMESR0_MBEE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MBEE_SHIFT)) & NETC_PRIV_UNMESR0_MBEE_MASK)
64230 /*! @} */
64231 
64232 /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */
64233 /*! @{ */
64234 
64235 #define NETC_PRIV_UNMESR1_ADDR_MASK              (0xFFFFFFFFU)
64236 #define NETC_PRIV_UNMESR1_ADDR_SHIFT             (0U)
64237 /*! ADDR - Address */
64238 #define NETC_PRIV_UNMESR1_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR1_ADDR_SHIFT)) & NETC_PRIV_UNMESR1_ADDR_MASK)
64239 /*! @} */
64240 
64241 /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */
64242 /*! @{ */
64243 
64244 #define NETC_PRIV_UNMECTR_COUNT_MASK             (0xFFU)
64245 #define NETC_PRIV_UNMECTR_COUNT_SHIFT            (0U)
64246 /*! COUNT - Count */
64247 #define NETC_PRIV_UNMECTR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECTR_COUNT_SHIFT)) & NETC_PRIV_UNMECTR_COUNT_MASK)
64248 /*! @} */
64249 
64250 /*! @name UFMECR - Uncorrectable fatal memory error configuration register */
64251 /*! @{ */
64252 
64253 #define NETC_PRIV_UFMECR_RD_MASK                 (0x80000000U)
64254 #define NETC_PRIV_UFMECR_RD_SHIFT                (31U)
64255 /*! RD - Report disable */
64256 #define NETC_PRIV_UFMECR_RD(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMECR_RD_SHIFT)) & NETC_PRIV_UFMECR_RD_MASK)
64257 /*! @} */
64258 
64259 /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */
64260 /*! @{ */
64261 
64262 #define NETC_PRIV_UFMESR0_SYNDROME_MASK          (0x7FFU)
64263 #define NETC_PRIV_UFMESR0_SYNDROME_SHIFT         (0U)
64264 /*! SYNDROME - Syndrome */
64265 #define NETC_PRIV_UFMESR0_SYNDROME(x)            (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UFMESR0_SYNDROME_MASK)
64266 
64267 #define NETC_PRIV_UFMESR0_MEM_ID_MASK            (0x1F0000U)
64268 #define NETC_PRIV_UFMESR0_MEM_ID_SHIFT           (16U)
64269 /*! MEM_ID - Memory ID */
64270 #define NETC_PRIV_UFMESR0_MEM_ID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UFMESR0_MEM_ID_MASK)
64271 
64272 #define NETC_PRIV_UFMESR0_M_MASK                 (0x40000000U)
64273 #define NETC_PRIV_UFMESR0_M_SHIFT                (30U)
64274 /*! M - Multiple */
64275 #define NETC_PRIV_UFMESR0_M(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_M_SHIFT)) & NETC_PRIV_UFMESR0_M_MASK)
64276 
64277 #define NETC_PRIV_UFMESR0_MBEE_MASK              (0x80000000U)
64278 #define NETC_PRIV_UFMESR0_MBEE_SHIFT             (31U)
64279 /*! MBEE - Multi-bit ECC error */
64280 #define NETC_PRIV_UFMESR0_MBEE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MBEE_SHIFT)) & NETC_PRIV_UFMESR0_MBEE_MASK)
64281 /*! @} */
64282 
64283 /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */
64284 /*! @{ */
64285 
64286 #define NETC_PRIV_UFMESR1_ADDR_MASK              (0xFFFFFFFFU)
64287 #define NETC_PRIV_UFMESR1_ADDR_SHIFT             (0U)
64288 /*! ADDR - Address */
64289 #define NETC_PRIV_UFMESR1_ADDR(x)                (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR1_ADDR_SHIFT)) & NETC_PRIV_UFMESR1_ADDR_MASK)
64290 /*! @} */
64291 
64292 
64293 /*!
64294  * @}
64295  */ /* end of group NETC_PRIV_Register_Masks */
64296 
64297 
64298 /* NETC_PRIV - Peripheral instance base addresses */
64299 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
64300   /** Peripheral NETC_PRIV base address */
64301   #define NETC_PRIV_BASE                           (0x70900000u)
64302   /** Peripheral NETC_PRIV base address */
64303   #define NETC_PRIV_BASE_NS                        (0x60900000u)
64304   /** Peripheral NETC_PRIV base pointer */
64305   #define NETC_PRIV                                ((NETC_PRIV_Type *)NETC_PRIV_BASE)
64306   /** Peripheral NETC_PRIV base pointer */
64307   #define NETC_PRIV_NS                             ((NETC_PRIV_Type *)NETC_PRIV_BASE_NS)
64308   /** Array initializer of NETC_PRIV peripheral base addresses */
64309   #define NETC_PRIV_BASE_ADDRS                     { NETC_PRIV_BASE }
64310   /** Array initializer of NETC_PRIV peripheral base pointers */
64311   #define NETC_PRIV_BASE_PTRS                      { NETC_PRIV }
64312   /** Array initializer of NETC_PRIV peripheral base addresses */
64313   #define NETC_PRIV_BASE_ADDRS_NS                  { NETC_PRIV_BASE_NS }
64314   /** Array initializer of NETC_PRIV peripheral base pointers */
64315   #define NETC_PRIV_BASE_PTRS_NS                   { NETC_PRIV_NS }
64316 #else
64317   /** Peripheral NETC_PRIV base address */
64318   #define NETC_PRIV_BASE                           (0x60900000u)
64319   /** Peripheral NETC_PRIV base pointer */
64320   #define NETC_PRIV                                ((NETC_PRIV_Type *)NETC_PRIV_BASE)
64321   /** Array initializer of NETC_PRIV peripheral base addresses */
64322   #define NETC_PRIV_BASE_ADDRS                     { NETC_PRIV_BASE }
64323   /** Array initializer of NETC_PRIV peripheral base pointers */
64324   #define NETC_PRIV_BASE_PTRS                      { NETC_PRIV }
64325 #endif
64326 
64327 /*!
64328  * @}
64329  */ /* end of group NETC_PRIV_Peripheral_Access_Layer */
64330 
64331 
64332 /* ----------------------------------------------------------------------------
64333    -- NETC_PSEUDO_LINK Peripheral Access Layer
64334    ---------------------------------------------------------------------------- */
64335 
64336 /*!
64337  * @addtogroup NETC_PSEUDO_LINK_Peripheral_Access_Layer NETC_PSEUDO_LINK Peripheral Access Layer
64338  * @{
64339  */
64340 
64341 /** NETC_PSEUDO_LINK - Register Layout Typedef */
64342 typedef struct {
64343   __I  uint32_t PPMSR;                             /**< Port pseudo MAC status register, offset: 0x0 */
64344        uint8_t RESERVED_0[12];
64345   __IO uint32_t PPMCR;                             /**< Port pseudo MAC configuration register, offset: 0x10, available only on: ENETC1_PSEUDO_MAC_PORT (missing on SW0_PSEUDO_MAC_PORT4) */
64346        uint8_t RESERVED_1[108];
64347   __I  uint32_t PPMROCR[2];                        /**< Port pseudo MAC receive octets counter, array offset: 0x80, array step: 0x4 */
64348   __I  uint32_t PPMRUFCR[2];                       /**< Port pseudo MAC receive unicast frame counter register, array offset: 0x88, array step: 0x4 */
64349   __I  uint32_t PPMRMFCR[2];                       /**< Port pseudo MAC receive multicast frame counter register, array offset: 0x90, array step: 0x4 */
64350   __I  uint32_t PPMRBFCR[2];                       /**< Port pseudo MAC receive broadcast frame counter register, array offset: 0x98, array step: 0x4 */
64351        uint8_t RESERVED_2[32];
64352   __I  uint32_t PPMTOCR[2];                        /**< Port pseudo MAC transmit octets counter, array offset: 0xC0, array step: 0x4 */
64353   __I  uint32_t PPMTUFCR[2];                       /**< Port pseudo MAC transmit unicast frame counter register, array offset: 0xC8, array step: 0x4 */
64354   __I  uint32_t PPMTMFCR[2];                       /**< Port pseudo MAC transmit multicast frame counter register, array offset: 0xD0, array step: 0x4 */
64355   __I  uint32_t PPMTBFCR[2];                       /**< Port pseudo MAC transmit broadcast frame counter register, array offset: 0xD8, array step: 0x4 */
64356 } NETC_PSEUDO_LINK_Type;
64357 
64358 /* ----------------------------------------------------------------------------
64359    -- NETC_PSEUDO_LINK Register Masks
64360    ---------------------------------------------------------------------------- */
64361 
64362 /*!
64363  * @addtogroup NETC_PSEUDO_LINK_Register_Masks NETC_PSEUDO_LINK Register Masks
64364  * @{
64365  */
64366 
64367 /*! @name PPMSR - Port pseudo MAC status register */
64368 /*! @{ */
64369 
64370 #define NETC_PSEUDO_LINK_PPMSR_LSTATE_MASK       (0x1U)
64371 #define NETC_PSEUDO_LINK_PPMSR_LSTATE_SHIFT      (0U)
64372 #define NETC_PSEUDO_LINK_PPMSR_LSTATE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMSR_LSTATE_SHIFT)) & NETC_PSEUDO_LINK_PPMSR_LSTATE_MASK)
64373 
64374 #define NETC_PSEUDO_LINK_PPMSR_RSTATE_MASK       (0x100U)
64375 #define NETC_PSEUDO_LINK_PPMSR_RSTATE_SHIFT      (8U)
64376 #define NETC_PSEUDO_LINK_PPMSR_RSTATE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMSR_RSTATE_SHIFT)) & NETC_PSEUDO_LINK_PPMSR_RSTATE_MASK)
64377 /*! @} */
64378 
64379 /*! @name PPMCR - Port pseudo MAC configuration register */
64380 /*! @{ */
64381 
64382 #define NETC_PSEUDO_LINK_PPMCR_TXPAD_MASK        (0x10000U)
64383 #define NETC_PSEUDO_LINK_PPMCR_TXPAD_SHIFT       (16U)
64384 /*! TXPAD - Transmit Padding */
64385 #define NETC_PSEUDO_LINK_PPMCR_TXPAD(x)          (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMCR_TXPAD_SHIFT)) & NETC_PSEUDO_LINK_PPMCR_TXPAD_MASK)
64386 /*! @} */
64387 
64388 /*! @name PPMROCR - Port pseudo MAC receive octets counter */
64389 /*! @{ */
64390 
64391 #define NETC_PSEUDO_LINK_PPMROCR_ROCT_MASK       (0xFFFFFFFFU)
64392 #define NETC_PSEUDO_LINK_PPMROCR_ROCT_SHIFT      (0U)
64393 #define NETC_PSEUDO_LINK_PPMROCR_ROCT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMROCR_ROCT_SHIFT)) & NETC_PSEUDO_LINK_PPMROCR_ROCT_MASK)
64394 /*! @} */
64395 
64396 /* The count of NETC_PSEUDO_LINK_PPMROCR */
64397 #define NETC_PSEUDO_LINK_PPMROCR_COUNT           (2U)
64398 
64399 /*! @name PPMRUFCR - Port pseudo MAC receive unicast frame counter register */
64400 /*! @{ */
64401 
64402 #define NETC_PSEUDO_LINK_PPMRUFCR_RUCA_MASK      (0xFFFFFFFFU)
64403 #define NETC_PSEUDO_LINK_PPMRUFCR_RUCA_SHIFT     (0U)
64404 #define NETC_PSEUDO_LINK_PPMRUFCR_RUCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMRUFCR_RUCA_SHIFT)) & NETC_PSEUDO_LINK_PPMRUFCR_RUCA_MASK)
64405 /*! @} */
64406 
64407 /* The count of NETC_PSEUDO_LINK_PPMRUFCR */
64408 #define NETC_PSEUDO_LINK_PPMRUFCR_COUNT          (2U)
64409 
64410 /*! @name PPMRMFCR - Port pseudo MAC receive multicast frame counter register */
64411 /*! @{ */
64412 
64413 #define NETC_PSEUDO_LINK_PPMRMFCR_RMCA_MASK      (0xFFFFFFFFU)
64414 #define NETC_PSEUDO_LINK_PPMRMFCR_RMCA_SHIFT     (0U)
64415 #define NETC_PSEUDO_LINK_PPMRMFCR_RMCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMRMFCR_RMCA_SHIFT)) & NETC_PSEUDO_LINK_PPMRMFCR_RMCA_MASK)
64416 /*! @} */
64417 
64418 /* The count of NETC_PSEUDO_LINK_PPMRMFCR */
64419 #define NETC_PSEUDO_LINK_PPMRMFCR_COUNT          (2U)
64420 
64421 /*! @name PPMRBFCR - Port pseudo MAC receive broadcast frame counter register */
64422 /*! @{ */
64423 
64424 #define NETC_PSEUDO_LINK_PPMRBFCR_RBCA_MASK      (0xFFFFFFFFU)
64425 #define NETC_PSEUDO_LINK_PPMRBFCR_RBCA_SHIFT     (0U)
64426 #define NETC_PSEUDO_LINK_PPMRBFCR_RBCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMRBFCR_RBCA_SHIFT)) & NETC_PSEUDO_LINK_PPMRBFCR_RBCA_MASK)
64427 /*! @} */
64428 
64429 /* The count of NETC_PSEUDO_LINK_PPMRBFCR */
64430 #define NETC_PSEUDO_LINK_PPMRBFCR_COUNT          (2U)
64431 
64432 /*! @name PPMTOCR - Port pseudo MAC transmit octets counter */
64433 /*! @{ */
64434 
64435 #define NETC_PSEUDO_LINK_PPMTOCR_TOCT_MASK       (0xFFFFFFFFU)
64436 #define NETC_PSEUDO_LINK_PPMTOCR_TOCT_SHIFT      (0U)
64437 #define NETC_PSEUDO_LINK_PPMTOCR_TOCT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMTOCR_TOCT_SHIFT)) & NETC_PSEUDO_LINK_PPMTOCR_TOCT_MASK)
64438 /*! @} */
64439 
64440 /* The count of NETC_PSEUDO_LINK_PPMTOCR */
64441 #define NETC_PSEUDO_LINK_PPMTOCR_COUNT           (2U)
64442 
64443 /*! @name PPMTUFCR - Port pseudo MAC transmit unicast frame counter register */
64444 /*! @{ */
64445 
64446 #define NETC_PSEUDO_LINK_PPMTUFCR_TUCA_MASK      (0xFFFFFFFFU)
64447 #define NETC_PSEUDO_LINK_PPMTUFCR_TUCA_SHIFT     (0U)
64448 #define NETC_PSEUDO_LINK_PPMTUFCR_TUCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMTUFCR_TUCA_SHIFT)) & NETC_PSEUDO_LINK_PPMTUFCR_TUCA_MASK)
64449 /*! @} */
64450 
64451 /* The count of NETC_PSEUDO_LINK_PPMTUFCR */
64452 #define NETC_PSEUDO_LINK_PPMTUFCR_COUNT          (2U)
64453 
64454 /*! @name PPMTMFCR - Port pseudo MAC transmit multicast frame counter register */
64455 /*! @{ */
64456 
64457 #define NETC_PSEUDO_LINK_PPMTMFCR_TMCA_MASK      (0xFFFFFFFFU)
64458 #define NETC_PSEUDO_LINK_PPMTMFCR_TMCA_SHIFT     (0U)
64459 #define NETC_PSEUDO_LINK_PPMTMFCR_TMCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMTMFCR_TMCA_SHIFT)) & NETC_PSEUDO_LINK_PPMTMFCR_TMCA_MASK)
64460 /*! @} */
64461 
64462 /* The count of NETC_PSEUDO_LINK_PPMTMFCR */
64463 #define NETC_PSEUDO_LINK_PPMTMFCR_COUNT          (2U)
64464 
64465 /*! @name PPMTBFCR - Port pseudo MAC transmit broadcast frame counter register */
64466 /*! @{ */
64467 
64468 #define NETC_PSEUDO_LINK_PPMTBFCR_TBCA_MASK      (0xFFFFFFFFU)
64469 #define NETC_PSEUDO_LINK_PPMTBFCR_TBCA_SHIFT     (0U)
64470 #define NETC_PSEUDO_LINK_PPMTBFCR_TBCA(x)        (((uint32_t)(((uint32_t)(x)) << NETC_PSEUDO_LINK_PPMTBFCR_TBCA_SHIFT)) & NETC_PSEUDO_LINK_PPMTBFCR_TBCA_MASK)
64471 /*! @} */
64472 
64473 /* The count of NETC_PSEUDO_LINK_PPMTBFCR */
64474 #define NETC_PSEUDO_LINK_PPMTBFCR_COUNT          (2U)
64475 
64476 
64477 /*!
64478  * @}
64479  */ /* end of group NETC_PSEUDO_LINK_Register_Masks */
64480 
64481 
64482 /* NETC_PSEUDO_LINK - Peripheral instance base addresses */
64483 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
64484   /** Peripheral ENETC1_PSEUDO_MAC_PORT base address */
64485   #define ENETC1_PSEUDO_MAC_PORT_BASE              (0x70B55000u)
64486   /** Peripheral ENETC1_PSEUDO_MAC_PORT base address */
64487   #define ENETC1_PSEUDO_MAC_PORT_BASE_NS           (0x60B55000u)
64488   /** Peripheral ENETC1_PSEUDO_MAC_PORT base pointer */
64489   #define ENETC1_PSEUDO_MAC_PORT                   ((NETC_PSEUDO_LINK_Type *)ENETC1_PSEUDO_MAC_PORT_BASE)
64490   /** Peripheral ENETC1_PSEUDO_MAC_PORT base pointer */
64491   #define ENETC1_PSEUDO_MAC_PORT_NS                ((NETC_PSEUDO_LINK_Type *)ENETC1_PSEUDO_MAC_PORT_BASE_NS)
64492   /** Peripheral SW0_PSEUDO_MAC_PORT4 base address */
64493   #define SW0_PSEUDO_MAC_PORT4_BASE                (0x70A15000u)
64494   /** Peripheral SW0_PSEUDO_MAC_PORT4 base address */
64495   #define SW0_PSEUDO_MAC_PORT4_BASE_NS             (0x60A15000u)
64496   /** Peripheral SW0_PSEUDO_MAC_PORT4 base pointer */
64497   #define SW0_PSEUDO_MAC_PORT4                     ((NETC_PSEUDO_LINK_Type *)SW0_PSEUDO_MAC_PORT4_BASE)
64498   /** Peripheral SW0_PSEUDO_MAC_PORT4 base pointer */
64499   #define SW0_PSEUDO_MAC_PORT4_NS                  ((NETC_PSEUDO_LINK_Type *)SW0_PSEUDO_MAC_PORT4_BASE_NS)
64500   /** Array initializer of NETC_PSEUDO_LINK peripheral base addresses */
64501   #define NETC_PSEUDO_LINK_BASE_ADDRS              { ENETC1_PSEUDO_MAC_PORT_BASE, SW0_PSEUDO_MAC_PORT4_BASE }
64502   /** Array initializer of NETC_PSEUDO_LINK peripheral base pointers */
64503   #define NETC_PSEUDO_LINK_BASE_PTRS               { ENETC1_PSEUDO_MAC_PORT, SW0_PSEUDO_MAC_PORT4 }
64504   /** Array initializer of NETC_PSEUDO_LINK peripheral base addresses */
64505   #define NETC_PSEUDO_LINK_BASE_ADDRS_NS           { ENETC1_PSEUDO_MAC_PORT_BASE_NS, SW0_PSEUDO_MAC_PORT4_BASE_NS }
64506   /** Array initializer of NETC_PSEUDO_LINK peripheral base pointers */
64507   #define NETC_PSEUDO_LINK_BASE_PTRS_NS            { ENETC1_PSEUDO_MAC_PORT_NS, SW0_PSEUDO_MAC_PORT4_NS }
64508 #else
64509   /** Peripheral ENETC1_PSEUDO_MAC_PORT base address */
64510   #define ENETC1_PSEUDO_MAC_PORT_BASE              (0x60B55000u)
64511   /** Peripheral ENETC1_PSEUDO_MAC_PORT base pointer */
64512   #define ENETC1_PSEUDO_MAC_PORT                   ((NETC_PSEUDO_LINK_Type *)ENETC1_PSEUDO_MAC_PORT_BASE)
64513   /** Peripheral SW0_PSEUDO_MAC_PORT4 base address */
64514   #define SW0_PSEUDO_MAC_PORT4_BASE                (0x60A15000u)
64515   /** Peripheral SW0_PSEUDO_MAC_PORT4 base pointer */
64516   #define SW0_PSEUDO_MAC_PORT4                     ((NETC_PSEUDO_LINK_Type *)SW0_PSEUDO_MAC_PORT4_BASE)
64517   /** Array initializer of NETC_PSEUDO_LINK peripheral base addresses */
64518   #define NETC_PSEUDO_LINK_BASE_ADDRS              { ENETC1_PSEUDO_MAC_PORT_BASE, SW0_PSEUDO_MAC_PORT4_BASE }
64519   /** Array initializer of NETC_PSEUDO_LINK peripheral base pointers */
64520   #define NETC_PSEUDO_LINK_BASE_PTRS               { ENETC1_PSEUDO_MAC_PORT, SW0_PSEUDO_MAC_PORT4 }
64521 #endif
64522 
64523 /*!
64524  * @}
64525  */ /* end of group NETC_PSEUDO_LINK_Peripheral_Access_Layer */
64526 
64527 
64528 /* ----------------------------------------------------------------------------
64529    -- NETC_SW Peripheral Access Layer
64530    ---------------------------------------------------------------------------- */
64531 
64532 /*!
64533  * @addtogroup NETC_SW_Peripheral_Access_Layer NETC_SW Peripheral Access Layer
64534  * @{
64535  */
64536 
64537 /** NETC_SW - Register Layout Typedef */
64538 typedef struct {
64539   __I  uint32_t SCAPR0;                            /**< Switch capability register 0, offset: 0x0 */
64540   __I  uint32_t SCAPR1;                            /**< Switch capability register 1, offset: 0x4 */
64541   __I  uint32_t BPCAPR;                            /**< Buffer pool capability register, offset: 0x8 */
64542        uint8_t RESERVED_0[12];
64543   __I  uint32_t FCAPR;                             /**< Forwarding capability register, offset: 0x18 */
64544        uint8_t RESERVED_1[36];
64545   __I  uint32_t SMBCAPR;                           /**< Shared memory buffer capability register, offset: 0x40 */
64546   __I  uint32_t SMBOR0;                            /**< Shared memory buffer operational register 0, offset: 0x44 */
64547   __I  uint32_t SMBOR1;                            /**< Shared memory buffer operational register 1, offset: 0x48 */
64548        uint8_t RESERVED_2[52];
64549   __IO uint32_t CCAR;                              /**< Command cache attribute register, offset: 0x80 */
64550        uint8_t RESERVED_3[892];
64551   __I  uint32_t MPCR;                              /**< Management port configuration register, offset: 0x400 */
64552        uint8_t RESERVED_4[28];
64553   __IO uint32_t IMDCR0;                            /**< Ingress mirror destination configuration register 0, offset: 0x420 */
64554   __IO uint32_t IMDCR1;                            /**< Ingress mirror destination configuration register 1, offset: 0x424 */
64555        uint8_t RESERVED_5[24];
64556   __IO uint32_t CTFCR;                             /**< Cut-through forwarding count register, offset: 0x440 */
64557        uint8_t RESERVED_6[956];
64558   struct {                                         /* offset: 0x800, array step: 0x30 */
64559     __IO uint32_t CBDRMR;                            /**< Command BDR 0 mode register..Command BDR 1 mode register, array offset: 0x800, array step: 0x30 */
64560     __I  uint32_t CBDRSR;                            /**< Command BDR 0 status register..Command BDR 1 status register, array offset: 0x804, array step: 0x30 */
64561          uint8_t RESERVED_0[8];
64562     __IO uint32_t CBDRBAR0;                          /**< Command BDR base address register 0, array offset: 0x810, array step: 0x30 */
64563     __IO uint32_t CBDRBAR1;                          /**< Command BDR 0 base address register 1..Command BDR 1 base address register 1, array offset: 0x814, array step: 0x30 */
64564     __IO uint32_t CBDRPIR;                           /**< Command BDR 0 producer index register..Command BDR 1 producer index register, array offset: 0x818, array step: 0x30 */
64565     __IO uint32_t CBDRCIR;                           /**< Command BDR 0 consumer index register..Command BDR 1 consumer index register, array offset: 0x81C, array step: 0x30 */
64566     __IO uint32_t CBDRLENR;                          /**< Command BDR 0 length register..Command BDR 1 length register, array offset: 0x820, array step: 0x30 */
64567          uint8_t RESERVED_1[12];
64568   } NUM_CBDR[2];
64569        uint8_t RESERVED_7[64];
64570   struct {                                         /* offset: 0x8A0, array step: 0x10 */
64571     __IO uint32_t CBDRIER;                           /**< Command BDR 0 interrupt enable register..Command BDR 1 interrupt enable register, array offset: 0x8A0, array step: 0x10 */
64572     __IO uint32_t CBDRIDR;                           /**< Command BDR 0 interrupt detect register..Command BDR 1 interrupt detect register, array offset: 0x8A4, array step: 0x10 */
64573     __IO uint32_t CBDRMSIVR;                         /**< Command BDR 0 MSI-X vector register..Command BDR 1 MSI-X vector register, array offset: 0x8A8, array step: 0x10 */
64574          uint8_t RESERVED_0[4];
64575   } NUM_CBDR_INT[2];
64576        uint8_t RESERVED_8[64];
64577   struct {                                         /* offset: 0x900, array step: 0x20 */
64578     __IO uint32_t QOSVLANMPR[4];                     /**< QoS to VLAN mapping profile 0 register 0..QoS to VLAN mapping profile 1 register 3, array offset: 0x900, array step: index*0x20, index2*0x4 */
64579          uint8_t RESERVED_0[16];
64580   } MAP_PCP[2];
64581        uint8_t RESERVED_9[448];
64582   __IO uint32_t PCP2PCPMPR[2];                     /**< PCP to PCP mapping profile 0 register..PCP to PCP mapping profile 1 register, array offset: 0xB00, array step: 0x4 */
64583        uint8_t RESERVED_10[5368];
64584   __I  uint32_t BRCAPR;                            /**< Bridge capability register, offset: 0x2000 */
64585        uint8_t RESERVED_11[4];
64586   __I  uint32_t VFHTCAPR;                          /**< VLAN filter hash table capability register, offset: 0x2008 */
64587   __I  uint32_t VFHTOR;                            /**< VLAN filter hash table operational register, offset: 0x200C */
64588   __IO uint32_t VFHTDECR0;                         /**< VLAN Filter (hash) table default entry configuration registers 0, offset: 0x2010 */
64589   __IO uint32_t VFHTDECR1;                         /**< VLAN filter hash table default entry configuration registers 1, offset: 0x2014 */
64590   __IO uint32_t VFHTDECR2;                         /**< VLAN filter hash table default entry configuration registers 2, offset: 0x2018 */
64591        uint8_t RESERVED_12[4];
64592   __I  uint32_t FDBHTCAPR;                         /**< FDB hash table capability register, offset: 0x2020 */
64593   __IO uint32_t FDBHTMCR;                          /**< FDB hash table memory configuration register, offset: 0x2024 */
64594   __I  uint32_t FDBHTOR0;                          /**< FDB hash table operational register 0, offset: 0x2028 */
64595   __I  uint32_t FDBHTOR1;                          /**< FDB hash table operational register 1, offset: 0x202C */
64596        uint8_t RESERVED_13[16];
64597   __I  uint32_t IPMFHTCAPR;                        /**< IP multicast filter hash table capability register, offset: 0x2040 */
64598   __I  uint32_t IPV4MFHTOR;                        /**< IPv4 multicast filter hash table operation register, offset: 0x2044 */
64599 } NETC_SW_Type;
64600 
64601 /* ----------------------------------------------------------------------------
64602    -- NETC_SW Register Masks
64603    ---------------------------------------------------------------------------- */
64604 
64605 /*!
64606  * @addtogroup NETC_SW_Register_Masks NETC_SW Register Masks
64607  * @{
64608  */
64609 
64610 /*! @name SCAPR0 - Switch capability register 0 */
64611 /*! @{ */
64612 
64613 #define NETC_SW_SCAPR0_NUM_PORT_MASK             (0x1FU)
64614 #define NETC_SW_SCAPR0_NUM_PORT_SHIFT            (0U)
64615 #define NETC_SW_SCAPR0_NUM_PORT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR0_NUM_PORT_SHIFT)) & NETC_SW_SCAPR0_NUM_PORT_MASK)
64616 
64617 #define NETC_SW_SCAPR0_NUM_IPV_MASK              (0x100U)
64618 #define NETC_SW_SCAPR0_NUM_IPV_SHIFT             (8U)
64619 #define NETC_SW_SCAPR0_NUM_IPV(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR0_NUM_IPV_SHIFT)) & NETC_SW_SCAPR0_NUM_IPV_MASK)
64620 
64621 #define NETC_SW_SCAPR0_NUM_MSIX_MASK             (0xF0000U)
64622 #define NETC_SW_SCAPR0_NUM_MSIX_SHIFT            (16U)
64623 #define NETC_SW_SCAPR0_NUM_MSIX(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR0_NUM_MSIX_SHIFT)) & NETC_SW_SCAPR0_NUM_MSIX_MASK)
64624 
64625 #define NETC_SW_SCAPR0_NUM_PCPMP_MASK            (0xF00000U)
64626 #define NETC_SW_SCAPR0_NUM_PCPMP_SHIFT           (20U)
64627 #define NETC_SW_SCAPR0_NUM_PCPMP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR0_NUM_PCPMP_SHIFT)) & NETC_SW_SCAPR0_NUM_PCPMP_MASK)
64628 
64629 #define NETC_SW_SCAPR0_NUM_QVMP_MASK             (0xF000000U)
64630 #define NETC_SW_SCAPR0_NUM_QVMP_SHIFT            (24U)
64631 #define NETC_SW_SCAPR0_NUM_QVMP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR0_NUM_QVMP_SHIFT)) & NETC_SW_SCAPR0_NUM_QVMP_MASK)
64632 /*! @} */
64633 
64634 /*! @name SCAPR1 - Switch capability register 1 */
64635 /*! @{ */
64636 
64637 #define NETC_SW_SCAPR1_FS_MASK                   (0x1U)
64638 #define NETC_SW_SCAPR1_FS_SHIFT                  (0U)
64639 /*! FS - Functional safety capability supported. */
64640 #define NETC_SW_SCAPR1_FS(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR1_FS_SHIFT)) & NETC_SW_SCAPR1_FS_MASK)
64641 
64642 #define NETC_SW_SCAPR1_CTF_MASK                  (0x4U)
64643 #define NETC_SW_SCAPR1_CTF_SHIFT                 (2U)
64644 #define NETC_SW_SCAPR1_CTF(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR1_CTF_SHIFT)) & NETC_SW_SCAPR1_CTF_MASK)
64645 
64646 #define NETC_SW_SCAPR1_TIMCAP_MASK               (0x8U)
64647 #define NETC_SW_SCAPR1_TIMCAP_SHIFT              (3U)
64648 #define NETC_SW_SCAPR1_TIMCAP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR1_TIMCAP_SHIFT)) & NETC_SW_SCAPR1_TIMCAP_MASK)
64649 
64650 #define NETC_SW_SCAPR1_IMIR_MASK                 (0x10U)
64651 #define NETC_SW_SCAPR1_IMIR_SHIFT                (4U)
64652 #define NETC_SW_SCAPR1_IMIR(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR1_IMIR_SHIFT)) & NETC_SW_SCAPR1_IMIR_MASK)
64653 
64654 #define NETC_SW_SCAPR1_SQ_TAGS_MASK              (0x1F0000U)
64655 #define NETC_SW_SCAPR1_SQ_TAGS_SHIFT             (16U)
64656 #define NETC_SW_SCAPR1_SQ_TAGS(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_SCAPR1_SQ_TAGS_SHIFT)) & NETC_SW_SCAPR1_SQ_TAGS_MASK)
64657 /*! @} */
64658 
64659 /*! @name BPCAPR - Buffer pool capability register */
64660 /*! @{ */
64661 
64662 #define NETC_SW_BPCAPR_NUM_BP_MASK               (0xFFU)
64663 #define NETC_SW_BPCAPR_NUM_BP_SHIFT              (0U)
64664 #define NETC_SW_BPCAPR_NUM_BP(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_BPCAPR_NUM_BP_SHIFT)) & NETC_SW_BPCAPR_NUM_BP_MASK)
64665 
64666 #define NETC_SW_BPCAPR_NUM_SPB_MASK              (0x1F0000U)
64667 #define NETC_SW_BPCAPR_NUM_SPB_SHIFT             (16U)
64668 #define NETC_SW_BPCAPR_NUM_SPB(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_BPCAPR_NUM_SPB_SHIFT)) & NETC_SW_BPCAPR_NUM_SPB_MASK)
64669 /*! @} */
64670 
64671 /*! @name FCAPR - Forwarding capability register */
64672 /*! @{ */
64673 
64674 #define NETC_SW_FCAPR_BR_MASK                    (0x1U)
64675 #define NETC_SW_FCAPR_BR_SHIFT                   (0U)
64676 /*! BR - 802.1Q bridge forwarding support.
64677  *  0b0..Not supported
64678  *  0b1..Supported
64679  */
64680 #define NETC_SW_FCAPR_BR(x)                      (((uint32_t)(((uint32_t)(x)) << NETC_SW_FCAPR_BR_SHIFT)) & NETC_SW_FCAPR_BR_MASK)
64681 
64682 #define NETC_SW_FCAPR_SF_MASK                    (0x2U)
64683 #define NETC_SW_FCAPR_SF_SHIFT                   (1U)
64684 /*! SF - Stream forwarding supported
64685  *  0b0..Not supported
64686  *  0b1..Supported
64687  */
64688 #define NETC_SW_FCAPR_SF(x)                      (((uint32_t)(((uint32_t)(x)) << NETC_SW_FCAPR_SF_SHIFT)) & NETC_SW_FCAPR_SF_MASK)
64689 /*! @} */
64690 
64691 /*! @name SMBCAPR - Shared memory buffer capability register */
64692 /*! @{ */
64693 
64694 #define NETC_SW_SMBCAPR_NUM_WORDS_MASK           (0xFFFFFFU)
64695 #define NETC_SW_SMBCAPR_NUM_WORDS_SHIFT          (0U)
64696 #define NETC_SW_SMBCAPR_NUM_WORDS(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_SMBCAPR_NUM_WORDS_SHIFT)) & NETC_SW_SMBCAPR_NUM_WORDS_MASK)
64697 
64698 #define NETC_SW_SMBCAPR_WORD_SIZE_MASK           (0x30000000U)
64699 #define NETC_SW_SMBCAPR_WORD_SIZE_SHIFT          (28U)
64700 /*! WORD_SIZE
64701  *  0b00..24 bytes
64702  *  0b01-0b11..
64703  */
64704 #define NETC_SW_SMBCAPR_WORD_SIZE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_SMBCAPR_WORD_SIZE_SHIFT)) & NETC_SW_SMBCAPR_WORD_SIZE_MASK)
64705 
64706 #define NETC_SW_SMBCAPR_MLOC_MASK                (0xC0000000U)
64707 #define NETC_SW_SMBCAPR_MLOC_SHIFT               (30U)
64708 /*! MLOC - Indicates memory location
64709  *  0b00..Common memory
64710  *  0b01-0b11..
64711  */
64712 #define NETC_SW_SMBCAPR_MLOC(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_SW_SMBCAPR_MLOC_SHIFT)) & NETC_SW_SMBCAPR_MLOC_MASK)
64713 /*! @} */
64714 
64715 /*! @name SMBOR0 - Shared memory buffer operational register 0 */
64716 /*! @{ */
64717 
64718 #define NETC_SW_SMBOR0_COUNT_MASK                (0xFFFFFFU)
64719 #define NETC_SW_SMBOR0_COUNT_SHIFT               (0U)
64720 #define NETC_SW_SMBOR0_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_SW_SMBOR0_COUNT_SHIFT)) & NETC_SW_SMBOR0_COUNT_MASK)
64721 /*! @} */
64722 
64723 /*! @name SMBOR1 - Shared memory buffer operational register 1 */
64724 /*! @{ */
64725 
64726 #define NETC_SW_SMBOR1_WATERMARK_MASK            (0xFFFFFFU)
64727 #define NETC_SW_SMBOR1_WATERMARK_SHIFT           (0U)
64728 #define NETC_SW_SMBOR1_WATERMARK(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_SMBOR1_WATERMARK_SHIFT)) & NETC_SW_SMBOR1_WATERMARK_MASK)
64729 /*! @} */
64730 
64731 /*! @name CCAR - Command cache attribute register */
64732 /*! @{ */
64733 
64734 #define NETC_SW_CCAR_CBD_WRCACHE_MASK            (0xFU)
64735 #define NETC_SW_CCAR_CBD_WRCACHE_SHIFT           (0U)
64736 #define NETC_SW_CCAR_CBD_WRCACHE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_WRCACHE_SHIFT)) & NETC_SW_CCAR_CBD_WRCACHE_MASK)
64737 
64738 #define NETC_SW_CCAR_CBD_WRDOMAIN_MASK           (0x30U)
64739 #define NETC_SW_CCAR_CBD_WRDOMAIN_SHIFT          (4U)
64740 #define NETC_SW_CCAR_CBD_WRDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_WRDOMAIN_SHIFT)) & NETC_SW_CCAR_CBD_WRDOMAIN_MASK)
64741 
64742 #define NETC_SW_CCAR_CBD_WRSNP_MASK              (0x40U)
64743 #define NETC_SW_CCAR_CBD_WRSNP_SHIFT             (6U)
64744 #define NETC_SW_CCAR_CBD_WRSNP(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_WRSNP_SHIFT)) & NETC_SW_CCAR_CBD_WRSNP_MASK)
64745 
64746 #define NETC_SW_CCAR_CWRCACHE_MASK               (0xF00U)
64747 #define NETC_SW_CCAR_CWRCACHE_SHIFT              (8U)
64748 #define NETC_SW_CCAR_CWRCACHE(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CWRCACHE_SHIFT)) & NETC_SW_CCAR_CWRCACHE_MASK)
64749 
64750 #define NETC_SW_CCAR_CWRDOMAIN_MASK              (0x3000U)
64751 #define NETC_SW_CCAR_CWRDOMAIN_SHIFT             (12U)
64752 #define NETC_SW_CCAR_CWRDOMAIN(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CWRDOMAIN_SHIFT)) & NETC_SW_CCAR_CWRDOMAIN_MASK)
64753 
64754 #define NETC_SW_CCAR_CWRSNP_MASK                 (0x4000U)
64755 #define NETC_SW_CCAR_CWRSNP_SHIFT                (14U)
64756 #define NETC_SW_CCAR_CWRSNP(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CWRSNP_SHIFT)) & NETC_SW_CCAR_CWRSNP_MASK)
64757 
64758 #define NETC_SW_CCAR_CBD_RDCACHE_MASK            (0xF0000U)
64759 #define NETC_SW_CCAR_CBD_RDCACHE_SHIFT           (16U)
64760 #define NETC_SW_CCAR_CBD_RDCACHE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_RDCACHE_SHIFT)) & NETC_SW_CCAR_CBD_RDCACHE_MASK)
64761 
64762 #define NETC_SW_CCAR_CBD_RDDOMAIN_MASK           (0x300000U)
64763 #define NETC_SW_CCAR_CBD_RDDOMAIN_SHIFT          (20U)
64764 #define NETC_SW_CCAR_CBD_RDDOMAIN(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_RDDOMAIN_SHIFT)) & NETC_SW_CCAR_CBD_RDDOMAIN_MASK)
64765 
64766 #define NETC_SW_CCAR_CBD_RDSNP_MASK              (0x400000U)
64767 #define NETC_SW_CCAR_CBD_RDSNP_SHIFT             (22U)
64768 #define NETC_SW_CCAR_CBD_RDSNP(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CBD_RDSNP_SHIFT)) & NETC_SW_CCAR_CBD_RDSNP_MASK)
64769 
64770 #define NETC_SW_CCAR_CRDCACHE_MASK               (0xF000000U)
64771 #define NETC_SW_CCAR_CRDCACHE_SHIFT              (24U)
64772 #define NETC_SW_CCAR_CRDCACHE(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CRDCACHE_SHIFT)) & NETC_SW_CCAR_CRDCACHE_MASK)
64773 
64774 #define NETC_SW_CCAR_CRDDOMAIN_MASK              (0x30000000U)
64775 #define NETC_SW_CCAR_CRDDOMAIN_SHIFT             (28U)
64776 #define NETC_SW_CCAR_CRDDOMAIN(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CRDDOMAIN_SHIFT)) & NETC_SW_CCAR_CRDDOMAIN_MASK)
64777 
64778 #define NETC_SW_CCAR_CRDSNP_MASK                 (0x40000000U)
64779 #define NETC_SW_CCAR_CRDSNP_SHIFT                (30U)
64780 #define NETC_SW_CCAR_CRDSNP(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_CCAR_CRDSNP_SHIFT)) & NETC_SW_CCAR_CRDSNP_MASK)
64781 /*! @} */
64782 
64783 /*! @name MPCR - Management port configuration register */
64784 /*! @{ */
64785 
64786 #define NETC_SW_MPCR_PORT_MASK                   (0x1FU)
64787 #define NETC_SW_MPCR_PORT_SHIFT                  (0U)
64788 /*! PORT - Switch Management Port */
64789 #define NETC_SW_MPCR_PORT(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_SW_MPCR_PORT_SHIFT)) & NETC_SW_MPCR_PORT_MASK)
64790 /*! @} */
64791 
64792 /*! @name IMDCR0 - Ingress mirror destination configuration register 0 */
64793 /*! @{ */
64794 
64795 #define NETC_SW_IMDCR0_MIREN_MASK                (0x1U)
64796 #define NETC_SW_IMDCR0_MIREN_SHIFT               (0U)
64797 /*! MIREN - Mirror enable.
64798  *  0b0..Ingress mirroring disabled
64799  *  0b1..Ingress mirroring enabled
64800  */
64801 #define NETC_SW_IMDCR0_MIREN(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_MIREN_SHIFT)) & NETC_SW_IMDCR0_MIREN_MASK)
64802 
64803 #define NETC_SW_IMDCR0_MIRDEST_MASK              (0x2U)
64804 #define NETC_SW_IMDCR0_MIRDEST_SHIFT             (1U)
64805 /*! MIRDEST - Indicates the mirror destination */
64806 #define NETC_SW_IMDCR0_MIRDEST(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_MIRDEST_SHIFT)) & NETC_SW_IMDCR0_MIRDEST_MASK)
64807 
64808 #define NETC_SW_IMDCR0_IPV_MASK                  (0x1CU)
64809 #define NETC_SW_IMDCR0_IPV_SHIFT                 (2U)
64810 #define NETC_SW_IMDCR0_IPV(x)                    (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_IPV_SHIFT)) & NETC_SW_IMDCR0_IPV_MASK)
64811 
64812 #define NETC_SW_IMDCR0_DR_MASK                   (0xC0U)
64813 #define NETC_SW_IMDCR0_DR_SHIFT                  (6U)
64814 #define NETC_SW_IMDCR0_DR(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_DR_SHIFT)) & NETC_SW_IMDCR0_DR_MASK)
64815 
64816 #define NETC_SW_IMDCR0_PORT_MASK                 (0x1F00U)
64817 #define NETC_SW_IMDCR0_PORT_SHIFT                (8U)
64818 #define NETC_SW_IMDCR0_PORT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR0_PORT_SHIFT)) & NETC_SW_IMDCR0_PORT_MASK)
64819 /*! @} */
64820 
64821 /*! @name IMDCR1 - Ingress mirror destination configuration register 1 */
64822 /*! @{ */
64823 
64824 #define NETC_SW_IMDCR1_EFMEID_MASK               (0xFFFFU)
64825 #define NETC_SW_IMDCR1_EFMEID_SHIFT              (0U)
64826 #define NETC_SW_IMDCR1_EFMEID(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR1_EFMEID_SHIFT)) & NETC_SW_IMDCR1_EFMEID_MASK)
64827 
64828 #define NETC_SW_IMDCR1_EFM_LEN_CHANGE_MASK       (0x7F0000U)
64829 #define NETC_SW_IMDCR1_EFM_LEN_CHANGE_SHIFT      (16U)
64830 #define NETC_SW_IMDCR1_EFM_LEN_CHANGE(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_IMDCR1_EFM_LEN_CHANGE_SHIFT)) & NETC_SW_IMDCR1_EFM_LEN_CHANGE_MASK)
64831 /*! @} */
64832 
64833 /*! @name CTFCR - Cut-through forwarding count register */
64834 /*! @{ */
64835 
64836 #define NETC_SW_CTFCR_COUNT_MASK                 (0xFFFFFFFFU)
64837 #define NETC_SW_CTFCR_COUNT_SHIFT                (0U)
64838 #define NETC_SW_CTFCR_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_CTFCR_COUNT_SHIFT)) & NETC_SW_CTFCR_COUNT_MASK)
64839 /*! @} */
64840 
64841 /*! @name CBDRMR - Command BDR 0 mode register..Command BDR 1 mode register */
64842 /*! @{ */
64843 
64844 #define NETC_SW_CBDRMR_EN_MASK                   (0x80000000U)
64845 #define NETC_SW_CBDRMR_EN_SHIFT                  (31U)
64846 /*! EN - Enable command buffer descriptor ring
64847  *  0b0..Disabled
64848  *  0b1..Enabled. When the ring is non-empty, command buffer descriptors will be processed
64849  */
64850 #define NETC_SW_CBDRMR_EN(x)                     (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRMR_EN_SHIFT)) & NETC_SW_CBDRMR_EN_MASK)
64851 /*! @} */
64852 
64853 /* The count of NETC_SW_CBDRMR */
64854 #define NETC_SW_CBDRMR_COUNT                     (2U)
64855 
64856 /*! @name CBDRSR - Command BDR 0 status register..Command BDR 1 status register */
64857 /*! @{ */
64858 
64859 #define NETC_SW_CBDRSR_BUSY_MASK                 (0x1U)
64860 #define NETC_SW_CBDRSR_BUSY_SHIFT                (0U)
64861 /*! BUSY - Busy.
64862  *  0b0..Idle
64863  *  0b1..Busy
64864  */
64865 #define NETC_SW_CBDRSR_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRSR_BUSY_SHIFT)) & NETC_SW_CBDRSR_BUSY_MASK)
64866 /*! @} */
64867 
64868 /* The count of NETC_SW_CBDRSR */
64869 #define NETC_SW_CBDRSR_COUNT                     (2U)
64870 
64871 /*! @name CBDRBAR0 - Command BDR base address register 0 */
64872 /*! @{ */
64873 
64874 #define NETC_SW_CBDRBAR0_ADDRL_MASK              (0xFFFFFF80U)
64875 #define NETC_SW_CBDRBAR0_ADDRL_SHIFT             (7U)
64876 #define NETC_SW_CBDRBAR0_ADDRL(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRBAR0_ADDRL_SHIFT)) & NETC_SW_CBDRBAR0_ADDRL_MASK)
64877 /*! @} */
64878 
64879 /* The count of NETC_SW_CBDRBAR0 */
64880 #define NETC_SW_CBDRBAR0_COUNT                   (2U)
64881 
64882 /*! @name CBDRBAR1 - Command BDR 0 base address register 1..Command BDR 1 base address register 1 */
64883 /*! @{ */
64884 
64885 #define NETC_SW_CBDRBAR1_ADDRH_MASK              (0xFFFFFFFFU)
64886 #define NETC_SW_CBDRBAR1_ADDRH_SHIFT             (0U)
64887 #define NETC_SW_CBDRBAR1_ADDRH(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRBAR1_ADDRH_SHIFT)) & NETC_SW_CBDRBAR1_ADDRH_MASK)
64888 /*! @} */
64889 
64890 /* The count of NETC_SW_CBDRBAR1 */
64891 #define NETC_SW_CBDRBAR1_COUNT                   (2U)
64892 
64893 /*! @name CBDRPIR - Command BDR 0 producer index register..Command BDR 1 producer index register */
64894 /*! @{ */
64895 
64896 #define NETC_SW_CBDRPIR_BDR_INDEX_MASK           (0x3FFU)
64897 #define NETC_SW_CBDRPIR_BDR_INDEX_SHIFT          (0U)
64898 #define NETC_SW_CBDRPIR_BDR_INDEX(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRPIR_BDR_INDEX_SHIFT)) & NETC_SW_CBDRPIR_BDR_INDEX_MASK)
64899 /*! @} */
64900 
64901 /* The count of NETC_SW_CBDRPIR */
64902 #define NETC_SW_CBDRPIR_COUNT                    (2U)
64903 
64904 /*! @name CBDRCIR - Command BDR 0 consumer index register..Command BDR 1 consumer index register */
64905 /*! @{ */
64906 
64907 #define NETC_SW_CBDRCIR_BDR_INDEX_MASK           (0x3FFU)
64908 #define NETC_SW_CBDRCIR_BDR_INDEX_SHIFT          (0U)
64909 #define NETC_SW_CBDRCIR_BDR_INDEX(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRCIR_BDR_INDEX_SHIFT)) & NETC_SW_CBDRCIR_BDR_INDEX_MASK)
64910 /*! @} */
64911 
64912 /* The count of NETC_SW_CBDRCIR */
64913 #define NETC_SW_CBDRCIR_COUNT                    (2U)
64914 
64915 /*! @name CBDRLENR - Command BDR 0 length register..Command BDR 1 length register */
64916 /*! @{ */
64917 
64918 #define NETC_SW_CBDRLENR_LENGTH_MASK             (0x7F8U)
64919 #define NETC_SW_CBDRLENR_LENGTH_SHIFT            (3U)
64920 #define NETC_SW_CBDRLENR_LENGTH(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRLENR_LENGTH_SHIFT)) & NETC_SW_CBDRLENR_LENGTH_MASK)
64921 /*! @} */
64922 
64923 /* The count of NETC_SW_CBDRLENR */
64924 #define NETC_SW_CBDRLENR_COUNT                   (2U)
64925 
64926 /*! @name CBDRIER - Command BDR 0 interrupt enable register..Command BDR 1 interrupt enable register */
64927 /*! @{ */
64928 
64929 #define NETC_SW_CBDRIER_CBDCIE_MASK              (0x1U)
64930 #define NETC_SW_CBDRIER_CBDCIE_SHIFT             (0U)
64931 #define NETC_SW_CBDRIER_CBDCIE(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRIER_CBDCIE_SHIFT)) & NETC_SW_CBDRIER_CBDCIE_MASK)
64932 /*! @} */
64933 
64934 /* The count of NETC_SW_CBDRIER */
64935 #define NETC_SW_CBDRIER_COUNT                    (2U)
64936 
64937 /*! @name CBDRIDR - Command BDR 0 interrupt detect register..Command BDR 1 interrupt detect register */
64938 /*! @{ */
64939 
64940 #define NETC_SW_CBDRIDR_CBDC_MASK                (0x1U)
64941 #define NETC_SW_CBDRIDR_CBDC_SHIFT               (0U)
64942 /*! CBDC
64943  *  0b0..No BD with CI=1 completed
64944  *  0b1..Processed BD with CI=1
64945  */
64946 #define NETC_SW_CBDRIDR_CBDC(x)                  (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRIDR_CBDC_SHIFT)) & NETC_SW_CBDRIDR_CBDC_MASK)
64947 /*! @} */
64948 
64949 /* The count of NETC_SW_CBDRIDR */
64950 #define NETC_SW_CBDRIDR_COUNT                    (2U)
64951 
64952 /*! @name CBDRMSIVR - Command BDR 0 MSI-X vector register..Command BDR 1 MSI-X vector register */
64953 /*! @{ */
64954 
64955 #define NETC_SW_CBDRMSIVR_VECTOR_MASK            (0xFU)
64956 #define NETC_SW_CBDRMSIVR_VECTOR_SHIFT           (0U)
64957 #define NETC_SW_CBDRMSIVR_VECTOR(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_CBDRMSIVR_VECTOR_SHIFT)) & NETC_SW_CBDRMSIVR_VECTOR_MASK)
64958 /*! @} */
64959 
64960 /* The count of NETC_SW_CBDRMSIVR */
64961 #define NETC_SW_CBDRMSIVR_COUNT                  (2U)
64962 
64963 /*! @name QOSVLANMPR - QoS to VLAN mapping profile 0 register 0..QoS to VLAN mapping profile 1 register 3 */
64964 /*! @{ */
64965 
64966 #define NETC_SW_QOSVLANMPR_IPV0_DR0_MASK         (0xFU)
64967 #define NETC_SW_QOSVLANMPR_IPV0_DR0_SHIFT        (0U)
64968 #define NETC_SW_QOSVLANMPR_IPV0_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV0_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV0_DR0_MASK)
64969 
64970 #define NETC_SW_QOSVLANMPR_IPV2_DR0_MASK         (0xFU)
64971 #define NETC_SW_QOSVLANMPR_IPV2_DR0_SHIFT        (0U)
64972 #define NETC_SW_QOSVLANMPR_IPV2_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV2_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV2_DR0_MASK)
64973 
64974 #define NETC_SW_QOSVLANMPR_IPV4_DR0_MASK         (0xFU)
64975 #define NETC_SW_QOSVLANMPR_IPV4_DR0_SHIFT        (0U)
64976 #define NETC_SW_QOSVLANMPR_IPV4_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV4_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV4_DR0_MASK)
64977 
64978 #define NETC_SW_QOSVLANMPR_IPV6_DR0_MASK         (0xFU)
64979 #define NETC_SW_QOSVLANMPR_IPV6_DR0_SHIFT        (0U)
64980 #define NETC_SW_QOSVLANMPR_IPV6_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV6_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV6_DR0_MASK)
64981 
64982 #define NETC_SW_QOSVLANMPR_IPV0_DR1_MASK         (0xF0U)
64983 #define NETC_SW_QOSVLANMPR_IPV0_DR1_SHIFT        (4U)
64984 #define NETC_SW_QOSVLANMPR_IPV0_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV0_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV0_DR1_MASK)
64985 
64986 #define NETC_SW_QOSVLANMPR_IPV2_DR1_MASK         (0xF0U)
64987 #define NETC_SW_QOSVLANMPR_IPV2_DR1_SHIFT        (4U)
64988 #define NETC_SW_QOSVLANMPR_IPV2_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV2_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV2_DR1_MASK)
64989 
64990 #define NETC_SW_QOSVLANMPR_IPV4_DR1_MASK         (0xF0U)
64991 #define NETC_SW_QOSVLANMPR_IPV4_DR1_SHIFT        (4U)
64992 #define NETC_SW_QOSVLANMPR_IPV4_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV4_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV4_DR1_MASK)
64993 
64994 #define NETC_SW_QOSVLANMPR_IPV6_DR1_MASK         (0xF0U)
64995 #define NETC_SW_QOSVLANMPR_IPV6_DR1_SHIFT        (4U)
64996 #define NETC_SW_QOSVLANMPR_IPV6_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV6_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV6_DR1_MASK)
64997 
64998 #define NETC_SW_QOSVLANMPR_IPV0_DR2_MASK         (0xF00U)
64999 #define NETC_SW_QOSVLANMPR_IPV0_DR2_SHIFT        (8U)
65000 #define NETC_SW_QOSVLANMPR_IPV0_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV0_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV0_DR2_MASK)
65001 
65002 #define NETC_SW_QOSVLANMPR_IPV2_DR2_MASK         (0xF00U)
65003 #define NETC_SW_QOSVLANMPR_IPV2_DR2_SHIFT        (8U)
65004 #define NETC_SW_QOSVLANMPR_IPV2_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV2_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV2_DR2_MASK)
65005 
65006 #define NETC_SW_QOSVLANMPR_IPV4_DR2_MASK         (0xF00U)
65007 #define NETC_SW_QOSVLANMPR_IPV4_DR2_SHIFT        (8U)
65008 #define NETC_SW_QOSVLANMPR_IPV4_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV4_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV4_DR2_MASK)
65009 
65010 #define NETC_SW_QOSVLANMPR_IPV6_DR2_MASK         (0xF00U)
65011 #define NETC_SW_QOSVLANMPR_IPV6_DR2_SHIFT        (8U)
65012 #define NETC_SW_QOSVLANMPR_IPV6_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV6_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV6_DR2_MASK)
65013 
65014 #define NETC_SW_QOSVLANMPR_IPV0_DR3_MASK         (0xF000U)
65015 #define NETC_SW_QOSVLANMPR_IPV0_DR3_SHIFT        (12U)
65016 #define NETC_SW_QOSVLANMPR_IPV0_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV0_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV0_DR3_MASK)
65017 
65018 #define NETC_SW_QOSVLANMPR_IPV2_DR3_MASK         (0xF000U)
65019 #define NETC_SW_QOSVLANMPR_IPV2_DR3_SHIFT        (12U)
65020 #define NETC_SW_QOSVLANMPR_IPV2_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV2_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV2_DR3_MASK)
65021 
65022 #define NETC_SW_QOSVLANMPR_IPV4_DR3_MASK         (0xF000U)
65023 #define NETC_SW_QOSVLANMPR_IPV4_DR3_SHIFT        (12U)
65024 #define NETC_SW_QOSVLANMPR_IPV4_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV4_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV4_DR3_MASK)
65025 
65026 #define NETC_SW_QOSVLANMPR_IPV6_DR3_MASK         (0xF000U)
65027 #define NETC_SW_QOSVLANMPR_IPV6_DR3_SHIFT        (12U)
65028 #define NETC_SW_QOSVLANMPR_IPV6_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV6_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV6_DR3_MASK)
65029 
65030 #define NETC_SW_QOSVLANMPR_IPV1_DR0_MASK         (0xF0000U)
65031 #define NETC_SW_QOSVLANMPR_IPV1_DR0_SHIFT        (16U)
65032 #define NETC_SW_QOSVLANMPR_IPV1_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV1_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV1_DR0_MASK)
65033 
65034 #define NETC_SW_QOSVLANMPR_IPV3_DR0_MASK         (0xF0000U)
65035 #define NETC_SW_QOSVLANMPR_IPV3_DR0_SHIFT        (16U)
65036 #define NETC_SW_QOSVLANMPR_IPV3_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV3_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV3_DR0_MASK)
65037 
65038 #define NETC_SW_QOSVLANMPR_IPV5_DR0_MASK         (0xF0000U)
65039 #define NETC_SW_QOSVLANMPR_IPV5_DR0_SHIFT        (16U)
65040 #define NETC_SW_QOSVLANMPR_IPV5_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV5_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV5_DR0_MASK)
65041 
65042 #define NETC_SW_QOSVLANMPR_IPV7_DR0_MASK         (0xF0000U)
65043 #define NETC_SW_QOSVLANMPR_IPV7_DR0_SHIFT        (16U)
65044 #define NETC_SW_QOSVLANMPR_IPV7_DR0(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV7_DR0_SHIFT)) & NETC_SW_QOSVLANMPR_IPV7_DR0_MASK)
65045 
65046 #define NETC_SW_QOSVLANMPR_IPV1_DR1_MASK         (0xF00000U)
65047 #define NETC_SW_QOSVLANMPR_IPV1_DR1_SHIFT        (20U)
65048 #define NETC_SW_QOSVLANMPR_IPV1_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV1_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV1_DR1_MASK)
65049 
65050 #define NETC_SW_QOSVLANMPR_IPV3_DR1_MASK         (0xF00000U)
65051 #define NETC_SW_QOSVLANMPR_IPV3_DR1_SHIFT        (20U)
65052 #define NETC_SW_QOSVLANMPR_IPV3_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV3_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV3_DR1_MASK)
65053 
65054 #define NETC_SW_QOSVLANMPR_IPV5_DR1_MASK         (0xF00000U)
65055 #define NETC_SW_QOSVLANMPR_IPV5_DR1_SHIFT        (20U)
65056 #define NETC_SW_QOSVLANMPR_IPV5_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV5_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV5_DR1_MASK)
65057 
65058 #define NETC_SW_QOSVLANMPR_IPV7_DR1_MASK         (0xF00000U)
65059 #define NETC_SW_QOSVLANMPR_IPV7_DR1_SHIFT        (20U)
65060 #define NETC_SW_QOSVLANMPR_IPV7_DR1(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV7_DR1_SHIFT)) & NETC_SW_QOSVLANMPR_IPV7_DR1_MASK)
65061 
65062 #define NETC_SW_QOSVLANMPR_IPV1_DR2_MASK         (0xF000000U)
65063 #define NETC_SW_QOSVLANMPR_IPV1_DR2_SHIFT        (24U)
65064 #define NETC_SW_QOSVLANMPR_IPV1_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV1_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV1_DR2_MASK)
65065 
65066 #define NETC_SW_QOSVLANMPR_IPV3_DR2_MASK         (0xF000000U)
65067 #define NETC_SW_QOSVLANMPR_IPV3_DR2_SHIFT        (24U)
65068 #define NETC_SW_QOSVLANMPR_IPV3_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV3_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV3_DR2_MASK)
65069 
65070 #define NETC_SW_QOSVLANMPR_IPV5_DR2_MASK         (0xF000000U)
65071 #define NETC_SW_QOSVLANMPR_IPV5_DR2_SHIFT        (24U)
65072 #define NETC_SW_QOSVLANMPR_IPV5_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV5_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV5_DR2_MASK)
65073 
65074 #define NETC_SW_QOSVLANMPR_IPV7_DR2_MASK         (0xF000000U)
65075 #define NETC_SW_QOSVLANMPR_IPV7_DR2_SHIFT        (24U)
65076 #define NETC_SW_QOSVLANMPR_IPV7_DR2(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV7_DR2_SHIFT)) & NETC_SW_QOSVLANMPR_IPV7_DR2_MASK)
65077 
65078 #define NETC_SW_QOSVLANMPR_IPV1_DR3_MASK         (0xF0000000U)
65079 #define NETC_SW_QOSVLANMPR_IPV1_DR3_SHIFT        (28U)
65080 #define NETC_SW_QOSVLANMPR_IPV1_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV1_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV1_DR3_MASK)
65081 
65082 #define NETC_SW_QOSVLANMPR_IPV3_DR3_MASK         (0xF0000000U)
65083 #define NETC_SW_QOSVLANMPR_IPV3_DR3_SHIFT        (28U)
65084 #define NETC_SW_QOSVLANMPR_IPV3_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV3_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV3_DR3_MASK)
65085 
65086 #define NETC_SW_QOSVLANMPR_IPV5_DR3_MASK         (0xF0000000U)
65087 #define NETC_SW_QOSVLANMPR_IPV5_DR3_SHIFT        (28U)
65088 #define NETC_SW_QOSVLANMPR_IPV5_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV5_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV5_DR3_MASK)
65089 
65090 #define NETC_SW_QOSVLANMPR_IPV7_DR3_MASK         (0xF0000000U)
65091 #define NETC_SW_QOSVLANMPR_IPV7_DR3_SHIFT        (28U)
65092 #define NETC_SW_QOSVLANMPR_IPV7_DR3(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_QOSVLANMPR_IPV7_DR3_SHIFT)) & NETC_SW_QOSVLANMPR_IPV7_DR3_MASK)
65093 /*! @} */
65094 
65095 /* The count of NETC_SW_QOSVLANMPR */
65096 #define NETC_SW_QOSVLANMPR_COUNT                 (2U)
65097 
65098 /* The count of NETC_SW_QOSVLANMPR */
65099 #define NETC_SW_QOSVLANMPR_COUNT2                (4U)
65100 
65101 /*! @name PCP2PCPMPR - PCP to PCP mapping profile 0 register..PCP to PCP mapping profile 1 register */
65102 /*! @{ */
65103 
65104 #define NETC_SW_PCP2PCPMPR_PCP0_MASK             (0x7U)
65105 #define NETC_SW_PCP2PCPMPR_PCP0_SHIFT            (0U)
65106 #define NETC_SW_PCP2PCPMPR_PCP0(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP0_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP0_MASK)
65107 
65108 #define NETC_SW_PCP2PCPMPR_PCP1_MASK             (0x70U)
65109 #define NETC_SW_PCP2PCPMPR_PCP1_SHIFT            (4U)
65110 #define NETC_SW_PCP2PCPMPR_PCP1(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP1_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP1_MASK)
65111 
65112 #define NETC_SW_PCP2PCPMPR_PCP2_MASK             (0x700U)
65113 #define NETC_SW_PCP2PCPMPR_PCP2_SHIFT            (8U)
65114 #define NETC_SW_PCP2PCPMPR_PCP2(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP2_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP2_MASK)
65115 
65116 #define NETC_SW_PCP2PCPMPR_PCP3_MASK             (0x7000U)
65117 #define NETC_SW_PCP2PCPMPR_PCP3_SHIFT            (12U)
65118 #define NETC_SW_PCP2PCPMPR_PCP3(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP3_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP3_MASK)
65119 
65120 #define NETC_SW_PCP2PCPMPR_PCP4_MASK             (0x70000U)
65121 #define NETC_SW_PCP2PCPMPR_PCP4_SHIFT            (16U)
65122 #define NETC_SW_PCP2PCPMPR_PCP4(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP4_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP4_MASK)
65123 
65124 #define NETC_SW_PCP2PCPMPR_PCP5_MASK             (0x700000U)
65125 #define NETC_SW_PCP2PCPMPR_PCP5_SHIFT            (20U)
65126 #define NETC_SW_PCP2PCPMPR_PCP5(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP5_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP5_MASK)
65127 
65128 #define NETC_SW_PCP2PCPMPR_PCP6_MASK             (0x7000000U)
65129 #define NETC_SW_PCP2PCPMPR_PCP6_SHIFT            (24U)
65130 #define NETC_SW_PCP2PCPMPR_PCP6(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP6_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP6_MASK)
65131 
65132 #define NETC_SW_PCP2PCPMPR_PCP7_MASK             (0x70000000U)
65133 #define NETC_SW_PCP2PCPMPR_PCP7_SHIFT            (28U)
65134 #define NETC_SW_PCP2PCPMPR_PCP7(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_PCP2PCPMPR_PCP7_SHIFT)) & NETC_SW_PCP2PCPMPR_PCP7_MASK)
65135 /*! @} */
65136 
65137 /* The count of NETC_SW_PCP2PCPMPR */
65138 #define NETC_SW_PCP2PCPMPR_COUNT                 (2U)
65139 
65140 /*! @name BRCAPR - Bridge capability register */
65141 /*! @{ */
65142 
65143 #define NETC_SW_BRCAPR_IPV4MFLT_MASK             (0x1U)
65144 #define NETC_SW_BRCAPR_IPV4MFLT_SHIFT            (0U)
65145 /*! IPV4MFLT - L2 IPv4 multicast filtering supported.
65146  *  0b0..Not supported
65147  *  0b1..Supported
65148  */
65149 #define NETC_SW_BRCAPR_IPV4MFLT(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_IPV4MFLT_SHIFT)) & NETC_SW_BRCAPR_IPV4MFLT_MASK)
65150 
65151 #define NETC_SW_BRCAPR_STAMVD_MASK               (0x4U)
65152 #define NETC_SW_BRCAPR_STAMVD_SHIFT              (2U)
65153 /*! STAMVD - Station Move Disable supported
65154  *  0b0..Not supported
65155  *  0b1..Supported
65156  */
65157 #define NETC_SW_BRCAPR_STAMVD(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_STAMVD_SHIFT)) & NETC_SW_BRCAPR_STAMVD_MASK)
65158 
65159 #define NETC_SW_BRCAPR_STRMCTRL_MASK             (0x8U)
65160 #define NETC_SW_BRCAPR_STRMCTRL_SHIFT            (3U)
65161 /*! STRMCTRL - Storm Control supported.
65162  *  0b0..Not supported
65163  *  0b1..Supported
65164  */
65165 #define NETC_SW_BRCAPR_STRMCTRL(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_STRMCTRL_SHIFT)) & NETC_SW_BRCAPR_STRMCTRL_MASK)
65166 
65167 #define NETC_SW_BRCAPR_SRCPPRND_MASK             (0x10U)
65168 #define NETC_SW_BRCAPR_SRCPPRND_SHIFT            (4U)
65169 /*! SRCPPRND - Source port pruning disable supported
65170  *  0b0..Source port pruning disable not supported
65171  *  0b1..Source port pruning disable supported
65172  */
65173 #define NETC_SW_BRCAPR_SRCPPRND(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_SRCPPRND_SHIFT)) & NETC_SW_BRCAPR_SRCPPRND_MASK)
65174 
65175 #define NETC_SW_BRCAPR_EVLANXLATE_MASK           (0x20U)
65176 #define NETC_SW_BRCAPR_EVLANXLATE_SHIFT          (5U)
65177 /*! EVLANXLATE - Egress VLAN translation supported
65178  *  0b0..Egress VLAN translation not supported
65179  *  0b1..Egress VLAN translation supported
65180  */
65181 #define NETC_SW_BRCAPR_EVLANXLATE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_EVLANXLATE_SHIFT)) & NETC_SW_BRCAPR_EVLANXLATE_MASK)
65182 
65183 #define NETC_SW_BRCAPR_NUM_STG_MASK              (0x3000U)
65184 #define NETC_SW_BRCAPR_NUM_STG_SHIFT             (12U)
65185 #define NETC_SW_BRCAPR_NUM_STG(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_BRCAPR_NUM_STG_SHIFT)) & NETC_SW_BRCAPR_NUM_STG_MASK)
65186 /*! @} */
65187 
65188 /*! @name VFHTCAPR - VLAN filter hash table capability register */
65189 /*! @{ */
65190 
65191 #define NETC_SW_VFHTCAPR_ACCESS_METH_MASK        (0xF00000U)
65192 #define NETC_SW_VFHTCAPR_ACCESS_METH_SHIFT       (20U)
65193 #define NETC_SW_VFHTCAPR_ACCESS_METH(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_VFHTCAPR_ACCESS_METH_MASK)
65194 /*! @} */
65195 
65196 /*! @name VFHTOR - VLAN filter hash table operational register */
65197 /*! @{ */
65198 
65199 #define NETC_SW_VFHTOR_NUM_ENTRIES_MASK          (0xFFFU)
65200 #define NETC_SW_VFHTOR_NUM_ENTRIES_SHIFT         (0U)
65201 #define NETC_SW_VFHTOR_NUM_ENTRIES(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTOR_NUM_ENTRIES_SHIFT)) & NETC_SW_VFHTOR_NUM_ENTRIES_MASK)
65202 /*! @} */
65203 
65204 /*! @name VFHTDECR0 - VLAN Filter (hash) table default entry configuration registers 0 */
65205 /*! @{ */
65206 
65207 #define NETC_SW_VFHTDECR0_PORT0_MASK             (0x1U)
65208 #define NETC_SW_VFHTDECR0_PORT0_SHIFT            (0U)
65209 /*! PORT0 - Port n
65210  *  0b0..Port is not a member of this VLAN.
65211  *  0b1..Port is a member of this VLAN.
65212  */
65213 #define NETC_SW_VFHTDECR0_PORT0(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_PORT0_SHIFT)) & NETC_SW_VFHTDECR0_PORT0_MASK)
65214 
65215 #define NETC_SW_VFHTDECR0_PORT1_MASK             (0x2U)
65216 #define NETC_SW_VFHTDECR0_PORT1_SHIFT            (1U)
65217 /*! PORT1 - Port n
65218  *  0b0..Port is not a member of this VLAN.
65219  *  0b1..Port is a member of this VLAN.
65220  */
65221 #define NETC_SW_VFHTDECR0_PORT1(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_PORT1_SHIFT)) & NETC_SW_VFHTDECR0_PORT1_MASK)
65222 
65223 #define NETC_SW_VFHTDECR0_PORT2_MASK             (0x4U)
65224 #define NETC_SW_VFHTDECR0_PORT2_SHIFT            (2U)
65225 /*! PORT2 - Port n
65226  *  0b0..Port is not a member of this VLAN.
65227  *  0b1..Port is a member of this VLAN.
65228  */
65229 #define NETC_SW_VFHTDECR0_PORT2(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_PORT2_SHIFT)) & NETC_SW_VFHTDECR0_PORT2_MASK)
65230 
65231 #define NETC_SW_VFHTDECR0_PORT3_MASK             (0x8U)
65232 #define NETC_SW_VFHTDECR0_PORT3_SHIFT            (3U)
65233 /*! PORT3 - Port n
65234  *  0b0..Port is not a member of this VLAN.
65235  *  0b1..Port is a member of this VLAN.
65236  */
65237 #define NETC_SW_VFHTDECR0_PORT3(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_PORT3_SHIFT)) & NETC_SW_VFHTDECR0_PORT3_MASK)
65238 
65239 #define NETC_SW_VFHTDECR0_PORT4_MASK             (0x10U)
65240 #define NETC_SW_VFHTDECR0_PORT4_SHIFT            (4U)
65241 /*! PORT4 - Port n
65242  *  0b0..Port is not a member of this VLAN.
65243  *  0b1..Port is a member of this VLAN.
65244  */
65245 #define NETC_SW_VFHTDECR0_PORT4(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_PORT4_SHIFT)) & NETC_SW_VFHTDECR0_PORT4_MASK)
65246 
65247 #define NETC_SW_VFHTDECR0_STG_ID_MASK            (0xF000000U)
65248 #define NETC_SW_VFHTDECR0_STG_ID_SHIFT           (24U)
65249 #define NETC_SW_VFHTDECR0_STG_ID(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_STG_ID_SHIFT)) & NETC_SW_VFHTDECR0_STG_ID_MASK)
65250 
65251 #define NETC_SW_VFHTDECR0_IPMFE_MASK             (0x20000000U)
65252 #define NETC_SW_VFHTDECR0_IPMFE_SHIFT            (29U)
65253 /*! IPMFE - IP Multicast Filtering Enable
65254  *  0b0..No IP multicast filtering is performed.
65255  *  0b1..If the frame is identified as a multicast IP packet, then IP multicast filtering is performed. If the
65256  *       frame is not identified as an IP multicast packet, the IP multicast filtering is not performed.
65257  */
65258 #define NETC_SW_VFHTDECR0_IPMFE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_IPMFE_SHIFT)) & NETC_SW_VFHTDECR0_IPMFE_MASK)
65259 
65260 #define NETC_SW_VFHTDECR0_IPMFLE_MASK            (0x40000000U)
65261 #define NETC_SW_VFHTDECR0_IPMFLE_SHIFT           (30U)
65262 /*! IPMFLE - IP Multicast Flooding Enable
65263  *  0b0..IP Multicast Flooding disabled, the frame is discarded.
65264  *  0b1..IP Multicast Flooding enabled, the frame is flooded.
65265  */
65266 #define NETC_SW_VFHTDECR0_IPMFLE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR0_IPMFLE_SHIFT)) & NETC_SW_VFHTDECR0_IPMFLE_MASK)
65267 /*! @} */
65268 
65269 /*! @name VFHTDECR1 - VLAN filter hash table default entry configuration registers 1 */
65270 /*! @{ */
65271 
65272 #define NETC_SW_VFHTDECR1_FID_MASK               (0xFFFU)
65273 #define NETC_SW_VFHTDECR1_FID_SHIFT              (0U)
65274 #define NETC_SW_VFHTDECR1_FID(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR1_FID_SHIFT)) & NETC_SW_VFHTDECR1_FID_MASK)
65275 
65276 #define NETC_SW_VFHTDECR1_VL_MODE_MASK           (0x1000U)
65277 #define NETC_SW_VFHTDECR1_VL_MODE_SHIFT          (12U)
65278 #define NETC_SW_VFHTDECR1_VL_MODE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR1_VL_MODE_SHIFT)) & NETC_SW_VFHTDECR1_VL_MODE_MASK)
65279 
65280 #define NETC_SW_VFHTDECR1_BASE_ETEID_MASK        (0xFFFF0000U)
65281 #define NETC_SW_VFHTDECR1_BASE_ETEID_SHIFT       (16U)
65282 #define NETC_SW_VFHTDECR1_BASE_ETEID(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR1_BASE_ETEID_SHIFT)) & NETC_SW_VFHTDECR1_BASE_ETEID_MASK)
65283 /*! @} */
65284 
65285 /*! @name VFHTDECR2 - VLAN filter hash table default entry configuration registers 2 */
65286 /*! @{ */
65287 
65288 #define NETC_SW_VFHTDECR2_ET_PORT0_MASK          (0x1U)
65289 #define NETC_SW_VFHTDECR2_ET_PORT0_SHIFT         (0U)
65290 /*! ET_PORT0 - Egress Treatment Applicability Port n.
65291  *  0b0..Port has no entry in the Egress Treatment table
65292  *  0b1..Port has an entry in the Egress Treatment table
65293  */
65294 #define NETC_SW_VFHTDECR2_ET_PORT0(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_ET_PORT0_SHIFT)) & NETC_SW_VFHTDECR2_ET_PORT0_MASK)
65295 
65296 #define NETC_SW_VFHTDECR2_ET_PORT1_MASK          (0x2U)
65297 #define NETC_SW_VFHTDECR2_ET_PORT1_SHIFT         (1U)
65298 /*! ET_PORT1 - Egress Treatment Applicability Port n.
65299  *  0b0..Port has no entry in the Egress Treatment table
65300  *  0b1..Port has an entry in the Egress Treatment table
65301  */
65302 #define NETC_SW_VFHTDECR2_ET_PORT1(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_ET_PORT1_SHIFT)) & NETC_SW_VFHTDECR2_ET_PORT1_MASK)
65303 
65304 #define NETC_SW_VFHTDECR2_ET_PORT2_MASK          (0x4U)
65305 #define NETC_SW_VFHTDECR2_ET_PORT2_SHIFT         (2U)
65306 /*! ET_PORT2 - Egress Treatment Applicability Port n.
65307  *  0b0..Port has no entry in the Egress Treatment table
65308  *  0b1..Port has an entry in the Egress Treatment table
65309  */
65310 #define NETC_SW_VFHTDECR2_ET_PORT2(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_ET_PORT2_SHIFT)) & NETC_SW_VFHTDECR2_ET_PORT2_MASK)
65311 
65312 #define NETC_SW_VFHTDECR2_ET_PORT3_MASK          (0x8U)
65313 #define NETC_SW_VFHTDECR2_ET_PORT3_SHIFT         (3U)
65314 /*! ET_PORT3 - Egress Treatment Applicability Port n.
65315  *  0b0..Port has no entry in the Egress Treatment table
65316  *  0b1..Port has an entry in the Egress Treatment table
65317  */
65318 #define NETC_SW_VFHTDECR2_ET_PORT3(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_ET_PORT3_SHIFT)) & NETC_SW_VFHTDECR2_ET_PORT3_MASK)
65319 
65320 #define NETC_SW_VFHTDECR2_ET_PORT4_MASK          (0x10U)
65321 #define NETC_SW_VFHTDECR2_ET_PORT4_SHIFT         (4U)
65322 /*! ET_PORT4 - Egress Treatment Applicability Port n.
65323  *  0b0..Port has no entry in the Egress Treatment table
65324  *  0b1..Port has an entry in the Egress Treatment table
65325  */
65326 #define NETC_SW_VFHTDECR2_ET_PORT4(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_ET_PORT4_SHIFT)) & NETC_SW_VFHTDECR2_ET_PORT4_MASK)
65327 
65328 #define NETC_SW_VFHTDECR2_MLO_MASK               (0x7000000U)
65329 #define NETC_SW_VFHTDECR2_MLO_SHIFT              (24U)
65330 #define NETC_SW_VFHTDECR2_MLO(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_MLO_SHIFT)) & NETC_SW_VFHTDECR2_MLO_MASK)
65331 
65332 #define NETC_SW_VFHTDECR2_MFO_MASK               (0x18000000U)
65333 #define NETC_SW_VFHTDECR2_MFO_SHIFT              (27U)
65334 #define NETC_SW_VFHTDECR2_MFO(x)                 (((uint32_t)(((uint32_t)(x)) << NETC_SW_VFHTDECR2_MFO_SHIFT)) & NETC_SW_VFHTDECR2_MFO_MASK)
65335 /*! @} */
65336 
65337 /*! @name FDBHTCAPR - FDB hash table capability register */
65338 /*! @{ */
65339 
65340 #define NETC_SW_FDBHTCAPR_NUM_GMAC_MASK          (0x1FFU)
65341 #define NETC_SW_FDBHTCAPR_NUM_GMAC_SHIFT         (0U)
65342 #define NETC_SW_FDBHTCAPR_NUM_GMAC(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTCAPR_NUM_GMAC_SHIFT)) & NETC_SW_FDBHTCAPR_NUM_GMAC_MASK)
65343 
65344 #define NETC_SW_FDBHTCAPR_ACCESS_METH_MASK       (0xF00000U)
65345 #define NETC_SW_FDBHTCAPR_ACCESS_METH_SHIFT      (20U)
65346 #define NETC_SW_FDBHTCAPR_ACCESS_METH(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_FDBHTCAPR_ACCESS_METH_MASK)
65347 /*! @} */
65348 
65349 /*! @name FDBHTMCR - FDB hash table memory configuration register */
65350 /*! @{ */
65351 
65352 #define NETC_SW_FDBHTMCR_DYN_LIMIT_MASK          (0xFFFFU)
65353 #define NETC_SW_FDBHTMCR_DYN_LIMIT_SHIFT         (0U)
65354 #define NETC_SW_FDBHTMCR_DYN_LIMIT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTMCR_DYN_LIMIT_SHIFT)) & NETC_SW_FDBHTMCR_DYN_LIMIT_MASK)
65355 /*! @} */
65356 
65357 /*! @name FDBHTOR0 - FDB hash table operational register 0 */
65358 /*! @{ */
65359 
65360 #define NETC_SW_FDBHTOR0_STATIC_ENTRIES_MASK     (0xFFFFU)
65361 #define NETC_SW_FDBHTOR0_STATIC_ENTRIES_SHIFT    (0U)
65362 #define NETC_SW_FDBHTOR0_STATIC_ENTRIES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTOR0_STATIC_ENTRIES_SHIFT)) & NETC_SW_FDBHTOR0_STATIC_ENTRIES_MASK)
65363 
65364 #define NETC_SW_FDBHTOR0_NUM_GENTRIES_MASK       (0x1FF0000U)
65365 #define NETC_SW_FDBHTOR0_NUM_GENTRIES_SHIFT      (16U)
65366 #define NETC_SW_FDBHTOR0_NUM_GENTRIES(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTOR0_NUM_GENTRIES_SHIFT)) & NETC_SW_FDBHTOR0_NUM_GENTRIES_MASK)
65367 /*! @} */
65368 
65369 /*! @name FDBHTOR1 - FDB hash table operational register 1 */
65370 /*! @{ */
65371 
65372 #define NETC_SW_FDBHTOR1_DYN_ENTRIES_MASK        (0xFFFFU)
65373 #define NETC_SW_FDBHTOR1_DYN_ENTRIES_SHIFT       (0U)
65374 #define NETC_SW_FDBHTOR1_DYN_ENTRIES(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTOR1_DYN_ENTRIES_SHIFT)) & NETC_SW_FDBHTOR1_DYN_ENTRIES_MASK)
65375 
65376 #define NETC_SW_FDBHTOR1_HWM_DYN_ENTRIES_MASK    (0xFFFF0000U)
65377 #define NETC_SW_FDBHTOR1_HWM_DYN_ENTRIES_SHIFT   (16U)
65378 #define NETC_SW_FDBHTOR1_HWM_DYN_ENTRIES(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_FDBHTOR1_HWM_DYN_ENTRIES_SHIFT)) & NETC_SW_FDBHTOR1_HWM_DYN_ENTRIES_MASK)
65379 /*! @} */
65380 
65381 /*! @name IPMFHTCAPR - IP multicast filter hash table capability register */
65382 /*! @{ */
65383 
65384 #define NETC_SW_IPMFHTCAPR_ACCESS_METH_MASK      (0xF00000U)
65385 #define NETC_SW_IPMFHTCAPR_ACCESS_METH_SHIFT     (20U)
65386 #define NETC_SW_IPMFHTCAPR_ACCESS_METH(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_IPMFHTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_IPMFHTCAPR_ACCESS_METH_MASK)
65387 /*! @} */
65388 
65389 /*! @name IPV4MFHTOR - IPv4 multicast filter hash table operation register */
65390 /*! @{ */
65391 
65392 #define NETC_SW_IPV4MFHTOR_ASM_ENTRIES_MASK      (0xFFFFU)
65393 #define NETC_SW_IPV4MFHTOR_ASM_ENTRIES_SHIFT     (0U)
65394 #define NETC_SW_IPV4MFHTOR_ASM_ENTRIES(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_IPV4MFHTOR_ASM_ENTRIES_SHIFT)) & NETC_SW_IPV4MFHTOR_ASM_ENTRIES_MASK)
65395 
65396 #define NETC_SW_IPV4MFHTOR_SSM_ENTRIES_MASK      (0xFFFF0000U)
65397 #define NETC_SW_IPV4MFHTOR_SSM_ENTRIES_SHIFT     (16U)
65398 #define NETC_SW_IPV4MFHTOR_SSM_ENTRIES(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_IPV4MFHTOR_SSM_ENTRIES_SHIFT)) & NETC_SW_IPV4MFHTOR_SSM_ENTRIES_MASK)
65399 /*! @} */
65400 
65401 
65402 /*!
65403  * @}
65404  */ /* end of group NETC_SW_Register_Masks */
65405 
65406 
65407 /* NETC_SW - Peripheral instance base addresses */
65408 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
65409   /** Peripheral SW0_BASE base address */
65410   #define SW0_BASE_BASE                            (0x70A00000u)
65411   /** Peripheral SW0_BASE base address */
65412   #define SW0_BASE_BASE_NS                         (0x60A00000u)
65413   /** Peripheral SW0_BASE base pointer */
65414   #define SW0_BASE                                 ((NETC_SW_Type *)SW0_BASE_BASE)
65415   /** Peripheral SW0_BASE base pointer */
65416   #define SW0_BASE_NS                              ((NETC_SW_Type *)SW0_BASE_BASE_NS)
65417   /** Array initializer of NETC_SW peripheral base addresses */
65418   #define NETC_SW_BASE_ADDRS                       { SW0_BASE_BASE }
65419   /** Array initializer of NETC_SW peripheral base pointers */
65420   #define NETC_SW_BASE_PTRS                        { SW0_BASE }
65421   /** Array initializer of NETC_SW peripheral base addresses */
65422   #define NETC_SW_BASE_ADDRS_NS                    { SW0_BASE_BASE_NS }
65423   /** Array initializer of NETC_SW peripheral base pointers */
65424   #define NETC_SW_BASE_PTRS_NS                     { SW0_BASE_NS }
65425 #else
65426   /** Peripheral SW0_BASE base address */
65427   #define SW0_BASE_BASE                            (0x60A00000u)
65428   /** Peripheral SW0_BASE base pointer */
65429   #define SW0_BASE                                 ((NETC_SW_Type *)SW0_BASE_BASE)
65430   /** Array initializer of NETC_SW peripheral base addresses */
65431   #define NETC_SW_BASE_ADDRS                       { SW0_BASE_BASE }
65432   /** Array initializer of NETC_SW peripheral base pointers */
65433   #define NETC_SW_BASE_PTRS                        { SW0_BASE }
65434 #endif
65435 
65436 /*!
65437  * @}
65438  */ /* end of group NETC_SW_Peripheral_Access_Layer */
65439 
65440 
65441 /* ----------------------------------------------------------------------------
65442    -- NETC_SW_ENETC Peripheral Access Layer
65443    ---------------------------------------------------------------------------- */
65444 
65445 /*!
65446  * @addtogroup NETC_SW_ENETC_Peripheral_Access_Layer NETC_SW_ENETC Peripheral Access Layer
65447  * @{
65448  */
65449 
65450 /** NETC_SW_ENETC - Register Layout Typedef */
65451 typedef struct {
65452        uint8_t RESERVED_0[4096];
65453   __I  uint32_t IPCAPR;                            /**< Ingress port capability register, offset: 0x1000 */
65454   __I  uint32_t EPCAPR;                            /**< Egress port capability register, offset: 0x1004 */
65455        uint8_t RESERVED_1[8];
65456   __I  uint32_t OSR;                               /**< Operational state register, offset: 0x1010 */
65457        uint8_t RESERVED_2[44];
65458   __IO uint32_t CMECR;                             /**< Correctable memory error configuration register, offset: 0x1040 */
65459   __IO uint32_t CMESR;                             /**< Correctable memory error status register, offset: 0x1044 */
65460        uint8_t RESERVED_3[4];
65461   __I  uint32_t CMECTR;                            /**< Correctable memory error count register, offset: 0x104C */
65462        uint8_t RESERVED_4[16];
65463   __IO uint32_t UNMACECR;                          /**< Uncorrectable non-fatal MAC error configuration register, offset: 0x1060 */
65464   __I  uint32_t UNMACESR;                          /**< Uncorrectable non-fatal MAC error status register, offset: 0x1064 */
65465        uint8_t RESERVED_5[8];
65466   __IO uint32_t UNSBECR;                           /**< Uncorrectable non-fatal system bus error configuration register, offset: 0x1070, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65467   __IO uint32_t UNSBESR;                           /**< Uncorrectable non-fatal system bus error status register, offset: 0x1074, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65468        uint8_t RESERVED_6[4];
65469   __I  uint32_t UNSBECTR;                          /**< Uncorrectable non-fatal system bus error count register, offset: 0x107C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65470   __IO uint32_t UFSBECR;                           /**< Uncorrectable fatal system bus error configuration register, offset: 0x1080, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65471   __IO uint32_t UFSBESR;                           /**< Uncorrectable fatal system bus error status register, offset: 0x1084, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65472        uint8_t RESERVED_7[8];
65473   __IO uint32_t UNMECR;                            /**< Uncorrectable non-fatal memory error configuration register, offset: 0x1090 */
65474   __IO uint32_t UNMESR0;                           /**< Uncorrectable non-fatal memory error status register 0, offset: 0x1094 */
65475   __I  uint32_t UNMESR1;                           /**< Uncorrectable non-fatal memory error status register 1, offset: 0x1098 */
65476   __I  uint32_t UNMECTR;                           /**< Uncorrectable non-fatal memory error count register, offset: 0x109C */
65477   __IO uint32_t UFMECR;                            /**< Uncorrectable fatal memory error configuration register, offset: 0x10A0 */
65478   __IO uint32_t UFMESR0;                           /**< Uncorrectable fatal memory error status register 0, offset: 0x10A4 */
65479   __I  uint32_t UFMESR1;                           /**< Uncorrectable fatal memory error status register 1, offset: 0x10A8 */
65480        uint8_t RESERVED_8[52];
65481   __I  uint32_t IMDIOIRR;                          /**< Internal MDIO interrupt reason register, offset: 0x10E0, available only on: ENETC0_COMMON, SW0_COMMON (missing on ENETC1_COMMON) */
65482   __IO uint32_t IMDIOMSIVR;                        /**< Internal MDIO MSI-X vector register, offset: 0x10E4, available only on: ENETC0_COMMON, SW0_COMMON (missing on ENETC1_COMMON) */
65483   __I  uint32_t EMDIOIRR;                          /**< External MDIO interrupt reason register, offset: 0x10E8, available only on: ENETC0_COMMON, SW0_COMMON (missing on ENETC1_COMMON) */
65484   __IO uint32_t EMDIOMSIVR;                        /**< External MDIO MSI-X vector register, offset: 0x10EC, available only on: ENETC0_COMMON, SW0_COMMON (missing on ENETC1_COMMON) */
65485        uint8_t RESERVED_9[16];
65486   __IO uint32_t TCCR;                              /**< Time capture configuration register, offset: 0x1100, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65487   __IO uint32_t TCIER;                             /**< Time capture interrupt enable register, offset: 0x1104, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65488   __IO uint32_t TCRPIDR;                           /**< Time capture receive port interrupt detect register, offset: 0x1108, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65489   __I  uint32_t TCRPSR;                            /**< Time capture receive port status register, offset: 0x110C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65490        uint8_t RESERVED_10[4];
65491   __I  uint32_t TCRPTSR;                           /**< Time capture receive port timestamp register, offset: 0x1114, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65492   __IO uint32_t TCMSIVR;                           /**< Time capture MSI-X vector register, offset: 0x1118, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65493        uint8_t RESERVED_11[228];
65494   __IO uint32_t CVLANR1;                           /**< Custom VLAN Ethertype register 1, offset: 0x1200 */
65495   __IO uint32_t CVLANR2;                           /**< Custom VLAN Ethertype register 2, offset: 0x1204 */
65496   __IO uint32_t PSRTAGETR;                         /**< Pre-Standard RTAG Ethertype register, offset: 0x1208, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65497        uint8_t RESERVED_12[20];
65498   __IO uint32_t DOSL2CR;                           /**< DoS L2 configuration register, offset: 0x1220 */
65499        uint8_t RESERVED_13[220];
65500   struct {                                         /* offset: 0x1300, array step: 0x10 */
65501     __IO uint32_t VLANIPVMPR0;                       /**< VLAN to IPV mapping profile 0 register 0..VLAN to IPV mapping profile 1 register 0, array offset: 0x1300, array step: 0x10, irregular array, not all indices are valid */
65502     __IO uint32_t VLANIPVMPR1;                       /**< VLAN to IPV mapping profile 0 register 1..VLAN to IPV mapping profile 1 register 1, array offset: 0x1304, array step: 0x10, irregular array, not all indices are valid */
65503     __IO uint32_t VLANDRMPR;                         /**< VLAN to DR mapping profile 0 register..VLAN to DR mapping profile 1 register, array offset: 0x1308, array step: 0x10, irregular array, not all indices are valid */
65504          uint8_t RESERVED_0[4];
65505   } NUM_PROFILE[2];
65506        uint8_t RESERVED_14[800];
65507   __I  uint32_t IPFCAPR;                           /**< Ingress port filter capability register, offset: 0x1640 */
65508   __I  uint32_t IPFTCAPR;                          /**< Ingress port filter table capability register, offset: 0x1644 */
65509   __I  uint32_t IPFTMOR;                           /**< Ingress port filter table memory operational register, offset: 0x1648 */
65510        uint8_t RESERVED_15[436];
65511   __I  uint32_t ITMCAPR;                           /**< Index table memory capability register, offset: 0x1800 */
65512        uint8_t RESERVED_16[12];
65513   __I  uint32_t RPCAPR;                            /**< Rate policer capability register, offset: 0x1810 */
65514   __I  uint32_t RPITCAPR;                          /**< Rate policer index table capability register, offset: 0x1814 */
65515   __IO uint32_t RPITMAR;                           /**< Rate policer index table memory allocation register, offset: 0x1818 */
65516   __I  uint32_t RPITOR;                            /**< Rate policer index table operational register, offset: 0x181C */
65517        uint8_t RESERVED_17[4];
65518   __I  uint32_t ISCITCAPR;                         /**< Ingress stream counter index table capability register, offset: 0x1824 */
65519   __IO uint32_t ISCITMAR;                          /**< Ingress stream counter index table memory allocation register, offset: 0x1828 */
65520   __I  uint32_t ISCITOR;                           /**< Ingress stream counter index table operational register, offset: 0x182C */
65521   __I  uint32_t ISCAPR;                            /**< Ingress stream capability register, offset: 0x1830 */
65522   __I  uint32_t ISITCAPR;                          /**< Ingress stream index table capability register, offset: 0x1834 */
65523   __IO uint32_t ISITMAR;                           /**< Ingress stream index table memory allocation register, offset: 0x1838 */
65524   __I  uint32_t ISITOR;                            /**< Ingress stream index table operational register, offset: 0x183C */
65525        uint8_t RESERVED_18[4];
65526   __I  uint32_t ISQGITCAPR;                        /**< Ingress sequence generation index table capability register, offset: 0x1844, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65527   __IO uint32_t ISQGITMAR;                         /**< Ingress sequence generation index table memory allocation register, offset: 0x1848, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65528   __I  uint32_t ISQGITOR;                          /**< Ingress sequence generation index table operational register, offset: 0x184C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65529        uint8_t RESERVED_19[16];
65530   __I  uint32_t SGCAPR;                            /**< Stream gate capability register, offset: 0x1860 */
65531   __I  uint32_t SGIITCAPR;                         /**< Stream gate instance index table capability register, offset: 0x1864 */
65532   __IO uint32_t SGIITMAR;                          /**< Stream gate instance index table memory allocation register, offset: 0x1868 */
65533   __I  uint32_t SGIITOR;                           /**< Stream gate instance index table operational register, offset: 0x186C */
65534        uint8_t RESERVED_20[4];
65535   __I  uint32_t SGCLITCAPR;                        /**< Stream gate control list index table capability register, offset: 0x1874 */
65536   __IO uint32_t SGCLITMAR;                         /**< Stream gate control list index table memory allocation register, offset: 0x1878 */
65537   __I  uint32_t SGCLTMOR;                          /**< Stream gate control list table memory operational register, offset: 0x187C */
65538   __I  uint32_t FMICAPR;                           /**< Frame modification ingress capability register, offset: 0x1880, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65539   __I  uint32_t FMECAPR;                           /**< Frame modification egress capability register, offset: 0x1884, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65540   __I  uint32_t FMITCAPR;                          /**< Frame modification index table capability register, offset: 0x1888, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65541   __IO uint32_t FMITMAR;                           /**< Frame modification index table memory allocation register, offset: 0x188C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65542   __I  uint32_t FMITOR;                            /**< Frame modification index table operational register, offset: 0x1890, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65543   __I  uint32_t FMDITCAPR;                         /**< Frame modification data index table capability register, offset: 0x1894, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65544   __IO uint32_t FMDITMAR;                          /**< Frame modification data index table memory allocation register, offset: 0x1898, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65545        uint8_t RESERVED_21[36];
65546   __I  uint32_t ETCAPR;                            /**< Egress treatment capability register, offset: 0x18C0, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65547   __I  uint32_t ETTCAPR;                           /**< Egress treatment table capability register, offset: 0x18C4, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65548        uint8_t RESERVED_22[4];
65549   __I  uint32_t ETTOR;                             /**< Egress treatment table operational register, offset: 0x18CC, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65550        uint8_t RESERVED_23[4];
65551   __I  uint32_t TGSTCAPR;                          /**< Time gate scheduling table capability register, offset: 0x18D4 */
65552        uint8_t RESERVED_24[4];
65553   __I  uint32_t TGSTMOR;                           /**< Time gate scheduling table memory operation register, offset: 0x18DC */
65554   __I  uint32_t ESQRCAPR;                          /**< Egress sequence recovery capability register, offset: 0x18E0, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65555   __I  uint32_t ESQRTCAPR;                         /**< Egress sequence recovery table capability register, offset: 0x18E4, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65556        uint8_t RESERVED_25[4];
65557   __I  uint32_t ECTCAPR;                           /**< Egress counter table capability register, offset: 0x18EC, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65558        uint8_t RESERVED_26[16];
65559   __I  uint32_t HTMCAPR;                           /**< Hash table memory capability register, offset: 0x1900 */
65560   __I  uint32_t HTMOR;                             /**< Hash table memory operational register, offset: 0x1904 */
65561        uint8_t RESERVED_27[8];
65562   __I  uint32_t ISIDCAPR;                          /**< Ingress stream identification capability register, offset: 0x1910 */
65563   __I  uint32_t ISIDHTCAPR;                        /**< Ingress stream identification hash table capability register, offset: 0x1914 */
65564        uint8_t RESERVED_28[8];
65565   __I  uint32_t ISIDKC0OR;                         /**< Ingress stream identification key construction 0 operational register, offset: 0x1920 */
65566   __IO uint32_t ISIDKC0CR0;                        /**< Ingress stream identification key construction 0 configuration register 0, offset: 0x1924 */
65567        uint8_t RESERVED_29[8];
65568   __IO uint32_t ISIDKC0PF0CR;                      /**< Ingress stream identification key construction 0 payload field 0 configuration register, offset: 0x1930 */
65569   __IO uint32_t ISIDKC0PF1CR;                      /**< Ingress stream identification key construction 0 payload field 1 configuration register, offset: 0x1934 */
65570   __IO uint32_t ISIDKC0PF2CR;                      /**< Ingress stream identification key construction 0 payload field 2 configuration register, offset: 0x1938 */
65571   __IO uint32_t ISIDKC0PF3CR;                      /**< Ingress stream identification key construction 0 payload field 3 configuration register, offset: 0x193C */
65572   __I  uint32_t ISIDKC1OR;                         /**< Ingress stream identification key construction 1 operational register, offset: 0x1940 */
65573   __IO uint32_t ISIDKC1CR0;                        /**< Ingress stream identification key construction 1 configuration register 0, offset: 0x1944 */
65574        uint8_t RESERVED_30[8];
65575   __IO uint32_t ISIDKC1PF0CR;                      /**< Ingress stream identification key construction 1 payload field 0 configuration register, offset: 0x1950 */
65576   __IO uint32_t ISIDKC1PF1CR;                      /**< Ingress stream identification key construction 1 payload field 1 configuration register, offset: 0x1954 */
65577   __IO uint32_t ISIDKC1PF2CR;                      /**< Ingress stream identification key construction 1 payload field 2 configuration register, offset: 0x1958 */
65578   __IO uint32_t ISIDKC1PF3CR;                      /**< Ingress stream identification key construction 1 payload field 3 configuration register, offset: 0x195C */
65579   __I  uint32_t ISIDKC2OR;                         /**< Ingress stream identification key construction 2 operational register, offset: 0x1960, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65580   __IO uint32_t ISIDKC2CR0;                        /**< Ingress stream identification key construction 2 configuration register 0, offset: 0x1964, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65581        uint8_t RESERVED_31[8];
65582   __IO uint32_t ISIDKC2PF0CR;                      /**< Ingress stream identification key construction 2 payload field 0 configuration register, offset: 0x1970, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65583   __IO uint32_t ISIDKC2PF1CR;                      /**< Ingress stream identification key construction 2 payload field 1 configuration register, offset: 0x1974, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65584   __IO uint32_t ISIDKC2PF2CR;                      /**< Ingress stream identification key construction 2 payload field 2 configuration register, offset: 0x1978, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65585   __IO uint32_t ISIDKC2PF3CR;                      /**< Ingress stream identification key construction 2 payload field 3 configuration register, offset: 0x197C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65586   __I  uint32_t ISIDKC3OR;                         /**< Ingress stream identification key construction 3 operational register, offset: 0x1980, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65587   __IO uint32_t ISIDKC3CR0;                        /**< Ingress stream identification key construction 3 configuration register 0, offset: 0x1984, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65588        uint8_t RESERVED_32[8];
65589   __IO uint32_t ISIDKC3PF0CR;                      /**< Ingress stream identification key construction 3 payload field 0 configuration register, offset: 0x1990, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65590   __IO uint32_t ISIDKC3PF1CR;                      /**< Ingress stream identification key construction 3 payload field 1 configuration register, offset: 0x1994, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65591   __IO uint32_t ISIDKC3PF2CR;                      /**< Ingress stream identification key construction 3 payload field 2 configuration register, offset: 0x1998, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65592   __IO uint32_t ISIDKC3PF3CR;                      /**< Ingress stream identification key construction 3 payload field 3 configuration register, offset: 0x199C, available only on: SW0_COMMON (missing on ENETC0_COMMON, ENETC1_COMMON) */
65593        uint8_t RESERVED_33[96];
65594   __I  uint32_t ISFHTCAPR;                         /**< Ingress stream filter hash table capability register, offset: 0x1A00 */
65595   __I  uint32_t ISFHTOR;                           /**< Ingress stream filter hash table operational register, offset: 0x1A04 */
65596 } NETC_SW_ENETC_Type;
65597 
65598 /* ----------------------------------------------------------------------------
65599    -- NETC_SW_ENETC Register Masks
65600    ---------------------------------------------------------------------------- */
65601 
65602 /*!
65603  * @addtogroup NETC_SW_ENETC_Register_Masks NETC_SW_ENETC Register Masks
65604  * @{
65605  */
65606 
65607 /*! @name IPCAPR - Ingress port capability register */
65608 /*! @{ */
65609 
65610 #define NETC_SW_ENETC_IPCAPR_RP_MASK             (0x1U)
65611 #define NETC_SW_ENETC_IPCAPR_RP_SHIFT            (0U)
65612 #define NETC_SW_ENETC_IPCAPR_RP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_RP_SHIFT)) & NETC_SW_ENETC_IPCAPR_RP_MASK)
65613 
65614 #define NETC_SW_ENETC_IPCAPR_IPFLT_MASK          (0x2U)
65615 #define NETC_SW_ENETC_IPCAPR_IPFLT_SHIFT         (1U)
65616 #define NETC_SW_ENETC_IPCAPR_IPFLT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_IPFLT_SHIFT)) & NETC_SW_ENETC_IPCAPR_IPFLT_MASK)
65617 
65618 #define NETC_SW_ENETC_IPCAPR_ISID_MASK           (0x4U)
65619 #define NETC_SW_ENETC_IPCAPR_ISID_SHIFT          (2U)
65620 #define NETC_SW_ENETC_IPCAPR_ISID(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_ISID_SHIFT)) & NETC_SW_ENETC_IPCAPR_ISID_MASK)
65621 
65622 #define NETC_SW_ENETC_IPCAPR_SDU_MASK            (0x1F00U)
65623 #define NETC_SW_ENETC_IPCAPR_SDU_SHIFT           (8U)
65624 /*! SDU - Indicates support for various PDU/SDUs (Protocol/Service Data Unit) definitions. */
65625 #define NETC_SW_ENETC_IPCAPR_SDU(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_SDU_SHIFT)) & NETC_SW_ENETC_IPCAPR_SDU_MASK)
65626 
65627 #define NETC_SW_ENETC_IPCAPR_NUM_VQMP_MASK       (0xF0000U)
65628 #define NETC_SW_ENETC_IPCAPR_NUM_VQMP_SHIFT      (16U)
65629 #define NETC_SW_ENETC_IPCAPR_NUM_VQMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_NUM_VQMP_SHIFT)) & NETC_SW_ENETC_IPCAPR_NUM_VQMP_MASK)
65630 /*! @} */
65631 
65632 /*! @name EPCAPR - Egress port capability register */
65633 /*! @{ */
65634 
65635 #define NETC_SW_ENETC_EPCAPR_ET_MASK             (0x1U)
65636 #define NETC_SW_ENETC_EPCAPR_ET_SHIFT            (0U)
65637 #define NETC_SW_ENETC_EPCAPR_ET(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EPCAPR_ET_SHIFT)) & NETC_SW_ENETC_EPCAPR_ET_MASK)
65638 
65639 #define NETC_SW_ENETC_EPCAPR_SDU_MASK            (0x1F00U)
65640 #define NETC_SW_ENETC_EPCAPR_SDU_SHIFT           (8U)
65641 /*! SDU - Indicates support for various PDU/SDUs (Protocol/Service Data Unit) definitions. */
65642 #define NETC_SW_ENETC_EPCAPR_SDU(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EPCAPR_SDU_SHIFT)) & NETC_SW_ENETC_EPCAPR_SDU_MASK)
65643 
65644 #define NETC_SW_ENETC_EPCAPR_NUM_QVMP_MASK       (0xF0000U)
65645 #define NETC_SW_ENETC_EPCAPR_NUM_QVMP_SHIFT      (16U)
65646 #define NETC_SW_ENETC_EPCAPR_NUM_QVMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EPCAPR_NUM_QVMP_SHIFT)) & NETC_SW_ENETC_EPCAPR_NUM_QVMP_MASK)
65647 /*! @} */
65648 
65649 /*! @name OSR - Operational state register */
65650 /*! @{ */
65651 
65652 #define NETC_SW_ENETC_OSR_STATE_MASK             (0x1U)
65653 #define NETC_SW_ENETC_OSR_STATE_SHIFT            (0U)
65654 #define NETC_SW_ENETC_OSR_STATE(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_OSR_STATE_SHIFT)) & NETC_SW_ENETC_OSR_STATE_MASK)
65655 
65656 #define NETC_SW_ENETC_OSR_ITM_STATE_MASK         (0x2U)
65657 #define NETC_SW_ENETC_OSR_ITM_STATE_SHIFT        (1U)
65658 #define NETC_SW_ENETC_OSR_ITM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_OSR_ITM_STATE_SHIFT)) & NETC_SW_ENETC_OSR_ITM_STATE_MASK)
65659 /*! @} */
65660 
65661 /*! @name CMECR - Correctable memory error configuration register */
65662 /*! @{ */
65663 
65664 #define NETC_SW_ENETC_CMECR_THRESHOLD_MASK       (0xFFU)
65665 #define NETC_SW_ENETC_CMECR_THRESHOLD_SHIFT      (0U)
65666 /*! THRESHOLD - Threshold */
65667 #define NETC_SW_ENETC_CMECR_THRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMECR_THRESHOLD_SHIFT)) & NETC_SW_ENETC_CMECR_THRESHOLD_MASK)
65668 /*! @} */
65669 
65670 /*! @name CMESR - Correctable memory error status register */
65671 /*! @{ */
65672 
65673 #define NETC_SW_ENETC_CMESR_MEM_ID_MASK          (0x1F0000U)
65674 #define NETC_SW_ENETC_CMESR_MEM_ID_SHIFT         (16U)
65675 /*! MEM_ID - Memory ID */
65676 #define NETC_SW_ENETC_CMESR_MEM_ID(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMESR_MEM_ID_SHIFT)) & NETC_SW_ENETC_CMESR_MEM_ID_MASK)
65677 
65678 #define NETC_SW_ENETC_CMESR_SBEE_MASK            (0x80000000U)
65679 #define NETC_SW_ENETC_CMESR_SBEE_SHIFT           (31U)
65680 /*! SBEE - Single-bit ECC error */
65681 #define NETC_SW_ENETC_CMESR_SBEE(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMESR_SBEE_SHIFT)) & NETC_SW_ENETC_CMESR_SBEE_MASK)
65682 /*! @} */
65683 
65684 /*! @name CMECTR - Correctable memory error count register */
65685 /*! @{ */
65686 
65687 #define NETC_SW_ENETC_CMECTR_COUNT_MASK          (0xFFU)
65688 #define NETC_SW_ENETC_CMECTR_COUNT_SHIFT         (0U)
65689 /*! COUNT - Count */
65690 #define NETC_SW_ENETC_CMECTR_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMECTR_COUNT_SHIFT)) & NETC_SW_ENETC_CMECTR_COUNT_MASK)
65691 /*! @} */
65692 
65693 /*! @name UNMACECR - Uncorrectable non-fatal MAC error configuration register */
65694 /*! @{ */
65695 
65696 #define NETC_SW_ENETC_UNMACECR_PORT0_MASK        (0x1U)
65697 #define NETC_SW_ENETC_UNMACECR_PORT0_SHIFT       (0U)
65698 /*! PORT0 - Report disable port */
65699 #define NETC_SW_ENETC_UNMACECR_PORT0(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT0_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT0_MASK)
65700 
65701 #define NETC_SW_ENETC_UNMACECR_PORT1_MASK        (0x2U)
65702 #define NETC_SW_ENETC_UNMACECR_PORT1_SHIFT       (1U)
65703 /*! PORT1 - Report disable port */
65704 #define NETC_SW_ENETC_UNMACECR_PORT1(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT1_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT1_MASK)
65705 
65706 #define NETC_SW_ENETC_UNMACECR_PORT2_MASK        (0x4U)
65707 #define NETC_SW_ENETC_UNMACECR_PORT2_SHIFT       (2U)
65708 /*! PORT2 - Report disable port */
65709 #define NETC_SW_ENETC_UNMACECR_PORT2(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT2_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT2_MASK)
65710 
65711 #define NETC_SW_ENETC_UNMACECR_PORT3_MASK        (0x8U)
65712 #define NETC_SW_ENETC_UNMACECR_PORT3_SHIFT       (3U)
65713 /*! PORT3 - Report disable port */
65714 #define NETC_SW_ENETC_UNMACECR_PORT3(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT3_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT3_MASK)
65715 
65716 #define NETC_SW_ENETC_UNMACECR_PORT4_MASK        (0x10U)
65717 #define NETC_SW_ENETC_UNMACECR_PORT4_SHIFT       (4U)
65718 /*! PORT4 - Report disable port */
65719 #define NETC_SW_ENETC_UNMACECR_PORT4(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT4_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT4_MASK)
65720 /*! @} */
65721 
65722 /*! @name UNMACESR - Uncorrectable non-fatal MAC error status register */
65723 /*! @{ */
65724 
65725 #define NETC_SW_ENETC_UNMACESR_PORT0_MASK        (0x1U)
65726 #define NETC_SW_ENETC_UNMACESR_PORT0_SHIFT       (0U)
65727 /*! PORT0 - Port 0 MAC error */
65728 #define NETC_SW_ENETC_UNMACESR_PORT0(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT0_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT0_MASK)
65729 
65730 #define NETC_SW_ENETC_UNMACESR_PORT1_MASK        (0x2U)
65731 #define NETC_SW_ENETC_UNMACESR_PORT1_SHIFT       (1U)
65732 /*! PORT1 - Port 1 MAC error */
65733 #define NETC_SW_ENETC_UNMACESR_PORT1(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT1_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT1_MASK)
65734 
65735 #define NETC_SW_ENETC_UNMACESR_PORT2_MASK        (0x4U)
65736 #define NETC_SW_ENETC_UNMACESR_PORT2_SHIFT       (2U)
65737 /*! PORT2 - Port 2 MAC error */
65738 #define NETC_SW_ENETC_UNMACESR_PORT2(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT2_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT2_MASK)
65739 
65740 #define NETC_SW_ENETC_UNMACESR_PORT3_MASK        (0x8U)
65741 #define NETC_SW_ENETC_UNMACESR_PORT3_SHIFT       (3U)
65742 /*! PORT3 - Port 3 MAC error */
65743 #define NETC_SW_ENETC_UNMACESR_PORT3(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT3_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT3_MASK)
65744 
65745 #define NETC_SW_ENETC_UNMACESR_PORT4_MASK        (0x10U)
65746 #define NETC_SW_ENETC_UNMACESR_PORT4_SHIFT       (4U)
65747 /*! PORT4 - Port 4 MAC error */
65748 #define NETC_SW_ENETC_UNMACESR_PORT4(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT4_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT4_MASK)
65749 /*! @} */
65750 
65751 /*! @name UNSBECR - Uncorrectable non-fatal system bus error configuration register */
65752 /*! @{ */
65753 
65754 #define NETC_SW_ENETC_UNSBECR_THRESHOLD_MASK     (0xFFU)
65755 #define NETC_SW_ENETC_UNSBECR_THRESHOLD_SHIFT    (0U)
65756 /*! THRESHOLD - Threshold */
65757 #define NETC_SW_ENETC_UNSBECR_THRESHOLD(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNSBECR_THRESHOLD_SHIFT)) & NETC_SW_ENETC_UNSBECR_THRESHOLD_MASK)
65758 /*! @} */
65759 
65760 /*! @name UNSBESR - Uncorrectable non-fatal system bus error status register */
65761 /*! @{ */
65762 
65763 #define NETC_SW_ENETC_UNSBESR_SB_ID_MASK         (0xFU)
65764 #define NETC_SW_ENETC_UNSBESR_SB_ID_SHIFT        (0U)
65765 /*! SB_ID - System Bus ID */
65766 #define NETC_SW_ENETC_UNSBESR_SB_ID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNSBESR_SB_ID_SHIFT)) & NETC_SW_ENETC_UNSBESR_SB_ID_MASK)
65767 
65768 #define NETC_SW_ENETC_UNSBESR_SBE_MASK           (0x80000000U)
65769 #define NETC_SW_ENETC_UNSBESR_SBE_SHIFT          (31U)
65770 /*! SBE - System bus error */
65771 #define NETC_SW_ENETC_UNSBESR_SBE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNSBESR_SBE_SHIFT)) & NETC_SW_ENETC_UNSBESR_SBE_MASK)
65772 /*! @} */
65773 
65774 /*! @name UNSBECTR - Uncorrectable non-fatal system bus error count register */
65775 /*! @{ */
65776 
65777 #define NETC_SW_ENETC_UNSBECTR_COUNT_MASK        (0xFFU)
65778 #define NETC_SW_ENETC_UNSBECTR_COUNT_SHIFT       (0U)
65779 /*! COUNT - Count */
65780 #define NETC_SW_ENETC_UNSBECTR_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNSBECTR_COUNT_SHIFT)) & NETC_SW_ENETC_UNSBECTR_COUNT_MASK)
65781 /*! @} */
65782 
65783 /*! @name UFSBECR - Uncorrectable fatal system bus error configuration register */
65784 /*! @{ */
65785 
65786 #define NETC_SW_ENETC_UFSBECR_RD_MASK            (0x80000000U)
65787 #define NETC_SW_ENETC_UFSBECR_RD_SHIFT           (31U)
65788 /*! RD - Report disable
65789  *  0b0..Enabled
65790  *  0b1..Disabled
65791  */
65792 #define NETC_SW_ENETC_UFSBECR_RD(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFSBECR_RD_SHIFT)) & NETC_SW_ENETC_UFSBECR_RD_MASK)
65793 /*! @} */
65794 
65795 /*! @name UFSBESR - Uncorrectable fatal system bus error status register */
65796 /*! @{ */
65797 
65798 #define NETC_SW_ENETC_UFSBESR_SB_ID_MASK         (0xFU)
65799 #define NETC_SW_ENETC_UFSBESR_SB_ID_SHIFT        (0U)
65800 /*! SB_ID - System Bus ID */
65801 #define NETC_SW_ENETC_UFSBESR_SB_ID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFSBESR_SB_ID_SHIFT)) & NETC_SW_ENETC_UFSBESR_SB_ID_MASK)
65802 
65803 #define NETC_SW_ENETC_UFSBESR_M_MASK             (0x40000000U)
65804 #define NETC_SW_ENETC_UFSBESR_M_SHIFT            (30U)
65805 /*! M - Multiple */
65806 #define NETC_SW_ENETC_UFSBESR_M(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFSBESR_M_SHIFT)) & NETC_SW_ENETC_UFSBESR_M_MASK)
65807 
65808 #define NETC_SW_ENETC_UFSBESR_SBE_MASK           (0x80000000U)
65809 #define NETC_SW_ENETC_UFSBESR_SBE_SHIFT          (31U)
65810 /*! SBE - System bus error */
65811 #define NETC_SW_ENETC_UFSBESR_SBE(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFSBESR_SBE_SHIFT)) & NETC_SW_ENETC_UFSBESR_SBE_MASK)
65812 /*! @} */
65813 
65814 /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */
65815 /*! @{ */
65816 
65817 #define NETC_SW_ENETC_UNMECR_THRESHOLD_MASK      (0xFFU)
65818 #define NETC_SW_ENETC_UNMECR_THRESHOLD_SHIFT     (0U)
65819 /*! THRESHOLD - Threshold */
65820 #define NETC_SW_ENETC_UNMECR_THRESHOLD(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECR_THRESHOLD_SHIFT)) & NETC_SW_ENETC_UNMECR_THRESHOLD_MASK)
65821 
65822 #define NETC_SW_ENETC_UNMECR_RD_MASK             (0x80000000U)
65823 #define NETC_SW_ENETC_UNMECR_RD_SHIFT            (31U)
65824 /*! RD - Report disable */
65825 #define NETC_SW_ENETC_UNMECR_RD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECR_RD_SHIFT)) & NETC_SW_ENETC_UNMECR_RD_MASK)
65826 /*! @} */
65827 
65828 /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */
65829 /*! @{ */
65830 
65831 #define NETC_SW_ENETC_UNMESR0_SYNDROME_MASK      (0x7FFU)
65832 #define NETC_SW_ENETC_UNMESR0_SYNDROME_SHIFT     (0U)
65833 /*! SYNDROME - Syndrome */
65834 #define NETC_SW_ENETC_UNMESR0_SYNDROME(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_SYNDROME_SHIFT)) & NETC_SW_ENETC_UNMESR0_SYNDROME_MASK)
65835 
65836 #define NETC_SW_ENETC_UNMESR0_MEM_ID_MASK        (0x1F0000U)
65837 #define NETC_SW_ENETC_UNMESR0_MEM_ID_SHIFT       (16U)
65838 /*! MEM_ID - Memory ID */
65839 #define NETC_SW_ENETC_UNMESR0_MEM_ID(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_MEM_ID_SHIFT)) & NETC_SW_ENETC_UNMESR0_MEM_ID_MASK)
65840 
65841 #define NETC_SW_ENETC_UNMESR0_MBEE_MASK          (0x80000000U)
65842 #define NETC_SW_ENETC_UNMESR0_MBEE_SHIFT         (31U)
65843 /*! MBEE - Multi-bit ECC error */
65844 #define NETC_SW_ENETC_UNMESR0_MBEE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_MBEE_SHIFT)) & NETC_SW_ENETC_UNMESR0_MBEE_MASK)
65845 /*! @} */
65846 
65847 /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */
65848 /*! @{ */
65849 
65850 #define NETC_SW_ENETC_UNMESR1_ADDR_MASK          (0xFFFFFFFFU)
65851 #define NETC_SW_ENETC_UNMESR1_ADDR_SHIFT         (0U)
65852 /*! ADDR - Address */
65853 #define NETC_SW_ENETC_UNMESR1_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR1_ADDR_SHIFT)) & NETC_SW_ENETC_UNMESR1_ADDR_MASK)
65854 /*! @} */
65855 
65856 /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */
65857 /*! @{ */
65858 
65859 #define NETC_SW_ENETC_UNMECTR_COUNT_MASK         (0xFFU)
65860 #define NETC_SW_ENETC_UNMECTR_COUNT_SHIFT        (0U)
65861 /*! COUNT - Count */
65862 #define NETC_SW_ENETC_UNMECTR_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECTR_COUNT_SHIFT)) & NETC_SW_ENETC_UNMECTR_COUNT_MASK)
65863 /*! @} */
65864 
65865 /*! @name UFMECR - Uncorrectable fatal memory error configuration register */
65866 /*! @{ */
65867 
65868 #define NETC_SW_ENETC_UFMECR_RD_MASK             (0x80000000U)
65869 #define NETC_SW_ENETC_UFMECR_RD_SHIFT            (31U)
65870 /*! RD - Report disable */
65871 #define NETC_SW_ENETC_UFMECR_RD(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMECR_RD_SHIFT)) & NETC_SW_ENETC_UFMECR_RD_MASK)
65872 /*! @} */
65873 
65874 /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */
65875 /*! @{ */
65876 
65877 #define NETC_SW_ENETC_UFMESR0_SYNDROME_MASK      (0x7FFU)
65878 #define NETC_SW_ENETC_UFMESR0_SYNDROME_SHIFT     (0U)
65879 /*! SYNDROME - Syndrome */
65880 #define NETC_SW_ENETC_UFMESR0_SYNDROME(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_SYNDROME_SHIFT)) & NETC_SW_ENETC_UFMESR0_SYNDROME_MASK)
65881 
65882 #define NETC_SW_ENETC_UFMESR0_MEM_ID_MASK        (0x1F0000U)
65883 #define NETC_SW_ENETC_UFMESR0_MEM_ID_SHIFT       (16U)
65884 /*! MEM_ID - Memory ID */
65885 #define NETC_SW_ENETC_UFMESR0_MEM_ID(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_MEM_ID_SHIFT)) & NETC_SW_ENETC_UFMESR0_MEM_ID_MASK)
65886 
65887 #define NETC_SW_ENETC_UFMESR0_M_MASK             (0x40000000U)
65888 #define NETC_SW_ENETC_UFMESR0_M_SHIFT            (30U)
65889 /*! M - Multiple */
65890 #define NETC_SW_ENETC_UFMESR0_M(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_M_SHIFT)) & NETC_SW_ENETC_UFMESR0_M_MASK)
65891 
65892 #define NETC_SW_ENETC_UFMESR0_MBEE_MASK          (0x80000000U)
65893 #define NETC_SW_ENETC_UFMESR0_MBEE_SHIFT         (31U)
65894 /*! MBEE - Multi-bit ECC error */
65895 #define NETC_SW_ENETC_UFMESR0_MBEE(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_MBEE_SHIFT)) & NETC_SW_ENETC_UFMESR0_MBEE_MASK)
65896 /*! @} */
65897 
65898 /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */
65899 /*! @{ */
65900 
65901 #define NETC_SW_ENETC_UFMESR1_ADDR_MASK          (0xFFFFFFFFU)
65902 #define NETC_SW_ENETC_UFMESR1_ADDR_SHIFT         (0U)
65903 /*! ADDR - Address */
65904 #define NETC_SW_ENETC_UFMESR1_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR1_ADDR_SHIFT)) & NETC_SW_ENETC_UFMESR1_ADDR_MASK)
65905 /*! @} */
65906 
65907 /*! @name IMDIOIRR - Internal MDIO interrupt reason register */
65908 /*! @{ */
65909 
65910 #define NETC_SW_ENETC_IMDIOIRR_PORT0_MASK        (0x1U)
65911 #define NETC_SW_ENETC_IMDIOIRR_PORT0_SHIFT       (0U)
65912 #define NETC_SW_ENETC_IMDIOIRR_PORT0(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOIRR_PORT0_SHIFT)) & NETC_SW_ENETC_IMDIOIRR_PORT0_MASK)
65913 
65914 #define NETC_SW_ENETC_IMDIOIRR_PORT1_MASK        (0x2U)
65915 #define NETC_SW_ENETC_IMDIOIRR_PORT1_SHIFT       (1U)
65916 #define NETC_SW_ENETC_IMDIOIRR_PORT1(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOIRR_PORT1_SHIFT)) & NETC_SW_ENETC_IMDIOIRR_PORT1_MASK)
65917 
65918 #define NETC_SW_ENETC_IMDIOIRR_PORT2_MASK        (0x4U)
65919 #define NETC_SW_ENETC_IMDIOIRR_PORT2_SHIFT       (2U)
65920 #define NETC_SW_ENETC_IMDIOIRR_PORT2(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOIRR_PORT2_SHIFT)) & NETC_SW_ENETC_IMDIOIRR_PORT2_MASK)
65921 
65922 #define NETC_SW_ENETC_IMDIOIRR_PORT3_MASK        (0x8U)
65923 #define NETC_SW_ENETC_IMDIOIRR_PORT3_SHIFT       (3U)
65924 #define NETC_SW_ENETC_IMDIOIRR_PORT3(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOIRR_PORT3_SHIFT)) & NETC_SW_ENETC_IMDIOIRR_PORT3_MASK)
65925 
65926 #define NETC_SW_ENETC_IMDIOIRR_PORT4_MASK        (0x10U)
65927 #define NETC_SW_ENETC_IMDIOIRR_PORT4_SHIFT       (4U)
65928 #define NETC_SW_ENETC_IMDIOIRR_PORT4(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOIRR_PORT4_SHIFT)) & NETC_SW_ENETC_IMDIOIRR_PORT4_MASK)
65929 /*! @} */
65930 
65931 /*! @name IMDIOMSIVR - Internal MDIO MSI-X vector register */
65932 /*! @{ */
65933 
65934 #define NETC_SW_ENETC_IMDIOMSIVR_VECTOR_MASK     (0x3FU)  /* Merged from fields with different position or width, of widths (4, 6), largest definition used */
65935 #define NETC_SW_ENETC_IMDIOMSIVR_VECTOR_SHIFT    (0U)
65936 #define NETC_SW_ENETC_IMDIOMSIVR_VECTOR(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IMDIOMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_IMDIOMSIVR_VECTOR_MASK)  /* Merged from fields with different position or width, of widths (4, 6), largest definition used */
65937 /*! @} */
65938 
65939 /*! @name EMDIOIRR - External MDIO interrupt reason register */
65940 /*! @{ */
65941 
65942 #define NETC_SW_ENETC_EMDIOIRR_PORT0_MASK        (0x1U)
65943 #define NETC_SW_ENETC_EMDIOIRR_PORT0_SHIFT       (0U)
65944 #define NETC_SW_ENETC_EMDIOIRR_PORT0(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT0_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT0_MASK)
65945 
65946 #define NETC_SW_ENETC_EMDIOIRR_PORT1_MASK        (0x2U)
65947 #define NETC_SW_ENETC_EMDIOIRR_PORT1_SHIFT       (1U)
65948 #define NETC_SW_ENETC_EMDIOIRR_PORT1(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT1_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT1_MASK)
65949 
65950 #define NETC_SW_ENETC_EMDIOIRR_PORT2_MASK        (0x4U)
65951 #define NETC_SW_ENETC_EMDIOIRR_PORT2_SHIFT       (2U)
65952 #define NETC_SW_ENETC_EMDIOIRR_PORT2(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT2_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT2_MASK)
65953 
65954 #define NETC_SW_ENETC_EMDIOIRR_PORT3_MASK        (0x8U)
65955 #define NETC_SW_ENETC_EMDIOIRR_PORT3_SHIFT       (3U)
65956 #define NETC_SW_ENETC_EMDIOIRR_PORT3(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT3_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT3_MASK)
65957 
65958 #define NETC_SW_ENETC_EMDIOIRR_PORT4_MASK        (0x10U)
65959 #define NETC_SW_ENETC_EMDIOIRR_PORT4_SHIFT       (4U)
65960 #define NETC_SW_ENETC_EMDIOIRR_PORT4(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT4_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT4_MASK)
65961 /*! @} */
65962 
65963 /*! @name EMDIOMSIVR - External MDIO MSI-X vector register */
65964 /*! @{ */
65965 
65966 #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR_MASK     (0x3FU)  /* Merged from fields with different position or width, of widths (4, 6), largest definition used */
65967 #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR_SHIFT    (0U)
65968 #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_EMDIOMSIVR_VECTOR_MASK)  /* Merged from fields with different position or width, of widths (4, 6), largest definition used */
65969 /*! @} */
65970 
65971 /*! @name TCCR - Time capture configuration register */
65972 /*! @{ */
65973 
65974 #define NETC_SW_ENETC_TCCR_TIMEOUT_MASK          (0xFFFFFFU)
65975 #define NETC_SW_ENETC_TCCR_TIMEOUT_SHIFT         (0U)
65976 #define NETC_SW_ENETC_TCCR_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCCR_TIMEOUT_SHIFT)) & NETC_SW_ENETC_TCCR_TIMEOUT_MASK)
65977 
65978 #define NETC_SW_ENETC_TCCR_ARM_MASK              (0xC0000000U)
65979 #define NETC_SW_ENETC_TCCR_ARM_SHIFT             (30U)
65980 #define NETC_SW_ENETC_TCCR_ARM(x)                (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCCR_ARM_SHIFT)) & NETC_SW_ENETC_TCCR_ARM_MASK)
65981 /*! @} */
65982 
65983 /*! @name TCIER - Time capture interrupt enable register */
65984 /*! @{ */
65985 
65986 #define NETC_SW_ENETC_TCIER_TRANSMIT_MASK        (0x40000000U)
65987 #define NETC_SW_ENETC_TCIER_TRANSMIT_SHIFT       (30U)
65988 /*! TRANSMIT - Transmit interrupt */
65989 #define NETC_SW_ENETC_TCIER_TRANSMIT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCIER_TRANSMIT_SHIFT)) & NETC_SW_ENETC_TCIER_TRANSMIT_MASK)
65990 
65991 #define NETC_SW_ENETC_TCIER_TIMEOUT_MASK         (0x80000000U)
65992 #define NETC_SW_ENETC_TCIER_TIMEOUT_SHIFT        (31U)
65993 /*! TIMEOUT - Timeout interrupt */
65994 #define NETC_SW_ENETC_TCIER_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCIER_TIMEOUT_SHIFT)) & NETC_SW_ENETC_TCIER_TIMEOUT_MASK)
65995 /*! @} */
65996 
65997 /*! @name TCRPIDR - Time capture receive port interrupt detect register */
65998 /*! @{ */
65999 
66000 #define NETC_SW_ENETC_TCRPIDR_TX_PORT0_MASK      (0x1U)
66001 #define NETC_SW_ENETC_TCRPIDR_TX_PORT0_SHIFT     (0U)
66002 #define NETC_SW_ENETC_TCRPIDR_TX_PORT0(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TX_PORT0_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TX_PORT0_MASK)
66003 
66004 #define NETC_SW_ENETC_TCRPIDR_TX_PORT1_MASK      (0x2U)
66005 #define NETC_SW_ENETC_TCRPIDR_TX_PORT1_SHIFT     (1U)
66006 #define NETC_SW_ENETC_TCRPIDR_TX_PORT1(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TX_PORT1_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TX_PORT1_MASK)
66007 
66008 #define NETC_SW_ENETC_TCRPIDR_TX_PORT2_MASK      (0x4U)
66009 #define NETC_SW_ENETC_TCRPIDR_TX_PORT2_SHIFT     (2U)
66010 #define NETC_SW_ENETC_TCRPIDR_TX_PORT2(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TX_PORT2_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TX_PORT2_MASK)
66011 
66012 #define NETC_SW_ENETC_TCRPIDR_TX_PORT3_MASK      (0x8U)
66013 #define NETC_SW_ENETC_TCRPIDR_TX_PORT3_SHIFT     (3U)
66014 #define NETC_SW_ENETC_TCRPIDR_TX_PORT3(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TX_PORT3_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TX_PORT3_MASK)
66015 
66016 #define NETC_SW_ENETC_TCRPIDR_TX_PORT4_MASK      (0x10U)
66017 #define NETC_SW_ENETC_TCRPIDR_TX_PORT4_SHIFT     (4U)
66018 #define NETC_SW_ENETC_TCRPIDR_TX_PORT4(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TX_PORT4_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TX_PORT4_MASK)
66019 
66020 #define NETC_SW_ENETC_TCRPIDR_TRANSMIT_MASK      (0x40000000U)
66021 #define NETC_SW_ENETC_TCRPIDR_TRANSMIT_SHIFT     (30U)
66022 /*! TRANSMIT - Transmit interrupt */
66023 #define NETC_SW_ENETC_TCRPIDR_TRANSMIT(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TRANSMIT_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TRANSMIT_MASK)
66024 
66025 #define NETC_SW_ENETC_TCRPIDR_TIMEOUT_MASK       (0x80000000U)
66026 #define NETC_SW_ENETC_TCRPIDR_TIMEOUT_SHIFT      (31U)
66027 /*! TIMEOUT - Timeout interrupt */
66028 #define NETC_SW_ENETC_TCRPIDR_TIMEOUT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPIDR_TIMEOUT_SHIFT)) & NETC_SW_ENETC_TCRPIDR_TIMEOUT_MASK)
66029 /*! @} */
66030 
66031 /*! @name TCRPSR - Time capture receive port status register */
66032 /*! @{ */
66033 
66034 #define NETC_SW_ENETC_TCRPSR_RX_PORT_MASK        (0x1FU)
66035 #define NETC_SW_ENETC_TCRPSR_RX_PORT_SHIFT       (0U)
66036 #define NETC_SW_ENETC_TCRPSR_RX_PORT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPSR_RX_PORT_SHIFT)) & NETC_SW_ENETC_TCRPSR_RX_PORT_MASK)
66037 
66038 #define NETC_SW_ENETC_TCRPSR_RX_CNT_MASK         (0x300U)
66039 #define NETC_SW_ENETC_TCRPSR_RX_CNT_SHIFT        (8U)
66040 #define NETC_SW_ENETC_TCRPSR_RX_CNT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPSR_RX_CNT_SHIFT)) & NETC_SW_ENETC_TCRPSR_RX_CNT_MASK)
66041 /*! @} */
66042 
66043 /*! @name TCRPTSR - Time capture receive port timestamp register */
66044 /*! @{ */
66045 
66046 #define NETC_SW_ENETC_TCRPTSR_TIMESTAMP_MASK     (0xFFFFFFFFU)
66047 #define NETC_SW_ENETC_TCRPTSR_TIMESTAMP_SHIFT    (0U)
66048 #define NETC_SW_ENETC_TCRPTSR_TIMESTAMP(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCRPTSR_TIMESTAMP_SHIFT)) & NETC_SW_ENETC_TCRPTSR_TIMESTAMP_MASK)
66049 /*! @} */
66050 
66051 /*! @name TCMSIVR - Time capture MSI-X vector register */
66052 /*! @{ */
66053 
66054 #define NETC_SW_ENETC_TCMSIVR_VECTOR_MASK        (0xFU)
66055 #define NETC_SW_ENETC_TCMSIVR_VECTOR_SHIFT       (0U)
66056 #define NETC_SW_ENETC_TCMSIVR_VECTOR(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TCMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_TCMSIVR_VECTOR_MASK)
66057 /*! @} */
66058 
66059 /*! @name CVLANR1 - Custom VLAN Ethertype register 1 */
66060 /*! @{ */
66061 
66062 #define NETC_SW_ENETC_CVLANR1_ETYPE_MASK         (0xFFFFU)
66063 #define NETC_SW_ENETC_CVLANR1_ETYPE_SHIFT        (0U)
66064 #define NETC_SW_ENETC_CVLANR1_ETYPE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR1_ETYPE_SHIFT)) & NETC_SW_ENETC_CVLANR1_ETYPE_MASK)
66065 
66066 #define NETC_SW_ENETC_CVLANR1_V_MASK             (0x80000000U)
66067 #define NETC_SW_ENETC_CVLANR1_V_SHIFT            (31U)
66068 /*! V - Valid */
66069 #define NETC_SW_ENETC_CVLANR1_V(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR1_V_SHIFT)) & NETC_SW_ENETC_CVLANR1_V_MASK)
66070 /*! @} */
66071 
66072 /*! @name CVLANR2 - Custom VLAN Ethertype register 2 */
66073 /*! @{ */
66074 
66075 #define NETC_SW_ENETC_CVLANR2_ETYPE_MASK         (0xFFFFU)
66076 #define NETC_SW_ENETC_CVLANR2_ETYPE_SHIFT        (0U)
66077 #define NETC_SW_ENETC_CVLANR2_ETYPE(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR2_ETYPE_SHIFT)) & NETC_SW_ENETC_CVLANR2_ETYPE_MASK)
66078 
66079 #define NETC_SW_ENETC_CVLANR2_V_MASK             (0x80000000U)
66080 #define NETC_SW_ENETC_CVLANR2_V_SHIFT            (31U)
66081 /*! V - Valid */
66082 #define NETC_SW_ENETC_CVLANR2_V(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR2_V_SHIFT)) & NETC_SW_ENETC_CVLANR2_V_MASK)
66083 /*! @} */
66084 
66085 /*! @name PSRTAGETR - Pre-Standard RTAG Ethertype register */
66086 /*! @{ */
66087 
66088 #define NETC_SW_ENETC_PSRTAGETR_ETHERTYPE_MASK   (0xFFFFU)
66089 #define NETC_SW_ENETC_PSRTAGETR_ETHERTYPE_SHIFT  (0U)
66090 #define NETC_SW_ENETC_PSRTAGETR_ETHERTYPE(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_PSRTAGETR_ETHERTYPE_SHIFT)) & NETC_SW_ENETC_PSRTAGETR_ETHERTYPE_MASK)
66091 /*! @} */
66092 
66093 /*! @name DOSL2CR - DoS L2 configuration register */
66094 /*! @{ */
66095 
66096 #define NETC_SW_ENETC_DOSL2CR_SAMEADDR_MASK      (0x1U)
66097 #define NETC_SW_ENETC_DOSL2CR_SAMEADDR_SHIFT     (0U)
66098 #define NETC_SW_ENETC_DOSL2CR_SAMEADDR(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_DOSL2CR_SAMEADDR_SHIFT)) & NETC_SW_ENETC_DOSL2CR_SAMEADDR_MASK)
66099 
66100 #define NETC_SW_ENETC_DOSL2CR_MSAMCC_MASK        (0x2U)
66101 #define NETC_SW_ENETC_DOSL2CR_MSAMCC_SHIFT       (1U)
66102 #define NETC_SW_ENETC_DOSL2CR_MSAMCC(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_DOSL2CR_MSAMCC_SHIFT)) & NETC_SW_ENETC_DOSL2CR_MSAMCC_MASK)
66103 /*! @} */
66104 
66105 /*! @name VLANIPVMPR0 - VLAN to IPV mapping profile 0 register 0..VLAN to IPV mapping profile 1 register 0 */
66106 /*! @{ */
66107 
66108 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_MASK (0x7U)
66109 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_SHIFT (0U)
66110 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_MASK)
66111 
66112 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_MASK (0x70U)
66113 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_SHIFT (4U)
66114 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_MASK)
66115 
66116 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_MASK (0x700U)
66117 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_SHIFT (8U)
66118 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_MASK)
66119 
66120 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_MASK (0x7000U)
66121 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_SHIFT (12U)
66122 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_MASK)
66123 
66124 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_MASK (0x70000U)
66125 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_SHIFT (16U)
66126 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_MASK)
66127 
66128 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_MASK (0x700000U)
66129 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_SHIFT (20U)
66130 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_MASK)
66131 
66132 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_MASK (0x7000000U)
66133 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_SHIFT (24U)
66134 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_MASK)
66135 
66136 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_MASK (0x70000000U)
66137 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_SHIFT (28U)
66138 #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_MASK)
66139 /*! @} */
66140 
66141 /* The count of NETC_SW_ENETC_VLANIPVMPR0 */
66142 #define NETC_SW_ENETC_VLANIPVMPR0_COUNT          (2U)
66143 
66144 /*! @name VLANIPVMPR1 - VLAN to IPV mapping profile 0 register 1..VLAN to IPV mapping profile 1 register 1 */
66145 /*! @{ */
66146 
66147 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_MASK (0x7U)
66148 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_SHIFT (0U)
66149 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_MASK)
66150 
66151 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_MASK (0x70U)
66152 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_SHIFT (4U)
66153 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_MASK)
66154 
66155 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_MASK (0x700U)
66156 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_SHIFT (8U)
66157 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_MASK)
66158 
66159 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_MASK (0x7000U)
66160 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_SHIFT (12U)
66161 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_MASK)
66162 
66163 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_MASK (0x70000U)
66164 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_SHIFT (16U)
66165 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_MASK)
66166 
66167 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_MASK (0x700000U)
66168 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_SHIFT (20U)
66169 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_MASK)
66170 
66171 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_MASK (0x7000000U)
66172 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_SHIFT (24U)
66173 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_MASK)
66174 
66175 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_MASK (0x70000000U)
66176 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_SHIFT (28U)
66177 #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_MASK)
66178 /*! @} */
66179 
66180 /* The count of NETC_SW_ENETC_VLANIPVMPR1 */
66181 #define NETC_SW_ENETC_VLANIPVMPR1_COUNT          (2U)
66182 
66183 /*! @name VLANDRMPR - VLAN to DR mapping profile 0 register..VLAN to DR mapping profile 1 register */
66184 /*! @{ */
66185 
66186 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_MASK   (0x3U)
66187 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_SHIFT  (0U)
66188 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_MASK)
66189 
66190 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_MASK   (0xCU)
66191 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_SHIFT  (2U)
66192 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_MASK)
66193 
66194 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_MASK   (0x30U)
66195 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_SHIFT  (4U)
66196 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_MASK)
66197 
66198 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_MASK   (0xC0U)
66199 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_SHIFT  (6U)
66200 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_MASK)
66201 
66202 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_MASK   (0x300U)
66203 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_SHIFT  (8U)
66204 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_MASK)
66205 
66206 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_MASK   (0xC00U)
66207 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_SHIFT  (10U)
66208 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_MASK)
66209 
66210 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_MASK   (0x3000U)
66211 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_SHIFT  (12U)
66212 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_MASK)
66213 
66214 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_MASK   (0xC000U)
66215 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_SHIFT  (14U)
66216 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_MASK)
66217 
66218 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_MASK   (0x30000U)
66219 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_SHIFT  (16U)
66220 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_MASK)
66221 
66222 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_MASK   (0xC0000U)
66223 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_SHIFT  (18U)
66224 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_MASK)
66225 
66226 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_MASK  (0x300000U)
66227 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_SHIFT (20U)
66228 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_MASK)
66229 
66230 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_MASK  (0xC00000U)
66231 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_SHIFT (22U)
66232 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_MASK)
66233 
66234 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_MASK  (0x3000000U)
66235 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_SHIFT (24U)
66236 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_MASK)
66237 
66238 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_MASK  (0xC000000U)
66239 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_SHIFT (26U)
66240 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_MASK)
66241 
66242 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_MASK  (0x30000000U)
66243 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_SHIFT (28U)
66244 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_MASK)
66245 
66246 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_MASK  (0xC0000000U)
66247 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_SHIFT (30U)
66248 #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_MASK)
66249 /*! @} */
66250 
66251 /* The count of NETC_SW_ENETC_VLANDRMPR */
66252 #define NETC_SW_ENETC_VLANDRMPR_COUNT            (2U)
66253 
66254 /*! @name IPFCAPR - Ingress port filter capability register */
66255 /*! @{ */
66256 
66257 #define NETC_SW_ENETC_IPFCAPR_RP_MASK            (0x1U)
66258 #define NETC_SW_ENETC_IPFCAPR_RP_SHIFT           (0U)
66259 /*! RP - Rate Policer function supported */
66260 #define NETC_SW_ENETC_IPFCAPR_RP(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_RP_SHIFT)) & NETC_SW_ENETC_IPFCAPR_RP_MASK)
66261 
66262 #define NETC_SW_ENETC_IPFCAPR_ISID_MASK          (0x2U)
66263 #define NETC_SW_ENETC_IPFCAPR_ISID_SHIFT         (1U)
66264 /*! ISID - Ingress Stream Identification supported. */
66265 #define NETC_SW_ENETC_IPFCAPR_ISID(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_ISID_SHIFT)) & NETC_SW_ENETC_IPFCAPR_ISID_MASK)
66266 
66267 #define NETC_SW_ENETC_IPFCAPR_FWD_SI_MASK        (0x4U)
66268 #define NETC_SW_ENETC_IPFCAPR_FWD_SI_SHIFT       (2U)
66269 #define NETC_SW_ENETC_IPFCAPR_FWD_SI(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_FWD_SI_SHIFT)) & NETC_SW_ENETC_IPFCAPR_FWD_SI_MASK)
66270 
66271 #define NETC_SW_ENETC_IPFCAPR_WOL_MASK           (0x8U)
66272 #define NETC_SW_ENETC_IPFCAPR_WOL_SHIFT          (3U)
66273 #define NETC_SW_ENETC_IPFCAPR_WOL(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_WOL_SHIFT)) & NETC_SW_ENETC_IPFCAPR_WOL_MASK)
66274 /*! @} */
66275 
66276 /*! @name IPFTCAPR - Ingress port filter table capability register */
66277 /*! @{ */
66278 
66279 #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_MASK    (0xFFFFU)
66280 #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_SHIFT   (0U)
66281 #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_MASK)
66282 
66283 #define NETC_SW_ENETC_IPFTCAPR_MGMT_MASK         (0x10000U)
66284 #define NETC_SW_ENETC_IPFTCAPR_MGMT_SHIFT        (16U)
66285 #define NETC_SW_ENETC_IPFTCAPR_MGMT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_MGMT_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_MGMT_MASK)
66286 
66287 #define NETC_SW_ENETC_IPFTCAPR_ACCESS_METH_MASK  (0xF00000U)
66288 #define NETC_SW_ENETC_IPFTCAPR_ACCESS_METH_SHIFT (20U)
66289 #define NETC_SW_ENETC_IPFTCAPR_ACCESS_METH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_ACCESS_METH_MASK)
66290 
66291 #define NETC_SW_ENETC_IPFTCAPR_ENTRY_MAX_WORDS_MASK (0xF000000U)
66292 #define NETC_SW_ENETC_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT (24U)
66293 #define NETC_SW_ENETC_IPFTCAPR_ENTRY_MAX_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_ENTRY_MAX_WORDS_MASK)
66294 
66295 #define NETC_SW_ENETC_IPFTCAPR_WORD_SIZE_MASK    (0x30000000U)
66296 #define NETC_SW_ENETC_IPFTCAPR_WORD_SIZE_SHIFT   (28U)
66297 #define NETC_SW_ENETC_IPFTCAPR_WORD_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_WORD_SIZE_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_WORD_SIZE_MASK)
66298 /*! @} */
66299 
66300 /*! @name IPFTMOR - Ingress port filter table memory operational register */
66301 /*! @{ */
66302 
66303 #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS_MASK     (0xFFFFU)
66304 #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS_SHIFT    (0U)
66305 #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_IPFTMOR_NUM_WORDS_MASK)
66306 /*! @} */
66307 
66308 /*! @name ITMCAPR - Index table memory capability register */
66309 /*! @{ */
66310 
66311 #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS_MASK     (0xFFFFU)
66312 #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS_SHIFT    (0U)
66313 #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ITMCAPR_NUM_WORDS_MASK)
66314 
66315 #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE_MASK     (0x30000000U)
66316 #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE_SHIFT    (28U)
66317 #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_WORD_SIZE_SHIFT)) & NETC_SW_ENETC_ITMCAPR_WORD_SIZE_MASK)
66318 
66319 #define NETC_SW_ENETC_ITMCAPR_MLOC_MASK          (0xC0000000U)
66320 #define NETC_SW_ENETC_ITMCAPR_MLOC_SHIFT         (30U)
66321 #define NETC_SW_ENETC_ITMCAPR_MLOC(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_MLOC_SHIFT)) & NETC_SW_ENETC_ITMCAPR_MLOC_MASK)
66322 /*! @} */
66323 
66324 /*! @name RPCAPR - Rate policer capability register */
66325 /*! @{ */
66326 
66327 #define NETC_SW_ENETC_RPCAPR_TRTCM_MASK          (0x1U)
66328 #define NETC_SW_ENETC_RPCAPR_TRTCM_SHIFT         (0U)
66329 /*! TRTCM - Two-Rate Three-Color Marker supported per MEF 10.3 standard. */
66330 #define NETC_SW_ENETC_RPCAPR_TRTCM(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPCAPR_TRTCM_SHIFT)) & NETC_SW_ENETC_RPCAPR_TRTCM_MASK)
66331 
66332 #define NETC_SW_ENETC_RPCAPR_CM_MASK             (0x2U)
66333 #define NETC_SW_ENETC_RPCAPR_CM_SHIFT            (1U)
66334 #define NETC_SW_ENETC_RPCAPR_CM(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPCAPR_CM_SHIFT)) & NETC_SW_ENETC_RPCAPR_CM_MASK)
66335 /*! @} */
66336 
66337 /*! @name RPITCAPR - Rate policer index table capability register */
66338 /*! @{ */
66339 
66340 #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_MASK  (0x3FFFU)
66341 #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_SHIFT (0U)
66342 #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_MASK)
66343 
66344 #define NETC_SW_ENETC_RPITCAPR_ACCESS_METH_MASK  (0xF00000U)
66345 #define NETC_SW_ENETC_RPITCAPR_ACCESS_METH_SHIFT (20U)
66346 #define NETC_SW_ENETC_RPITCAPR_ACCESS_METH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_RPITCAPR_ACCESS_METH_MASK)
66347 /*! @} */
66348 
66349 /*! @name RPITMAR - Rate policer index table memory allocation register */
66350 /*! @{ */
66351 
66352 #define NETC_SW_ENETC_RPITMAR_NUM_WORDS_MASK     (0xFFFFU)
66353 #define NETC_SW_ENETC_RPITMAR_NUM_WORDS_SHIFT    (0U)
66354 #define NETC_SW_ENETC_RPITMAR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_RPITMAR_NUM_WORDS_MASK)
66355 /*! @} */
66356 
66357 /*! @name RPITOR - Rate policer index table operational register */
66358 /*! @{ */
66359 
66360 #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES_MASK    (0x3FFFU)
66361 #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES_SHIFT   (0U)
66362 #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_RPITOR_NUM_ENTRIES_MASK)
66363 /*! @} */
66364 
66365 /*! @name ISCITCAPR - Ingress stream counter index table capability register */
66366 /*! @{ */
66367 
66368 #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_MASK (0xFFFFU)
66369 #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_SHIFT (0U)
66370 #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_MASK)
66371 
66372 #define NETC_SW_ENETC_ISCITCAPR_ACCESS_METH_MASK (0xF00000U)
66373 #define NETC_SW_ENETC_ISCITCAPR_ACCESS_METH_SHIFT (20U)
66374 #define NETC_SW_ENETC_ISCITCAPR_ACCESS_METH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ISCITCAPR_ACCESS_METH_MASK)
66375 /*! @} */
66376 
66377 /*! @name ISCITMAR - Ingress stream counter index table memory allocation register */
66378 /*! @{ */
66379 
66380 #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS_MASK    (0xFFFFU)
66381 #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS_SHIFT   (0U)
66382 #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ISCITMAR_NUM_WORDS_MASK)
66383 /*! @} */
66384 
66385 /*! @name ISCITOR - Ingress stream counter index table operational register */
66386 /*! @{ */
66387 
66388 #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_MASK   (0xFFFFU)
66389 #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_SHIFT  (0U)
66390 #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_MASK)
66391 /*! @} */
66392 
66393 /*! @name ISCAPR - Ingress stream capability register */
66394 /*! @{ */
66395 
66396 #define NETC_SW_ENETC_ISCAPR_ISQG_MASK           (0x2U)
66397 #define NETC_SW_ENETC_ISCAPR_ISQG_SHIFT          (1U)
66398 #define NETC_SW_ENETC_ISCAPR_ISQG(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_ISQG_SHIFT)) & NETC_SW_ENETC_ISCAPR_ISQG_MASK)
66399 
66400 #define NETC_SW_ENETC_ISCAPR_SG_MASK             (0x8U)
66401 #define NETC_SW_ENETC_ISCAPR_SG_SHIFT            (3U)
66402 #define NETC_SW_ENETC_ISCAPR_SG(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_SG_SHIFT)) & NETC_SW_ENETC_ISCAPR_SG_MASK)
66403 
66404 #define NETC_SW_ENETC_ISCAPR_RP_MASK             (0x10U)
66405 #define NETC_SW_ENETC_ISCAPR_RP_SHIFT            (4U)
66406 #define NETC_SW_ENETC_ISCAPR_RP(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_RP_SHIFT)) & NETC_SW_ENETC_ISCAPR_RP_MASK)
66407 
66408 #define NETC_SW_ENETC_ISCAPR_MAXSDU_MASK         (0x20U)
66409 #define NETC_SW_ENETC_ISCAPR_MAXSDU_SHIFT        (5U)
66410 #define NETC_SW_ENETC_ISCAPR_MAXSDU(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_MAXSDU_SHIFT)) & NETC_SW_ENETC_ISCAPR_MAXSDU_MASK)
66411 
66412 #define NETC_SW_ENETC_ISCAPR_FWD_MASK            (0x200U)
66413 #define NETC_SW_ENETC_ISCAPR_FWD_SHIFT           (9U)
66414 #define NETC_SW_ENETC_ISCAPR_FWD(x)              (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_FWD_SHIFT)) & NETC_SW_ENETC_ISCAPR_FWD_MASK)
66415 
66416 #define NETC_SW_ENETC_ISCAPR_ET_MASK             (0x400U)
66417 #define NETC_SW_ENETC_ISCAPR_ET_SHIFT            (10U)
66418 #define NETC_SW_ENETC_ISCAPR_ET(x)               (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_ET_SHIFT)) & NETC_SW_ENETC_ISCAPR_ET_MASK)
66419 /*! @} */
66420 
66421 /*! @name ISITCAPR - Ingress stream index table capability register */
66422 /*! @{ */
66423 
66424 #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_MASK  (0xFFFFU)
66425 #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_SHIFT (0U)
66426 #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_MASK)
66427 
66428 #define NETC_SW_ENETC_ISITCAPR_ACCESS_METH_MASK  (0xF00000U)
66429 #define NETC_SW_ENETC_ISITCAPR_ACCESS_METH_SHIFT (20U)
66430 #define NETC_SW_ENETC_ISITCAPR_ACCESS_METH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ISITCAPR_ACCESS_METH_MASK)
66431 /*! @} */
66432 
66433 /*! @name ISITMAR - Ingress stream index table memory allocation register */
66434 /*! @{ */
66435 
66436 #define NETC_SW_ENETC_ISITMAR_NUM_WORDS_MASK     (0xFFFFU)
66437 #define NETC_SW_ENETC_ISITMAR_NUM_WORDS_SHIFT    (0U)
66438 #define NETC_SW_ENETC_ISITMAR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ISITMAR_NUM_WORDS_MASK)
66439 /*! @} */
66440 
66441 /*! @name ISITOR - Ingress stream index table operational register */
66442 /*! @{ */
66443 
66444 #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES_MASK    (0xFFFFU)
66445 #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES_SHIFT   (0U)
66446 #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISITOR_NUM_ENTRIES_MASK)
66447 /*! @} */
66448 
66449 /*! @name ISQGITCAPR - Ingress sequence generation index table capability register */
66450 /*! @{ */
66451 
66452 #define NETC_SW_ENETC_ISQGITCAPR_NUM_ENTRIES_MASK (0xFFFFU)
66453 #define NETC_SW_ENETC_ISQGITCAPR_NUM_ENTRIES_SHIFT (0U)
66454 #define NETC_SW_ENETC_ISQGITCAPR_NUM_ENTRIES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISQGITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISQGITCAPR_NUM_ENTRIES_MASK)
66455 
66456 #define NETC_SW_ENETC_ISQGITCAPR_ACCESS_METH_MASK (0xF00000U)
66457 #define NETC_SW_ENETC_ISQGITCAPR_ACCESS_METH_SHIFT (20U)
66458 #define NETC_SW_ENETC_ISQGITCAPR_ACCESS_METH(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISQGITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ISQGITCAPR_ACCESS_METH_MASK)
66459 /*! @} */
66460 
66461 /*! @name ISQGITMAR - Ingress sequence generation index table memory allocation register */
66462 /*! @{ */
66463 
66464 #define NETC_SW_ENETC_ISQGITMAR_NUM_WORDS_MASK   (0x1FFFU)
66465 #define NETC_SW_ENETC_ISQGITMAR_NUM_WORDS_SHIFT  (0U)
66466 #define NETC_SW_ENETC_ISQGITMAR_NUM_WORDS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISQGITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ISQGITMAR_NUM_WORDS_MASK)
66467 /*! @} */
66468 
66469 /*! @name ISQGITOR - Ingress sequence generation index table operational register */
66470 /*! @{ */
66471 
66472 #define NETC_SW_ENETC_ISQGITOR_NUM_ENTRIES_MASK  (0xFFFFU)
66473 #define NETC_SW_ENETC_ISQGITOR_NUM_ENTRIES_SHIFT (0U)
66474 #define NETC_SW_ENETC_ISQGITOR_NUM_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISQGITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISQGITOR_NUM_ENTRIES_MASK)
66475 /*! @} */
66476 
66477 /*! @name SGCAPR - Stream gate capability register */
66478 /*! @{ */
66479 
66480 #define NETC_SW_ENETC_SGCAPR_GLC_AO_MASK         (0x1U)
66481 #define NETC_SW_ENETC_SGCAPR_GLC_AO_SHIFT        (0U)
66482 #define NETC_SW_ENETC_SGCAPR_GLC_AO(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_AO_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_AO_MASK)
66483 
66484 #define NETC_SW_ENETC_SGCAPR_GLC_GC_MASK         (0x2U)
66485 #define NETC_SW_ENETC_SGCAPR_GLC_GC_SHIFT        (1U)
66486 #define NETC_SW_ENETC_SGCAPR_GLC_GC(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_GC_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_GC_MASK)
66487 
66488 #define NETC_SW_ENETC_SGCAPR_GLC_IO_MASK         (0x4U)
66489 #define NETC_SW_ENETC_SGCAPR_GLC_IO_SHIFT        (2U)
66490 #define NETC_SW_ENETC_SGCAPR_GLC_IO(x)           (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_IO_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_IO_MASK)
66491 
66492 #define NETC_SW_ENETC_SGCAPR_GLC_IPV_MASK        (0x8U)
66493 #define NETC_SW_ENETC_SGCAPR_GLC_IPV_SHIFT       (3U)
66494 #define NETC_SW_ENETC_SGCAPR_GLC_IPV(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_IPV_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_IPV_MASK)
66495 
66496 #define NETC_SW_ENETC_SGCAPR_GLC_CTD_MASK        (0x10U)
66497 #define NETC_SW_ENETC_SGCAPR_GLC_CTD_SHIFT       (4U)
66498 #define NETC_SW_ENETC_SGCAPR_GLC_CTD(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_CTD_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_CTD_MASK)
66499 /*! @} */
66500 
66501 /*! @name SGIITCAPR - Stream gate instance index table capability register */
66502 /*! @{ */
66503 
66504 #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_MASK (0xFFFFU)
66505 #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_SHIFT (0U)
66506 #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_MASK)
66507 
66508 #define NETC_SW_ENETC_SGIITCAPR_ACCESS_METH_MASK (0xF00000U)
66509 #define NETC_SW_ENETC_SGIITCAPR_ACCESS_METH_SHIFT (20U)
66510 #define NETC_SW_ENETC_SGIITCAPR_ACCESS_METH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_SGIITCAPR_ACCESS_METH_MASK)
66511 /*! @} */
66512 
66513 /*! @name SGIITMAR - Stream gate instance index table memory allocation register */
66514 /*! @{ */
66515 
66516 #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS_MASK    (0xFFFFU)
66517 #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS_SHIFT   (0U)
66518 #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGIITMAR_NUM_WORDS_MASK)
66519 /*! @} */
66520 
66521 /*! @name SGIITOR - Stream gate instance index table operational register */
66522 /*! @{ */
66523 
66524 #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_MASK   (0xFFFFU)
66525 #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_SHIFT  (0U)
66526 #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_MASK)
66527 /*! @} */
66528 
66529 /*! @name SGCLITCAPR - Stream gate control list index table capability register */
66530 /*! @{ */
66531 
66532 #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_MASK  (0xFFFFU)
66533 #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_SHIFT (0U)
66534 #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_MASK)
66535 
66536 #define NETC_SW_ENETC_SGCLITCAPR_ACCESS_METH_MASK (0xF00000U)
66537 #define NETC_SW_ENETC_SGCLITCAPR_ACCESS_METH_SHIFT (20U)
66538 #define NETC_SW_ENETC_SGCLITCAPR_ACCESS_METH(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_SGCLITCAPR_ACCESS_METH_MASK)
66539 /*! @} */
66540 
66541 /*! @name SGCLITMAR - Stream gate control list index table memory allocation register */
66542 /*! @{ */
66543 
66544 #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_MASK   (0xFFFFU)
66545 #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_SHIFT  (0U)
66546 #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_MASK)
66547 /*! @} */
66548 
66549 /*! @name SGCLTMOR - Stream gate control list table memory operational register */
66550 /*! @{ */
66551 
66552 #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_MASK    (0xFFFFU)
66553 #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_SHIFT   (0U)
66554 #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_MASK)
66555 /*! @} */
66556 
66557 /*! @name FMICAPR - Frame modification ingress capability register */
66558 /*! @{ */
66559 
66560 #define NETC_SW_ENETC_FMICAPR_L2_ACT_MASK        (0xFFU)
66561 #define NETC_SW_ENETC_FMICAPR_L2_ACT_SHIFT       (0U)
66562 /*! L2_ACT - Layer 2 frame modification actions supported */
66563 #define NETC_SW_ENETC_FMICAPR_L2_ACT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMICAPR_L2_ACT_SHIFT)) & NETC_SW_ENETC_FMICAPR_L2_ACT_MASK)
66564 /*! @} */
66565 
66566 /*! @name FMECAPR - Frame modification egress capability register */
66567 /*! @{ */
66568 
66569 #define NETC_SW_ENETC_FMECAPR_L2_ACT_MASK        (0xFFU)
66570 #define NETC_SW_ENETC_FMECAPR_L2_ACT_SHIFT       (0U)
66571 /*! L2_ACT - Layer 2 frame modification actions */
66572 #define NETC_SW_ENETC_FMECAPR_L2_ACT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMECAPR_L2_ACT_SHIFT)) & NETC_SW_ENETC_FMECAPR_L2_ACT_MASK)
66573 
66574 #define NETC_SW_ENETC_FMECAPR_L3_ACT_MASK        (0xFF0000U)
66575 #define NETC_SW_ENETC_FMECAPR_L3_ACT_SHIFT       (16U)
66576 /*! L3_ACT - Layer 3 frame modification actions */
66577 #define NETC_SW_ENETC_FMECAPR_L3_ACT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMECAPR_L3_ACT_SHIFT)) & NETC_SW_ENETC_FMECAPR_L3_ACT_MASK)
66578 /*! @} */
66579 
66580 /*! @name FMITCAPR - Frame modification index table capability register */
66581 /*! @{ */
66582 
66583 #define NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES_MASK  (0x1FFFU)
66584 #define NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES_SHIFT (0U)
66585 #define NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES_MASK)
66586 
66587 #define NETC_SW_ENETC_FMITCAPR_ACCESS_METH_MASK  (0xF00000U)
66588 #define NETC_SW_ENETC_FMITCAPR_ACCESS_METH_SHIFT (20U)
66589 #define NETC_SW_ENETC_FMITCAPR_ACCESS_METH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_FMITCAPR_ACCESS_METH_MASK)
66590 /*! @} */
66591 
66592 /*! @name FMITMAR - Frame modification index table memory allocation register */
66593 /*! @{ */
66594 
66595 #define NETC_SW_ENETC_FMITMAR_NUM_WORDS_MASK     (0x1FFFU)
66596 #define NETC_SW_ENETC_FMITMAR_NUM_WORDS_SHIFT    (0U)
66597 #define NETC_SW_ENETC_FMITMAR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_FMITMAR_NUM_WORDS_MASK)
66598 /*! @} */
66599 
66600 /*! @name FMITOR - Frame modification index table operational register */
66601 /*! @{ */
66602 
66603 #define NETC_SW_ENETC_FMITOR_NUM_ENTRIES_MASK    (0x1FFFU)
66604 #define NETC_SW_ENETC_FMITOR_NUM_ENTRIES_SHIFT   (0U)
66605 #define NETC_SW_ENETC_FMITOR_NUM_ENTRIES(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_FMITOR_NUM_ENTRIES_MASK)
66606 /*! @} */
66607 
66608 /*! @name FMDITCAPR - Frame modification data index table capability register */
66609 /*! @{ */
66610 
66611 #define NETC_SW_ENETC_FMDITCAPR_NUM_WORDS_MASK   (0xFFFFU)
66612 #define NETC_SW_ENETC_FMDITCAPR_NUM_WORDS_SHIFT  (0U)
66613 #define NETC_SW_ENETC_FMDITCAPR_NUM_WORDS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMDITCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_FMDITCAPR_NUM_WORDS_MASK)
66614 
66615 #define NETC_SW_ENETC_FMDITCAPR_ACCESS_METH_MASK (0xF00000U)
66616 #define NETC_SW_ENETC_FMDITCAPR_ACCESS_METH_SHIFT (20U)
66617 #define NETC_SW_ENETC_FMDITCAPR_ACCESS_METH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMDITCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_FMDITCAPR_ACCESS_METH_MASK)
66618 /*! @} */
66619 
66620 /*! @name FMDITMAR - Frame modification data index table memory allocation register */
66621 /*! @{ */
66622 
66623 #define NETC_SW_ENETC_FMDITMAR_NUM_WORDS_MASK    (0xFFFFU)
66624 #define NETC_SW_ENETC_FMDITMAR_NUM_WORDS_SHIFT   (0U)
66625 #define NETC_SW_ENETC_FMDITMAR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_FMDITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_FMDITMAR_NUM_WORDS_MASK)
66626 /*! @} */
66627 
66628 /*! @name ETCAPR - Egress treatment capability register */
66629 /*! @{ */
66630 
66631 #define NETC_SW_ENETC_ETCAPR_ESQR_MASK           (0x1U)
66632 #define NETC_SW_ENETC_ETCAPR_ESQR_SHIFT          (0U)
66633 /*! ESQR - Egress Sequence Recovery supported */
66634 #define NETC_SW_ENETC_ETCAPR_ESQR(x)             (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ETCAPR_ESQR_SHIFT)) & NETC_SW_ENETC_ETCAPR_ESQR_MASK)
66635 /*! @} */
66636 
66637 /*! @name ETTCAPR - Egress treatment table capability register */
66638 /*! @{ */
66639 
66640 #define NETC_SW_ENETC_ETTCAPR_NUM_ENTRIES_MASK   (0xFFFFU)
66641 #define NETC_SW_ENETC_ETTCAPR_NUM_ENTRIES_SHIFT  (0U)
66642 #define NETC_SW_ENETC_ETTCAPR_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ETTCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ETTCAPR_NUM_ENTRIES_MASK)
66643 
66644 #define NETC_SW_ENETC_ETTCAPR_ACCESS_METH_MASK   (0xF00000U)
66645 #define NETC_SW_ENETC_ETTCAPR_ACCESS_METH_SHIFT  (20U)
66646 #define NETC_SW_ENETC_ETTCAPR_ACCESS_METH(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ETTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ETTCAPR_ACCESS_METH_MASK)
66647 /*! @} */
66648 
66649 /*! @name ETTOR - Egress treatment table operational register */
66650 /*! @{ */
66651 
66652 #define NETC_SW_ENETC_ETTOR_NUM_ENTRIES_MASK     (0xFFFFU)
66653 #define NETC_SW_ENETC_ETTOR_NUM_ENTRIES_SHIFT    (0U)
66654 #define NETC_SW_ENETC_ETTOR_NUM_ENTRIES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ETTOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ETTOR_NUM_ENTRIES_MASK)
66655 /*! @} */
66656 
66657 /*! @name TGSTCAPR - Time gate scheduling table capability register */
66658 /*! @{ */
66659 
66660 #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_MASK    (0xFFFFU)
66661 #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_SHIFT   (0U)
66662 /*! NUM_WORDS - Number of Words */
66663 #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_MASK)
66664 
66665 #define NETC_SW_ENETC_TGSTCAPR_ACCESS_METH_MASK  (0xF00000U)
66666 #define NETC_SW_ENETC_TGSTCAPR_ACCESS_METH_SHIFT (20U)
66667 /*! ACCESS_METH - Access Method
66668  *  0bxxx1..Index
66669  *  0bxx1x..EntryId
66670  *  0bx1xx..Search
66671  *  0b1xxx..
66672  */
66673 #define NETC_SW_ENETC_TGSTCAPR_ACCESS_METH(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_TGSTCAPR_ACCESS_METH_MASK)
66674 
66675 #define NETC_SW_ENETC_TGSTCAPR_MAX_GCL_LEN_MASK  (0x3000000U)
66676 #define NETC_SW_ENETC_TGSTCAPR_MAX_GCL_LEN_SHIFT (24U)
66677 /*! MAX_GCL_LEN - Maximum Gate Control List Length
66678  *  0b00..64
66679  *  0b01..128
66680  *  0b10..256
66681  *  0b11..
66682  */
66683 #define NETC_SW_ENETC_TGSTCAPR_MAX_GCL_LEN(x)    (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTCAPR_MAX_GCL_LEN_SHIFT)) & NETC_SW_ENETC_TGSTCAPR_MAX_GCL_LEN_MASK)
66684 /*! @} */
66685 
66686 /*! @name TGSTMOR - Time gate scheduling table memory operation register */
66687 /*! @{ */
66688 
66689 #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS_MASK     (0xFFFFU)
66690 #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS_SHIFT    (0U)
66691 #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_TGSTMOR_NUM_WORDS_MASK)
66692 /*! @} */
66693 
66694 /*! @name ESQRCAPR - Egress sequence recovery capability register */
66695 /*! @{ */
66696 
66697 #define NETC_SW_ENETC_ESQRCAPR_SQR_TYPE_MASK     (0x3U)
66698 #define NETC_SW_ENETC_ESQRCAPR_SQR_TYPE_SHIFT    (0U)
66699 #define NETC_SW_ENETC_ESQRCAPR_SQR_TYPE(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ESQRCAPR_SQR_TYPE_SHIFT)) & NETC_SW_ENETC_ESQRCAPR_SQR_TYPE_MASK)
66700 
66701 #define NETC_SW_ENETC_ESQRCAPR_SQR_ALG_MASK      (0xCU)
66702 #define NETC_SW_ENETC_ESQRCAPR_SQR_ALG_SHIFT     (2U)
66703 #define NETC_SW_ENETC_ESQRCAPR_SQR_ALG(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ESQRCAPR_SQR_ALG_SHIFT)) & NETC_SW_ENETC_ESQRCAPR_SQR_ALG_MASK)
66704 
66705 #define NETC_SW_ENETC_ESQRCAPR_SQR_MAX_HL_MASK   (0x700U)
66706 #define NETC_SW_ENETC_ESQRCAPR_SQR_MAX_HL_SHIFT  (8U)
66707 #define NETC_SW_ENETC_ESQRCAPR_SQR_MAX_HL(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ESQRCAPR_SQR_MAX_HL_SHIFT)) & NETC_SW_ENETC_ESQRCAPR_SQR_MAX_HL_MASK)
66708 /*! @} */
66709 
66710 /*! @name ESQRTCAPR - Egress sequence recovery table capability register */
66711 /*! @{ */
66712 
66713 #define NETC_SW_ENETC_ESQRTCAPR_NUM_ENTRIES_MASK (0xFFFFU)
66714 #define NETC_SW_ENETC_ESQRTCAPR_NUM_ENTRIES_SHIFT (0U)
66715 #define NETC_SW_ENETC_ESQRTCAPR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ESQRTCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ESQRTCAPR_NUM_ENTRIES_MASK)
66716 
66717 #define NETC_SW_ENETC_ESQRTCAPR_ACCESS_METH_MASK (0xF00000U)
66718 #define NETC_SW_ENETC_ESQRTCAPR_ACCESS_METH_SHIFT (20U)
66719 #define NETC_SW_ENETC_ESQRTCAPR_ACCESS_METH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ESQRTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ESQRTCAPR_ACCESS_METH_MASK)
66720 /*! @} */
66721 
66722 /*! @name ECTCAPR - Egress counter table capability register */
66723 /*! @{ */
66724 
66725 #define NETC_SW_ENETC_ECTCAPR_NUM_ENTRIES_MASK   (0xFFFFU)
66726 #define NETC_SW_ENETC_ECTCAPR_NUM_ENTRIES_SHIFT  (0U)
66727 #define NETC_SW_ENETC_ECTCAPR_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ECTCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ECTCAPR_NUM_ENTRIES_MASK)
66728 
66729 #define NETC_SW_ENETC_ECTCAPR_ACCESS_METH_MASK   (0xF00000U)
66730 #define NETC_SW_ENETC_ECTCAPR_ACCESS_METH_SHIFT  (20U)
66731 #define NETC_SW_ENETC_ECTCAPR_ACCESS_METH(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ECTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ECTCAPR_ACCESS_METH_MASK)
66732 /*! @} */
66733 
66734 /*! @name HTMCAPR - Hash table memory capability register */
66735 /*! @{ */
66736 
66737 #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS_MASK     (0xFFFFU)
66738 #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS_SHIFT    (0U)
66739 #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_HTMCAPR_NUM_WORDS_MASK)
66740 
66741 #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE_MASK     (0x30000000U)
66742 #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE_SHIFT    (28U)
66743 #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE(x)       (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_WORD_SIZE_SHIFT)) & NETC_SW_ENETC_HTMCAPR_WORD_SIZE_MASK)
66744 
66745 #define NETC_SW_ENETC_HTMCAPR_MLOC_MASK          (0xC0000000U)
66746 #define NETC_SW_ENETC_HTMCAPR_MLOC_SHIFT         (30U)
66747 #define NETC_SW_ENETC_HTMCAPR_MLOC(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_MLOC_SHIFT)) & NETC_SW_ENETC_HTMCAPR_MLOC_MASK)
66748 /*! @} */
66749 
66750 /*! @name HTMOR - Hash table memory operational register */
66751 /*! @{ */
66752 
66753 #define NETC_SW_ENETC_HTMOR_AMOUNT_MASK          (0xFFFFU)
66754 #define NETC_SW_ENETC_HTMOR_AMOUNT_SHIFT         (0U)
66755 #define NETC_SW_ENETC_HTMOR_AMOUNT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMOR_AMOUNT_SHIFT)) & NETC_SW_ENETC_HTMOR_AMOUNT_MASK)
66756 
66757 #define NETC_SW_ENETC_HTMOR_WATERMARK_MASK       (0xFFFF0000U)
66758 #define NETC_SW_ENETC_HTMOR_WATERMARK_SHIFT      (16U)
66759 #define NETC_SW_ENETC_HTMOR_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMOR_WATERMARK_SHIFT)) & NETC_SW_ENETC_HTMOR_WATERMARK_MASK)
66760 /*! @} */
66761 
66762 /*! @name ISIDCAPR - Ingress stream identification capability register */
66763 /*! @{ */
66764 
66765 #define NETC_SW_ENETC_ISIDCAPR_NUM_KC_MASK       (0x3U)
66766 #define NETC_SW_ENETC_ISIDCAPR_NUM_KC_SHIFT      (0U)
66767 #define NETC_SW_ENETC_ISIDCAPR_NUM_KC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_NUM_KC_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_NUM_KC_MASK)
66768 
66769 #define NETC_SW_ENETC_ISIDCAPR_NUM_PF_MASK       (0x1CU)
66770 #define NETC_SW_ENETC_ISIDCAPR_NUM_PF_SHIFT      (2U)
66771 #define NETC_SW_ENETC_ISIDCAPR_NUM_PF(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_NUM_PF_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_NUM_PF_MASK)
66772 
66773 #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_MASK    (0x1F00U)
66774 #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_SHIFT   (8U)
66775 #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE(x)      (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_MASK)
66776 
66777 #define NETC_SW_ENETC_ISIDCAPR_UFT_MASK          (0x10000U)
66778 #define NETC_SW_ENETC_ISIDCAPR_UFT_SHIFT         (16U)
66779 #define NETC_SW_ENETC_ISIDCAPR_UFT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_UFT_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_UFT_MASK)
66780 
66781 #define NETC_SW_ENETC_ISIDCAPR_ETHFT_MASK        (0x20000U)
66782 #define NETC_SW_ENETC_ISIDCAPR_ETHFT_SHIFT       (17U)
66783 #define NETC_SW_ENETC_ISIDCAPR_ETHFT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_ETHFT_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_ETHFT_MASK)
66784 /*! @} */
66785 
66786 /*! @name ISIDHTCAPR - Ingress stream identification hash table capability register */
66787 /*! @{ */
66788 
66789 #define NETC_SW_ENETC_ISIDHTCAPR_ACCESS_METH_MASK (0xF00000U)
66790 #define NETC_SW_ENETC_ISIDHTCAPR_ACCESS_METH_SHIFT (20U)
66791 #define NETC_SW_ENETC_ISIDHTCAPR_ACCESS_METH(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDHTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ISIDHTCAPR_ACCESS_METH_MASK)
66792 /*! @} */
66793 
66794 /*! @name ISIDKC0OR - Ingress stream identification key construction 0 operational register */
66795 /*! @{ */
66796 
66797 #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_MASK (0xFFFFU)
66798 #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_SHIFT (0U)
66799 #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_MASK)
66800 
66801 #define NETC_SW_ENETC_ISIDKC0OR_EN_MASK          (0x80000000U)
66802 #define NETC_SW_ENETC_ISIDKC0OR_EN_SHIFT         (31U)
66803 #define NETC_SW_ENETC_ISIDKC0OR_EN(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC0OR_EN_MASK)
66804 /*! @} */
66805 
66806 /*! @name ISIDKC0CR0 - Ingress stream identification key construction 0 configuration register 0 */
66807 /*! @{ */
66808 
66809 #define NETC_SW_ENETC_ISIDKC0CR0_VALID_MASK      (0x1U)
66810 #define NETC_SW_ENETC_ISIDKC0CR0_VALID_SHIFT     (0U)
66811 /*! VALID - Valid
66812  *  0b0..The entire key construction rule is not valid including any configuration payload key fields defined.
66813  *  0b1..The key construction rule is valid.
66814  */
66815 #define NETC_SW_ENETC_ISIDKC0CR0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_VALID_MASK)
66816 
66817 #define NETC_SW_ENETC_ISIDKC0CR0_PORTP_MASK      (0x2U)
66818 #define NETC_SW_ENETC_ISIDKC0CR0_PORTP_SHIFT     (1U)
66819 /*! PORTP
66820  *  0b0..Not present
66821  *  0b1..Present
66822  */
66823 #define NETC_SW_ENETC_ISIDKC0CR0_PORTP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_PORTP_MASK)
66824 
66825 #define NETC_SW_ENETC_ISIDKC0CR0_SPMP_MASK       (0x4U)
66826 #define NETC_SW_ENETC_ISIDKC0CR0_SPMP_SHIFT      (2U)
66827 /*! SPMP - Switch Port Masquerading (flag) Present
66828  *  0b0..Not present
66829  *  0b1..Present
66830  */
66831 #define NETC_SW_ENETC_ISIDKC0CR0_SPMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_SPMP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_SPMP_MASK)
66832 
66833 #define NETC_SW_ENETC_ISIDKC0CR0_DMACP_MASK      (0x8U)
66834 #define NETC_SW_ENETC_ISIDKC0CR0_DMACP_SHIFT     (3U)
66835 /*! DMACP - Destination MAC (address) Present
66836  *  0b0..Not present
66837  *  0b1..Present
66838  */
66839 #define NETC_SW_ENETC_ISIDKC0CR0_DMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_DMACP_MASK)
66840 
66841 #define NETC_SW_ENETC_ISIDKC0CR0_SMACP_MASK      (0x10U)
66842 #define NETC_SW_ENETC_ISIDKC0CR0_SMACP_SHIFT     (4U)
66843 /*! SMACP - Source MAC (address) Present.
66844  *  0b0..Not present
66845  *  0b1..Present
66846  */
66847 #define NETC_SW_ENETC_ISIDKC0CR0_SMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_SMACP_MASK)
66848 
66849 #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK      (0x20U)
66850 #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT     (5U)
66851 /*! OVIDP - Outer VID Present
66852  *  0b0..Not present
66853  *  0b1..Present
66854  */
66855 #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK)
66856 
66857 #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP_MASK      (0x40U)
66858 #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP_SHIFT     (6U)
66859 /*! OPCPP - Outer PCP Present
66860  *  0b0..Outer VLAN header's PCP field not present in the key
66861  *  0b1..Outer VLAN header's PCP field present in the key
66862  */
66863 #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_OPCPP_MASK)
66864 
66865 #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK      (0x80U)
66866 #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT     (7U)
66867 /*! IVIDP - Inner VID Present.
66868  *  0b0..Not present
66869  *  0b1..Present
66870  */
66871 #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK)
66872 
66873 #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK      (0x100U)
66874 #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT     (8U)
66875 /*! IPCPP - Inner PCP Present.
66876  *  0b0..Not present
66877  *  0b1..Present
66878  */
66879 #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK)
66880 
66881 #define NETC_SW_ENETC_ISIDKC0CR0_SQTP_MASK       (0x200U)
66882 #define NETC_SW_ENETC_ISIDKC0CR0_SQTP_SHIFT      (9U)
66883 /*! SQTP - Sequence Tag (code point) Present.
66884  *  0b0..Not present
66885  *  0b1..Present
66886  */
66887 #define NETC_SW_ENETC_ISIDKC0CR0_SQTP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_SQTP_MASK)
66888 
66889 #define NETC_SW_ENETC_ISIDKC0CR0_ETP_MASK        (0x400U)
66890 #define NETC_SW_ENETC_ISIDKC0CR0_ETP_SHIFT       (10U)
66891 /*! ETP - EtherType Present.
66892  *  0b0..Not present
66893  *  0b1..Present
66894  */
66895 #define NETC_SW_ENETC_ISIDKC0CR0_ETP(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_ETP_MASK)
66896 /*! @} */
66897 
66898 /*! @name ISIDKC0PF0CR - Ingress stream identification key construction 0 payload field 0 configuration register */
66899 /*! @{ */
66900 
66901 #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP_MASK      (0x1U)
66902 #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP_SHIFT     (0U)
66903 #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_PFP_MASK)
66904 
66905 #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_MASK (0x1EU)
66906 #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_SHIFT (1U)
66907 #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_MASK)
66908 
66909 #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_MASK (0x7F00U)
66910 #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT (8U)
66911 #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_MASK)
66912 
66913 #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_MASK   (0x70000U)
66914 #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_SHIFT  (16U)
66915 #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_MASK)
66916 
66917 #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_MASK   (0x700000U)
66918 #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_SHIFT  (20U)
66919 #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_MASK)
66920 /*! @} */
66921 
66922 /*! @name ISIDKC0PF1CR - Ingress stream identification key construction 0 payload field 1 configuration register */
66923 /*! @{ */
66924 
66925 #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP_MASK      (0x1U)
66926 #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP_SHIFT     (0U)
66927 #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_PFP_MASK)
66928 
66929 #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_MASK (0x1EU)
66930 #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_SHIFT (1U)
66931 #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_MASK)
66932 
66933 #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_MASK (0x7F00U)
66934 #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT (8U)
66935 #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_MASK)
66936 
66937 #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_MASK   (0x70000U)
66938 #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_SHIFT  (16U)
66939 #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_MASK)
66940 
66941 #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_MASK   (0x700000U)
66942 #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_SHIFT  (20U)
66943 #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_MASK)
66944 /*! @} */
66945 
66946 /*! @name ISIDKC0PF2CR - Ingress stream identification key construction 0 payload field 2 configuration register */
66947 /*! @{ */
66948 
66949 #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP_MASK      (0x1U)
66950 #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP_SHIFT     (0U)
66951 #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_PFP_MASK)
66952 
66953 #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_MASK (0x1EU)
66954 #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_SHIFT (1U)
66955 #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_MASK)
66956 
66957 #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_MASK (0x7F00U)
66958 #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT (8U)
66959 #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_MASK)
66960 
66961 #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_MASK   (0x70000U)
66962 #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_SHIFT  (16U)
66963 #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_MASK)
66964 
66965 #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_MASK   (0x700000U)
66966 #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_SHIFT  (20U)
66967 #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_MASK)
66968 /*! @} */
66969 
66970 /*! @name ISIDKC0PF3CR - Ingress stream identification key construction 0 payload field 3 configuration register */
66971 /*! @{ */
66972 
66973 #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP_MASK      (0x1U)
66974 #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP_SHIFT     (0U)
66975 #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_PFP_MASK)
66976 
66977 #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_MASK (0x1EU)
66978 #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_SHIFT (1U)
66979 #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_MASK)
66980 
66981 #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_MASK (0x7F00U)
66982 #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT (8U)
66983 #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_MASK)
66984 
66985 #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_MASK   (0x70000U)
66986 #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_SHIFT  (16U)
66987 #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_MASK)
66988 
66989 #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_MASK   (0x700000U)
66990 #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_SHIFT  (20U)
66991 #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_MASK)
66992 /*! @} */
66993 
66994 /*! @name ISIDKC1OR - Ingress stream identification key construction 1 operational register */
66995 /*! @{ */
66996 
66997 #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_MASK (0xFFFFU)
66998 #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_SHIFT (0U)
66999 #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_MASK)
67000 
67001 #define NETC_SW_ENETC_ISIDKC1OR_EN_MASK          (0x80000000U)
67002 #define NETC_SW_ENETC_ISIDKC1OR_EN_SHIFT         (31U)
67003 #define NETC_SW_ENETC_ISIDKC1OR_EN(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC1OR_EN_MASK)
67004 /*! @} */
67005 
67006 /*! @name ISIDKC1CR0 - Ingress stream identification key construction 1 configuration register 0 */
67007 /*! @{ */
67008 
67009 #define NETC_SW_ENETC_ISIDKC1CR0_VALID_MASK      (0x1U)
67010 #define NETC_SW_ENETC_ISIDKC1CR0_VALID_SHIFT     (0U)
67011 /*! VALID - Valid
67012  *  0b0..The entire key construction rule is not valid including any configuration payload key fields defined.
67013  *  0b1..The key construction rule is valid.
67014  */
67015 #define NETC_SW_ENETC_ISIDKC1CR0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_VALID_MASK)
67016 
67017 #define NETC_SW_ENETC_ISIDKC1CR0_PORTP_MASK      (0x2U)
67018 #define NETC_SW_ENETC_ISIDKC1CR0_PORTP_SHIFT     (1U)
67019 /*! PORTP
67020  *  0b0..Not present
67021  *  0b1..Present
67022  */
67023 #define NETC_SW_ENETC_ISIDKC1CR0_PORTP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_PORTP_MASK)
67024 
67025 #define NETC_SW_ENETC_ISIDKC1CR0_SPMP_MASK       (0x4U)
67026 #define NETC_SW_ENETC_ISIDKC1CR0_SPMP_SHIFT      (2U)
67027 /*! SPMP - Switch Port Masquerading (flag) Present
67028  *  0b0..Not present
67029  *  0b1..Present
67030  */
67031 #define NETC_SW_ENETC_ISIDKC1CR0_SPMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_SPMP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_SPMP_MASK)
67032 
67033 #define NETC_SW_ENETC_ISIDKC1CR0_DMACP_MASK      (0x8U)
67034 #define NETC_SW_ENETC_ISIDKC1CR0_DMACP_SHIFT     (3U)
67035 /*! DMACP - Destination MAC (address) Present
67036  *  0b0..Not present
67037  *  0b1..Present
67038  */
67039 #define NETC_SW_ENETC_ISIDKC1CR0_DMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_DMACP_MASK)
67040 
67041 #define NETC_SW_ENETC_ISIDKC1CR0_SMACP_MASK      (0x10U)
67042 #define NETC_SW_ENETC_ISIDKC1CR0_SMACP_SHIFT     (4U)
67043 /*! SMACP - Source MAC (address) Present.
67044  *  0b0..Not present
67045  *  0b1..Present
67046  */
67047 #define NETC_SW_ENETC_ISIDKC1CR0_SMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_SMACP_MASK)
67048 
67049 #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK      (0x20U)
67050 #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT     (5U)
67051 /*! OVIDP - Outer VID Present
67052  *  0b0..Not present
67053  *  0b1..Present
67054  */
67055 #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK)
67056 
67057 #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP_MASK      (0x40U)
67058 #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP_SHIFT     (6U)
67059 /*! OPCPP - Outer PCP Present
67060  *  0b0..Outer VLAN header's PCP field not present in the key
67061  *  0b1..Outer VLAN header's PCP field present in the key
67062  */
67063 #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_OPCPP_MASK)
67064 
67065 #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK      (0x80U)
67066 #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT     (7U)
67067 /*! IVIDP - Inner VID Present.
67068  *  0b0..Not present
67069  *  0b1..Present
67070  */
67071 #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK)
67072 
67073 #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK      (0x100U)
67074 #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT     (8U)
67075 /*! IPCPP - Inner PCP Present.
67076  *  0b0..Not present
67077  *  0b1..Present
67078  */
67079 #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK)
67080 
67081 #define NETC_SW_ENETC_ISIDKC1CR0_SQTP_MASK       (0x200U)
67082 #define NETC_SW_ENETC_ISIDKC1CR0_SQTP_SHIFT      (9U)
67083 /*! SQTP - Sequence Tag (code point) Present.
67084  *  0b0..Not present
67085  *  0b1..Present
67086  */
67087 #define NETC_SW_ENETC_ISIDKC1CR0_SQTP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_SQTP_MASK)
67088 
67089 #define NETC_SW_ENETC_ISIDKC1CR0_ETP_MASK        (0x400U)
67090 #define NETC_SW_ENETC_ISIDKC1CR0_ETP_SHIFT       (10U)
67091 /*! ETP - EtherType Present.
67092  *  0b0..Not present
67093  *  0b1..Present
67094  */
67095 #define NETC_SW_ENETC_ISIDKC1CR0_ETP(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_ETP_MASK)
67096 /*! @} */
67097 
67098 /*! @name ISIDKC1PF0CR - Ingress stream identification key construction 1 payload field 0 configuration register */
67099 /*! @{ */
67100 
67101 #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP_MASK      (0x1U)
67102 #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP_SHIFT     (0U)
67103 #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_PFP_MASK)
67104 
67105 #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_MASK (0x1EU)
67106 #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_SHIFT (1U)
67107 #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_MASK)
67108 
67109 #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_MASK (0x7F00U)
67110 #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT (8U)
67111 #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_MASK)
67112 
67113 #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_MASK   (0x70000U)
67114 #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_SHIFT  (16U)
67115 #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_MASK)
67116 
67117 #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_MASK   (0x700000U)
67118 #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_SHIFT  (20U)
67119 #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_MASK)
67120 /*! @} */
67121 
67122 /*! @name ISIDKC1PF1CR - Ingress stream identification key construction 1 payload field 1 configuration register */
67123 /*! @{ */
67124 
67125 #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP_MASK      (0x1U)
67126 #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP_SHIFT     (0U)
67127 #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_PFP_MASK)
67128 
67129 #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_MASK (0x1EU)
67130 #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_SHIFT (1U)
67131 #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_MASK)
67132 
67133 #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_MASK (0x7F00U)
67134 #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT (8U)
67135 #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_MASK)
67136 
67137 #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_MASK   (0x70000U)
67138 #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_SHIFT  (16U)
67139 #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_MASK)
67140 
67141 #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_MASK   (0x700000U)
67142 #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_SHIFT  (20U)
67143 #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_MASK)
67144 /*! @} */
67145 
67146 /*! @name ISIDKC1PF2CR - Ingress stream identification key construction 1 payload field 2 configuration register */
67147 /*! @{ */
67148 
67149 #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP_MASK      (0x1U)
67150 #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP_SHIFT     (0U)
67151 #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_PFP_MASK)
67152 
67153 #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_MASK (0x1EU)
67154 #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_SHIFT (1U)
67155 #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_MASK)
67156 
67157 #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_MASK (0x7F00U)
67158 #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT (8U)
67159 #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_MASK)
67160 
67161 #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_MASK   (0x70000U)
67162 #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_SHIFT  (16U)
67163 #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_MASK)
67164 
67165 #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_MASK   (0x700000U)
67166 #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_SHIFT  (20U)
67167 #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_MASK)
67168 /*! @} */
67169 
67170 /*! @name ISIDKC1PF3CR - Ingress stream identification key construction 1 payload field 3 configuration register */
67171 /*! @{ */
67172 
67173 #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP_MASK      (0x1U)
67174 #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP_SHIFT     (0U)
67175 #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_PFP_MASK)
67176 
67177 #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_MASK (0x1EU)
67178 #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_SHIFT (1U)
67179 #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_MASK)
67180 
67181 #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_MASK (0x7F00U)
67182 #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT (8U)
67183 #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_MASK)
67184 
67185 #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_MASK   (0x70000U)
67186 #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_SHIFT  (16U)
67187 #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_MASK)
67188 
67189 #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_MASK   (0x700000U)
67190 #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_SHIFT  (20U)
67191 #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_MASK)
67192 /*! @} */
67193 
67194 /*! @name ISIDKC2OR - Ingress stream identification key construction 2 operational register */
67195 /*! @{ */
67196 
67197 #define NETC_SW_ENETC_ISIDKC2OR_NUM_ENTRIES_MASK (0xFFFFU)
67198 #define NETC_SW_ENETC_ISIDKC2OR_NUM_ENTRIES_SHIFT (0U)
67199 #define NETC_SW_ENETC_ISIDKC2OR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC2OR_NUM_ENTRIES_MASK)
67200 
67201 #define NETC_SW_ENETC_ISIDKC2OR_EN_MASK          (0x80000000U)
67202 #define NETC_SW_ENETC_ISIDKC2OR_EN_SHIFT         (31U)
67203 #define NETC_SW_ENETC_ISIDKC2OR_EN(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC2OR_EN_MASK)
67204 /*! @} */
67205 
67206 /*! @name ISIDKC2CR0 - Ingress stream identification key construction 2 configuration register 0 */
67207 /*! @{ */
67208 
67209 #define NETC_SW_ENETC_ISIDKC2CR0_VALID_MASK      (0x1U)
67210 #define NETC_SW_ENETC_ISIDKC2CR0_VALID_SHIFT     (0U)
67211 /*! VALID - Valid
67212  *  0b0..The entire key construction rule is not valid including any configuration payload key fields defined.
67213  *  0b1..The key construction rule is valid.
67214  */
67215 #define NETC_SW_ENETC_ISIDKC2CR0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_VALID_MASK)
67216 
67217 #define NETC_SW_ENETC_ISIDKC2CR0_PORTP_MASK      (0x2U)
67218 #define NETC_SW_ENETC_ISIDKC2CR0_PORTP_SHIFT     (1U)
67219 /*! PORTP
67220  *  0b0..Not present
67221  *  0b1..Present
67222  */
67223 #define NETC_SW_ENETC_ISIDKC2CR0_PORTP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_PORTP_MASK)
67224 
67225 #define NETC_SW_ENETC_ISIDKC2CR0_SPMP_MASK       (0x4U)
67226 #define NETC_SW_ENETC_ISIDKC2CR0_SPMP_SHIFT      (2U)
67227 /*! SPMP - Switch Port Masquerading (flag) Present
67228  *  0b0..Not present
67229  *  0b1..Present
67230  */
67231 #define NETC_SW_ENETC_ISIDKC2CR0_SPMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_SPMP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_SPMP_MASK)
67232 
67233 #define NETC_SW_ENETC_ISIDKC2CR0_DMACP_MASK      (0x8U)
67234 #define NETC_SW_ENETC_ISIDKC2CR0_DMACP_SHIFT     (3U)
67235 /*! DMACP - Destination MAC (address) Present
67236  *  0b0..Not present
67237  *  0b1..Present
67238  */
67239 #define NETC_SW_ENETC_ISIDKC2CR0_DMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_DMACP_MASK)
67240 
67241 #define NETC_SW_ENETC_ISIDKC2CR0_SMACP_MASK      (0x10U)
67242 #define NETC_SW_ENETC_ISIDKC2CR0_SMACP_SHIFT     (4U)
67243 /*! SMACP - Source MAC (address) Present.
67244  *  0b0..Not present
67245  *  0b1..Present
67246  */
67247 #define NETC_SW_ENETC_ISIDKC2CR0_SMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_SMACP_MASK)
67248 
67249 #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP_MASK      (0x20U)
67250 #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP_SHIFT     (5U)
67251 /*! OVIDP - Outer VID Present
67252  *  0b0..Not present
67253  *  0b1..Present
67254  */
67255 #define NETC_SW_ENETC_ISIDKC2CR0_OVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_OVIDP_MASK)
67256 
67257 #define NETC_SW_ENETC_ISIDKC2CR0_OPCPP_MASK      (0x40U)
67258 #define NETC_SW_ENETC_ISIDKC2CR0_OPCPP_SHIFT     (6U)
67259 /*! OPCPP - Outer PCP Present
67260  *  0b0..Outer VLAN header's PCP field not present in the key
67261  *  0b1..Outer VLAN header's PCP field present in the key
67262  */
67263 #define NETC_SW_ENETC_ISIDKC2CR0_OPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_OPCPP_MASK)
67264 
67265 #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP_MASK      (0x80U)
67266 #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP_SHIFT     (7U)
67267 /*! IVIDP - Inner VID Present.
67268  *  0b0..Not present
67269  *  0b1..Present
67270  */
67271 #define NETC_SW_ENETC_ISIDKC2CR0_IVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_IVIDP_MASK)
67272 
67273 #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP_MASK      (0x100U)
67274 #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP_SHIFT     (8U)
67275 /*! IPCPP - Inner PCP Present.
67276  *  0b0..Not present
67277  *  0b1..Present
67278  */
67279 #define NETC_SW_ENETC_ISIDKC2CR0_IPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_IPCPP_MASK)
67280 
67281 #define NETC_SW_ENETC_ISIDKC2CR0_SQTP_MASK       (0x200U)
67282 #define NETC_SW_ENETC_ISIDKC2CR0_SQTP_SHIFT      (9U)
67283 /*! SQTP - Sequence Tag (code point) Present.
67284  *  0b0..Not present
67285  *  0b1..Present
67286  */
67287 #define NETC_SW_ENETC_ISIDKC2CR0_SQTP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_SQTP_MASK)
67288 
67289 #define NETC_SW_ENETC_ISIDKC2CR0_ETP_MASK        (0x400U)
67290 #define NETC_SW_ENETC_ISIDKC2CR0_ETP_SHIFT       (10U)
67291 /*! ETP - EtherType Present.
67292  *  0b0..Not present
67293  *  0b1..Present
67294  */
67295 #define NETC_SW_ENETC_ISIDKC2CR0_ETP(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC2CR0_ETP_MASK)
67296 /*! @} */
67297 
67298 /*! @name ISIDKC2PF0CR - Ingress stream identification key construction 2 payload field 0 configuration register */
67299 /*! @{ */
67300 
67301 #define NETC_SW_ENETC_ISIDKC2PF0CR_PFP_MASK      (0x1U)
67302 #define NETC_SW_ENETC_ISIDKC2PF0CR_PFP_SHIFT     (0U)
67303 #define NETC_SW_ENETC_ISIDKC2PF0CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF0CR_PFP_MASK)
67304 
67305 #define NETC_SW_ENETC_ISIDKC2PF0CR_NUM_BYTES_MASK (0x1EU)
67306 #define NETC_SW_ENETC_ISIDKC2PF0CR_NUM_BYTES_SHIFT (1U)
67307 #define NETC_SW_ENETC_ISIDKC2PF0CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF0CR_NUM_BYTES_MASK)
67308 
67309 #define NETC_SW_ENETC_ISIDKC2PF0CR_BYTE_OFFSET_MASK (0x7F00U)
67310 #define NETC_SW_ENETC_ISIDKC2PF0CR_BYTE_OFFSET_SHIFT (8U)
67311 #define NETC_SW_ENETC_ISIDKC2PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF0CR_BYTE_OFFSET_MASK)
67312 
67313 #define NETC_SW_ENETC_ISIDKC2PF0CR_FBMASK_MASK   (0x70000U)
67314 #define NETC_SW_ENETC_ISIDKC2PF0CR_FBMASK_SHIFT  (16U)
67315 #define NETC_SW_ENETC_ISIDKC2PF0CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF0CR_FBMASK_MASK)
67316 
67317 #define NETC_SW_ENETC_ISIDKC2PF0CR_LBMASK_MASK   (0x700000U)
67318 #define NETC_SW_ENETC_ISIDKC2PF0CR_LBMASK_SHIFT  (20U)
67319 #define NETC_SW_ENETC_ISIDKC2PF0CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF0CR_LBMASK_MASK)
67320 /*! @} */
67321 
67322 /*! @name ISIDKC2PF1CR - Ingress stream identification key construction 2 payload field 1 configuration register */
67323 /*! @{ */
67324 
67325 #define NETC_SW_ENETC_ISIDKC2PF1CR_PFP_MASK      (0x1U)
67326 #define NETC_SW_ENETC_ISIDKC2PF1CR_PFP_SHIFT     (0U)
67327 #define NETC_SW_ENETC_ISIDKC2PF1CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF1CR_PFP_MASK)
67328 
67329 #define NETC_SW_ENETC_ISIDKC2PF1CR_NUM_BYTES_MASK (0x1EU)
67330 #define NETC_SW_ENETC_ISIDKC2PF1CR_NUM_BYTES_SHIFT (1U)
67331 #define NETC_SW_ENETC_ISIDKC2PF1CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF1CR_NUM_BYTES_MASK)
67332 
67333 #define NETC_SW_ENETC_ISIDKC2PF1CR_BYTE_OFFSET_MASK (0x7F00U)
67334 #define NETC_SW_ENETC_ISIDKC2PF1CR_BYTE_OFFSET_SHIFT (8U)
67335 #define NETC_SW_ENETC_ISIDKC2PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF1CR_BYTE_OFFSET_MASK)
67336 
67337 #define NETC_SW_ENETC_ISIDKC2PF1CR_FBMASK_MASK   (0x70000U)
67338 #define NETC_SW_ENETC_ISIDKC2PF1CR_FBMASK_SHIFT  (16U)
67339 #define NETC_SW_ENETC_ISIDKC2PF1CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF1CR_FBMASK_MASK)
67340 
67341 #define NETC_SW_ENETC_ISIDKC2PF1CR_LBMASK_MASK   (0x700000U)
67342 #define NETC_SW_ENETC_ISIDKC2PF1CR_LBMASK_SHIFT  (20U)
67343 #define NETC_SW_ENETC_ISIDKC2PF1CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF1CR_LBMASK_MASK)
67344 /*! @} */
67345 
67346 /*! @name ISIDKC2PF2CR - Ingress stream identification key construction 2 payload field 2 configuration register */
67347 /*! @{ */
67348 
67349 #define NETC_SW_ENETC_ISIDKC2PF2CR_PFP_MASK      (0x1U)
67350 #define NETC_SW_ENETC_ISIDKC2PF2CR_PFP_SHIFT     (0U)
67351 #define NETC_SW_ENETC_ISIDKC2PF2CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF2CR_PFP_MASK)
67352 
67353 #define NETC_SW_ENETC_ISIDKC2PF2CR_NUM_BYTES_MASK (0x1EU)
67354 #define NETC_SW_ENETC_ISIDKC2PF2CR_NUM_BYTES_SHIFT (1U)
67355 #define NETC_SW_ENETC_ISIDKC2PF2CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF2CR_NUM_BYTES_MASK)
67356 
67357 #define NETC_SW_ENETC_ISIDKC2PF2CR_BYTE_OFFSET_MASK (0x7F00U)
67358 #define NETC_SW_ENETC_ISIDKC2PF2CR_BYTE_OFFSET_SHIFT (8U)
67359 #define NETC_SW_ENETC_ISIDKC2PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF2CR_BYTE_OFFSET_MASK)
67360 
67361 #define NETC_SW_ENETC_ISIDKC2PF2CR_FBMASK_MASK   (0x70000U)
67362 #define NETC_SW_ENETC_ISIDKC2PF2CR_FBMASK_SHIFT  (16U)
67363 #define NETC_SW_ENETC_ISIDKC2PF2CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF2CR_FBMASK_MASK)
67364 
67365 #define NETC_SW_ENETC_ISIDKC2PF2CR_LBMASK_MASK   (0x700000U)
67366 #define NETC_SW_ENETC_ISIDKC2PF2CR_LBMASK_SHIFT  (20U)
67367 #define NETC_SW_ENETC_ISIDKC2PF2CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF2CR_LBMASK_MASK)
67368 /*! @} */
67369 
67370 /*! @name ISIDKC2PF3CR - Ingress stream identification key construction 2 payload field 3 configuration register */
67371 /*! @{ */
67372 
67373 #define NETC_SW_ENETC_ISIDKC2PF3CR_PFP_MASK      (0x1U)
67374 #define NETC_SW_ENETC_ISIDKC2PF3CR_PFP_SHIFT     (0U)
67375 #define NETC_SW_ENETC_ISIDKC2PF3CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF3CR_PFP_MASK)
67376 
67377 #define NETC_SW_ENETC_ISIDKC2PF3CR_NUM_BYTES_MASK (0x1EU)
67378 #define NETC_SW_ENETC_ISIDKC2PF3CR_NUM_BYTES_SHIFT (1U)
67379 #define NETC_SW_ENETC_ISIDKC2PF3CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF3CR_NUM_BYTES_MASK)
67380 
67381 #define NETC_SW_ENETC_ISIDKC2PF3CR_BYTE_OFFSET_MASK (0x7F00U)
67382 #define NETC_SW_ENETC_ISIDKC2PF3CR_BYTE_OFFSET_SHIFT (8U)
67383 #define NETC_SW_ENETC_ISIDKC2PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF3CR_BYTE_OFFSET_MASK)
67384 
67385 #define NETC_SW_ENETC_ISIDKC2PF3CR_FBMASK_MASK   (0x70000U)
67386 #define NETC_SW_ENETC_ISIDKC2PF3CR_FBMASK_SHIFT  (16U)
67387 #define NETC_SW_ENETC_ISIDKC2PF3CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF3CR_FBMASK_MASK)
67388 
67389 #define NETC_SW_ENETC_ISIDKC2PF3CR_LBMASK_MASK   (0x700000U)
67390 #define NETC_SW_ENETC_ISIDKC2PF3CR_LBMASK_SHIFT  (20U)
67391 #define NETC_SW_ENETC_ISIDKC2PF3CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC2PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC2PF3CR_LBMASK_MASK)
67392 /*! @} */
67393 
67394 /*! @name ISIDKC3OR - Ingress stream identification key construction 3 operational register */
67395 /*! @{ */
67396 
67397 #define NETC_SW_ENETC_ISIDKC3OR_NUM_ENTRIES_MASK (0xFFFFU)
67398 #define NETC_SW_ENETC_ISIDKC3OR_NUM_ENTRIES_SHIFT (0U)
67399 #define NETC_SW_ENETC_ISIDKC3OR_NUM_ENTRIES(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC3OR_NUM_ENTRIES_MASK)
67400 
67401 #define NETC_SW_ENETC_ISIDKC3OR_EN_MASK          (0x80000000U)
67402 #define NETC_SW_ENETC_ISIDKC3OR_EN_SHIFT         (31U)
67403 #define NETC_SW_ENETC_ISIDKC3OR_EN(x)            (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC3OR_EN_MASK)
67404 /*! @} */
67405 
67406 /*! @name ISIDKC3CR0 - Ingress stream identification key construction 3 configuration register 0 */
67407 /*! @{ */
67408 
67409 #define NETC_SW_ENETC_ISIDKC3CR0_VALID_MASK      (0x1U)
67410 #define NETC_SW_ENETC_ISIDKC3CR0_VALID_SHIFT     (0U)
67411 /*! VALID - Valid
67412  *  0b0..The entire key construction rule is not valid including any configuration payload key fields defined.
67413  *  0b1..The key construction rule is valid.
67414  */
67415 #define NETC_SW_ENETC_ISIDKC3CR0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_VALID_MASK)
67416 
67417 #define NETC_SW_ENETC_ISIDKC3CR0_PORTP_MASK      (0x2U)
67418 #define NETC_SW_ENETC_ISIDKC3CR0_PORTP_SHIFT     (1U)
67419 /*! PORTP
67420  *  0b0..Not present
67421  *  0b1..Present
67422  */
67423 #define NETC_SW_ENETC_ISIDKC3CR0_PORTP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_PORTP_MASK)
67424 
67425 #define NETC_SW_ENETC_ISIDKC3CR0_SPMP_MASK       (0x4U)
67426 #define NETC_SW_ENETC_ISIDKC3CR0_SPMP_SHIFT      (2U)
67427 /*! SPMP - Switch Port Masquerading (flag) Present
67428  *  0b0..Not present
67429  *  0b1..Present
67430  */
67431 #define NETC_SW_ENETC_ISIDKC3CR0_SPMP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_SPMP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_SPMP_MASK)
67432 
67433 #define NETC_SW_ENETC_ISIDKC3CR0_DMACP_MASK      (0x8U)
67434 #define NETC_SW_ENETC_ISIDKC3CR0_DMACP_SHIFT     (3U)
67435 /*! DMACP - Destination MAC (address) Present
67436  *  0b0..Not present
67437  *  0b1..Present
67438  */
67439 #define NETC_SW_ENETC_ISIDKC3CR0_DMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_DMACP_MASK)
67440 
67441 #define NETC_SW_ENETC_ISIDKC3CR0_SMACP_MASK      (0x10U)
67442 #define NETC_SW_ENETC_ISIDKC3CR0_SMACP_SHIFT     (4U)
67443 /*! SMACP - Source MAC (address) Present.
67444  *  0b0..Not present
67445  *  0b1..Present
67446  */
67447 #define NETC_SW_ENETC_ISIDKC3CR0_SMACP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_SMACP_MASK)
67448 
67449 #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP_MASK      (0x20U)
67450 #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP_SHIFT     (5U)
67451 /*! OVIDP - Outer VID Present
67452  *  0b0..Not present
67453  *  0b1..Present
67454  */
67455 #define NETC_SW_ENETC_ISIDKC3CR0_OVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_OVIDP_MASK)
67456 
67457 #define NETC_SW_ENETC_ISIDKC3CR0_OPCPP_MASK      (0x40U)
67458 #define NETC_SW_ENETC_ISIDKC3CR0_OPCPP_SHIFT     (6U)
67459 /*! OPCPP - Outer PCP Present
67460  *  0b0..Outer VLAN header's PCP field not present in the key
67461  *  0b1..Outer VLAN header's PCP field present in the key
67462  */
67463 #define NETC_SW_ENETC_ISIDKC3CR0_OPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_OPCPP_MASK)
67464 
67465 #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP_MASK      (0x80U)
67466 #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP_SHIFT     (7U)
67467 /*! IVIDP - Inner VID Present.
67468  *  0b0..Not present
67469  *  0b1..Present
67470  */
67471 #define NETC_SW_ENETC_ISIDKC3CR0_IVIDP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_IVIDP_MASK)
67472 
67473 #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP_MASK      (0x100U)
67474 #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP_SHIFT     (8U)
67475 /*! IPCPP - Inner PCP Present.
67476  *  0b0..Not present
67477  *  0b1..Present
67478  */
67479 #define NETC_SW_ENETC_ISIDKC3CR0_IPCPP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_IPCPP_MASK)
67480 
67481 #define NETC_SW_ENETC_ISIDKC3CR0_SQTP_MASK       (0x200U)
67482 #define NETC_SW_ENETC_ISIDKC3CR0_SQTP_SHIFT      (9U)
67483 /*! SQTP - Sequence Tag (code point) Present.
67484  *  0b0..Not present
67485  *  0b1..Present
67486  */
67487 #define NETC_SW_ENETC_ISIDKC3CR0_SQTP(x)         (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_SQTP_MASK)
67488 
67489 #define NETC_SW_ENETC_ISIDKC3CR0_ETP_MASK        (0x400U)
67490 #define NETC_SW_ENETC_ISIDKC3CR0_ETP_SHIFT       (10U)
67491 /*! ETP - EtherType Present.
67492  *  0b0..Not present
67493  *  0b1..Present
67494  */
67495 #define NETC_SW_ENETC_ISIDKC3CR0_ETP(x)          (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC3CR0_ETP_MASK)
67496 /*! @} */
67497 
67498 /*! @name ISIDKC3PF0CR - Ingress stream identification key construction 3 payload field 0 configuration register */
67499 /*! @{ */
67500 
67501 #define NETC_SW_ENETC_ISIDKC3PF0CR_PFP_MASK      (0x1U)
67502 #define NETC_SW_ENETC_ISIDKC3PF0CR_PFP_SHIFT     (0U)
67503 #define NETC_SW_ENETC_ISIDKC3PF0CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF0CR_PFP_MASK)
67504 
67505 #define NETC_SW_ENETC_ISIDKC3PF0CR_NUM_BYTES_MASK (0x1EU)
67506 #define NETC_SW_ENETC_ISIDKC3PF0CR_NUM_BYTES_SHIFT (1U)
67507 #define NETC_SW_ENETC_ISIDKC3PF0CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF0CR_NUM_BYTES_MASK)
67508 
67509 #define NETC_SW_ENETC_ISIDKC3PF0CR_BYTE_OFFSET_MASK (0x7F00U)
67510 #define NETC_SW_ENETC_ISIDKC3PF0CR_BYTE_OFFSET_SHIFT (8U)
67511 #define NETC_SW_ENETC_ISIDKC3PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF0CR_BYTE_OFFSET_MASK)
67512 
67513 #define NETC_SW_ENETC_ISIDKC3PF0CR_FBMASK_MASK   (0x70000U)
67514 #define NETC_SW_ENETC_ISIDKC3PF0CR_FBMASK_SHIFT  (16U)
67515 #define NETC_SW_ENETC_ISIDKC3PF0CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF0CR_FBMASK_MASK)
67516 
67517 #define NETC_SW_ENETC_ISIDKC3PF0CR_LBMASK_MASK   (0x700000U)
67518 #define NETC_SW_ENETC_ISIDKC3PF0CR_LBMASK_SHIFT  (20U)
67519 #define NETC_SW_ENETC_ISIDKC3PF0CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF0CR_LBMASK_MASK)
67520 /*! @} */
67521 
67522 /*! @name ISIDKC3PF1CR - Ingress stream identification key construction 3 payload field 1 configuration register */
67523 /*! @{ */
67524 
67525 #define NETC_SW_ENETC_ISIDKC3PF1CR_PFP_MASK      (0x1U)
67526 #define NETC_SW_ENETC_ISIDKC3PF1CR_PFP_SHIFT     (0U)
67527 #define NETC_SW_ENETC_ISIDKC3PF1CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF1CR_PFP_MASK)
67528 
67529 #define NETC_SW_ENETC_ISIDKC3PF1CR_NUM_BYTES_MASK (0x1EU)
67530 #define NETC_SW_ENETC_ISIDKC3PF1CR_NUM_BYTES_SHIFT (1U)
67531 #define NETC_SW_ENETC_ISIDKC3PF1CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF1CR_NUM_BYTES_MASK)
67532 
67533 #define NETC_SW_ENETC_ISIDKC3PF1CR_BYTE_OFFSET_MASK (0x7F00U)
67534 #define NETC_SW_ENETC_ISIDKC3PF1CR_BYTE_OFFSET_SHIFT (8U)
67535 #define NETC_SW_ENETC_ISIDKC3PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF1CR_BYTE_OFFSET_MASK)
67536 
67537 #define NETC_SW_ENETC_ISIDKC3PF1CR_FBMASK_MASK   (0x70000U)
67538 #define NETC_SW_ENETC_ISIDKC3PF1CR_FBMASK_SHIFT  (16U)
67539 #define NETC_SW_ENETC_ISIDKC3PF1CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF1CR_FBMASK_MASK)
67540 
67541 #define NETC_SW_ENETC_ISIDKC3PF1CR_LBMASK_MASK   (0x700000U)
67542 #define NETC_SW_ENETC_ISIDKC3PF1CR_LBMASK_SHIFT  (20U)
67543 #define NETC_SW_ENETC_ISIDKC3PF1CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF1CR_LBMASK_MASK)
67544 /*! @} */
67545 
67546 /*! @name ISIDKC3PF2CR - Ingress stream identification key construction 3 payload field 2 configuration register */
67547 /*! @{ */
67548 
67549 #define NETC_SW_ENETC_ISIDKC3PF2CR_PFP_MASK      (0x1U)
67550 #define NETC_SW_ENETC_ISIDKC3PF2CR_PFP_SHIFT     (0U)
67551 #define NETC_SW_ENETC_ISIDKC3PF2CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF2CR_PFP_MASK)
67552 
67553 #define NETC_SW_ENETC_ISIDKC3PF2CR_NUM_BYTES_MASK (0x1EU)
67554 #define NETC_SW_ENETC_ISIDKC3PF2CR_NUM_BYTES_SHIFT (1U)
67555 #define NETC_SW_ENETC_ISIDKC3PF2CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF2CR_NUM_BYTES_MASK)
67556 
67557 #define NETC_SW_ENETC_ISIDKC3PF2CR_BYTE_OFFSET_MASK (0x7F00U)
67558 #define NETC_SW_ENETC_ISIDKC3PF2CR_BYTE_OFFSET_SHIFT (8U)
67559 #define NETC_SW_ENETC_ISIDKC3PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF2CR_BYTE_OFFSET_MASK)
67560 
67561 #define NETC_SW_ENETC_ISIDKC3PF2CR_FBMASK_MASK   (0x70000U)
67562 #define NETC_SW_ENETC_ISIDKC3PF2CR_FBMASK_SHIFT  (16U)
67563 #define NETC_SW_ENETC_ISIDKC3PF2CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF2CR_FBMASK_MASK)
67564 
67565 #define NETC_SW_ENETC_ISIDKC3PF2CR_LBMASK_MASK   (0x700000U)
67566 #define NETC_SW_ENETC_ISIDKC3PF2CR_LBMASK_SHIFT  (20U)
67567 #define NETC_SW_ENETC_ISIDKC3PF2CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF2CR_LBMASK_MASK)
67568 /*! @} */
67569 
67570 /*! @name ISIDKC3PF3CR - Ingress stream identification key construction 3 payload field 3 configuration register */
67571 /*! @{ */
67572 
67573 #define NETC_SW_ENETC_ISIDKC3PF3CR_PFP_MASK      (0x1U)
67574 #define NETC_SW_ENETC_ISIDKC3PF3CR_PFP_SHIFT     (0U)
67575 #define NETC_SW_ENETC_ISIDKC3PF3CR_PFP(x)        (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF3CR_PFP_MASK)
67576 
67577 #define NETC_SW_ENETC_ISIDKC3PF3CR_NUM_BYTES_MASK (0x1EU)
67578 #define NETC_SW_ENETC_ISIDKC3PF3CR_NUM_BYTES_SHIFT (1U)
67579 #define NETC_SW_ENETC_ISIDKC3PF3CR_NUM_BYTES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF3CR_NUM_BYTES_MASK)
67580 
67581 #define NETC_SW_ENETC_ISIDKC3PF3CR_BYTE_OFFSET_MASK (0x7F00U)
67582 #define NETC_SW_ENETC_ISIDKC3PF3CR_BYTE_OFFSET_SHIFT (8U)
67583 #define NETC_SW_ENETC_ISIDKC3PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF3CR_BYTE_OFFSET_MASK)
67584 
67585 #define NETC_SW_ENETC_ISIDKC3PF3CR_FBMASK_MASK   (0x70000U)
67586 #define NETC_SW_ENETC_ISIDKC3PF3CR_FBMASK_SHIFT  (16U)
67587 #define NETC_SW_ENETC_ISIDKC3PF3CR_FBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF3CR_FBMASK_MASK)
67588 
67589 #define NETC_SW_ENETC_ISIDKC3PF3CR_LBMASK_MASK   (0x700000U)
67590 #define NETC_SW_ENETC_ISIDKC3PF3CR_LBMASK_SHIFT  (20U)
67591 #define NETC_SW_ENETC_ISIDKC3PF3CR_LBMASK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC3PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC3PF3CR_LBMASK_MASK)
67592 /*! @} */
67593 
67594 /*! @name ISFHTCAPR - Ingress stream filter hash table capability register */
67595 /*! @{ */
67596 
67597 #define NETC_SW_ENETC_ISFHTCAPR_ACCESS_METH_MASK (0xF00000U)
67598 #define NETC_SW_ENETC_ISFHTCAPR_ACCESS_METH_SHIFT (20U)
67599 #define NETC_SW_ENETC_ISFHTCAPR_ACCESS_METH(x)   (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISFHTCAPR_ACCESS_METH_SHIFT)) & NETC_SW_ENETC_ISFHTCAPR_ACCESS_METH_MASK)
67600 /*! @} */
67601 
67602 /*! @name ISFHTOR - Ingress stream filter hash table operational register */
67603 /*! @{ */
67604 
67605 #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_MASK   (0xFFFFU)
67606 #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_SHIFT  (0U)
67607 #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_MASK)
67608 /*! @} */
67609 
67610 
67611 /*!
67612  * @}
67613  */ /* end of group NETC_SW_ENETC_Register_Masks */
67614 
67615 
67616 /* NETC_SW_ENETC - Peripheral instance base addresses */
67617 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
67618   /** Peripheral ENETC0_COMMON base address */
67619   #define ENETC0_COMMON_BASE                       (0x70B10000u)
67620   /** Peripheral ENETC0_COMMON base address */
67621   #define ENETC0_COMMON_BASE_NS                    (0x60B10000u)
67622   /** Peripheral ENETC0_COMMON base pointer */
67623   #define ENETC0_COMMON                            ((NETC_SW_ENETC_Type *)ENETC0_COMMON_BASE)
67624   /** Peripheral ENETC0_COMMON base pointer */
67625   #define ENETC0_COMMON_NS                         ((NETC_SW_ENETC_Type *)ENETC0_COMMON_BASE_NS)
67626   /** Peripheral ENETC1_COMMON base address */
67627   #define ENETC1_COMMON_BASE                       (0x70B50000u)
67628   /** Peripheral ENETC1_COMMON base address */
67629   #define ENETC1_COMMON_BASE_NS                    (0x60B50000u)
67630   /** Peripheral ENETC1_COMMON base pointer */
67631   #define ENETC1_COMMON                            ((NETC_SW_ENETC_Type *)ENETC1_COMMON_BASE)
67632   /** Peripheral ENETC1_COMMON base pointer */
67633   #define ENETC1_COMMON_NS                         ((NETC_SW_ENETC_Type *)ENETC1_COMMON_BASE_NS)
67634   /** Peripheral SW0_COMMON base address */
67635   #define SW0_COMMON_BASE                          (0x70A00000u)
67636   /** Peripheral SW0_COMMON base address */
67637   #define SW0_COMMON_BASE_NS                       (0x60A00000u)
67638   /** Peripheral SW0_COMMON base pointer */
67639   #define SW0_COMMON                               ((NETC_SW_ENETC_Type *)SW0_COMMON_BASE)
67640   /** Peripheral SW0_COMMON base pointer */
67641   #define SW0_COMMON_NS                            ((NETC_SW_ENETC_Type *)SW0_COMMON_BASE_NS)
67642   /** Array initializer of NETC_SW_ENETC peripheral base addresses */
67643   #define NETC_SW_ENETC_BASE_ADDRS                 { ENETC0_COMMON_BASE, ENETC1_COMMON_BASE, SW0_COMMON_BASE }
67644   /** Array initializer of NETC_SW_ENETC peripheral base pointers */
67645   #define NETC_SW_ENETC_BASE_PTRS                  { ENETC0_COMMON, ENETC1_COMMON, SW0_COMMON }
67646   /** Array initializer of NETC_SW_ENETC peripheral base addresses */
67647   #define NETC_SW_ENETC_BASE_ADDRS_NS              { ENETC0_COMMON_BASE_NS, ENETC1_COMMON_BASE_NS, SW0_COMMON_BASE_NS }
67648   /** Array initializer of NETC_SW_ENETC peripheral base pointers */
67649   #define NETC_SW_ENETC_BASE_PTRS_NS               { ENETC0_COMMON_NS, ENETC1_COMMON_NS, SW0_COMMON_NS }
67650 #else
67651   /** Peripheral ENETC0_COMMON base address */
67652   #define ENETC0_COMMON_BASE                       (0x60B10000u)
67653   /** Peripheral ENETC0_COMMON base pointer */
67654   #define ENETC0_COMMON                            ((NETC_SW_ENETC_Type *)ENETC0_COMMON_BASE)
67655   /** Peripheral ENETC1_COMMON base address */
67656   #define ENETC1_COMMON_BASE                       (0x60B50000u)
67657   /** Peripheral ENETC1_COMMON base pointer */
67658   #define ENETC1_COMMON                            ((NETC_SW_ENETC_Type *)ENETC1_COMMON_BASE)
67659   /** Peripheral SW0_COMMON base address */
67660   #define SW0_COMMON_BASE                          (0x60A00000u)
67661   /** Peripheral SW0_COMMON base pointer */
67662   #define SW0_COMMON                               ((NETC_SW_ENETC_Type *)SW0_COMMON_BASE)
67663   /** Array initializer of NETC_SW_ENETC peripheral base addresses */
67664   #define NETC_SW_ENETC_BASE_ADDRS                 { ENETC0_COMMON_BASE, ENETC1_COMMON_BASE, SW0_COMMON_BASE }
67665   /** Array initializer of NETC_SW_ENETC peripheral base pointers */
67666   #define NETC_SW_ENETC_BASE_PTRS                  { ENETC0_COMMON, ENETC1_COMMON, SW0_COMMON }
67667 #endif
67668 
67669 /*!
67670  * @}
67671  */ /* end of group NETC_SW_ENETC_Peripheral_Access_Layer */
67672 
67673 
67674 /* ----------------------------------------------------------------------------
67675    -- OCOTP_FSB Peripheral Access Layer
67676    ---------------------------------------------------------------------------- */
67677 
67678 /*!
67679  * @addtogroup OCOTP_FSB_Peripheral_Access_Layer OCOTP_FSB Peripheral Access Layer
67680  * @{
67681  */
67682 
67683 /** OCOTP_FSB - Register Layout Typedef */
67684 typedef struct {
67685   __IO uint32_t OTP_SHADOW_PARTA[52];              /**< OTP shadow register, array offset: 0x0, array step: 0x4 */
67686        uint8_t RESERVED_0[1040];
67687   __IO uint32_t OTP_SHADOW_PARTB[200];             /**< OTP shadow register, array offset: 0x4E0, array step: 0x4 */
67688 } OCOTP_FSB_Type;
67689 
67690 /* ----------------------------------------------------------------------------
67691    -- OCOTP_FSB Register Masks
67692    ---------------------------------------------------------------------------- */
67693 
67694 /*!
67695  * @addtogroup OCOTP_FSB_Register_Masks OCOTP_FSB Register Masks
67696  * @{
67697  */
67698 
67699 /*! @name OTP_SHADOW_PARTA - OTP shadow register */
67700 /*! @{ */
67701 
67702 #define OCOTP_FSB_OTP_SHADOW_PARTA_SHADOW_MASK   (0xFFFFFFFFU)
67703 #define OCOTP_FSB_OTP_SHADOW_PARTA_SHADOW_SHIFT  (0U)
67704 /*! SHADOW - OTP shadow register, fsb have read access of shadow 0-51 (offset should be 0*4-51*4) */
67705 #define OCOTP_FSB_OTP_SHADOW_PARTA_SHADOW(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_FSB_OTP_SHADOW_PARTA_SHADOW_SHIFT)) & OCOTP_FSB_OTP_SHADOW_PARTA_SHADOW_MASK)
67706 /*! @} */
67707 
67708 /* The count of OCOTP_FSB_OTP_SHADOW_PARTA */
67709 #define OCOTP_FSB_OTP_SHADOW_PARTA_COUNT         (52U)
67710 
67711 /*! @name OTP_SHADOW_PARTB - OTP shadow register */
67712 /*! @{ */
67713 
67714 #define OCOTP_FSB_OTP_SHADOW_PARTB_SHADOW_MASK   (0xFFFFFFFFU)
67715 #define OCOTP_FSB_OTP_SHADOW_PARTB_SHADOW_SHIFT  (0U)
67716 /*! SHADOW - OTP shadow register, fsb have read access of shadow 312-511 (offset should be 312*4-511*4) */
67717 #define OCOTP_FSB_OTP_SHADOW_PARTB_SHADOW(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_FSB_OTP_SHADOW_PARTB_SHADOW_SHIFT)) & OCOTP_FSB_OTP_SHADOW_PARTB_SHADOW_MASK)
67718 /*! @} */
67719 
67720 /* The count of OCOTP_FSB_OTP_SHADOW_PARTB */
67721 #define OCOTP_FSB_OTP_SHADOW_PARTB_COUNT         (200U)
67722 
67723 
67724 /*!
67725  * @}
67726  */ /* end of group OCOTP_FSB_Register_Masks */
67727 
67728 
67729 /* OCOTP_FSB - Peripheral instance base addresses */
67730 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
67731   /** Peripheral OCOTP_FSB base address */
67732   #define OCOTP_FSB_BASE                           (0x57518000u)
67733   /** Peripheral OCOTP_FSB base address */
67734   #define OCOTP_FSB_BASE_NS                        (0x47518000u)
67735   /** Peripheral OCOTP_FSB base pointer */
67736   #define OCOTP_FSB                                ((OCOTP_FSB_Type *)OCOTP_FSB_BASE)
67737   /** Peripheral OCOTP_FSB base pointer */
67738   #define OCOTP_FSB_NS                             ((OCOTP_FSB_Type *)OCOTP_FSB_BASE_NS)
67739   /** Array initializer of OCOTP_FSB peripheral base addresses */
67740   #define OCOTP_FSB_BASE_ADDRS                     { OCOTP_FSB_BASE }
67741   /** Array initializer of OCOTP_FSB peripheral base pointers */
67742   #define OCOTP_FSB_BASE_PTRS                      { OCOTP_FSB }
67743   /** Array initializer of OCOTP_FSB peripheral base addresses */
67744   #define OCOTP_FSB_BASE_ADDRS_NS                  { OCOTP_FSB_BASE_NS }
67745   /** Array initializer of OCOTP_FSB peripheral base pointers */
67746   #define OCOTP_FSB_BASE_PTRS_NS                   { OCOTP_FSB_NS }
67747 #else
67748   /** Peripheral OCOTP_FSB base address */
67749   #define OCOTP_FSB_BASE                           (0x47518000u)
67750   /** Peripheral OCOTP_FSB base pointer */
67751   #define OCOTP_FSB                                ((OCOTP_FSB_Type *)OCOTP_FSB_BASE)
67752   /** Array initializer of OCOTP_FSB peripheral base addresses */
67753   #define OCOTP_FSB_BASE_ADDRS                     { OCOTP_FSB_BASE }
67754   /** Array initializer of OCOTP_FSB peripheral base pointers */
67755   #define OCOTP_FSB_BASE_PTRS                      { OCOTP_FSB }
67756 #endif
67757 
67758 /*!
67759  * @}
67760  */ /* end of group OCOTP_FSB_Peripheral_Access_Layer */
67761 
67762 
67763 /* ----------------------------------------------------------------------------
67764    -- OSC_RC_400M Peripheral Access Layer
67765    ---------------------------------------------------------------------------- */
67766 
67767 /*!
67768  * @addtogroup OSC_RC_400M_Peripheral_Access_Layer OSC_RC_400M Peripheral Access Layer
67769  * @{
67770  */
67771 
67772 /** OSC_RC_400M - Register Layout Typedef */
67773 typedef struct {
67774   struct {                                         /* offset: 0x0 */
67775     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
67776     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
67777     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
67778     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
67779   } CTRL0;
67780   struct {                                         /* offset: 0x10 */
67781     __IO uint32_t RW;                                /**< Analog Control Register CTRL1, offset: 0x10 */
67782     __IO uint32_t SET;                               /**< Analog Control Register CTRL1, offset: 0x14 */
67783     __IO uint32_t CLR;                               /**< Analog Control Register CTRL1, offset: 0x18 */
67784     __IO uint32_t TOG;                               /**< Analog Control Register CTRL1, offset: 0x1C */
67785   } CTRL1;
67786   struct {                                         /* offset: 0x20 */
67787     __IO uint32_t RW;                                /**< Analog Control Register CTRL2, offset: 0x20 */
67788     __IO uint32_t SET;                               /**< Analog Control Register CTRL2, offset: 0x24 */
67789     __IO uint32_t CLR;                               /**< Analog Control Register CTRL2, offset: 0x28 */
67790     __IO uint32_t TOG;                               /**< Analog Control Register CTRL2, offset: 0x2C */
67791   } CTRL2;
67792   struct {                                         /* offset: 0x30 */
67793     __IO uint32_t RW;                                /**< Analog Control Register CTRL3, offset: 0x30 */
67794     __IO uint32_t SET;                               /**< Analog Control Register CTRL3, offset: 0x34 */
67795     __IO uint32_t CLR;                               /**< Analog Control Register CTRL3, offset: 0x38 */
67796     __IO uint32_t TOG;                               /**< Analog Control Register CTRL3, offset: 0x3C */
67797   } CTRL3;
67798        uint8_t RESERVED_0[16];
67799   __I  uint32_t STAT0;                             /**< Analog Status Register STAT0, offset: 0x50 */
67800        uint8_t RESERVED_1[12];
67801   __I  uint32_t STAT1;                             /**< Analog Status Register STAT1, offset: 0x60 */
67802        uint8_t RESERVED_2[12];
67803   __I  uint32_t STAT2;                             /**< Analog Status Register STAT2, offset: 0x70 */
67804 } OSC_RC_400M_Type;
67805 
67806 /* ----------------------------------------------------------------------------
67807    -- OSC_RC_400M Register Masks
67808    ---------------------------------------------------------------------------- */
67809 
67810 /*!
67811  * @addtogroup OSC_RC_400M_Register_Masks OSC_RC_400M Register Masks
67812  * @{
67813  */
67814 
67815 /*! @name CTRL0 - Analog Control Register CTRL0 */
67816 /*! @{ */
67817 
67818 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK       (0x3F000000U)
67819 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT      (24U)
67820 /*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk. */
67821 #define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)         (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
67822 /*! @} */
67823 
67824 /*! @name CTRL1 - Analog Control Register CTRL1 */
67825 /*! @{ */
67826 
67827 #define OSC_RC_400M_CTRL1_HYST_MINUS_MASK        (0xFU)
67828 #define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT       (0U)
67829 /*! HYST_MINUS - Negative hysteresis value for the tuned clock. */
67830 #define OSC_RC_400M_CTRL1_HYST_MINUS(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
67831 
67832 #define OSC_RC_400M_CTRL1_HYST_PLUS_MASK         (0xF00U)
67833 #define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT        (8U)
67834 /*! HYST_PLUS - Positive hysteresis value for the tuned clock. */
67835 #define OSC_RC_400M_CTRL1_HYST_PLUS(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
67836 
67837 #define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK      (0xFFFF0000U)
67838 #define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT     (16U)
67839 /*! TARGET_COUNT - Target count for the fast clock. */
67840 #define OSC_RC_400M_CTRL1_TARGET_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
67841 /*! @} */
67842 
67843 /*! @name CTRL2 - Analog Control Register CTRL2 */
67844 /*! @{ */
67845 
67846 #define OSC_RC_400M_CTRL2_TUNE_INV_MASK          (0x100U)
67847 #define OSC_RC_400M_CTRL2_TUNE_INV_SHIFT         (8U)
67848 /*! TUNE_INV - Inverse tuning direction. */
67849 #define OSC_RC_400M_CTRL2_TUNE_INV(x)            (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_INV_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_INV_MASK)
67850 
67851 #define OSC_RC_400M_CTRL2_TUNE_BYP_MASK          (0x400U)
67852 #define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT         (10U)
67853 /*! TUNE_BYP - Bypass the tuning logic */
67854 #define OSC_RC_400M_CTRL2_TUNE_BYP(x)            (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
67855 
67856 #define OSC_RC_400M_CTRL2_TUNE_EN_MASK           (0x1000U)
67857 #define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT          (12U)
67858 /*! TUNE_EN - Freeze/Unfreeze the tuning value. */
67859 #define OSC_RC_400M_CTRL2_TUNE_EN(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
67860 
67861 #define OSC_RC_400M_CTRL2_TUNE_START_MASK        (0x4000U)
67862 #define OSC_RC_400M_CTRL2_TUNE_START_SHIFT       (14U)
67863 /*! TUNE_START - Start/Stop tuning. */
67864 #define OSC_RC_400M_CTRL2_TUNE_START(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
67865 
67866 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK      (0xFF000000U)
67867 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT     (24U)
67868 /*! OSC_TUNE_VAL - Program the oscillator frequency. */
67869 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
67870 /*! @} */
67871 
67872 /*! @name CTRL3 - Analog Control Register CTRL3 */
67873 /*! @{ */
67874 
67875 #define OSC_RC_400M_CTRL3_CLR_ERR_MASK           (0x1U)
67876 #define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT          (0U)
67877 /*! CLR_ERR - Clear the error flag CLK1M_ERR
67878  *  0b0..Normal operation
67879  *  0b1..Clears the error flag CLK1M_ERR in status register STAT0.
67880  */
67881 #define OSC_RC_400M_CTRL3_CLR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
67882 
67883 #define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK         (0x100U)
67884 #define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT        (8U)
67885 /*! EN_1M_CLK - 1: Disable clk_1m_out. */
67886 #define OSC_RC_400M_CTRL3_EN_1M_CLK(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
67887 
67888 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK        (0x400U)
67889 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT       (10U)
67890 /*! MUX_1M_CLK - Select free/locked 1MHz output */
67891 #define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
67892 
67893 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK      (0xFFFF0000U)
67894 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT     (16U)
67895 /*! COUNT_1M_CLK - Count for the locked clk_1m_out. */
67896 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
67897 /*! @} */
67898 
67899 /*! @name STAT0 - Analog Status Register STAT0 */
67900 /*! @{ */
67901 
67902 #define OSC_RC_400M_STAT0_CLK1M_ERR_MASK         (0x1U)
67903 #define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT        (0U)
67904 /*! CLK1M_ERR - Error flag for clk_1m_locked.
67905  *  0b0..No error.
67906  *  0b1..Indicates error.
67907  */
67908 #define OSC_RC_400M_STAT0_CLK1M_ERR(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
67909 /*! @} */
67910 
67911 /*! @name STAT1 - Analog Status Register STAT1 */
67912 /*! @{ */
67913 
67914 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK    (0xFFFF0000U)
67915 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
67916 /*! CURR_COUNT_VAL - Current count for the fast clock. */
67917 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)      (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
67918 /*! @} */
67919 
67920 /*! @name STAT2 - Analog Status Register STAT2 */
67921 /*! @{ */
67922 
67923 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
67924 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
67925 /*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator. */
67926 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
67927 /*! @} */
67928 
67929 
67930 /*!
67931  * @}
67932  */ /* end of group OSC_RC_400M_Register_Masks */
67933 
67934 
67935 /* OSC_RC_400M - Peripheral instance base addresses */
67936 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
67937   /** Peripheral OSC_RC_400M base address */
67938   #define OSC_RC_400M_BASE                         (0x54484380u)
67939   /** Peripheral OSC_RC_400M base address */
67940   #define OSC_RC_400M_BASE_NS                      (0x44484380u)
67941   /** Peripheral OSC_RC_400M base pointer */
67942   #define OSC_RC_400M                              ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
67943   /** Peripheral OSC_RC_400M base pointer */
67944   #define OSC_RC_400M_NS                           ((OSC_RC_400M_Type *)OSC_RC_400M_BASE_NS)
67945   /** Array initializer of OSC_RC_400M peripheral base addresses */
67946   #define OSC_RC_400M_BASE_ADDRS                   { OSC_RC_400M_BASE }
67947   /** Array initializer of OSC_RC_400M peripheral base pointers */
67948   #define OSC_RC_400M_BASE_PTRS                    { OSC_RC_400M }
67949   /** Array initializer of OSC_RC_400M peripheral base addresses */
67950   #define OSC_RC_400M_BASE_ADDRS_NS                { OSC_RC_400M_BASE_NS }
67951   /** Array initializer of OSC_RC_400M peripheral base pointers */
67952   #define OSC_RC_400M_BASE_PTRS_NS                 { OSC_RC_400M_NS }
67953 #else
67954   /** Peripheral OSC_RC_400M base address */
67955   #define OSC_RC_400M_BASE                         (0x44484380u)
67956   /** Peripheral OSC_RC_400M base pointer */
67957   #define OSC_RC_400M                              ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
67958   /** Array initializer of OSC_RC_400M peripheral base addresses */
67959   #define OSC_RC_400M_BASE_ADDRS                   { OSC_RC_400M_BASE }
67960   /** Array initializer of OSC_RC_400M peripheral base pointers */
67961   #define OSC_RC_400M_BASE_PTRS                    { OSC_RC_400M }
67962 #endif
67963 
67964 /*!
67965  * @}
67966  */ /* end of group OSC_RC_400M_Peripheral_Access_Layer */
67967 
67968 
67969 /* ----------------------------------------------------------------------------
67970    -- OTFAD Peripheral Access Layer
67971    ---------------------------------------------------------------------------- */
67972 
67973 /*!
67974  * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
67975  * @{
67976  */
67977 
67978 /** OTFAD - Register Layout Typedef */
67979 typedef struct {
67980        uint8_t RESERVED_0[3072];
67981   __IO uint32_t CR;                                /**< Control Register, offset: 0xC00 */
67982   __IO uint32_t SR;                                /**< Status Register, offset: 0xC04 */
67983        uint8_t RESERVED_1[248];
67984   struct {                                         /* offset: 0xD00, array step: 0x40 */
67985     __IO uint32_t KEY[4];                            /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
67986     __IO uint32_t CTR[2];                            /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
67987     __IO uint32_t RGD_W0;                            /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
67988     __IO uint32_t RGD_W1;                            /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
67989          uint8_t RESERVED_0[32];
67990   } CTX[4];
67991 } OTFAD_Type;
67992 
67993 /* ----------------------------------------------------------------------------
67994    -- OTFAD Register Masks
67995    ---------------------------------------------------------------------------- */
67996 
67997 /*!
67998  * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
67999  * @{
68000  */
68001 
68002 /*! @name CR - Control Register */
68003 /*! @{ */
68004 
68005 #define OTFAD_CR_FERR_MASK                       (0x2U)
68006 #define OTFAD_CR_FERR_SHIFT                      (1U)
68007 /*! FERR - Force Error
68008  *  0b0..No effect on the SR[KBERE] indicator.
68009  *  0b1..SR[KBERR] is immediately set after a write with this data bit set.
68010  */
68011 #define OTFAD_CR_FERR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
68012 
68013 #define OTFAD_CR_FLDM_MASK                       (0x8U)
68014 #define OTFAD_CR_FLDM_SHIFT                      (3U)
68015 /*! FLDM - Force Logically Disabled Mode
68016  *  0b0..No effect on the operating mode.
68017  *  0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
68018  */
68019 #define OTFAD_CR_FLDM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
68020 
68021 #define OTFAD_CR_KBSE_MASK                       (0x10U)
68022 #define OTFAD_CR_KBSE_SHIFT                      (4U)
68023 /*! KBSE - Key Blob Scramble Enable
68024  *  0b0..Key blob KEK scrambling is disabled.
68025  *  0b1..Key blob KEK scrambling is enabled.
68026  */
68027 #define OTFAD_CR_KBSE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
68028 
68029 #define OTFAD_CR_KBPE_MASK                       (0x20U)
68030 #define OTFAD_CR_KBPE_SHIFT                      (5U)
68031 /*! KBPE - Key Blob Processing Enable
68032  *  0b0..Key blob processing is disabled.
68033  *  0b1..Key blob processing is enabled.
68034  */
68035 #define OTFAD_CR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
68036 
68037 #define OTFAD_CR_RRAE_MASK                       (0x80U)
68038 #define OTFAD_CR_RRAE_SHIFT                      (7U)
68039 /*! RRAE - Restricted Register Access Enable
68040  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
68041  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
68042  */
68043 #define OTFAD_CR_RRAE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
68044 
68045 #define OTFAD_CR_SKBP_MASK                       (0x40000000U)
68046 #define OTFAD_CR_SKBP_SHIFT                      (30U)
68047 /*! SKBP - Start key blob processing
68048  *  0b0..Key blob processing is not initiated.
68049  *  0b1..Properly-enabled key blob processing is initiated.
68050  */
68051 #define OTFAD_CR_SKBP(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
68052 
68053 #define OTFAD_CR_GE_MASK                         (0x80000000U)
68054 #define OTFAD_CR_GE_SHIFT                        (31U)
68055 /*! GE - Global OTFAD Enable
68056  *  0b0..OTFAD has decryption disabled. All data fetched by the QuadSPI bypasses OTFAD processing.
68057  *  0b1..OTFAD has decryption enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration.
68058  */
68059 #define OTFAD_CR_GE(x)                           (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
68060 /*! @} */
68061 
68062 /*! @name SR - Status Register */
68063 /*! @{ */
68064 
68065 #define OTFAD_SR_KBERR_MASK                      (0x1U)
68066 #define OTFAD_SR_KBERR_SHIFT                     (0U)
68067 /*! KBERR - Key Blob Error
68068  *  0b0..No key blob error detected.
68069  *  0b1..One or more key blob errors has been detected.
68070  */
68071 #define OTFAD_SR_KBERR(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
68072 
68073 #define OTFAD_SR_MDPCP_MASK                      (0x2U)
68074 #define OTFAD_SR_MDPCP_SHIFT                     (1U)
68075 /*! MDPCP - MDPC Present */
68076 #define OTFAD_SR_MDPCP(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
68077 
68078 #define OTFAD_SR_MODE_MASK                       (0xCU)
68079 #define OTFAD_SR_MODE_SHIFT                      (2U)
68080 /*! MODE - Operating Mode
68081  *  0b00..Operating in Normal mode (NRM)
68082  *  0b01..Unused (reserved)
68083  *  0b10..Unused (reserved)
68084  *  0b11..Operating in Logically Disabled Mode (LDM)
68085  */
68086 #define OTFAD_SR_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
68087 
68088 #define OTFAD_SR_NCTX_MASK                       (0xF0U)
68089 #define OTFAD_SR_NCTX_SHIFT                      (4U)
68090 /*! NCTX - Number of Contexts */
68091 #define OTFAD_SR_NCTX(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
68092 
68093 #define OTFAD_SR_CTXER0_MASK                     (0x100U)
68094 #define OTFAD_SR_CTXER0_SHIFT                    (8U)
68095 /*! CTXER0 - Context Error
68096  *  0b0..No key blob error was detected for context "n".
68097  *  0b1..A key blob integrity error might have been detected in context "n".
68098  */
68099 #define OTFAD_SR_CTXER0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
68100 
68101 #define OTFAD_SR_CTXER1_MASK                     (0x200U)
68102 #define OTFAD_SR_CTXER1_SHIFT                    (9U)
68103 /*! CTXER1 - Context Error
68104  *  0b0..No key blob error was detected for context "n".
68105  *  0b1..A key blob integrity error might have been detected in context "n".
68106  */
68107 #define OTFAD_SR_CTXER1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
68108 
68109 #define OTFAD_SR_CTXER2_MASK                     (0x400U)
68110 #define OTFAD_SR_CTXER2_SHIFT                    (10U)
68111 /*! CTXER2 - Context Error
68112  *  0b0..No key blob error was detected for context "n".
68113  *  0b1..A key blob integrity error might have been detected in context "n".
68114  */
68115 #define OTFAD_SR_CTXER2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
68116 
68117 #define OTFAD_SR_CTXER3_MASK                     (0x800U)
68118 #define OTFAD_SR_CTXER3_SHIFT                    (11U)
68119 /*! CTXER3 - Context Error
68120  *  0b0..No key blob error was detected for context "n".
68121  *  0b1..A key blob integrity error might have been detected in context "n".
68122  */
68123 #define OTFAD_SR_CTXER3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
68124 
68125 #define OTFAD_SR_CTXIE0_MASK                     (0x10000U)
68126 #define OTFAD_SR_CTXIE0_SHIFT                    (16U)
68127 /*! CTXIE0 - Context Integrity Error
68128  *  0b0..No key blob integrity error was detected for context "n".
68129  *  0b1..A key blob integrity error was detected in context "n".
68130  */
68131 #define OTFAD_SR_CTXIE0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
68132 
68133 #define OTFAD_SR_CTXIE1_MASK                     (0x20000U)
68134 #define OTFAD_SR_CTXIE1_SHIFT                    (17U)
68135 /*! CTXIE1 - Context Integrity Error
68136  *  0b0..No key blob integrity error was detected for context "n".
68137  *  0b1..A key blob integrity error was detected in context "n".
68138  */
68139 #define OTFAD_SR_CTXIE1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
68140 
68141 #define OTFAD_SR_CTXIE2_MASK                     (0x40000U)
68142 #define OTFAD_SR_CTXIE2_SHIFT                    (18U)
68143 /*! CTXIE2 - Context Integrity Error
68144  *  0b0..No key blob integrity error was detected for context "n".
68145  *  0b1..A key blob integrity error was detected in context "n".
68146  */
68147 #define OTFAD_SR_CTXIE2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
68148 
68149 #define OTFAD_SR_CTXIE3_MASK                     (0x80000U)
68150 #define OTFAD_SR_CTXIE3_SHIFT                    (19U)
68151 /*! CTXIE3 - Context Integrity Error
68152  *  0b0..No key blob integrity error was detected for context "n".
68153  *  0b1..A key blob integrity error was detected in context "n".
68154  */
68155 #define OTFAD_SR_CTXIE3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
68156 
68157 #define OTFAD_SR_HRL_MASK                        (0xF000000U)
68158 #define OTFAD_SR_HRL_SHIFT                       (24U)
68159 /*! HRL - Hardware Revision Level */
68160 #define OTFAD_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
68161 
68162 #define OTFAD_SR_RRAM_MASK                       (0x10000000U)
68163 #define OTFAD_SR_RRAM_SHIFT                      (28U)
68164 /*! RRAM - Restricted Register Access Mode
68165  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
68166  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
68167  */
68168 #define OTFAD_SR_RRAM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
68169 
68170 #define OTFAD_SR_GEM_MASK                        (0x20000000U)
68171 #define OTFAD_SR_GEM_SHIFT                       (29U)
68172 /*! GEM - Global Enable Mode
68173  *  0b0..OTFAD is disabled. All data fetched by the QuadSPI bypasses OTFAD processing.
68174  *  0b1..OTFAD is enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration.
68175  */
68176 #define OTFAD_SR_GEM(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
68177 
68178 #define OTFAD_SR_KBPE_MASK                       (0x40000000U)
68179 #define OTFAD_SR_KBPE_SHIFT                      (30U)
68180 /*! KBPE - Key Blob Processing Enable
68181  *  0b0..Key blob processing is not enabled.
68182  *  0b1..Key blob processing is enabled.
68183  */
68184 #define OTFAD_SR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
68185 
68186 #define OTFAD_SR_KBD_MASK                        (0x80000000U)
68187 #define OTFAD_SR_KBD_SHIFT                       (31U)
68188 /*! KBD - Key Blob Processing Done
68189  *  0b0..Key blob processing was not enabled, or is not complete.
68190  *  0b1..Key blob processing was enabled and is complete.
68191  */
68192 #define OTFAD_SR_KBD(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
68193 /*! @} */
68194 
68195 /*! @name KEY - AES Key Word */
68196 /*! @{ */
68197 
68198 #define OTFAD_KEY_KEY_MASK                       (0xFFFFFFFFU)
68199 #define OTFAD_KEY_KEY_SHIFT                      (0U)
68200 /*! KEY - AES Key */
68201 #define OTFAD_KEY_KEY(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
68202 /*! @} */
68203 
68204 /* The count of OTFAD_KEY */
68205 #define OTFAD_KEY_COUNT                          (4U)
68206 
68207 /* The count of OTFAD_KEY */
68208 #define OTFAD_KEY_COUNT2                         (4U)
68209 
68210 /*! @name CTR - AES Counter Word */
68211 /*! @{ */
68212 
68213 #define OTFAD_CTR_CTR_MASK                       (0xFFFFFFFFU)
68214 #define OTFAD_CTR_CTR_SHIFT                      (0U)
68215 /*! CTR - AES Counter */
68216 #define OTFAD_CTR_CTR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
68217 /*! @} */
68218 
68219 /* The count of OTFAD_CTR */
68220 #define OTFAD_CTR_COUNT                          (4U)
68221 
68222 /* The count of OTFAD_CTR */
68223 #define OTFAD_CTR_COUNT2                         (2U)
68224 
68225 /*! @name RGD_W0 - AES Region Descriptor Word0 */
68226 /*! @{ */
68227 
68228 #define OTFAD_RGD_W0_SRTADDR_MASK                (0xFFFFFC00U)
68229 #define OTFAD_RGD_W0_SRTADDR_SHIFT               (10U)
68230 /*! SRTADDR - Start Address */
68231 #define OTFAD_RGD_W0_SRTADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
68232 /*! @} */
68233 
68234 /* The count of OTFAD_RGD_W0 */
68235 #define OTFAD_RGD_W0_COUNT                       (4U)
68236 
68237 /*! @name RGD_W1 - AES Region Descriptor Word1 */
68238 /*! @{ */
68239 
68240 #define OTFAD_RGD_W1_VLD_MASK                    (0x1U)
68241 #define OTFAD_RGD_W1_VLD_SHIFT                   (0U)
68242 /*! VLD - Valid
68243  *  0b0..Context is invalid.
68244  *  0b1..Context is valid.
68245  */
68246 #define OTFAD_RGD_W1_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
68247 
68248 #define OTFAD_RGD_W1_ADE_MASK                    (0x2U)
68249 #define OTFAD_RGD_W1_ADE_SHIFT                   (1U)
68250 /*! ADE - AES Decryption Enable.
68251  *  0b0..Bypass the fetched data.
68252  *  0b1..Perform the CTR-AES128 mode decryption on the fetched data.
68253  */
68254 #define OTFAD_RGD_W1_ADE(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
68255 
68256 #define OTFAD_RGD_W1_RO_MASK                     (0x4U)
68257 #define OTFAD_RGD_W1_RO_SHIFT                    (2U)
68258 /*! RO - Read-Only
68259  *  0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
68260  *  0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
68261  */
68262 #define OTFAD_RGD_W1_RO(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
68263 
68264 #define OTFAD_RGD_W1_ENDADDR_MASK                (0xFFFFFC00U)
68265 #define OTFAD_RGD_W1_ENDADDR_SHIFT               (10U)
68266 /*! ENDADDR - End Address */
68267 #define OTFAD_RGD_W1_ENDADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
68268 /*! @} */
68269 
68270 /* The count of OTFAD_RGD_W1 */
68271 #define OTFAD_RGD_W1_COUNT                       (4U)
68272 
68273 
68274 /*!
68275  * @}
68276  */ /* end of group OTFAD_Register_Masks */
68277 
68278 
68279 /* OTFAD - Peripheral instance base addresses */
68280 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
68281   /** Peripheral OTFAD1 base address */
68282   #define OTFAD1_BASE                              (0x525E0000u)
68283   /** Peripheral OTFAD1 base address */
68284   #define OTFAD1_BASE_NS                           (0x425E0000u)
68285   /** Peripheral OTFAD1 base pointer */
68286   #define OTFAD1                                   ((OTFAD_Type *)OTFAD1_BASE)
68287   /** Peripheral OTFAD1 base pointer */
68288   #define OTFAD1_NS                                ((OTFAD_Type *)OTFAD1_BASE_NS)
68289   /** Peripheral OTFAD2 base address */
68290   #define OTFAD2_BASE                              (0x545E0000u)
68291   /** Peripheral OTFAD2 base address */
68292   #define OTFAD2_BASE_NS                           (0x445E0000u)
68293   /** Peripheral OTFAD2 base pointer */
68294   #define OTFAD2                                   ((OTFAD_Type *)OTFAD2_BASE)
68295   /** Peripheral OTFAD2 base pointer */
68296   #define OTFAD2_NS                                ((OTFAD_Type *)OTFAD2_BASE_NS)
68297   /** Array initializer of OTFAD peripheral base addresses */
68298   #define OTFAD_BASE_ADDRS                         { 0u, OTFAD1_BASE, OTFAD2_BASE }
68299   /** Array initializer of OTFAD peripheral base pointers */
68300   #define OTFAD_BASE_PTRS                          { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
68301   /** Array initializer of OTFAD peripheral base addresses */
68302   #define OTFAD_BASE_ADDRS_NS                      { 0u, OTFAD1_BASE_NS, OTFAD2_BASE_NS }
68303   /** Array initializer of OTFAD peripheral base pointers */
68304   #define OTFAD_BASE_PTRS_NS                       { (OTFAD_Type *)0u, OTFAD1_NS, OTFAD2_NS }
68305 #else
68306   /** Peripheral OTFAD1 base address */
68307   #define OTFAD1_BASE                              (0x425E0000u)
68308   /** Peripheral OTFAD1 base pointer */
68309   #define OTFAD1                                   ((OTFAD_Type *)OTFAD1_BASE)
68310   /** Peripheral OTFAD2 base address */
68311   #define OTFAD2_BASE                              (0x445E0000u)
68312   /** Peripheral OTFAD2 base pointer */
68313   #define OTFAD2                                   ((OTFAD_Type *)OTFAD2_BASE)
68314   /** Array initializer of OTFAD peripheral base addresses */
68315   #define OTFAD_BASE_ADDRS                         { 0u, OTFAD1_BASE, OTFAD2_BASE }
68316   /** Array initializer of OTFAD peripheral base pointers */
68317   #define OTFAD_BASE_PTRS                          { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
68318 #endif
68319 
68320 /*!
68321  * @}
68322  */ /* end of group OTFAD_Peripheral_Access_Layer */
68323 
68324 
68325 /* ----------------------------------------------------------------------------
68326    -- PDM Peripheral Access Layer
68327    ---------------------------------------------------------------------------- */
68328 
68329 /*!
68330  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
68331  * @{
68332  */
68333 
68334 /** PDM - Register Layout Typedef */
68335 typedef struct {
68336   __IO uint32_t CTRL_1;                            /**< MICFIL Control 1, offset: 0x0 */
68337   __IO uint32_t CTRL_2;                            /**< MICFIL Control 2, offset: 0x4 */
68338   __IO uint32_t STAT;                              /**< MICFIL Status, offset: 0x8 */
68339        uint8_t RESERVED_0[4];
68340   __IO uint32_t FIFO_CTRL;                         /**< MICFIL FIFO Control, offset: 0x10 */
68341   __IO uint32_t FIFO_STAT;                         /**< MICFIL FIFO Status, offset: 0x14 */
68342        uint8_t RESERVED_1[12];
68343   __I  uint32_t DATACH[8];                         /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */
68344        uint8_t RESERVED_2[32];
68345   __IO uint32_t DC_CTRL;                           /**< MICFIL DC Remover Control, offset: 0x64 */
68346        uint8_t RESERVED_3[12];
68347   __IO uint32_t RANGE_CTRL;                        /**< MICFIL Range Control, offset: 0x74 */
68348        uint8_t RESERVED_4[4];
68349   __IO uint32_t RANGE_STAT;                        /**< MICFIL Range Status, offset: 0x7C */
68350        uint8_t RESERVED_5[16];
68351   __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control, offset: 0x90 */
68352   __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control, offset: 0x94 */
68353   __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status, offset: 0x98 */
68354   __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
68355   __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
68356   __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
68357   __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
68358 } PDM_Type;
68359 
68360 /* ----------------------------------------------------------------------------
68361    -- PDM Register Masks
68362    ---------------------------------------------------------------------------- */
68363 
68364 /*!
68365  * @addtogroup PDM_Register_Masks PDM Register Masks
68366  * @{
68367  */
68368 
68369 /*! @name CTRL_1 - MICFIL Control 1 */
68370 /*! @{ */
68371 
68372 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
68373 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
68374 /*! CH0EN - Channel 0 Enable */
68375 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
68376 
68377 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
68378 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
68379 /*! CH1EN - Channel 1 Enable */
68380 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
68381 
68382 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
68383 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
68384 /*! CH2EN - Channel 2 Enable */
68385 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
68386 
68387 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
68388 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
68389 /*! CH3EN - Channel 3 Enable */
68390 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
68391 
68392 #define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
68393 #define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
68394 /*! CH4EN - Channel 4 Enable */
68395 #define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
68396 
68397 #define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
68398 #define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
68399 /*! CH5EN - Channel 5 Enable */
68400 #define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
68401 
68402 #define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
68403 #define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
68404 /*! CH6EN - Channel 6 Enable */
68405 #define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
68406 
68407 #define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
68408 #define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
68409 /*! CH7EN - Channel 7 Enable */
68410 #define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
68411 
68412 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
68413 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
68414 /*! ERREN - Error Interruption Enable
68415  *  0b0..Disables
68416  *  0b1..Enables
68417  */
68418 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
68419 
68420 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
68421 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
68422 /*! DISEL - DMA Interrupt Selection
68423  *  0b00..Disables DMA and interrupt requests
68424  *  0b01..Enables DMA requests
68425  *  0b10..Enables interrupt requests
68426  *  0b11..Reserved
68427  */
68428 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
68429 
68430 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
68431 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
68432 /*! DBGE - Module Enable in Debug
68433  *  0b0..Disables after completing the current frame
68434  *  0b1..Enables operation
68435  */
68436 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
68437 
68438 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
68439 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
68440 /*! SRES - Software Reset
68441  *  0b0..No action
68442  *  0b1..Software reset
68443  */
68444 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
68445 
68446 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
68447 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
68448 /*! DBG - Debug Mode
68449  *  0b0..Normal
68450  *  0b1..Debug
68451  */
68452 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
68453 
68454 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
68455 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
68456 /*! PDMIEN - MICFIL Enable
68457  *  0b0..Stops MICFIL operation
68458  *  0b1..Starts MICFIL operation
68459  */
68460 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
68461 
68462 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
68463 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
68464 /*! DOZEN - Doze Enable
68465  *  0b0..Disables
68466  *  0b1..Enables
68467  */
68468 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
68469 
68470 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
68471 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
68472 /*! MDIS - Module Disable
68473  *  0b0..Normal mode
68474  *  0b1..DLL mode
68475  */
68476 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
68477 /*! @} */
68478 
68479 /*! @name CTRL_2 - MICFIL Control 2 */
68480 /*! @{ */
68481 
68482 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
68483 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
68484 /*! CLKDIV - Clock Divider
68485  *  0b00000000..Internal clock divider value = 0
68486  *  0b00000001..Internal clock divider value = 1
68487  *  0b00000010-0b11111110.....
68488  *  0b11111111..Internal clock divider value = 255
68489  */
68490 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
68491 
68492 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
68493 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
68494 /*! CICOSR - CIC Decimation Rate
68495  *  0b0000..CIC oversampling rate = 0
68496  *  0b0001..CIC oversampling rate = 1
68497  *  0b0010-0b1110.....
68498  *  0b1111..CIC oversampling rate = 15
68499  */
68500 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
68501 
68502 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
68503 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
68504 /*! QSEL - Quality Mode
68505  *  0b001..High-Quality mode
68506  *  0b000..Medium-Quality mode
68507  *  0b111..Low-Quality mode
68508  *  0b110..Very-Low-Quality 0 mode
68509  *  0b101..Very-Low-Quality 1 mode
68510  *  0b100..Very-Low-Quality 2 mode
68511  */
68512 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
68513 /*! @} */
68514 
68515 /*! @name STAT - MICFIL Status */
68516 /*! @{ */
68517 
68518 #define PDM_STAT_CH0F_MASK                       (0x1U)
68519 #define PDM_STAT_CH0F_SHIFT                      (0U)
68520 /*! CH0F - Channel 0 Output Data Flag
68521  *  0b0..Not surpassed
68522  *  0b1..Surpassed
68523  */
68524 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
68525 
68526 #define PDM_STAT_CH1F_MASK                       (0x2U)
68527 #define PDM_STAT_CH1F_SHIFT                      (1U)
68528 /*! CH1F - Channel 1 Output Data Flag
68529  *  0b0..Not surpassed
68530  *  0b1..Surpassed
68531  */
68532 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
68533 
68534 #define PDM_STAT_CH2F_MASK                       (0x4U)
68535 #define PDM_STAT_CH2F_SHIFT                      (2U)
68536 /*! CH2F - Channel 2 Output Data Flag
68537  *  0b0..Not surpassed
68538  *  0b1..Surpassed
68539  */
68540 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
68541 
68542 #define PDM_STAT_CH3F_MASK                       (0x8U)
68543 #define PDM_STAT_CH3F_SHIFT                      (3U)
68544 /*! CH3F - Channel 3 Output Data Flag
68545  *  0b0..Not surpassed
68546  *  0b1..Surpassed
68547  */
68548 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
68549 
68550 #define PDM_STAT_CH4F_MASK                       (0x10U)
68551 #define PDM_STAT_CH4F_SHIFT                      (4U)
68552 /*! CH4F - Channel 4 Output Data Flag
68553  *  0b0..Not surpassed
68554  *  0b1..Surpassed
68555  */
68556 #define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
68557 
68558 #define PDM_STAT_CH5F_MASK                       (0x20U)
68559 #define PDM_STAT_CH5F_SHIFT                      (5U)
68560 /*! CH5F - Channel 5 Output Data Flag
68561  *  0b0..Not surpassed
68562  *  0b1..Surpassed
68563  */
68564 #define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
68565 
68566 #define PDM_STAT_CH6F_MASK                       (0x40U)
68567 #define PDM_STAT_CH6F_SHIFT                      (6U)
68568 /*! CH6F - Channel 6 Output Data Flag
68569  *  0b0..Not surpassed
68570  *  0b1..Surpassed
68571  */
68572 #define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
68573 
68574 #define PDM_STAT_CH7F_MASK                       (0x80U)
68575 #define PDM_STAT_CH7F_SHIFT                      (7U)
68576 /*! CH7F - Channel 7 Output Data Flag
68577  *  0b0..Not surpassed
68578  *  0b1..Surpassed
68579  */
68580 #define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
68581 
68582 #define PDM_STAT_LOWFREQF_MASK                   (0x20000000U)
68583 #define PDM_STAT_LOWFREQF_SHIFT                  (29U)
68584 /*! LOWFREQF - Low Frequency Flag
68585  *  0b0..CLKDIV value is OK
68586  *  0b1..CLKDIV value is too low
68587  */
68588 #define PDM_STAT_LOWFREQF(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
68589 
68590 #define PDM_STAT_FIR_RDY_MASK                    (0x40000000U)
68591 #define PDM_STAT_FIR_RDY_SHIFT                   (30U)
68592 /*! FIR_RDY - Filter Data Ready
68593  *  0b0..Not reliable
68594  *  0b1..Reliable
68595  */
68596 #define PDM_STAT_FIR_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
68597 
68598 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
68599 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
68600 /*! BSY_FIL - Busy Flag
68601  *  0b1..MICFIL is running
68602  *  0b0..MICFIL is stopped
68603  */
68604 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
68605 /*! @} */
68606 
68607 /*! @name FIFO_CTRL - MICFIL FIFO Control */
68608 /*! @{ */
68609 
68610 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
68611 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
68612 /*! FIFOWMK - FIFO Watermark Control */
68613 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
68614 /*! @} */
68615 
68616 /*! @name FIFO_STAT - MICFIL FIFO Status */
68617 /*! @{ */
68618 
68619 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
68620 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
68621 /*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0
68622  *  0b0..No exception by FIFO overflow
68623  *  0b1..Exception by FIFO overflow
68624  */
68625 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
68626 
68627 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
68628 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
68629 /*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1
68630  *  0b0..No exception by FIFO overflow
68631  *  0b1..Exception by FIFO overflow
68632  */
68633 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
68634 
68635 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
68636 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
68637 /*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2
68638  *  0b0..No exception by FIFO overflow
68639  *  0b1..Exception by FIFO overflow
68640  */
68641 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
68642 
68643 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
68644 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
68645 /*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3
68646  *  0b0..No exception by FIFO overflow
68647  *  0b1..Exception by FIFO overflow
68648  */
68649 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
68650 
68651 #define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
68652 #define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
68653 /*! FIFOOVF4 - FIFO Overflow Exception Flag for Channel 4
68654  *  0b0..No exception by FIFO overflow
68655  *  0b1..Exception by FIFO overflow
68656  */
68657 #define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
68658 
68659 #define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
68660 #define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
68661 /*! FIFOOVF5 - FIFO Overflow Exception Flag for Channel 5
68662  *  0b0..No exception by FIFO overflow
68663  *  0b1..Exception by FIFO overflow
68664  */
68665 #define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
68666 
68667 #define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
68668 #define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
68669 /*! FIFOOVF6 - FIFO Overflow Exception Flag for Channel 6
68670  *  0b0..No exception by FIFO overflow
68671  *  0b1..Exception by FIFO overflow
68672  */
68673 #define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
68674 
68675 #define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
68676 #define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
68677 /*! FIFOOVF7 - FIFO Overflow Exception Flag for Channel 7
68678  *  0b0..No exception by FIFO overflow
68679  *  0b1..Exception by FIFO overflow
68680  */
68681 #define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
68682 
68683 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
68684 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
68685 /*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0
68686  *  0b0..No exception by FIFO underflow
68687  *  0b1..Exception by FIFO underflow
68688  */
68689 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
68690 
68691 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
68692 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
68693 /*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1
68694  *  0b0..No exception by FIFO underflow
68695  *  0b1..Exception by FIFO underflow
68696  */
68697 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
68698 
68699 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
68700 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
68701 /*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2
68702  *  0b0..No exception by FIFO underflow
68703  *  0b1..Exception by FIFO underflow
68704  */
68705 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
68706 
68707 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
68708 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
68709 /*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3
68710  *  0b0..No exception by FIFO underflow
68711  *  0b1..Exception by FIFO underflow
68712  */
68713 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
68714 
68715 #define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
68716 #define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
68717 /*! FIFOUND4 - FIFO Underflow Exception Flag for Channel 4
68718  *  0b0..No exception by FIFO underflow
68719  *  0b1..Exception by FIFO underflow
68720  */
68721 #define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
68722 
68723 #define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
68724 #define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
68725 /*! FIFOUND5 - FIFO Underflow Exception Flag for Channel 5
68726  *  0b0..No exception by FIFO underflow
68727  *  0b1..Exception by FIFO underflow
68728  */
68729 #define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
68730 
68731 #define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
68732 #define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
68733 /*! FIFOUND6 - FIFO Underflow Exception Flag for Channel 6
68734  *  0b0..No exception by FIFO underflow
68735  *  0b1..Exception by FIFO underflow
68736  */
68737 #define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
68738 
68739 #define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
68740 #define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
68741 /*! FIFOUND7 - FIFO Underflow Exception Flag for Channel 7
68742  *  0b0..No exception by FIFO underflow
68743  *  0b1..Exception by FIFO underflow
68744  */
68745 #define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
68746 /*! @} */
68747 
68748 /*! @name DATACH - MICFIL Output Result */
68749 /*! @{ */
68750 
68751 #define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
68752 #define PDM_DATACH_DATA_SHIFT                    (0U)
68753 /*! DATA - Channel n Data */
68754 #define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
68755 /*! @} */
68756 
68757 /* The count of PDM_DATACH */
68758 #define PDM_DATACH_COUNT                         (8U)
68759 
68760 /*! @name DC_CTRL - MICFIL DC Remover Control */
68761 /*! @{ */
68762 
68763 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
68764 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
68765 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
68766  *  0b11..DC remover is bypassed
68767  *  0b00..21 Hz
68768  *  0b01..83 Hz
68769  *  0b10..152 Hz
68770  */
68771 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
68772 
68773 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
68774 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
68775 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
68776  *  0b11..DC remover is bypassed
68777  *  0b00..21 Hz
68778  *  0b01..83 Hz
68779  *  0b10..152 Hz
68780  */
68781 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
68782 
68783 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
68784 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
68785 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
68786  *  0b11..DC remover is bypassed
68787  *  0b00..21 Hz
68788  *  0b01..83 Hz
68789  *  0b10..152 Hz
68790  */
68791 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
68792 
68793 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
68794 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
68795 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
68796  *  0b11..DC remover is bypassed
68797  *  0b00..21 Hz
68798  *  0b01..83 Hz
68799  *  0b10..152 Hz
68800  */
68801 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
68802 
68803 #define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
68804 #define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
68805 /*! DCCONFIG4 - Channel 4 DC Remover Configuration
68806  *  0b11..DC remover is bypassed
68807  *  0b00..21 Hz
68808  *  0b01..83 Hz
68809  *  0b10..152 Hz
68810  */
68811 #define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
68812 
68813 #define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
68814 #define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
68815 /*! DCCONFIG5 - Channel 5 DC Remover Configuration
68816  *  0b11..DC remover is bypassed
68817  *  0b00..21 Hz
68818  *  0b01..83 Hz
68819  *  0b10..152 Hz
68820  */
68821 #define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
68822 
68823 #define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
68824 #define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
68825 /*! DCCONFIG6 - Channel 6 DC Remover Configuration
68826  *  0b11..DC remover is bypassed
68827  *  0b00..21 Hz
68828  *  0b01..83 Hz
68829  *  0b10..152 Hz
68830  */
68831 #define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
68832 
68833 #define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
68834 #define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
68835 /*! DCCONFIG7 - Channel 7 DC Remover Configuration
68836  *  0b11..DC remover is bypassed
68837  *  0b00..21 Hz
68838  *  0b01..83 Hz
68839  *  0b10..152 Hz
68840  */
68841 #define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
68842 /*! @} */
68843 
68844 /*! @name RANGE_CTRL - MICFIL Range Control */
68845 /*! @{ */
68846 
68847 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
68848 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
68849 /*! RANGEADJ0 - Channel 0 Range Adjustment */
68850 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
68851 
68852 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
68853 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
68854 /*! RANGEADJ1 - Channel 1 Range Adjustment */
68855 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
68856 
68857 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
68858 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
68859 /*! RANGEADJ2 - Channel 2 Range Adjustment */
68860 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
68861 
68862 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
68863 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
68864 /*! RANGEADJ3 - Channel 3 Range Adjustment */
68865 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
68866 
68867 #define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
68868 #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
68869 /*! RANGEADJ4 - Channel 4 Range Adjustment */
68870 #define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
68871 
68872 #define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
68873 #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
68874 /*! RANGEADJ5 - Channel 5 Range Adjustment */
68875 #define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
68876 
68877 #define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
68878 #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
68879 /*! RANGEADJ6 - Channel 6 Range Adjustment */
68880 #define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
68881 
68882 #define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
68883 #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
68884 /*! RANGEADJ7 - Channel 7 Range Adjustment */
68885 #define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
68886 /*! @} */
68887 
68888 /*! @name RANGE_STAT - MICFIL Range Status */
68889 /*! @{ */
68890 
68891 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
68892 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
68893 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
68894  *  0b0..No exception by range overflow
68895  *  0b1..Exception by range overflow
68896  */
68897 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
68898 
68899 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
68900 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
68901 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
68902  *  0b0..No exception by range overflow
68903  *  0b1..Exception by range overflow
68904  */
68905 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
68906 
68907 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
68908 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
68909 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
68910  *  0b0..No exception by range overflow
68911  *  0b1..Exception by range overflow
68912  */
68913 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
68914 
68915 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
68916 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
68917 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
68918  *  0b0..No exception by range overflow
68919  *  0b1..Exception by range overflow
68920  */
68921 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
68922 
68923 #define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
68924 #define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
68925 /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
68926  *  0b0..No exception by range overflow
68927  *  0b1..Exception by range overflow
68928  */
68929 #define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
68930 
68931 #define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
68932 #define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
68933 /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
68934  *  0b0..No exception by range overflow
68935  *  0b1..Exception by range overflow
68936  */
68937 #define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
68938 
68939 #define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
68940 #define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
68941 /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
68942  *  0b0..No exception by range overflow
68943  *  0b1..Exception by range overflow
68944  */
68945 #define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
68946 
68947 #define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
68948 #define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
68949 /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
68950  *  0b0..No exception by range overflow
68951  *  0b1..Exception by range overflow
68952  */
68953 #define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
68954 
68955 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
68956 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
68957 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
68958  *  0b0..No exception by range underflow
68959  *  0b1..Exception by range underflow
68960  */
68961 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
68962 
68963 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
68964 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
68965 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
68966  *  0b0..No exception by range underflow
68967  *  0b1..Exception by range underflow
68968  */
68969 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
68970 
68971 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
68972 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
68973 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
68974  *  0b0..No exception by range underflow
68975  *  0b1..Exception by range underflow
68976  */
68977 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
68978 
68979 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
68980 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
68981 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
68982  *  0b0..No exception by range underflow
68983  *  0b1..Exception by range underflow
68984  */
68985 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
68986 
68987 #define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
68988 #define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
68989 /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
68990  *  0b0..No exception by range underflow
68991  *  0b1..Exception by range underflow
68992  */
68993 #define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
68994 
68995 #define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
68996 #define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
68997 /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
68998  *  0b0..No exception by range underflow
68999  *  0b1..Exception by range underflow
69000  */
69001 #define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
69002 
69003 #define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
69004 #define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
69005 /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
69006  *  0b0..No exception by range underflow
69007  *  0b1..Exception by range underflow
69008  */
69009 #define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
69010 
69011 #define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
69012 #define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
69013 /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
69014  *  0b0..No exception by range underflow
69015  *  0b1..Exception by range underflow
69016  */
69017 #define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
69018 /*! @} */
69019 
69020 /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control */
69021 /*! @{ */
69022 
69023 #define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
69024 #define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
69025 /*! VADEN - Voice Activity Detector Enable
69026  *  0b0..Disables
69027  *  0b1..Enables
69028  */
69029 #define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
69030 
69031 #define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
69032 #define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
69033 /*! VADRST - Voice Activity Detector Reset */
69034 #define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
69035 
69036 #define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
69037 #define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
69038 /*! VADIE - Voice Activity Detector Interruption Enable
69039  *  0b0..Disables
69040  *  0b1..Enables
69041  */
69042 #define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
69043 
69044 #define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
69045 #define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
69046 /*! VADERIE - Voice Activity Detector Error Interruption Enable
69047  *  0b0..Disables
69048  *  0b1..Enables
69049  */
69050 #define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
69051 
69052 #define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
69053 #define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
69054 /*! VADST10 - Voice Activity Detector Internal Filters Initialization
69055  *  0b0..Normal operation
69056  *  0b1..Filters initialized
69057  */
69058 #define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
69059 
69060 #define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
69061 #define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
69062 /*! VADINITT - Voice Activity Detector Initialization Time
69063  *  0b00000..VADINITT = 0
69064  *  0b00001..VADINITT = 1
69065  *  0b00010-0b11110.....
69066  *  0b11111..VADINITT = 31
69067  */
69068 #define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
69069 
69070 #define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
69071 #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
69072 /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate */
69073 #define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
69074 
69075 #define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
69076 #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
69077 /*! VADCHSEL - Voice Activity Detector Channel Selector
69078  *  0b000..PDM Microphone 0 Left
69079  *  0b001..PDM Microphone 0 Right
69080  *  0b010..PDM Microphone 1 Left
69081  *  0b011-0b101.....
69082  *  0b110..PDM Microphone 3 Left
69083  *  0b111..PDM Microphone 3 Right
69084  */
69085 #define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
69086 /*! @} */
69087 
69088 /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control */
69089 /*! @{ */
69090 
69091 #define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
69092 #define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
69093 /*! VADHPF - Voice Activity Detector High-Pass Filter
69094  *  0b00..Filter bypassed
69095  *  0b01..Cut-off frequency at 1750 Hz
69096  *  0b10..Cut-off frequency at 215 Hz
69097  *  0b11..Cut-off frequency at 102 Hz
69098  */
69099 #define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
69100 
69101 #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
69102 #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
69103 /*! VADINPGAIN - Voice Activity Detector Input Gain
69104  *  0b0000..No shift
69105  *  0b0001..Shift 1 bit to the left
69106  *  0b0010..Shift 2 bits to the left
69107  *  0b0011-0b0110.....
69108  *  0b0111..Shift 7 bits to the left
69109  *  0b1000..Shift 8 bits to the right
69110  *  0b1001..Shift 7 bits to the right
69111  *  0b1010-0b1110.....
69112  *  0b1111..Shift 1 bits to the right
69113  */
69114 #define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
69115 
69116 #define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
69117 #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
69118 /*! VADFRAMET - Voice Activity Detector Frame Time
69119  *  0b000000..VADFRAMET = 1
69120  *  0b000001..VADFRAMET = 2
69121  *  0b000010-0b111110.....
69122  *  0b111111..VADFRAMET = 63
69123  */
69124 #define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
69125 
69126 #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
69127 #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
69128 /*! VADFOUTDIS - Voice Activity Detector Force Output Disable
69129  *  0b0..Enables
69130  *  0b1..Disables
69131  */
69132 #define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
69133 
69134 #define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
69135 #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
69136 /*! VADPREFEN - Voice Activity Detector Pre Filter Enable
69137  *  0b0..Pre-filter bypassed
69138  *  0b1..Pre-filter enabled
69139  */
69140 #define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
69141 
69142 #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
69143 #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
69144 /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
69145  *  0b1..Disables
69146  *  0b0..Enables
69147  */
69148 #define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
69149 /*! @} */
69150 
69151 /*! @name VAD0_STAT - Voice Activity Detector 0 Status */
69152 /*! @{ */
69153 
69154 #define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
69155 #define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
69156 /*! VADIF - Voice Activity Detector Interrupt Flag
69157  *  0b0..Not detected
69158  *  0b1..Detected
69159  */
69160 #define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
69161 
69162 #define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
69163 #define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
69164 /*! VADINSATF - Voice Activity Detector Input Saturation Flag
69165  *  0b0..No exception
69166  *  0b1..Exception
69167  */
69168 #define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
69169 
69170 #define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
69171 #define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
69172 /*! VADINITF - Voice Activity Detector Initialization Flag
69173  *  0b0..Not being initialized
69174  *  0b1..Being initialized
69175  */
69176 #define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
69177 /*! @} */
69178 
69179 /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
69180 /*! @{ */
69181 
69182 #define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
69183 #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
69184 /*! VADSGAIN - Voice Activity Detector Signal Gain
69185  *  0b0000, 0b0001..Multiplier = 1
69186  *  0b0010..Multiplier = 2
69187  *  0b0011-0b1110.....
69188  *  0b1111..Multiplier = 15
69189  */
69190 #define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
69191 
69192 #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
69193 #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
69194 /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
69195  *  0b0..Maximum block bypassed
69196  *  0b1..Maximum block enabled
69197  */
69198 #define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
69199 
69200 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
69201 #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
69202 /*! VADSFILEN - Voice Activity Detector Signal Filter Enable
69203  *  0b0..Disables
69204  *  0b1..Enables
69205  */
69206 #define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
69207 /*! @} */
69208 
69209 /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
69210 /*! @{ */
69211 
69212 #define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
69213 #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
69214 /*! VADNGAIN - Voice Activity Detector Noise Gain
69215  *  0b0000, 0b0001..Multiplier = 1
69216  *  0b0010..Multiplier = 2
69217  *  0b0011-0b1110.....
69218  *  0b1111..Multiplier = 15
69219  */
69220 #define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
69221 
69222 #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
69223 #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
69224 /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment
69225  *  0b00000..Adjustment value = 0
69226  *  0b00001..Adjustment value = 1
69227  *  0b00010-0b11110.....
69228  *  0b11111..Adjustment value = 31
69229  */
69230 #define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
69231 
69232 #define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
69233 #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
69234 /*! VADNOREN - Voice Activity Detector Noise OR Enable
69235  *  0b0..Not decimated
69236  *  0b1..Decimated
69237  */
69238 #define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
69239 
69240 #define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
69241 #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
69242 /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
69243  *  0b0..Not decimated
69244  *  0b1..Decimated
69245  */
69246 #define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
69247 
69248 #define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
69249 #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
69250 /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
69251  *  0b0..Minimum block bypassed
69252  *  0b1..Minimum block enabled
69253  */
69254 #define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
69255 
69256 #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
69257 #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
69258 /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
69259  *  0b0..Noise filter always enabled
69260  *  0b1..Noise filter enabled/disabled based on voice activity information
69261  */
69262 #define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
69263 /*! @} */
69264 
69265 /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
69266 /*! @{ */
69267 
69268 #define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
69269 #define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
69270 /*! VADNDATA - Voice Activity Detector Noise Data */
69271 #define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
69272 /*! @} */
69273 
69274 /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
69275 /*! @{ */
69276 
69277 #define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
69278 #define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
69279 /*! VADZCDEN - Zero-Crossing Detector Enable
69280  *  0b0..Disables
69281  *  0b1..Enables
69282  */
69283 #define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
69284 
69285 #define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
69286 #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
69287 /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
69288  *  0b0..Disables
69289  *  0b1..Enables
69290  */
69291 #define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
69292 
69293 #define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
69294 #define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
69295 /*! VADZCDAND - Zero-Crossing Detector AND Behavior
69296  *  0b0..OR
69297  *  0b1..AND
69298  */
69299 #define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
69300 
69301 #define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
69302 #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
69303 /*! VADZCDADJ - Zero-Crossing Detector Adjustment
69304  *  0b0000..Adjustment value = 0
69305  *  0b0001..Adjustment value = 1
69306  *  0b0010-0b1110.....
69307  *  0b1111..Adjustment value = 15
69308  */
69309 #define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
69310 
69311 #define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
69312 #define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
69313 /*! VADZCDTH - Zero-Crossing Detector Threshold */
69314 #define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
69315 /*! @} */
69316 
69317 
69318 /*!
69319  * @}
69320  */ /* end of group PDM_Register_Masks */
69321 
69322 
69323 /* PDM - Peripheral instance base addresses */
69324 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
69325   /** Peripheral PDM base address */
69326   #define PDM_BASE                                 (0x52BE0000u)
69327   /** Peripheral PDM base address */
69328   #define PDM_BASE_NS                              (0x42BE0000u)
69329   /** Peripheral PDM base pointer */
69330   #define PDM                                      ((PDM_Type *)PDM_BASE)
69331   /** Peripheral PDM base pointer */
69332   #define PDM_NS                                   ((PDM_Type *)PDM_BASE_NS)
69333   /** Array initializer of PDM peripheral base addresses */
69334   #define PDM_BASE_ADDRS                           { PDM_BASE }
69335   /** Array initializer of PDM peripheral base pointers */
69336   #define PDM_BASE_PTRS                            { PDM }
69337   /** Array initializer of PDM peripheral base addresses */
69338   #define PDM_BASE_ADDRS_NS                        { PDM_BASE_NS }
69339   /** Array initializer of PDM peripheral base pointers */
69340   #define PDM_BASE_PTRS_NS                         { PDM_NS }
69341 #else
69342   /** Peripheral PDM base address */
69343   #define PDM_BASE                                 (0x42BE0000u)
69344   /** Peripheral PDM base pointer */
69345   #define PDM                                      ((PDM_Type *)PDM_BASE)
69346   /** Array initializer of PDM peripheral base addresses */
69347   #define PDM_BASE_ADDRS                           { PDM_BASE }
69348   /** Array initializer of PDM peripheral base pointers */
69349   #define PDM_BASE_PTRS                            { PDM }
69350 #endif
69351 /** Interrupt vectors for the PDM peripheral type */
69352 #define PDM_HWVAD_Event_IRQS                     { PDM_HWVAD_EVENT_IRQn }
69353 #define PDM_HWVAD_Error_IRQS                     { PDM_HWVAD_ERROR_IRQn }
69354 #define PDM_Event_IRQS                           { PDM_EVENT_IRQn }
69355 #define PDM_Error_IRQS                           { PDM_ERROR_IRQn }
69356 
69357 /*!
69358  * @}
69359  */ /* end of group PDM_Peripheral_Access_Layer */
69360 
69361 
69362 /* ----------------------------------------------------------------------------
69363    -- PHY_LDO Peripheral Access Layer
69364    ---------------------------------------------------------------------------- */
69365 
69366 /*!
69367  * @addtogroup PHY_LDO_Peripheral_Access_Layer PHY_LDO Peripheral Access Layer
69368  * @{
69369  */
69370 
69371 /** PHY_LDO - Register Layout Typedef */
69372 typedef struct {
69373   struct {                                         /* offset: 0x0 */
69374     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
69375     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
69376     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
69377     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
69378   } CTRL0;
69379        uint8_t RESERVED_0[64];
69380   struct {                                         /* offset: 0x50 */
69381     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
69382     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
69383     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
69384     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
69385   } STAT0;
69386 } PHY_LDO_Type;
69387 
69388 /* ----------------------------------------------------------------------------
69389    -- PHY_LDO Register Masks
69390    ---------------------------------------------------------------------------- */
69391 
69392 /*!
69393  * @addtogroup PHY_LDO_Register_Masks PHY_LDO Register Masks
69394  * @{
69395  */
69396 
69397 /*! @name CTRL0 - Analog Control Register CTRL0 */
69398 /*! @{ */
69399 
69400 #define PHY_LDO_CTRL0_LINREG_EN_MASK             (0x1U)
69401 #define PHY_LDO_CTRL0_LINREG_EN_SHIFT            (0U)
69402 /*! LINREG_EN - LinrReg master enable */
69403 #define PHY_LDO_CTRL0_LINREG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
69404 
69405 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK  (0x2U)
69406 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
69407 /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
69408  *  0b0..Internal pull-down enabled
69409  *  0b1..Internal pull-down disabled
69410  */
69411 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x)    (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
69412 
69413 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK      (0x4U)
69414 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT     (2U)
69415 /*! LINREG_ILIMIT_EN - LinReg current-limit enable */
69416 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
69417 
69418 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK     (0x1F0U)
69419 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT    (4U)
69420 /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting */
69421 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
69422 
69423 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK      (0x8000U)
69424 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT     (15U)
69425 /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load */
69426 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
69427 /*! @} */
69428 
69429 /*! @name STAT0 - Analog Status Register STAT0 */
69430 /*! @{ */
69431 
69432 #define PHY_LDO_STAT0_LINREG_STAT_MASK           (0xFU)
69433 #define PHY_LDO_STAT0_LINREG_STAT_SHIFT          (0U)
69434 /*! LINREG_STAT - LinReg Status Bits */
69435 #define PHY_LDO_STAT0_LINREG_STAT(x)             (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK)
69436 /*! @} */
69437 
69438 
69439 /*!
69440  * @}
69441  */ /* end of group PHY_LDO_Register_Masks */
69442 
69443 
69444 /* PHY_LDO - Peripheral instance base addresses */
69445 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
69446   /** Peripheral PHY_LDO base address */
69447   #define PHY_LDO_BASE                             (0x54484680u)
69448   /** Peripheral PHY_LDO base address */
69449   #define PHY_LDO_BASE_NS                          (0x44484680u)
69450   /** Peripheral PHY_LDO base pointer */
69451   #define PHY_LDO                                  ((PHY_LDO_Type *)PHY_LDO_BASE)
69452   /** Peripheral PHY_LDO base pointer */
69453   #define PHY_LDO_NS                               ((PHY_LDO_Type *)PHY_LDO_BASE_NS)
69454   /** Array initializer of PHY_LDO peripheral base addresses */
69455   #define PHY_LDO_BASE_ADDRS                       { PHY_LDO_BASE }
69456   /** Array initializer of PHY_LDO peripheral base pointers */
69457   #define PHY_LDO_BASE_PTRS                        { PHY_LDO }
69458   /** Array initializer of PHY_LDO peripheral base addresses */
69459   #define PHY_LDO_BASE_ADDRS_NS                    { PHY_LDO_BASE_NS }
69460   /** Array initializer of PHY_LDO peripheral base pointers */
69461   #define PHY_LDO_BASE_PTRS_NS                     { PHY_LDO_NS }
69462 #else
69463   /** Peripheral PHY_LDO base address */
69464   #define PHY_LDO_BASE                             (0x44484680u)
69465   /** Peripheral PHY_LDO base pointer */
69466   #define PHY_LDO                                  ((PHY_LDO_Type *)PHY_LDO_BASE)
69467   /** Array initializer of PHY_LDO peripheral base addresses */
69468   #define PHY_LDO_BASE_ADDRS                       { PHY_LDO_BASE }
69469   /** Array initializer of PHY_LDO peripheral base pointers */
69470   #define PHY_LDO_BASE_PTRS                        { PHY_LDO }
69471 #endif
69472 
69473 /*!
69474  * @}
69475  */ /* end of group PHY_LDO_Peripheral_Access_Layer */
69476 
69477 
69478 /* ----------------------------------------------------------------------------
69479    -- PLL Peripheral Access Layer
69480    ---------------------------------------------------------------------------- */
69481 
69482 /*!
69483  * @addtogroup PLL_Peripheral_Access_Layer PLL Peripheral Access Layer
69484  * @{
69485  */
69486 
69487 /** PLL - Register Layout Typedef */
69488 typedef struct {
69489   struct {                                         /* offset: 0x0 */
69490     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
69491     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
69492     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
69493     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
69494   } CTRL0;
69495   struct {                                         /* offset: 0x10 */
69496     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
69497     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
69498     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
69499     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
69500   } SPREAD_SPECTRUM;
69501   struct {                                         /* offset: 0x20 */
69502     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
69503     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
69504     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
69505     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
69506   } NUMERATOR;
69507   struct {                                         /* offset: 0x30 */
69508     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
69509     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
69510     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
69511     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
69512   } DENOMINATOR;
69513 } PLL_Type;
69514 
69515 /* ----------------------------------------------------------------------------
69516    -- PLL Register Masks
69517    ---------------------------------------------------------------------------- */
69518 
69519 /*!
69520  * @addtogroup PLL_Register_Masks PLL Register Masks
69521  * @{
69522  */
69523 
69524 /*! @name CTRL0 - Fractional PLL Control Register */
69525 /*! @{ */
69526 
69527 #define PLL_CTRL0_DIV_SELECT_MASK                (0x7FU)
69528 #define PLL_CTRL0_DIV_SELECT_SHIFT               (0U)
69529 /*! DIV_SELECT - DIV_SELECT */
69530 #define PLL_CTRL0_DIV_SELECT(x)                  (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_DIV_SELECT_SHIFT)) & PLL_CTRL0_DIV_SELECT_MASK)
69531 
69532 #define PLL_CTRL0_ENABLE_ALT_MASK                (0x100U)
69533 #define PLL_CTRL0_ENABLE_ALT_SHIFT               (8U)
69534 /*! ENABLE_ALT - ENABLE_ALT
69535  *  0b0..Disable the alternate clock output
69536  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
69537  */
69538 #define PLL_CTRL0_ENABLE_ALT(x)                  (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_ENABLE_ALT_SHIFT)) & PLL_CTRL0_ENABLE_ALT_MASK)
69539 
69540 #define PLL_CTRL0_HOLD_RING_OFF_MASK             (0x2000U)
69541 #define PLL_CTRL0_HOLD_RING_OFF_SHIFT            (13U)
69542 /*! HOLD_RING_OFF - PLL Start up initialization
69543  *  0b0..Normal operation
69544  *  0b1..Initialize PLL start up
69545  */
69546 #define PLL_CTRL0_HOLD_RING_OFF(x)               (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & PLL_CTRL0_HOLD_RING_OFF_MASK)
69547 
69548 #define PLL_CTRL0_POWERUP_MASK                   (0x4000U)
69549 #define PLL_CTRL0_POWERUP_SHIFT                  (14U)
69550 /*! POWERUP - POWERUP
69551  *  0b1..Power Up the PLL
69552  *  0b0..Power down the PLL
69553  */
69554 #define PLL_CTRL0_POWERUP(x)                     (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_POWERUP_SHIFT)) & PLL_CTRL0_POWERUP_MASK)
69555 
69556 #define PLL_CTRL0_ENABLE_MASK                    (0x8000U)
69557 #define PLL_CTRL0_ENABLE_SHIFT                   (15U)
69558 /*! ENABLE - ENABLE
69559  *  0b1..Enable the clock output
69560  *  0b0..Disable the clock output
69561  */
69562 #define PLL_CTRL0_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_ENABLE_SHIFT)) & PLL_CTRL0_ENABLE_MASK)
69563 
69564 #define PLL_CTRL0_BYPASS_MASK                    (0x10000U)
69565 #define PLL_CTRL0_BYPASS_SHIFT                   (16U)
69566 /*! BYPASS - BYPASS
69567  *  0b1..Bypass the PLL
69568  *  0b0..No Bypass
69569  */
69570 #define PLL_CTRL0_BYPASS(x)                      (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_BYPASS_SHIFT)) & PLL_CTRL0_BYPASS_MASK)
69571 
69572 #define PLL_CTRL0_DITHER_EN_MASK                 (0x20000U)
69573 #define PLL_CTRL0_DITHER_EN_SHIFT                (17U)
69574 /*! DITHER_EN - DITHER_EN
69575  *  0b0..Disable Dither
69576  *  0b1..Enable Dither
69577  */
69578 #define PLL_CTRL0_DITHER_EN(x)                   (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_DITHER_EN_SHIFT)) & PLL_CTRL0_DITHER_EN_MASK)
69579 
69580 #define PLL_CTRL0_PLL_REG_EN_MASK                (0x400000U)
69581 #define PLL_CTRL0_PLL_REG_EN_SHIFT               (22U)
69582 /*! PLL_REG_EN - PLL_REG_EN
69583  *  0b0..Disable
69584  *  0b1..Enable
69585  */
69586 #define PLL_CTRL0_PLL_REG_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_PLL_REG_EN_SHIFT)) & PLL_CTRL0_PLL_REG_EN_MASK)
69587 
69588 #define PLL_CTRL0_POST_DIV_SEL_MASK              (0xE000000U)
69589 #define PLL_CTRL0_POST_DIV_SEL_SHIFT             (25U)
69590 /*! POST_DIV_SEL - Post Divide Select
69591  *  0b000..Divide by 1
69592  *  0b001..Divide by 2
69593  *  0b010..Divide by 4
69594  *  0b011..Divide by 8
69595  *  0b100..Divide by 16
69596  *  0b101..Divide by 32
69597  */
69598 #define PLL_CTRL0_POST_DIV_SEL(x)                (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_POST_DIV_SEL_SHIFT)) & PLL_CTRL0_POST_DIV_SEL_MASK)
69599 
69600 #define PLL_CTRL0_BIAS_SELECT_MASK               (0x20000000U)
69601 #define PLL_CTRL0_BIAS_SELECT_SHIFT              (29U)
69602 /*! BIAS_SELECT - BIAS_SELECT
69603  *  0b0..Used in SoCs with a bias current of 10uA
69604  *  0b1..Used in SoCs with a bias current of 2uA
69605  */
69606 #define PLL_CTRL0_BIAS_SELECT(x)                 (((uint32_t)(((uint32_t)(x)) << PLL_CTRL0_BIAS_SELECT_SHIFT)) & PLL_CTRL0_BIAS_SELECT_MASK)
69607 /*! @} */
69608 
69609 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
69610 /*! @{ */
69611 
69612 #define PLL_SPREAD_SPECTRUM_STEP_MASK            (0x7FFFU)
69613 #define PLL_SPREAD_SPECTRUM_STEP_SHIFT           (0U)
69614 /*! STEP - Step */
69615 #define PLL_SPREAD_SPECTRUM_STEP(x)              (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & PLL_SPREAD_SPECTRUM_STEP_MASK)
69616 
69617 #define PLL_SPREAD_SPECTRUM_ENABLE_MASK          (0x8000U)
69618 #define PLL_SPREAD_SPECTRUM_ENABLE_SHIFT         (15U)
69619 /*! ENABLE - Enable
69620  *  0b0..Disable
69621  *  0b1..Enable
69622  */
69623 #define PLL_SPREAD_SPECTRUM_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & PLL_SPREAD_SPECTRUM_ENABLE_MASK)
69624 
69625 #define PLL_SPREAD_SPECTRUM_STOP_MASK            (0xFFFF0000U)
69626 #define PLL_SPREAD_SPECTRUM_STOP_SHIFT           (16U)
69627 /*! STOP - Stop */
69628 #define PLL_SPREAD_SPECTRUM_STOP(x)              (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & PLL_SPREAD_SPECTRUM_STOP_MASK)
69629 /*! @} */
69630 
69631 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
69632 /*! @{ */
69633 
69634 #define PLL_NUMERATOR_NUM_MASK                   (0x3FFFFFFFU)
69635 #define PLL_NUMERATOR_NUM_SHIFT                  (0U)
69636 /*! NUM - Numerator */
69637 #define PLL_NUMERATOR_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << PLL_NUMERATOR_NUM_SHIFT)) & PLL_NUMERATOR_NUM_MASK)
69638 /*! @} */
69639 
69640 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
69641 /*! @{ */
69642 
69643 #define PLL_DENOMINATOR_DENOM_MASK               (0x3FFFFFFFU)
69644 #define PLL_DENOMINATOR_DENOM_SHIFT              (0U)
69645 /*! DENOM - Denominator */
69646 #define PLL_DENOMINATOR_DENOM(x)                 (((uint32_t)(((uint32_t)(x)) << PLL_DENOMINATOR_DENOM_SHIFT)) & PLL_DENOMINATOR_DENOM_MASK)
69647 /*! @} */
69648 
69649 
69650 /*!
69651  * @}
69652  */ /* end of group PLL_Register_Masks */
69653 
69654 
69655 /* PLL - Peripheral instance base addresses */
69656 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
69657   /** Peripheral AUDIO_PLL base address */
69658   #define AUDIO_PLL_BASE                           (0x54484280u)
69659   /** Peripheral AUDIO_PLL base address */
69660   #define AUDIO_PLL_BASE_NS                        (0x44484280u)
69661   /** Peripheral AUDIO_PLL base pointer */
69662   #define AUDIO_PLL                                ((PLL_Type *)AUDIO_PLL_BASE)
69663   /** Peripheral AUDIO_PLL base pointer */
69664   #define AUDIO_PLL_NS                             ((PLL_Type *)AUDIO_PLL_BASE_NS)
69665   /** Peripheral ETHERNET_PLL base address */
69666   #define ETHERNET_PLL_BASE                        (0x54484180u)
69667   /** Peripheral ETHERNET_PLL base address */
69668   #define ETHERNET_PLL_BASE_NS                     (0x44484180u)
69669   /** Peripheral ETHERNET_PLL base pointer */
69670   #define ETHERNET_PLL                             ((PLL_Type *)ETHERNET_PLL_BASE)
69671   /** Peripheral ETHERNET_PLL base pointer */
69672   #define ETHERNET_PLL_NS                          ((PLL_Type *)ETHERNET_PLL_BASE_NS)
69673   /** Array initializer of PLL peripheral base addresses */
69674   #define PLL_BASE_ADDRS                           { AUDIO_PLL_BASE, ETHERNET_PLL_BASE }
69675   /** Array initializer of PLL peripheral base pointers */
69676   #define PLL_BASE_PTRS                            { AUDIO_PLL, ETHERNET_PLL }
69677   /** Array initializer of PLL peripheral base addresses */
69678   #define PLL_BASE_ADDRS_NS                        { AUDIO_PLL_BASE_NS, ETHERNET_PLL_BASE_NS }
69679   /** Array initializer of PLL peripheral base pointers */
69680   #define PLL_BASE_PTRS_NS                         { AUDIO_PLL_NS, ETHERNET_PLL_NS }
69681 #else
69682   /** Peripheral AUDIO_PLL base address */
69683   #define AUDIO_PLL_BASE                           (0x44484280u)
69684   /** Peripheral AUDIO_PLL base pointer */
69685   #define AUDIO_PLL                                ((PLL_Type *)AUDIO_PLL_BASE)
69686   /** Peripheral ETHERNET_PLL base address */
69687   #define ETHERNET_PLL_BASE                        (0x44484180u)
69688   /** Peripheral ETHERNET_PLL base pointer */
69689   #define ETHERNET_PLL                             ((PLL_Type *)ETHERNET_PLL_BASE)
69690   /** Array initializer of PLL peripheral base addresses */
69691   #define PLL_BASE_ADDRS                           { AUDIO_PLL_BASE, ETHERNET_PLL_BASE }
69692   /** Array initializer of PLL peripheral base pointers */
69693   #define PLL_BASE_PTRS                            { AUDIO_PLL, ETHERNET_PLL }
69694 #endif
69695 
69696 /*!
69697  * @}
69698  */ /* end of group PLL_Peripheral_Access_Layer */
69699 
69700 
69701 /* ----------------------------------------------------------------------------
69702    -- PWM Peripheral Access Layer
69703    ---------------------------------------------------------------------------- */
69704 
69705 /*!
69706  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
69707  * @{
69708  */
69709 
69710 /** PWM - Register Layout Typedef */
69711 typedef struct {
69712   struct {                                         /* offset: 0x0, array step: 0x60 */
69713     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
69714     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
69715     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
69716     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
69717          uint8_t RESERVED_0[2];
69718     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
69719     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
69720     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
69721     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
69722     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
69723     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
69724     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
69725     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
69726     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
69727     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
69728     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
69729     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
69730     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
69731     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
69732     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
69733     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
69734     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
69735     __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
69736          uint8_t RESERVED_1[2];
69737     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
69738     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
69739     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
69740     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
69741     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
69742     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
69743     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
69744     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
69745     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
69746     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
69747     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
69748     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
69749     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
69750     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
69751     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
69752     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
69753     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
69754     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
69755     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
69756     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
69757     __IO uint16_t PHASEDLY;                          /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */
69758     __IO uint16_t CAPTFILTA;                         /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */
69759     __IO uint16_t CAPTFILTB;                         /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */
69760     __IO uint16_t CAPTFILTX;                         /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */
69761   } SM[4];
69762   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
69763   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
69764   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
69765   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
69766   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
69767   __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
69768   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
69769   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
69770   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
69771   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
69772   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
69773 } PWM_Type;
69774 
69775 /* ----------------------------------------------------------------------------
69776    -- PWM Register Masks
69777    ---------------------------------------------------------------------------- */
69778 
69779 /*!
69780  * @addtogroup PWM_Register_Masks PWM Register Masks
69781  * @{
69782  */
69783 
69784 /*! @name CNT - Counter Register */
69785 /*! @{ */
69786 
69787 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
69788 #define PWM_CNT_CNT_SHIFT                        (0U)
69789 /*! CNT - Counter Register Bits */
69790 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
69791 /*! @} */
69792 
69793 /* The count of PWM_CNT */
69794 #define PWM_CNT_COUNT                            (4U)
69795 
69796 /*! @name INIT - Initial Count Register */
69797 /*! @{ */
69798 
69799 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
69800 #define PWM_INIT_INIT_SHIFT                      (0U)
69801 /*! INIT - Initial Count Register Bits */
69802 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
69803 /*! @} */
69804 
69805 /* The count of PWM_INIT */
69806 #define PWM_INIT_COUNT                           (4U)
69807 
69808 /*! @name CTRL2 - Control 2 Register */
69809 /*! @{ */
69810 
69811 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
69812 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
69813 /*! CLK_SEL - Clock Source Select
69814  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
69815  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
69816  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
69817  *        setting should not be used in submodule 0 as it forces the clock to logic 0.
69818  *  0b11..Reserved
69819  */
69820 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
69821 
69822 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
69823 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
69824 /*! RELOAD_SEL - Reload Source Select
69825  *  0b0..The local RELOAD signal is used to reload registers.
69826  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
69827  *       in submodule 0 as it forces the RELOAD signal to logic 0.
69828  */
69829 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
69830 
69831 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
69832 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
69833 /*! FORCE_SEL - Force Select
69834  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
69835  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
69836  *         submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
69837  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
69838  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
69839  *         not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
69840  *  0b100..The local sync signal from this submodule is used to force updates.
69841  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
69842  *         submodule0 as it holds the FORCE OUTPUT signal to logic 0.
69843  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
69844  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
69845  */
69846 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
69847 
69848 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
69849 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
69850 /*! FORCE - Force Initialization */
69851 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
69852 
69853 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
69854 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
69855 /*! FRCEN - Force Enable
69856  *  0b0..Initialization from a FORCE_OUT is disabled.
69857  *  0b1..Initialization from a FORCE_OUT is enabled.
69858  */
69859 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
69860 
69861 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
69862 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
69863 /*! INIT_SEL - Initialization Control Select
69864  *  0b00..Local sync (PWM_X) causes initialization.
69865  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
69866  *        it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload
69867  *        occurs.
69868  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
69869  *  0b11..EXT_SYNC causes initialization.
69870  */
69871 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
69872 
69873 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
69874 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
69875 /*! PWMX_INIT - PWM_X Initial Value */
69876 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
69877 
69878 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
69879 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
69880 /*! PWM45_INIT - PWM45 Initial Value */
69881 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
69882 
69883 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
69884 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
69885 /*! PWM23_INIT - PWM23 Initial Value */
69886 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
69887 
69888 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
69889 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
69890 /*! INDEP - Independent or Complementary Pair Operation
69891  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
69892  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
69893  */
69894 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
69895 
69896 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
69897 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
69898 /*! WAITEN - Wait Enable */
69899 #define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
69900 
69901 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
69902 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
69903 /*! DBGEN - Debug Enable */
69904 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
69905 /*! @} */
69906 
69907 /* The count of PWM_CTRL2 */
69908 #define PWM_CTRL2_COUNT                          (4U)
69909 
69910 /*! @name CTRL - Control Register */
69911 /*! @{ */
69912 
69913 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
69914 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
69915 /*! DBLEN - Double Switching Enable
69916  *  0b0..Double switching disabled.
69917  *  0b1..Double switching enabled.
69918  */
69919 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
69920 
69921 #define PWM_CTRL_DBLX_MASK                       (0x2U)
69922 #define PWM_CTRL_DBLX_SHIFT                      (1U)
69923 /*! DBLX - PWM_X Double Switching Enable
69924  *  0b0..PWM_X double pulse disabled.
69925  *  0b1..PWM_X double pulse enabled.
69926  */
69927 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
69928 
69929 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
69930 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
69931 /*! LDMOD - Load Mode Select
69932  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
69933  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
69934  *       In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
69935  */
69936 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
69937 
69938 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
69939 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
69940 /*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B
69941  *  0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses.
69942  *  0b1..DBLPWM is split to PWM_A and PWM_B.
69943  */
69944 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
69945 
69946 #define PWM_CTRL_PRSC_MASK                       (0x70U)
69947 #define PWM_CTRL_PRSC_SHIFT                      (4U)
69948 /*! PRSC - Prescaler
69949  *  0b000..Prescaler 1
69950  *  0b001..Prescaler 2
69951  *  0b010..Prescaler 4
69952  *  0b011..Prescaler 8
69953  *  0b100..Prescaler 16
69954  *  0b101..Prescaler 32
69955  *  0b110..Prescaler 64
69956  *  0b111..Prescaler 128
69957  */
69958 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
69959 
69960 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
69961 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
69962 /*! COMPMODE - Compare Mode
69963  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
69964  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A
69965  *       output that is high at the end of a period maintains this state until a match with VAL3 clears the output
69966  *       in the following period.
69967  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
69968  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
69969  *       values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the
69970  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
69971  */
69972 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
69973 
69974 #define PWM_CTRL_DT_MASK                         (0x300U)
69975 #define PWM_CTRL_DT_SHIFT                        (8U)
69976 /*! DT - Deadtime */
69977 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
69978 
69979 #define PWM_CTRL_FULL_MASK                       (0x400U)
69980 #define PWM_CTRL_FULL_SHIFT                      (10U)
69981 /*! FULL - Full Cycle Reload
69982  *  0b0..Full-cycle reloads disabled.
69983  *  0b1..Full-cycle reloads enabled.
69984  */
69985 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
69986 
69987 #define PWM_CTRL_HALF_MASK                       (0x800U)
69988 #define PWM_CTRL_HALF_SHIFT                      (11U)
69989 /*! HALF - Half Cycle Reload
69990  *  0b0..Half-cycle reloads disabled.
69991  *  0b1..Half-cycle reloads enabled.
69992  */
69993 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
69994 
69995 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
69996 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
69997 /*! LDFQ - Load Frequency
69998  *  0b0000..Every PWM opportunity
69999  *  0b0001..Every 2 PWM opportunities
70000  *  0b0010..Every 3 PWM opportunities
70001  *  0b0011..Every 4 PWM opportunities
70002  *  0b0100..Every 5 PWM opportunities
70003  *  0b0101..Every 6 PWM opportunities
70004  *  0b0110..Every 7 PWM opportunities
70005  *  0b0111..Every 8 PWM opportunities
70006  *  0b1000..Every 9 PWM opportunities
70007  *  0b1001..Every 10 PWM opportunities
70008  *  0b1010..Every 11 PWM opportunities
70009  *  0b1011..Every 12 PWM opportunities
70010  *  0b1100..Every 13 PWM opportunities
70011  *  0b1101..Every 14 PWM opportunities
70012  *  0b1110..Every 15 PWM opportunities
70013  *  0b1111..Every 16 PWM opportunities
70014  */
70015 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
70016 /*! @} */
70017 
70018 /* The count of PWM_CTRL */
70019 #define PWM_CTRL_COUNT                           (4U)
70020 
70021 /*! @name VAL0 - Value Register 0 */
70022 /*! @{ */
70023 
70024 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
70025 #define PWM_VAL0_VAL0_SHIFT                      (0U)
70026 /*! VAL0 - Value 0 */
70027 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
70028 /*! @} */
70029 
70030 /* The count of PWM_VAL0 */
70031 #define PWM_VAL0_COUNT                           (4U)
70032 
70033 /*! @name FRACVAL1 - Fractional Value Register 1 */
70034 /*! @{ */
70035 
70036 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
70037 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
70038 /*! FRACVAL1 - Fractional Value 1 */
70039 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
70040 /*! @} */
70041 
70042 /* The count of PWM_FRACVAL1 */
70043 #define PWM_FRACVAL1_COUNT                       (4U)
70044 
70045 /*! @name VAL1 - Value Register 1 */
70046 /*! @{ */
70047 
70048 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
70049 #define PWM_VAL1_VAL1_SHIFT                      (0U)
70050 /*! VAL1 - Value 1 */
70051 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
70052 /*! @} */
70053 
70054 /* The count of PWM_VAL1 */
70055 #define PWM_VAL1_COUNT                           (4U)
70056 
70057 /*! @name FRACVAL2 - Fractional Value Register 2 */
70058 /*! @{ */
70059 
70060 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
70061 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
70062 /*! FRACVAL2 - Fractional Value 2 */
70063 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
70064 /*! @} */
70065 
70066 /* The count of PWM_FRACVAL2 */
70067 #define PWM_FRACVAL2_COUNT                       (4U)
70068 
70069 /*! @name VAL2 - Value Register 2 */
70070 /*! @{ */
70071 
70072 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
70073 #define PWM_VAL2_VAL2_SHIFT                      (0U)
70074 /*! VAL2 - Value 2 */
70075 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
70076 /*! @} */
70077 
70078 /* The count of PWM_VAL2 */
70079 #define PWM_VAL2_COUNT                           (4U)
70080 
70081 /*! @name FRACVAL3 - Fractional Value Register 3 */
70082 /*! @{ */
70083 
70084 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
70085 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
70086 /*! FRACVAL3 - Fractional Value 3 */
70087 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
70088 /*! @} */
70089 
70090 /* The count of PWM_FRACVAL3 */
70091 #define PWM_FRACVAL3_COUNT                       (4U)
70092 
70093 /*! @name VAL3 - Value Register 3 */
70094 /*! @{ */
70095 
70096 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
70097 #define PWM_VAL3_VAL3_SHIFT                      (0U)
70098 /*! VAL3 - Value 3 */
70099 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
70100 /*! @} */
70101 
70102 /* The count of PWM_VAL3 */
70103 #define PWM_VAL3_COUNT                           (4U)
70104 
70105 /*! @name FRACVAL4 - Fractional Value Register 4 */
70106 /*! @{ */
70107 
70108 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
70109 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
70110 /*! FRACVAL4 - Fractional Value 4 */
70111 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
70112 /*! @} */
70113 
70114 /* The count of PWM_FRACVAL4 */
70115 #define PWM_FRACVAL4_COUNT                       (4U)
70116 
70117 /*! @name VAL4 - Value Register 4 */
70118 /*! @{ */
70119 
70120 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
70121 #define PWM_VAL4_VAL4_SHIFT                      (0U)
70122 /*! VAL4 - Value 4 */
70123 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
70124 /*! @} */
70125 
70126 /* The count of PWM_VAL4 */
70127 #define PWM_VAL4_COUNT                           (4U)
70128 
70129 /*! @name FRACVAL5 - Fractional Value Register 5 */
70130 /*! @{ */
70131 
70132 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
70133 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
70134 /*! FRACVAL5 - Fractional Value 5 */
70135 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
70136 /*! @} */
70137 
70138 /* The count of PWM_FRACVAL5 */
70139 #define PWM_FRACVAL5_COUNT                       (4U)
70140 
70141 /*! @name VAL5 - Value Register 5 */
70142 /*! @{ */
70143 
70144 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
70145 #define PWM_VAL5_VAL5_SHIFT                      (0U)
70146 /*! VAL5 - Value 5 */
70147 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
70148 /*! @} */
70149 
70150 /* The count of PWM_VAL5 */
70151 #define PWM_VAL5_COUNT                           (4U)
70152 
70153 /*! @name FRCTRL - Fractional Control Register */
70154 /*! @{ */
70155 
70156 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
70157 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
70158 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
70159  *  0b0..Disable fractional cycle length for the PWM period.
70160  *  0b1..Enable fractional cycle length for the PWM period.
70161  */
70162 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
70163 
70164 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
70165 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
70166 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
70167  *  0b0..Disable fractional cycle placement for PWM_A.
70168  *  0b1..Enable fractional cycle placement for PWM_A.
70169  */
70170 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
70171 
70172 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
70173 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
70174 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
70175  *  0b0..Disable fractional cycle placement for PWM_B.
70176  *  0b1..Enable fractional cycle placement for PWM_B.
70177  */
70178 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
70179 
70180 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
70181 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
70182 /*! TEST - Test Status Bit */
70183 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
70184 /*! @} */
70185 
70186 /* The count of PWM_FRCTRL */
70187 #define PWM_FRCTRL_COUNT                         (4U)
70188 
70189 /*! @name OCTRL - Output Control Register */
70190 /*! @{ */
70191 
70192 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
70193 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
70194 /*! PWMXFS - PWM_X Fault State
70195  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
70196  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
70197  *  0b10, 0b11..Output is put in a high-impedance state.
70198  */
70199 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
70200 
70201 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
70202 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
70203 /*! PWMBFS - PWM_B Fault State
70204  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
70205  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
70206  *  0b10, 0b11..Output is put in a high-impedance state.
70207  */
70208 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
70209 
70210 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
70211 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
70212 /*! PWMAFS - PWM_A Fault State
70213  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
70214  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
70215  *  0b10, 0b11..Output is put in a high-impedance state.
70216  */
70217 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
70218 
70219 #define PWM_OCTRL_POLX_MASK                      (0x100U)
70220 #define PWM_OCTRL_POLX_SHIFT                     (8U)
70221 /*! POLX - PWM_X Output Polarity
70222  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
70223  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
70224  */
70225 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
70226 
70227 #define PWM_OCTRL_POLB_MASK                      (0x200U)
70228 #define PWM_OCTRL_POLB_SHIFT                     (9U)
70229 /*! POLB - PWM_B Output Polarity
70230  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
70231  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
70232  */
70233 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
70234 
70235 #define PWM_OCTRL_POLA_MASK                      (0x400U)
70236 #define PWM_OCTRL_POLA_SHIFT                     (10U)
70237 /*! POLA - PWM_A Output Polarity
70238  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
70239  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
70240  */
70241 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
70242 
70243 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
70244 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
70245 /*! PWMX_IN - PWM_X Input */
70246 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
70247 
70248 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
70249 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
70250 /*! PWMB_IN - PWM_B Input */
70251 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
70252 
70253 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
70254 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
70255 /*! PWMA_IN - PWM_A Input */
70256 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
70257 /*! @} */
70258 
70259 /* The count of PWM_OCTRL */
70260 #define PWM_OCTRL_COUNT                          (4U)
70261 
70262 /*! @name STS - Status Register */
70263 /*! @{ */
70264 
70265 #define PWM_STS_CMPF_MASK                        (0x3FU)
70266 #define PWM_STS_CMPF_SHIFT                       (0U)
70267 /*! CMPF - Compare Flags
70268  *  0b000000..No compare event has occurred for a particular VALx value.
70269  *  0b000001..A compare event has occurred for a particular VALx value.
70270  */
70271 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
70272 
70273 #define PWM_STS_CFX0_MASK                        (0x40U)
70274 #define PWM_STS_CFX0_SHIFT                       (6U)
70275 /*! CFX0 - Capture Flag X0 */
70276 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
70277 
70278 #define PWM_STS_CFX1_MASK                        (0x80U)
70279 #define PWM_STS_CFX1_SHIFT                       (7U)
70280 /*! CFX1 - Capture Flag X1 */
70281 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
70282 
70283 #define PWM_STS_CFB0_MASK                        (0x100U)
70284 #define PWM_STS_CFB0_SHIFT                       (8U)
70285 /*! CFB0 - Capture Flag B0 */
70286 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
70287 
70288 #define PWM_STS_CFB1_MASK                        (0x200U)
70289 #define PWM_STS_CFB1_SHIFT                       (9U)
70290 /*! CFB1 - Capture Flag B1 */
70291 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
70292 
70293 #define PWM_STS_CFA0_MASK                        (0x400U)
70294 #define PWM_STS_CFA0_SHIFT                       (10U)
70295 /*! CFA0 - Capture Flag A0 */
70296 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
70297 
70298 #define PWM_STS_CFA1_MASK                        (0x800U)
70299 #define PWM_STS_CFA1_SHIFT                       (11U)
70300 /*! CFA1 - Capture Flag A1 */
70301 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
70302 
70303 #define PWM_STS_RF_MASK                          (0x1000U)
70304 #define PWM_STS_RF_SHIFT                         (12U)
70305 /*! RF - Reload Flag
70306  *  0b0..No new reload cycle since last STS[RF] clearing
70307  *  0b1..New reload cycle since last STS[RF] clearing
70308  */
70309 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
70310 
70311 #define PWM_STS_REF_MASK                         (0x2000U)
70312 #define PWM_STS_REF_SHIFT                        (13U)
70313 /*! REF - Reload Error Flag
70314  *  0b0..No reload error occurred.
70315  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
70316  */
70317 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
70318 
70319 #define PWM_STS_RUF_MASK                         (0x4000U)
70320 #define PWM_STS_RUF_SHIFT                        (14U)
70321 /*! RUF - Registers Updated Flag
70322  *  0b0..No register update has occurred since last reload.
70323  *  0b1..At least one of the double buffered registers has been updated since the last reload.
70324  */
70325 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
70326 /*! @} */
70327 
70328 /* The count of PWM_STS */
70329 #define PWM_STS_COUNT                            (4U)
70330 
70331 /*! @name INTEN - Interrupt Enable Register */
70332 /*! @{ */
70333 
70334 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
70335 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
70336 /*! CMPIE - Compare Interrupt Enables
70337  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
70338  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
70339  */
70340 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
70341 
70342 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
70343 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
70344 /*! CX0IE - Capture X 0 Interrupt Enable
70345  *  0b0..Interrupt request disabled for STS[CFX0].
70346  *  0b1..Interrupt request enabled for STS[CFX0].
70347  */
70348 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
70349 
70350 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
70351 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
70352 /*! CX1IE - Capture X 1 Interrupt Enable
70353  *  0b0..Interrupt request disabled for STS[CFX1].
70354  *  0b1..Interrupt request enabled for STS[CFX1].
70355  */
70356 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
70357 
70358 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
70359 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
70360 /*! CB0IE - Capture B 0 Interrupt Enable
70361  *  0b0..Interrupt request disabled for STS[CFB0].
70362  *  0b1..Interrupt request enabled for STS[CFB0].
70363  */
70364 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
70365 
70366 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
70367 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
70368 /*! CB1IE - Capture B 1 Interrupt Enable
70369  *  0b0..Interrupt request disabled for STS[CFB1].
70370  *  0b1..Interrupt request enabled for STS[CFB1].
70371  */
70372 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
70373 
70374 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
70375 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
70376 /*! CA0IE - Capture A 0 Interrupt Enable
70377  *  0b0..Interrupt request disabled for STS[CFA0].
70378  *  0b1..Interrupt request enabled for STS[CFA0].
70379  */
70380 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
70381 
70382 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
70383 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
70384 /*! CA1IE - Capture A 1 Interrupt Enable
70385  *  0b0..Interrupt request disabled for STS[CFA1]
70386  *  0b1..Interrupt request enabled for STS[CFA1]
70387  */
70388 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
70389 
70390 #define PWM_INTEN_RIE_MASK                       (0x1000U)
70391 #define PWM_INTEN_RIE_SHIFT                      (12U)
70392 /*! RIE - Reload Interrupt Enable
70393  *  0b0..STS[RF] CPU interrupt requests disabled
70394  *  0b1..STS[RF] CPU interrupt requests enabled
70395  */
70396 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
70397 
70398 #define PWM_INTEN_REIE_MASK                      (0x2000U)
70399 #define PWM_INTEN_REIE_SHIFT                     (13U)
70400 /*! REIE - Reload Error Interrupt Enable
70401  *  0b0..STS[REF] CPU interrupt requests disabled
70402  *  0b1..STS[REF] CPU interrupt requests enabled
70403  */
70404 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
70405 /*! @} */
70406 
70407 /* The count of PWM_INTEN */
70408 #define PWM_INTEN_COUNT                          (4U)
70409 
70410 /*! @name DMAEN - DMA Enable Register */
70411 /*! @{ */
70412 
70413 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
70414 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
70415 /*! CX0DE - Capture X0 FIFO DMA Enable */
70416 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
70417 
70418 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
70419 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
70420 /*! CX1DE - Capture X1 FIFO DMA Enable */
70421 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
70422 
70423 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
70424 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
70425 /*! CB0DE - Capture B0 FIFO DMA Enable */
70426 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
70427 
70428 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
70429 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
70430 /*! CB1DE - Capture B1 FIFO DMA Enable */
70431 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
70432 
70433 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
70434 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
70435 /*! CA0DE - Capture A0 FIFO DMA Enable */
70436 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
70437 
70438 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
70439 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
70440 /*! CA1DE - Capture A1 FIFO DMA Enable */
70441 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
70442 
70443 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
70444 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
70445 /*! CAPTDE - Capture DMA Enable Source Select
70446  *  0b00..Read DMA requests disabled.
70447  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
70448  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which
70449  *        watermark(s) the DMA request is sensitive.
70450  *  0b10..A local synchronization (VAL1 matches counter) sets the read DMA request.
70451  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
70452  */
70453 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
70454 
70455 #define PWM_DMAEN_FAND_MASK                      (0x100U)
70456 #define PWM_DMAEN_FAND_SHIFT                     (8U)
70457 /*! FAND - FIFO Watermark AND Control
70458  *  0b0..Selected FIFO watermarks are OR'ed together.
70459  *  0b1..Selected FIFO watermarks are AND'ed together.
70460  */
70461 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
70462 
70463 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
70464 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
70465 /*! VALDE - Value Registers DMA Enable
70466  *  0b0..DMA write requests disabled
70467  *  0b1..Enabled
70468  */
70469 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
70470 /*! @} */
70471 
70472 /* The count of PWM_DMAEN */
70473 #define PWM_DMAEN_COUNT                          (4U)
70474 
70475 /*! @name TCTRL - Output Trigger Control Register */
70476 /*! @{ */
70477 
70478 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
70479 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
70480 /*! OUT_TRIG_EN - Output Trigger Enables
70481  *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
70482  *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
70483  *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
70484  *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
70485  *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
70486  *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
70487  */
70488 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
70489 
70490 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
70491 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
70492 /*! TRGFRQ - Trigger Frequency
70493  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
70494  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
70495  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
70496  */
70497 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
70498 
70499 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
70500 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
70501 /*! PWBOT1 - Mux Output Trigger 1 Source Select
70502  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
70503  *  0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port.
70504  */
70505 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
70506 
70507 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
70508 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
70509 /*! PWAOT0 - Mux Output Trigger 0 Source Select
70510  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
70511  *  0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port.
70512  */
70513 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
70514 /*! @} */
70515 
70516 /* The count of PWM_TCTRL */
70517 #define PWM_TCTRL_COUNT                          (4U)
70518 
70519 /*! @name DISMAP - Fault Disable Mapping Register 0 */
70520 /*! @{ */
70521 
70522 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
70523 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
70524 /*! DIS0A - PWM_A Fault Disable Mask 0 */
70525 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
70526 
70527 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
70528 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
70529 /*! DIS0B - PWM_B Fault Disable Mask 0 */
70530 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
70531 
70532 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
70533 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
70534 /*! DIS0X - PWM_X Fault Disable Mask 0 */
70535 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
70536 /*! @} */
70537 
70538 /* The count of PWM_DISMAP */
70539 #define PWM_DISMAP_COUNT                         (4U)
70540 
70541 /* The count of PWM_DISMAP */
70542 #define PWM_DISMAP_COUNT2                        (1U)
70543 
70544 /*! @name DTCNT0 - Deadtime Count Register 0 */
70545 /*! @{ */
70546 
70547 #define PWM_DTCNT0_DTCNT0_MASK                   (0xFFFFU)
70548 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
70549 /*! DTCNT0 - DTCNT0 */
70550 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
70551 /*! @} */
70552 
70553 /* The count of PWM_DTCNT0 */
70554 #define PWM_DTCNT0_COUNT                         (4U)
70555 
70556 /*! @name DTCNT1 - Deadtime Count Register 1 */
70557 /*! @{ */
70558 
70559 #define PWM_DTCNT1_DTCNT1_MASK                   (0xFFFFU)
70560 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
70561 /*! DTCNT1 - DTCNT1 */
70562 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
70563 /*! @} */
70564 
70565 /* The count of PWM_DTCNT1 */
70566 #define PWM_DTCNT1_COUNT                         (4U)
70567 
70568 /*! @name CAPTCTRLA - Capture Control A Register */
70569 /*! @{ */
70570 
70571 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
70572 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
70573 /*! ARMA - Arm A
70574  *  0b0..Input capture operation is disabled.
70575  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
70576  */
70577 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
70578 
70579 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
70580 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
70581 /*! ONESHOTA - One Shot Mode A
70582  *  0b0..Free Running
70583  *  0b1..One Shot
70584  */
70585 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
70586 
70587 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
70588 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
70589 /*! EDGA0 - Edge A 0
70590  *  0b00..Disabled
70591  *  0b01..Capture falling edges
70592  *  0b10..Capture rising edges
70593  *  0b11..Capture any edge
70594  */
70595 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
70596 
70597 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
70598 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
70599 /*! EDGA1 - Edge A 1
70600  *  0b00..Disabled
70601  *  0b01..Capture falling edges
70602  *  0b10..Capture rising edges
70603  *  0b11..Capture any edge
70604  */
70605 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
70606 
70607 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
70608 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
70609 /*! INP_SELA - Input Select A
70610  *  0b0..Raw PWM_A input signal selected as source.
70611  *  0b1..Edge Counter
70612  */
70613 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
70614 
70615 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
70616 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
70617 /*! EDGCNTA_EN - Edge Counter A Enable
70618  *  0b0..Edge counter disabled and held in reset
70619  *  0b1..Edge counter enabled
70620  */
70621 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
70622 
70623 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
70624 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
70625 /*! CFAWM - Capture A FIFOs Water Mark */
70626 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
70627 
70628 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
70629 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
70630 /*! CA0CNT - Capture A0 FIFO Word Count */
70631 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
70632 
70633 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
70634 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
70635 /*! CA1CNT - Capture A1 FIFO Word Count */
70636 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
70637 /*! @} */
70638 
70639 /* The count of PWM_CAPTCTRLA */
70640 #define PWM_CAPTCTRLA_COUNT                      (4U)
70641 
70642 /*! @name CAPTCOMPA - Capture Compare A Register */
70643 /*! @{ */
70644 
70645 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
70646 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
70647 /*! EDGCMPA - Edge Compare A */
70648 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
70649 
70650 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
70651 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
70652 /*! EDGCNTA - Edge Counter A */
70653 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
70654 /*! @} */
70655 
70656 /* The count of PWM_CAPTCOMPA */
70657 #define PWM_CAPTCOMPA_COUNT                      (4U)
70658 
70659 /*! @name CAPTCTRLB - Capture Control B Register */
70660 /*! @{ */
70661 
70662 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
70663 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
70664 /*! ARMB - Arm B
70665  *  0b0..Input capture operation is disabled.
70666  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
70667  */
70668 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
70669 
70670 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
70671 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
70672 /*! ONESHOTB - One Shot Mode B
70673  *  0b0..Free Running
70674  *  0b1..One Shot
70675  */
70676 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
70677 
70678 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
70679 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
70680 /*! EDGB0 - Edge B 0
70681  *  0b00..Disabled
70682  *  0b01..Capture falling edges
70683  *  0b10..Capture rising edges
70684  *  0b11..Capture any edge
70685  */
70686 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
70687 
70688 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
70689 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
70690 /*! EDGB1 - Edge B 1
70691  *  0b00..Disabled
70692  *  0b01..Capture falling edges
70693  *  0b10..Capture rising edges
70694  *  0b11..Capture any edge
70695  */
70696 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
70697 
70698 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
70699 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
70700 /*! INP_SELB - Input Select B
70701  *  0b0..Raw PWM_B input signal selected as source.
70702  *  0b1..Edge Counter
70703  */
70704 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
70705 
70706 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
70707 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
70708 /*! EDGCNTB_EN - Edge Counter B Enable
70709  *  0b0..Edge counter disabled and held in reset
70710  *  0b1..Edge counter enabled
70711  */
70712 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
70713 
70714 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
70715 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
70716 /*! CFBWM - Capture B FIFOs Water Mark */
70717 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
70718 
70719 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
70720 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
70721 /*! CB0CNT - Capture B0 FIFO Word Count */
70722 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
70723 
70724 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
70725 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
70726 /*! CB1CNT - Capture B1 FIFO Word Count */
70727 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
70728 /*! @} */
70729 
70730 /* The count of PWM_CAPTCTRLB */
70731 #define PWM_CAPTCTRLB_COUNT                      (4U)
70732 
70733 /*! @name CAPTCOMPB - Capture Compare B Register */
70734 /*! @{ */
70735 
70736 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
70737 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
70738 /*! EDGCMPB - Edge Compare B */
70739 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
70740 
70741 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
70742 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
70743 /*! EDGCNTB - Edge Counter B */
70744 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
70745 /*! @} */
70746 
70747 /* The count of PWM_CAPTCOMPB */
70748 #define PWM_CAPTCOMPB_COUNT                      (4U)
70749 
70750 /*! @name CAPTCTRLX - Capture Control X Register */
70751 /*! @{ */
70752 
70753 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
70754 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
70755 /*! ARMX - Arm X
70756  *  0b0..Input capture operation is disabled.
70757  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
70758  */
70759 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
70760 
70761 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
70762 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
70763 /*! ONESHOTX - One Shot Mode Aux
70764  *  0b0..Free Running
70765  *  0b1..One Shot
70766  */
70767 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
70768 
70769 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
70770 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
70771 /*! EDGX0 - Edge X 0
70772  *  0b00..Disabled
70773  *  0b01..Capture falling edges
70774  *  0b10..Capture rising edges
70775  *  0b11..Capture any edge
70776  */
70777 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
70778 
70779 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
70780 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
70781 /*! EDGX1 - Edge X 1
70782  *  0b00..Disabled
70783  *  0b01..Capture falling edges
70784  *  0b10..Capture rising edges
70785  *  0b11..Capture any edge
70786  */
70787 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
70788 
70789 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
70790 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
70791 /*! INP_SELX - Input Select X
70792  *  0b0..Raw PWM_X input signal selected as source.
70793  *  0b1..Edge Counter
70794  */
70795 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
70796 
70797 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
70798 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
70799 /*! EDGCNTX_EN - Edge Counter X Enable
70800  *  0b0..Edge counter disabled and held in reset
70801  *  0b1..Edge counter enabled
70802  */
70803 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
70804 
70805 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
70806 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
70807 /*! CFXWM - Capture X FIFOs Water Mark */
70808 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
70809 
70810 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
70811 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
70812 /*! CX0CNT - Capture X0 FIFO Word Count */
70813 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
70814 
70815 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
70816 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
70817 /*! CX1CNT - Capture X1 FIFO Word Count */
70818 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
70819 /*! @} */
70820 
70821 /* The count of PWM_CAPTCTRLX */
70822 #define PWM_CAPTCTRLX_COUNT                      (4U)
70823 
70824 /*! @name CAPTCOMPX - Capture Compare X Register */
70825 /*! @{ */
70826 
70827 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
70828 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
70829 /*! EDGCMPX - Edge Compare X */
70830 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
70831 
70832 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
70833 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
70834 /*! EDGCNTX - Edge Counter X */
70835 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
70836 /*! @} */
70837 
70838 /* The count of PWM_CAPTCOMPX */
70839 #define PWM_CAPTCOMPX_COUNT                      (4U)
70840 
70841 /*! @name CVAL0 - Capture Value 0 Register */
70842 /*! @{ */
70843 
70844 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
70845 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
70846 /*! CAPTVAL0 - Capture Value 0 */
70847 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
70848 /*! @} */
70849 
70850 /* The count of PWM_CVAL0 */
70851 #define PWM_CVAL0_COUNT                          (4U)
70852 
70853 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
70854 /*! @{ */
70855 
70856 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
70857 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
70858 /*! CVAL0CYC - Capture Value 0 Cycle */
70859 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
70860 /*! @} */
70861 
70862 /* The count of PWM_CVAL0CYC */
70863 #define PWM_CVAL0CYC_COUNT                       (4U)
70864 
70865 /*! @name CVAL1 - Capture Value 1 Register */
70866 /*! @{ */
70867 
70868 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
70869 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
70870 /*! CAPTVAL1 - Capture Value 1 */
70871 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
70872 /*! @} */
70873 
70874 /* The count of PWM_CVAL1 */
70875 #define PWM_CVAL1_COUNT                          (4U)
70876 
70877 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
70878 /*! @{ */
70879 
70880 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
70881 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
70882 /*! CVAL1CYC - Capture Value 1 Cycle */
70883 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
70884 /*! @} */
70885 
70886 /* The count of PWM_CVAL1CYC */
70887 #define PWM_CVAL1CYC_COUNT                       (4U)
70888 
70889 /*! @name CVAL2 - Capture Value 2 Register */
70890 /*! @{ */
70891 
70892 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
70893 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
70894 /*! CAPTVAL2 - Capture Value 2 */
70895 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
70896 /*! @} */
70897 
70898 /* The count of PWM_CVAL2 */
70899 #define PWM_CVAL2_COUNT                          (4U)
70900 
70901 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
70902 /*! @{ */
70903 
70904 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
70905 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
70906 /*! CVAL2CYC - Capture Value 2 Cycle */
70907 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
70908 /*! @} */
70909 
70910 /* The count of PWM_CVAL2CYC */
70911 #define PWM_CVAL2CYC_COUNT                       (4U)
70912 
70913 /*! @name CVAL3 - Capture Value 3 Register */
70914 /*! @{ */
70915 
70916 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
70917 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
70918 /*! CAPTVAL3 - Capture Value 3 */
70919 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
70920 /*! @} */
70921 
70922 /* The count of PWM_CVAL3 */
70923 #define PWM_CVAL3_COUNT                          (4U)
70924 
70925 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
70926 /*! @{ */
70927 
70928 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
70929 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
70930 /*! CVAL3CYC - Capture Value 3 Cycle */
70931 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
70932 /*! @} */
70933 
70934 /* The count of PWM_CVAL3CYC */
70935 #define PWM_CVAL3CYC_COUNT                       (4U)
70936 
70937 /*! @name CVAL4 - Capture Value 4 Register */
70938 /*! @{ */
70939 
70940 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
70941 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
70942 /*! CAPTVAL4 - Capture Value 4 */
70943 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
70944 /*! @} */
70945 
70946 /* The count of PWM_CVAL4 */
70947 #define PWM_CVAL4_COUNT                          (4U)
70948 
70949 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
70950 /*! @{ */
70951 
70952 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
70953 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
70954 /*! CVAL4CYC - Capture Value 4 Cycle */
70955 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
70956 /*! @} */
70957 
70958 /* The count of PWM_CVAL4CYC */
70959 #define PWM_CVAL4CYC_COUNT                       (4U)
70960 
70961 /*! @name CVAL5 - Capture Value 5 Register */
70962 /*! @{ */
70963 
70964 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
70965 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
70966 /*! CAPTVAL5 - Capture Value 5 */
70967 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
70968 /*! @} */
70969 
70970 /* The count of PWM_CVAL5 */
70971 #define PWM_CVAL5_COUNT                          (4U)
70972 
70973 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
70974 /*! @{ */
70975 
70976 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
70977 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
70978 /*! CVAL5CYC - Capture Value 5 Cycle */
70979 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
70980 /*! @} */
70981 
70982 /* The count of PWM_CVAL5CYC */
70983 #define PWM_CVAL5CYC_COUNT                       (4U)
70984 
70985 /*! @name PHASEDLY - Phase Delay Register */
70986 /*! @{ */
70987 
70988 #define PWM_PHASEDLY_PHASEDLY_MASK               (0xFFFFU)
70989 #define PWM_PHASEDLY_PHASEDLY_SHIFT              (0U)
70990 /*! PHASEDLY - Initial Count Register Bits */
70991 #define PWM_PHASEDLY_PHASEDLY(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
70992 /*! @} */
70993 
70994 /* The count of PWM_PHASEDLY */
70995 #define PWM_PHASEDLY_COUNT                       (4U)
70996 
70997 /*! @name CAPTFILTA - Capture PWM_A Input Filter Register */
70998 /*! @{ */
70999 
71000 #define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK        (0xFFU)
71001 #define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT       (0U)
71002 /*! CAPTA_FILT_PER - Input Capture Filter Period */
71003 #define PWM_CAPTFILTA_CAPTA_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK)
71004 
71005 #define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK        (0x700U)
71006 #define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT       (8U)
71007 /*! CAPTA_FILT_CNT - Input Capture Filter Count */
71008 #define PWM_CAPTFILTA_CAPTA_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK)
71009 /*! @} */
71010 
71011 /* The count of PWM_CAPTFILTA */
71012 #define PWM_CAPTFILTA_COUNT                      (4U)
71013 
71014 /*! @name CAPTFILTB - Capture PWM_B Input Filter Register */
71015 /*! @{ */
71016 
71017 #define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK        (0xFFU)
71018 #define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT       (0U)
71019 /*! CAPTB_FILT_PER - Input Capture Filter Period */
71020 #define PWM_CAPTFILTB_CAPTB_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK)
71021 
71022 #define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK        (0x700U)
71023 #define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT       (8U)
71024 /*! CAPTB_FILT_CNT - Input Capture Filter Count */
71025 #define PWM_CAPTFILTB_CAPTB_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK)
71026 /*! @} */
71027 
71028 /* The count of PWM_CAPTFILTB */
71029 #define PWM_CAPTFILTB_COUNT                      (4U)
71030 
71031 /*! @name CAPTFILTX - Capture PWM_X Input Filter Register */
71032 /*! @{ */
71033 
71034 #define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK        (0xFFU)
71035 #define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT       (0U)
71036 /*! CAPTX_FILT_PER - Input Capture Filter Period */
71037 #define PWM_CAPTFILTX_CAPTX_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK)
71038 
71039 #define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK        (0x700U)
71040 #define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT       (8U)
71041 /*! CAPTX_FILT_CNT - Input Capture Filter Count */
71042 #define PWM_CAPTFILTX_CAPTX_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK)
71043 /*! @} */
71044 
71045 /* The count of PWM_CAPTFILTX */
71046 #define PWM_CAPTFILTX_COUNT                      (4U)
71047 
71048 /*! @name OUTEN - Output Enable Register */
71049 /*! @{ */
71050 
71051 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
71052 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
71053 /*! PWMX_EN - PWM_X Output Enables */
71054 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
71055 
71056 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
71057 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
71058 /*! PWMB_EN - PWM_B Output Enables */
71059 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
71060 
71061 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
71062 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
71063 /*! PWMA_EN - PWM_A Output Enables */
71064 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
71065 /*! @} */
71066 
71067 /*! @name MASK - Mask Register */
71068 /*! @{ */
71069 
71070 #define PWM_MASK_MASKX_MASK                      (0xFU)
71071 #define PWM_MASK_MASKX_SHIFT                     (0U)
71072 /*! MASKX - PWM_X Masks */
71073 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
71074 
71075 #define PWM_MASK_MASKB_MASK                      (0xF0U)
71076 #define PWM_MASK_MASKB_SHIFT                     (4U)
71077 /*! MASKB - PWM_B Masks */
71078 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
71079 
71080 #define PWM_MASK_MASKA_MASK                      (0xF00U)
71081 #define PWM_MASK_MASKA_SHIFT                     (8U)
71082 /*! MASKA - PWM_A Masks */
71083 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
71084 /*! @} */
71085 
71086 /*! @name SWCOUT - Software Controlled Output Register */
71087 /*! @{ */
71088 
71089 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
71090 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
71091 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
71092  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
71093  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
71094  */
71095 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
71096 
71097 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
71098 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
71099 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
71100  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
71101  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
71102  */
71103 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
71104 
71105 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
71106 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
71107 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
71108  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
71109  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
71110  */
71111 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
71112 
71113 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
71114 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
71115 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
71116  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
71117  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
71118  */
71119 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
71120 
71121 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
71122 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
71123 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
71124  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
71125  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
71126  */
71127 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
71128 
71129 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
71130 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
71131 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
71132  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
71133  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
71134  */
71135 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
71136 
71137 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
71138 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
71139 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
71140  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
71141  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
71142  */
71143 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
71144 
71145 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
71146 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
71147 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
71148  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
71149  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
71150  */
71151 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
71152 /*! @} */
71153 
71154 /*! @name DTSRCSEL - PWM Source Select Register */
71155 /*! @{ */
71156 
71157 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
71158 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
71159 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
71160  *  0b00..Generated SM0PWM45 signal used by the deadtime logic.
71161  *  0b01..Inverted generated SM0PWM45 signal used by the deadtime logic.
71162  *  0b10..SWCOUT[SM0OUT45] used by the deadtime logic.
71163  *  0b11..Reserved
71164  */
71165 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
71166 
71167 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
71168 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
71169 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
71170  *  0b00..Generated SM0PWM23 signal used by the deadtime logic.
71171  *  0b01..Inverted generated SM0PWM23 signal used by the deadtime logic.
71172  *  0b10..SWCOUT[SM0OUT23] used by the deadtime logic.
71173  *  0b11..PWM0_EXTA signal used by the deadtime logic.
71174  */
71175 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
71176 
71177 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
71178 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
71179 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
71180  *  0b00..Generated SM1PWM45 signal used by the deadtime logic.
71181  *  0b01..Inverted generated SM1PWM45 signal used by the deadtime logic.
71182  *  0b10..SWCOUT[SM1OUT45] used by the deadtime logic.
71183  *  0b11..Reserved
71184  */
71185 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
71186 
71187 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
71188 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
71189 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
71190  *  0b00..Generated SM1PWM23 signal used by the deadtime logic.
71191  *  0b01..Inverted generated SM1PWM23 signal used by the deadtime logic.
71192  *  0b10..SWCOUT[SM1OUT23] used by the deadtime logic.
71193  *  0b11..PWM1_EXTA signal used by the deadtime logic.
71194  */
71195 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
71196 
71197 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
71198 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
71199 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
71200  *  0b00..Generated SM2PWM45 signal used by the deadtime logic.
71201  *  0b01..Inverted generated SM2PWM45 signal used by the deadtime logic.
71202  *  0b10..SWCOUT[SM2OUT45] used by the deadtime logic.
71203  *  0b11..Reserved
71204  */
71205 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
71206 
71207 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
71208 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
71209 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
71210  *  0b00..Generated SM2PWM23 signal used by the deadtime logic.
71211  *  0b01..Inverted generated SM2PWM23 signal used by the deadtime logic.
71212  *  0b10..SWCOUT[SM2OUT23] used by the deadtime logic.
71213  *  0b11..PWM2_EXTA signal used by the deadtime logic.
71214  */
71215 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
71216 
71217 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
71218 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
71219 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
71220  *  0b00..Generated SM3PWM45 signal used by the deadtime logic.
71221  *  0b01..Inverted generated SM3PWM45 signal used by the deadtime logic.
71222  *  0b10..SWCOUT[SM3OUT45] used by the deadtime logic.
71223  *  0b11..Reserved
71224  */
71225 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
71226 
71227 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
71228 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
71229 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
71230  *  0b00..Generated SM3PWM23 signal used by the deadtime logic.
71231  *  0b01..Inverted generated SM3PWM23 signal used by the deadtime logic.
71232  *  0b10..SWCOUT[SM3OUT23] used by the deadtime logic.
71233  *  0b11..PWM3_EXTA signal used by the deadtime logic.
71234  */
71235 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
71236 /*! @} */
71237 
71238 /*! @name MCTRL - Master Control Register */
71239 /*! @{ */
71240 
71241 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
71242 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
71243 /*! LDOK - Load Okay
71244  *  0b0000..Do not load new values.
71245  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
71246  */
71247 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
71248 
71249 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
71250 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
71251 /*! CLDOK - Clear Load Okay */
71252 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
71253 
71254 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
71255 #define PWM_MCTRL_RUN_SHIFT                      (8U)
71256 /*! RUN - Run
71257  *  0b0000..PWM counter is stopped, but PWM outputs hold the current state.
71258  *  0b0001..PWM counter is started in the corresponding submodule.
71259  */
71260 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
71261 
71262 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
71263 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
71264 /*! IPOL - Current Polarity
71265  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
71266  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
71267  */
71268 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
71269 /*! @} */
71270 
71271 /*! @name MCTRL2 - Master Control 2 Register */
71272 /*! @{ */
71273 
71274 #define PWM_MCTRL2_WRPROT_MASK                   (0xCU)
71275 #define PWM_MCTRL2_WRPROT_SHIFT                  (2U)
71276 /*! WRPROT - Write protect
71277  *  0b00..Write protection off (default).
71278  *  0b01..Write protection on.
71279  *  0b10..Write protection off and locked until chip reset.
71280  *  0b11..Write protection on and locked until chip reset.
71281  */
71282 #define PWM_MCTRL2_WRPROT(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK)
71283 /*! @} */
71284 
71285 /*! @name FCTRL - Fault Control Register */
71286 /*! @{ */
71287 
71288 #define PWM_FCTRL_FIE_MASK                       (0xFU)
71289 #define PWM_FCTRL_FIE_SHIFT                      (0U)
71290 /*! FIE - Fault Interrupt Enables
71291  *  0b0000..FAULTx CPU interrupt requests disabled.
71292  *  0b0001..FAULTx CPU interrupt requests enabled.
71293  */
71294 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
71295 
71296 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
71297 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
71298 /*! FSAFE - Fault Safety Mode
71299  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
71300  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
71301  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be
71302  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
71303  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
71304  *          DISMAPn).
71305  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
71306  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
71307  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
71308  */
71309 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
71310 
71311 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
71312 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
71313 /*! FAUTO - Automatic Fault Clearing
71314  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
71315  *          at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If
71316  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled
71317  *          by FCTRL[FSAFE].
71318  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
71319  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
71320  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
71321  *          cannot be cleared.
71322  */
71323 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
71324 
71325 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
71326 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
71327 /*! FLVL - Fault Level
71328  *  0b0000..A logic 0 on the fault input indicates a fault condition.
71329  *  0b0001..A logic 1 on the fault input indicates a fault condition.
71330  */
71331 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
71332 /*! @} */
71333 
71334 /*! @name FSTS - Fault Status Register */
71335 /*! @{ */
71336 
71337 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
71338 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
71339 /*! FFLAG - Fault Flags
71340  *  0b0000..No fault on the FAULTx pin.
71341  *  0b0001..Fault on the FAULTx pin.
71342  */
71343 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
71344 
71345 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
71346 #define PWM_FSTS_FFULL_SHIFT                     (4U)
71347 /*! FFULL - Full Cycle
71348  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
71349  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
71350  */
71351 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
71352 
71353 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
71354 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
71355 /*! FFPIN - Filtered Fault Pins */
71356 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
71357 
71358 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
71359 #define PWM_FSTS_FHALF_SHIFT                     (12U)
71360 /*! FHALF - Half Cycle Fault Recovery
71361  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
71362  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
71363  */
71364 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
71365 /*! @} */
71366 
71367 /*! @name FFILT - Fault Filter Register */
71368 /*! @{ */
71369 
71370 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
71371 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
71372 /*! FILT_PER - Fault Filter Period */
71373 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
71374 
71375 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
71376 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
71377 /*! FILT_CNT - Fault Filter Count */
71378 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
71379 
71380 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
71381 #define PWM_FFILT_GSTR_SHIFT                     (15U)
71382 /*! GSTR - Fault Glitch Stretch Enable
71383  *  0b0..Fault input glitch stretching is disabled.
71384  *  0b1..Input fault signals are stretched to at least 2 IPBus clock cycles.
71385  */
71386 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
71387 /*! @} */
71388 
71389 /*! @name FTST - Fault Test Register */
71390 /*! @{ */
71391 
71392 #define PWM_FTST_FTEST_MASK                      (0x1U)
71393 #define PWM_FTST_FTEST_SHIFT                     (0U)
71394 /*! FTEST - Fault Test
71395  *  0b0..No fault
71396  *  0b1..Cause a simulated fault
71397  */
71398 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
71399 /*! @} */
71400 
71401 /*! @name FCTRL2 - Fault Control 2 Register */
71402 /*! @{ */
71403 
71404 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
71405 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
71406 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
71407  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
71408  *          with the filtered and latched fault signals to disable the PWM outputs.
71409  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
71410  *          and latched fault signals are used to disable the PWM outputs.
71411  */
71412 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
71413 /*! @} */
71414 
71415 
71416 /*!
71417  * @}
71418  */ /* end of group PWM_Register_Masks */
71419 
71420 
71421 /* PWM - Peripheral instance base addresses */
71422 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
71423   /** Peripheral PWM1 base address */
71424   #define PWM1_BASE                                (0x52650000u)
71425   /** Peripheral PWM1 base address */
71426   #define PWM1_BASE_NS                             (0x42650000u)
71427   /** Peripheral PWM1 base pointer */
71428   #define PWM1                                     ((PWM_Type *)PWM1_BASE)
71429   /** Peripheral PWM1 base pointer */
71430   #define PWM1_NS                                  ((PWM_Type *)PWM1_BASE_NS)
71431   /** Peripheral PWM2 base address */
71432   #define PWM2_BASE                                (0x52660000u)
71433   /** Peripheral PWM2 base address */
71434   #define PWM2_BASE_NS                             (0x42660000u)
71435   /** Peripheral PWM2 base pointer */
71436   #define PWM2                                     ((PWM_Type *)PWM2_BASE)
71437   /** Peripheral PWM2 base pointer */
71438   #define PWM2_NS                                  ((PWM_Type *)PWM2_BASE_NS)
71439   /** Array initializer of PWM peripheral base addresses */
71440   #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE }
71441   /** Array initializer of PWM peripheral base pointers */
71442   #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2 }
71443   /** Array initializer of PWM peripheral base addresses */
71444   #define PWM_BASE_ADDRS_NS                        { 0u, PWM1_BASE_NS, PWM2_BASE_NS }
71445   /** Array initializer of PWM peripheral base pointers */
71446   #define PWM_BASE_PTRS_NS                         { (PWM_Type *)0u, PWM1_NS, PWM2_NS }
71447 #else
71448   /** Peripheral PWM1 base address */
71449   #define PWM1_BASE                                (0x42650000u)
71450   /** Peripheral PWM1 base pointer */
71451   #define PWM1                                     ((PWM_Type *)PWM1_BASE)
71452   /** Peripheral PWM2 base address */
71453   #define PWM2_BASE                                (0x42660000u)
71454   /** Peripheral PWM2 base pointer */
71455   #define PWM2                                     ((PWM_Type *)PWM2_BASE)
71456   /** Array initializer of PWM peripheral base addresses */
71457   #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE }
71458   /** Array initializer of PWM peripheral base pointers */
71459   #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2 }
71460 #endif
71461 /** Interrupt vectors for the PWM peripheral type */
71462 #define PWM_CMP_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
71463 #define PWM_RELOAD_IRQS                          { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
71464 #define PWM_CAPTURE_IRQS                         { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
71465 #define PWM_FAULT_IRQS                           { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }
71466 #define PWM_RELOAD_ERROR_IRQS                    { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }
71467 
71468 /*!
71469  * @}
71470  */ /* end of group PWM_Peripheral_Access_Layer */
71471 
71472 
71473 /* ----------------------------------------------------------------------------
71474    -- RGPIO Peripheral Access Layer
71475    ---------------------------------------------------------------------------- */
71476 
71477 /*!
71478  * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer
71479  * @{
71480  */
71481 
71482 /** RGPIO - Register Layout Typedef */
71483 typedef struct {
71484   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
71485   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
71486        uint8_t RESERVED_0[4];
71487   __IO uint32_t LOCK;                              /**< Lock, offset: 0xC */
71488   __IO uint32_t PCNS;                              /**< Pin Control Non-Secure, offset: 0x10 */
71489   __IO uint32_t ICNS;                              /**< Interrupt Control Non-Secure, offset: 0x14 */
71490   __IO uint32_t PCNP;                              /**< Pin Control Non-Privilege, offset: 0x18 */
71491   __IO uint32_t ICNP;                              /**< Interrupt Control Non-Privilege, offset: 0x1C */
71492        uint8_t RESERVED_1[32];
71493   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x40 */
71494   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x44 */
71495   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x48 */
71496   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0x4C */
71497   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x50 */
71498   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x54 */
71499   __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x58 */
71500        uint8_t RESERVED_2[4];
71501   __IO uint8_t PDR[32];                            /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */
71502   __IO uint32_t ICR[32];                           /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4 */
71503   __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x100 */
71504   __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x104 */
71505        uint8_t RESERVED_3[24];
71506   __IO uint32_t ISFR[2];                           /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */
71507 } RGPIO_Type;
71508 
71509 /* ----------------------------------------------------------------------------
71510    -- RGPIO Register Masks
71511    ---------------------------------------------------------------------------- */
71512 
71513 /*!
71514  * @addtogroup RGPIO_Register_Masks RGPIO Register Masks
71515  * @{
71516  */
71517 
71518 /*! @name VERID - Version ID */
71519 /*! @{ */
71520 
71521 #define RGPIO_VERID_FEATURE_MASK                 (0xFFFFU)
71522 #define RGPIO_VERID_FEATURE_SHIFT                (0U)
71523 /*! FEATURE - Feature Specification Number
71524  *  0b0000000000000000..Basic implementation.
71525  *  0b0000000000000001..Protection registers implemented.
71526  */
71527 #define RGPIO_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_FEATURE_SHIFT)) & RGPIO_VERID_FEATURE_MASK)
71528 
71529 #define RGPIO_VERID_MINOR_MASK                   (0xFF0000U)
71530 #define RGPIO_VERID_MINOR_SHIFT                  (16U)
71531 /*! MINOR - Minor Version Number */
71532 #define RGPIO_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MINOR_SHIFT)) & RGPIO_VERID_MINOR_MASK)
71533 
71534 #define RGPIO_VERID_MAJOR_MASK                   (0xFF000000U)
71535 #define RGPIO_VERID_MAJOR_SHIFT                  (24U)
71536 /*! MAJOR - Major Version Number */
71537 #define RGPIO_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MAJOR_SHIFT)) & RGPIO_VERID_MAJOR_MASK)
71538 /*! @} */
71539 
71540 /*! @name PARAM - Parameter */
71541 /*! @{ */
71542 
71543 #define RGPIO_PARAM_IRQNUM_MASK                  (0xFU)
71544 #define RGPIO_PARAM_IRQNUM_SHIFT                 (0U)
71545 /*! IRQNUM - Interrupt Number */
71546 #define RGPIO_PARAM_IRQNUM(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_PARAM_IRQNUM_SHIFT)) & RGPIO_PARAM_IRQNUM_MASK)
71547 /*! @} */
71548 
71549 /*! @name LOCK - Lock */
71550 /*! @{ */
71551 
71552 #define RGPIO_LOCK_PCNS_MASK                     (0x1U)
71553 #define RGPIO_LOCK_PCNS_SHIFT                    (0U)
71554 /*! PCNS - Lock PCNS
71555  *  0b0..PCNS register is writable by software in Secure-Privilege state.
71556  *  0b1..PCNS register is not writable until the next reset.
71557  */
71558 #define RGPIO_LOCK_PCNS(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNS_SHIFT)) & RGPIO_LOCK_PCNS_MASK)
71559 
71560 #define RGPIO_LOCK_ICNS_MASK                     (0x2U)
71561 #define RGPIO_LOCK_ICNS_SHIFT                    (1U)
71562 /*! ICNS - Lock ICNS
71563  *  0b0..ICNS register is writable by software in Secure-Privilege state.
71564  *  0b1..ICNS register is not writable until the next reset.
71565  */
71566 #define RGPIO_LOCK_ICNS(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNS_SHIFT)) & RGPIO_LOCK_ICNS_MASK)
71567 
71568 #define RGPIO_LOCK_PCNP_MASK                     (0x4U)
71569 #define RGPIO_LOCK_PCNP_SHIFT                    (2U)
71570 /*! PCNP - Lock PCNP
71571  *  0b0..PCNP register is writable by software in Secure-Privilege state.
71572  *  0b1..PCNP register is not writable until the next reset.
71573  */
71574 #define RGPIO_LOCK_PCNP(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNP_SHIFT)) & RGPIO_LOCK_PCNP_MASK)
71575 
71576 #define RGPIO_LOCK_ICNP_MASK                     (0x8U)
71577 #define RGPIO_LOCK_ICNP_SHIFT                    (3U)
71578 /*! ICNP - Lock ICNP
71579  *  0b0..ICNP register is writable by software in Secure-Privilege state.
71580  *  0b1..ICNP register is not writable until the next reset.
71581  */
71582 #define RGPIO_LOCK_ICNP(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNP_SHIFT)) & RGPIO_LOCK_ICNP_MASK)
71583 /*! @} */
71584 
71585 /*! @name PCNS - Pin Control Non-Secure */
71586 /*! @{ */
71587 
71588 #define RGPIO_PCNS_NSE0_MASK                     (0x1U)
71589 #define RGPIO_PCNS_NSE0_SHIFT                    (0U)
71590 /*! NSE0 - Non-Secure Enable
71591  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71592  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71593  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71594  *       ignored.
71595  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71596  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71597  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71598  *       ignored.
71599  */
71600 #define RGPIO_PCNS_NSE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE0_SHIFT)) & RGPIO_PCNS_NSE0_MASK)
71601 
71602 #define RGPIO_PCNS_NSE1_MASK                     (0x2U)
71603 #define RGPIO_PCNS_NSE1_SHIFT                    (1U)
71604 /*! NSE1 - Non-Secure Enable
71605  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71606  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71607  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71608  *       ignored.
71609  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71610  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71611  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71612  *       ignored.
71613  */
71614 #define RGPIO_PCNS_NSE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE1_SHIFT)) & RGPIO_PCNS_NSE1_MASK)
71615 
71616 #define RGPIO_PCNS_NSE2_MASK                     (0x4U)
71617 #define RGPIO_PCNS_NSE2_SHIFT                    (2U)
71618 /*! NSE2 - Non-Secure Enable
71619  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71620  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71621  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71622  *       ignored.
71623  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71624  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71625  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71626  *       ignored.
71627  */
71628 #define RGPIO_PCNS_NSE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE2_SHIFT)) & RGPIO_PCNS_NSE2_MASK)
71629 
71630 #define RGPIO_PCNS_NSE3_MASK                     (0x8U)
71631 #define RGPIO_PCNS_NSE3_SHIFT                    (3U)
71632 /*! NSE3 - Non-Secure Enable
71633  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71634  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71635  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71636  *       ignored.
71637  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71638  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71639  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71640  *       ignored.
71641  */
71642 #define RGPIO_PCNS_NSE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE3_SHIFT)) & RGPIO_PCNS_NSE3_MASK)
71643 
71644 #define RGPIO_PCNS_NSE4_MASK                     (0x10U)
71645 #define RGPIO_PCNS_NSE4_SHIFT                    (4U)
71646 /*! NSE4 - Non-Secure Enable
71647  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71648  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71649  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71650  *       ignored.
71651  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71652  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71653  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71654  *       ignored.
71655  */
71656 #define RGPIO_PCNS_NSE4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE4_SHIFT)) & RGPIO_PCNS_NSE4_MASK)
71657 
71658 #define RGPIO_PCNS_NSE5_MASK                     (0x20U)
71659 #define RGPIO_PCNS_NSE5_SHIFT                    (5U)
71660 /*! NSE5 - Non-Secure Enable
71661  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71662  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71663  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71664  *       ignored.
71665  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71666  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71667  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71668  *       ignored.
71669  */
71670 #define RGPIO_PCNS_NSE5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE5_SHIFT)) & RGPIO_PCNS_NSE5_MASK)
71671 
71672 #define RGPIO_PCNS_NSE6_MASK                     (0x40U)
71673 #define RGPIO_PCNS_NSE6_SHIFT                    (6U)
71674 /*! NSE6 - Non-Secure Enable
71675  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71676  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71677  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71678  *       ignored.
71679  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71680  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71681  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71682  *       ignored.
71683  */
71684 #define RGPIO_PCNS_NSE6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE6_SHIFT)) & RGPIO_PCNS_NSE6_MASK)
71685 
71686 #define RGPIO_PCNS_NSE7_MASK                     (0x80U)
71687 #define RGPIO_PCNS_NSE7_SHIFT                    (7U)
71688 /*! NSE7 - Non-Secure Enable
71689  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71690  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71691  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71692  *       ignored.
71693  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71694  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71695  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71696  *       ignored.
71697  */
71698 #define RGPIO_PCNS_NSE7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE7_SHIFT)) & RGPIO_PCNS_NSE7_MASK)
71699 
71700 #define RGPIO_PCNS_NSE8_MASK                     (0x100U)
71701 #define RGPIO_PCNS_NSE8_SHIFT                    (8U)
71702 /*! NSE8 - Non-Secure Enable
71703  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71704  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71705  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71706  *       ignored.
71707  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71708  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71709  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71710  *       ignored.
71711  */
71712 #define RGPIO_PCNS_NSE8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE8_SHIFT)) & RGPIO_PCNS_NSE8_MASK)
71713 
71714 #define RGPIO_PCNS_NSE9_MASK                     (0x200U)
71715 #define RGPIO_PCNS_NSE9_SHIFT                    (9U)
71716 /*! NSE9 - Non-Secure Enable
71717  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71718  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71719  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71720  *       ignored.
71721  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71722  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71723  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71724  *       ignored.
71725  */
71726 #define RGPIO_PCNS_NSE9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE9_SHIFT)) & RGPIO_PCNS_NSE9_MASK)
71727 
71728 #define RGPIO_PCNS_NSE10_MASK                    (0x400U)
71729 #define RGPIO_PCNS_NSE10_SHIFT                   (10U)
71730 /*! NSE10 - Non-Secure Enable
71731  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71732  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71733  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71734  *       ignored.
71735  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71736  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71737  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71738  *       ignored.
71739  */
71740 #define RGPIO_PCNS_NSE10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE10_SHIFT)) & RGPIO_PCNS_NSE10_MASK)
71741 
71742 #define RGPIO_PCNS_NSE11_MASK                    (0x800U)
71743 #define RGPIO_PCNS_NSE11_SHIFT                   (11U)
71744 /*! NSE11 - Non-Secure Enable
71745  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71746  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71747  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71748  *       ignored.
71749  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71750  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71751  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71752  *       ignored.
71753  */
71754 #define RGPIO_PCNS_NSE11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE11_SHIFT)) & RGPIO_PCNS_NSE11_MASK)
71755 
71756 #define RGPIO_PCNS_NSE12_MASK                    (0x1000U)
71757 #define RGPIO_PCNS_NSE12_SHIFT                   (12U)
71758 /*! NSE12 - Non-Secure Enable
71759  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71760  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71761  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71762  *       ignored.
71763  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71764  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71765  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71766  *       ignored.
71767  */
71768 #define RGPIO_PCNS_NSE12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE12_SHIFT)) & RGPIO_PCNS_NSE12_MASK)
71769 
71770 #define RGPIO_PCNS_NSE13_MASK                    (0x2000U)
71771 #define RGPIO_PCNS_NSE13_SHIFT                   (13U)
71772 /*! NSE13 - Non-Secure Enable
71773  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71774  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71775  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71776  *       ignored.
71777  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71778  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71779  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71780  *       ignored.
71781  */
71782 #define RGPIO_PCNS_NSE13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE13_SHIFT)) & RGPIO_PCNS_NSE13_MASK)
71783 
71784 #define RGPIO_PCNS_NSE14_MASK                    (0x4000U)
71785 #define RGPIO_PCNS_NSE14_SHIFT                   (14U)
71786 /*! NSE14 - Non-Secure Enable
71787  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71788  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71789  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71790  *       ignored.
71791  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71792  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71793  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71794  *       ignored.
71795  */
71796 #define RGPIO_PCNS_NSE14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE14_SHIFT)) & RGPIO_PCNS_NSE14_MASK)
71797 
71798 #define RGPIO_PCNS_NSE15_MASK                    (0x8000U)
71799 #define RGPIO_PCNS_NSE15_SHIFT                   (15U)
71800 /*! NSE15 - Non-Secure Enable
71801  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71802  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71803  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71804  *       ignored.
71805  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71806  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71807  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71808  *       ignored.
71809  */
71810 #define RGPIO_PCNS_NSE15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE15_SHIFT)) & RGPIO_PCNS_NSE15_MASK)
71811 
71812 #define RGPIO_PCNS_NSE16_MASK                    (0x10000U)
71813 #define RGPIO_PCNS_NSE16_SHIFT                   (16U)
71814 /*! NSE16 - Non-Secure Enable
71815  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71816  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71817  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71818  *       ignored.
71819  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71820  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71821  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71822  *       ignored.
71823  */
71824 #define RGPIO_PCNS_NSE16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE16_SHIFT)) & RGPIO_PCNS_NSE16_MASK)
71825 
71826 #define RGPIO_PCNS_NSE17_MASK                    (0x20000U)
71827 #define RGPIO_PCNS_NSE17_SHIFT                   (17U)
71828 /*! NSE17 - Non-Secure Enable
71829  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71830  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71831  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71832  *       ignored.
71833  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71834  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71835  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71836  *       ignored.
71837  */
71838 #define RGPIO_PCNS_NSE17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE17_SHIFT)) & RGPIO_PCNS_NSE17_MASK)
71839 
71840 #define RGPIO_PCNS_NSE18_MASK                    (0x40000U)
71841 #define RGPIO_PCNS_NSE18_SHIFT                   (18U)
71842 /*! NSE18 - Non-Secure Enable
71843  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71844  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71845  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71846  *       ignored.
71847  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71848  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71849  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71850  *       ignored.
71851  */
71852 #define RGPIO_PCNS_NSE18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE18_SHIFT)) & RGPIO_PCNS_NSE18_MASK)
71853 
71854 #define RGPIO_PCNS_NSE19_MASK                    (0x80000U)
71855 #define RGPIO_PCNS_NSE19_SHIFT                   (19U)
71856 /*! NSE19 - Non-Secure Enable
71857  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71858  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71859  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71860  *       ignored.
71861  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71862  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71863  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71864  *       ignored.
71865  */
71866 #define RGPIO_PCNS_NSE19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE19_SHIFT)) & RGPIO_PCNS_NSE19_MASK)
71867 
71868 #define RGPIO_PCNS_NSE20_MASK                    (0x100000U)
71869 #define RGPIO_PCNS_NSE20_SHIFT                   (20U)
71870 /*! NSE20 - Non-Secure Enable
71871  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71872  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71873  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71874  *       ignored.
71875  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71876  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71877  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71878  *       ignored.
71879  */
71880 #define RGPIO_PCNS_NSE20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE20_SHIFT)) & RGPIO_PCNS_NSE20_MASK)
71881 
71882 #define RGPIO_PCNS_NSE21_MASK                    (0x200000U)
71883 #define RGPIO_PCNS_NSE21_SHIFT                   (21U)
71884 /*! NSE21 - Non-Secure Enable
71885  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71886  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71887  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71888  *       ignored.
71889  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71890  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71891  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71892  *       ignored.
71893  */
71894 #define RGPIO_PCNS_NSE21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE21_SHIFT)) & RGPIO_PCNS_NSE21_MASK)
71895 
71896 #define RGPIO_PCNS_NSE22_MASK                    (0x400000U)
71897 #define RGPIO_PCNS_NSE22_SHIFT                   (22U)
71898 /*! NSE22 - Non-Secure Enable
71899  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71900  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71901  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71902  *       ignored.
71903  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71904  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71905  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71906  *       ignored.
71907  */
71908 #define RGPIO_PCNS_NSE22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE22_SHIFT)) & RGPIO_PCNS_NSE22_MASK)
71909 
71910 #define RGPIO_PCNS_NSE23_MASK                    (0x800000U)
71911 #define RGPIO_PCNS_NSE23_SHIFT                   (23U)
71912 /*! NSE23 - Non-Secure Enable
71913  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71914  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71915  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71916  *       ignored.
71917  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71918  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71919  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71920  *       ignored.
71921  */
71922 #define RGPIO_PCNS_NSE23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE23_SHIFT)) & RGPIO_PCNS_NSE23_MASK)
71923 
71924 #define RGPIO_PCNS_NSE24_MASK                    (0x1000000U)
71925 #define RGPIO_PCNS_NSE24_SHIFT                   (24U)
71926 /*! NSE24 - Non-Secure Enable
71927  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71928  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71929  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71930  *       ignored.
71931  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71932  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71933  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71934  *       ignored.
71935  */
71936 #define RGPIO_PCNS_NSE24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE24_SHIFT)) & RGPIO_PCNS_NSE24_MASK)
71937 
71938 #define RGPIO_PCNS_NSE25_MASK                    (0x2000000U)
71939 #define RGPIO_PCNS_NSE25_SHIFT                   (25U)
71940 /*! NSE25 - Non-Secure Enable
71941  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71942  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71943  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71944  *       ignored.
71945  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71946  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71947  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71948  *       ignored.
71949  */
71950 #define RGPIO_PCNS_NSE25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE25_SHIFT)) & RGPIO_PCNS_NSE25_MASK)
71951 
71952 #define RGPIO_PCNS_NSE26_MASK                    (0x4000000U)
71953 #define RGPIO_PCNS_NSE26_SHIFT                   (26U)
71954 /*! NSE26 - Non-Secure Enable
71955  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71956  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71957  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71958  *       ignored.
71959  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71960  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71961  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71962  *       ignored.
71963  */
71964 #define RGPIO_PCNS_NSE26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE26_SHIFT)) & RGPIO_PCNS_NSE26_MASK)
71965 
71966 #define RGPIO_PCNS_NSE27_MASK                    (0x8000000U)
71967 #define RGPIO_PCNS_NSE27_SHIFT                   (27U)
71968 /*! NSE27 - Non-Secure Enable
71969  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71970  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71971  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71972  *       ignored.
71973  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71974  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71975  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71976  *       ignored.
71977  */
71978 #define RGPIO_PCNS_NSE27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE27_SHIFT)) & RGPIO_PCNS_NSE27_MASK)
71979 
71980 #define RGPIO_PCNS_NSE28_MASK                    (0x10000000U)
71981 #define RGPIO_PCNS_NSE28_SHIFT                   (28U)
71982 /*! NSE28 - Non-Secure Enable
71983  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71984  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71985  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
71986  *       ignored.
71987  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
71988  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
71989  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
71990  *       ignored.
71991  */
71992 #define RGPIO_PCNS_NSE28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE28_SHIFT)) & RGPIO_PCNS_NSE28_MASK)
71993 
71994 #define RGPIO_PCNS_NSE29_MASK                    (0x20000000U)
71995 #define RGPIO_PCNS_NSE29_SHIFT                   (29U)
71996 /*! NSE29 - Non-Secure Enable
71997  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
71998  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
71999  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
72000  *       ignored.
72001  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
72002  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
72003  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
72004  *       ignored.
72005  */
72006 #define RGPIO_PCNS_NSE29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE29_SHIFT)) & RGPIO_PCNS_NSE29_MASK)
72007 
72008 #define RGPIO_PCNS_NSE30_MASK                    (0x40000000U)
72009 #define RGPIO_PCNS_NSE30_SHIFT                   (30U)
72010 /*! NSE30 - Non-Secure Enable
72011  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
72012  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
72013  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
72014  *       ignored.
72015  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
72016  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
72017  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
72018  *       ignored.
72019  */
72020 #define RGPIO_PCNS_NSE30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE30_SHIFT)) & RGPIO_PCNS_NSE30_MASK)
72021 
72022 #define RGPIO_PCNS_NSE31_MASK                    (0x80000000U)
72023 #define RGPIO_PCNS_NSE31_SHIFT                   (31U)
72024 /*! NSE31 - Non-Secure Enable
72025  *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
72026  *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
72027  *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
72028  *       ignored.
72029  *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
72030  *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
72031  *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
72032  *       ignored.
72033  */
72034 #define RGPIO_PCNS_NSE31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE31_SHIFT)) & RGPIO_PCNS_NSE31_MASK)
72035 /*! @} */
72036 
72037 /*! @name ICNS - Interrupt Control Non-Secure */
72038 /*! @{ */
72039 
72040 #define RGPIO_ICNS_NSE0_MASK                     (0x1U)
72041 #define RGPIO_ICNS_NSE0_SHIFT                    (0U)
72042 /*! NSE0 - Non-Secure Enable
72043  *  0b0..The interrupt or DMA request is configured for Secure access. Only software in Secure state can configure
72044  *       a pin to use the corresponding interrupt or DMA request or reconfigure a pin that is already configured
72045  *       to use the corresponding interrupt or DMA request.
72046  *  0b1..The interrupt or DMA request is configured for Non-Secure access. Only software in Non-Secure state can
72047  *       configure a pin to use the corresponding interrupt or DMA request or reconfigure a pin that is already
72048  *       configured to use the corresponding interrupt or DMA request.
72049  */
72050 #define RGPIO_ICNS_NSE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE0_SHIFT)) & RGPIO_ICNS_NSE0_MASK)
72051 
72052 #define RGPIO_ICNS_NSE1_MASK                     (0x2U)
72053 #define RGPIO_ICNS_NSE1_SHIFT                    (1U)
72054 /*! NSE1 - Non-Secure Enable
72055  *  0b0..The interrupt or DMA request is configured for Secure access. Only software in Secure state can configure
72056  *       a pin to use the corresponding interrupt or DMA request or reconfigure a pin that is already configured
72057  *       to use the corresponding interrupt or DMA request.
72058  *  0b1..The interrupt or DMA request is configured for Non-Secure access. Only software in Non-Secure state can
72059  *       configure a pin to use the corresponding interrupt or DMA request or reconfigure a pin that is already
72060  *       configured to use the corresponding interrupt or DMA request.
72061  */
72062 #define RGPIO_ICNS_NSE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE1_SHIFT)) & RGPIO_ICNS_NSE1_MASK)
72063 /*! @} */
72064 
72065 /*! @name PCNP - Pin Control Non-Privilege */
72066 /*! @{ */
72067 
72068 #define RGPIO_PCNP_NPE0_MASK                     (0x1U)
72069 #define RGPIO_PCNP_NPE0_SHIFT                    (0U)
72070 /*! NPE0 - Non-Privilege Enable
72071  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72072  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72073  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72074  *       but write ignored.
72075  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72076  *       is allowed by software in both Privilege and Non-Privilege state.
72077  */
72078 #define RGPIO_PCNP_NPE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE0_SHIFT)) & RGPIO_PCNP_NPE0_MASK)
72079 
72080 #define RGPIO_PCNP_NPE1_MASK                     (0x2U)
72081 #define RGPIO_PCNP_NPE1_SHIFT                    (1U)
72082 /*! NPE1 - Non-Privilege Enable
72083  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72084  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72085  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72086  *       but write ignored.
72087  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72088  *       is allowed by software in both Privilege and Non-Privilege state.
72089  */
72090 #define RGPIO_PCNP_NPE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE1_SHIFT)) & RGPIO_PCNP_NPE1_MASK)
72091 
72092 #define RGPIO_PCNP_NPE2_MASK                     (0x4U)
72093 #define RGPIO_PCNP_NPE2_SHIFT                    (2U)
72094 /*! NPE2 - Non-Privilege Enable
72095  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72096  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72097  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72098  *       but write ignored.
72099  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72100  *       is allowed by software in both Privilege and Non-Privilege state.
72101  */
72102 #define RGPIO_PCNP_NPE2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE2_SHIFT)) & RGPIO_PCNP_NPE2_MASK)
72103 
72104 #define RGPIO_PCNP_NPE3_MASK                     (0x8U)
72105 #define RGPIO_PCNP_NPE3_SHIFT                    (3U)
72106 /*! NPE3 - Non-Privilege Enable
72107  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72108  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72109  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72110  *       but write ignored.
72111  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72112  *       is allowed by software in both Privilege and Non-Privilege state.
72113  */
72114 #define RGPIO_PCNP_NPE3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE3_SHIFT)) & RGPIO_PCNP_NPE3_MASK)
72115 
72116 #define RGPIO_PCNP_NPE4_MASK                     (0x10U)
72117 #define RGPIO_PCNP_NPE4_SHIFT                    (4U)
72118 /*! NPE4 - Non-Privilege Enable
72119  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72120  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72121  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72122  *       but write ignored.
72123  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72124  *       is allowed by software in both Privilege and Non-Privilege state.
72125  */
72126 #define RGPIO_PCNP_NPE4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE4_SHIFT)) & RGPIO_PCNP_NPE4_MASK)
72127 
72128 #define RGPIO_PCNP_NPE5_MASK                     (0x20U)
72129 #define RGPIO_PCNP_NPE5_SHIFT                    (5U)
72130 /*! NPE5 - Non-Privilege Enable
72131  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72132  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72133  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72134  *       but write ignored.
72135  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72136  *       is allowed by software in both Privilege and Non-Privilege state.
72137  */
72138 #define RGPIO_PCNP_NPE5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE5_SHIFT)) & RGPIO_PCNP_NPE5_MASK)
72139 
72140 #define RGPIO_PCNP_NPE6_MASK                     (0x40U)
72141 #define RGPIO_PCNP_NPE6_SHIFT                    (6U)
72142 /*! NPE6 - Non-Privilege Enable
72143  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72144  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72145  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72146  *       but write ignored.
72147  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72148  *       is allowed by software in both Privilege and Non-Privilege state.
72149  */
72150 #define RGPIO_PCNP_NPE6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE6_SHIFT)) & RGPIO_PCNP_NPE6_MASK)
72151 
72152 #define RGPIO_PCNP_NPE7_MASK                     (0x80U)
72153 #define RGPIO_PCNP_NPE7_SHIFT                    (7U)
72154 /*! NPE7 - Non-Privilege Enable
72155  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72156  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72157  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72158  *       but write ignored.
72159  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72160  *       is allowed by software in both Privilege and Non-Privilege state.
72161  */
72162 #define RGPIO_PCNP_NPE7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE7_SHIFT)) & RGPIO_PCNP_NPE7_MASK)
72163 
72164 #define RGPIO_PCNP_NPE8_MASK                     (0x100U)
72165 #define RGPIO_PCNP_NPE8_SHIFT                    (8U)
72166 /*! NPE8 - Non-Privilege Enable
72167  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72168  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72169  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72170  *       but write ignored.
72171  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72172  *       is allowed by software in both Privilege and Non-Privilege state.
72173  */
72174 #define RGPIO_PCNP_NPE8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE8_SHIFT)) & RGPIO_PCNP_NPE8_MASK)
72175 
72176 #define RGPIO_PCNP_NPE9_MASK                     (0x200U)
72177 #define RGPIO_PCNP_NPE9_SHIFT                    (9U)
72178 /*! NPE9 - Non-Privilege Enable
72179  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72180  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72181  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72182  *       but write ignored.
72183  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72184  *       is allowed by software in both Privilege and Non-Privilege state.
72185  */
72186 #define RGPIO_PCNP_NPE9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE9_SHIFT)) & RGPIO_PCNP_NPE9_MASK)
72187 
72188 #define RGPIO_PCNP_NPE10_MASK                    (0x400U)
72189 #define RGPIO_PCNP_NPE10_SHIFT                   (10U)
72190 /*! NPE10 - Non-Privilege Enable
72191  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72192  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72193  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72194  *       but write ignored.
72195  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72196  *       is allowed by software in both Privilege and Non-Privilege state.
72197  */
72198 #define RGPIO_PCNP_NPE10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE10_SHIFT)) & RGPIO_PCNP_NPE10_MASK)
72199 
72200 #define RGPIO_PCNP_NPE11_MASK                    (0x800U)
72201 #define RGPIO_PCNP_NPE11_SHIFT                   (11U)
72202 /*! NPE11 - Non-Privilege Enable
72203  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72204  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72205  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72206  *       but write ignored.
72207  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72208  *       is allowed by software in both Privilege and Non-Privilege state.
72209  */
72210 #define RGPIO_PCNP_NPE11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE11_SHIFT)) & RGPIO_PCNP_NPE11_MASK)
72211 
72212 #define RGPIO_PCNP_NPE12_MASK                    (0x1000U)
72213 #define RGPIO_PCNP_NPE12_SHIFT                   (12U)
72214 /*! NPE12 - Non-Privilege Enable
72215  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72216  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72217  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72218  *       but write ignored.
72219  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72220  *       is allowed by software in both Privilege and Non-Privilege state.
72221  */
72222 #define RGPIO_PCNP_NPE12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE12_SHIFT)) & RGPIO_PCNP_NPE12_MASK)
72223 
72224 #define RGPIO_PCNP_NPE13_MASK                    (0x2000U)
72225 #define RGPIO_PCNP_NPE13_SHIFT                   (13U)
72226 /*! NPE13 - Non-Privilege Enable
72227  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72228  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72229  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72230  *       but write ignored.
72231  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72232  *       is allowed by software in both Privilege and Non-Privilege state.
72233  */
72234 #define RGPIO_PCNP_NPE13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE13_SHIFT)) & RGPIO_PCNP_NPE13_MASK)
72235 
72236 #define RGPIO_PCNP_NPE14_MASK                    (0x4000U)
72237 #define RGPIO_PCNP_NPE14_SHIFT                   (14U)
72238 /*! NPE14 - Non-Privilege Enable
72239  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72240  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72241  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72242  *       but write ignored.
72243  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72244  *       is allowed by software in both Privilege and Non-Privilege state.
72245  */
72246 #define RGPIO_PCNP_NPE14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE14_SHIFT)) & RGPIO_PCNP_NPE14_MASK)
72247 
72248 #define RGPIO_PCNP_NPE15_MASK                    (0x8000U)
72249 #define RGPIO_PCNP_NPE15_SHIFT                   (15U)
72250 /*! NPE15 - Non-Privilege Enable
72251  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72252  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72253  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72254  *       but write ignored.
72255  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72256  *       is allowed by software in both Privilege and Non-Privilege state.
72257  */
72258 #define RGPIO_PCNP_NPE15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE15_SHIFT)) & RGPIO_PCNP_NPE15_MASK)
72259 
72260 #define RGPIO_PCNP_NPE16_MASK                    (0x10000U)
72261 #define RGPIO_PCNP_NPE16_SHIFT                   (16U)
72262 /*! NPE16 - Non-Privilege Enable
72263  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72264  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72265  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72266  *       but write ignored.
72267  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72268  *       is allowed by software in both Privilege and Non-Privilege state.
72269  */
72270 #define RGPIO_PCNP_NPE16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE16_SHIFT)) & RGPIO_PCNP_NPE16_MASK)
72271 
72272 #define RGPIO_PCNP_NPE17_MASK                    (0x20000U)
72273 #define RGPIO_PCNP_NPE17_SHIFT                   (17U)
72274 /*! NPE17 - Non-Privilege Enable
72275  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72276  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72277  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72278  *       but write ignored.
72279  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72280  *       is allowed by software in both Privilege and Non-Privilege state.
72281  */
72282 #define RGPIO_PCNP_NPE17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE17_SHIFT)) & RGPIO_PCNP_NPE17_MASK)
72283 
72284 #define RGPIO_PCNP_NPE18_MASK                    (0x40000U)
72285 #define RGPIO_PCNP_NPE18_SHIFT                   (18U)
72286 /*! NPE18 - Non-Privilege Enable
72287  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72288  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72289  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72290  *       but write ignored.
72291  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72292  *       is allowed by software in both Privilege and Non-Privilege state.
72293  */
72294 #define RGPIO_PCNP_NPE18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE18_SHIFT)) & RGPIO_PCNP_NPE18_MASK)
72295 
72296 #define RGPIO_PCNP_NPE19_MASK                    (0x80000U)
72297 #define RGPIO_PCNP_NPE19_SHIFT                   (19U)
72298 /*! NPE19 - Non-Privilege Enable
72299  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72300  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72301  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72302  *       but write ignored.
72303  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72304  *       is allowed by software in both Privilege and Non-Privilege state.
72305  */
72306 #define RGPIO_PCNP_NPE19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE19_SHIFT)) & RGPIO_PCNP_NPE19_MASK)
72307 
72308 #define RGPIO_PCNP_NPE20_MASK                    (0x100000U)
72309 #define RGPIO_PCNP_NPE20_SHIFT                   (20U)
72310 /*! NPE20 - Non-Privilege Enable
72311  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72312  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72313  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72314  *       but write ignored.
72315  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72316  *       is allowed by software in both Privilege and Non-Privilege state.
72317  */
72318 #define RGPIO_PCNP_NPE20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE20_SHIFT)) & RGPIO_PCNP_NPE20_MASK)
72319 
72320 #define RGPIO_PCNP_NPE21_MASK                    (0x200000U)
72321 #define RGPIO_PCNP_NPE21_SHIFT                   (21U)
72322 /*! NPE21 - Non-Privilege Enable
72323  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72324  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72325  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72326  *       but write ignored.
72327  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72328  *       is allowed by software in both Privilege and Non-Privilege state.
72329  */
72330 #define RGPIO_PCNP_NPE21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE21_SHIFT)) & RGPIO_PCNP_NPE21_MASK)
72331 
72332 #define RGPIO_PCNP_NPE22_MASK                    (0x400000U)
72333 #define RGPIO_PCNP_NPE22_SHIFT                   (22U)
72334 /*! NPE22 - Non-Privilege Enable
72335  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72336  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72337  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72338  *       but write ignored.
72339  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72340  *       is allowed by software in both Privilege and Non-Privilege state.
72341  */
72342 #define RGPIO_PCNP_NPE22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE22_SHIFT)) & RGPIO_PCNP_NPE22_MASK)
72343 
72344 #define RGPIO_PCNP_NPE23_MASK                    (0x800000U)
72345 #define RGPIO_PCNP_NPE23_SHIFT                   (23U)
72346 /*! NPE23 - Non-Privilege Enable
72347  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72348  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72349  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72350  *       but write ignored.
72351  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72352  *       is allowed by software in both Privilege and Non-Privilege state.
72353  */
72354 #define RGPIO_PCNP_NPE23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE23_SHIFT)) & RGPIO_PCNP_NPE23_MASK)
72355 
72356 #define RGPIO_PCNP_NPE24_MASK                    (0x1000000U)
72357 #define RGPIO_PCNP_NPE24_SHIFT                   (24U)
72358 /*! NPE24 - Non-Privilege Enable
72359  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72360  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72361  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72362  *       but write ignored.
72363  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72364  *       is allowed by software in both Privilege and Non-Privilege state.
72365  */
72366 #define RGPIO_PCNP_NPE24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE24_SHIFT)) & RGPIO_PCNP_NPE24_MASK)
72367 
72368 #define RGPIO_PCNP_NPE25_MASK                    (0x2000000U)
72369 #define RGPIO_PCNP_NPE25_SHIFT                   (25U)
72370 /*! NPE25 - Non-Privilege Enable
72371  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72372  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72373  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72374  *       but write ignored.
72375  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72376  *       is allowed by software in both Privilege and Non-Privilege state.
72377  */
72378 #define RGPIO_PCNP_NPE25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE25_SHIFT)) & RGPIO_PCNP_NPE25_MASK)
72379 
72380 #define RGPIO_PCNP_NPE26_MASK                    (0x4000000U)
72381 #define RGPIO_PCNP_NPE26_SHIFT                   (26U)
72382 /*! NPE26 - Non-Privilege Enable
72383  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72384  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72385  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72386  *       but write ignored.
72387  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72388  *       is allowed by software in both Privilege and Non-Privilege state.
72389  */
72390 #define RGPIO_PCNP_NPE26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE26_SHIFT)) & RGPIO_PCNP_NPE26_MASK)
72391 
72392 #define RGPIO_PCNP_NPE27_MASK                    (0x8000000U)
72393 #define RGPIO_PCNP_NPE27_SHIFT                   (27U)
72394 /*! NPE27 - Non-Privilege Enable
72395  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72396  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72397  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72398  *       but write ignored.
72399  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72400  *       is allowed by software in both Privilege and Non-Privilege state.
72401  */
72402 #define RGPIO_PCNP_NPE27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE27_SHIFT)) & RGPIO_PCNP_NPE27_MASK)
72403 
72404 #define RGPIO_PCNP_NPE28_MASK                    (0x10000000U)
72405 #define RGPIO_PCNP_NPE28_SHIFT                   (28U)
72406 /*! NPE28 - Non-Privilege Enable
72407  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72408  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72409  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72410  *       but write ignored.
72411  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72412  *       is allowed by software in both Privilege and Non-Privilege state.
72413  */
72414 #define RGPIO_PCNP_NPE28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE28_SHIFT)) & RGPIO_PCNP_NPE28_MASK)
72415 
72416 #define RGPIO_PCNP_NPE29_MASK                    (0x20000000U)
72417 #define RGPIO_PCNP_NPE29_SHIFT                   (29U)
72418 /*! NPE29 - Non-Privilege Enable
72419  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72420  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72421  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72422  *       but write ignored.
72423  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72424  *       is allowed by software in both Privilege and Non-Privilege state.
72425  */
72426 #define RGPIO_PCNP_NPE29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE29_SHIFT)) & RGPIO_PCNP_NPE29_MASK)
72427 
72428 #define RGPIO_PCNP_NPE30_MASK                    (0x40000000U)
72429 #define RGPIO_PCNP_NPE30_SHIFT                   (30U)
72430 /*! NPE30 - Non-Privilege Enable
72431  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72432  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72433  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72434  *       but write ignored.
72435  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72436  *       is allowed by software in both Privilege and Non-Privilege state.
72437  */
72438 #define RGPIO_PCNP_NPE30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE30_SHIFT)) & RGPIO_PCNP_NPE30_MASK)
72439 
72440 #define RGPIO_PCNP_NPE31_MASK                    (0x80000000U)
72441 #define RGPIO_PCNP_NPE31_SHIFT                   (31U)
72442 /*! NPE31 - Non-Privilege Enable
72443  *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
72444  *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
72445  *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
72446  *       but write ignored.
72447  *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
72448  *       is allowed by software in both Privilege and Non-Privilege state.
72449  */
72450 #define RGPIO_PCNP_NPE31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE31_SHIFT)) & RGPIO_PCNP_NPE31_MASK)
72451 /*! @} */
72452 
72453 /*! @name ICNP - Interrupt Control Non-Privilege */
72454 /*! @{ */
72455 
72456 #define RGPIO_ICNP_NPE0_MASK                     (0x1U)
72457 #define RGPIO_ICNP_NPE0_SHIFT                    (0U)
72458 /*! NPE0 - Non-Privilege Enable
72459  *  0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use
72460  *       the corresponding interrupt/DMA request or reconfigure a pin that is already configured to use the
72461  *       corresponding interrupt/DMA request.
72462  *  0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can
72463  *       configure a pin to use the corresponding interrupt/DMA request or reconfigure a pin that is already
72464  *       configured to use the corresponding interrupt/DMA request.
72465  */
72466 #define RGPIO_ICNP_NPE0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE0_SHIFT)) & RGPIO_ICNP_NPE0_MASK)
72467 
72468 #define RGPIO_ICNP_NPE1_MASK                     (0x2U)
72469 #define RGPIO_ICNP_NPE1_SHIFT                    (1U)
72470 /*! NPE1 - Non-Privilege Enable
72471  *  0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use
72472  *       the corresponding interrupt/DMA request or reconfigure a pin that is already configured to use the
72473  *       corresponding interrupt/DMA request.
72474  *  0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can
72475  *       configure a pin to use the corresponding interrupt/DMA request or reconfigure a pin that is already
72476  *       configured to use the corresponding interrupt/DMA request.
72477  */
72478 #define RGPIO_ICNP_NPE1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE1_SHIFT)) & RGPIO_ICNP_NPE1_MASK)
72479 /*! @} */
72480 
72481 /*! @name PDOR - Port Data Output Register */
72482 /*! @{ */
72483 
72484 #define RGPIO_PDOR_PDO0_MASK                     (0x1U)
72485 #define RGPIO_PDOR_PDO0_SHIFT                    (0U)
72486 /*! PDO0 - Port Data Output
72487  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72488  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72489  */
72490 #define RGPIO_PDOR_PDO0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO0_SHIFT)) & RGPIO_PDOR_PDO0_MASK)
72491 
72492 #define RGPIO_PDOR_PDO1_MASK                     (0x2U)
72493 #define RGPIO_PDOR_PDO1_SHIFT                    (1U)
72494 /*! PDO1 - Port Data Output
72495  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72496  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72497  */
72498 #define RGPIO_PDOR_PDO1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO1_SHIFT)) & RGPIO_PDOR_PDO1_MASK)
72499 
72500 #define RGPIO_PDOR_PDO2_MASK                     (0x4U)
72501 #define RGPIO_PDOR_PDO2_SHIFT                    (2U)
72502 /*! PDO2 - Port Data Output
72503  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72504  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72505  */
72506 #define RGPIO_PDOR_PDO2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO2_SHIFT)) & RGPIO_PDOR_PDO2_MASK)
72507 
72508 #define RGPIO_PDOR_PDO3_MASK                     (0x8U)
72509 #define RGPIO_PDOR_PDO3_SHIFT                    (3U)
72510 /*! PDO3 - Port Data Output
72511  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72512  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72513  */
72514 #define RGPIO_PDOR_PDO3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO3_SHIFT)) & RGPIO_PDOR_PDO3_MASK)
72515 
72516 #define RGPIO_PDOR_PDO4_MASK                     (0x10U)
72517 #define RGPIO_PDOR_PDO4_SHIFT                    (4U)
72518 /*! PDO4 - Port Data Output
72519  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72520  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72521  */
72522 #define RGPIO_PDOR_PDO4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO4_SHIFT)) & RGPIO_PDOR_PDO4_MASK)
72523 
72524 #define RGPIO_PDOR_PDO5_MASK                     (0x20U)
72525 #define RGPIO_PDOR_PDO5_SHIFT                    (5U)
72526 /*! PDO5 - Port Data Output
72527  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72528  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72529  */
72530 #define RGPIO_PDOR_PDO5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO5_SHIFT)) & RGPIO_PDOR_PDO5_MASK)
72531 
72532 #define RGPIO_PDOR_PDO6_MASK                     (0x40U)
72533 #define RGPIO_PDOR_PDO6_SHIFT                    (6U)
72534 /*! PDO6 - Port Data Output
72535  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72536  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72537  */
72538 #define RGPIO_PDOR_PDO6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO6_SHIFT)) & RGPIO_PDOR_PDO6_MASK)
72539 
72540 #define RGPIO_PDOR_PDO7_MASK                     (0x80U)
72541 #define RGPIO_PDOR_PDO7_SHIFT                    (7U)
72542 /*! PDO7 - Port Data Output
72543  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72544  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72545  */
72546 #define RGPIO_PDOR_PDO7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO7_SHIFT)) & RGPIO_PDOR_PDO7_MASK)
72547 
72548 #define RGPIO_PDOR_PDO8_MASK                     (0x100U)
72549 #define RGPIO_PDOR_PDO8_SHIFT                    (8U)
72550 /*! PDO8 - Port Data Output
72551  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72552  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72553  */
72554 #define RGPIO_PDOR_PDO8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO8_SHIFT)) & RGPIO_PDOR_PDO8_MASK)
72555 
72556 #define RGPIO_PDOR_PDO9_MASK                     (0x200U)
72557 #define RGPIO_PDOR_PDO9_SHIFT                    (9U)
72558 /*! PDO9 - Port Data Output
72559  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72560  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72561  */
72562 #define RGPIO_PDOR_PDO9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO9_SHIFT)) & RGPIO_PDOR_PDO9_MASK)
72563 
72564 #define RGPIO_PDOR_PDO10_MASK                    (0x400U)
72565 #define RGPIO_PDOR_PDO10_SHIFT                   (10U)
72566 /*! PDO10 - Port Data Output
72567  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72568  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72569  */
72570 #define RGPIO_PDOR_PDO10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO10_SHIFT)) & RGPIO_PDOR_PDO10_MASK)
72571 
72572 #define RGPIO_PDOR_PDO11_MASK                    (0x800U)
72573 #define RGPIO_PDOR_PDO11_SHIFT                   (11U)
72574 /*! PDO11 - Port Data Output
72575  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72576  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72577  */
72578 #define RGPIO_PDOR_PDO11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO11_SHIFT)) & RGPIO_PDOR_PDO11_MASK)
72579 
72580 #define RGPIO_PDOR_PDO12_MASK                    (0x1000U)
72581 #define RGPIO_PDOR_PDO12_SHIFT                   (12U)
72582 /*! PDO12 - Port Data Output
72583  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72584  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72585  */
72586 #define RGPIO_PDOR_PDO12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO12_SHIFT)) & RGPIO_PDOR_PDO12_MASK)
72587 
72588 #define RGPIO_PDOR_PDO13_MASK                    (0x2000U)
72589 #define RGPIO_PDOR_PDO13_SHIFT                   (13U)
72590 /*! PDO13 - Port Data Output
72591  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72592  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72593  */
72594 #define RGPIO_PDOR_PDO13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO13_SHIFT)) & RGPIO_PDOR_PDO13_MASK)
72595 
72596 #define RGPIO_PDOR_PDO14_MASK                    (0x4000U)
72597 #define RGPIO_PDOR_PDO14_SHIFT                   (14U)
72598 /*! PDO14 - Port Data Output
72599  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72600  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72601  */
72602 #define RGPIO_PDOR_PDO14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO14_SHIFT)) & RGPIO_PDOR_PDO14_MASK)
72603 
72604 #define RGPIO_PDOR_PDO15_MASK                    (0x8000U)
72605 #define RGPIO_PDOR_PDO15_SHIFT                   (15U)
72606 /*! PDO15 - Port Data Output
72607  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72608  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72609  */
72610 #define RGPIO_PDOR_PDO15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO15_SHIFT)) & RGPIO_PDOR_PDO15_MASK)
72611 
72612 #define RGPIO_PDOR_PDO16_MASK                    (0x10000U)
72613 #define RGPIO_PDOR_PDO16_SHIFT                   (16U)
72614 /*! PDO16 - Port Data Output
72615  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72616  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72617  */
72618 #define RGPIO_PDOR_PDO16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO16_SHIFT)) & RGPIO_PDOR_PDO16_MASK)
72619 
72620 #define RGPIO_PDOR_PDO17_MASK                    (0x20000U)
72621 #define RGPIO_PDOR_PDO17_SHIFT                   (17U)
72622 /*! PDO17 - Port Data Output
72623  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72624  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72625  */
72626 #define RGPIO_PDOR_PDO17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO17_SHIFT)) & RGPIO_PDOR_PDO17_MASK)
72627 
72628 #define RGPIO_PDOR_PDO18_MASK                    (0x40000U)
72629 #define RGPIO_PDOR_PDO18_SHIFT                   (18U)
72630 /*! PDO18 - Port Data Output
72631  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72632  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72633  */
72634 #define RGPIO_PDOR_PDO18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO18_SHIFT)) & RGPIO_PDOR_PDO18_MASK)
72635 
72636 #define RGPIO_PDOR_PDO19_MASK                    (0x80000U)
72637 #define RGPIO_PDOR_PDO19_SHIFT                   (19U)
72638 /*! PDO19 - Port Data Output
72639  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72640  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72641  */
72642 #define RGPIO_PDOR_PDO19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO19_SHIFT)) & RGPIO_PDOR_PDO19_MASK)
72643 
72644 #define RGPIO_PDOR_PDO20_MASK                    (0x100000U)
72645 #define RGPIO_PDOR_PDO20_SHIFT                   (20U)
72646 /*! PDO20 - Port Data Output
72647  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72648  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72649  */
72650 #define RGPIO_PDOR_PDO20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO20_SHIFT)) & RGPIO_PDOR_PDO20_MASK)
72651 
72652 #define RGPIO_PDOR_PDO21_MASK                    (0x200000U)
72653 #define RGPIO_PDOR_PDO21_SHIFT                   (21U)
72654 /*! PDO21 - Port Data Output
72655  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72656  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72657  */
72658 #define RGPIO_PDOR_PDO21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO21_SHIFT)) & RGPIO_PDOR_PDO21_MASK)
72659 
72660 #define RGPIO_PDOR_PDO22_MASK                    (0x400000U)
72661 #define RGPIO_PDOR_PDO22_SHIFT                   (22U)
72662 /*! PDO22 - Port Data Output
72663  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72664  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72665  */
72666 #define RGPIO_PDOR_PDO22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO22_SHIFT)) & RGPIO_PDOR_PDO22_MASK)
72667 
72668 #define RGPIO_PDOR_PDO23_MASK                    (0x800000U)
72669 #define RGPIO_PDOR_PDO23_SHIFT                   (23U)
72670 /*! PDO23 - Port Data Output
72671  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72672  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72673  */
72674 #define RGPIO_PDOR_PDO23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO23_SHIFT)) & RGPIO_PDOR_PDO23_MASK)
72675 
72676 #define RGPIO_PDOR_PDO24_MASK                    (0x1000000U)
72677 #define RGPIO_PDOR_PDO24_SHIFT                   (24U)
72678 /*! PDO24 - Port Data Output
72679  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72680  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72681  */
72682 #define RGPIO_PDOR_PDO24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO24_SHIFT)) & RGPIO_PDOR_PDO24_MASK)
72683 
72684 #define RGPIO_PDOR_PDO25_MASK                    (0x2000000U)
72685 #define RGPIO_PDOR_PDO25_SHIFT                   (25U)
72686 /*! PDO25 - Port Data Output
72687  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72688  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72689  */
72690 #define RGPIO_PDOR_PDO25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO25_SHIFT)) & RGPIO_PDOR_PDO25_MASK)
72691 
72692 #define RGPIO_PDOR_PDO26_MASK                    (0x4000000U)
72693 #define RGPIO_PDOR_PDO26_SHIFT                   (26U)
72694 /*! PDO26 - Port Data Output
72695  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72696  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72697  */
72698 #define RGPIO_PDOR_PDO26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO26_SHIFT)) & RGPIO_PDOR_PDO26_MASK)
72699 
72700 #define RGPIO_PDOR_PDO27_MASK                    (0x8000000U)
72701 #define RGPIO_PDOR_PDO27_SHIFT                   (27U)
72702 /*! PDO27 - Port Data Output
72703  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72704  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72705  */
72706 #define RGPIO_PDOR_PDO27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO27_SHIFT)) & RGPIO_PDOR_PDO27_MASK)
72707 
72708 #define RGPIO_PDOR_PDO28_MASK                    (0x10000000U)
72709 #define RGPIO_PDOR_PDO28_SHIFT                   (28U)
72710 /*! PDO28 - Port Data Output
72711  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72712  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72713  */
72714 #define RGPIO_PDOR_PDO28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO28_SHIFT)) & RGPIO_PDOR_PDO28_MASK)
72715 
72716 #define RGPIO_PDOR_PDO29_MASK                    (0x20000000U)
72717 #define RGPIO_PDOR_PDO29_SHIFT                   (29U)
72718 /*! PDO29 - Port Data Output
72719  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72720  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72721  */
72722 #define RGPIO_PDOR_PDO29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO29_SHIFT)) & RGPIO_PDOR_PDO29_MASK)
72723 
72724 #define RGPIO_PDOR_PDO30_MASK                    (0x40000000U)
72725 #define RGPIO_PDOR_PDO30_SHIFT                   (30U)
72726 /*! PDO30 - Port Data Output
72727  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72728  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72729  */
72730 #define RGPIO_PDOR_PDO30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO30_SHIFT)) & RGPIO_PDOR_PDO30_MASK)
72731 
72732 #define RGPIO_PDOR_PDO31_MASK                    (0x80000000U)
72733 #define RGPIO_PDOR_PDO31_SHIFT                   (31U)
72734 /*! PDO31 - Port Data Output
72735  *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
72736  *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
72737  */
72738 #define RGPIO_PDOR_PDO31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO31_SHIFT)) & RGPIO_PDOR_PDO31_MASK)
72739 /*! @} */
72740 
72741 /*! @name PSOR - Port Set Output Register */
72742 /*! @{ */
72743 
72744 #define RGPIO_PSOR_PTSO0_MASK                    (0x1U)
72745 #define RGPIO_PSOR_PTSO0_SHIFT                   (0U)
72746 /*! PTSO0 - Port Set Output
72747  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72748  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72749  */
72750 #define RGPIO_PSOR_PTSO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO0_SHIFT)) & RGPIO_PSOR_PTSO0_MASK)
72751 
72752 #define RGPIO_PSOR_PTSO1_MASK                    (0x2U)
72753 #define RGPIO_PSOR_PTSO1_SHIFT                   (1U)
72754 /*! PTSO1 - Port Set Output
72755  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72756  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72757  */
72758 #define RGPIO_PSOR_PTSO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO1_SHIFT)) & RGPIO_PSOR_PTSO1_MASK)
72759 
72760 #define RGPIO_PSOR_PTSO2_MASK                    (0x4U)
72761 #define RGPIO_PSOR_PTSO2_SHIFT                   (2U)
72762 /*! PTSO2 - Port Set Output
72763  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72764  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72765  */
72766 #define RGPIO_PSOR_PTSO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO2_SHIFT)) & RGPIO_PSOR_PTSO2_MASK)
72767 
72768 #define RGPIO_PSOR_PTSO3_MASK                    (0x8U)
72769 #define RGPIO_PSOR_PTSO3_SHIFT                   (3U)
72770 /*! PTSO3 - Port Set Output
72771  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72772  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72773  */
72774 #define RGPIO_PSOR_PTSO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO3_SHIFT)) & RGPIO_PSOR_PTSO3_MASK)
72775 
72776 #define RGPIO_PSOR_PTSO4_MASK                    (0x10U)
72777 #define RGPIO_PSOR_PTSO4_SHIFT                   (4U)
72778 /*! PTSO4 - Port Set Output
72779  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72780  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72781  */
72782 #define RGPIO_PSOR_PTSO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO4_SHIFT)) & RGPIO_PSOR_PTSO4_MASK)
72783 
72784 #define RGPIO_PSOR_PTSO5_MASK                    (0x20U)
72785 #define RGPIO_PSOR_PTSO5_SHIFT                   (5U)
72786 /*! PTSO5 - Port Set Output
72787  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72788  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72789  */
72790 #define RGPIO_PSOR_PTSO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO5_SHIFT)) & RGPIO_PSOR_PTSO5_MASK)
72791 
72792 #define RGPIO_PSOR_PTSO6_MASK                    (0x40U)
72793 #define RGPIO_PSOR_PTSO6_SHIFT                   (6U)
72794 /*! PTSO6 - Port Set Output
72795  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72796  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72797  */
72798 #define RGPIO_PSOR_PTSO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO6_SHIFT)) & RGPIO_PSOR_PTSO6_MASK)
72799 
72800 #define RGPIO_PSOR_PTSO7_MASK                    (0x80U)
72801 #define RGPIO_PSOR_PTSO7_SHIFT                   (7U)
72802 /*! PTSO7 - Port Set Output
72803  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72804  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72805  */
72806 #define RGPIO_PSOR_PTSO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO7_SHIFT)) & RGPIO_PSOR_PTSO7_MASK)
72807 
72808 #define RGPIO_PSOR_PTSO8_MASK                    (0x100U)
72809 #define RGPIO_PSOR_PTSO8_SHIFT                   (8U)
72810 /*! PTSO8 - Port Set Output
72811  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72812  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72813  */
72814 #define RGPIO_PSOR_PTSO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO8_SHIFT)) & RGPIO_PSOR_PTSO8_MASK)
72815 
72816 #define RGPIO_PSOR_PTSO9_MASK                    (0x200U)
72817 #define RGPIO_PSOR_PTSO9_SHIFT                   (9U)
72818 /*! PTSO9 - Port Set Output
72819  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72820  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72821  */
72822 #define RGPIO_PSOR_PTSO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO9_SHIFT)) & RGPIO_PSOR_PTSO9_MASK)
72823 
72824 #define RGPIO_PSOR_PTSO10_MASK                   (0x400U)
72825 #define RGPIO_PSOR_PTSO10_SHIFT                  (10U)
72826 /*! PTSO10 - Port Set Output
72827  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72828  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72829  */
72830 #define RGPIO_PSOR_PTSO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO10_SHIFT)) & RGPIO_PSOR_PTSO10_MASK)
72831 
72832 #define RGPIO_PSOR_PTSO11_MASK                   (0x800U)
72833 #define RGPIO_PSOR_PTSO11_SHIFT                  (11U)
72834 /*! PTSO11 - Port Set Output
72835  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72836  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72837  */
72838 #define RGPIO_PSOR_PTSO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO11_SHIFT)) & RGPIO_PSOR_PTSO11_MASK)
72839 
72840 #define RGPIO_PSOR_PTSO12_MASK                   (0x1000U)
72841 #define RGPIO_PSOR_PTSO12_SHIFT                  (12U)
72842 /*! PTSO12 - Port Set Output
72843  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72844  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72845  */
72846 #define RGPIO_PSOR_PTSO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO12_SHIFT)) & RGPIO_PSOR_PTSO12_MASK)
72847 
72848 #define RGPIO_PSOR_PTSO13_MASK                   (0x2000U)
72849 #define RGPIO_PSOR_PTSO13_SHIFT                  (13U)
72850 /*! PTSO13 - Port Set Output
72851  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72852  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72853  */
72854 #define RGPIO_PSOR_PTSO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO13_SHIFT)) & RGPIO_PSOR_PTSO13_MASK)
72855 
72856 #define RGPIO_PSOR_PTSO14_MASK                   (0x4000U)
72857 #define RGPIO_PSOR_PTSO14_SHIFT                  (14U)
72858 /*! PTSO14 - Port Set Output
72859  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72860  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72861  */
72862 #define RGPIO_PSOR_PTSO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO14_SHIFT)) & RGPIO_PSOR_PTSO14_MASK)
72863 
72864 #define RGPIO_PSOR_PTSO15_MASK                   (0x8000U)
72865 #define RGPIO_PSOR_PTSO15_SHIFT                  (15U)
72866 /*! PTSO15 - Port Set Output
72867  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72868  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72869  */
72870 #define RGPIO_PSOR_PTSO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO15_SHIFT)) & RGPIO_PSOR_PTSO15_MASK)
72871 
72872 #define RGPIO_PSOR_PTSO16_MASK                   (0x10000U)
72873 #define RGPIO_PSOR_PTSO16_SHIFT                  (16U)
72874 /*! PTSO16 - Port Set Output
72875  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72876  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72877  */
72878 #define RGPIO_PSOR_PTSO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO16_SHIFT)) & RGPIO_PSOR_PTSO16_MASK)
72879 
72880 #define RGPIO_PSOR_PTSO17_MASK                   (0x20000U)
72881 #define RGPIO_PSOR_PTSO17_SHIFT                  (17U)
72882 /*! PTSO17 - Port Set Output
72883  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72884  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72885  */
72886 #define RGPIO_PSOR_PTSO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO17_SHIFT)) & RGPIO_PSOR_PTSO17_MASK)
72887 
72888 #define RGPIO_PSOR_PTSO18_MASK                   (0x40000U)
72889 #define RGPIO_PSOR_PTSO18_SHIFT                  (18U)
72890 /*! PTSO18 - Port Set Output
72891  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72892  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72893  */
72894 #define RGPIO_PSOR_PTSO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO18_SHIFT)) & RGPIO_PSOR_PTSO18_MASK)
72895 
72896 #define RGPIO_PSOR_PTSO19_MASK                   (0x80000U)
72897 #define RGPIO_PSOR_PTSO19_SHIFT                  (19U)
72898 /*! PTSO19 - Port Set Output
72899  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72900  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72901  */
72902 #define RGPIO_PSOR_PTSO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO19_SHIFT)) & RGPIO_PSOR_PTSO19_MASK)
72903 
72904 #define RGPIO_PSOR_PTSO20_MASK                   (0x100000U)
72905 #define RGPIO_PSOR_PTSO20_SHIFT                  (20U)
72906 /*! PTSO20 - Port Set Output
72907  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72908  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72909  */
72910 #define RGPIO_PSOR_PTSO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO20_SHIFT)) & RGPIO_PSOR_PTSO20_MASK)
72911 
72912 #define RGPIO_PSOR_PTSO21_MASK                   (0x200000U)
72913 #define RGPIO_PSOR_PTSO21_SHIFT                  (21U)
72914 /*! PTSO21 - Port Set Output
72915  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72916  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72917  */
72918 #define RGPIO_PSOR_PTSO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO21_SHIFT)) & RGPIO_PSOR_PTSO21_MASK)
72919 
72920 #define RGPIO_PSOR_PTSO22_MASK                   (0x400000U)
72921 #define RGPIO_PSOR_PTSO22_SHIFT                  (22U)
72922 /*! PTSO22 - Port Set Output
72923  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72924  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72925  */
72926 #define RGPIO_PSOR_PTSO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO22_SHIFT)) & RGPIO_PSOR_PTSO22_MASK)
72927 
72928 #define RGPIO_PSOR_PTSO23_MASK                   (0x800000U)
72929 #define RGPIO_PSOR_PTSO23_SHIFT                  (23U)
72930 /*! PTSO23 - Port Set Output
72931  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72932  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72933  */
72934 #define RGPIO_PSOR_PTSO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO23_SHIFT)) & RGPIO_PSOR_PTSO23_MASK)
72935 
72936 #define RGPIO_PSOR_PTSO24_MASK                   (0x1000000U)
72937 #define RGPIO_PSOR_PTSO24_SHIFT                  (24U)
72938 /*! PTSO24 - Port Set Output
72939  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72940  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72941  */
72942 #define RGPIO_PSOR_PTSO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO24_SHIFT)) & RGPIO_PSOR_PTSO24_MASK)
72943 
72944 #define RGPIO_PSOR_PTSO25_MASK                   (0x2000000U)
72945 #define RGPIO_PSOR_PTSO25_SHIFT                  (25U)
72946 /*! PTSO25 - Port Set Output
72947  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72948  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72949  */
72950 #define RGPIO_PSOR_PTSO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO25_SHIFT)) & RGPIO_PSOR_PTSO25_MASK)
72951 
72952 #define RGPIO_PSOR_PTSO26_MASK                   (0x4000000U)
72953 #define RGPIO_PSOR_PTSO26_SHIFT                  (26U)
72954 /*! PTSO26 - Port Set Output
72955  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72956  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72957  */
72958 #define RGPIO_PSOR_PTSO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO26_SHIFT)) & RGPIO_PSOR_PTSO26_MASK)
72959 
72960 #define RGPIO_PSOR_PTSO27_MASK                   (0x8000000U)
72961 #define RGPIO_PSOR_PTSO27_SHIFT                  (27U)
72962 /*! PTSO27 - Port Set Output
72963  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72964  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72965  */
72966 #define RGPIO_PSOR_PTSO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO27_SHIFT)) & RGPIO_PSOR_PTSO27_MASK)
72967 
72968 #define RGPIO_PSOR_PTSO28_MASK                   (0x10000000U)
72969 #define RGPIO_PSOR_PTSO28_SHIFT                  (28U)
72970 /*! PTSO28 - Port Set Output
72971  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72972  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72973  */
72974 #define RGPIO_PSOR_PTSO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO28_SHIFT)) & RGPIO_PSOR_PTSO28_MASK)
72975 
72976 #define RGPIO_PSOR_PTSO29_MASK                   (0x20000000U)
72977 #define RGPIO_PSOR_PTSO29_SHIFT                  (29U)
72978 /*! PTSO29 - Port Set Output
72979  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72980  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72981  */
72982 #define RGPIO_PSOR_PTSO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO29_SHIFT)) & RGPIO_PSOR_PTSO29_MASK)
72983 
72984 #define RGPIO_PSOR_PTSO30_MASK                   (0x40000000U)
72985 #define RGPIO_PSOR_PTSO30_SHIFT                  (30U)
72986 /*! PTSO30 - Port Set Output
72987  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72988  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72989  */
72990 #define RGPIO_PSOR_PTSO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO30_SHIFT)) & RGPIO_PSOR_PTSO30_MASK)
72991 
72992 #define RGPIO_PSOR_PTSO31_MASK                   (0x80000000U)
72993 #define RGPIO_PSOR_PTSO31_SHIFT                  (31U)
72994 /*! PTSO31 - Port Set Output
72995  *  0b0..Corresponding field of PDOR[PDOn] does not change.
72996  *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
72997  */
72998 #define RGPIO_PSOR_PTSO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO31_SHIFT)) & RGPIO_PSOR_PTSO31_MASK)
72999 /*! @} */
73000 
73001 /*! @name PCOR - Port Clear Output Register */
73002 /*! @{ */
73003 
73004 #define RGPIO_PCOR_PTCO0_MASK                    (0x1U)
73005 #define RGPIO_PCOR_PTCO0_SHIFT                   (0U)
73006 /*! PTCO0 - Port Clear Output
73007  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73008  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73009  */
73010 #define RGPIO_PCOR_PTCO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO0_SHIFT)) & RGPIO_PCOR_PTCO0_MASK)
73011 
73012 #define RGPIO_PCOR_PTCO1_MASK                    (0x2U)
73013 #define RGPIO_PCOR_PTCO1_SHIFT                   (1U)
73014 /*! PTCO1 - Port Clear Output
73015  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73016  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73017  */
73018 #define RGPIO_PCOR_PTCO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO1_SHIFT)) & RGPIO_PCOR_PTCO1_MASK)
73019 
73020 #define RGPIO_PCOR_PTCO2_MASK                    (0x4U)
73021 #define RGPIO_PCOR_PTCO2_SHIFT                   (2U)
73022 /*! PTCO2 - Port Clear Output
73023  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73024  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73025  */
73026 #define RGPIO_PCOR_PTCO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO2_SHIFT)) & RGPIO_PCOR_PTCO2_MASK)
73027 
73028 #define RGPIO_PCOR_PTCO3_MASK                    (0x8U)
73029 #define RGPIO_PCOR_PTCO3_SHIFT                   (3U)
73030 /*! PTCO3 - Port Clear Output
73031  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73032  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73033  */
73034 #define RGPIO_PCOR_PTCO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO3_SHIFT)) & RGPIO_PCOR_PTCO3_MASK)
73035 
73036 #define RGPIO_PCOR_PTCO4_MASK                    (0x10U)
73037 #define RGPIO_PCOR_PTCO4_SHIFT                   (4U)
73038 /*! PTCO4 - Port Clear Output
73039  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73040  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73041  */
73042 #define RGPIO_PCOR_PTCO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO4_SHIFT)) & RGPIO_PCOR_PTCO4_MASK)
73043 
73044 #define RGPIO_PCOR_PTCO5_MASK                    (0x20U)
73045 #define RGPIO_PCOR_PTCO5_SHIFT                   (5U)
73046 /*! PTCO5 - Port Clear Output
73047  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73048  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73049  */
73050 #define RGPIO_PCOR_PTCO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO5_SHIFT)) & RGPIO_PCOR_PTCO5_MASK)
73051 
73052 #define RGPIO_PCOR_PTCO6_MASK                    (0x40U)
73053 #define RGPIO_PCOR_PTCO6_SHIFT                   (6U)
73054 /*! PTCO6 - Port Clear Output
73055  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73056  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73057  */
73058 #define RGPIO_PCOR_PTCO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO6_SHIFT)) & RGPIO_PCOR_PTCO6_MASK)
73059 
73060 #define RGPIO_PCOR_PTCO7_MASK                    (0x80U)
73061 #define RGPIO_PCOR_PTCO7_SHIFT                   (7U)
73062 /*! PTCO7 - Port Clear Output
73063  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73064  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73065  */
73066 #define RGPIO_PCOR_PTCO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO7_SHIFT)) & RGPIO_PCOR_PTCO7_MASK)
73067 
73068 #define RGPIO_PCOR_PTCO8_MASK                    (0x100U)
73069 #define RGPIO_PCOR_PTCO8_SHIFT                   (8U)
73070 /*! PTCO8 - Port Clear Output
73071  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73072  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73073  */
73074 #define RGPIO_PCOR_PTCO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO8_SHIFT)) & RGPIO_PCOR_PTCO8_MASK)
73075 
73076 #define RGPIO_PCOR_PTCO9_MASK                    (0x200U)
73077 #define RGPIO_PCOR_PTCO9_SHIFT                   (9U)
73078 /*! PTCO9 - Port Clear Output
73079  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73080  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73081  */
73082 #define RGPIO_PCOR_PTCO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO9_SHIFT)) & RGPIO_PCOR_PTCO9_MASK)
73083 
73084 #define RGPIO_PCOR_PTCO10_MASK                   (0x400U)
73085 #define RGPIO_PCOR_PTCO10_SHIFT                  (10U)
73086 /*! PTCO10 - Port Clear Output
73087  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73088  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73089  */
73090 #define RGPIO_PCOR_PTCO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO10_SHIFT)) & RGPIO_PCOR_PTCO10_MASK)
73091 
73092 #define RGPIO_PCOR_PTCO11_MASK                   (0x800U)
73093 #define RGPIO_PCOR_PTCO11_SHIFT                  (11U)
73094 /*! PTCO11 - Port Clear Output
73095  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73096  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73097  */
73098 #define RGPIO_PCOR_PTCO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO11_SHIFT)) & RGPIO_PCOR_PTCO11_MASK)
73099 
73100 #define RGPIO_PCOR_PTCO12_MASK                   (0x1000U)
73101 #define RGPIO_PCOR_PTCO12_SHIFT                  (12U)
73102 /*! PTCO12 - Port Clear Output
73103  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73104  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73105  */
73106 #define RGPIO_PCOR_PTCO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO12_SHIFT)) & RGPIO_PCOR_PTCO12_MASK)
73107 
73108 #define RGPIO_PCOR_PTCO13_MASK                   (0x2000U)
73109 #define RGPIO_PCOR_PTCO13_SHIFT                  (13U)
73110 /*! PTCO13 - Port Clear Output
73111  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73112  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73113  */
73114 #define RGPIO_PCOR_PTCO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO13_SHIFT)) & RGPIO_PCOR_PTCO13_MASK)
73115 
73116 #define RGPIO_PCOR_PTCO14_MASK                   (0x4000U)
73117 #define RGPIO_PCOR_PTCO14_SHIFT                  (14U)
73118 /*! PTCO14 - Port Clear Output
73119  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73120  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73121  */
73122 #define RGPIO_PCOR_PTCO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO14_SHIFT)) & RGPIO_PCOR_PTCO14_MASK)
73123 
73124 #define RGPIO_PCOR_PTCO15_MASK                   (0x8000U)
73125 #define RGPIO_PCOR_PTCO15_SHIFT                  (15U)
73126 /*! PTCO15 - Port Clear Output
73127  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73128  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73129  */
73130 #define RGPIO_PCOR_PTCO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO15_SHIFT)) & RGPIO_PCOR_PTCO15_MASK)
73131 
73132 #define RGPIO_PCOR_PTCO16_MASK                   (0x10000U)
73133 #define RGPIO_PCOR_PTCO16_SHIFT                  (16U)
73134 /*! PTCO16 - Port Clear Output
73135  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73136  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73137  */
73138 #define RGPIO_PCOR_PTCO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO16_SHIFT)) & RGPIO_PCOR_PTCO16_MASK)
73139 
73140 #define RGPIO_PCOR_PTCO17_MASK                   (0x20000U)
73141 #define RGPIO_PCOR_PTCO17_SHIFT                  (17U)
73142 /*! PTCO17 - Port Clear Output
73143  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73144  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73145  */
73146 #define RGPIO_PCOR_PTCO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO17_SHIFT)) & RGPIO_PCOR_PTCO17_MASK)
73147 
73148 #define RGPIO_PCOR_PTCO18_MASK                   (0x40000U)
73149 #define RGPIO_PCOR_PTCO18_SHIFT                  (18U)
73150 /*! PTCO18 - Port Clear Output
73151  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73152  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73153  */
73154 #define RGPIO_PCOR_PTCO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO18_SHIFT)) & RGPIO_PCOR_PTCO18_MASK)
73155 
73156 #define RGPIO_PCOR_PTCO19_MASK                   (0x80000U)
73157 #define RGPIO_PCOR_PTCO19_SHIFT                  (19U)
73158 /*! PTCO19 - Port Clear Output
73159  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73160  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73161  */
73162 #define RGPIO_PCOR_PTCO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO19_SHIFT)) & RGPIO_PCOR_PTCO19_MASK)
73163 
73164 #define RGPIO_PCOR_PTCO20_MASK                   (0x100000U)
73165 #define RGPIO_PCOR_PTCO20_SHIFT                  (20U)
73166 /*! PTCO20 - Port Clear Output
73167  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73168  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73169  */
73170 #define RGPIO_PCOR_PTCO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO20_SHIFT)) & RGPIO_PCOR_PTCO20_MASK)
73171 
73172 #define RGPIO_PCOR_PTCO21_MASK                   (0x200000U)
73173 #define RGPIO_PCOR_PTCO21_SHIFT                  (21U)
73174 /*! PTCO21 - Port Clear Output
73175  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73176  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73177  */
73178 #define RGPIO_PCOR_PTCO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO21_SHIFT)) & RGPIO_PCOR_PTCO21_MASK)
73179 
73180 #define RGPIO_PCOR_PTCO22_MASK                   (0x400000U)
73181 #define RGPIO_PCOR_PTCO22_SHIFT                  (22U)
73182 /*! PTCO22 - Port Clear Output
73183  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73184  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73185  */
73186 #define RGPIO_PCOR_PTCO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO22_SHIFT)) & RGPIO_PCOR_PTCO22_MASK)
73187 
73188 #define RGPIO_PCOR_PTCO23_MASK                   (0x800000U)
73189 #define RGPIO_PCOR_PTCO23_SHIFT                  (23U)
73190 /*! PTCO23 - Port Clear Output
73191  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73192  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73193  */
73194 #define RGPIO_PCOR_PTCO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO23_SHIFT)) & RGPIO_PCOR_PTCO23_MASK)
73195 
73196 #define RGPIO_PCOR_PTCO24_MASK                   (0x1000000U)
73197 #define RGPIO_PCOR_PTCO24_SHIFT                  (24U)
73198 /*! PTCO24 - Port Clear Output
73199  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73200  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73201  */
73202 #define RGPIO_PCOR_PTCO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO24_SHIFT)) & RGPIO_PCOR_PTCO24_MASK)
73203 
73204 #define RGPIO_PCOR_PTCO25_MASK                   (0x2000000U)
73205 #define RGPIO_PCOR_PTCO25_SHIFT                  (25U)
73206 /*! PTCO25 - Port Clear Output
73207  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73208  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73209  */
73210 #define RGPIO_PCOR_PTCO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO25_SHIFT)) & RGPIO_PCOR_PTCO25_MASK)
73211 
73212 #define RGPIO_PCOR_PTCO26_MASK                   (0x4000000U)
73213 #define RGPIO_PCOR_PTCO26_SHIFT                  (26U)
73214 /*! PTCO26 - Port Clear Output
73215  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73216  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73217  */
73218 #define RGPIO_PCOR_PTCO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO26_SHIFT)) & RGPIO_PCOR_PTCO26_MASK)
73219 
73220 #define RGPIO_PCOR_PTCO27_MASK                   (0x8000000U)
73221 #define RGPIO_PCOR_PTCO27_SHIFT                  (27U)
73222 /*! PTCO27 - Port Clear Output
73223  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73224  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73225  */
73226 #define RGPIO_PCOR_PTCO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO27_SHIFT)) & RGPIO_PCOR_PTCO27_MASK)
73227 
73228 #define RGPIO_PCOR_PTCO28_MASK                   (0x10000000U)
73229 #define RGPIO_PCOR_PTCO28_SHIFT                  (28U)
73230 /*! PTCO28 - Port Clear Output
73231  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73232  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73233  */
73234 #define RGPIO_PCOR_PTCO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO28_SHIFT)) & RGPIO_PCOR_PTCO28_MASK)
73235 
73236 #define RGPIO_PCOR_PTCO29_MASK                   (0x20000000U)
73237 #define RGPIO_PCOR_PTCO29_SHIFT                  (29U)
73238 /*! PTCO29 - Port Clear Output
73239  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73240  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73241  */
73242 #define RGPIO_PCOR_PTCO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO29_SHIFT)) & RGPIO_PCOR_PTCO29_MASK)
73243 
73244 #define RGPIO_PCOR_PTCO30_MASK                   (0x40000000U)
73245 #define RGPIO_PCOR_PTCO30_SHIFT                  (30U)
73246 /*! PTCO30 - Port Clear Output
73247  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73248  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73249  */
73250 #define RGPIO_PCOR_PTCO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO30_SHIFT)) & RGPIO_PCOR_PTCO30_MASK)
73251 
73252 #define RGPIO_PCOR_PTCO31_MASK                   (0x80000000U)
73253 #define RGPIO_PCOR_PTCO31_SHIFT                  (31U)
73254 /*! PTCO31 - Port Clear Output
73255  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73256  *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
73257  */
73258 #define RGPIO_PCOR_PTCO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO31_SHIFT)) & RGPIO_PCOR_PTCO31_MASK)
73259 /*! @} */
73260 
73261 /*! @name PTOR - Port Toggle Output Register */
73262 /*! @{ */
73263 
73264 #define RGPIO_PTOR_PTTO0_MASK                    (0x1U)
73265 #define RGPIO_PTOR_PTTO0_SHIFT                   (0U)
73266 /*! PTTO0 - Port Toggle Output
73267  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73268  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73269  */
73270 #define RGPIO_PTOR_PTTO0(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO0_SHIFT)) & RGPIO_PTOR_PTTO0_MASK)
73271 
73272 #define RGPIO_PTOR_PTTO1_MASK                    (0x2U)
73273 #define RGPIO_PTOR_PTTO1_SHIFT                   (1U)
73274 /*! PTTO1 - Port Toggle Output
73275  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73276  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73277  */
73278 #define RGPIO_PTOR_PTTO1(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO1_SHIFT)) & RGPIO_PTOR_PTTO1_MASK)
73279 
73280 #define RGPIO_PTOR_PTTO2_MASK                    (0x4U)
73281 #define RGPIO_PTOR_PTTO2_SHIFT                   (2U)
73282 /*! PTTO2 - Port Toggle Output
73283  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73284  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73285  */
73286 #define RGPIO_PTOR_PTTO2(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO2_SHIFT)) & RGPIO_PTOR_PTTO2_MASK)
73287 
73288 #define RGPIO_PTOR_PTTO3_MASK                    (0x8U)
73289 #define RGPIO_PTOR_PTTO3_SHIFT                   (3U)
73290 /*! PTTO3 - Port Toggle Output
73291  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73292  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73293  */
73294 #define RGPIO_PTOR_PTTO3(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO3_SHIFT)) & RGPIO_PTOR_PTTO3_MASK)
73295 
73296 #define RGPIO_PTOR_PTTO4_MASK                    (0x10U)
73297 #define RGPIO_PTOR_PTTO4_SHIFT                   (4U)
73298 /*! PTTO4 - Port Toggle Output
73299  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73300  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73301  */
73302 #define RGPIO_PTOR_PTTO4(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO4_SHIFT)) & RGPIO_PTOR_PTTO4_MASK)
73303 
73304 #define RGPIO_PTOR_PTTO5_MASK                    (0x20U)
73305 #define RGPIO_PTOR_PTTO5_SHIFT                   (5U)
73306 /*! PTTO5 - Port Toggle Output
73307  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73308  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73309  */
73310 #define RGPIO_PTOR_PTTO5(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO5_SHIFT)) & RGPIO_PTOR_PTTO5_MASK)
73311 
73312 #define RGPIO_PTOR_PTTO6_MASK                    (0x40U)
73313 #define RGPIO_PTOR_PTTO6_SHIFT                   (6U)
73314 /*! PTTO6 - Port Toggle Output
73315  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73316  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73317  */
73318 #define RGPIO_PTOR_PTTO6(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO6_SHIFT)) & RGPIO_PTOR_PTTO6_MASK)
73319 
73320 #define RGPIO_PTOR_PTTO7_MASK                    (0x80U)
73321 #define RGPIO_PTOR_PTTO7_SHIFT                   (7U)
73322 /*! PTTO7 - Port Toggle Output
73323  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73324  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73325  */
73326 #define RGPIO_PTOR_PTTO7(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO7_SHIFT)) & RGPIO_PTOR_PTTO7_MASK)
73327 
73328 #define RGPIO_PTOR_PTTO8_MASK                    (0x100U)
73329 #define RGPIO_PTOR_PTTO8_SHIFT                   (8U)
73330 /*! PTTO8 - Port Toggle Output
73331  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73332  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73333  */
73334 #define RGPIO_PTOR_PTTO8(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO8_SHIFT)) & RGPIO_PTOR_PTTO8_MASK)
73335 
73336 #define RGPIO_PTOR_PTTO9_MASK                    (0x200U)
73337 #define RGPIO_PTOR_PTTO9_SHIFT                   (9U)
73338 /*! PTTO9 - Port Toggle Output
73339  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73340  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73341  */
73342 #define RGPIO_PTOR_PTTO9(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO9_SHIFT)) & RGPIO_PTOR_PTTO9_MASK)
73343 
73344 #define RGPIO_PTOR_PTTO10_MASK                   (0x400U)
73345 #define RGPIO_PTOR_PTTO10_SHIFT                  (10U)
73346 /*! PTTO10 - Port Toggle Output
73347  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73348  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73349  */
73350 #define RGPIO_PTOR_PTTO10(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO10_SHIFT)) & RGPIO_PTOR_PTTO10_MASK)
73351 
73352 #define RGPIO_PTOR_PTTO11_MASK                   (0x800U)
73353 #define RGPIO_PTOR_PTTO11_SHIFT                  (11U)
73354 /*! PTTO11 - Port Toggle Output
73355  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73356  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73357  */
73358 #define RGPIO_PTOR_PTTO11(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO11_SHIFT)) & RGPIO_PTOR_PTTO11_MASK)
73359 
73360 #define RGPIO_PTOR_PTTO12_MASK                   (0x1000U)
73361 #define RGPIO_PTOR_PTTO12_SHIFT                  (12U)
73362 /*! PTTO12 - Port Toggle Output
73363  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73364  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73365  */
73366 #define RGPIO_PTOR_PTTO12(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO12_SHIFT)) & RGPIO_PTOR_PTTO12_MASK)
73367 
73368 #define RGPIO_PTOR_PTTO13_MASK                   (0x2000U)
73369 #define RGPIO_PTOR_PTTO13_SHIFT                  (13U)
73370 /*! PTTO13 - Port Toggle Output
73371  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73372  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73373  */
73374 #define RGPIO_PTOR_PTTO13(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO13_SHIFT)) & RGPIO_PTOR_PTTO13_MASK)
73375 
73376 #define RGPIO_PTOR_PTTO14_MASK                   (0x4000U)
73377 #define RGPIO_PTOR_PTTO14_SHIFT                  (14U)
73378 /*! PTTO14 - Port Toggle Output
73379  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73380  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73381  */
73382 #define RGPIO_PTOR_PTTO14(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO14_SHIFT)) & RGPIO_PTOR_PTTO14_MASK)
73383 
73384 #define RGPIO_PTOR_PTTO15_MASK                   (0x8000U)
73385 #define RGPIO_PTOR_PTTO15_SHIFT                  (15U)
73386 /*! PTTO15 - Port Toggle Output
73387  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73388  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73389  */
73390 #define RGPIO_PTOR_PTTO15(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO15_SHIFT)) & RGPIO_PTOR_PTTO15_MASK)
73391 
73392 #define RGPIO_PTOR_PTTO16_MASK                   (0x10000U)
73393 #define RGPIO_PTOR_PTTO16_SHIFT                  (16U)
73394 /*! PTTO16 - Port Toggle Output
73395  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73396  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73397  */
73398 #define RGPIO_PTOR_PTTO16(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO16_SHIFT)) & RGPIO_PTOR_PTTO16_MASK)
73399 
73400 #define RGPIO_PTOR_PTTO17_MASK                   (0x20000U)
73401 #define RGPIO_PTOR_PTTO17_SHIFT                  (17U)
73402 /*! PTTO17 - Port Toggle Output
73403  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73404  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73405  */
73406 #define RGPIO_PTOR_PTTO17(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO17_SHIFT)) & RGPIO_PTOR_PTTO17_MASK)
73407 
73408 #define RGPIO_PTOR_PTTO18_MASK                   (0x40000U)
73409 #define RGPIO_PTOR_PTTO18_SHIFT                  (18U)
73410 /*! PTTO18 - Port Toggle Output
73411  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73412  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73413  */
73414 #define RGPIO_PTOR_PTTO18(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO18_SHIFT)) & RGPIO_PTOR_PTTO18_MASK)
73415 
73416 #define RGPIO_PTOR_PTTO19_MASK                   (0x80000U)
73417 #define RGPIO_PTOR_PTTO19_SHIFT                  (19U)
73418 /*! PTTO19 - Port Toggle Output
73419  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73420  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73421  */
73422 #define RGPIO_PTOR_PTTO19(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO19_SHIFT)) & RGPIO_PTOR_PTTO19_MASK)
73423 
73424 #define RGPIO_PTOR_PTTO20_MASK                   (0x100000U)
73425 #define RGPIO_PTOR_PTTO20_SHIFT                  (20U)
73426 /*! PTTO20 - Port Toggle Output
73427  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73428  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73429  */
73430 #define RGPIO_PTOR_PTTO20(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO20_SHIFT)) & RGPIO_PTOR_PTTO20_MASK)
73431 
73432 #define RGPIO_PTOR_PTTO21_MASK                   (0x200000U)
73433 #define RGPIO_PTOR_PTTO21_SHIFT                  (21U)
73434 /*! PTTO21 - Port Toggle Output
73435  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73436  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73437  */
73438 #define RGPIO_PTOR_PTTO21(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO21_SHIFT)) & RGPIO_PTOR_PTTO21_MASK)
73439 
73440 #define RGPIO_PTOR_PTTO22_MASK                   (0x400000U)
73441 #define RGPIO_PTOR_PTTO22_SHIFT                  (22U)
73442 /*! PTTO22 - Port Toggle Output
73443  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73444  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73445  */
73446 #define RGPIO_PTOR_PTTO22(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO22_SHIFT)) & RGPIO_PTOR_PTTO22_MASK)
73447 
73448 #define RGPIO_PTOR_PTTO23_MASK                   (0x800000U)
73449 #define RGPIO_PTOR_PTTO23_SHIFT                  (23U)
73450 /*! PTTO23 - Port Toggle Output
73451  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73452  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73453  */
73454 #define RGPIO_PTOR_PTTO23(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO23_SHIFT)) & RGPIO_PTOR_PTTO23_MASK)
73455 
73456 #define RGPIO_PTOR_PTTO24_MASK                   (0x1000000U)
73457 #define RGPIO_PTOR_PTTO24_SHIFT                  (24U)
73458 /*! PTTO24 - Port Toggle Output
73459  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73460  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73461  */
73462 #define RGPIO_PTOR_PTTO24(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO24_SHIFT)) & RGPIO_PTOR_PTTO24_MASK)
73463 
73464 #define RGPIO_PTOR_PTTO25_MASK                   (0x2000000U)
73465 #define RGPIO_PTOR_PTTO25_SHIFT                  (25U)
73466 /*! PTTO25 - Port Toggle Output
73467  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73468  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73469  */
73470 #define RGPIO_PTOR_PTTO25(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO25_SHIFT)) & RGPIO_PTOR_PTTO25_MASK)
73471 
73472 #define RGPIO_PTOR_PTTO26_MASK                   (0x4000000U)
73473 #define RGPIO_PTOR_PTTO26_SHIFT                  (26U)
73474 /*! PTTO26 - Port Toggle Output
73475  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73476  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73477  */
73478 #define RGPIO_PTOR_PTTO26(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO26_SHIFT)) & RGPIO_PTOR_PTTO26_MASK)
73479 
73480 #define RGPIO_PTOR_PTTO27_MASK                   (0x8000000U)
73481 #define RGPIO_PTOR_PTTO27_SHIFT                  (27U)
73482 /*! PTTO27 - Port Toggle Output
73483  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73484  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73485  */
73486 #define RGPIO_PTOR_PTTO27(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO27_SHIFT)) & RGPIO_PTOR_PTTO27_MASK)
73487 
73488 #define RGPIO_PTOR_PTTO28_MASK                   (0x10000000U)
73489 #define RGPIO_PTOR_PTTO28_SHIFT                  (28U)
73490 /*! PTTO28 - Port Toggle Output
73491  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73492  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73493  */
73494 #define RGPIO_PTOR_PTTO28(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO28_SHIFT)) & RGPIO_PTOR_PTTO28_MASK)
73495 
73496 #define RGPIO_PTOR_PTTO29_MASK                   (0x20000000U)
73497 #define RGPIO_PTOR_PTTO29_SHIFT                  (29U)
73498 /*! PTTO29 - Port Toggle Output
73499  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73500  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73501  */
73502 #define RGPIO_PTOR_PTTO29(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO29_SHIFT)) & RGPIO_PTOR_PTTO29_MASK)
73503 
73504 #define RGPIO_PTOR_PTTO30_MASK                   (0x40000000U)
73505 #define RGPIO_PTOR_PTTO30_SHIFT                  (30U)
73506 /*! PTTO30 - Port Toggle Output
73507  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73508  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73509  */
73510 #define RGPIO_PTOR_PTTO30(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO30_SHIFT)) & RGPIO_PTOR_PTTO30_MASK)
73511 
73512 #define RGPIO_PTOR_PTTO31_MASK                   (0x80000000U)
73513 #define RGPIO_PTOR_PTTO31_SHIFT                  (31U)
73514 /*! PTTO31 - Port Toggle Output
73515  *  0b0..Corresponding field of PDOR[PDOn] does not change.
73516  *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
73517  */
73518 #define RGPIO_PTOR_PTTO31(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO31_SHIFT)) & RGPIO_PTOR_PTTO31_MASK)
73519 /*! @} */
73520 
73521 /*! @name PDIR - Port Data Input Register */
73522 /*! @{ */
73523 
73524 #define RGPIO_PDIR_PDI0_MASK                     (0x1U)
73525 #define RGPIO_PDIR_PDI0_SHIFT                    (0U)
73526 /*! PDI0 - Port Data Input
73527  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73528  *  0b1..Pin logic level is logic 1.
73529  */
73530 #define RGPIO_PDIR_PDI0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI0_SHIFT)) & RGPIO_PDIR_PDI0_MASK)
73531 
73532 #define RGPIO_PDIR_PDI1_MASK                     (0x2U)
73533 #define RGPIO_PDIR_PDI1_SHIFT                    (1U)
73534 /*! PDI1 - Port Data Input
73535  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73536  *  0b1..Pin logic level is logic 1.
73537  */
73538 #define RGPIO_PDIR_PDI1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI1_SHIFT)) & RGPIO_PDIR_PDI1_MASK)
73539 
73540 #define RGPIO_PDIR_PDI2_MASK                     (0x4U)
73541 #define RGPIO_PDIR_PDI2_SHIFT                    (2U)
73542 /*! PDI2 - Port Data Input
73543  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73544  *  0b1..Pin logic level is logic 1.
73545  */
73546 #define RGPIO_PDIR_PDI2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI2_SHIFT)) & RGPIO_PDIR_PDI2_MASK)
73547 
73548 #define RGPIO_PDIR_PDI3_MASK                     (0x8U)
73549 #define RGPIO_PDIR_PDI3_SHIFT                    (3U)
73550 /*! PDI3 - Port Data Input
73551  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73552  *  0b1..Pin logic level is logic 1.
73553  */
73554 #define RGPIO_PDIR_PDI3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI3_SHIFT)) & RGPIO_PDIR_PDI3_MASK)
73555 
73556 #define RGPIO_PDIR_PDI4_MASK                     (0x10U)
73557 #define RGPIO_PDIR_PDI4_SHIFT                    (4U)
73558 /*! PDI4 - Port Data Input
73559  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73560  *  0b1..Pin logic level is logic 1.
73561  */
73562 #define RGPIO_PDIR_PDI4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI4_SHIFT)) & RGPIO_PDIR_PDI4_MASK)
73563 
73564 #define RGPIO_PDIR_PDI5_MASK                     (0x20U)
73565 #define RGPIO_PDIR_PDI5_SHIFT                    (5U)
73566 /*! PDI5 - Port Data Input
73567  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73568  *  0b1..Pin logic level is logic 1.
73569  */
73570 #define RGPIO_PDIR_PDI5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI5_SHIFT)) & RGPIO_PDIR_PDI5_MASK)
73571 
73572 #define RGPIO_PDIR_PDI6_MASK                     (0x40U)
73573 #define RGPIO_PDIR_PDI6_SHIFT                    (6U)
73574 /*! PDI6 - Port Data Input
73575  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73576  *  0b1..Pin logic level is logic 1.
73577  */
73578 #define RGPIO_PDIR_PDI6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI6_SHIFT)) & RGPIO_PDIR_PDI6_MASK)
73579 
73580 #define RGPIO_PDIR_PDI7_MASK                     (0x80U)
73581 #define RGPIO_PDIR_PDI7_SHIFT                    (7U)
73582 /*! PDI7 - Port Data Input
73583  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73584  *  0b1..Pin logic level is logic 1.
73585  */
73586 #define RGPIO_PDIR_PDI7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI7_SHIFT)) & RGPIO_PDIR_PDI7_MASK)
73587 
73588 #define RGPIO_PDIR_PDI8_MASK                     (0x100U)
73589 #define RGPIO_PDIR_PDI8_SHIFT                    (8U)
73590 /*! PDI8 - Port Data Input
73591  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73592  *  0b1..Pin logic level is logic 1.
73593  */
73594 #define RGPIO_PDIR_PDI8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI8_SHIFT)) & RGPIO_PDIR_PDI8_MASK)
73595 
73596 #define RGPIO_PDIR_PDI9_MASK                     (0x200U)
73597 #define RGPIO_PDIR_PDI9_SHIFT                    (9U)
73598 /*! PDI9 - Port Data Input
73599  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73600  *  0b1..Pin logic level is logic 1.
73601  */
73602 #define RGPIO_PDIR_PDI9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI9_SHIFT)) & RGPIO_PDIR_PDI9_MASK)
73603 
73604 #define RGPIO_PDIR_PDI10_MASK                    (0x400U)
73605 #define RGPIO_PDIR_PDI10_SHIFT                   (10U)
73606 /*! PDI10 - Port Data Input
73607  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73608  *  0b1..Pin logic level is logic 1.
73609  */
73610 #define RGPIO_PDIR_PDI10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI10_SHIFT)) & RGPIO_PDIR_PDI10_MASK)
73611 
73612 #define RGPIO_PDIR_PDI11_MASK                    (0x800U)
73613 #define RGPIO_PDIR_PDI11_SHIFT                   (11U)
73614 /*! PDI11 - Port Data Input
73615  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73616  *  0b1..Pin logic level is logic 1.
73617  */
73618 #define RGPIO_PDIR_PDI11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI11_SHIFT)) & RGPIO_PDIR_PDI11_MASK)
73619 
73620 #define RGPIO_PDIR_PDI12_MASK                    (0x1000U)
73621 #define RGPIO_PDIR_PDI12_SHIFT                   (12U)
73622 /*! PDI12 - Port Data Input
73623  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73624  *  0b1..Pin logic level is logic 1.
73625  */
73626 #define RGPIO_PDIR_PDI12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI12_SHIFT)) & RGPIO_PDIR_PDI12_MASK)
73627 
73628 #define RGPIO_PDIR_PDI13_MASK                    (0x2000U)
73629 #define RGPIO_PDIR_PDI13_SHIFT                   (13U)
73630 /*! PDI13 - Port Data Input
73631  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73632  *  0b1..Pin logic level is logic 1.
73633  */
73634 #define RGPIO_PDIR_PDI13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI13_SHIFT)) & RGPIO_PDIR_PDI13_MASK)
73635 
73636 #define RGPIO_PDIR_PDI14_MASK                    (0x4000U)
73637 #define RGPIO_PDIR_PDI14_SHIFT                   (14U)
73638 /*! PDI14 - Port Data Input
73639  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73640  *  0b1..Pin logic level is logic 1.
73641  */
73642 #define RGPIO_PDIR_PDI14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI14_SHIFT)) & RGPIO_PDIR_PDI14_MASK)
73643 
73644 #define RGPIO_PDIR_PDI15_MASK                    (0x8000U)
73645 #define RGPIO_PDIR_PDI15_SHIFT                   (15U)
73646 /*! PDI15 - Port Data Input
73647  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73648  *  0b1..Pin logic level is logic 1.
73649  */
73650 #define RGPIO_PDIR_PDI15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI15_SHIFT)) & RGPIO_PDIR_PDI15_MASK)
73651 
73652 #define RGPIO_PDIR_PDI16_MASK                    (0x10000U)
73653 #define RGPIO_PDIR_PDI16_SHIFT                   (16U)
73654 /*! PDI16 - Port Data Input
73655  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73656  *  0b1..Pin logic level is logic 1.
73657  */
73658 #define RGPIO_PDIR_PDI16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI16_SHIFT)) & RGPIO_PDIR_PDI16_MASK)
73659 
73660 #define RGPIO_PDIR_PDI17_MASK                    (0x20000U)
73661 #define RGPIO_PDIR_PDI17_SHIFT                   (17U)
73662 /*! PDI17 - Port Data Input
73663  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73664  *  0b1..Pin logic level is logic 1.
73665  */
73666 #define RGPIO_PDIR_PDI17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI17_SHIFT)) & RGPIO_PDIR_PDI17_MASK)
73667 
73668 #define RGPIO_PDIR_PDI18_MASK                    (0x40000U)
73669 #define RGPIO_PDIR_PDI18_SHIFT                   (18U)
73670 /*! PDI18 - Port Data Input
73671  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73672  *  0b1..Pin logic level is logic 1.
73673  */
73674 #define RGPIO_PDIR_PDI18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI18_SHIFT)) & RGPIO_PDIR_PDI18_MASK)
73675 
73676 #define RGPIO_PDIR_PDI19_MASK                    (0x80000U)
73677 #define RGPIO_PDIR_PDI19_SHIFT                   (19U)
73678 /*! PDI19 - Port Data Input
73679  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73680  *  0b1..Pin logic level is logic 1.
73681  */
73682 #define RGPIO_PDIR_PDI19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI19_SHIFT)) & RGPIO_PDIR_PDI19_MASK)
73683 
73684 #define RGPIO_PDIR_PDI20_MASK                    (0x100000U)
73685 #define RGPIO_PDIR_PDI20_SHIFT                   (20U)
73686 /*! PDI20 - Port Data Input
73687  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73688  *  0b1..Pin logic level is logic 1.
73689  */
73690 #define RGPIO_PDIR_PDI20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI20_SHIFT)) & RGPIO_PDIR_PDI20_MASK)
73691 
73692 #define RGPIO_PDIR_PDI21_MASK                    (0x200000U)
73693 #define RGPIO_PDIR_PDI21_SHIFT                   (21U)
73694 /*! PDI21 - Port Data Input
73695  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73696  *  0b1..Pin logic level is logic 1.
73697  */
73698 #define RGPIO_PDIR_PDI21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI21_SHIFT)) & RGPIO_PDIR_PDI21_MASK)
73699 
73700 #define RGPIO_PDIR_PDI22_MASK                    (0x400000U)
73701 #define RGPIO_PDIR_PDI22_SHIFT                   (22U)
73702 /*! PDI22 - Port Data Input
73703  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73704  *  0b1..Pin logic level is logic 1.
73705  */
73706 #define RGPIO_PDIR_PDI22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI22_SHIFT)) & RGPIO_PDIR_PDI22_MASK)
73707 
73708 #define RGPIO_PDIR_PDI23_MASK                    (0x800000U)
73709 #define RGPIO_PDIR_PDI23_SHIFT                   (23U)
73710 /*! PDI23 - Port Data Input
73711  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73712  *  0b1..Pin logic level is logic 1.
73713  */
73714 #define RGPIO_PDIR_PDI23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI23_SHIFT)) & RGPIO_PDIR_PDI23_MASK)
73715 
73716 #define RGPIO_PDIR_PDI24_MASK                    (0x1000000U)
73717 #define RGPIO_PDIR_PDI24_SHIFT                   (24U)
73718 /*! PDI24 - Port Data Input
73719  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73720  *  0b1..Pin logic level is logic 1.
73721  */
73722 #define RGPIO_PDIR_PDI24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI24_SHIFT)) & RGPIO_PDIR_PDI24_MASK)
73723 
73724 #define RGPIO_PDIR_PDI25_MASK                    (0x2000000U)
73725 #define RGPIO_PDIR_PDI25_SHIFT                   (25U)
73726 /*! PDI25 - Port Data Input
73727  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73728  *  0b1..Pin logic level is logic 1.
73729  */
73730 #define RGPIO_PDIR_PDI25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI25_SHIFT)) & RGPIO_PDIR_PDI25_MASK)
73731 
73732 #define RGPIO_PDIR_PDI26_MASK                    (0x4000000U)
73733 #define RGPIO_PDIR_PDI26_SHIFT                   (26U)
73734 /*! PDI26 - Port Data Input
73735  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73736  *  0b1..Pin logic level is logic 1.
73737  */
73738 #define RGPIO_PDIR_PDI26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI26_SHIFT)) & RGPIO_PDIR_PDI26_MASK)
73739 
73740 #define RGPIO_PDIR_PDI27_MASK                    (0x8000000U)
73741 #define RGPIO_PDIR_PDI27_SHIFT                   (27U)
73742 /*! PDI27 - Port Data Input
73743  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73744  *  0b1..Pin logic level is logic 1.
73745  */
73746 #define RGPIO_PDIR_PDI27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI27_SHIFT)) & RGPIO_PDIR_PDI27_MASK)
73747 
73748 #define RGPIO_PDIR_PDI28_MASK                    (0x10000000U)
73749 #define RGPIO_PDIR_PDI28_SHIFT                   (28U)
73750 /*! PDI28 - Port Data Input
73751  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73752  *  0b1..Pin logic level is logic 1.
73753  */
73754 #define RGPIO_PDIR_PDI28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI28_SHIFT)) & RGPIO_PDIR_PDI28_MASK)
73755 
73756 #define RGPIO_PDIR_PDI29_MASK                    (0x20000000U)
73757 #define RGPIO_PDIR_PDI29_SHIFT                   (29U)
73758 /*! PDI29 - Port Data Input
73759  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73760  *  0b1..Pin logic level is logic 1.
73761  */
73762 #define RGPIO_PDIR_PDI29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI29_SHIFT)) & RGPIO_PDIR_PDI29_MASK)
73763 
73764 #define RGPIO_PDIR_PDI30_MASK                    (0x40000000U)
73765 #define RGPIO_PDIR_PDI30_SHIFT                   (30U)
73766 /*! PDI30 - Port Data Input
73767  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73768  *  0b1..Pin logic level is logic 1.
73769  */
73770 #define RGPIO_PDIR_PDI30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI30_SHIFT)) & RGPIO_PDIR_PDI30_MASK)
73771 
73772 #define RGPIO_PDIR_PDI31_MASK                    (0x80000000U)
73773 #define RGPIO_PDIR_PDI31_SHIFT                   (31U)
73774 /*! PDI31 - Port Data Input
73775  *  0b0..Pin logic level is logic 0 or is not configured for use by digital function.
73776  *  0b1..Pin logic level is logic 1.
73777  */
73778 #define RGPIO_PDIR_PDI31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI31_SHIFT)) & RGPIO_PDIR_PDI31_MASK)
73779 /*! @} */
73780 
73781 /*! @name PDDR - Port Data Direction Register */
73782 /*! @{ */
73783 
73784 #define RGPIO_PDDR_PDD0_MASK                     (0x1U)
73785 #define RGPIO_PDDR_PDD0_SHIFT                    (0U)
73786 /*! PDD0 - Port Data Direction
73787  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73788  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73789  */
73790 #define RGPIO_PDDR_PDD0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD0_SHIFT)) & RGPIO_PDDR_PDD0_MASK)
73791 
73792 #define RGPIO_PDDR_PDD1_MASK                     (0x2U)
73793 #define RGPIO_PDDR_PDD1_SHIFT                    (1U)
73794 /*! PDD1 - Port Data Direction
73795  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73796  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73797  */
73798 #define RGPIO_PDDR_PDD1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD1_SHIFT)) & RGPIO_PDDR_PDD1_MASK)
73799 
73800 #define RGPIO_PDDR_PDD2_MASK                     (0x4U)
73801 #define RGPIO_PDDR_PDD2_SHIFT                    (2U)
73802 /*! PDD2 - Port Data Direction
73803  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73804  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73805  */
73806 #define RGPIO_PDDR_PDD2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD2_SHIFT)) & RGPIO_PDDR_PDD2_MASK)
73807 
73808 #define RGPIO_PDDR_PDD3_MASK                     (0x8U)
73809 #define RGPIO_PDDR_PDD3_SHIFT                    (3U)
73810 /*! PDD3 - Port Data Direction
73811  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73812  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73813  */
73814 #define RGPIO_PDDR_PDD3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD3_SHIFT)) & RGPIO_PDDR_PDD3_MASK)
73815 
73816 #define RGPIO_PDDR_PDD4_MASK                     (0x10U)
73817 #define RGPIO_PDDR_PDD4_SHIFT                    (4U)
73818 /*! PDD4 - Port Data Direction
73819  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73820  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73821  */
73822 #define RGPIO_PDDR_PDD4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD4_SHIFT)) & RGPIO_PDDR_PDD4_MASK)
73823 
73824 #define RGPIO_PDDR_PDD5_MASK                     (0x20U)
73825 #define RGPIO_PDDR_PDD5_SHIFT                    (5U)
73826 /*! PDD5 - Port Data Direction
73827  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73828  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73829  */
73830 #define RGPIO_PDDR_PDD5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD5_SHIFT)) & RGPIO_PDDR_PDD5_MASK)
73831 
73832 #define RGPIO_PDDR_PDD6_MASK                     (0x40U)
73833 #define RGPIO_PDDR_PDD6_SHIFT                    (6U)
73834 /*! PDD6 - Port Data Direction
73835  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73836  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73837  */
73838 #define RGPIO_PDDR_PDD6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD6_SHIFT)) & RGPIO_PDDR_PDD6_MASK)
73839 
73840 #define RGPIO_PDDR_PDD7_MASK                     (0x80U)
73841 #define RGPIO_PDDR_PDD7_SHIFT                    (7U)
73842 /*! PDD7 - Port Data Direction
73843  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73844  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73845  */
73846 #define RGPIO_PDDR_PDD7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD7_SHIFT)) & RGPIO_PDDR_PDD7_MASK)
73847 
73848 #define RGPIO_PDDR_PDD8_MASK                     (0x100U)
73849 #define RGPIO_PDDR_PDD8_SHIFT                    (8U)
73850 /*! PDD8 - Port Data Direction
73851  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73852  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73853  */
73854 #define RGPIO_PDDR_PDD8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD8_SHIFT)) & RGPIO_PDDR_PDD8_MASK)
73855 
73856 #define RGPIO_PDDR_PDD9_MASK                     (0x200U)
73857 #define RGPIO_PDDR_PDD9_SHIFT                    (9U)
73858 /*! PDD9 - Port Data Direction
73859  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73860  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73861  */
73862 #define RGPIO_PDDR_PDD9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD9_SHIFT)) & RGPIO_PDDR_PDD9_MASK)
73863 
73864 #define RGPIO_PDDR_PDD10_MASK                    (0x400U)
73865 #define RGPIO_PDDR_PDD10_SHIFT                   (10U)
73866 /*! PDD10 - Port Data Direction
73867  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73868  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73869  */
73870 #define RGPIO_PDDR_PDD10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD10_SHIFT)) & RGPIO_PDDR_PDD10_MASK)
73871 
73872 #define RGPIO_PDDR_PDD11_MASK                    (0x800U)
73873 #define RGPIO_PDDR_PDD11_SHIFT                   (11U)
73874 /*! PDD11 - Port Data Direction
73875  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73876  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73877  */
73878 #define RGPIO_PDDR_PDD11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD11_SHIFT)) & RGPIO_PDDR_PDD11_MASK)
73879 
73880 #define RGPIO_PDDR_PDD12_MASK                    (0x1000U)
73881 #define RGPIO_PDDR_PDD12_SHIFT                   (12U)
73882 /*! PDD12 - Port Data Direction
73883  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73884  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73885  */
73886 #define RGPIO_PDDR_PDD12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD12_SHIFT)) & RGPIO_PDDR_PDD12_MASK)
73887 
73888 #define RGPIO_PDDR_PDD13_MASK                    (0x2000U)
73889 #define RGPIO_PDDR_PDD13_SHIFT                   (13U)
73890 /*! PDD13 - Port Data Direction
73891  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73892  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73893  */
73894 #define RGPIO_PDDR_PDD13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD13_SHIFT)) & RGPIO_PDDR_PDD13_MASK)
73895 
73896 #define RGPIO_PDDR_PDD14_MASK                    (0x4000U)
73897 #define RGPIO_PDDR_PDD14_SHIFT                   (14U)
73898 /*! PDD14 - Port Data Direction
73899  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73900  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73901  */
73902 #define RGPIO_PDDR_PDD14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD14_SHIFT)) & RGPIO_PDDR_PDD14_MASK)
73903 
73904 #define RGPIO_PDDR_PDD15_MASK                    (0x8000U)
73905 #define RGPIO_PDDR_PDD15_SHIFT                   (15U)
73906 /*! PDD15 - Port Data Direction
73907  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73908  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73909  */
73910 #define RGPIO_PDDR_PDD15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD15_SHIFT)) & RGPIO_PDDR_PDD15_MASK)
73911 
73912 #define RGPIO_PDDR_PDD16_MASK                    (0x10000U)
73913 #define RGPIO_PDDR_PDD16_SHIFT                   (16U)
73914 /*! PDD16 - Port Data Direction
73915  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73916  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73917  */
73918 #define RGPIO_PDDR_PDD16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD16_SHIFT)) & RGPIO_PDDR_PDD16_MASK)
73919 
73920 #define RGPIO_PDDR_PDD17_MASK                    (0x20000U)
73921 #define RGPIO_PDDR_PDD17_SHIFT                   (17U)
73922 /*! PDD17 - Port Data Direction
73923  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73924  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73925  */
73926 #define RGPIO_PDDR_PDD17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD17_SHIFT)) & RGPIO_PDDR_PDD17_MASK)
73927 
73928 #define RGPIO_PDDR_PDD18_MASK                    (0x40000U)
73929 #define RGPIO_PDDR_PDD18_SHIFT                   (18U)
73930 /*! PDD18 - Port Data Direction
73931  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73932  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73933  */
73934 #define RGPIO_PDDR_PDD18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD18_SHIFT)) & RGPIO_PDDR_PDD18_MASK)
73935 
73936 #define RGPIO_PDDR_PDD19_MASK                    (0x80000U)
73937 #define RGPIO_PDDR_PDD19_SHIFT                   (19U)
73938 /*! PDD19 - Port Data Direction
73939  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73940  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73941  */
73942 #define RGPIO_PDDR_PDD19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD19_SHIFT)) & RGPIO_PDDR_PDD19_MASK)
73943 
73944 #define RGPIO_PDDR_PDD20_MASK                    (0x100000U)
73945 #define RGPIO_PDDR_PDD20_SHIFT                   (20U)
73946 /*! PDD20 - Port Data Direction
73947  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73948  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73949  */
73950 #define RGPIO_PDDR_PDD20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD20_SHIFT)) & RGPIO_PDDR_PDD20_MASK)
73951 
73952 #define RGPIO_PDDR_PDD21_MASK                    (0x200000U)
73953 #define RGPIO_PDDR_PDD21_SHIFT                   (21U)
73954 /*! PDD21 - Port Data Direction
73955  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73956  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73957  */
73958 #define RGPIO_PDDR_PDD21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD21_SHIFT)) & RGPIO_PDDR_PDD21_MASK)
73959 
73960 #define RGPIO_PDDR_PDD22_MASK                    (0x400000U)
73961 #define RGPIO_PDDR_PDD22_SHIFT                   (22U)
73962 /*! PDD22 - Port Data Direction
73963  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73964  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73965  */
73966 #define RGPIO_PDDR_PDD22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD22_SHIFT)) & RGPIO_PDDR_PDD22_MASK)
73967 
73968 #define RGPIO_PDDR_PDD23_MASK                    (0x800000U)
73969 #define RGPIO_PDDR_PDD23_SHIFT                   (23U)
73970 /*! PDD23 - Port Data Direction
73971  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73972  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73973  */
73974 #define RGPIO_PDDR_PDD23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD23_SHIFT)) & RGPIO_PDDR_PDD23_MASK)
73975 
73976 #define RGPIO_PDDR_PDD24_MASK                    (0x1000000U)
73977 #define RGPIO_PDDR_PDD24_SHIFT                   (24U)
73978 /*! PDD24 - Port Data Direction
73979  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73980  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73981  */
73982 #define RGPIO_PDDR_PDD24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD24_SHIFT)) & RGPIO_PDDR_PDD24_MASK)
73983 
73984 #define RGPIO_PDDR_PDD25_MASK                    (0x2000000U)
73985 #define RGPIO_PDDR_PDD25_SHIFT                   (25U)
73986 /*! PDD25 - Port Data Direction
73987  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73988  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73989  */
73990 #define RGPIO_PDDR_PDD25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD25_SHIFT)) & RGPIO_PDDR_PDD25_MASK)
73991 
73992 #define RGPIO_PDDR_PDD26_MASK                    (0x4000000U)
73993 #define RGPIO_PDDR_PDD26_SHIFT                   (26U)
73994 /*! PDD26 - Port Data Direction
73995  *  0b0..Pin is configured as general-purpose input for the GPIO function.
73996  *  0b1..Pin is configured as general-purpose output for the GPIO function.
73997  */
73998 #define RGPIO_PDDR_PDD26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD26_SHIFT)) & RGPIO_PDDR_PDD26_MASK)
73999 
74000 #define RGPIO_PDDR_PDD27_MASK                    (0x8000000U)
74001 #define RGPIO_PDDR_PDD27_SHIFT                   (27U)
74002 /*! PDD27 - Port Data Direction
74003  *  0b0..Pin is configured as general-purpose input for the GPIO function.
74004  *  0b1..Pin is configured as general-purpose output for the GPIO function.
74005  */
74006 #define RGPIO_PDDR_PDD27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD27_SHIFT)) & RGPIO_PDDR_PDD27_MASK)
74007 
74008 #define RGPIO_PDDR_PDD28_MASK                    (0x10000000U)
74009 #define RGPIO_PDDR_PDD28_SHIFT                   (28U)
74010 /*! PDD28 - Port Data Direction
74011  *  0b0..Pin is configured as general-purpose input for the GPIO function.
74012  *  0b1..Pin is configured as general-purpose output for the GPIO function.
74013  */
74014 #define RGPIO_PDDR_PDD28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD28_SHIFT)) & RGPIO_PDDR_PDD28_MASK)
74015 
74016 #define RGPIO_PDDR_PDD29_MASK                    (0x20000000U)
74017 #define RGPIO_PDDR_PDD29_SHIFT                   (29U)
74018 /*! PDD29 - Port Data Direction
74019  *  0b0..Pin is configured as general-purpose input for the GPIO function.
74020  *  0b1..Pin is configured as general-purpose output for the GPIO function.
74021  */
74022 #define RGPIO_PDDR_PDD29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD29_SHIFT)) & RGPIO_PDDR_PDD29_MASK)
74023 
74024 #define RGPIO_PDDR_PDD30_MASK                    (0x40000000U)
74025 #define RGPIO_PDDR_PDD30_SHIFT                   (30U)
74026 /*! PDD30 - Port Data Direction
74027  *  0b0..Pin is configured as general-purpose input for the GPIO function.
74028  *  0b1..Pin is configured as general-purpose output for the GPIO function.
74029  */
74030 #define RGPIO_PDDR_PDD30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD30_SHIFT)) & RGPIO_PDDR_PDD30_MASK)
74031 
74032 #define RGPIO_PDDR_PDD31_MASK                    (0x80000000U)
74033 #define RGPIO_PDDR_PDD31_SHIFT                   (31U)
74034 /*! PDD31 - Port Data Direction
74035  *  0b0..Pin is configured as general-purpose input for the GPIO function.
74036  *  0b1..Pin is configured as general-purpose output for the GPIO function.
74037  */
74038 #define RGPIO_PDDR_PDD31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD31_SHIFT)) & RGPIO_PDDR_PDD31_MASK)
74039 /*! @} */
74040 
74041 /*! @name PIDR - Port Input Disable Register */
74042 /*! @{ */
74043 
74044 #define RGPIO_PIDR_PID0_MASK                     (0x1U)
74045 #define RGPIO_PIDR_PID0_SHIFT                    (0U)
74046 /*! PID0 - Port Input Disable
74047  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74048  *  0b1..Pin is disabled for general-purpose input.
74049  */
74050 #define RGPIO_PIDR_PID0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID0_SHIFT)) & RGPIO_PIDR_PID0_MASK)
74051 
74052 #define RGPIO_PIDR_PID1_MASK                     (0x2U)
74053 #define RGPIO_PIDR_PID1_SHIFT                    (1U)
74054 /*! PID1 - Port Input Disable
74055  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74056  *  0b1..Pin is disabled for general-purpose input.
74057  */
74058 #define RGPIO_PIDR_PID1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID1_SHIFT)) & RGPIO_PIDR_PID1_MASK)
74059 
74060 #define RGPIO_PIDR_PID2_MASK                     (0x4U)
74061 #define RGPIO_PIDR_PID2_SHIFT                    (2U)
74062 /*! PID2 - Port Input Disable
74063  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74064  *  0b1..Pin is disabled for general-purpose input.
74065  */
74066 #define RGPIO_PIDR_PID2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID2_SHIFT)) & RGPIO_PIDR_PID2_MASK)
74067 
74068 #define RGPIO_PIDR_PID3_MASK                     (0x8U)
74069 #define RGPIO_PIDR_PID3_SHIFT                    (3U)
74070 /*! PID3 - Port Input Disable
74071  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74072  *  0b1..Pin is disabled for general-purpose input.
74073  */
74074 #define RGPIO_PIDR_PID3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID3_SHIFT)) & RGPIO_PIDR_PID3_MASK)
74075 
74076 #define RGPIO_PIDR_PID4_MASK                     (0x10U)
74077 #define RGPIO_PIDR_PID4_SHIFT                    (4U)
74078 /*! PID4 - Port Input Disable
74079  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74080  *  0b1..Pin is disabled for general-purpose input.
74081  */
74082 #define RGPIO_PIDR_PID4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID4_SHIFT)) & RGPIO_PIDR_PID4_MASK)
74083 
74084 #define RGPIO_PIDR_PID5_MASK                     (0x20U)
74085 #define RGPIO_PIDR_PID5_SHIFT                    (5U)
74086 /*! PID5 - Port Input Disable
74087  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74088  *  0b1..Pin is disabled for general-purpose input.
74089  */
74090 #define RGPIO_PIDR_PID5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID5_SHIFT)) & RGPIO_PIDR_PID5_MASK)
74091 
74092 #define RGPIO_PIDR_PID6_MASK                     (0x40U)
74093 #define RGPIO_PIDR_PID6_SHIFT                    (6U)
74094 /*! PID6 - Port Input Disable
74095  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74096  *  0b1..Pin is disabled for general-purpose input.
74097  */
74098 #define RGPIO_PIDR_PID6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID6_SHIFT)) & RGPIO_PIDR_PID6_MASK)
74099 
74100 #define RGPIO_PIDR_PID7_MASK                     (0x80U)
74101 #define RGPIO_PIDR_PID7_SHIFT                    (7U)
74102 /*! PID7 - Port Input Disable
74103  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74104  *  0b1..Pin is disabled for general-purpose input.
74105  */
74106 #define RGPIO_PIDR_PID7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID7_SHIFT)) & RGPIO_PIDR_PID7_MASK)
74107 
74108 #define RGPIO_PIDR_PID8_MASK                     (0x100U)
74109 #define RGPIO_PIDR_PID8_SHIFT                    (8U)
74110 /*! PID8 - Port Input Disable
74111  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74112  *  0b1..Pin is disabled for general-purpose input.
74113  */
74114 #define RGPIO_PIDR_PID8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID8_SHIFT)) & RGPIO_PIDR_PID8_MASK)
74115 
74116 #define RGPIO_PIDR_PID9_MASK                     (0x200U)
74117 #define RGPIO_PIDR_PID9_SHIFT                    (9U)
74118 /*! PID9 - Port Input Disable
74119  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74120  *  0b1..Pin is disabled for general-purpose input.
74121  */
74122 #define RGPIO_PIDR_PID9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID9_SHIFT)) & RGPIO_PIDR_PID9_MASK)
74123 
74124 #define RGPIO_PIDR_PID10_MASK                    (0x400U)
74125 #define RGPIO_PIDR_PID10_SHIFT                   (10U)
74126 /*! PID10 - Port Input Disable
74127  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74128  *  0b1..Pin is disabled for general-purpose input.
74129  */
74130 #define RGPIO_PIDR_PID10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID10_SHIFT)) & RGPIO_PIDR_PID10_MASK)
74131 
74132 #define RGPIO_PIDR_PID11_MASK                    (0x800U)
74133 #define RGPIO_PIDR_PID11_SHIFT                   (11U)
74134 /*! PID11 - Port Input Disable
74135  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74136  *  0b1..Pin is disabled for general-purpose input.
74137  */
74138 #define RGPIO_PIDR_PID11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID11_SHIFT)) & RGPIO_PIDR_PID11_MASK)
74139 
74140 #define RGPIO_PIDR_PID12_MASK                    (0x1000U)
74141 #define RGPIO_PIDR_PID12_SHIFT                   (12U)
74142 /*! PID12 - Port Input Disable
74143  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74144  *  0b1..Pin is disabled for general-purpose input.
74145  */
74146 #define RGPIO_PIDR_PID12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID12_SHIFT)) & RGPIO_PIDR_PID12_MASK)
74147 
74148 #define RGPIO_PIDR_PID13_MASK                    (0x2000U)
74149 #define RGPIO_PIDR_PID13_SHIFT                   (13U)
74150 /*! PID13 - Port Input Disable
74151  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74152  *  0b1..Pin is disabled for general-purpose input.
74153  */
74154 #define RGPIO_PIDR_PID13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID13_SHIFT)) & RGPIO_PIDR_PID13_MASK)
74155 
74156 #define RGPIO_PIDR_PID14_MASK                    (0x4000U)
74157 #define RGPIO_PIDR_PID14_SHIFT                   (14U)
74158 /*! PID14 - Port Input Disable
74159  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74160  *  0b1..Pin is disabled for general-purpose input.
74161  */
74162 #define RGPIO_PIDR_PID14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID14_SHIFT)) & RGPIO_PIDR_PID14_MASK)
74163 
74164 #define RGPIO_PIDR_PID15_MASK                    (0x8000U)
74165 #define RGPIO_PIDR_PID15_SHIFT                   (15U)
74166 /*! PID15 - Port Input Disable
74167  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74168  *  0b1..Pin is disabled for general-purpose input.
74169  */
74170 #define RGPIO_PIDR_PID15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID15_SHIFT)) & RGPIO_PIDR_PID15_MASK)
74171 
74172 #define RGPIO_PIDR_PID16_MASK                    (0x10000U)
74173 #define RGPIO_PIDR_PID16_SHIFT                   (16U)
74174 /*! PID16 - Port Input Disable
74175  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74176  *  0b1..Pin is disabled for general-purpose input.
74177  */
74178 #define RGPIO_PIDR_PID16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID16_SHIFT)) & RGPIO_PIDR_PID16_MASK)
74179 
74180 #define RGPIO_PIDR_PID17_MASK                    (0x20000U)
74181 #define RGPIO_PIDR_PID17_SHIFT                   (17U)
74182 /*! PID17 - Port Input Disable
74183  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74184  *  0b1..Pin is disabled for general-purpose input.
74185  */
74186 #define RGPIO_PIDR_PID17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID17_SHIFT)) & RGPIO_PIDR_PID17_MASK)
74187 
74188 #define RGPIO_PIDR_PID18_MASK                    (0x40000U)
74189 #define RGPIO_PIDR_PID18_SHIFT                   (18U)
74190 /*! PID18 - Port Input Disable
74191  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74192  *  0b1..Pin is disabled for general-purpose input.
74193  */
74194 #define RGPIO_PIDR_PID18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID18_SHIFT)) & RGPIO_PIDR_PID18_MASK)
74195 
74196 #define RGPIO_PIDR_PID19_MASK                    (0x80000U)
74197 #define RGPIO_PIDR_PID19_SHIFT                   (19U)
74198 /*! PID19 - Port Input Disable
74199  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74200  *  0b1..Pin is disabled for general-purpose input.
74201  */
74202 #define RGPIO_PIDR_PID19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID19_SHIFT)) & RGPIO_PIDR_PID19_MASK)
74203 
74204 #define RGPIO_PIDR_PID20_MASK                    (0x100000U)
74205 #define RGPIO_PIDR_PID20_SHIFT                   (20U)
74206 /*! PID20 - Port Input Disable
74207  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74208  *  0b1..Pin is disabled for general-purpose input.
74209  */
74210 #define RGPIO_PIDR_PID20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID20_SHIFT)) & RGPIO_PIDR_PID20_MASK)
74211 
74212 #define RGPIO_PIDR_PID21_MASK                    (0x200000U)
74213 #define RGPIO_PIDR_PID21_SHIFT                   (21U)
74214 /*! PID21 - Port Input Disable
74215  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74216  *  0b1..Pin is disabled for general-purpose input.
74217  */
74218 #define RGPIO_PIDR_PID21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID21_SHIFT)) & RGPIO_PIDR_PID21_MASK)
74219 
74220 #define RGPIO_PIDR_PID22_MASK                    (0x400000U)
74221 #define RGPIO_PIDR_PID22_SHIFT                   (22U)
74222 /*! PID22 - Port Input Disable
74223  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74224  *  0b1..Pin is disabled for general-purpose input.
74225  */
74226 #define RGPIO_PIDR_PID22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID22_SHIFT)) & RGPIO_PIDR_PID22_MASK)
74227 
74228 #define RGPIO_PIDR_PID23_MASK                    (0x800000U)
74229 #define RGPIO_PIDR_PID23_SHIFT                   (23U)
74230 /*! PID23 - Port Input Disable
74231  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74232  *  0b1..Pin is disabled for general-purpose input.
74233  */
74234 #define RGPIO_PIDR_PID23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID23_SHIFT)) & RGPIO_PIDR_PID23_MASK)
74235 
74236 #define RGPIO_PIDR_PID24_MASK                    (0x1000000U)
74237 #define RGPIO_PIDR_PID24_SHIFT                   (24U)
74238 /*! PID24 - Port Input Disable
74239  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74240  *  0b1..Pin is disabled for general-purpose input.
74241  */
74242 #define RGPIO_PIDR_PID24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID24_SHIFT)) & RGPIO_PIDR_PID24_MASK)
74243 
74244 #define RGPIO_PIDR_PID25_MASK                    (0x2000000U)
74245 #define RGPIO_PIDR_PID25_SHIFT                   (25U)
74246 /*! PID25 - Port Input Disable
74247  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74248  *  0b1..Pin is disabled for general-purpose input.
74249  */
74250 #define RGPIO_PIDR_PID25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID25_SHIFT)) & RGPIO_PIDR_PID25_MASK)
74251 
74252 #define RGPIO_PIDR_PID26_MASK                    (0x4000000U)
74253 #define RGPIO_PIDR_PID26_SHIFT                   (26U)
74254 /*! PID26 - Port Input Disable
74255  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74256  *  0b1..Pin is disabled for general-purpose input.
74257  */
74258 #define RGPIO_PIDR_PID26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID26_SHIFT)) & RGPIO_PIDR_PID26_MASK)
74259 
74260 #define RGPIO_PIDR_PID27_MASK                    (0x8000000U)
74261 #define RGPIO_PIDR_PID27_SHIFT                   (27U)
74262 /*! PID27 - Port Input Disable
74263  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74264  *  0b1..Pin is disabled for general-purpose input.
74265  */
74266 #define RGPIO_PIDR_PID27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID27_SHIFT)) & RGPIO_PIDR_PID27_MASK)
74267 
74268 #define RGPIO_PIDR_PID28_MASK                    (0x10000000U)
74269 #define RGPIO_PIDR_PID28_SHIFT                   (28U)
74270 /*! PID28 - Port Input Disable
74271  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74272  *  0b1..Pin is disabled for general-purpose input.
74273  */
74274 #define RGPIO_PIDR_PID28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID28_SHIFT)) & RGPIO_PIDR_PID28_MASK)
74275 
74276 #define RGPIO_PIDR_PID29_MASK                    (0x20000000U)
74277 #define RGPIO_PIDR_PID29_SHIFT                   (29U)
74278 /*! PID29 - Port Input Disable
74279  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74280  *  0b1..Pin is disabled for general-purpose input.
74281  */
74282 #define RGPIO_PIDR_PID29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID29_SHIFT)) & RGPIO_PIDR_PID29_MASK)
74283 
74284 #define RGPIO_PIDR_PID30_MASK                    (0x40000000U)
74285 #define RGPIO_PIDR_PID30_SHIFT                   (30U)
74286 /*! PID30 - Port Input Disable
74287  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74288  *  0b1..Pin is disabled for general-purpose input.
74289  */
74290 #define RGPIO_PIDR_PID30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID30_SHIFT)) & RGPIO_PIDR_PID30_MASK)
74291 
74292 #define RGPIO_PIDR_PID31_MASK                    (0x80000000U)
74293 #define RGPIO_PIDR_PID31_SHIFT                   (31U)
74294 /*! PID31 - Port Input Disable
74295  *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
74296  *  0b1..Pin is disabled for general-purpose input.
74297  */
74298 #define RGPIO_PIDR_PID31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID31_SHIFT)) & RGPIO_PIDR_PID31_MASK)
74299 /*! @} */
74300 
74301 /*! @name PDR - Pin Data Register a */
74302 /*! @{ */
74303 
74304 #define RGPIO_PDR_PD_MASK                        (0x1U)
74305 #define RGPIO_PDR_PD_SHIFT                       (0U)
74306 /*! PD - Pin Data (input and output)
74307  *  0b0..Pin logic level is logic zero or not configured for use by digital function.
74308  *  0b1..Pin logic level is logic one.
74309  */
74310 #define RGPIO_PDR_PD(x)                          (((uint8_t)(((uint8_t)(x)) << RGPIO_PDR_PD_SHIFT)) & RGPIO_PDR_PD_MASK)
74311 /*! @} */
74312 
74313 /* The count of RGPIO_PDR */
74314 #define RGPIO_PDR_COUNT                          (32U)
74315 
74316 /*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */
74317 /*! @{ */
74318 
74319 #define RGPIO_ICR_IRQC_MASK                      (0xF0000U)
74320 #define RGPIO_ICR_IRQC_SHIFT                     (16U)
74321 /*! IRQC - Interrupt Configuration
74322  *  0b0000..Interrupt Status Flag (ISF) is disabled.
74323  *  0b0001..ISF flag and DMA request on rising edge.
74324  *  0b0010..ISF flag and DMA request on falling edge.
74325  *  0b0011..ISF flag and DMA request on either edge.
74326  *  0b0100..Reserved.
74327  *  0b0101..ISF flag sets on rising edge.
74328  *  0b0110..ISF flag sets on falling edge.
74329  *  0b0111..ISF flag sets on either edge.
74330  *  0b1000..ISF flag and Interrupt when logic 0.
74331  *  0b1001..ISF flag and Interrupt on rising-edge.
74332  *  0b1010..ISF flag and Interrupt on falling-edge.
74333  *  0b1011..ISF flag and Interrupt on either edge.
74334  *  0b1100..ISF flag and Interrupt when logic 1.
74335  *  0b1101..Reserved
74336  *  0b1110..Reserved
74337  *  0b1111..Reserved.
74338  */
74339 #define RGPIO_ICR_IRQC(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQC_SHIFT)) & RGPIO_ICR_IRQC_MASK)
74340 
74341 #define RGPIO_ICR_IRQS_MASK                      (0x100000U)
74342 #define RGPIO_ICR_IRQS_SHIFT                     (20U)
74343 /*! IRQS - Interrupt Select
74344  *  0b0..Interrupt/DMA request 0.
74345  *  0b1..Interrupt/DMA request 1.
74346  */
74347 #define RGPIO_ICR_IRQS(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQS_SHIFT)) & RGPIO_ICR_IRQS_MASK)
74348 
74349 #define RGPIO_ICR_LK_MASK                        (0x800000U)
74350 #define RGPIO_ICR_LK_SHIFT                       (23U)
74351 /*! LK - Lock Register
74352  *  0b0..Interrupt configuration by ICR[23:0] is not locked and can be updated.
74353  *  0b1..Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset.
74354  */
74355 #define RGPIO_ICR_LK(x)                          (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_LK_SHIFT)) & RGPIO_ICR_LK_MASK)
74356 
74357 #define RGPIO_ICR_ISF_MASK                       (0x1000000U)
74358 #define RGPIO_ICR_ISF_SHIFT                      (24U)
74359 /*! ISF - Interrupt Status Flag
74360  *  0b0..Configured interrupt is not detected.
74361  *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
74362  *       corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the
74363  *       flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive
74364  *       interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
74365  */
74366 #define RGPIO_ICR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK)
74367 /*! @} */
74368 
74369 /* The count of RGPIO_ICR */
74370 #define RGPIO_ICR_COUNT                          (32U)
74371 
74372 /*! @name GICLR - Global Interrupt Control Low Register */
74373 /*! @{ */
74374 
74375 #define RGPIO_GICLR_GIWE0_MASK                   (0x1U)
74376 #define RGPIO_GICLR_GIWE0_SHIFT                  (0U)
74377 /*! GIWE0 - Global Interrupt Write Enable
74378  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74379  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74380  */
74381 #define RGPIO_GICLR_GIWE0(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE0_SHIFT)) & RGPIO_GICLR_GIWE0_MASK)
74382 
74383 #define RGPIO_GICLR_GIWE1_MASK                   (0x2U)
74384 #define RGPIO_GICLR_GIWE1_SHIFT                  (1U)
74385 /*! GIWE1 - Global Interrupt Write Enable
74386  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74387  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74388  */
74389 #define RGPIO_GICLR_GIWE1(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE1_SHIFT)) & RGPIO_GICLR_GIWE1_MASK)
74390 
74391 #define RGPIO_GICLR_GIWE2_MASK                   (0x4U)
74392 #define RGPIO_GICLR_GIWE2_SHIFT                  (2U)
74393 /*! GIWE2 - Global Interrupt Write Enable
74394  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74395  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74396  */
74397 #define RGPIO_GICLR_GIWE2(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE2_SHIFT)) & RGPIO_GICLR_GIWE2_MASK)
74398 
74399 #define RGPIO_GICLR_GIWE3_MASK                   (0x8U)
74400 #define RGPIO_GICLR_GIWE3_SHIFT                  (3U)
74401 /*! GIWE3 - Global Interrupt Write Enable
74402  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74403  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74404  */
74405 #define RGPIO_GICLR_GIWE3(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE3_SHIFT)) & RGPIO_GICLR_GIWE3_MASK)
74406 
74407 #define RGPIO_GICLR_GIWE4_MASK                   (0x10U)
74408 #define RGPIO_GICLR_GIWE4_SHIFT                  (4U)
74409 /*! GIWE4 - Global Interrupt Write Enable
74410  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74411  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74412  */
74413 #define RGPIO_GICLR_GIWE4(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE4_SHIFT)) & RGPIO_GICLR_GIWE4_MASK)
74414 
74415 #define RGPIO_GICLR_GIWE5_MASK                   (0x20U)
74416 #define RGPIO_GICLR_GIWE5_SHIFT                  (5U)
74417 /*! GIWE5 - Global Interrupt Write Enable
74418  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74419  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74420  */
74421 #define RGPIO_GICLR_GIWE5(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE5_SHIFT)) & RGPIO_GICLR_GIWE5_MASK)
74422 
74423 #define RGPIO_GICLR_GIWE6_MASK                   (0x40U)
74424 #define RGPIO_GICLR_GIWE6_SHIFT                  (6U)
74425 /*! GIWE6 - Global Interrupt Write Enable
74426  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74427  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74428  */
74429 #define RGPIO_GICLR_GIWE6(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE6_SHIFT)) & RGPIO_GICLR_GIWE6_MASK)
74430 
74431 #define RGPIO_GICLR_GIWE7_MASK                   (0x80U)
74432 #define RGPIO_GICLR_GIWE7_SHIFT                  (7U)
74433 /*! GIWE7 - Global Interrupt Write Enable
74434  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74435  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74436  */
74437 #define RGPIO_GICLR_GIWE7(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE7_SHIFT)) & RGPIO_GICLR_GIWE7_MASK)
74438 
74439 #define RGPIO_GICLR_GIWE8_MASK                   (0x100U)
74440 #define RGPIO_GICLR_GIWE8_SHIFT                  (8U)
74441 /*! GIWE8 - Global Interrupt Write Enable
74442  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74443  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74444  */
74445 #define RGPIO_GICLR_GIWE8(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE8_SHIFT)) & RGPIO_GICLR_GIWE8_MASK)
74446 
74447 #define RGPIO_GICLR_GIWE9_MASK                   (0x200U)
74448 #define RGPIO_GICLR_GIWE9_SHIFT                  (9U)
74449 /*! GIWE9 - Global Interrupt Write Enable
74450  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74451  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74452  */
74453 #define RGPIO_GICLR_GIWE9(x)                     (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE9_SHIFT)) & RGPIO_GICLR_GIWE9_MASK)
74454 
74455 #define RGPIO_GICLR_GIWE10_MASK                  (0x400U)
74456 #define RGPIO_GICLR_GIWE10_SHIFT                 (10U)
74457 /*! GIWE10 - Global Interrupt Write Enable
74458  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74459  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74460  */
74461 #define RGPIO_GICLR_GIWE10(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE10_SHIFT)) & RGPIO_GICLR_GIWE10_MASK)
74462 
74463 #define RGPIO_GICLR_GIWE11_MASK                  (0x800U)
74464 #define RGPIO_GICLR_GIWE11_SHIFT                 (11U)
74465 /*! GIWE11 - Global Interrupt Write Enable
74466  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74467  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74468  */
74469 #define RGPIO_GICLR_GIWE11(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE11_SHIFT)) & RGPIO_GICLR_GIWE11_MASK)
74470 
74471 #define RGPIO_GICLR_GIWE12_MASK                  (0x1000U)
74472 #define RGPIO_GICLR_GIWE12_SHIFT                 (12U)
74473 /*! GIWE12 - Global Interrupt Write Enable
74474  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74475  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74476  */
74477 #define RGPIO_GICLR_GIWE12(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE12_SHIFT)) & RGPIO_GICLR_GIWE12_MASK)
74478 
74479 #define RGPIO_GICLR_GIWE13_MASK                  (0x2000U)
74480 #define RGPIO_GICLR_GIWE13_SHIFT                 (13U)
74481 /*! GIWE13 - Global Interrupt Write Enable
74482  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74483  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74484  */
74485 #define RGPIO_GICLR_GIWE13(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE13_SHIFT)) & RGPIO_GICLR_GIWE13_MASK)
74486 
74487 #define RGPIO_GICLR_GIWE14_MASK                  (0x4000U)
74488 #define RGPIO_GICLR_GIWE14_SHIFT                 (14U)
74489 /*! GIWE14 - Global Interrupt Write Enable
74490  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74491  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74492  */
74493 #define RGPIO_GICLR_GIWE14(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE14_SHIFT)) & RGPIO_GICLR_GIWE14_MASK)
74494 
74495 #define RGPIO_GICLR_GIWE15_MASK                  (0x8000U)
74496 #define RGPIO_GICLR_GIWE15_SHIFT                 (15U)
74497 /*! GIWE15 - Global Interrupt Write Enable
74498  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74499  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74500  */
74501 #define RGPIO_GICLR_GIWE15(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE15_SHIFT)) & RGPIO_GICLR_GIWE15_MASK)
74502 
74503 #define RGPIO_GICLR_GIWD_MASK                    (0xFFFF0000U)
74504 #define RGPIO_GICLR_GIWD_SHIFT                   (16U)
74505 /*! GIWD - Global Interrupt Write Data */
74506 #define RGPIO_GICLR_GIWD(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWD_SHIFT)) & RGPIO_GICLR_GIWD_MASK)
74507 /*! @} */
74508 
74509 /*! @name GICHR - Global Interrupt Control High Register */
74510 /*! @{ */
74511 
74512 #define RGPIO_GICHR_GIWE16_MASK                  (0x1U)
74513 #define RGPIO_GICHR_GIWE16_SHIFT                 (0U)
74514 /*! GIWE16 - Global Interrupt Write Enable
74515  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74516  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74517  */
74518 #define RGPIO_GICHR_GIWE16(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE16_SHIFT)) & RGPIO_GICHR_GIWE16_MASK)
74519 
74520 #define RGPIO_GICHR_GIWE17_MASK                  (0x2U)
74521 #define RGPIO_GICHR_GIWE17_SHIFT                 (1U)
74522 /*! GIWE17 - Global Interrupt Write Enable
74523  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74524  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74525  */
74526 #define RGPIO_GICHR_GIWE17(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE17_SHIFT)) & RGPIO_GICHR_GIWE17_MASK)
74527 
74528 #define RGPIO_GICHR_GIWE18_MASK                  (0x4U)
74529 #define RGPIO_GICHR_GIWE18_SHIFT                 (2U)
74530 /*! GIWE18 - Global Interrupt Write Enable
74531  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74532  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74533  */
74534 #define RGPIO_GICHR_GIWE18(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE18_SHIFT)) & RGPIO_GICHR_GIWE18_MASK)
74535 
74536 #define RGPIO_GICHR_GIWE19_MASK                  (0x8U)
74537 #define RGPIO_GICHR_GIWE19_SHIFT                 (3U)
74538 /*! GIWE19 - Global Interrupt Write Enable
74539  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74540  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74541  */
74542 #define RGPIO_GICHR_GIWE19(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE19_SHIFT)) & RGPIO_GICHR_GIWE19_MASK)
74543 
74544 #define RGPIO_GICHR_GIWE20_MASK                  (0x10U)
74545 #define RGPIO_GICHR_GIWE20_SHIFT                 (4U)
74546 /*! GIWE20 - Global Interrupt Write Enable
74547  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74548  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74549  */
74550 #define RGPIO_GICHR_GIWE20(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE20_SHIFT)) & RGPIO_GICHR_GIWE20_MASK)
74551 
74552 #define RGPIO_GICHR_GIWE21_MASK                  (0x20U)
74553 #define RGPIO_GICHR_GIWE21_SHIFT                 (5U)
74554 /*! GIWE21 - Global Interrupt Write Enable
74555  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74556  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74557  */
74558 #define RGPIO_GICHR_GIWE21(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE21_SHIFT)) & RGPIO_GICHR_GIWE21_MASK)
74559 
74560 #define RGPIO_GICHR_GIWE22_MASK                  (0x40U)
74561 #define RGPIO_GICHR_GIWE22_SHIFT                 (6U)
74562 /*! GIWE22 - Global Interrupt Write Enable
74563  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74564  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74565  */
74566 #define RGPIO_GICHR_GIWE22(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE22_SHIFT)) & RGPIO_GICHR_GIWE22_MASK)
74567 
74568 #define RGPIO_GICHR_GIWE23_MASK                  (0x80U)
74569 #define RGPIO_GICHR_GIWE23_SHIFT                 (7U)
74570 /*! GIWE23 - Global Interrupt Write Enable
74571  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74572  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74573  */
74574 #define RGPIO_GICHR_GIWE23(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE23_SHIFT)) & RGPIO_GICHR_GIWE23_MASK)
74575 
74576 #define RGPIO_GICHR_GIWE24_MASK                  (0x100U)
74577 #define RGPIO_GICHR_GIWE24_SHIFT                 (8U)
74578 /*! GIWE24 - Global Interrupt Write Enable
74579  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74580  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74581  */
74582 #define RGPIO_GICHR_GIWE24(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE24_SHIFT)) & RGPIO_GICHR_GIWE24_MASK)
74583 
74584 #define RGPIO_GICHR_GIWE25_MASK                  (0x200U)
74585 #define RGPIO_GICHR_GIWE25_SHIFT                 (9U)
74586 /*! GIWE25 - Global Interrupt Write Enable
74587  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74588  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74589  */
74590 #define RGPIO_GICHR_GIWE25(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE25_SHIFT)) & RGPIO_GICHR_GIWE25_MASK)
74591 
74592 #define RGPIO_GICHR_GIWE26_MASK                  (0x400U)
74593 #define RGPIO_GICHR_GIWE26_SHIFT                 (10U)
74594 /*! GIWE26 - Global Interrupt Write Enable
74595  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74596  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74597  */
74598 #define RGPIO_GICHR_GIWE26(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE26_SHIFT)) & RGPIO_GICHR_GIWE26_MASK)
74599 
74600 #define RGPIO_GICHR_GIWE27_MASK                  (0x800U)
74601 #define RGPIO_GICHR_GIWE27_SHIFT                 (11U)
74602 /*! GIWE27 - Global Interrupt Write Enable
74603  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74604  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74605  */
74606 #define RGPIO_GICHR_GIWE27(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE27_SHIFT)) & RGPIO_GICHR_GIWE27_MASK)
74607 
74608 #define RGPIO_GICHR_GIWE28_MASK                  (0x1000U)
74609 #define RGPIO_GICHR_GIWE28_SHIFT                 (12U)
74610 /*! GIWE28 - Global Interrupt Write Enable
74611  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74612  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74613  */
74614 #define RGPIO_GICHR_GIWE28(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE28_SHIFT)) & RGPIO_GICHR_GIWE28_MASK)
74615 
74616 #define RGPIO_GICHR_GIWE29_MASK                  (0x2000U)
74617 #define RGPIO_GICHR_GIWE29_SHIFT                 (13U)
74618 /*! GIWE29 - Global Interrupt Write Enable
74619  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74620  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74621  */
74622 #define RGPIO_GICHR_GIWE29(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE29_SHIFT)) & RGPIO_GICHR_GIWE29_MASK)
74623 
74624 #define RGPIO_GICHR_GIWE30_MASK                  (0x4000U)
74625 #define RGPIO_GICHR_GIWE30_SHIFT                 (14U)
74626 /*! GIWE30 - Global Interrupt Write Enable
74627  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74628  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74629  */
74630 #define RGPIO_GICHR_GIWE30(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE30_SHIFT)) & RGPIO_GICHR_GIWE30_MASK)
74631 
74632 #define RGPIO_GICHR_GIWE31_MASK                  (0x8000U)
74633 #define RGPIO_GICHR_GIWE31_SHIFT                 (15U)
74634 /*! GIWE31 - Global Interrupt Write Enable
74635  *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
74636  *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
74637  */
74638 #define RGPIO_GICHR_GIWE31(x)                    (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE31_SHIFT)) & RGPIO_GICHR_GIWE31_MASK)
74639 
74640 #define RGPIO_GICHR_GIWD_MASK                    (0xFFFF0000U)
74641 #define RGPIO_GICHR_GIWD_SHIFT                   (16U)
74642 /*! GIWD - Global Interrupt Write Data */
74643 #define RGPIO_GICHR_GIWD(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWD_SHIFT)) & RGPIO_GICHR_GIWD_MASK)
74644 /*! @} */
74645 
74646 /*! @name ISFR - Interrupt Status Flag Register */
74647 /*! @{ */
74648 
74649 #define RGPIO_ISFR_ISF0_MASK                     (0x1U)
74650 #define RGPIO_ISFR_ISF0_SHIFT                    (0U)
74651 /*! ISF0 - Interrupt Status Flag
74652  *  0b0..Configured interrupt is not detected on the pin of the same number.
74653  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74654  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74655  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74656  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74657  *       after it is cleared.
74658  */
74659 #define RGPIO_ISFR_ISF0(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK)
74660 
74661 #define RGPIO_ISFR_ISF1_MASK                     (0x2U)
74662 #define RGPIO_ISFR_ISF1_SHIFT                    (1U)
74663 /*! ISF1 - Interrupt Status Flag
74664  *  0b0..Configured interrupt is not detected on the pin of the same number.
74665  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74666  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74667  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74668  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74669  *       after it is cleared.
74670  */
74671 #define RGPIO_ISFR_ISF1(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK)
74672 
74673 #define RGPIO_ISFR_ISF2_MASK                     (0x4U)
74674 #define RGPIO_ISFR_ISF2_SHIFT                    (2U)
74675 /*! ISF2 - Interrupt Status Flag
74676  *  0b0..Configured interrupt is not detected on the pin of the same number.
74677  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74678  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74679  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74680  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74681  *       after it is cleared.
74682  */
74683 #define RGPIO_ISFR_ISF2(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK)
74684 
74685 #define RGPIO_ISFR_ISF3_MASK                     (0x8U)
74686 #define RGPIO_ISFR_ISF3_SHIFT                    (3U)
74687 /*! ISF3 - Interrupt Status Flag
74688  *  0b0..Configured interrupt is not detected on the pin of the same number.
74689  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74690  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74691  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74692  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74693  *       after it is cleared.
74694  */
74695 #define RGPIO_ISFR_ISF3(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK)
74696 
74697 #define RGPIO_ISFR_ISF4_MASK                     (0x10U)
74698 #define RGPIO_ISFR_ISF4_SHIFT                    (4U)
74699 /*! ISF4 - Interrupt Status Flag
74700  *  0b0..Configured interrupt is not detected on the pin of the same number.
74701  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74702  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74703  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74704  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74705  *       after it is cleared.
74706  */
74707 #define RGPIO_ISFR_ISF4(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK)
74708 
74709 #define RGPIO_ISFR_ISF5_MASK                     (0x20U)
74710 #define RGPIO_ISFR_ISF5_SHIFT                    (5U)
74711 /*! ISF5 - Interrupt Status Flag
74712  *  0b0..Configured interrupt is not detected on the pin of the same number.
74713  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74714  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74715  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74716  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74717  *       after it is cleared.
74718  */
74719 #define RGPIO_ISFR_ISF5(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK)
74720 
74721 #define RGPIO_ISFR_ISF6_MASK                     (0x40U)
74722 #define RGPIO_ISFR_ISF6_SHIFT                    (6U)
74723 /*! ISF6 - Interrupt Status Flag
74724  *  0b0..Configured interrupt is not detected on the pin of the same number.
74725  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74726  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74727  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74728  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74729  *       after it is cleared.
74730  */
74731 #define RGPIO_ISFR_ISF6(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK)
74732 
74733 #define RGPIO_ISFR_ISF7_MASK                     (0x80U)
74734 #define RGPIO_ISFR_ISF7_SHIFT                    (7U)
74735 /*! ISF7 - Interrupt Status Flag
74736  *  0b0..Configured interrupt is not detected on the pin of the same number.
74737  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74738  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74739  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74740  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74741  *       after it is cleared.
74742  */
74743 #define RGPIO_ISFR_ISF7(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK)
74744 
74745 #define RGPIO_ISFR_ISF8_MASK                     (0x100U)
74746 #define RGPIO_ISFR_ISF8_SHIFT                    (8U)
74747 /*! ISF8 - Interrupt Status Flag
74748  *  0b0..Configured interrupt is not detected on the pin of the same number.
74749  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74750  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74751  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74752  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74753  *       after it is cleared.
74754  */
74755 #define RGPIO_ISFR_ISF8(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK)
74756 
74757 #define RGPIO_ISFR_ISF9_MASK                     (0x200U)
74758 #define RGPIO_ISFR_ISF9_SHIFT                    (9U)
74759 /*! ISF9 - Interrupt Status Flag
74760  *  0b0..Configured interrupt is not detected on the pin of the same number.
74761  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74762  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74763  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74764  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74765  *       after it is cleared.
74766  */
74767 #define RGPIO_ISFR_ISF9(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK)
74768 
74769 #define RGPIO_ISFR_ISF10_MASK                    (0x400U)
74770 #define RGPIO_ISFR_ISF10_SHIFT                   (10U)
74771 /*! ISF10 - Interrupt Status Flag
74772  *  0b0..Configured interrupt is not detected on the pin of the same number.
74773  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74774  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74775  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74776  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74777  *       after it is cleared.
74778  */
74779 #define RGPIO_ISFR_ISF10(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK)
74780 
74781 #define RGPIO_ISFR_ISF11_MASK                    (0x800U)
74782 #define RGPIO_ISFR_ISF11_SHIFT                   (11U)
74783 /*! ISF11 - Interrupt Status Flag
74784  *  0b0..Configured interrupt is not detected on the pin of the same number.
74785  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74786  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74787  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74788  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74789  *       after it is cleared.
74790  */
74791 #define RGPIO_ISFR_ISF11(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK)
74792 
74793 #define RGPIO_ISFR_ISF12_MASK                    (0x1000U)
74794 #define RGPIO_ISFR_ISF12_SHIFT                   (12U)
74795 /*! ISF12 - Interrupt Status Flag
74796  *  0b0..Configured interrupt is not detected on the pin of the same number.
74797  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74798  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74799  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74800  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74801  *       after it is cleared.
74802  */
74803 #define RGPIO_ISFR_ISF12(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK)
74804 
74805 #define RGPIO_ISFR_ISF13_MASK                    (0x2000U)
74806 #define RGPIO_ISFR_ISF13_SHIFT                   (13U)
74807 /*! ISF13 - Interrupt Status Flag
74808  *  0b0..Configured interrupt is not detected on the pin of the same number.
74809  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74810  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74811  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74812  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74813  *       after it is cleared.
74814  */
74815 #define RGPIO_ISFR_ISF13(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK)
74816 
74817 #define RGPIO_ISFR_ISF14_MASK                    (0x4000U)
74818 #define RGPIO_ISFR_ISF14_SHIFT                   (14U)
74819 /*! ISF14 - Interrupt Status Flag
74820  *  0b0..Configured interrupt is not detected on the pin of the same number.
74821  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74822  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74823  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74824  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74825  *       after it is cleared.
74826  */
74827 #define RGPIO_ISFR_ISF14(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK)
74828 
74829 #define RGPIO_ISFR_ISF15_MASK                    (0x8000U)
74830 #define RGPIO_ISFR_ISF15_SHIFT                   (15U)
74831 /*! ISF15 - Interrupt Status Flag
74832  *  0b0..Configured interrupt is not detected on the pin of the same number.
74833  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74834  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74835  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74836  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74837  *       after it is cleared.
74838  */
74839 #define RGPIO_ISFR_ISF15(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK)
74840 
74841 #define RGPIO_ISFR_ISF16_MASK                    (0x10000U)
74842 #define RGPIO_ISFR_ISF16_SHIFT                   (16U)
74843 /*! ISF16 - Interrupt Status Flag
74844  *  0b0..Configured interrupt is not detected on the pin of the same number.
74845  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74846  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74847  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74848  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74849  *       after it is cleared.
74850  */
74851 #define RGPIO_ISFR_ISF16(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK)
74852 
74853 #define RGPIO_ISFR_ISF17_MASK                    (0x20000U)
74854 #define RGPIO_ISFR_ISF17_SHIFT                   (17U)
74855 /*! ISF17 - Interrupt Status Flag
74856  *  0b0..Configured interrupt is not detected on the pin of the same number.
74857  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74858  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74859  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74860  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74861  *       after it is cleared.
74862  */
74863 #define RGPIO_ISFR_ISF17(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK)
74864 
74865 #define RGPIO_ISFR_ISF18_MASK                    (0x40000U)
74866 #define RGPIO_ISFR_ISF18_SHIFT                   (18U)
74867 /*! ISF18 - Interrupt Status Flag
74868  *  0b0..Configured interrupt is not detected on the pin of the same number.
74869  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74870  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74871  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74872  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74873  *       after it is cleared.
74874  */
74875 #define RGPIO_ISFR_ISF18(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK)
74876 
74877 #define RGPIO_ISFR_ISF19_MASK                    (0x80000U)
74878 #define RGPIO_ISFR_ISF19_SHIFT                   (19U)
74879 /*! ISF19 - Interrupt Status Flag
74880  *  0b0..Configured interrupt is not detected on the pin of the same number.
74881  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74882  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74883  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74884  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74885  *       after it is cleared.
74886  */
74887 #define RGPIO_ISFR_ISF19(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK)
74888 
74889 #define RGPIO_ISFR_ISF20_MASK                    (0x100000U)
74890 #define RGPIO_ISFR_ISF20_SHIFT                   (20U)
74891 /*! ISF20 - Interrupt Status Flag
74892  *  0b0..Configured interrupt is not detected on the pin of the same number.
74893  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74894  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74895  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74896  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74897  *       after it is cleared.
74898  */
74899 #define RGPIO_ISFR_ISF20(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK)
74900 
74901 #define RGPIO_ISFR_ISF21_MASK                    (0x200000U)
74902 #define RGPIO_ISFR_ISF21_SHIFT                   (21U)
74903 /*! ISF21 - Interrupt Status Flag
74904  *  0b0..Configured interrupt is not detected on the pin of the same number.
74905  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74906  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74907  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74908  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74909  *       after it is cleared.
74910  */
74911 #define RGPIO_ISFR_ISF21(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK)
74912 
74913 #define RGPIO_ISFR_ISF22_MASK                    (0x400000U)
74914 #define RGPIO_ISFR_ISF22_SHIFT                   (22U)
74915 /*! ISF22 - Interrupt Status Flag
74916  *  0b0..Configured interrupt is not detected on the pin of the same number.
74917  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74918  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74919  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74920  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74921  *       after it is cleared.
74922  */
74923 #define RGPIO_ISFR_ISF22(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK)
74924 
74925 #define RGPIO_ISFR_ISF23_MASK                    (0x800000U)
74926 #define RGPIO_ISFR_ISF23_SHIFT                   (23U)
74927 /*! ISF23 - Interrupt Status Flag
74928  *  0b0..Configured interrupt is not detected on the pin of the same number.
74929  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74930  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74931  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74932  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74933  *       after it is cleared.
74934  */
74935 #define RGPIO_ISFR_ISF23(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK)
74936 
74937 #define RGPIO_ISFR_ISF24_MASK                    (0x1000000U)
74938 #define RGPIO_ISFR_ISF24_SHIFT                   (24U)
74939 /*! ISF24 - Interrupt Status Flag
74940  *  0b0..Configured interrupt is not detected on the pin of the same number.
74941  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74942  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74943  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74944  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74945  *       after it is cleared.
74946  */
74947 #define RGPIO_ISFR_ISF24(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK)
74948 
74949 #define RGPIO_ISFR_ISF25_MASK                    (0x2000000U)
74950 #define RGPIO_ISFR_ISF25_SHIFT                   (25U)
74951 /*! ISF25 - Interrupt Status Flag
74952  *  0b0..Configured interrupt is not detected on the pin of the same number.
74953  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74954  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74955  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74956  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74957  *       after it is cleared.
74958  */
74959 #define RGPIO_ISFR_ISF25(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK)
74960 
74961 #define RGPIO_ISFR_ISF26_MASK                    (0x4000000U)
74962 #define RGPIO_ISFR_ISF26_SHIFT                   (26U)
74963 /*! ISF26 - Interrupt Status Flag
74964  *  0b0..Configured interrupt is not detected on the pin of the same number.
74965  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74966  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74967  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74968  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74969  *       after it is cleared.
74970  */
74971 #define RGPIO_ISFR_ISF26(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK)
74972 
74973 #define RGPIO_ISFR_ISF27_MASK                    (0x8000000U)
74974 #define RGPIO_ISFR_ISF27_SHIFT                   (27U)
74975 /*! ISF27 - Interrupt Status Flag
74976  *  0b0..Configured interrupt is not detected on the pin of the same number.
74977  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74978  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74979  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74980  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74981  *       after it is cleared.
74982  */
74983 #define RGPIO_ISFR_ISF27(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK)
74984 
74985 #define RGPIO_ISFR_ISF28_MASK                    (0x10000000U)
74986 #define RGPIO_ISFR_ISF28_SHIFT                   (28U)
74987 /*! ISF28 - Interrupt Status Flag
74988  *  0b0..Configured interrupt is not detected on the pin of the same number.
74989  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
74990  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
74991  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
74992  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
74993  *       after it is cleared.
74994  */
74995 #define RGPIO_ISFR_ISF28(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK)
74996 
74997 #define RGPIO_ISFR_ISF29_MASK                    (0x20000000U)
74998 #define RGPIO_ISFR_ISF29_SHIFT                   (29U)
74999 /*! ISF29 - Interrupt Status Flag
75000  *  0b0..Configured interrupt is not detected on the pin of the same number.
75001  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
75002  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
75003  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
75004  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
75005  *       after it is cleared.
75006  */
75007 #define RGPIO_ISFR_ISF29(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK)
75008 
75009 #define RGPIO_ISFR_ISF30_MASK                    (0x40000000U)
75010 #define RGPIO_ISFR_ISF30_SHIFT                   (30U)
75011 /*! ISF30 - Interrupt Status Flag
75012  *  0b0..Configured interrupt is not detected on the pin of the same number.
75013  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
75014  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
75015  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
75016  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
75017  *       after it is cleared.
75018  */
75019 #define RGPIO_ISFR_ISF30(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK)
75020 
75021 #define RGPIO_ISFR_ISF31_MASK                    (0x80000000U)
75022 #define RGPIO_ISFR_ISF31_SHIFT                   (31U)
75023 /*! ISF31 - Interrupt Status Flag
75024  *  0b0..Configured interrupt is not detected on the pin of the same number.
75025  *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
75026  *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
75027  *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
75028  *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
75029  *       after it is cleared.
75030  */
75031 #define RGPIO_ISFR_ISF31(x)                      (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK)
75032 /*! @} */
75033 
75034 /* The count of RGPIO_ISFR */
75035 #define RGPIO_ISFR_COUNT                         (2U)
75036 
75037 
75038 /*!
75039  * @}
75040  */ /* end of group RGPIO_Register_Masks */
75041 
75042 
75043 /* RGPIO - Peripheral instance base addresses */
75044 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
75045   /** Peripheral RGPIO1 base address */
75046   #define RGPIO1_BASE                              (0x57400000u)
75047   /** Peripheral RGPIO1 base address */
75048   #define RGPIO1_BASE_NS                           (0x47400000u)
75049   /** Peripheral RGPIO1 base pointer */
75050   #define RGPIO1                                   ((RGPIO_Type *)RGPIO1_BASE)
75051   /** Peripheral RGPIO1 base pointer */
75052   #define RGPIO1_NS                                ((RGPIO_Type *)RGPIO1_BASE_NS)
75053   /** Peripheral RGPIO2 base address */
75054   #define RGPIO2_BASE                              (0x53810000u)
75055   /** Peripheral RGPIO2 base address */
75056   #define RGPIO2_BASE_NS                           (0x43810000u)
75057   /** Peripheral RGPIO2 base pointer */
75058   #define RGPIO2                                   ((RGPIO_Type *)RGPIO2_BASE)
75059   /** Peripheral RGPIO2 base pointer */
75060   #define RGPIO2_NS                                ((RGPIO_Type *)RGPIO2_BASE_NS)
75061   /** Peripheral RGPIO3 base address */
75062   #define RGPIO3_BASE                              (0x53820000u)
75063   /** Peripheral RGPIO3 base address */
75064   #define RGPIO3_BASE_NS                           (0x43820000u)
75065   /** Peripheral RGPIO3 base pointer */
75066   #define RGPIO3                                   ((RGPIO_Type *)RGPIO3_BASE)
75067   /** Peripheral RGPIO3 base pointer */
75068   #define RGPIO3_NS                                ((RGPIO_Type *)RGPIO3_BASE_NS)
75069   /** Peripheral RGPIO4 base address */
75070   #define RGPIO4_BASE                              (0x53830000u)
75071   /** Peripheral RGPIO4 base address */
75072   #define RGPIO4_BASE_NS                           (0x43830000u)
75073   /** Peripheral RGPIO4 base pointer */
75074   #define RGPIO4                                   ((RGPIO_Type *)RGPIO4_BASE)
75075   /** Peripheral RGPIO4 base pointer */
75076   #define RGPIO4_NS                                ((RGPIO_Type *)RGPIO4_BASE_NS)
75077   /** Peripheral RGPIO5 base address */
75078   #define RGPIO5_BASE                              (0x53840000u)
75079   /** Peripheral RGPIO5 base address */
75080   #define RGPIO5_BASE_NS                           (0x43840000u)
75081   /** Peripheral RGPIO5 base pointer */
75082   #define RGPIO5                                   ((RGPIO_Type *)RGPIO5_BASE)
75083   /** Peripheral RGPIO5 base pointer */
75084   #define RGPIO5_NS                                ((RGPIO_Type *)RGPIO5_BASE_NS)
75085   /** Peripheral RGPIO6 base address */
75086   #define RGPIO6_BASE                              (0x53850000u)
75087   /** Peripheral RGPIO6 base address */
75088   #define RGPIO6_BASE_NS                           (0x43850000u)
75089   /** Peripheral RGPIO6 base pointer */
75090   #define RGPIO6                                   ((RGPIO_Type *)RGPIO6_BASE)
75091   /** Peripheral RGPIO6 base pointer */
75092   #define RGPIO6_NS                                ((RGPIO_Type *)RGPIO6_BASE_NS)
75093   /** Array initializer of RGPIO peripheral base addresses */
75094   #define RGPIO_BASE_ADDRS                         { 0u, RGPIO1_BASE, RGPIO2_BASE, RGPIO3_BASE, RGPIO4_BASE, RGPIO5_BASE, RGPIO6_BASE }
75095   /** Array initializer of RGPIO peripheral base pointers */
75096   #define RGPIO_BASE_PTRS                          { (RGPIO_Type *)0u, RGPIO1, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6 }
75097   /** Array initializer of RGPIO peripheral base addresses */
75098   #define RGPIO_BASE_ADDRS_NS                      { 0u, RGPIO1_BASE_NS, RGPIO2_BASE_NS, RGPIO3_BASE_NS, RGPIO4_BASE_NS, RGPIO5_BASE_NS, RGPIO6_BASE_NS }
75099   /** Array initializer of RGPIO peripheral base pointers */
75100   #define RGPIO_BASE_PTRS_NS                       { (RGPIO_Type *)0u, RGPIO1_NS, RGPIO2_NS, RGPIO3_NS, RGPIO4_NS, RGPIO5_NS, RGPIO6_NS }
75101 #else
75102   /** Peripheral RGPIO1 base address */
75103   #define RGPIO1_BASE                              (0x47400000u)
75104   /** Peripheral RGPIO1 base pointer */
75105   #define RGPIO1                                   ((RGPIO_Type *)RGPIO1_BASE)
75106   /** Peripheral RGPIO2 base address */
75107   #define RGPIO2_BASE                              (0x43810000u)
75108   /** Peripheral RGPIO2 base pointer */
75109   #define RGPIO2                                   ((RGPIO_Type *)RGPIO2_BASE)
75110   /** Peripheral RGPIO3 base address */
75111   #define RGPIO3_BASE                              (0x43820000u)
75112   /** Peripheral RGPIO3 base pointer */
75113   #define RGPIO3                                   ((RGPIO_Type *)RGPIO3_BASE)
75114   /** Peripheral RGPIO4 base address */
75115   #define RGPIO4_BASE                              (0x43830000u)
75116   /** Peripheral RGPIO4 base pointer */
75117   #define RGPIO4                                   ((RGPIO_Type *)RGPIO4_BASE)
75118   /** Peripheral RGPIO5 base address */
75119   #define RGPIO5_BASE                              (0x43840000u)
75120   /** Peripheral RGPIO5 base pointer */
75121   #define RGPIO5                                   ((RGPIO_Type *)RGPIO5_BASE)
75122   /** Peripheral RGPIO6 base address */
75123   #define RGPIO6_BASE                              (0x43850000u)
75124   /** Peripheral RGPIO6 base pointer */
75125   #define RGPIO6                                   ((RGPIO_Type *)RGPIO6_BASE)
75126   /** Array initializer of RGPIO peripheral base addresses */
75127   #define RGPIO_BASE_ADDRS                         { 0u, RGPIO1_BASE, RGPIO2_BASE, RGPIO3_BASE, RGPIO4_BASE, RGPIO5_BASE, RGPIO6_BASE }
75128   /** Array initializer of RGPIO peripheral base pointers */
75129   #define RGPIO_BASE_PTRS                          { (RGPIO_Type *)0u, RGPIO1, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6 }
75130 #endif
75131 /** Interrupt vectors for the RGPIO peripheral type */
75132 #define RGPIO_CH0_IRQS                           { NotAvail_IRQn, GPIO1_0_IRQn, GPIO2_0_IRQn, GPIO3_0_IRQn, GPIO4_IRQn, GPIO5_IRQn, GPIO6_IRQn }
75133 #define RGPIO_CH1_IRQS                           { NotAvail_IRQn, GPIO1_1_IRQn, GPIO2_1_IRQn, GPIO3_1_IRQn, GPIO4_IRQn, GPIO5_IRQn, GPIO6_IRQn }
75134 
75135 /*!
75136  * @}
75137  */ /* end of group RGPIO_Peripheral_Access_Layer */
75138 
75139 
75140 /* ----------------------------------------------------------------------------
75141    -- RTWDOG Peripheral Access Layer
75142    ---------------------------------------------------------------------------- */
75143 
75144 /*!
75145  * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
75146  * @{
75147  */
75148 
75149 /** RTWDOG - Register Layout Typedef */
75150 typedef struct {
75151   __IO uint32_t CS;                                /**< WDOG Control and Status, offset: 0x0 */
75152   __IO uint32_t CNT;                               /**< WDOG Counter, offset: 0x4 */
75153   __IO uint32_t TOVAL;                             /**< WDOG Timeout Value, offset: 0x8 */
75154   __IO uint32_t WIN;                               /**< Watchdog Window, offset: 0xC */
75155 } RTWDOG_Type;
75156 
75157 /* ----------------------------------------------------------------------------
75158    -- RTWDOG Register Masks
75159    ---------------------------------------------------------------------------- */
75160 
75161 /*!
75162  * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
75163  * @{
75164  */
75165 
75166 /*! @name CS - WDOG Control and Status */
75167 /*! @{ */
75168 
75169 #define RTWDOG_CS_STOP_MASK                      (0x1U)
75170 #define RTWDOG_CS_STOP_SHIFT                     (0U)
75171 /*! STOP - Stop Enable
75172  *  0b0..Disable
75173  *  0b1..Enable
75174  */
75175 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
75176 
75177 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
75178 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
75179 /*! WAIT - Wait Enable
75180  *  0b0..Disable
75181  *  0b1..Enable
75182  */
75183 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
75184 
75185 #define RTWDOG_CS_DBG_MASK                       (0x4U)
75186 #define RTWDOG_CS_DBG_SHIFT                      (2U)
75187 /*! DBG - Debug Enable
75188  *  0b0..Disable
75189  *  0b1..Enable
75190  */
75191 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
75192 
75193 #define RTWDOG_CS_TST_MASK                       (0x18U)
75194 #define RTWDOG_CS_TST_SHIFT                      (3U)
75195 /*! TST - WDOG Test
75196  *  0b00..Disable WDOG Test mode
75197  *  0b01..Enable WDOG User mode
75198  *  0b10-0b11..Enable WDOG Test mode
75199  */
75200 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
75201 
75202 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
75203 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
75204 /*! UPDATE - Updates Allowed
75205  *  0b0..Updates not allowed
75206  *  0b1..Updates allowed
75207  */
75208 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
75209 
75210 #define RTWDOG_CS_INT_MASK                       (0x40U)
75211 #define RTWDOG_CS_INT_SHIFT                      (6U)
75212 /*! INT - WDOG Interrupt
75213  *  0b0..Disable
75214  *  0b1..Enable
75215  */
75216 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
75217 
75218 #define RTWDOG_CS_EN_MASK                        (0x80U)
75219 #define RTWDOG_CS_EN_SHIFT                       (7U)
75220 /*! EN - WDOG Enable
75221  *  0b0..Disable
75222  *  0b1..Enable
75223  */
75224 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
75225 
75226 #define RTWDOG_CS_CLK_MASK                       (0x300U)
75227 #define RTWDOG_CS_CLK_SHIFT                      (8U)
75228 /*! CLK - WDOG Clock */
75229 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
75230 
75231 #define RTWDOG_CS_RCS_MASK                       (0x400U)
75232 #define RTWDOG_CS_RCS_SHIFT                      (10U)
75233 /*! RCS - Reconfiguration Success
75234  *  0b0..Unsuccessful
75235  *  0b1..Successful
75236  */
75237 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
75238 
75239 #define RTWDOG_CS_ULK_MASK                       (0x800U)
75240 #define RTWDOG_CS_ULK_SHIFT                      (11U)
75241 /*! ULK - Unlock Status
75242  *  0b0..Locked
75243  *  0b1..Unlocked
75244  */
75245 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
75246 
75247 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
75248 #define RTWDOG_CS_PRES_SHIFT                     (12U)
75249 /*! PRES - WDOG Prescaler
75250  *  0b0..Disable
75251  *  0b1..Enable
75252  */
75253 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
75254 
75255 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
75256 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
75257 /*! CMD32EN - Command 32 Enable
75258  *  0b0..Disable
75259  *  0b1..Enable
75260  */
75261 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
75262 
75263 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
75264 #define RTWDOG_CS_FLG_SHIFT                      (14U)
75265 /*! FLG - WDOG Interrupt Flag
75266  *  0b0..No interrupt occurred
75267  *  0b1..An interrupt occurred
75268  */
75269 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
75270 
75271 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
75272 #define RTWDOG_CS_WIN_SHIFT                      (15U)
75273 /*! WIN - WDOG Window
75274  *  0b0..Disable
75275  *  0b1..Enable
75276  */
75277 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
75278 /*! @} */
75279 
75280 /*! @name CNT - WDOG Counter */
75281 /*! @{ */
75282 
75283 #define RTWDOG_CNT_CNTLOW_MASK                   (0xFFU)
75284 #define RTWDOG_CNT_CNTLOW_SHIFT                  (0U)
75285 /*! CNTLOW - Counter High Byte */
75286 #define RTWDOG_CNT_CNTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
75287 
75288 #define RTWDOG_CNT_CNTHIGH_MASK                  (0xFF00U)
75289 #define RTWDOG_CNT_CNTHIGH_SHIFT                 (8U)
75290 /*! CNTHIGH - Counter Low Byte */
75291 #define RTWDOG_CNT_CNTHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
75292 /*! @} */
75293 
75294 /*! @name TOVAL - WDOG Timeout Value */
75295 /*! @{ */
75296 
75297 #define RTWDOG_TOVAL_TOVALLOW_MASK               (0xFFU)
75298 #define RTWDOG_TOVAL_TOVALLOW_SHIFT              (0U)
75299 /*! TOVALLOW - Timeout Value Low */
75300 #define RTWDOG_TOVAL_TOVALLOW(x)                 (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
75301 
75302 #define RTWDOG_TOVAL_TOVALHIGH_MASK              (0xFF00U)
75303 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT             (8U)
75304 /*! TOVALHIGH - Timeout Value High */
75305 #define RTWDOG_TOVAL_TOVALHIGH(x)                (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
75306 /*! @} */
75307 
75308 /*! @name WIN - Watchdog Window */
75309 /*! @{ */
75310 
75311 #define RTWDOG_WIN_WINLOW_MASK                   (0xFFU)
75312 #define RTWDOG_WIN_WINLOW_SHIFT                  (0U)
75313 /*! WINLOW - Low Byte */
75314 #define RTWDOG_WIN_WINLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
75315 
75316 #define RTWDOG_WIN_WINHIGH_MASK                  (0xFF00U)
75317 #define RTWDOG_WIN_WINHIGH_SHIFT                 (8U)
75318 /*! WINHIGH - High Byte */
75319 #define RTWDOG_WIN_WINHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
75320 /*! @} */
75321 
75322 
75323 /*!
75324  * @}
75325  */ /* end of group RTWDOG_Register_Masks */
75326 
75327 
75328 /* RTWDOG - Peripheral instance base addresses */
75329 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
75330   /** Peripheral RTWDOG1 base address */
75331   #define RTWDOG1_BASE                             (0x542D0000u)
75332   /** Peripheral RTWDOG1 base address */
75333   #define RTWDOG1_BASE_NS                          (0x442D0000u)
75334   /** Peripheral RTWDOG1 base pointer */
75335   #define RTWDOG1                                  ((RTWDOG_Type *)RTWDOG1_BASE)
75336   /** Peripheral RTWDOG1 base pointer */
75337   #define RTWDOG1_NS                               ((RTWDOG_Type *)RTWDOG1_BASE_NS)
75338   /** Peripheral RTWDOG2 base address */
75339   #define RTWDOG2_BASE                             (0x542E0000u)
75340   /** Peripheral RTWDOG2 base address */
75341   #define RTWDOG2_BASE_NS                          (0x442E0000u)
75342   /** Peripheral RTWDOG2 base pointer */
75343   #define RTWDOG2                                  ((RTWDOG_Type *)RTWDOG2_BASE)
75344   /** Peripheral RTWDOG2 base pointer */
75345   #define RTWDOG2_NS                               ((RTWDOG_Type *)RTWDOG2_BASE_NS)
75346   /** Peripheral RTWDOG3 base address */
75347   #define RTWDOG3_BASE                             (0x52490000u)
75348   /** Peripheral RTWDOG3 base address */
75349   #define RTWDOG3_BASE_NS                          (0x42490000u)
75350   /** Peripheral RTWDOG3 base pointer */
75351   #define RTWDOG3                                  ((RTWDOG_Type *)RTWDOG3_BASE)
75352   /** Peripheral RTWDOG3 base pointer */
75353   #define RTWDOG3_NS                               ((RTWDOG_Type *)RTWDOG3_BASE_NS)
75354   /** Peripheral RTWDOG4 base address */
75355   #define RTWDOG4_BASE                             (0x524A0000u)
75356   /** Peripheral RTWDOG4 base address */
75357   #define RTWDOG4_BASE_NS                          (0x424A0000u)
75358   /** Peripheral RTWDOG4 base pointer */
75359   #define RTWDOG4                                  ((RTWDOG_Type *)RTWDOG4_BASE)
75360   /** Peripheral RTWDOG4 base pointer */
75361   #define RTWDOG4_NS                               ((RTWDOG_Type *)RTWDOG4_BASE_NS)
75362   /** Peripheral RTWDOG5 base address */
75363   #define RTWDOG5_BASE                             (0x524B0000u)
75364   /** Peripheral RTWDOG5 base address */
75365   #define RTWDOG5_BASE_NS                          (0x424B0000u)
75366   /** Peripheral RTWDOG5 base pointer */
75367   #define RTWDOG5                                  ((RTWDOG_Type *)RTWDOG5_BASE)
75368   /** Peripheral RTWDOG5 base pointer */
75369   #define RTWDOG5_NS                               ((RTWDOG_Type *)RTWDOG5_BASE_NS)
75370   /** Array initializer of RTWDOG peripheral base addresses */
75371   #define RTWDOG_BASE_ADDRS                        { 0u, RTWDOG1_BASE, RTWDOG2_BASE, RTWDOG3_BASE, RTWDOG4_BASE, RTWDOG5_BASE }
75372   /** Array initializer of RTWDOG peripheral base pointers */
75373   #define RTWDOG_BASE_PTRS                         { (RTWDOG_Type *)0u, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 }
75374   /** Array initializer of RTWDOG peripheral base addresses */
75375   #define RTWDOG_BASE_ADDRS_NS                     { 0u, RTWDOG1_BASE_NS, RTWDOG2_BASE_NS, RTWDOG3_BASE_NS, RTWDOG4_BASE_NS, RTWDOG5_BASE_NS }
75376   /** Array initializer of RTWDOG peripheral base pointers */
75377   #define RTWDOG_BASE_PTRS_NS                      { (RTWDOG_Type *)0u, RTWDOG1_NS, RTWDOG2_NS, RTWDOG3_NS, RTWDOG4_NS, RTWDOG5_NS }
75378 #else
75379   /** Peripheral RTWDOG1 base address */
75380   #define RTWDOG1_BASE                             (0x442D0000u)
75381   /** Peripheral RTWDOG1 base pointer */
75382   #define RTWDOG1                                  ((RTWDOG_Type *)RTWDOG1_BASE)
75383   /** Peripheral RTWDOG2 base address */
75384   #define RTWDOG2_BASE                             (0x442E0000u)
75385   /** Peripheral RTWDOG2 base pointer */
75386   #define RTWDOG2                                  ((RTWDOG_Type *)RTWDOG2_BASE)
75387   /** Peripheral RTWDOG3 base address */
75388   #define RTWDOG3_BASE                             (0x42490000u)
75389   /** Peripheral RTWDOG3 base pointer */
75390   #define RTWDOG3                                  ((RTWDOG_Type *)RTWDOG3_BASE)
75391   /** Peripheral RTWDOG4 base address */
75392   #define RTWDOG4_BASE                             (0x424A0000u)
75393   /** Peripheral RTWDOG4 base pointer */
75394   #define RTWDOG4                                  ((RTWDOG_Type *)RTWDOG4_BASE)
75395   /** Peripheral RTWDOG5 base address */
75396   #define RTWDOG5_BASE                             (0x424B0000u)
75397   /** Peripheral RTWDOG5 base pointer */
75398   #define RTWDOG5                                  ((RTWDOG_Type *)RTWDOG5_BASE)
75399   /** Array initializer of RTWDOG peripheral base addresses */
75400   #define RTWDOG_BASE_ADDRS                        { 0u, RTWDOG1_BASE, RTWDOG2_BASE, RTWDOG3_BASE, RTWDOG4_BASE, RTWDOG5_BASE }
75401   /** Array initializer of RTWDOG peripheral base pointers */
75402   #define RTWDOG_BASE_PTRS                         { (RTWDOG_Type *)0u, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 }
75403 #endif
75404 /** Interrupt vectors for the RTWDOG peripheral type */
75405 #define RTWDOG_IRQS                              { NotAvail_IRQn, RTWDOG1_IRQn, RTWDOG2_IRQn, RTWDOG3_IRQn, RTWDOG4_IRQn, RTWDOG5_IRQn }
75406 /* Extra definition */
75407 #define RTWDOG_UPDATE_KEY                        (0xD928C520U)
75408 #define RTWDOG_REFRESH_KEY                       (0xB480A602U)
75409 
75410 
75411 /*!
75412  * @}
75413  */ /* end of group RTWDOG_Peripheral_Access_Layer */
75414 
75415 
75416 /* ----------------------------------------------------------------------------
75417    -- S3MU Peripheral Access Layer
75418    ---------------------------------------------------------------------------- */
75419 
75420 /*!
75421  * @addtogroup S3MU_Peripheral_Access_Layer S3MU Peripheral Access Layer
75422  * @{
75423  */
75424 
75425 /** S3MU - Register Layout Typedef */
75426 typedef struct {
75427   __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
75428   __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
75429        uint32_t UNUSED0;                           /**< Unused Register 0, offset: 0x8 */
75430   __I  uint32_t SR;                                /**< Status Register, offset: 0xC */
75431        uint8_t RESERVED_0[272];
75432   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0x120 */
75433   __I  uint32_t TSR;                               /**< Transmit Status Register, offset: 0x124 */
75434   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x128 */
75435   __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x12C */
75436        uint8_t RESERVED_1[204];
75437   __IO uint32_t UNUSED1;                           /**< Unused Register 1, offset: 0x1FC */
75438   __O  uint32_t TR[8];                             /**< Transmit Register, array offset: 0x200, array step: 0x4 */
75439        uint8_t RESERVED_2[96];
75440   __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x280, array step: 0x4 */
75441 } S3MU_Type;
75442 
75443 /* ----------------------------------------------------------------------------
75444    -- S3MU Register Masks
75445    ---------------------------------------------------------------------------- */
75446 
75447 /*!
75448  * @addtogroup S3MU_Register_Masks S3MU Register Masks
75449  * @{
75450  */
75451 
75452 /*! @name VER - Version ID Register */
75453 /*! @{ */
75454 
75455 #define S3MU_VER_FEATURE_MASK                    (0xFFFFU)
75456 #define S3MU_VER_FEATURE_SHIFT                   (0U)
75457 /*! FEATURE - Feature Set Number
75458  *  0b0000000000000000..Standard features are implemented.
75459  */
75460 #define S3MU_VER_FEATURE(x)                      (((uint32_t)(((uint32_t)(x)) << S3MU_VER_FEATURE_SHIFT)) & S3MU_VER_FEATURE_MASK)
75461 
75462 #define S3MU_VER_MINOR_MASK                      (0xFF0000U)
75463 #define S3MU_VER_MINOR_SHIFT                     (16U)
75464 /*! MINOR - Minor Version Number (0x00 ) */
75465 #define S3MU_VER_MINOR(x)                        (((uint32_t)(((uint32_t)(x)) << S3MU_VER_MINOR_SHIFT)) & S3MU_VER_MINOR_MASK)
75466 
75467 #define S3MU_VER_MAJOR_MASK                      (0xFF000000U)
75468 #define S3MU_VER_MAJOR_SHIFT                     (24U)
75469 /*! MAJOR - Major Version Number (0x01 ) */
75470 #define S3MU_VER_MAJOR(x)                        (((uint32_t)(((uint32_t)(x)) << S3MU_VER_MAJOR_SHIFT)) & S3MU_VER_MAJOR_MASK)
75471 /*! @} */
75472 
75473 /*! @name PAR - Parameter Register */
75474 /*! @{ */
75475 
75476 #define S3MU_PAR_TR_NUM_MASK                     (0xFFU)
75477 #define S3MU_PAR_TR_NUM_SHIFT                    (0U)
75478 /*! TR_NUM - Number of Transmit (TRn) registers (8) */
75479 #define S3MU_PAR_TR_NUM(x)                       (((uint32_t)(((uint32_t)(x)) << S3MU_PAR_TR_NUM_SHIFT)) & S3MU_PAR_TR_NUM_MASK)
75480 
75481 #define S3MU_PAR_RR_NUM_MASK                     (0xFF00U)
75482 #define S3MU_PAR_RR_NUM_SHIFT                    (8U)
75483 /*! RR_NUM - Number of Receive (RRn) registers (4) */
75484 #define S3MU_PAR_RR_NUM(x)                       (((uint32_t)(((uint32_t)(x)) << S3MU_PAR_RR_NUM_SHIFT)) & S3MU_PAR_RR_NUM_MASK)
75485 /*! @} */
75486 
75487 /*! @name SR - Status Register */
75488 /*! @{ */
75489 
75490 #define S3MU_SR_TEP_MASK                         (0x20U)
75491 #define S3MU_SR_TEP_SHIFT                        (5U)
75492 /*! TEP - Transmit Empty Pending */
75493 #define S3MU_SR_TEP(x)                           (((uint32_t)(((uint32_t)(x)) << S3MU_SR_TEP_SHIFT)) & S3MU_SR_TEP_MASK)
75494 
75495 #define S3MU_SR_RFP_MASK                         (0x40U)
75496 #define S3MU_SR_RFP_SHIFT                        (6U)
75497 /*! RFP - Receive Full Pending Flag
75498  *  0b0..No data is ready to be read. All RSR[RFn] bits are clear.
75499  *  0b1..Data is ready to be read. One or more RSR[RFn] bits are set.
75500  */
75501 #define S3MU_SR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << S3MU_SR_RFP_SHIFT)) & S3MU_SR_RFP_MASK)
75502 /*! @} */
75503 
75504 /*! @name TCR - Transmit Control Register */
75505 /*! @{ */
75506 
75507 #define S3MU_TCR_TEIEn_MASK                      (0xFFU)
75508 #define S3MU_TCR_TEIEn_SHIFT                     (0U)
75509 /*! TEIEn - Transmit Register n Empty Interrupt Enable */
75510 #define S3MU_TCR_TEIEn(x)                        (((uint32_t)(((uint32_t)(x)) << S3MU_TCR_TEIEn_SHIFT)) & S3MU_TCR_TEIEn_MASK)
75511 /*! @} */
75512 
75513 /*! @name TSR - Transmit Status Register */
75514 /*! @{ */
75515 
75516 #define S3MU_TSR_TEn_MASK                        (0xFFU)
75517 #define S3MU_TSR_TEn_SHIFT                       (0U)
75518 /*! TEn - Transmit Register n Empty */
75519 #define S3MU_TSR_TEn(x)                          (((uint32_t)(((uint32_t)(x)) << S3MU_TSR_TEn_SHIFT)) & S3MU_TSR_TEn_MASK)
75520 /*! @} */
75521 
75522 /*! @name RCR - Receive Control Register */
75523 /*! @{ */
75524 
75525 #define S3MU_RCR_RFIEn_MASK                      (0xFU)
75526 #define S3MU_RCR_RFIEn_SHIFT                     (0U)
75527 /*! RFIEn - Receive Register n Full Interrupt Enable */
75528 #define S3MU_RCR_RFIEn(x)                        (((uint32_t)(((uint32_t)(x)) << S3MU_RCR_RFIEn_SHIFT)) & S3MU_RCR_RFIEn_MASK)
75529 /*! @} */
75530 
75531 /*! @name RSR - Receive Status Register */
75532 /*! @{ */
75533 
75534 #define S3MU_RSR_RFn_MASK                        (0xFU)
75535 #define S3MU_RSR_RFn_SHIFT                       (0U)
75536 /*! RFn - Receive Register n Full */
75537 #define S3MU_RSR_RFn(x)                          (((uint32_t)(((uint32_t)(x)) << S3MU_RSR_RFn_SHIFT)) & S3MU_RSR_RFn_MASK)
75538 /*! @} */
75539 
75540 /*! @name UNUSED1 - Unused Register 1 */
75541 /*! @{ */
75542 
75543 #define S3MU_UNUSED1_DATA16_MASK                 (0xFFFFU)
75544 #define S3MU_UNUSED1_DATA16_SHIFT                (0U)
75545 /*! DATA16 - Unused 16-bit Register */
75546 #define S3MU_UNUSED1_DATA16(x)                   (((uint32_t)(((uint32_t)(x)) << S3MU_UNUSED1_DATA16_SHIFT)) & S3MU_UNUSED1_DATA16_MASK)
75547 /*! @} */
75548 
75549 /*! @name TR - Transmit Register */
75550 /*! @{ */
75551 
75552 #define S3MU_TR_TR_DATA_MASK                     (0xFFFFFFFFU)
75553 #define S3MU_TR_TR_DATA_SHIFT                    (0U)
75554 /*! TR_DATA - Transmit Data */
75555 #define S3MU_TR_TR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << S3MU_TR_TR_DATA_SHIFT)) & S3MU_TR_TR_DATA_MASK)
75556 /*! @} */
75557 
75558 /* The count of S3MU_TR */
75559 #define S3MU_TR_COUNT                            (8U)
75560 
75561 /*! @name RR - Receive Register */
75562 /*! @{ */
75563 
75564 #define S3MU_RR_RR_DATA_MASK                     (0xFFFFFFFFU)
75565 #define S3MU_RR_RR_DATA_SHIFT                    (0U)
75566 /*! RR_DATA - Receive Data */
75567 #define S3MU_RR_RR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << S3MU_RR_RR_DATA_SHIFT)) & S3MU_RR_RR_DATA_MASK)
75568 /*! @} */
75569 
75570 /* The count of S3MU_RR */
75571 #define S3MU_RR_COUNT                            (4U)
75572 
75573 
75574 /*!
75575  * @}
75576  */ /* end of group S3MU_Register_Masks */
75577 
75578 
75579 /* S3MU - Peripheral instance base addresses */
75580 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
75581   /** Peripheral MU_APPS_S3MUA base address */
75582   #define MU_APPS_S3MUA_BASE                       (0x57520000u)
75583   /** Peripheral MU_APPS_S3MUA base address */
75584   #define MU_APPS_S3MUA_BASE_NS                    (0x47520000u)
75585   /** Peripheral MU_APPS_S3MUA base pointer */
75586   #define MU_APPS_S3MUA                            ((S3MU_Type *)MU_APPS_S3MUA_BASE)
75587   /** Peripheral MU_APPS_S3MUA base pointer */
75588   #define MU_APPS_S3MUA_NS                         ((S3MU_Type *)MU_APPS_S3MUA_BASE_NS)
75589   /** Peripheral MU_RT_S3MUA base address */
75590   #define MU_RT_S3MUA_BASE                         (0x57540000u)
75591   /** Peripheral MU_RT_S3MUA base address */
75592   #define MU_RT_S3MUA_BASE_NS                      (0x47540000u)
75593   /** Peripheral MU_RT_S3MUA base pointer */
75594   #define MU_RT_S3MUA                              ((S3MU_Type *)MU_RT_S3MUA_BASE)
75595   /** Peripheral MU_RT_S3MUA base pointer */
75596   #define MU_RT_S3MUA_NS                           ((S3MU_Type *)MU_RT_S3MUA_BASE_NS)
75597   /** Array initializer of S3MU peripheral base addresses */
75598   #define S3MU_BASE_ADDRS                          { MU_APPS_S3MUA_BASE, MU_RT_S3MUA_BASE }
75599   /** Array initializer of S3MU peripheral base pointers */
75600   #define S3MU_BASE_PTRS                           { MU_APPS_S3MUA, MU_RT_S3MUA }
75601   /** Array initializer of S3MU peripheral base addresses */
75602   #define S3MU_BASE_ADDRS_NS                       { MU_APPS_S3MUA_BASE_NS, MU_RT_S3MUA_BASE_NS }
75603   /** Array initializer of S3MU peripheral base pointers */
75604   #define S3MU_BASE_PTRS_NS                        { MU_APPS_S3MUA_NS, MU_RT_S3MUA_NS }
75605 #else
75606   /** Peripheral MU_APPS_S3MUA base address */
75607   #define MU_APPS_S3MUA_BASE                       (0x47520000u)
75608   /** Peripheral MU_APPS_S3MUA base pointer */
75609   #define MU_APPS_S3MUA                            ((S3MU_Type *)MU_APPS_S3MUA_BASE)
75610   /** Peripheral MU_RT_S3MUA base address */
75611   #define MU_RT_S3MUA_BASE                         (0x47540000u)
75612   /** Peripheral MU_RT_S3MUA base pointer */
75613   #define MU_RT_S3MUA                              ((S3MU_Type *)MU_RT_S3MUA_BASE)
75614   /** Array initializer of S3MU peripheral base addresses */
75615   #define S3MU_BASE_ADDRS                          { MU_APPS_S3MUA_BASE, MU_RT_S3MUA_BASE }
75616   /** Array initializer of S3MU peripheral base pointers */
75617   #define S3MU_BASE_PTRS                           { MU_APPS_S3MUA, MU_RT_S3MUA }
75618 #endif
75619 
75620 /*!
75621  * @}
75622  */ /* end of group S3MU_Peripheral_Access_Layer */
75623 
75624 
75625 /* ----------------------------------------------------------------------------
75626    -- SEMA42 Peripheral Access Layer
75627    ---------------------------------------------------------------------------- */
75628 
75629 /*!
75630  * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
75631  * @{
75632  */
75633 
75634 /** SEMA42 - Register Layout Typedef */
75635 typedef struct {
75636   __IO uint8_t GATE3;                              /**< Gate, offset: 0x0 */
75637   __IO uint8_t GATE2;                              /**< Gate, offset: 0x1 */
75638   __IO uint8_t GATE1;                              /**< Gate, offset: 0x2 */
75639   __IO uint8_t GATE0;                              /**< Gate, offset: 0x3 */
75640   __IO uint8_t GATE7;                              /**< Gate, offset: 0x4 */
75641   __IO uint8_t GATE6;                              /**< Gate, offset: 0x5 */
75642   __IO uint8_t GATE5;                              /**< Gate, offset: 0x6 */
75643   __IO uint8_t GATE4;                              /**< Gate, offset: 0x7 */
75644   __IO uint8_t GATE11;                             /**< Gate, offset: 0x8 */
75645   __IO uint8_t GATE10;                             /**< Gate, offset: 0x9 */
75646   __IO uint8_t GATE9;                              /**< Gate, offset: 0xA */
75647   __IO uint8_t GATE8;                              /**< Gate, offset: 0xB */
75648   __IO uint8_t GATE15;                             /**< Gate, offset: 0xC */
75649   __IO uint8_t GATE14;                             /**< Gate, offset: 0xD */
75650   __IO uint8_t GATE13;                             /**< Gate, offset: 0xE */
75651   __IO uint8_t GATE12;                             /**< Gate, offset: 0xF */
75652   __IO uint8_t GATE19;                             /**< Gate, offset: 0x10 */
75653   __IO uint8_t GATE18;                             /**< Gate, offset: 0x11 */
75654   __IO uint8_t GATE17;                             /**< Gate, offset: 0x12 */
75655   __IO uint8_t GATE16;                             /**< Gate, offset: 0x13 */
75656   __IO uint8_t GATE23;                             /**< Gate, offset: 0x14 */
75657   __IO uint8_t GATE22;                             /**< Gate, offset: 0x15 */
75658   __IO uint8_t GATE21;                             /**< Gate, offset: 0x16 */
75659   __IO uint8_t GATE20;                             /**< Gate, offset: 0x17 */
75660   __IO uint8_t GATE27;                             /**< Gate, offset: 0x18 */
75661   __IO uint8_t GATE26;                             /**< Gate, offset: 0x19 */
75662   __IO uint8_t GATE25;                             /**< Gate, offset: 0x1A */
75663   __IO uint8_t GATE24;                             /**< Gate, offset: 0x1B */
75664   __IO uint8_t GATE31;                             /**< Gate, offset: 0x1C */
75665   __IO uint8_t GATE30;                             /**< Gate, offset: 0x1D */
75666   __IO uint8_t GATE29;                             /**< Gate, offset: 0x1E */
75667   __IO uint8_t GATE28;                             /**< Gate, offset: 0x1F */
75668   __IO uint8_t GATE35;                             /**< Gate, offset: 0x20 */
75669   __IO uint8_t GATE34;                             /**< Gate, offset: 0x21 */
75670   __IO uint8_t GATE33;                             /**< Gate, offset: 0x22 */
75671   __IO uint8_t GATE32;                             /**< Gate, offset: 0x23 */
75672   __IO uint8_t GATE39;                             /**< Gate, offset: 0x24 */
75673   __IO uint8_t GATE38;                             /**< Gate, offset: 0x25 */
75674   __IO uint8_t GATE37;                             /**< Gate, offset: 0x26 */
75675   __IO uint8_t GATE36;                             /**< Gate, offset: 0x27 */
75676   __IO uint8_t GATE43;                             /**< Gate, offset: 0x28 */
75677   __IO uint8_t GATE42;                             /**< Gate, offset: 0x29 */
75678   __IO uint8_t GATE41;                             /**< Gate, offset: 0x2A */
75679   __IO uint8_t GATE40;                             /**< Gate, offset: 0x2B */
75680   __IO uint8_t GATE47;                             /**< Gate, offset: 0x2C */
75681   __IO uint8_t GATE46;                             /**< Gate, offset: 0x2D */
75682   __IO uint8_t GATE45;                             /**< Gate, offset: 0x2E */
75683   __IO uint8_t GATE44;                             /**< Gate, offset: 0x2F */
75684   __IO uint8_t GATE51;                             /**< Gate, offset: 0x30 */
75685   __IO uint8_t GATE50;                             /**< Gate, offset: 0x31 */
75686   __IO uint8_t GATE49;                             /**< Gate, offset: 0x32 */
75687   __IO uint8_t GATE48;                             /**< Gate, offset: 0x33 */
75688   __IO uint8_t GATE55;                             /**< Gate, offset: 0x34 */
75689   __IO uint8_t GATE54;                             /**< Gate, offset: 0x35 */
75690   __IO uint8_t GATE53;                             /**< Gate, offset: 0x36 */
75691   __IO uint8_t GATE52;                             /**< Gate, offset: 0x37 */
75692   __IO uint8_t GATE59;                             /**< Gate, offset: 0x38 */
75693   __IO uint8_t GATE58;                             /**< Gate, offset: 0x39 */
75694   __IO uint8_t GATE57;                             /**< Gate, offset: 0x3A */
75695   __IO uint8_t GATE56;                             /**< Gate, offset: 0x3B */
75696   __IO uint8_t GATE63;                             /**< Gate, offset: 0x3C */
75697   __IO uint8_t GATE62;                             /**< Gate, offset: 0x3D */
75698   __IO uint8_t GATE61;                             /**< Gate, offset: 0x3E */
75699   __IO uint8_t GATE60;                             /**< Gate, offset: 0x3F */
75700        uint8_t RESERVED_0[2];
75701   union {                                          /* offset: 0x42 */
75702     __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
75703     __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
75704   };
75705 } SEMA42_Type;
75706 
75707 /* ----------------------------------------------------------------------------
75708    -- SEMA42 Register Masks
75709    ---------------------------------------------------------------------------- */
75710 
75711 /*!
75712  * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
75713  * @{
75714  */
75715 
75716 /*! @name GATE3 - Gate */
75717 /*! @{ */
75718 
75719 #define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
75720 #define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
75721 /*! GTFSM - Gate Finite State Machine
75722  *  0b0000..The gate is unlocked (free).
75723  *  0b0001..Domain 0 locked the gate.
75724  *  0b0010..Domain 1 locked the gate.
75725  *  0b0011..Domain 2 locked the gate.
75726  *  0b0100..Domain 3 locked the gate.
75727  *  0b0101..Domain 4 locked the gate.
75728  *  0b0110..Domain 5 locked the gate.
75729  *  0b0111..Domain 6 locked the gate.
75730  *  0b1000..Domain 7 locked the gate.
75731  *  0b1001..Domain 8 locked the gate.
75732  *  0b1010..Domain 9 locked the gate.
75733  *  0b1011..Domain 10 locked the gate.
75734  *  0b1100..Domain 11 locked the gate.
75735  *  0b1101..Domain 12 locked the gate.
75736  *  0b1110..Domain 13 locked the gate.
75737  *  0b1111..Domain 14 locked the gate.
75738  */
75739 #define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
75740 /*! @} */
75741 
75742 /*! @name GATE2 - Gate */
75743 /*! @{ */
75744 
75745 #define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
75746 #define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
75747 /*! GTFSM - Gate Finite State Machine
75748  *  0b0000..The gate is unlocked (free).
75749  *  0b0001..Domain 0 locked the gate.
75750  *  0b0010..Domain 1 locked the gate.
75751  *  0b0011..Domain 2 locked the gate.
75752  *  0b0100..Domain 3 locked the gate.
75753  *  0b0101..Domain 4 locked the gate.
75754  *  0b0110..Domain 5 locked the gate.
75755  *  0b0111..Domain 6 locked the gate.
75756  *  0b1000..Domain 7 locked the gate.
75757  *  0b1001..Domain 8 locked the gate.
75758  *  0b1010..Domain 9 locked the gate.
75759  *  0b1011..Domain 10 locked the gate.
75760  *  0b1100..Domain 11 locked the gate.
75761  *  0b1101..Domain 12 locked the gate.
75762  *  0b1110..Domain 13 locked the gate.
75763  *  0b1111..Domain 14 locked the gate.
75764  */
75765 #define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
75766 /*! @} */
75767 
75768 /*! @name GATE1 - Gate */
75769 /*! @{ */
75770 
75771 #define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
75772 #define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
75773 /*! GTFSM - Gate Finite State Machine
75774  *  0b0000..The gate is unlocked (free).
75775  *  0b0001..Domain 0 locked the gate.
75776  *  0b0010..Domain 1 locked the gate.
75777  *  0b0011..Domain 2 locked the gate.
75778  *  0b0100..Domain 3 locked the gate.
75779  *  0b0101..Domain 4 locked the gate.
75780  *  0b0110..Domain 5 locked the gate.
75781  *  0b0111..Domain 6 locked the gate.
75782  *  0b1000..Domain 7 locked the gate.
75783  *  0b1001..Domain 8 locked the gate.
75784  *  0b1010..Domain 9 locked the gate.
75785  *  0b1011..Domain 10 locked the gate.
75786  *  0b1100..Domain 11 locked the gate.
75787  *  0b1101..Domain 12 locked the gate.
75788  *  0b1110..Domain 13 locked the gate.
75789  *  0b1111..Domain 14 locked the gate.
75790  */
75791 #define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
75792 /*! @} */
75793 
75794 /*! @name GATE0 - Gate */
75795 /*! @{ */
75796 
75797 #define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
75798 #define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
75799 /*! GTFSM - Gate Finite State Machine
75800  *  0b0000..The gate is unlocked (free).
75801  *  0b0001..Domain 0 locked the gate.
75802  *  0b0010..Domain 1 locked the gate.
75803  *  0b0011..Domain 2 locked the gate.
75804  *  0b0100..Domain 3 locked the gate.
75805  *  0b0101..Domain 4 locked the gate.
75806  *  0b0110..Domain 5 locked the gate.
75807  *  0b0111..Domain 6 locked the gate.
75808  *  0b1000..Domain 7 locked the gate.
75809  *  0b1001..Domain 8 locked the gate.
75810  *  0b1010..Domain 9 locked the gate.
75811  *  0b1011..Domain 10 locked the gate.
75812  *  0b1100..Domain 11 locked the gate.
75813  *  0b1101..Domain 12 locked the gate.
75814  *  0b1110..Domain 13 locked the gate.
75815  *  0b1111..Domain 14 locked the gate.
75816  */
75817 #define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
75818 /*! @} */
75819 
75820 /*! @name GATE7 - Gate */
75821 /*! @{ */
75822 
75823 #define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
75824 #define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
75825 /*! GTFSM - Gate Finite State Machine
75826  *  0b0000..The gate is unlocked (free).
75827  *  0b0001..Domain 0 locked the gate.
75828  *  0b0010..Domain 1 locked the gate.
75829  *  0b0011..Domain 2 locked the gate.
75830  *  0b0100..Domain 3 locked the gate.
75831  *  0b0101..Domain 4 locked the gate.
75832  *  0b0110..Domain 5 locked the gate.
75833  *  0b0111..Domain 6 locked the gate.
75834  *  0b1000..Domain 7 locked the gate.
75835  *  0b1001..Domain 8 locked the gate.
75836  *  0b1010..Domain 9 locked the gate.
75837  *  0b1011..Domain 10 locked the gate.
75838  *  0b1100..Domain 11 locked the gate.
75839  *  0b1101..Domain 12 locked the gate.
75840  *  0b1110..Domain 13 locked the gate.
75841  *  0b1111..Domain 14 locked the gate.
75842  */
75843 #define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
75844 /*! @} */
75845 
75846 /*! @name GATE6 - Gate */
75847 /*! @{ */
75848 
75849 #define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
75850 #define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
75851 /*! GTFSM - Gate Finite State Machine
75852  *  0b0000..The gate is unlocked (free).
75853  *  0b0001..Domain 0 locked the gate.
75854  *  0b0010..Domain 1 locked the gate.
75855  *  0b0011..Domain 2 locked the gate.
75856  *  0b0100..Domain 3 locked the gate.
75857  *  0b0101..Domain 4 locked the gate.
75858  *  0b0110..Domain 5 locked the gate.
75859  *  0b0111..Domain 6 locked the gate.
75860  *  0b1000..Domain 7 locked the gate.
75861  *  0b1001..Domain 8 locked the gate.
75862  *  0b1010..Domain 9 locked the gate.
75863  *  0b1011..Domain 10 locked the gate.
75864  *  0b1100..Domain 11 locked the gate.
75865  *  0b1101..Domain 12 locked the gate.
75866  *  0b1110..Domain 13 locked the gate.
75867  *  0b1111..Domain 14 locked the gate.
75868  */
75869 #define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
75870 /*! @} */
75871 
75872 /*! @name GATE5 - Gate */
75873 /*! @{ */
75874 
75875 #define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
75876 #define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
75877 /*! GTFSM - Gate Finite State Machine
75878  *  0b0000..The gate is unlocked (free).
75879  *  0b0001..Domain 0 locked the gate.
75880  *  0b0010..Domain 1 locked the gate.
75881  *  0b0011..Domain 2 locked the gate.
75882  *  0b0100..Domain 3 locked the gate.
75883  *  0b0101..Domain 4 locked the gate.
75884  *  0b0110..Domain 5 locked the gate.
75885  *  0b0111..Domain 6 locked the gate.
75886  *  0b1000..Domain 7 locked the gate.
75887  *  0b1001..Domain 8 locked the gate.
75888  *  0b1010..Domain 9 locked the gate.
75889  *  0b1011..Domain 10 locked the gate.
75890  *  0b1100..Domain 11 locked the gate.
75891  *  0b1101..Domain 12 locked the gate.
75892  *  0b1110..Domain 13 locked the gate.
75893  *  0b1111..Domain 14 locked the gate.
75894  */
75895 #define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
75896 /*! @} */
75897 
75898 /*! @name GATE4 - Gate */
75899 /*! @{ */
75900 
75901 #define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
75902 #define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
75903 /*! GTFSM - Gate Finite State Machine
75904  *  0b0000..The gate is unlocked (free).
75905  *  0b0001..Domain 0 locked the gate.
75906  *  0b0010..Domain 1 locked the gate.
75907  *  0b0011..Domain 2 locked the gate.
75908  *  0b0100..Domain 3 locked the gate.
75909  *  0b0101..Domain 4 locked the gate.
75910  *  0b0110..Domain 5 locked the gate.
75911  *  0b0111..Domain 6 locked the gate.
75912  *  0b1000..Domain 7 locked the gate.
75913  *  0b1001..Domain 8 locked the gate.
75914  *  0b1010..Domain 9 locked the gate.
75915  *  0b1011..Domain 10 locked the gate.
75916  *  0b1100..Domain 11 locked the gate.
75917  *  0b1101..Domain 12 locked the gate.
75918  *  0b1110..Domain 13 locked the gate.
75919  *  0b1111..Domain 14 locked the gate.
75920  */
75921 #define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
75922 /*! @} */
75923 
75924 /*! @name GATE11 - Gate */
75925 /*! @{ */
75926 
75927 #define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
75928 #define SEMA42_GATE11_GTFSM_SHIFT                (0U)
75929 /*! GTFSM - Gate Finite State Machine
75930  *  0b0000..The gate is unlocked (free).
75931  *  0b0001..Domain 0 locked the gate.
75932  *  0b0010..Domain 1 locked the gate.
75933  *  0b0011..Domain 2 locked the gate.
75934  *  0b0100..Domain 3 locked the gate.
75935  *  0b0101..Domain 4 locked the gate.
75936  *  0b0110..Domain 5 locked the gate.
75937  *  0b0111..Domain 6 locked the gate.
75938  *  0b1000..Domain 7 locked the gate.
75939  *  0b1001..Domain 8 locked the gate.
75940  *  0b1010..Domain 9 locked the gate.
75941  *  0b1011..Domain 10 locked the gate.
75942  *  0b1100..Domain 11 locked the gate.
75943  *  0b1101..Domain 12 locked the gate.
75944  *  0b1110..Domain 13 locked the gate.
75945  *  0b1111..Domain 14 locked the gate.
75946  */
75947 #define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
75948 /*! @} */
75949 
75950 /*! @name GATE10 - Gate */
75951 /*! @{ */
75952 
75953 #define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
75954 #define SEMA42_GATE10_GTFSM_SHIFT                (0U)
75955 /*! GTFSM - Gate Finite State Machine
75956  *  0b0000..The gate is unlocked (free).
75957  *  0b0001..Domain 0 locked the gate.
75958  *  0b0010..Domain 1 locked the gate.
75959  *  0b0011..Domain 2 locked the gate.
75960  *  0b0100..Domain 3 locked the gate.
75961  *  0b0101..Domain 4 locked the gate.
75962  *  0b0110..Domain 5 locked the gate.
75963  *  0b0111..Domain 6 locked the gate.
75964  *  0b1000..Domain 7 locked the gate.
75965  *  0b1001..Domain 8 locked the gate.
75966  *  0b1010..Domain 9 locked the gate.
75967  *  0b1011..Domain 10 locked the gate.
75968  *  0b1100..Domain 11 locked the gate.
75969  *  0b1101..Domain 12 locked the gate.
75970  *  0b1110..Domain 13 locked the gate.
75971  *  0b1111..Domain 14 locked the gate.
75972  */
75973 #define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
75974 /*! @} */
75975 
75976 /*! @name GATE9 - Gate */
75977 /*! @{ */
75978 
75979 #define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
75980 #define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
75981 /*! GTFSM - Gate Finite State Machine
75982  *  0b0000..The gate is unlocked (free).
75983  *  0b0001..Domain 0 locked the gate.
75984  *  0b0010..Domain 1 locked the gate.
75985  *  0b0011..Domain 2 locked the gate.
75986  *  0b0100..Domain 3 locked the gate.
75987  *  0b0101..Domain 4 locked the gate.
75988  *  0b0110..Domain 5 locked the gate.
75989  *  0b0111..Domain 6 locked the gate.
75990  *  0b1000..Domain 7 locked the gate.
75991  *  0b1001..Domain 8 locked the gate.
75992  *  0b1010..Domain 9 locked the gate.
75993  *  0b1011..Domain 10 locked the gate.
75994  *  0b1100..Domain 11 locked the gate.
75995  *  0b1101..Domain 12 locked the gate.
75996  *  0b1110..Domain 13 locked the gate.
75997  *  0b1111..Domain 14 locked the gate.
75998  */
75999 #define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
76000 /*! @} */
76001 
76002 /*! @name GATE8 - Gate */
76003 /*! @{ */
76004 
76005 #define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
76006 #define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
76007 /*! GTFSM - Gate Finite State Machine
76008  *  0b0000..The gate is unlocked (free).
76009  *  0b0001..Domain 0 locked the gate.
76010  *  0b0010..Domain 1 locked the gate.
76011  *  0b0011..Domain 2 locked the gate.
76012  *  0b0100..Domain 3 locked the gate.
76013  *  0b0101..Domain 4 locked the gate.
76014  *  0b0110..Domain 5 locked the gate.
76015  *  0b0111..Domain 6 locked the gate.
76016  *  0b1000..Domain 7 locked the gate.
76017  *  0b1001..Domain 8 locked the gate.
76018  *  0b1010..Domain 9 locked the gate.
76019  *  0b1011..Domain 10 locked the gate.
76020  *  0b1100..Domain 11 locked the gate.
76021  *  0b1101..Domain 12 locked the gate.
76022  *  0b1110..Domain 13 locked the gate.
76023  *  0b1111..Domain 14 locked the gate.
76024  */
76025 #define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
76026 /*! @} */
76027 
76028 /*! @name GATE15 - Gate */
76029 /*! @{ */
76030 
76031 #define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
76032 #define SEMA42_GATE15_GTFSM_SHIFT                (0U)
76033 /*! GTFSM - Gate Finite State Machine
76034  *  0b0000..The gate is unlocked (free).
76035  *  0b0001..Domain 0 locked the gate.
76036  *  0b0010..Domain 1 locked the gate.
76037  *  0b0011..Domain 2 locked the gate.
76038  *  0b0100..Domain 3 locked the gate.
76039  *  0b0101..Domain 4 locked the gate.
76040  *  0b0110..Domain 5 locked the gate.
76041  *  0b0111..Domain 6 locked the gate.
76042  *  0b1000..Domain 7 locked the gate.
76043  *  0b1001..Domain 8 locked the gate.
76044  *  0b1010..Domain 9 locked the gate.
76045  *  0b1011..Domain 10 locked the gate.
76046  *  0b1100..Domain 11 locked the gate.
76047  *  0b1101..Domain 12 locked the gate.
76048  *  0b1110..Domain 13 locked the gate.
76049  *  0b1111..Domain 14 locked the gate.
76050  */
76051 #define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
76052 /*! @} */
76053 
76054 /*! @name GATE14 - Gate */
76055 /*! @{ */
76056 
76057 #define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
76058 #define SEMA42_GATE14_GTFSM_SHIFT                (0U)
76059 /*! GTFSM - Gate Finite State Machine
76060  *  0b0000..The gate is unlocked (free).
76061  *  0b0001..Domain 0 locked the gate.
76062  *  0b0010..Domain 1 locked the gate.
76063  *  0b0011..Domain 2 locked the gate.
76064  *  0b0100..Domain 3 locked the gate.
76065  *  0b0101..Domain 4 locked the gate.
76066  *  0b0110..Domain 5 locked the gate.
76067  *  0b0111..Domain 6 locked the gate.
76068  *  0b1000..Domain 7 locked the gate.
76069  *  0b1001..Domain 8 locked the gate.
76070  *  0b1010..Domain 9 locked the gate.
76071  *  0b1011..Domain 10 locked the gate.
76072  *  0b1100..Domain 11 locked the gate.
76073  *  0b1101..Domain 12 locked the gate.
76074  *  0b1110..Domain 13 locked the gate.
76075  *  0b1111..Domain 14 locked the gate.
76076  */
76077 #define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
76078 /*! @} */
76079 
76080 /*! @name GATE13 - Gate */
76081 /*! @{ */
76082 
76083 #define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
76084 #define SEMA42_GATE13_GTFSM_SHIFT                (0U)
76085 /*! GTFSM - Gate Finite State Machine
76086  *  0b0000..The gate is unlocked (free).
76087  *  0b0001..Domain 0 locked the gate.
76088  *  0b0010..Domain 1 locked the gate.
76089  *  0b0011..Domain 2 locked the gate.
76090  *  0b0100..Domain 3 locked the gate.
76091  *  0b0101..Domain 4 locked the gate.
76092  *  0b0110..Domain 5 locked the gate.
76093  *  0b0111..Domain 6 locked the gate.
76094  *  0b1000..Domain 7 locked the gate.
76095  *  0b1001..Domain 8 locked the gate.
76096  *  0b1010..Domain 9 locked the gate.
76097  *  0b1011..Domain 10 locked the gate.
76098  *  0b1100..Domain 11 locked the gate.
76099  *  0b1101..Domain 12 locked the gate.
76100  *  0b1110..Domain 13 locked the gate.
76101  *  0b1111..Domain 14 locked the gate.
76102  */
76103 #define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
76104 /*! @} */
76105 
76106 /*! @name GATE12 - Gate */
76107 /*! @{ */
76108 
76109 #define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
76110 #define SEMA42_GATE12_GTFSM_SHIFT                (0U)
76111 /*! GTFSM - Gate Finite State Machine
76112  *  0b0000..The gate is unlocked (free).
76113  *  0b0001..Domain 0 locked the gate.
76114  *  0b0010..Domain 1 locked the gate.
76115  *  0b0011..Domain 2 locked the gate.
76116  *  0b0100..Domain 3 locked the gate.
76117  *  0b0101..Domain 4 locked the gate.
76118  *  0b0110..Domain 5 locked the gate.
76119  *  0b0111..Domain 6 locked the gate.
76120  *  0b1000..Domain 7 locked the gate.
76121  *  0b1001..Domain 8 locked the gate.
76122  *  0b1010..Domain 9 locked the gate.
76123  *  0b1011..Domain 10 locked the gate.
76124  *  0b1100..Domain 11 locked the gate.
76125  *  0b1101..Domain 12 locked the gate.
76126  *  0b1110..Domain 13 locked the gate.
76127  *  0b1111..Domain 14 locked the gate.
76128  */
76129 #define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
76130 /*! @} */
76131 
76132 /*! @name GATE19 - Gate */
76133 /*! @{ */
76134 
76135 #define SEMA42_GATE19_GTFSM_MASK                 (0xFU)
76136 #define SEMA42_GATE19_GTFSM_SHIFT                (0U)
76137 /*! GTFSM - Gate Finite State Machine
76138  *  0b0000..The gate is unlocked (free).
76139  *  0b0001..Domain 0 locked the gate.
76140  *  0b0010..Domain 1 locked the gate.
76141  *  0b0011..Domain 2 locked the gate.
76142  *  0b0100..Domain 3 locked the gate.
76143  *  0b0101..Domain 4 locked the gate.
76144  *  0b0110..Domain 5 locked the gate.
76145  *  0b0111..Domain 6 locked the gate.
76146  *  0b1000..Domain 7 locked the gate.
76147  *  0b1001..Domain 8 locked the gate.
76148  *  0b1010..Domain 9 locked the gate.
76149  *  0b1011..Domain 10 locked the gate.
76150  *  0b1100..Domain 11 locked the gate.
76151  *  0b1101..Domain 12 locked the gate.
76152  *  0b1110..Domain 13 locked the gate.
76153  *  0b1111..Domain 14 locked the gate.
76154  */
76155 #define SEMA42_GATE19_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE19_GTFSM_SHIFT)) & SEMA42_GATE19_GTFSM_MASK)
76156 /*! @} */
76157 
76158 /*! @name GATE18 - Gate */
76159 /*! @{ */
76160 
76161 #define SEMA42_GATE18_GTFSM_MASK                 (0xFU)
76162 #define SEMA42_GATE18_GTFSM_SHIFT                (0U)
76163 /*! GTFSM - Gate Finite State Machine
76164  *  0b0000..The gate is unlocked (free).
76165  *  0b0001..Domain 0 locked the gate.
76166  *  0b0010..Domain 1 locked the gate.
76167  *  0b0011..Domain 2 locked the gate.
76168  *  0b0100..Domain 3 locked the gate.
76169  *  0b0101..Domain 4 locked the gate.
76170  *  0b0110..Domain 5 locked the gate.
76171  *  0b0111..Domain 6 locked the gate.
76172  *  0b1000..Domain 7 locked the gate.
76173  *  0b1001..Domain 8 locked the gate.
76174  *  0b1010..Domain 9 locked the gate.
76175  *  0b1011..Domain 10 locked the gate.
76176  *  0b1100..Domain 11 locked the gate.
76177  *  0b1101..Domain 12 locked the gate.
76178  *  0b1110..Domain 13 locked the gate.
76179  *  0b1111..Domain 14 locked the gate.
76180  */
76181 #define SEMA42_GATE18_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE18_GTFSM_SHIFT)) & SEMA42_GATE18_GTFSM_MASK)
76182 /*! @} */
76183 
76184 /*! @name GATE17 - Gate */
76185 /*! @{ */
76186 
76187 #define SEMA42_GATE17_GTFSM_MASK                 (0xFU)
76188 #define SEMA42_GATE17_GTFSM_SHIFT                (0U)
76189 /*! GTFSM - Gate Finite State Machine
76190  *  0b0000..The gate is unlocked (free).
76191  *  0b0001..Domain 0 locked the gate.
76192  *  0b0010..Domain 1 locked the gate.
76193  *  0b0011..Domain 2 locked the gate.
76194  *  0b0100..Domain 3 locked the gate.
76195  *  0b0101..Domain 4 locked the gate.
76196  *  0b0110..Domain 5 locked the gate.
76197  *  0b0111..Domain 6 locked the gate.
76198  *  0b1000..Domain 7 locked the gate.
76199  *  0b1001..Domain 8 locked the gate.
76200  *  0b1010..Domain 9 locked the gate.
76201  *  0b1011..Domain 10 locked the gate.
76202  *  0b1100..Domain 11 locked the gate.
76203  *  0b1101..Domain 12 locked the gate.
76204  *  0b1110..Domain 13 locked the gate.
76205  *  0b1111..Domain 14 locked the gate.
76206  */
76207 #define SEMA42_GATE17_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE17_GTFSM_SHIFT)) & SEMA42_GATE17_GTFSM_MASK)
76208 /*! @} */
76209 
76210 /*! @name GATE16 - Gate */
76211 /*! @{ */
76212 
76213 #define SEMA42_GATE16_GTFSM_MASK                 (0xFU)
76214 #define SEMA42_GATE16_GTFSM_SHIFT                (0U)
76215 /*! GTFSM - Gate Finite State Machine
76216  *  0b0000..The gate is unlocked (free).
76217  *  0b0001..Domain 0 locked the gate.
76218  *  0b0010..Domain 1 locked the gate.
76219  *  0b0011..Domain 2 locked the gate.
76220  *  0b0100..Domain 3 locked the gate.
76221  *  0b0101..Domain 4 locked the gate.
76222  *  0b0110..Domain 5 locked the gate.
76223  *  0b0111..Domain 6 locked the gate.
76224  *  0b1000..Domain 7 locked the gate.
76225  *  0b1001..Domain 8 locked the gate.
76226  *  0b1010..Domain 9 locked the gate.
76227  *  0b1011..Domain 10 locked the gate.
76228  *  0b1100..Domain 11 locked the gate.
76229  *  0b1101..Domain 12 locked the gate.
76230  *  0b1110..Domain 13 locked the gate.
76231  *  0b1111..Domain 14 locked the gate.
76232  */
76233 #define SEMA42_GATE16_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE16_GTFSM_SHIFT)) & SEMA42_GATE16_GTFSM_MASK)
76234 /*! @} */
76235 
76236 /*! @name GATE23 - Gate */
76237 /*! @{ */
76238 
76239 #define SEMA42_GATE23_GTFSM_MASK                 (0xFU)
76240 #define SEMA42_GATE23_GTFSM_SHIFT                (0U)
76241 /*! GTFSM - Gate Finite State Machine
76242  *  0b0000..The gate is unlocked (free).
76243  *  0b0001..Domain 0 locked the gate.
76244  *  0b0010..Domain 1 locked the gate.
76245  *  0b0011..Domain 2 locked the gate.
76246  *  0b0100..Domain 3 locked the gate.
76247  *  0b0101..Domain 4 locked the gate.
76248  *  0b0110..Domain 5 locked the gate.
76249  *  0b0111..Domain 6 locked the gate.
76250  *  0b1000..Domain 7 locked the gate.
76251  *  0b1001..Domain 8 locked the gate.
76252  *  0b1010..Domain 9 locked the gate.
76253  *  0b1011..Domain 10 locked the gate.
76254  *  0b1100..Domain 11 locked the gate.
76255  *  0b1101..Domain 12 locked the gate.
76256  *  0b1110..Domain 13 locked the gate.
76257  *  0b1111..Domain 14 locked the gate.
76258  */
76259 #define SEMA42_GATE23_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE23_GTFSM_SHIFT)) & SEMA42_GATE23_GTFSM_MASK)
76260 /*! @} */
76261 
76262 /*! @name GATE22 - Gate */
76263 /*! @{ */
76264 
76265 #define SEMA42_GATE22_GTFSM_MASK                 (0xFU)
76266 #define SEMA42_GATE22_GTFSM_SHIFT                (0U)
76267 /*! GTFSM - Gate Finite State Machine
76268  *  0b0000..The gate is unlocked (free).
76269  *  0b0001..Domain 0 locked the gate.
76270  *  0b0010..Domain 1 locked the gate.
76271  *  0b0011..Domain 2 locked the gate.
76272  *  0b0100..Domain 3 locked the gate.
76273  *  0b0101..Domain 4 locked the gate.
76274  *  0b0110..Domain 5 locked the gate.
76275  *  0b0111..Domain 6 locked the gate.
76276  *  0b1000..Domain 7 locked the gate.
76277  *  0b1001..Domain 8 locked the gate.
76278  *  0b1010..Domain 9 locked the gate.
76279  *  0b1011..Domain 10 locked the gate.
76280  *  0b1100..Domain 11 locked the gate.
76281  *  0b1101..Domain 12 locked the gate.
76282  *  0b1110..Domain 13 locked the gate.
76283  *  0b1111..Domain 14 locked the gate.
76284  */
76285 #define SEMA42_GATE22_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE22_GTFSM_SHIFT)) & SEMA42_GATE22_GTFSM_MASK)
76286 /*! @} */
76287 
76288 /*! @name GATE21 - Gate */
76289 /*! @{ */
76290 
76291 #define SEMA42_GATE21_GTFSM_MASK                 (0xFU)
76292 #define SEMA42_GATE21_GTFSM_SHIFT                (0U)
76293 /*! GTFSM - Gate Finite State Machine
76294  *  0b0000..The gate is unlocked (free).
76295  *  0b0001..Domain 0 locked the gate.
76296  *  0b0010..Domain 1 locked the gate.
76297  *  0b0011..Domain 2 locked the gate.
76298  *  0b0100..Domain 3 locked the gate.
76299  *  0b0101..Domain 4 locked the gate.
76300  *  0b0110..Domain 5 locked the gate.
76301  *  0b0111..Domain 6 locked the gate.
76302  *  0b1000..Domain 7 locked the gate.
76303  *  0b1001..Domain 8 locked the gate.
76304  *  0b1010..Domain 9 locked the gate.
76305  *  0b1011..Domain 10 locked the gate.
76306  *  0b1100..Domain 11 locked the gate.
76307  *  0b1101..Domain 12 locked the gate.
76308  *  0b1110..Domain 13 locked the gate.
76309  *  0b1111..Domain 14 locked the gate.
76310  */
76311 #define SEMA42_GATE21_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE21_GTFSM_SHIFT)) & SEMA42_GATE21_GTFSM_MASK)
76312 /*! @} */
76313 
76314 /*! @name GATE20 - Gate */
76315 /*! @{ */
76316 
76317 #define SEMA42_GATE20_GTFSM_MASK                 (0xFU)
76318 #define SEMA42_GATE20_GTFSM_SHIFT                (0U)
76319 /*! GTFSM - Gate Finite State Machine
76320  *  0b0000..The gate is unlocked (free).
76321  *  0b0001..Domain 0 locked the gate.
76322  *  0b0010..Domain 1 locked the gate.
76323  *  0b0011..Domain 2 locked the gate.
76324  *  0b0100..Domain 3 locked the gate.
76325  *  0b0101..Domain 4 locked the gate.
76326  *  0b0110..Domain 5 locked the gate.
76327  *  0b0111..Domain 6 locked the gate.
76328  *  0b1000..Domain 7 locked the gate.
76329  *  0b1001..Domain 8 locked the gate.
76330  *  0b1010..Domain 9 locked the gate.
76331  *  0b1011..Domain 10 locked the gate.
76332  *  0b1100..Domain 11 locked the gate.
76333  *  0b1101..Domain 12 locked the gate.
76334  *  0b1110..Domain 13 locked the gate.
76335  *  0b1111..Domain 14 locked the gate.
76336  */
76337 #define SEMA42_GATE20_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE20_GTFSM_SHIFT)) & SEMA42_GATE20_GTFSM_MASK)
76338 /*! @} */
76339 
76340 /*! @name GATE27 - Gate */
76341 /*! @{ */
76342 
76343 #define SEMA42_GATE27_GTFSM_MASK                 (0xFU)
76344 #define SEMA42_GATE27_GTFSM_SHIFT                (0U)
76345 /*! GTFSM - Gate Finite State Machine
76346  *  0b0000..The gate is unlocked (free).
76347  *  0b0001..Domain 0 locked the gate.
76348  *  0b0010..Domain 1 locked the gate.
76349  *  0b0011..Domain 2 locked the gate.
76350  *  0b0100..Domain 3 locked the gate.
76351  *  0b0101..Domain 4 locked the gate.
76352  *  0b0110..Domain 5 locked the gate.
76353  *  0b0111..Domain 6 locked the gate.
76354  *  0b1000..Domain 7 locked the gate.
76355  *  0b1001..Domain 8 locked the gate.
76356  *  0b1010..Domain 9 locked the gate.
76357  *  0b1011..Domain 10 locked the gate.
76358  *  0b1100..Domain 11 locked the gate.
76359  *  0b1101..Domain 12 locked the gate.
76360  *  0b1110..Domain 13 locked the gate.
76361  *  0b1111..Domain 14 locked the gate.
76362  */
76363 #define SEMA42_GATE27_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE27_GTFSM_SHIFT)) & SEMA42_GATE27_GTFSM_MASK)
76364 /*! @} */
76365 
76366 /*! @name GATE26 - Gate */
76367 /*! @{ */
76368 
76369 #define SEMA42_GATE26_GTFSM_MASK                 (0xFU)
76370 #define SEMA42_GATE26_GTFSM_SHIFT                (0U)
76371 /*! GTFSM - Gate Finite State Machine
76372  *  0b0000..The gate is unlocked (free).
76373  *  0b0001..Domain 0 locked the gate.
76374  *  0b0010..Domain 1 locked the gate.
76375  *  0b0011..Domain 2 locked the gate.
76376  *  0b0100..Domain 3 locked the gate.
76377  *  0b0101..Domain 4 locked the gate.
76378  *  0b0110..Domain 5 locked the gate.
76379  *  0b0111..Domain 6 locked the gate.
76380  *  0b1000..Domain 7 locked the gate.
76381  *  0b1001..Domain 8 locked the gate.
76382  *  0b1010..Domain 9 locked the gate.
76383  *  0b1011..Domain 10 locked the gate.
76384  *  0b1100..Domain 11 locked the gate.
76385  *  0b1101..Domain 12 locked the gate.
76386  *  0b1110..Domain 13 locked the gate.
76387  *  0b1111..Domain 14 locked the gate.
76388  */
76389 #define SEMA42_GATE26_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE26_GTFSM_SHIFT)) & SEMA42_GATE26_GTFSM_MASK)
76390 /*! @} */
76391 
76392 /*! @name GATE25 - Gate */
76393 /*! @{ */
76394 
76395 #define SEMA42_GATE25_GTFSM_MASK                 (0xFU)
76396 #define SEMA42_GATE25_GTFSM_SHIFT                (0U)
76397 /*! GTFSM - Gate Finite State Machine
76398  *  0b0000..The gate is unlocked (free).
76399  *  0b0001..Domain 0 locked the gate.
76400  *  0b0010..Domain 1 locked the gate.
76401  *  0b0011..Domain 2 locked the gate.
76402  *  0b0100..Domain 3 locked the gate.
76403  *  0b0101..Domain 4 locked the gate.
76404  *  0b0110..Domain 5 locked the gate.
76405  *  0b0111..Domain 6 locked the gate.
76406  *  0b1000..Domain 7 locked the gate.
76407  *  0b1001..Domain 8 locked the gate.
76408  *  0b1010..Domain 9 locked the gate.
76409  *  0b1011..Domain 10 locked the gate.
76410  *  0b1100..Domain 11 locked the gate.
76411  *  0b1101..Domain 12 locked the gate.
76412  *  0b1110..Domain 13 locked the gate.
76413  *  0b1111..Domain 14 locked the gate.
76414  */
76415 #define SEMA42_GATE25_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE25_GTFSM_SHIFT)) & SEMA42_GATE25_GTFSM_MASK)
76416 /*! @} */
76417 
76418 /*! @name GATE24 - Gate */
76419 /*! @{ */
76420 
76421 #define SEMA42_GATE24_GTFSM_MASK                 (0xFU)
76422 #define SEMA42_GATE24_GTFSM_SHIFT                (0U)
76423 /*! GTFSM - Gate Finite State Machine
76424  *  0b0000..The gate is unlocked (free).
76425  *  0b0001..Domain 0 locked the gate.
76426  *  0b0010..Domain 1 locked the gate.
76427  *  0b0011..Domain 2 locked the gate.
76428  *  0b0100..Domain 3 locked the gate.
76429  *  0b0101..Domain 4 locked the gate.
76430  *  0b0110..Domain 5 locked the gate.
76431  *  0b0111..Domain 6 locked the gate.
76432  *  0b1000..Domain 7 locked the gate.
76433  *  0b1001..Domain 8 locked the gate.
76434  *  0b1010..Domain 9 locked the gate.
76435  *  0b1011..Domain 10 locked the gate.
76436  *  0b1100..Domain 11 locked the gate.
76437  *  0b1101..Domain 12 locked the gate.
76438  *  0b1110..Domain 13 locked the gate.
76439  *  0b1111..Domain 14 locked the gate.
76440  */
76441 #define SEMA42_GATE24_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE24_GTFSM_SHIFT)) & SEMA42_GATE24_GTFSM_MASK)
76442 /*! @} */
76443 
76444 /*! @name GATE31 - Gate */
76445 /*! @{ */
76446 
76447 #define SEMA42_GATE31_GTFSM_MASK                 (0xFU)
76448 #define SEMA42_GATE31_GTFSM_SHIFT                (0U)
76449 /*! GTFSM - Gate Finite State Machine
76450  *  0b0000..The gate is unlocked (free).
76451  *  0b0001..Domain 0 locked the gate.
76452  *  0b0010..Domain 1 locked the gate.
76453  *  0b0011..Domain 2 locked the gate.
76454  *  0b0100..Domain 3 locked the gate.
76455  *  0b0101..Domain 4 locked the gate.
76456  *  0b0110..Domain 5 locked the gate.
76457  *  0b0111..Domain 6 locked the gate.
76458  *  0b1000..Domain 7 locked the gate.
76459  *  0b1001..Domain 8 locked the gate.
76460  *  0b1010..Domain 9 locked the gate.
76461  *  0b1011..Domain 10 locked the gate.
76462  *  0b1100..Domain 11 locked the gate.
76463  *  0b1101..Domain 12 locked the gate.
76464  *  0b1110..Domain 13 locked the gate.
76465  *  0b1111..Domain 14 locked the gate.
76466  */
76467 #define SEMA42_GATE31_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE31_GTFSM_SHIFT)) & SEMA42_GATE31_GTFSM_MASK)
76468 /*! @} */
76469 
76470 /*! @name GATE30 - Gate */
76471 /*! @{ */
76472 
76473 #define SEMA42_GATE30_GTFSM_MASK                 (0xFU)
76474 #define SEMA42_GATE30_GTFSM_SHIFT                (0U)
76475 /*! GTFSM - Gate Finite State Machine
76476  *  0b0000..The gate is unlocked (free).
76477  *  0b0001..Domain 0 locked the gate.
76478  *  0b0010..Domain 1 locked the gate.
76479  *  0b0011..Domain 2 locked the gate.
76480  *  0b0100..Domain 3 locked the gate.
76481  *  0b0101..Domain 4 locked the gate.
76482  *  0b0110..Domain 5 locked the gate.
76483  *  0b0111..Domain 6 locked the gate.
76484  *  0b1000..Domain 7 locked the gate.
76485  *  0b1001..Domain 8 locked the gate.
76486  *  0b1010..Domain 9 locked the gate.
76487  *  0b1011..Domain 10 locked the gate.
76488  *  0b1100..Domain 11 locked the gate.
76489  *  0b1101..Domain 12 locked the gate.
76490  *  0b1110..Domain 13 locked the gate.
76491  *  0b1111..Domain 14 locked the gate.
76492  */
76493 #define SEMA42_GATE30_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE30_GTFSM_SHIFT)) & SEMA42_GATE30_GTFSM_MASK)
76494 /*! @} */
76495 
76496 /*! @name GATE29 - Gate */
76497 /*! @{ */
76498 
76499 #define SEMA42_GATE29_GTFSM_MASK                 (0xFU)
76500 #define SEMA42_GATE29_GTFSM_SHIFT                (0U)
76501 /*! GTFSM - Gate Finite State Machine
76502  *  0b0000..The gate is unlocked (free).
76503  *  0b0001..Domain 0 locked the gate.
76504  *  0b0010..Domain 1 locked the gate.
76505  *  0b0011..Domain 2 locked the gate.
76506  *  0b0100..Domain 3 locked the gate.
76507  *  0b0101..Domain 4 locked the gate.
76508  *  0b0110..Domain 5 locked the gate.
76509  *  0b0111..Domain 6 locked the gate.
76510  *  0b1000..Domain 7 locked the gate.
76511  *  0b1001..Domain 8 locked the gate.
76512  *  0b1010..Domain 9 locked the gate.
76513  *  0b1011..Domain 10 locked the gate.
76514  *  0b1100..Domain 11 locked the gate.
76515  *  0b1101..Domain 12 locked the gate.
76516  *  0b1110..Domain 13 locked the gate.
76517  *  0b1111..Domain 14 locked the gate.
76518  */
76519 #define SEMA42_GATE29_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE29_GTFSM_SHIFT)) & SEMA42_GATE29_GTFSM_MASK)
76520 /*! @} */
76521 
76522 /*! @name GATE28 - Gate */
76523 /*! @{ */
76524 
76525 #define SEMA42_GATE28_GTFSM_MASK                 (0xFU)
76526 #define SEMA42_GATE28_GTFSM_SHIFT                (0U)
76527 /*! GTFSM - Gate Finite State Machine
76528  *  0b0000..The gate is unlocked (free).
76529  *  0b0001..Domain 0 locked the gate.
76530  *  0b0010..Domain 1 locked the gate.
76531  *  0b0011..Domain 2 locked the gate.
76532  *  0b0100..Domain 3 locked the gate.
76533  *  0b0101..Domain 4 locked the gate.
76534  *  0b0110..Domain 5 locked the gate.
76535  *  0b0111..Domain 6 locked the gate.
76536  *  0b1000..Domain 7 locked the gate.
76537  *  0b1001..Domain 8 locked the gate.
76538  *  0b1010..Domain 9 locked the gate.
76539  *  0b1011..Domain 10 locked the gate.
76540  *  0b1100..Domain 11 locked the gate.
76541  *  0b1101..Domain 12 locked the gate.
76542  *  0b1110..Domain 13 locked the gate.
76543  *  0b1111..Domain 14 locked the gate.
76544  */
76545 #define SEMA42_GATE28_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE28_GTFSM_SHIFT)) & SEMA42_GATE28_GTFSM_MASK)
76546 /*! @} */
76547 
76548 /*! @name GATE35 - Gate */
76549 /*! @{ */
76550 
76551 #define SEMA42_GATE35_GTFSM_MASK                 (0xFU)
76552 #define SEMA42_GATE35_GTFSM_SHIFT                (0U)
76553 /*! GTFSM - Gate Finite State Machine
76554  *  0b0000..The gate is unlocked (free).
76555  *  0b0001..Domain 0 locked the gate.
76556  *  0b0010..Domain 1 locked the gate.
76557  *  0b0011..Domain 2 locked the gate.
76558  *  0b0100..Domain 3 locked the gate.
76559  *  0b0101..Domain 4 locked the gate.
76560  *  0b0110..Domain 5 locked the gate.
76561  *  0b0111..Domain 6 locked the gate.
76562  *  0b1000..Domain 7 locked the gate.
76563  *  0b1001..Domain 8 locked the gate.
76564  *  0b1010..Domain 9 locked the gate.
76565  *  0b1011..Domain 10 locked the gate.
76566  *  0b1100..Domain 11 locked the gate.
76567  *  0b1101..Domain 12 locked the gate.
76568  *  0b1110..Domain 13 locked the gate.
76569  *  0b1111..Domain 14 locked the gate.
76570  */
76571 #define SEMA42_GATE35_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE35_GTFSM_SHIFT)) & SEMA42_GATE35_GTFSM_MASK)
76572 /*! @} */
76573 
76574 /*! @name GATE34 - Gate */
76575 /*! @{ */
76576 
76577 #define SEMA42_GATE34_GTFSM_MASK                 (0xFU)
76578 #define SEMA42_GATE34_GTFSM_SHIFT                (0U)
76579 /*! GTFSM - Gate Finite State Machine
76580  *  0b0000..The gate is unlocked (free).
76581  *  0b0001..Domain 0 locked the gate.
76582  *  0b0010..Domain 1 locked the gate.
76583  *  0b0011..Domain 2 locked the gate.
76584  *  0b0100..Domain 3 locked the gate.
76585  *  0b0101..Domain 4 locked the gate.
76586  *  0b0110..Domain 5 locked the gate.
76587  *  0b0111..Domain 6 locked the gate.
76588  *  0b1000..Domain 7 locked the gate.
76589  *  0b1001..Domain 8 locked the gate.
76590  *  0b1010..Domain 9 locked the gate.
76591  *  0b1011..Domain 10 locked the gate.
76592  *  0b1100..Domain 11 locked the gate.
76593  *  0b1101..Domain 12 locked the gate.
76594  *  0b1110..Domain 13 locked the gate.
76595  *  0b1111..Domain 14 locked the gate.
76596  */
76597 #define SEMA42_GATE34_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE34_GTFSM_SHIFT)) & SEMA42_GATE34_GTFSM_MASK)
76598 /*! @} */
76599 
76600 /*! @name GATE33 - Gate */
76601 /*! @{ */
76602 
76603 #define SEMA42_GATE33_GTFSM_MASK                 (0xFU)
76604 #define SEMA42_GATE33_GTFSM_SHIFT                (0U)
76605 /*! GTFSM - Gate Finite State Machine
76606  *  0b0000..The gate is unlocked (free).
76607  *  0b0001..Domain 0 locked the gate.
76608  *  0b0010..Domain 1 locked the gate.
76609  *  0b0011..Domain 2 locked the gate.
76610  *  0b0100..Domain 3 locked the gate.
76611  *  0b0101..Domain 4 locked the gate.
76612  *  0b0110..Domain 5 locked the gate.
76613  *  0b0111..Domain 6 locked the gate.
76614  *  0b1000..Domain 7 locked the gate.
76615  *  0b1001..Domain 8 locked the gate.
76616  *  0b1010..Domain 9 locked the gate.
76617  *  0b1011..Domain 10 locked the gate.
76618  *  0b1100..Domain 11 locked the gate.
76619  *  0b1101..Domain 12 locked the gate.
76620  *  0b1110..Domain 13 locked the gate.
76621  *  0b1111..Domain 14 locked the gate.
76622  */
76623 #define SEMA42_GATE33_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE33_GTFSM_SHIFT)) & SEMA42_GATE33_GTFSM_MASK)
76624 /*! @} */
76625 
76626 /*! @name GATE32 - Gate */
76627 /*! @{ */
76628 
76629 #define SEMA42_GATE32_GTFSM_MASK                 (0xFU)
76630 #define SEMA42_GATE32_GTFSM_SHIFT                (0U)
76631 /*! GTFSM - Gate Finite State Machine
76632  *  0b0000..The gate is unlocked (free).
76633  *  0b0001..Domain 0 locked the gate.
76634  *  0b0010..Domain 1 locked the gate.
76635  *  0b0011..Domain 2 locked the gate.
76636  *  0b0100..Domain 3 locked the gate.
76637  *  0b0101..Domain 4 locked the gate.
76638  *  0b0110..Domain 5 locked the gate.
76639  *  0b0111..Domain 6 locked the gate.
76640  *  0b1000..Domain 7 locked the gate.
76641  *  0b1001..Domain 8 locked the gate.
76642  *  0b1010..Domain 9 locked the gate.
76643  *  0b1011..Domain 10 locked the gate.
76644  *  0b1100..Domain 11 locked the gate.
76645  *  0b1101..Domain 12 locked the gate.
76646  *  0b1110..Domain 13 locked the gate.
76647  *  0b1111..Domain 14 locked the gate.
76648  */
76649 #define SEMA42_GATE32_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE32_GTFSM_SHIFT)) & SEMA42_GATE32_GTFSM_MASK)
76650 /*! @} */
76651 
76652 /*! @name GATE39 - Gate */
76653 /*! @{ */
76654 
76655 #define SEMA42_GATE39_GTFSM_MASK                 (0xFU)
76656 #define SEMA42_GATE39_GTFSM_SHIFT                (0U)
76657 /*! GTFSM - Gate Finite State Machine
76658  *  0b0000..The gate is unlocked (free).
76659  *  0b0001..Domain 0 locked the gate.
76660  *  0b0010..Domain 1 locked the gate.
76661  *  0b0011..Domain 2 locked the gate.
76662  *  0b0100..Domain 3 locked the gate.
76663  *  0b0101..Domain 4 locked the gate.
76664  *  0b0110..Domain 5 locked the gate.
76665  *  0b0111..Domain 6 locked the gate.
76666  *  0b1000..Domain 7 locked the gate.
76667  *  0b1001..Domain 8 locked the gate.
76668  *  0b1010..Domain 9 locked the gate.
76669  *  0b1011..Domain 10 locked the gate.
76670  *  0b1100..Domain 11 locked the gate.
76671  *  0b1101..Domain 12 locked the gate.
76672  *  0b1110..Domain 13 locked the gate.
76673  *  0b1111..Domain 14 locked the gate.
76674  */
76675 #define SEMA42_GATE39_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE39_GTFSM_SHIFT)) & SEMA42_GATE39_GTFSM_MASK)
76676 /*! @} */
76677 
76678 /*! @name GATE38 - Gate */
76679 /*! @{ */
76680 
76681 #define SEMA42_GATE38_GTFSM_MASK                 (0xFU)
76682 #define SEMA42_GATE38_GTFSM_SHIFT                (0U)
76683 /*! GTFSM - Gate Finite State Machine
76684  *  0b0000..The gate is unlocked (free).
76685  *  0b0001..Domain 0 locked the gate.
76686  *  0b0010..Domain 1 locked the gate.
76687  *  0b0011..Domain 2 locked the gate.
76688  *  0b0100..Domain 3 locked the gate.
76689  *  0b0101..Domain 4 locked the gate.
76690  *  0b0110..Domain 5 locked the gate.
76691  *  0b0111..Domain 6 locked the gate.
76692  *  0b1000..Domain 7 locked the gate.
76693  *  0b1001..Domain 8 locked the gate.
76694  *  0b1010..Domain 9 locked the gate.
76695  *  0b1011..Domain 10 locked the gate.
76696  *  0b1100..Domain 11 locked the gate.
76697  *  0b1101..Domain 12 locked the gate.
76698  *  0b1110..Domain 13 locked the gate.
76699  *  0b1111..Domain 14 locked the gate.
76700  */
76701 #define SEMA42_GATE38_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE38_GTFSM_SHIFT)) & SEMA42_GATE38_GTFSM_MASK)
76702 /*! @} */
76703 
76704 /*! @name GATE37 - Gate */
76705 /*! @{ */
76706 
76707 #define SEMA42_GATE37_GTFSM_MASK                 (0xFU)
76708 #define SEMA42_GATE37_GTFSM_SHIFT                (0U)
76709 /*! GTFSM - Gate Finite State Machine
76710  *  0b0000..The gate is unlocked (free).
76711  *  0b0001..Domain 0 locked the gate.
76712  *  0b0010..Domain 1 locked the gate.
76713  *  0b0011..Domain 2 locked the gate.
76714  *  0b0100..Domain 3 locked the gate.
76715  *  0b0101..Domain 4 locked the gate.
76716  *  0b0110..Domain 5 locked the gate.
76717  *  0b0111..Domain 6 locked the gate.
76718  *  0b1000..Domain 7 locked the gate.
76719  *  0b1001..Domain 8 locked the gate.
76720  *  0b1010..Domain 9 locked the gate.
76721  *  0b1011..Domain 10 locked the gate.
76722  *  0b1100..Domain 11 locked the gate.
76723  *  0b1101..Domain 12 locked the gate.
76724  *  0b1110..Domain 13 locked the gate.
76725  *  0b1111..Domain 14 locked the gate.
76726  */
76727 #define SEMA42_GATE37_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE37_GTFSM_SHIFT)) & SEMA42_GATE37_GTFSM_MASK)
76728 /*! @} */
76729 
76730 /*! @name GATE36 - Gate */
76731 /*! @{ */
76732 
76733 #define SEMA42_GATE36_GTFSM_MASK                 (0xFU)
76734 #define SEMA42_GATE36_GTFSM_SHIFT                (0U)
76735 /*! GTFSM - Gate Finite State Machine
76736  *  0b0000..The gate is unlocked (free).
76737  *  0b0001..Domain 0 locked the gate.
76738  *  0b0010..Domain 1 locked the gate.
76739  *  0b0011..Domain 2 locked the gate.
76740  *  0b0100..Domain 3 locked the gate.
76741  *  0b0101..Domain 4 locked the gate.
76742  *  0b0110..Domain 5 locked the gate.
76743  *  0b0111..Domain 6 locked the gate.
76744  *  0b1000..Domain 7 locked the gate.
76745  *  0b1001..Domain 8 locked the gate.
76746  *  0b1010..Domain 9 locked the gate.
76747  *  0b1011..Domain 10 locked the gate.
76748  *  0b1100..Domain 11 locked the gate.
76749  *  0b1101..Domain 12 locked the gate.
76750  *  0b1110..Domain 13 locked the gate.
76751  *  0b1111..Domain 14 locked the gate.
76752  */
76753 #define SEMA42_GATE36_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE36_GTFSM_SHIFT)) & SEMA42_GATE36_GTFSM_MASK)
76754 /*! @} */
76755 
76756 /*! @name GATE43 - Gate */
76757 /*! @{ */
76758 
76759 #define SEMA42_GATE43_GTFSM_MASK                 (0xFU)
76760 #define SEMA42_GATE43_GTFSM_SHIFT                (0U)
76761 /*! GTFSM - Gate Finite State Machine
76762  *  0b0000..The gate is unlocked (free).
76763  *  0b0001..Domain 0 locked the gate.
76764  *  0b0010..Domain 1 locked the gate.
76765  *  0b0011..Domain 2 locked the gate.
76766  *  0b0100..Domain 3 locked the gate.
76767  *  0b0101..Domain 4 locked the gate.
76768  *  0b0110..Domain 5 locked the gate.
76769  *  0b0111..Domain 6 locked the gate.
76770  *  0b1000..Domain 7 locked the gate.
76771  *  0b1001..Domain 8 locked the gate.
76772  *  0b1010..Domain 9 locked the gate.
76773  *  0b1011..Domain 10 locked the gate.
76774  *  0b1100..Domain 11 locked the gate.
76775  *  0b1101..Domain 12 locked the gate.
76776  *  0b1110..Domain 13 locked the gate.
76777  *  0b1111..Domain 14 locked the gate.
76778  */
76779 #define SEMA42_GATE43_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE43_GTFSM_SHIFT)) & SEMA42_GATE43_GTFSM_MASK)
76780 /*! @} */
76781 
76782 /*! @name GATE42 - Gate */
76783 /*! @{ */
76784 
76785 #define SEMA42_GATE42_GTFSM_MASK                 (0xFU)
76786 #define SEMA42_GATE42_GTFSM_SHIFT                (0U)
76787 /*! GTFSM - Gate Finite State Machine
76788  *  0b0000..The gate is unlocked (free).
76789  *  0b0001..Domain 0 locked the gate.
76790  *  0b0010..Domain 1 locked the gate.
76791  *  0b0011..Domain 2 locked the gate.
76792  *  0b0100..Domain 3 locked the gate.
76793  *  0b0101..Domain 4 locked the gate.
76794  *  0b0110..Domain 5 locked the gate.
76795  *  0b0111..Domain 6 locked the gate.
76796  *  0b1000..Domain 7 locked the gate.
76797  *  0b1001..Domain 8 locked the gate.
76798  *  0b1010..Domain 9 locked the gate.
76799  *  0b1011..Domain 10 locked the gate.
76800  *  0b1100..Domain 11 locked the gate.
76801  *  0b1101..Domain 12 locked the gate.
76802  *  0b1110..Domain 13 locked the gate.
76803  *  0b1111..Domain 14 locked the gate.
76804  */
76805 #define SEMA42_GATE42_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE42_GTFSM_SHIFT)) & SEMA42_GATE42_GTFSM_MASK)
76806 /*! @} */
76807 
76808 /*! @name GATE41 - Gate */
76809 /*! @{ */
76810 
76811 #define SEMA42_GATE41_GTFSM_MASK                 (0xFU)
76812 #define SEMA42_GATE41_GTFSM_SHIFT                (0U)
76813 /*! GTFSM - Gate Finite State Machine
76814  *  0b0000..The gate is unlocked (free).
76815  *  0b0001..Domain 0 locked the gate.
76816  *  0b0010..Domain 1 locked the gate.
76817  *  0b0011..Domain 2 locked the gate.
76818  *  0b0100..Domain 3 locked the gate.
76819  *  0b0101..Domain 4 locked the gate.
76820  *  0b0110..Domain 5 locked the gate.
76821  *  0b0111..Domain 6 locked the gate.
76822  *  0b1000..Domain 7 locked the gate.
76823  *  0b1001..Domain 8 locked the gate.
76824  *  0b1010..Domain 9 locked the gate.
76825  *  0b1011..Domain 10 locked the gate.
76826  *  0b1100..Domain 11 locked the gate.
76827  *  0b1101..Domain 12 locked the gate.
76828  *  0b1110..Domain 13 locked the gate.
76829  *  0b1111..Domain 14 locked the gate.
76830  */
76831 #define SEMA42_GATE41_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE41_GTFSM_SHIFT)) & SEMA42_GATE41_GTFSM_MASK)
76832 /*! @} */
76833 
76834 /*! @name GATE40 - Gate */
76835 /*! @{ */
76836 
76837 #define SEMA42_GATE40_GTFSM_MASK                 (0xFU)
76838 #define SEMA42_GATE40_GTFSM_SHIFT                (0U)
76839 /*! GTFSM - Gate Finite State Machine
76840  *  0b0000..The gate is unlocked (free).
76841  *  0b0001..Domain 0 locked the gate.
76842  *  0b0010..Domain 1 locked the gate.
76843  *  0b0011..Domain 2 locked the gate.
76844  *  0b0100..Domain 3 locked the gate.
76845  *  0b0101..Domain 4 locked the gate.
76846  *  0b0110..Domain 5 locked the gate.
76847  *  0b0111..Domain 6 locked the gate.
76848  *  0b1000..Domain 7 locked the gate.
76849  *  0b1001..Domain 8 locked the gate.
76850  *  0b1010..Domain 9 locked the gate.
76851  *  0b1011..Domain 10 locked the gate.
76852  *  0b1100..Domain 11 locked the gate.
76853  *  0b1101..Domain 12 locked the gate.
76854  *  0b1110..Domain 13 locked the gate.
76855  *  0b1111..Domain 14 locked the gate.
76856  */
76857 #define SEMA42_GATE40_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE40_GTFSM_SHIFT)) & SEMA42_GATE40_GTFSM_MASK)
76858 /*! @} */
76859 
76860 /*! @name GATE47 - Gate */
76861 /*! @{ */
76862 
76863 #define SEMA42_GATE47_GTFSM_MASK                 (0xFU)
76864 #define SEMA42_GATE47_GTFSM_SHIFT                (0U)
76865 /*! GTFSM - Gate Finite State Machine
76866  *  0b0000..The gate is unlocked (free).
76867  *  0b0001..Domain 0 locked the gate.
76868  *  0b0010..Domain 1 locked the gate.
76869  *  0b0011..Domain 2 locked the gate.
76870  *  0b0100..Domain 3 locked the gate.
76871  *  0b0101..Domain 4 locked the gate.
76872  *  0b0110..Domain 5 locked the gate.
76873  *  0b0111..Domain 6 locked the gate.
76874  *  0b1000..Domain 7 locked the gate.
76875  *  0b1001..Domain 8 locked the gate.
76876  *  0b1010..Domain 9 locked the gate.
76877  *  0b1011..Domain 10 locked the gate.
76878  *  0b1100..Domain 11 locked the gate.
76879  *  0b1101..Domain 12 locked the gate.
76880  *  0b1110..Domain 13 locked the gate.
76881  *  0b1111..Domain 14 locked the gate.
76882  */
76883 #define SEMA42_GATE47_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE47_GTFSM_SHIFT)) & SEMA42_GATE47_GTFSM_MASK)
76884 /*! @} */
76885 
76886 /*! @name GATE46 - Gate */
76887 /*! @{ */
76888 
76889 #define SEMA42_GATE46_GTFSM_MASK                 (0xFU)
76890 #define SEMA42_GATE46_GTFSM_SHIFT                (0U)
76891 /*! GTFSM - Gate Finite State Machine
76892  *  0b0000..The gate is unlocked (free).
76893  *  0b0001..Domain 0 locked the gate.
76894  *  0b0010..Domain 1 locked the gate.
76895  *  0b0011..Domain 2 locked the gate.
76896  *  0b0100..Domain 3 locked the gate.
76897  *  0b0101..Domain 4 locked the gate.
76898  *  0b0110..Domain 5 locked the gate.
76899  *  0b0111..Domain 6 locked the gate.
76900  *  0b1000..Domain 7 locked the gate.
76901  *  0b1001..Domain 8 locked the gate.
76902  *  0b1010..Domain 9 locked the gate.
76903  *  0b1011..Domain 10 locked the gate.
76904  *  0b1100..Domain 11 locked the gate.
76905  *  0b1101..Domain 12 locked the gate.
76906  *  0b1110..Domain 13 locked the gate.
76907  *  0b1111..Domain 14 locked the gate.
76908  */
76909 #define SEMA42_GATE46_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE46_GTFSM_SHIFT)) & SEMA42_GATE46_GTFSM_MASK)
76910 /*! @} */
76911 
76912 /*! @name GATE45 - Gate */
76913 /*! @{ */
76914 
76915 #define SEMA42_GATE45_GTFSM_MASK                 (0xFU)
76916 #define SEMA42_GATE45_GTFSM_SHIFT                (0U)
76917 /*! GTFSM - Gate Finite State Machine
76918  *  0b0000..The gate is unlocked (free).
76919  *  0b0001..Domain 0 locked the gate.
76920  *  0b0010..Domain 1 locked the gate.
76921  *  0b0011..Domain 2 locked the gate.
76922  *  0b0100..Domain 3 locked the gate.
76923  *  0b0101..Domain 4 locked the gate.
76924  *  0b0110..Domain 5 locked the gate.
76925  *  0b0111..Domain 6 locked the gate.
76926  *  0b1000..Domain 7 locked the gate.
76927  *  0b1001..Domain 8 locked the gate.
76928  *  0b1010..Domain 9 locked the gate.
76929  *  0b1011..Domain 10 locked the gate.
76930  *  0b1100..Domain 11 locked the gate.
76931  *  0b1101..Domain 12 locked the gate.
76932  *  0b1110..Domain 13 locked the gate.
76933  *  0b1111..Domain 14 locked the gate.
76934  */
76935 #define SEMA42_GATE45_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE45_GTFSM_SHIFT)) & SEMA42_GATE45_GTFSM_MASK)
76936 /*! @} */
76937 
76938 /*! @name GATE44 - Gate */
76939 /*! @{ */
76940 
76941 #define SEMA42_GATE44_GTFSM_MASK                 (0xFU)
76942 #define SEMA42_GATE44_GTFSM_SHIFT                (0U)
76943 /*! GTFSM - Gate Finite State Machine
76944  *  0b0000..The gate is unlocked (free).
76945  *  0b0001..Domain 0 locked the gate.
76946  *  0b0010..Domain 1 locked the gate.
76947  *  0b0011..Domain 2 locked the gate.
76948  *  0b0100..Domain 3 locked the gate.
76949  *  0b0101..Domain 4 locked the gate.
76950  *  0b0110..Domain 5 locked the gate.
76951  *  0b0111..Domain 6 locked the gate.
76952  *  0b1000..Domain 7 locked the gate.
76953  *  0b1001..Domain 8 locked the gate.
76954  *  0b1010..Domain 9 locked the gate.
76955  *  0b1011..Domain 10 locked the gate.
76956  *  0b1100..Domain 11 locked the gate.
76957  *  0b1101..Domain 12 locked the gate.
76958  *  0b1110..Domain 13 locked the gate.
76959  *  0b1111..Domain 14 locked the gate.
76960  */
76961 #define SEMA42_GATE44_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE44_GTFSM_SHIFT)) & SEMA42_GATE44_GTFSM_MASK)
76962 /*! @} */
76963 
76964 /*! @name GATE51 - Gate */
76965 /*! @{ */
76966 
76967 #define SEMA42_GATE51_GTFSM_MASK                 (0xFU)
76968 #define SEMA42_GATE51_GTFSM_SHIFT                (0U)
76969 /*! GTFSM - Gate Finite State Machine
76970  *  0b0000..The gate is unlocked (free).
76971  *  0b0001..Domain 0 locked the gate.
76972  *  0b0010..Domain 1 locked the gate.
76973  *  0b0011..Domain 2 locked the gate.
76974  *  0b0100..Domain 3 locked the gate.
76975  *  0b0101..Domain 4 locked the gate.
76976  *  0b0110..Domain 5 locked the gate.
76977  *  0b0111..Domain 6 locked the gate.
76978  *  0b1000..Domain 7 locked the gate.
76979  *  0b1001..Domain 8 locked the gate.
76980  *  0b1010..Domain 9 locked the gate.
76981  *  0b1011..Domain 10 locked the gate.
76982  *  0b1100..Domain 11 locked the gate.
76983  *  0b1101..Domain 12 locked the gate.
76984  *  0b1110..Domain 13 locked the gate.
76985  *  0b1111..Domain 14 locked the gate.
76986  */
76987 #define SEMA42_GATE51_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE51_GTFSM_SHIFT)) & SEMA42_GATE51_GTFSM_MASK)
76988 /*! @} */
76989 
76990 /*! @name GATE50 - Gate */
76991 /*! @{ */
76992 
76993 #define SEMA42_GATE50_GTFSM_MASK                 (0xFU)
76994 #define SEMA42_GATE50_GTFSM_SHIFT                (0U)
76995 /*! GTFSM - Gate Finite State Machine
76996  *  0b0000..The gate is unlocked (free).
76997  *  0b0001..Domain 0 locked the gate.
76998  *  0b0010..Domain 1 locked the gate.
76999  *  0b0011..Domain 2 locked the gate.
77000  *  0b0100..Domain 3 locked the gate.
77001  *  0b0101..Domain 4 locked the gate.
77002  *  0b0110..Domain 5 locked the gate.
77003  *  0b0111..Domain 6 locked the gate.
77004  *  0b1000..Domain 7 locked the gate.
77005  *  0b1001..Domain 8 locked the gate.
77006  *  0b1010..Domain 9 locked the gate.
77007  *  0b1011..Domain 10 locked the gate.
77008  *  0b1100..Domain 11 locked the gate.
77009  *  0b1101..Domain 12 locked the gate.
77010  *  0b1110..Domain 13 locked the gate.
77011  *  0b1111..Domain 14 locked the gate.
77012  */
77013 #define SEMA42_GATE50_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE50_GTFSM_SHIFT)) & SEMA42_GATE50_GTFSM_MASK)
77014 /*! @} */
77015 
77016 /*! @name GATE49 - Gate */
77017 /*! @{ */
77018 
77019 #define SEMA42_GATE49_GTFSM_MASK                 (0xFU)
77020 #define SEMA42_GATE49_GTFSM_SHIFT                (0U)
77021 /*! GTFSM - Gate Finite State Machine
77022  *  0b0000..The gate is unlocked (free).
77023  *  0b0001..Domain 0 locked the gate.
77024  *  0b0010..Domain 1 locked the gate.
77025  *  0b0011..Domain 2 locked the gate.
77026  *  0b0100..Domain 3 locked the gate.
77027  *  0b0101..Domain 4 locked the gate.
77028  *  0b0110..Domain 5 locked the gate.
77029  *  0b0111..Domain 6 locked the gate.
77030  *  0b1000..Domain 7 locked the gate.
77031  *  0b1001..Domain 8 locked the gate.
77032  *  0b1010..Domain 9 locked the gate.
77033  *  0b1011..Domain 10 locked the gate.
77034  *  0b1100..Domain 11 locked the gate.
77035  *  0b1101..Domain 12 locked the gate.
77036  *  0b1110..Domain 13 locked the gate.
77037  *  0b1111..Domain 14 locked the gate.
77038  */
77039 #define SEMA42_GATE49_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE49_GTFSM_SHIFT)) & SEMA42_GATE49_GTFSM_MASK)
77040 /*! @} */
77041 
77042 /*! @name GATE48 - Gate */
77043 /*! @{ */
77044 
77045 #define SEMA42_GATE48_GTFSM_MASK                 (0xFU)
77046 #define SEMA42_GATE48_GTFSM_SHIFT                (0U)
77047 /*! GTFSM - Gate Finite State Machine
77048  *  0b0000..The gate is unlocked (free).
77049  *  0b0001..Domain 0 locked the gate.
77050  *  0b0010..Domain 1 locked the gate.
77051  *  0b0011..Domain 2 locked the gate.
77052  *  0b0100..Domain 3 locked the gate.
77053  *  0b0101..Domain 4 locked the gate.
77054  *  0b0110..Domain 5 locked the gate.
77055  *  0b0111..Domain 6 locked the gate.
77056  *  0b1000..Domain 7 locked the gate.
77057  *  0b1001..Domain 8 locked the gate.
77058  *  0b1010..Domain 9 locked the gate.
77059  *  0b1011..Domain 10 locked the gate.
77060  *  0b1100..Domain 11 locked the gate.
77061  *  0b1101..Domain 12 locked the gate.
77062  *  0b1110..Domain 13 locked the gate.
77063  *  0b1111..Domain 14 locked the gate.
77064  */
77065 #define SEMA42_GATE48_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE48_GTFSM_SHIFT)) & SEMA42_GATE48_GTFSM_MASK)
77066 /*! @} */
77067 
77068 /*! @name GATE55 - Gate */
77069 /*! @{ */
77070 
77071 #define SEMA42_GATE55_GTFSM_MASK                 (0xFU)
77072 #define SEMA42_GATE55_GTFSM_SHIFT                (0U)
77073 /*! GTFSM - Gate Finite State Machine
77074  *  0b0000..The gate is unlocked (free).
77075  *  0b0001..Domain 0 locked the gate.
77076  *  0b0010..Domain 1 locked the gate.
77077  *  0b0011..Domain 2 locked the gate.
77078  *  0b0100..Domain 3 locked the gate.
77079  *  0b0101..Domain 4 locked the gate.
77080  *  0b0110..Domain 5 locked the gate.
77081  *  0b0111..Domain 6 locked the gate.
77082  *  0b1000..Domain 7 locked the gate.
77083  *  0b1001..Domain 8 locked the gate.
77084  *  0b1010..Domain 9 locked the gate.
77085  *  0b1011..Domain 10 locked the gate.
77086  *  0b1100..Domain 11 locked the gate.
77087  *  0b1101..Domain 12 locked the gate.
77088  *  0b1110..Domain 13 locked the gate.
77089  *  0b1111..Domain 14 locked the gate.
77090  */
77091 #define SEMA42_GATE55_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE55_GTFSM_SHIFT)) & SEMA42_GATE55_GTFSM_MASK)
77092 /*! @} */
77093 
77094 /*! @name GATE54 - Gate */
77095 /*! @{ */
77096 
77097 #define SEMA42_GATE54_GTFSM_MASK                 (0xFU)
77098 #define SEMA42_GATE54_GTFSM_SHIFT                (0U)
77099 /*! GTFSM - Gate Finite State Machine
77100  *  0b0000..The gate is unlocked (free).
77101  *  0b0001..Domain 0 locked the gate.
77102  *  0b0010..Domain 1 locked the gate.
77103  *  0b0011..Domain 2 locked the gate.
77104  *  0b0100..Domain 3 locked the gate.
77105  *  0b0101..Domain 4 locked the gate.
77106  *  0b0110..Domain 5 locked the gate.
77107  *  0b0111..Domain 6 locked the gate.
77108  *  0b1000..Domain 7 locked the gate.
77109  *  0b1001..Domain 8 locked the gate.
77110  *  0b1010..Domain 9 locked the gate.
77111  *  0b1011..Domain 10 locked the gate.
77112  *  0b1100..Domain 11 locked the gate.
77113  *  0b1101..Domain 12 locked the gate.
77114  *  0b1110..Domain 13 locked the gate.
77115  *  0b1111..Domain 14 locked the gate.
77116  */
77117 #define SEMA42_GATE54_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE54_GTFSM_SHIFT)) & SEMA42_GATE54_GTFSM_MASK)
77118 /*! @} */
77119 
77120 /*! @name GATE53 - Gate */
77121 /*! @{ */
77122 
77123 #define SEMA42_GATE53_GTFSM_MASK                 (0xFU)
77124 #define SEMA42_GATE53_GTFSM_SHIFT                (0U)
77125 /*! GTFSM - Gate Finite State Machine
77126  *  0b0000..The gate is unlocked (free).
77127  *  0b0001..Domain 0 locked the gate.
77128  *  0b0010..Domain 1 locked the gate.
77129  *  0b0011..Domain 2 locked the gate.
77130  *  0b0100..Domain 3 locked the gate.
77131  *  0b0101..Domain 4 locked the gate.
77132  *  0b0110..Domain 5 locked the gate.
77133  *  0b0111..Domain 6 locked the gate.
77134  *  0b1000..Domain 7 locked the gate.
77135  *  0b1001..Domain 8 locked the gate.
77136  *  0b1010..Domain 9 locked the gate.
77137  *  0b1011..Domain 10 locked the gate.
77138  *  0b1100..Domain 11 locked the gate.
77139  *  0b1101..Domain 12 locked the gate.
77140  *  0b1110..Domain 13 locked the gate.
77141  *  0b1111..Domain 14 locked the gate.
77142  */
77143 #define SEMA42_GATE53_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE53_GTFSM_SHIFT)) & SEMA42_GATE53_GTFSM_MASK)
77144 /*! @} */
77145 
77146 /*! @name GATE52 - Gate */
77147 /*! @{ */
77148 
77149 #define SEMA42_GATE52_GTFSM_MASK                 (0xFU)
77150 #define SEMA42_GATE52_GTFSM_SHIFT                (0U)
77151 /*! GTFSM - Gate Finite State Machine
77152  *  0b0000..The gate is unlocked (free).
77153  *  0b0001..Domain 0 locked the gate.
77154  *  0b0010..Domain 1 locked the gate.
77155  *  0b0011..Domain 2 locked the gate.
77156  *  0b0100..Domain 3 locked the gate.
77157  *  0b0101..Domain 4 locked the gate.
77158  *  0b0110..Domain 5 locked the gate.
77159  *  0b0111..Domain 6 locked the gate.
77160  *  0b1000..Domain 7 locked the gate.
77161  *  0b1001..Domain 8 locked the gate.
77162  *  0b1010..Domain 9 locked the gate.
77163  *  0b1011..Domain 10 locked the gate.
77164  *  0b1100..Domain 11 locked the gate.
77165  *  0b1101..Domain 12 locked the gate.
77166  *  0b1110..Domain 13 locked the gate.
77167  *  0b1111..Domain 14 locked the gate.
77168  */
77169 #define SEMA42_GATE52_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE52_GTFSM_SHIFT)) & SEMA42_GATE52_GTFSM_MASK)
77170 /*! @} */
77171 
77172 /*! @name GATE59 - Gate */
77173 /*! @{ */
77174 
77175 #define SEMA42_GATE59_GTFSM_MASK                 (0xFU)
77176 #define SEMA42_GATE59_GTFSM_SHIFT                (0U)
77177 /*! GTFSM - Gate Finite State Machine
77178  *  0b0000..The gate is unlocked (free).
77179  *  0b0001..Domain 0 locked the gate.
77180  *  0b0010..Domain 1 locked the gate.
77181  *  0b0011..Domain 2 locked the gate.
77182  *  0b0100..Domain 3 locked the gate.
77183  *  0b0101..Domain 4 locked the gate.
77184  *  0b0110..Domain 5 locked the gate.
77185  *  0b0111..Domain 6 locked the gate.
77186  *  0b1000..Domain 7 locked the gate.
77187  *  0b1001..Domain 8 locked the gate.
77188  *  0b1010..Domain 9 locked the gate.
77189  *  0b1011..Domain 10 locked the gate.
77190  *  0b1100..Domain 11 locked the gate.
77191  *  0b1101..Domain 12 locked the gate.
77192  *  0b1110..Domain 13 locked the gate.
77193  *  0b1111..Domain 14 locked the gate.
77194  */
77195 #define SEMA42_GATE59_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE59_GTFSM_SHIFT)) & SEMA42_GATE59_GTFSM_MASK)
77196 /*! @} */
77197 
77198 /*! @name GATE58 - Gate */
77199 /*! @{ */
77200 
77201 #define SEMA42_GATE58_GTFSM_MASK                 (0xFU)
77202 #define SEMA42_GATE58_GTFSM_SHIFT                (0U)
77203 /*! GTFSM - Gate Finite State Machine
77204  *  0b0000..The gate is unlocked (free).
77205  *  0b0001..Domain 0 locked the gate.
77206  *  0b0010..Domain 1 locked the gate.
77207  *  0b0011..Domain 2 locked the gate.
77208  *  0b0100..Domain 3 locked the gate.
77209  *  0b0101..Domain 4 locked the gate.
77210  *  0b0110..Domain 5 locked the gate.
77211  *  0b0111..Domain 6 locked the gate.
77212  *  0b1000..Domain 7 locked the gate.
77213  *  0b1001..Domain 8 locked the gate.
77214  *  0b1010..Domain 9 locked the gate.
77215  *  0b1011..Domain 10 locked the gate.
77216  *  0b1100..Domain 11 locked the gate.
77217  *  0b1101..Domain 12 locked the gate.
77218  *  0b1110..Domain 13 locked the gate.
77219  *  0b1111..Domain 14 locked the gate.
77220  */
77221 #define SEMA42_GATE58_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE58_GTFSM_SHIFT)) & SEMA42_GATE58_GTFSM_MASK)
77222 /*! @} */
77223 
77224 /*! @name GATE57 - Gate */
77225 /*! @{ */
77226 
77227 #define SEMA42_GATE57_GTFSM_MASK                 (0xFU)
77228 #define SEMA42_GATE57_GTFSM_SHIFT                (0U)
77229 /*! GTFSM - Gate Finite State Machine
77230  *  0b0000..The gate is unlocked (free).
77231  *  0b0001..Domain 0 locked the gate.
77232  *  0b0010..Domain 1 locked the gate.
77233  *  0b0011..Domain 2 locked the gate.
77234  *  0b0100..Domain 3 locked the gate.
77235  *  0b0101..Domain 4 locked the gate.
77236  *  0b0110..Domain 5 locked the gate.
77237  *  0b0111..Domain 6 locked the gate.
77238  *  0b1000..Domain 7 locked the gate.
77239  *  0b1001..Domain 8 locked the gate.
77240  *  0b1010..Domain 9 locked the gate.
77241  *  0b1011..Domain 10 locked the gate.
77242  *  0b1100..Domain 11 locked the gate.
77243  *  0b1101..Domain 12 locked the gate.
77244  *  0b1110..Domain 13 locked the gate.
77245  *  0b1111..Domain 14 locked the gate.
77246  */
77247 #define SEMA42_GATE57_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE57_GTFSM_SHIFT)) & SEMA42_GATE57_GTFSM_MASK)
77248 /*! @} */
77249 
77250 /*! @name GATE56 - Gate */
77251 /*! @{ */
77252 
77253 #define SEMA42_GATE56_GTFSM_MASK                 (0xFU)
77254 #define SEMA42_GATE56_GTFSM_SHIFT                (0U)
77255 /*! GTFSM - Gate Finite State Machine
77256  *  0b0000..The gate is unlocked (free).
77257  *  0b0001..Domain 0 locked the gate.
77258  *  0b0010..Domain 1 locked the gate.
77259  *  0b0011..Domain 2 locked the gate.
77260  *  0b0100..Domain 3 locked the gate.
77261  *  0b0101..Domain 4 locked the gate.
77262  *  0b0110..Domain 5 locked the gate.
77263  *  0b0111..Domain 6 locked the gate.
77264  *  0b1000..Domain 7 locked the gate.
77265  *  0b1001..Domain 8 locked the gate.
77266  *  0b1010..Domain 9 locked the gate.
77267  *  0b1011..Domain 10 locked the gate.
77268  *  0b1100..Domain 11 locked the gate.
77269  *  0b1101..Domain 12 locked the gate.
77270  *  0b1110..Domain 13 locked the gate.
77271  *  0b1111..Domain 14 locked the gate.
77272  */
77273 #define SEMA42_GATE56_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE56_GTFSM_SHIFT)) & SEMA42_GATE56_GTFSM_MASK)
77274 /*! @} */
77275 
77276 /*! @name GATE63 - Gate */
77277 /*! @{ */
77278 
77279 #define SEMA42_GATE63_GTFSM_MASK                 (0xFU)
77280 #define SEMA42_GATE63_GTFSM_SHIFT                (0U)
77281 /*! GTFSM - Gate Finite State Machine
77282  *  0b0000..The gate is unlocked (free).
77283  *  0b0001..Domain 0 locked the gate.
77284  *  0b0010..Domain 1 locked the gate.
77285  *  0b0011..Domain 2 locked the gate.
77286  *  0b0100..Domain 3 locked the gate.
77287  *  0b0101..Domain 4 locked the gate.
77288  *  0b0110..Domain 5 locked the gate.
77289  *  0b0111..Domain 6 locked the gate.
77290  *  0b1000..Domain 7 locked the gate.
77291  *  0b1001..Domain 8 locked the gate.
77292  *  0b1010..Domain 9 locked the gate.
77293  *  0b1011..Domain 10 locked the gate.
77294  *  0b1100..Domain 11 locked the gate.
77295  *  0b1101..Domain 12 locked the gate.
77296  *  0b1110..Domain 13 locked the gate.
77297  *  0b1111..Domain 14 locked the gate.
77298  */
77299 #define SEMA42_GATE63_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE63_GTFSM_SHIFT)) & SEMA42_GATE63_GTFSM_MASK)
77300 /*! @} */
77301 
77302 /*! @name GATE62 - Gate */
77303 /*! @{ */
77304 
77305 #define SEMA42_GATE62_GTFSM_MASK                 (0xFU)
77306 #define SEMA42_GATE62_GTFSM_SHIFT                (0U)
77307 /*! GTFSM - Gate Finite State Machine
77308  *  0b0000..The gate is unlocked (free).
77309  *  0b0001..Domain 0 locked the gate.
77310  *  0b0010..Domain 1 locked the gate.
77311  *  0b0011..Domain 2 locked the gate.
77312  *  0b0100..Domain 3 locked the gate.
77313  *  0b0101..Domain 4 locked the gate.
77314  *  0b0110..Domain 5 locked the gate.
77315  *  0b0111..Domain 6 locked the gate.
77316  *  0b1000..Domain 7 locked the gate.
77317  *  0b1001..Domain 8 locked the gate.
77318  *  0b1010..Domain 9 locked the gate.
77319  *  0b1011..Domain 10 locked the gate.
77320  *  0b1100..Domain 11 locked the gate.
77321  *  0b1101..Domain 12 locked the gate.
77322  *  0b1110..Domain 13 locked the gate.
77323  *  0b1111..Domain 14 locked the gate.
77324  */
77325 #define SEMA42_GATE62_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE62_GTFSM_SHIFT)) & SEMA42_GATE62_GTFSM_MASK)
77326 /*! @} */
77327 
77328 /*! @name GATE61 - Gate */
77329 /*! @{ */
77330 
77331 #define SEMA42_GATE61_GTFSM_MASK                 (0xFU)
77332 #define SEMA42_GATE61_GTFSM_SHIFT                (0U)
77333 /*! GTFSM - Gate Finite State Machine
77334  *  0b0000..The gate is unlocked (free).
77335  *  0b0001..Domain 0 locked the gate.
77336  *  0b0010..Domain 1 locked the gate.
77337  *  0b0011..Domain 2 locked the gate.
77338  *  0b0100..Domain 3 locked the gate.
77339  *  0b0101..Domain 4 locked the gate.
77340  *  0b0110..Domain 5 locked the gate.
77341  *  0b0111..Domain 6 locked the gate.
77342  *  0b1000..Domain 7 locked the gate.
77343  *  0b1001..Domain 8 locked the gate.
77344  *  0b1010..Domain 9 locked the gate.
77345  *  0b1011..Domain 10 locked the gate.
77346  *  0b1100..Domain 11 locked the gate.
77347  *  0b1101..Domain 12 locked the gate.
77348  *  0b1110..Domain 13 locked the gate.
77349  *  0b1111..Domain 14 locked the gate.
77350  */
77351 #define SEMA42_GATE61_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE61_GTFSM_SHIFT)) & SEMA42_GATE61_GTFSM_MASK)
77352 /*! @} */
77353 
77354 /*! @name GATE60 - Gate */
77355 /*! @{ */
77356 
77357 #define SEMA42_GATE60_GTFSM_MASK                 (0xFU)
77358 #define SEMA42_GATE60_GTFSM_SHIFT                (0U)
77359 /*! GTFSM - Gate Finite State Machine
77360  *  0b0000..The gate is unlocked (free).
77361  *  0b0001..Domain 0 locked the gate.
77362  *  0b0010..Domain 1 locked the gate.
77363  *  0b0011..Domain 2 locked the gate.
77364  *  0b0100..Domain 3 locked the gate.
77365  *  0b0101..Domain 4 locked the gate.
77366  *  0b0110..Domain 5 locked the gate.
77367  *  0b0111..Domain 6 locked the gate.
77368  *  0b1000..Domain 7 locked the gate.
77369  *  0b1001..Domain 8 locked the gate.
77370  *  0b1010..Domain 9 locked the gate.
77371  *  0b1011..Domain 10 locked the gate.
77372  *  0b1100..Domain 11 locked the gate.
77373  *  0b1101..Domain 12 locked the gate.
77374  *  0b1110..Domain 13 locked the gate.
77375  *  0b1111..Domain 14 locked the gate.
77376  */
77377 #define SEMA42_GATE60_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE60_GTFSM_SHIFT)) & SEMA42_GATE60_GTFSM_MASK)
77378 /*! @} */
77379 
77380 /*! @name RSTGT_R - Reset Gate Read */
77381 /*! @{ */
77382 
77383 #define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
77384 #define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
77385 /*! RSTGTN - Reset Gate Number */
77386 #define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
77387 
77388 #define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
77389 #define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
77390 /*! RSTGMS - Reset Gate Domain */
77391 #define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
77392 
77393 #define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
77394 #define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
77395 /*! RSTGSM - Reset Gate Finite State Machine
77396  *  0b00..Idle, waiting for the first data pattern write.
77397  *  0b01..Waiting for the second data pattern write
77398  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
77399  *        this machine returns to the idle (waiting for first data pattern write) state.
77400  *  0b11..This state encoding is never used and therefore reserved.
77401  */
77402 #define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
77403 /*! @} */
77404 
77405 /*! @name RSTGT_W - Reset Gate Write */
77406 /*! @{ */
77407 
77408 #define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
77409 #define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
77410 /*! RSTGTN - Reset Gate Number */
77411 #define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
77412 
77413 #define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
77414 #define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
77415 /*! RSTGDP - Reset Gate Data Pattern */
77416 #define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
77417 /*! @} */
77418 
77419 
77420 /*!
77421  * @}
77422  */ /* end of group SEMA42_Register_Masks */
77423 
77424 
77425 /* SEMA42 - Peripheral instance base addresses */
77426 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
77427   /** Peripheral SEMA1 base address */
77428   #define SEMA1_BASE                               (0x54260000u)
77429   /** Peripheral SEMA1 base address */
77430   #define SEMA1_BASE_NS                            (0x44260000u)
77431   /** Peripheral SEMA1 base pointer */
77432   #define SEMA1                                    ((SEMA42_Type *)SEMA1_BASE)
77433   /** Peripheral SEMA1 base pointer */
77434   #define SEMA1_NS                                 ((SEMA42_Type *)SEMA1_BASE_NS)
77435   /** Peripheral SEMA2 base address */
77436   #define SEMA2_BASE                               (0x52450000u)
77437   /** Peripheral SEMA2 base address */
77438   #define SEMA2_BASE_NS                            (0x42450000u)
77439   /** Peripheral SEMA2 base pointer */
77440   #define SEMA2                                    ((SEMA42_Type *)SEMA2_BASE)
77441   /** Peripheral SEMA2 base pointer */
77442   #define SEMA2_NS                                 ((SEMA42_Type *)SEMA2_BASE_NS)
77443   /** Array initializer of SEMA42 peripheral base addresses */
77444   #define SEMA42_BASE_ADDRS                        { SEMA1_BASE, SEMA2_BASE }
77445   /** Array initializer of SEMA42 peripheral base pointers */
77446   #define SEMA42_BASE_PTRS                         { SEMA1, SEMA2 }
77447   /** Array initializer of SEMA42 peripheral base addresses */
77448   #define SEMA42_BASE_ADDRS_NS                     { SEMA1_BASE_NS, SEMA2_BASE_NS }
77449   /** Array initializer of SEMA42 peripheral base pointers */
77450   #define SEMA42_BASE_PTRS_NS                      { SEMA1_NS, SEMA2_NS }
77451 #else
77452   /** Peripheral SEMA1 base address */
77453   #define SEMA1_BASE                               (0x44260000u)
77454   /** Peripheral SEMA1 base pointer */
77455   #define SEMA1                                    ((SEMA42_Type *)SEMA1_BASE)
77456   /** Peripheral SEMA2 base address */
77457   #define SEMA2_BASE                               (0x42450000u)
77458   /** Peripheral SEMA2 base pointer */
77459   #define SEMA2                                    ((SEMA42_Type *)SEMA2_BASE)
77460   /** Array initializer of SEMA42 peripheral base addresses */
77461   #define SEMA42_BASE_ADDRS                        { SEMA1_BASE, SEMA2_BASE }
77462   /** Array initializer of SEMA42 peripheral base pointers */
77463   #define SEMA42_BASE_PTRS                         { SEMA1, SEMA2 }
77464 #endif
77465 
77466 /*!
77467  * @}
77468  */ /* end of group SEMA42_Peripheral_Access_Layer */
77469 
77470 
77471 /* ----------------------------------------------------------------------------
77472    -- SPDIF Peripheral Access Layer
77473    ---------------------------------------------------------------------------- */
77474 
77475 /*!
77476  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
77477  * @{
77478  */
77479 
77480 /** SPDIF - Register Layout Typedef */
77481 typedef struct {
77482   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
77483   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
77484   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
77485   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
77486   __IO uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
77487   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
77488   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
77489   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
77490   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
77491   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
77492   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
77493   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
77494   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
77495   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
77496   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
77497        uint8_t RESERVED_0[8];
77498   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
77499        uint8_t RESERVED_1[8];
77500   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
77501        uint8_t RESERVED_2[12];
77502   __I  uint32_t SPDIFRXCCHANNEL_ADDR_31_0;         /**< SPDIF receive C channel register, bits 31-0, offset: 0x60 */
77503   __I  uint32_t SPDIFRXCCHANNEL_ADDR_63_32;        /**< SPDIF receive C channel register, bits 63-32, offset: 0x64 */
77504   __I  uint32_t SPDIFRXCCHANNEL_ADDR_95_64;        /**< SPDIF receive C channel register, bits 95-64, offset: 0x68 */
77505   __I  uint32_t SPDIFRXCCHANNEL_ADDR_127_96;       /**< SPDIF receive C channel register, bits 127-96, offset: 0x6C */
77506   __I  uint32_t SPDIFRXCCHANNEL_ADDR_159_128;      /**< SPDIF receive C channel register, bits 159-128, offset: 0x70 */
77507   __I  uint32_t SPDIFRXCCHANNEL_ADDR_191_160;      /**< SPDIF receive C channel register, bits 191-160, offset: 0x74 */
77508   __IO uint32_t SPDIFTXCCHANNEL_ADDR_31_0;         /**< SPDIF transmit C channel register, bits 31-0, offset: 0x78 */
77509   __IO uint32_t SPDIFTXCCHANNEL_ADDR_63_32;        /**< SPDIF transmit C channel register, bits 63-32, offset: 0x7C */
77510   __IO uint32_t SPDIFTXCCHANNEL_ADDR_95_64;        /**< SPDIF transmit C channel register, bits 95-64, offset: 0x80 */
77511   __IO uint32_t SPDIFTXCCHANNEL_ADDR_127_96;       /**< SPDIF transmit C channel register, bits 127-96, offset: 0x84 */
77512   __IO uint32_t SPDIFTXCCHANNEL_ADDR_159_128;      /**< SPDIF transmit C channel register, bits 159-128, offset: 0x88 */
77513   __IO uint32_t SPDIFTXCCHANNEL_ADDR_191_160;      /**< SPDIF transmit C channel register, bits 191-160, offset: 0x8C */
77514 } SPDIF_Type;
77515 
77516 /* ----------------------------------------------------------------------------
77517    -- SPDIF Register Masks
77518    ---------------------------------------------------------------------------- */
77519 
77520 /*!
77521  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
77522  * @{
77523  */
77524 
77525 /*! @name SCR - SPDIF Configuration Register */
77526 /*! @{ */
77527 
77528 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
77529 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
77530 /*! USrc_Sel - USrc_Sel
77531  *  0b00..No embedded U channel
77532  *  0b01..U channel from SPDIF receive block (CD mode)
77533  *  0b10..Reserved
77534  *  0b11..U channel from on chip transmitter
77535  */
77536 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
77537 
77538 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
77539 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
77540 /*! TxSel - TxSel
77541  *  0b000..Off and output 0
77542  *  0b001..Feed-through SPDIF_IN
77543  *  0b010-0b100..Reserved
77544  *  0b101..Tx Normal operation - From SPDIF Tx Block
77545  *  0b110, 0b111..Reserved
77546  */
77547 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
77548 
77549 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
77550 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
77551 /*! ValCtrl - ValCtrl
77552  *  0b0..Outgoing Validity always set
77553  *  0b1..Outgoing Validity always clear
77554  */
77555 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
77556 
77557 #define SPDIF_SCR_INPUTSRCSEL_MASK               (0xC0U)
77558 #define SPDIF_SCR_INPUTSRCSEL_SHIFT              (6U)
77559 /*! InputSrcSel - InputSrcSel
77560  *  0b00..SPDIF_IN
77561  *  0b01-0b11..None
77562  */
77563 #define SPDIF_SCR_INPUTSRCSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
77564 
77565 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
77566 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
77567 /*! DMA_TX_En - DMA_TX_En */
77568 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
77569 
77570 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
77571 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
77572 /*! DMA_Rx_En - DMA_Rx_En */
77573 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
77574 
77575 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
77576 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
77577 /*! TxFIFO_Ctrl - TxFIFO_Ctrl
77578  *  0b00..Send out digital zero on SPDIF Tx
77579  *  0b01..Tx Normal operation
77580  *  0b10..Reset to 1 sample remaining
77581  *  0b11..Reserved
77582  */
77583 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
77584 
77585 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
77586 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
77587 /*! soft_reset - soft_reset */
77588 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
77589 
77590 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
77591 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
77592 /*! LOW_POWER - LOW_POWER */
77593 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
77594 
77595 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
77596 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
77597 /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
77598  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
77599  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
77600  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
77601  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
77602  */
77603 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
77604 
77605 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
77606 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
77607 /*! TxAutoSync - TxAutoSync
77608  *  0b0..Tx FIFO auto sync off
77609  *  0b1..Tx FIFO auto sync on
77610  */
77611 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
77612 
77613 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
77614 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
77615 /*! RxAutoSync - RxAutoSync
77616  *  0b0..Rx FIFO auto sync off
77617  *  0b1..RxFIFO auto sync on
77618  */
77619 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
77620 
77621 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
77622 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
77623 /*! RxFIFOFull_Sel - RxFIFOFull_Sel
77624  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
77625  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
77626  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
77627  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
77628  */
77629 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
77630 
77631 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
77632 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
77633 /*! RxFIFO_Rst - RxFIFO_Rst
77634  *  0b0..Normal operation
77635  *  0b1..Reset register to 1 sample remaining
77636  */
77637 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
77638 
77639 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
77640 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
77641 /*! RxFIFO_Off_On - RxFIFO_Off_On
77642  *  0b0..SPDIF Rx FIFO is on
77643  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
77644  */
77645 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
77646 
77647 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
77648 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
77649 /*! RxFIFO_Ctrl - RxFIFO_Ctrl
77650  *  0b0..Normal operation
77651  *  0b1..Always read zero from Rx data register
77652  */
77653 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
77654 
77655 #define SPDIF_SCR_TXCCHANNEL_192B_EN_MASK        (0x1000000U)
77656 #define SPDIF_SCR_TXCCHANNEL_192B_EN_SHIFT       (24U)
77657 /*! TXCChannel_192b_en - TXCChannel_192b_en
77658  *  0b0..SPDIF transmits 48 bits of C in audio stream. Other C bits in 49 to 192 frames are 0
77659  *  0b1..SPDIF transmits 192 bits of C in audio stream
77660  */
77661 #define SPDIF_SCR_TXCCHANNEL_192B_EN(x)          (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXCCHANNEL_192B_EN_SHIFT)) & SPDIF_SCR_TXCCHANNEL_192B_EN_MASK)
77662 
77663 #define SPDIF_SCR_RXCCHANNEL_192B_EN_MASK        (0x2000000U)
77664 #define SPDIF_SCR_RXCCHANNEL_192B_EN_SHIFT       (25U)
77665 /*! RXCChannel_192b_en - RXCChannel_192b_en
77666  *  0b0..SPDIF receives only 48 bits of 192 C bits from input audio stream
77667  *  0b1..SPDIF receives 192 bits of C in audio stream
77668  */
77669 #define SPDIF_SCR_RXCCHANNEL_192B_EN(x)          (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXCCHANNEL_192B_EN_SHIFT)) & SPDIF_SCR_RXCCHANNEL_192B_EN_MASK)
77670 /*! @} */
77671 
77672 /*! @name SRCD - CDText Control Register */
77673 /*! @{ */
77674 
77675 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
77676 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
77677 /*! USyncMode - USyncMode
77678  *  0b0..Non-CD data
77679  *  0b1..CD user channel subcode
77680  */
77681 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
77682 /*! @} */
77683 
77684 /*! @name SRPC - PhaseConfig Register */
77685 /*! @{ */
77686 
77687 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
77688 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
77689 /*! GainSel - GainSel
77690  *  0b000..24*(2**10)
77691  *  0b001..16*(2**10)
77692  *  0b010..12*(2**10)
77693  *  0b011..8*(2**10)
77694  *  0b100..6*(2**10)
77695  *  0b101..4*(2**10)
77696  *  0b110..3*(2**10)
77697  *  0b111..Reserved
77698  */
77699 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
77700 
77701 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
77702 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
77703 /*! LOCK - LOCK */
77704 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
77705 
77706 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
77707 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
77708 /*! ClkSrc_Sel - ClkSrc_Sel
77709  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
77710  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
77711  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
77712  *  0b0101..REF_CLK_32K (XTALOSC)
77713  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
77714  *  0b1000..SPDIF_EXT_CLK
77715  */
77716 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
77717 /*! @} */
77718 
77719 /*! @name SIE - InterruptEn Register */
77720 /*! @{ */
77721 
77722 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
77723 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
77724 /*! RxFIFOFul - RxFIFOFul */
77725 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
77726 
77727 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
77728 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
77729 /*! TxEm - TxEm */
77730 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
77731 
77732 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
77733 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
77734 /*! LockLoss - LockLoss */
77735 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
77736 
77737 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
77738 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
77739 /*! RxFIFOResyn - RxFIFOResyn */
77740 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
77741 
77742 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
77743 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
77744 /*! RxFIFOUnOv - RxFIFOUnOv */
77745 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
77746 
77747 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
77748 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
77749 /*! UQErr - UQErr */
77750 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
77751 
77752 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
77753 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
77754 /*! UQSync - UQSync */
77755 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
77756 
77757 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
77758 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
77759 /*! QRxOv - QRxOv */
77760 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
77761 
77762 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
77763 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
77764 /*! QRxFul - QRxFul */
77765 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
77766 
77767 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
77768 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
77769 /*! URxOv - URxOv */
77770 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
77771 
77772 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
77773 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
77774 /*! URxFul - URxFul */
77775 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
77776 
77777 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
77778 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
77779 /*! BitErr - BitErr */
77780 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
77781 
77782 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
77783 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
77784 /*! SymErr - SymErr */
77785 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
77786 
77787 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
77788 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
77789 /*! ValNoGood - ValNoGood */
77790 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
77791 
77792 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
77793 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
77794 /*! CNew - CNew */
77795 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
77796 
77797 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
77798 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
77799 /*! TxResyn - TxResyn */
77800 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
77801 
77802 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
77803 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
77804 /*! TxUnOv - TxUnOv */
77805 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
77806 
77807 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
77808 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
77809 /*! Lock - Lock */
77810 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
77811 /*! @} */
77812 
77813 /*! @name SIS - InterruptStat Register */
77814 /*! @{ */
77815 
77816 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
77817 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
77818 /*! RxFIFOFul - RxFIFOFul */
77819 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
77820 
77821 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
77822 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
77823 /*! TxEm - TxEm */
77824 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
77825 
77826 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
77827 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
77828 /*! LockLoss - LockLoss */
77829 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
77830 
77831 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
77832 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
77833 /*! RxFIFOResyn - RxFIFOResyn */
77834 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
77835 
77836 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
77837 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
77838 /*! RxFIFOUnOv - RxFIFOUnOv */
77839 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
77840 
77841 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
77842 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
77843 /*! UQErr - UQErr */
77844 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
77845 
77846 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
77847 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
77848 /*! UQSync - UQSync */
77849 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
77850 
77851 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
77852 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
77853 /*! QRxOv - QRxOv */
77854 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
77855 
77856 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
77857 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
77858 /*! QRxFul - QRxFul */
77859 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
77860 
77861 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
77862 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
77863 /*! URxOv - URxOv */
77864 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
77865 
77866 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
77867 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
77868 /*! URxFul - URxFul */
77869 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
77870 
77871 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
77872 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
77873 /*! BitErr - BitErr */
77874 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
77875 
77876 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
77877 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
77878 /*! SymErr - SymErr */
77879 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
77880 
77881 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
77882 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
77883 /*! ValNoGood - ValNoGood */
77884 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
77885 
77886 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
77887 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
77888 /*! CNew - CNew */
77889 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
77890 
77891 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
77892 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
77893 /*! TxResyn - TxResyn */
77894 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
77895 
77896 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
77897 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
77898 /*! TxUnOv - TxUnOv */
77899 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
77900 
77901 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
77902 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
77903 /*! Lock - Lock */
77904 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
77905 /*! @} */
77906 
77907 /*! @name SRL - SPDIFRxLeft Register */
77908 /*! @{ */
77909 
77910 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
77911 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
77912 /*! RxDataLeft - RxDataLeft */
77913 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
77914 /*! @} */
77915 
77916 /*! @name SRR - SPDIFRxRight Register */
77917 /*! @{ */
77918 
77919 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
77920 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
77921 /*! RxDataRight - RxDataRight */
77922 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
77923 /*! @} */
77924 
77925 /*! @name SRCSH - SPDIFRxCChannel_h Register */
77926 /*! @{ */
77927 
77928 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
77929 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
77930 /*! RxCChannel_h - RxCChannel_h */
77931 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
77932 /*! @} */
77933 
77934 /*! @name SRCSL - SPDIFRxCChannel_l Register */
77935 /*! @{ */
77936 
77937 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
77938 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
77939 /*! RxCChannel_l - RxCChannel_l */
77940 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
77941 /*! @} */
77942 
77943 /*! @name SRU - UchannelRx Register */
77944 /*! @{ */
77945 
77946 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
77947 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
77948 /*! RxUChannel - RxUChannel */
77949 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
77950 /*! @} */
77951 
77952 /*! @name SRQ - QchannelRx Register */
77953 /*! @{ */
77954 
77955 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
77956 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
77957 /*! RxQChannel - RxQChannel */
77958 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
77959 /*! @} */
77960 
77961 /*! @name STL - SPDIFTxLeft Register */
77962 /*! @{ */
77963 
77964 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
77965 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
77966 /*! TxDataLeft - TxDataLeft */
77967 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
77968 /*! @} */
77969 
77970 /*! @name STR - SPDIFTxRight Register */
77971 /*! @{ */
77972 
77973 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
77974 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
77975 /*! TxDataRight - TxDataRight */
77976 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
77977 /*! @} */
77978 
77979 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
77980 /*! @{ */
77981 
77982 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
77983 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
77984 /*! TxCChannelCons_h - TxCChannelCons_h */
77985 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
77986 /*! @} */
77987 
77988 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
77989 /*! @{ */
77990 
77991 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
77992 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
77993 /*! TxCChannelCons_l - TxCChannelCons_l */
77994 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
77995 /*! @} */
77996 
77997 /*! @name SRFM - FreqMeas Register */
77998 /*! @{ */
77999 
78000 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
78001 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
78002 /*! FreqMeas - FreqMeas */
78003 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
78004 /*! @} */
78005 
78006 /*! @name STC - SPDIFTxClk Register */
78007 /*! @{ */
78008 
78009 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
78010 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
78011 /*! TxClk_DF - TxClk_DF
78012  *  0b0000000..divider factor is 1
78013  *  0b0000001..divider factor is 2
78014  *  0b1111111..divider factor is 128
78015  */
78016 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
78017 
78018 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
78019 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
78020 /*! tx_all_clk_en - tx_all_clk_en
78021  *  0b0..disable transfer clock.
78022  *  0b1..enable transfer clock.
78023  */
78024 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
78025 
78026 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
78027 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
78028 /*! TxClk_Source - TxClk_Source */
78029 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
78030 
78031 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
78032 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
78033 /*! SYSCLK_DF - SYSCLK_DF
78034  *  0b000000000..no clock signal
78035  *  0b000000001..divider factor is 2
78036  *  0b111111111..divider factor is 512
78037  */
78038 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
78039 /*! @} */
78040 
78041 /*! @name SPDIFRXCCHANNEL_ADDR_31_0 - SPDIF receive C channel register, bits 31-0 */
78042 /*! @{ */
78043 
78044 #define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_MASK (0xFFFFFFFFU)
78045 #define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_SHIFT (0U)
78046 /*! RxCChannel_Addr_31_0 - RxCChannel_Addr_31_0 */
78047 #define SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_31_0_RXCCHANNEL_ADDR_31_0_MASK)
78048 /*! @} */
78049 
78050 /*! @name SPDIFRXCCHANNEL_ADDR_63_32 - SPDIF receive C channel register, bits 63-32 */
78051 /*! @{ */
78052 
78053 #define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_MASK (0xFFFFFFFFU)
78054 #define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_SHIFT (0U)
78055 /*! RxCChannel_Addr_63_32 - RxCChannel_Addr_63_32 */
78056 #define SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_63_32_RXCCHANNEL_ADDR_63_32_MASK)
78057 /*! @} */
78058 
78059 /*! @name SPDIFRXCCHANNEL_ADDR_95_64 - SPDIF receive C channel register, bits 95-64 */
78060 /*! @{ */
78061 
78062 #define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_MASK (0xFFFFFFFFU)
78063 #define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_SHIFT (0U)
78064 /*! RxCChannel_Addr_95_64 - RxCChannel_Addr_95_64 */
78065 #define SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_95_64_RXCCHANNEL_ADDR_95_64_MASK)
78066 /*! @} */
78067 
78068 /*! @name SPDIFRXCCHANNEL_ADDR_127_96 - SPDIF receive C channel register, bits 127-96 */
78069 /*! @{ */
78070 
78071 #define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_MASK (0xFFFFFFFFU)
78072 #define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_SHIFT (0U)
78073 /*! RxCChannel_Addr_127_96 - RxCChannel_Addr_127_96 */
78074 #define SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_127_96_RXCCHANNEL_ADDR_127_96_MASK)
78075 /*! @} */
78076 
78077 /*! @name SPDIFRXCCHANNEL_ADDR_159_128 - SPDIF receive C channel register, bits 159-128 */
78078 /*! @{ */
78079 
78080 #define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_MASK (0xFFFFFFFFU)
78081 #define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_SHIFT (0U)
78082 /*! RxCChannel_Addr_159_128 - RxCChannel_Addr_159_128 */
78083 #define SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_159_128_RXCCHANNEL_ADDR_159_128_MASK)
78084 /*! @} */
78085 
78086 /*! @name SPDIFRXCCHANNEL_ADDR_191_160 - SPDIF receive C channel register, bits 191-160 */
78087 /*! @{ */
78088 
78089 #define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_MASK (0xFFFFFFFFU)
78090 #define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_SHIFT (0U)
78091 /*! RxCChannel_Addr_191_160 - RxCChannel_Addr_191_160 */
78092 #define SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_SHIFT)) & SPDIF_SPDIFRXCCHANNEL_ADDR_191_160_RXCCHANNEL_ADDR_191_160_MASK)
78093 /*! @} */
78094 
78095 /*! @name SPDIFTXCCHANNEL_ADDR_31_0 - SPDIF transmit C channel register, bits 31-0 */
78096 /*! @{ */
78097 
78098 #define SPDIF_SPDIFTXCCHANNEL_ADDR_31_0_TXCCHANNEL_ADDR_31_0_MASK (0xFFFFFFFFU)
78099 #define SPDIF_SPDIFTXCCHANNEL_ADDR_31_0_TXCCHANNEL_ADDR_31_0_SHIFT (0U)
78100 /*! TxCChannel_Addr_31_0 - TxCChannel_Addr_31_0 */
78101 #define SPDIF_SPDIFTXCCHANNEL_ADDR_31_0_TXCCHANNEL_ADDR_31_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_31_0_TXCCHANNEL_ADDR_31_0_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_31_0_TXCCHANNEL_ADDR_31_0_MASK)
78102 /*! @} */
78103 
78104 /*! @name SPDIFTXCCHANNEL_ADDR_63_32 - SPDIF transmit C channel register, bits 63-32 */
78105 /*! @{ */
78106 
78107 #define SPDIF_SPDIFTXCCHANNEL_ADDR_63_32_TXCCHANNEL_ADDR_63_32_MASK (0xFFFFFFFFU)
78108 #define SPDIF_SPDIFTXCCHANNEL_ADDR_63_32_TXCCHANNEL_ADDR_63_32_SHIFT (0U)
78109 /*! TxCChannel_Addr_63_32 - TxCChannel_Addr_63_32 */
78110 #define SPDIF_SPDIFTXCCHANNEL_ADDR_63_32_TXCCHANNEL_ADDR_63_32(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_63_32_TXCCHANNEL_ADDR_63_32_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_63_32_TXCCHANNEL_ADDR_63_32_MASK)
78111 /*! @} */
78112 
78113 /*! @name SPDIFTXCCHANNEL_ADDR_95_64 - SPDIF transmit C channel register, bits 95-64 */
78114 /*! @{ */
78115 
78116 #define SPDIF_SPDIFTXCCHANNEL_ADDR_95_64_TXCCHANNEL_ADDR_95_64_MASK (0xFFFFFFFFU)
78117 #define SPDIF_SPDIFTXCCHANNEL_ADDR_95_64_TXCCHANNEL_ADDR_95_64_SHIFT (0U)
78118 /*! TxCChannel_Addr_95_64 - TxCChannel_Addr_95_64 */
78119 #define SPDIF_SPDIFTXCCHANNEL_ADDR_95_64_TXCCHANNEL_ADDR_95_64(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_95_64_TXCCHANNEL_ADDR_95_64_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_95_64_TXCCHANNEL_ADDR_95_64_MASK)
78120 /*! @} */
78121 
78122 /*! @name SPDIFTXCCHANNEL_ADDR_127_96 - SPDIF transmit C channel register, bits 127-96 */
78123 /*! @{ */
78124 
78125 #define SPDIF_SPDIFTXCCHANNEL_ADDR_127_96_TXCCHANNEL_ADDR_127_96_MASK (0xFFFFFFFFU)
78126 #define SPDIF_SPDIFTXCCHANNEL_ADDR_127_96_TXCCHANNEL_ADDR_127_96_SHIFT (0U)
78127 /*! TxCChannel_Addr_127_96 - TxCChannel_Addr_127_96 */
78128 #define SPDIF_SPDIFTXCCHANNEL_ADDR_127_96_TXCCHANNEL_ADDR_127_96(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_127_96_TXCCHANNEL_ADDR_127_96_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_127_96_TXCCHANNEL_ADDR_127_96_MASK)
78129 /*! @} */
78130 
78131 /*! @name SPDIFTXCCHANNEL_ADDR_159_128 - SPDIF transmit C channel register, bits 159-128 */
78132 /*! @{ */
78133 
78134 #define SPDIF_SPDIFTXCCHANNEL_ADDR_159_128_TXCCHANNEL_ADDR_159_128_MASK (0xFFFFFFFFU)
78135 #define SPDIF_SPDIFTXCCHANNEL_ADDR_159_128_TXCCHANNEL_ADDR_159_128_SHIFT (0U)
78136 /*! TxCChannel_Addr_159_128 - TxCChannel_Addr_159_128 */
78137 #define SPDIF_SPDIFTXCCHANNEL_ADDR_159_128_TXCCHANNEL_ADDR_159_128(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_159_128_TXCCHANNEL_ADDR_159_128_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_159_128_TXCCHANNEL_ADDR_159_128_MASK)
78138 /*! @} */
78139 
78140 /*! @name SPDIFTXCCHANNEL_ADDR_191_160 - SPDIF transmit C channel register, bits 191-160 */
78141 /*! @{ */
78142 
78143 #define SPDIF_SPDIFTXCCHANNEL_ADDR_191_160_TXCCHANNEL_ADDR_191_160_MASK (0xFFFFFFFFU)
78144 #define SPDIF_SPDIFTXCCHANNEL_ADDR_191_160_TXCCHANNEL_ADDR_191_160_SHIFT (0U)
78145 /*! TxCChannel_Addr_191_160 - TxCChannel_Addr_191_160 */
78146 #define SPDIF_SPDIFTXCCHANNEL_ADDR_191_160_TXCCHANNEL_ADDR_191_160(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SPDIFTXCCHANNEL_ADDR_191_160_TXCCHANNEL_ADDR_191_160_SHIFT)) & SPDIF_SPDIFTXCCHANNEL_ADDR_191_160_TXCCHANNEL_ADDR_191_160_MASK)
78147 /*! @} */
78148 
78149 
78150 /*!
78151  * @}
78152  */ /* end of group SPDIF_Register_Masks */
78153 
78154 
78155 /* SPDIF - Peripheral instance base addresses */
78156 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
78157   /** Peripheral SPDIF base address */
78158   #define SPDIF_BASE                               (0x52BA0000u)
78159   /** Peripheral SPDIF base address */
78160   #define SPDIF_BASE_NS                            (0x42BA0000u)
78161   /** Peripheral SPDIF base pointer */
78162   #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
78163   /** Peripheral SPDIF base pointer */
78164   #define SPDIF_NS                                 ((SPDIF_Type *)SPDIF_BASE_NS)
78165   /** Array initializer of SPDIF peripheral base addresses */
78166   #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
78167   /** Array initializer of SPDIF peripheral base pointers */
78168   #define SPDIF_BASE_PTRS                          { SPDIF }
78169   /** Array initializer of SPDIF peripheral base addresses */
78170   #define SPDIF_BASE_ADDRS_NS                      { SPDIF_BASE_NS }
78171   /** Array initializer of SPDIF peripheral base pointers */
78172   #define SPDIF_BASE_PTRS_NS                       { SPDIF_NS }
78173 #else
78174   /** Peripheral SPDIF base address */
78175   #define SPDIF_BASE                               (0x42BA0000u)
78176   /** Peripheral SPDIF base pointer */
78177   #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
78178   /** Array initializer of SPDIF peripheral base addresses */
78179   #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
78180   /** Array initializer of SPDIF peripheral base pointers */
78181   #define SPDIF_BASE_PTRS                          { SPDIF }
78182 #endif
78183 /** Interrupt vectors for the SPDIF peripheral type */
78184 #define SPDIF_IRQS                               { SPDIF_IRQn }
78185 
78186 /*!
78187  * @}
78188  */ /* end of group SPDIF_Peripheral_Access_Layer */
78189 
78190 
78191 /* ----------------------------------------------------------------------------
78192    -- SRC_GENERAL Peripheral Access Layer
78193    ---------------------------------------------------------------------------- */
78194 
78195 /*!
78196  * @addtogroup SRC_GENERAL_Peripheral_Access_Layer SRC_GENERAL Peripheral Access Layer
78197  * @{
78198  */
78199 
78200 /** SRC_GENERAL - Register Layout Typedef */
78201 typedef struct {
78202        uint8_t RESERVED_0[4];
78203   __IO uint32_t AUTHEN_CTRL;                       /**< Authentication Control, offset: 0x4 */
78204        uint8_t RESERVED_1[8];
78205   __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x10 */
78206   __IO uint32_t SRTMR;                             /**< SRC Reset Trigger Mode Register, offset: 0x14 */
78207   __IO uint32_t SRMASK;                            /**< SRC Reset Mask Register, offset: 0x18 */
78208        uint8_t RESERVED_2[36];
78209   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x40 */
78210   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0x44 */
78211        uint8_t RESERVED_3[4];
78212   __IO uint32_t SRSR_BBSM;                         /**< SRC Reset Status Register backup in BBSM domain, offset: 0x4C */
78213   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x50 */
78214   __IO uint32_t GPR[20];                           /**< SRC General Purpose Register, array offset: 0x54, array step: 0x4 */
78215 } SRC_GENERAL_Type;
78216 
78217 /* ----------------------------------------------------------------------------
78218    -- SRC_GENERAL Register Masks
78219    ---------------------------------------------------------------------------- */
78220 
78221 /*!
78222  * @addtogroup SRC_GENERAL_Register_Masks SRC_GENERAL Register Masks
78223  * @{
78224  */
78225 
78226 /*! @name AUTHEN_CTRL - Authentication Control */
78227 /*! @{ */
78228 
78229 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_CFG_MASK    (0x80U)
78230 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_CFG_SHIFT   (7U)
78231 /*! LOCK_CFG - Configuration lock
78232  *  0b0..General registers are not locked.
78233  *  0b1..LOCK_CFG and registers in the list are locked.
78234  */
78235 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_CFG(x)      (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_LOCK_CFG_MASK)
78236 
78237 #define SRC_GENERAL_AUTHEN_CTRL_TZ_USER_MASK     (0x100U)
78238 #define SRC_GENERAL_AUTHEN_CTRL_TZ_USER_SHIFT    (8U)
78239 /*! TZ_USER - Allow user mode write
78240  *  0b0..General registers can only be written in privilege mode.
78241  *  0b1..General registers can be written either in privilege mode or user mode.
78242  */
78243 #define SRC_GENERAL_AUTHEN_CTRL_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_TZ_USER_MASK)
78244 
78245 #define SRC_GENERAL_AUTHEN_CTRL_TZ_NS_MASK       (0x200U)
78246 #define SRC_GENERAL_AUTHEN_CTRL_TZ_NS_SHIFT      (9U)
78247 /*! TZ_NS - Allow non-secure mode access
78248  *  0b0..General registers can only be written in secure mode.
78249  *  0b1..General registers can be written either in secure mode or non-secure mode.
78250  */
78251 #define SRC_GENERAL_AUTHEN_CTRL_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_TZ_NS_MASK)
78252 
78253 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_TZ_MASK     (0x800U)
78254 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_TZ_SHIFT    (11U)
78255 /*! LOCK_TZ - Lock Trust Zone Non Secure(TZ_NS) and Trust Zone User(TZ_USER) bits
78256  *  0b0..TZ_NS and TZ_USER values can be changed.
78257  *  0b1..LOCK_TZ, TZ_NS and TZ_USER values cannot be changed.
78258  */
78259 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_LOCK_TZ_MASK)
78260 
78261 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_LIST_MASK   (0x8000U)
78262 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_LIST_SHIFT  (15U)
78263 /*! LOCK_LIST - White list lock
78264  *  0b0..WHITE_LIST value can be changed.
78265  *  0b1..LOCK_LIST and WHITE_LIST values cannot be changed.
78266  */
78267 #define SRC_GENERAL_AUTHEN_CTRL_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_LOCK_LIST_MASK)
78268 
78269 #define SRC_GENERAL_AUTHEN_CTRL_WHITE_LIST_MASK  (0xFFFF0000U)
78270 #define SRC_GENERAL_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U)
78271 /*! WHITE_LIST - Domain ID white list
78272  *  0b0000000000000001..Core with domain ID=0 can write General registers.
78273  *  0b0000000000000010..Core with domain ID=1 can write General registers.
78274  *  0b0000000000000100..Core with domain ID=2 can write General registers.
78275  *  0b0000000000001000..Core with domain ID=3 can write General registers.
78276  *  0b0000000000010000..Core with domain ID=4 can write General registers.
78277  *  0b0000000000100000..Core with domain ID=5 can write General registers.
78278  *  0b0000000001000000..Core with domain ID=6 can write General registers.
78279  *  0b0000000010000000..Core with domain ID=7 can write General registers.
78280  *  0b0000000100000000..Core with domain ID=8 can write General registers.
78281  *  0b0000001000000000..Core with domain ID=9 can write General registers.
78282  *  0b0000010000000000..Core with domain ID=10 can write General registers.
78283  *  0b0000100000000000..Core with domain ID=11 can write General registers.
78284  *  0b0001000000000000..Core with domain ID=12 can write General registers.
78285  *  0b0010000000000000..Core with domain ID=13 can write General registers.
78286  *  0b0100000000000000..Core with domain ID=14 can write General registers.
78287  *  0b1000000000000000..Core with domain ID=15 can write General registers.
78288  */
78289 #define SRC_GENERAL_AUTHEN_CTRL_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_GENERAL_AUTHEN_CTRL_WHITE_LIST_MASK)
78290 /*! @} */
78291 
78292 /*! @name SCR - SRC Control Register */
78293 /*! @{ */
78294 
78295 #define SRC_GENERAL_SCR_BT_RELEASE_M7_MASK       (0x1U)
78296 #define SRC_GENERAL_SCR_BT_RELEASE_M7_SHIFT      (0U)
78297 /*! BT_RELEASE_M7 - Boot release M7
78298  *  0b0..Holds M7 Core reset.
78299  *  0b1..Releases M7 Core reset and let it run. After this bit is set, it cannot be cleared by SW write.
78300  */
78301 #define SRC_GENERAL_SCR_BT_RELEASE_M7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SCR_BT_RELEASE_M7_SHIFT)) & SRC_GENERAL_SCR_BT_RELEASE_M7_MASK)
78302 /*! @} */
78303 
78304 /*! @name SRTMR - SRC Reset Trigger Mode Register */
78305 /*! @{ */
78306 
78307 #define SRC_GENERAL_SRTMR_WDOG1_TRIG_MODE_MASK   (0x1U)
78308 #define SRC_GENERAL_SRTMR_WDOG1_TRIG_MODE_SHIFT  (0U)
78309 /*! WDOG1_TRIG_MODE - Wdog1 reset trigger mode configuration, locked by LOCK_CFG field
78310  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78311  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78312  */
78313 #define SRC_GENERAL_SRTMR_WDOG1_TRIG_MODE(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_WDOG1_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_WDOG1_TRIG_MODE_MASK)
78314 
78315 #define SRC_GENERAL_SRTMR_WDOG2_TRIG_MODE_MASK   (0x2U)
78316 #define SRC_GENERAL_SRTMR_WDOG2_TRIG_MODE_SHIFT  (1U)
78317 /*! WDOG2_TRIG_MODE - Wdog2 reset trigger mode configuration, locked by LOCK_CFG field
78318  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78319  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78320  */
78321 #define SRC_GENERAL_SRTMR_WDOG2_TRIG_MODE(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_WDOG2_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_WDOG2_TRIG_MODE_MASK)
78322 
78323 #define SRC_GENERAL_SRTMR_WDOG3_TRIG_MODE_MASK   (0x4U)
78324 #define SRC_GENERAL_SRTMR_WDOG3_TRIG_MODE_SHIFT  (2U)
78325 /*! WDOG3_TRIG_MODE - Wdog3 reset trigger mode configuration, locked by LOCK_CFG field
78326  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78327  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78328  */
78329 #define SRC_GENERAL_SRTMR_WDOG3_TRIG_MODE(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_WDOG3_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_WDOG3_TRIG_MODE_MASK)
78330 
78331 #define SRC_GENERAL_SRTMR_WDOG4_TRIG_MODE_MASK   (0x8U)
78332 #define SRC_GENERAL_SRTMR_WDOG4_TRIG_MODE_SHIFT  (3U)
78333 /*! WDOG4_TRIG_MODE - Wdog4 reset trigger mode configuration, locked by LOCK_CFG field
78334  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78335  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78336  */
78337 #define SRC_GENERAL_SRTMR_WDOG4_TRIG_MODE(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_WDOG4_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_WDOG4_TRIG_MODE_MASK)
78338 
78339 #define SRC_GENERAL_SRTMR_WDOG5_TRIG_MODE_MASK   (0x10U)
78340 #define SRC_GENERAL_SRTMR_WDOG5_TRIG_MODE_SHIFT  (4U)
78341 /*! WDOG5_TRIG_MODE - Wdog5 reset trigger mode configuration, locked by LOCK_CFG field
78342  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78343  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78344  */
78345 #define SRC_GENERAL_SRTMR_WDOG5_TRIG_MODE(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_WDOG5_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_WDOG5_TRIG_MODE_MASK)
78346 
78347 #define SRC_GENERAL_SRTMR_TEMPSENSE_TRIG_MODE_MASK (0x20U)
78348 #define SRC_GENERAL_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT (5U)
78349 /*! TEMPSENSE_TRIG_MODE - TempSense reset trigger mode configuration, locked by LOCK_CFG field
78350  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78351  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78352  */
78353 #define SRC_GENERAL_SRTMR_TEMPSENSE_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_TEMPSENSE_TRIG_MODE_MASK)
78354 
78355 #define SRC_GENERAL_SRTMR_EDGELOCK_TRIG_MODE_MASK (0x40U)
78356 #define SRC_GENERAL_SRTMR_EDGELOCK_TRIG_MODE_SHIFT (6U)
78357 /*! EDGELOCK_TRIG_MODE - Edgelock reset trigger mode configuration, locked by LOCK_CFG field
78358  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78359  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78360  */
78361 #define SRC_GENERAL_SRTMR_EDGELOCK_TRIG_MODE(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_EDGELOCK_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_EDGELOCK_TRIG_MODE_MASK)
78362 
78363 #define SRC_GENERAL_SRTMR_JTAGSW_TRIG_MODE_MASK  (0x80U)
78364 #define SRC_GENERAL_SRTMR_JTAGSW_TRIG_MODE_SHIFT (7U)
78365 /*! JTAGSW_TRIG_MODE - Jtagsw reset trigger mode configuration, locked by LOCK_CFG field
78366  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78367  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78368  */
78369 #define SRC_GENERAL_SRTMR_JTAGSW_TRIG_MODE(x)    (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_JTAGSW_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_JTAGSW_TRIG_MODE_MASK)
78370 
78371 #define SRC_GENERAL_SRTMR_CM33_RESET_TRIG_MODE_MASK (0x100U)
78372 #define SRC_GENERAL_SRTMR_CM33_RESET_TRIG_MODE_SHIFT (8U)
78373 /*! CM33_RESET_TRIG_MODE - CM33 reset trigger mode configuration, locked by LOCK_CFG field.
78374  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78375  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78376  */
78377 #define SRC_GENERAL_SRTMR_CM33_RESET_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_CM33_RESET_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_CM33_RESET_TRIG_MODE_MASK)
78378 
78379 #define SRC_GENERAL_SRTMR_CM33_LOCKUP_TRIG_MODE_MASK (0x200U)
78380 #define SRC_GENERAL_SRTMR_CM33_LOCKUP_TRIG_MODE_SHIFT (9U)
78381 /*! CM33_LOCKUP_TRIG_MODE - CM33 lockup trigger mode configuration, locked by LOCK_CFG field.
78382  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78383  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78384  */
78385 #define SRC_GENERAL_SRTMR_CM33_LOCKUP_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_CM33_LOCKUP_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_CM33_LOCKUP_TRIG_MODE_MASK)
78386 
78387 #define SRC_GENERAL_SRTMR_CM7_RESET_TRIG_MODE_MASK (0x400U)
78388 #define SRC_GENERAL_SRTMR_CM7_RESET_TRIG_MODE_SHIFT (10U)
78389 /*! CM7_RESET_TRIG_MODE - CM7 reset trigger mode configuration, locked by LOCK_CFG field
78390  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78391  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78392  */
78393 #define SRC_GENERAL_SRTMR_CM7_RESET_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_CM7_RESET_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_CM7_RESET_TRIG_MODE_MASK)
78394 
78395 #define SRC_GENERAL_SRTMR_CM7_LOCKUP_TRIG_MODE_MASK (0x800U)
78396 #define SRC_GENERAL_SRTMR_CM7_LOCKUP_TRIG_MODE_SHIFT (11U)
78397 /*! CM7_LOCKUP_TRIG_MODE - CM7 lockup trigger mode configuration, locked by LOCK_CFG field
78398  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78399  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78400  */
78401 #define SRC_GENERAL_SRTMR_CM7_LOCKUP_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_CM7_LOCKUP_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_CM7_LOCKUP_TRIG_MODE_MASK)
78402 
78403 #define SRC_GENERAL_SRTMR_DCDC_OVVT_TRIG_MODE_MASK (0x1000U)
78404 #define SRC_GENERAL_SRTMR_DCDC_OVVT_TRIG_MODE_SHIFT (12U)
78405 /*! DCDC_OVVT_TRIG_MODE - DCDC over voltage trigger mode configuration, locked by LOCK_CFG field
78406  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78407  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78408  */
78409 #define SRC_GENERAL_SRTMR_DCDC_OVVT_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_DCDC_OVVT_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_DCDC_OVVT_TRIG_MODE_MASK)
78410 
78411 #define SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_MASK (0x2000U)
78412 #define SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_SHIFT (13U)
78413 /*! ECAT_RSTO_TRIG_MODE - ECAT reset output mode configuration, locked by LOCK_CFG field
78414  *  0b0..Level-sensitive: System stays in reset until the reset source deasserts.
78415  *  0b1..Edge-sensitive: System resets once, even if the reset source remains asserted.
78416  */
78417 #define SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_SHIFT)) & SRC_GENERAL_SRTMR_ECAT_RSTO_TRIG_MODE_MASK)
78418 /*! @} */
78419 
78420 /*! @name SRMASK - SRC Reset Mask Register */
78421 /*! @{ */
78422 
78423 #define SRC_GENERAL_SRMASK_WDOG1_MASK_MASK       (0x1U)
78424 #define SRC_GENERAL_SRMASK_WDOG1_MASK_SHIFT      (0U)
78425 /*! WDOG1_MASK - WDOG1 reset mask
78426  *  0b0..The reset source can work
78427  *  0b1..The reset source is masked, cannot work
78428  */
78429 #define SRC_GENERAL_SRMASK_WDOG1_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG1_MASK_SHIFT)) & SRC_GENERAL_SRMASK_WDOG1_MASK_MASK)
78430 
78431 #define SRC_GENERAL_SRMASK_WDOG2_MASK_MASK       (0x2U)
78432 #define SRC_GENERAL_SRMASK_WDOG2_MASK_SHIFT      (1U)
78433 /*! WDOG2_MASK - WDOG2 reset mask
78434  *  0b0..The reset source can work
78435  *  0b1..The reset source is masked, cannot work
78436  */
78437 #define SRC_GENERAL_SRMASK_WDOG2_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG2_MASK_SHIFT)) & SRC_GENERAL_SRMASK_WDOG2_MASK_MASK)
78438 
78439 #define SRC_GENERAL_SRMASK_WDOG3_MASK_MASK       (0x4U)
78440 #define SRC_GENERAL_SRMASK_WDOG3_MASK_SHIFT      (2U)
78441 /*! WDOG3_MASK - WDOG3 reset mask
78442  *  0b0..The reset source can work
78443  *  0b1..The reset source is masked, cannot work
78444  */
78445 #define SRC_GENERAL_SRMASK_WDOG3_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG3_MASK_SHIFT)) & SRC_GENERAL_SRMASK_WDOG3_MASK_MASK)
78446 
78447 #define SRC_GENERAL_SRMASK_WDOG4_MASK_MASK       (0x8U)
78448 #define SRC_GENERAL_SRMASK_WDOG4_MASK_SHIFT      (3U)
78449 /*! WDOG4_MASK - WDOG4 reset mask
78450  *  0b0..The reset source can work
78451  *  0b1..The reset source is masked, cannot work
78452  */
78453 #define SRC_GENERAL_SRMASK_WDOG4_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG4_MASK_SHIFT)) & SRC_GENERAL_SRMASK_WDOG4_MASK_MASK)
78454 
78455 #define SRC_GENERAL_SRMASK_WDOG5_MASK_MASK       (0x10U)
78456 #define SRC_GENERAL_SRMASK_WDOG5_MASK_SHIFT      (4U)
78457 /*! WDOG5_MASK - WDOG5 reset mask
78458  *  0b0..The reset source can work
78459  *  0b1..The reset source is masked, cannot work
78460  */
78461 #define SRC_GENERAL_SRMASK_WDOG5_MASK(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG5_MASK_SHIFT)) & SRC_GENERAL_SRMASK_WDOG5_MASK_MASK)
78462 
78463 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK_MASK   (0x20U)
78464 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK_SHIFT  (5U)
78465 /*! TEMPSENSE_MASK - TempSense reset mask
78466  *  0b0..The reset source can work
78467  *  0b1..The reset source is masked, cannot work
78468  */
78469 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_TEMPSENSE_MASK_SHIFT)) & SRC_GENERAL_SRMASK_TEMPSENSE_MASK_MASK)
78470 
78471 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK_MASK    (0x40U)
78472 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK_SHIFT   (6U)
78473 /*! EDGELOCK_MASK - Edgelock reset mask
78474  *  0b0..The reset source can work
78475  *  0b1..The reset source is masked, cannot work
78476  */
78477 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_EDGELOCK_MASK_SHIFT)) & SRC_GENERAL_SRMASK_EDGELOCK_MASK_MASK)
78478 
78479 #define SRC_GENERAL_SRMASK_JTAGSW_MASK_MASK      (0x80U)
78480 #define SRC_GENERAL_SRMASK_JTAGSW_MASK_SHIFT     (7U)
78481 /*! JTAGSW_MASK - JTAGSW reset mask
78482  *  0b0..The reset source can work
78483  *  0b1..The reset source is masked, cannot work
78484  */
78485 #define SRC_GENERAL_SRMASK_JTAGSW_MASK(x)        (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_JTAGSW_MASK_SHIFT)) & SRC_GENERAL_SRMASK_JTAGSW_MASK_MASK)
78486 
78487 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK_MASK  (0x100U)
78488 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK_SHIFT (8U)
78489 /*! CM33_RESET_MASK - CM33 reset mask
78490  *  0b0..The reset source can work
78491  *  0b1..The reset source is masked, cannot work
78492  */
78493 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK(x)    (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM33_RESET_MASK_SHIFT)) & SRC_GENERAL_SRMASK_CM33_RESET_MASK_MASK)
78494 
78495 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_MASK (0x200U)
78496 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_SHIFT (9U)
78497 /*! CM33_LOCKUP_MASK - CM33 lockup mask
78498  *  0b0..The reset source can work
78499  *  0b1..The reset source is masked, cannot work
78500  */
78501 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_SHIFT)) & SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_MASK)
78502 
78503 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK_MASK   (0x400U)
78504 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK_SHIFT  (10U)
78505 /*! CM7_RESET_MASK - CM7 reset mask
78506  *  0b0..The reset source can work
78507  *  0b1..The reset source is masked, cannot work
78508  */
78509 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM7_RESET_MASK_SHIFT)) & SRC_GENERAL_SRMASK_CM7_RESET_MASK_MASK)
78510 
78511 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_MASK  (0x800U)
78512 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_SHIFT (11U)
78513 /*! CM7_LOCKUP_MASK - CM7 lockup reset mask
78514  *  0b0..The reset source can work
78515  *  0b1..The reset source is masked, cannot work
78516  */
78517 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_SHIFT)) & SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_MASK)
78518 
78519 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_MASK   (0x1000U)
78520 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_SHIFT  (12U)
78521 /*! DCDC_OVVT_MASK - DCDC over voltage mask
78522  *  0b0..The reset source can work
78523  *  0b1..The reset source is masked, cannot work
78524  */
78525 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_SHIFT)) & SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_MASK)
78526 
78527 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_MASK   (0x2000U)
78528 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_SHIFT  (13U)
78529 /*! ECAT_RSTO_MASK - ECAT reset output mask
78530  *  0b0..The reset source can work
78531  *  0b1..The reset source is masked, cannot work
78532  */
78533 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_SHIFT)) & SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_MASK)
78534 
78535 #define SRC_GENERAL_SRMASK_WDOG1_MASK_LOCKED_MASK (0x10000U)
78536 #define SRC_GENERAL_SRMASK_WDOG1_MASK_LOCKED_SHIFT (16U)
78537 /*! WDOG1_MASK_LOCKED - Lock WDOG1_MASK
78538  *  0b0..This bit and WDOG1_MASK's value can be changed.
78539  *  0b1..This bit and WDOG1_MASK's value cannot be changed.
78540  */
78541 #define SRC_GENERAL_SRMASK_WDOG1_MASK_LOCKED(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG1_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_WDOG1_MASK_LOCKED_MASK)
78542 
78543 #define SRC_GENERAL_SRMASK_WDOG2_MASK_LOCKED_MASK (0x20000U)
78544 #define SRC_GENERAL_SRMASK_WDOG2_MASK_LOCKED_SHIFT (17U)
78545 /*! WDOG2_MASK_LOCKED - Lock WDOG2_MASK
78546  *  0b0..This bit and WDOG2_MASK's value can be changed.
78547  *  0b1..This bit and WDOG2_MASK's value cannot be changed.
78548  */
78549 #define SRC_GENERAL_SRMASK_WDOG2_MASK_LOCKED(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG2_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_WDOG2_MASK_LOCKED_MASK)
78550 
78551 #define SRC_GENERAL_SRMASK_WDOG3_MASK_LOCKED_MASK (0x40000U)
78552 #define SRC_GENERAL_SRMASK_WDOG3_MASK_LOCKED_SHIFT (18U)
78553 /*! WDOG3_MASK_LOCKED - Lock WDOG3_MASK
78554  *  0b0..This bit and WDOG3_MASK's value can be changed.
78555  *  0b1..This bit and WDOG3_MASK's value cannot be changed.
78556  */
78557 #define SRC_GENERAL_SRMASK_WDOG3_MASK_LOCKED(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG3_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_WDOG3_MASK_LOCKED_MASK)
78558 
78559 #define SRC_GENERAL_SRMASK_WDOG4_MASK_LOCKED_MASK (0x80000U)
78560 #define SRC_GENERAL_SRMASK_WDOG4_MASK_LOCKED_SHIFT (19U)
78561 /*! WDOG4_MASK_LOCKED - Lock WDOG4_MASK
78562  *  0b0..This bit and WDOG4_MASK's value can be changed.
78563  *  0b1..This bit and WDOG4_MASK's value cannot be changed.
78564  */
78565 #define SRC_GENERAL_SRMASK_WDOG4_MASK_LOCKED(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG4_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_WDOG4_MASK_LOCKED_MASK)
78566 
78567 #define SRC_GENERAL_SRMASK_WDOG5_MASK_LOCKED_MASK (0x100000U)
78568 #define SRC_GENERAL_SRMASK_WDOG5_MASK_LOCKED_SHIFT (20U)
78569 /*! WDOG5_MASK_LOCKED - Lock WDOG5_MASK
78570  *  0b0..This bit and WDOG5_MASK's value can be changed.
78571  *  0b1..This bit and WDOG5_MASK's value cannot be changed.
78572  */
78573 #define SRC_GENERAL_SRMASK_WDOG5_MASK_LOCKED(x)  (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_WDOG5_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_WDOG5_MASK_LOCKED_MASK)
78574 
78575 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK_LOCKED_MASK (0x200000U)
78576 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK_LOCKED_SHIFT (21U)
78577 /*! TEMPSENSE_MASK_LOCKED - Lock TEMPSENSE_MASK
78578  *  0b0..TEMPSENSE_MASK's value can be changed.
78579  *  0b1..This bit and TEMPSENSE_MASK's value cannot be changed.
78580  */
78581 #define SRC_GENERAL_SRMASK_TEMPSENSE_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_TEMPSENSE_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_TEMPSENSE_MASK_LOCKED_MASK)
78582 
78583 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK_LOCKED_MASK (0x400000U)
78584 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK_LOCKED_SHIFT (22U)
78585 /*! EDGELOCK_MASK_LOCKED - Lock EDGELOCK_MASK
78586  *  0b0..EDGELOCK_MASK's value can be changed.
78587  *  0b1..This bit and EDGELOCK_MASK's value cannot be changed.
78588  */
78589 #define SRC_GENERAL_SRMASK_EDGELOCK_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_EDGELOCK_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_EDGELOCK_MASK_LOCKED_MASK)
78590 
78591 #define SRC_GENERAL_SRMASK_JTAGSW_MASK_LOCKED_MASK (0x800000U)
78592 #define SRC_GENERAL_SRMASK_JTAGSW_MASK_LOCKED_SHIFT (23U)
78593 /*! JTAGSW_MASK_LOCKED - Lock JTAGSW_MASK
78594  *  0b0..JTAGSW_MASK's value can be changed.
78595  *  0b1..This bit and JTAGSW_MASK's value cannot be changed.
78596  */
78597 #define SRC_GENERAL_SRMASK_JTAGSW_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_JTAGSW_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_JTAGSW_MASK_LOCKED_MASK)
78598 
78599 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK_LOCKED_MASK (0x1000000U)
78600 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK_LOCKED_SHIFT (24U)
78601 /*! CM33_RESET_MASK_LOCKED - Lock CM33_RESET_MASK
78602  *  0b0..CM33_RESET_MASK's value can be changed.
78603  *  0b1..This bit and CM33_RESET_MASK's value cannot be changed.
78604  */
78605 #define SRC_GENERAL_SRMASK_CM33_RESET_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM33_RESET_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_CM33_RESET_MASK_LOCKED_MASK)
78606 
78607 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_LOCKED_MASK (0x2000000U)
78608 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_LOCKED_SHIFT (25U)
78609 /*! CM33_LOCKUP_MASK_LOCKED - Lock CM33_LOCKUP_MASK
78610  *  0b0..CM33_LOCKUP_MASK's value can be changed.
78611  *  0b1..This bit and CM33_LOCKUP_MASK's value cannot be changed.
78612  */
78613 #define SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_CM33_LOCKUP_MASK_LOCKED_MASK)
78614 
78615 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK_LOCKED_MASK (0x4000000U)
78616 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK_LOCKED_SHIFT (26U)
78617 /*! CM7_RESET_MASK_LOCKED - Lock CM7 reset mask bit
78618  *  0b0..CM7_RESET_MASK's value can be changed.
78619  *  0b1..This bit and CM7_RESET_MASK's value cannot be changed.
78620  */
78621 #define SRC_GENERAL_SRMASK_CM7_RESET_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM7_RESET_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_CM7_RESET_MASK_LOCKED_MASK)
78622 
78623 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_LOCKED_MASK (0x8000000U)
78624 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_LOCKED_SHIFT (27U)
78625 /*! CM7_LOCKUP_MASK_LOCKED - Lock CM7_LOCKUP_MASK
78626  *  0b0..CM7_LOCKUP_MASK's value can be changed.
78627  *  0b1..This bit and CM7_LOCKUP_MASK's value cannot be changed.
78628  */
78629 #define SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_CM7_LOCKUP_MASK_LOCKED_MASK)
78630 
78631 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_LOCKED_MASK (0x10000000U)
78632 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_LOCKED_SHIFT (28U)
78633 /*! DCDC_OVVT_MASK_LOCKED - Lock DCDC_OVVT_MASK
78634  *  0b0..DCDC_OVVT_MASK's value can be changed.
78635  *  0b1..This bit and DCDC_OVVT_MASK's value cannot be changed.
78636  */
78637 #define SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_DCDC_OVVT_MASK_LOCKED_MASK)
78638 
78639 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_LOCKED_MASK (0x20000000U)
78640 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_LOCKED_SHIFT (29U)
78641 /*! ECAT_RSTO_MASK_LOCKED - Lock ECAT_RSTO_MASK
78642  *  0b0..ECAT_RSTO_MASK's value can be changed.
78643  *  0b1..This bit and ECAT_RSTO_MASK's value cannot be changed.
78644  */
78645 #define SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_LOCKED_SHIFT)) & SRC_GENERAL_SRMASK_ECAT_RSTO_MASK_LOCKED_MASK)
78646 /*! @} */
78647 
78648 /*! @name SBMR1 - SRC Boot Mode Register 1 */
78649 /*! @{ */
78650 
78651 #define SRC_GENERAL_SBMR1_BOOT_CFG1_MASK         (0xFFU)
78652 #define SRC_GENERAL_SBMR1_BOOT_CFG1_SHIFT        (0U)
78653 /*! BOOT_CFG1 - Reserved. */
78654 #define SRC_GENERAL_SBMR1_BOOT_CFG1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SBMR1_BOOT_CFG1_SHIFT)) & SRC_GENERAL_SBMR1_BOOT_CFG1_MASK)
78655 
78656 #define SRC_GENERAL_SBMR1_BOOT_CFG2_MASK         (0xFF00U)
78657 #define SRC_GENERAL_SBMR1_BOOT_CFG2_SHIFT        (8U)
78658 /*! BOOT_CFG2 - Reserved. */
78659 #define SRC_GENERAL_SBMR1_BOOT_CFG2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SBMR1_BOOT_CFG2_SHIFT)) & SRC_GENERAL_SBMR1_BOOT_CFG2_MASK)
78660 
78661 #define SRC_GENERAL_SBMR1_BOOT_CFG3_MASK         (0xFF0000U)
78662 #define SRC_GENERAL_SBMR1_BOOT_CFG3_SHIFT        (16U)
78663 /*! BOOT_CFG3 - Reserved. */
78664 #define SRC_GENERAL_SBMR1_BOOT_CFG3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SBMR1_BOOT_CFG3_SHIFT)) & SRC_GENERAL_SBMR1_BOOT_CFG3_MASK)
78665 
78666 #define SRC_GENERAL_SBMR1_BOOT_CFG4_MASK         (0xFF000000U)
78667 #define SRC_GENERAL_SBMR1_BOOT_CFG4_SHIFT        (24U)
78668 /*! BOOT_CFG4 - Reserved. */
78669 #define SRC_GENERAL_SBMR1_BOOT_CFG4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SBMR1_BOOT_CFG4_SHIFT)) & SRC_GENERAL_SBMR1_BOOT_CFG4_MASK)
78670 /*! @} */
78671 
78672 /*! @name SBMR2 - SRC Boot Mode Register 2 */
78673 /*! @{ */
78674 
78675 #define SRC_GENERAL_SBMR2_IPP_BOOT_MODE_MASK     (0x3F000000U)
78676 #define SRC_GENERAL_SBMR2_IPP_BOOT_MODE_SHIFT    (24U)
78677 /*! IPP_BOOT_MODE
78678  *  0b000000..Boot from internal Fuses
78679  *  0b000001..Serial Downloader: USB1 or LPUART1
78680  *  0b000010..USDHC1 8-bit eMMC 5.1
78681  *  0b000011..USDHC2 4-bit SD 3.0
78682  *  0b000100..FlexSPI Serial NOR with SFDP (JESD-216) discoverable parameters
78683  *  0b000101..FlexSPI Serial NAND 2k page
78684  *  0b000110..FlexSPI Serial NAND 4k page
78685  *  0b000111..Test mode/Infinite loop mode
78686  */
78687 #define SRC_GENERAL_SBMR2_IPP_BOOT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_GENERAL_SBMR2_IPP_BOOT_MODE_MASK)
78688 /*! @} */
78689 
78690 /*! @name SRSR_BBSM - SRC Reset Status Register backup in BBSM domain */
78691 /*! @{ */
78692 
78693 #define SRC_GENERAL_SRSR_BBSM_POR_RST_MASK       (0x1U)
78694 #define SRC_GENERAL_SRSR_BBSM_POR_RST_SHIFT      (0U)
78695 /*! POR_RST - Indicates whether the reset was the result of power up or chip PAD POR_B.
78696  *  0b0..Reset is not a result of power up or chip PAD POR_B.
78697  *  0b1..Reset is a result of power up or chip PAD POR_B.
78698  */
78699 #define SRC_GENERAL_SRSR_BBSM_POR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_POR_RST_SHIFT)) & SRC_GENERAL_SRSR_BBSM_POR_RST_MASK)
78700 
78701 #define SRC_GENERAL_SRSR_BBSM_WDOG1_RST_B_MASK   (0x2U)
78702 #define SRC_GENERAL_SRSR_BBSM_WDOG1_RST_B_SHIFT  (1U)
78703 /*! WDOG1_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog1 time-out event.
78704  *  0b0..Reset is not a result of the watchdog time-out event.
78705  *  0b1..Reset is a result of the watchdog time-out event.
78706  */
78707 #define SRC_GENERAL_SRSR_BBSM_WDOG1_RST_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_WDOG1_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_WDOG1_RST_B_MASK)
78708 
78709 #define SRC_GENERAL_SRSR_BBSM_WDOG2_RST_B_MASK   (0x4U)
78710 #define SRC_GENERAL_SRSR_BBSM_WDOG2_RST_B_SHIFT  (2U)
78711 /*! WDOG2_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event.
78712  *  0b0..Reset is not a result of the watchdog time-out event.
78713  *  0b1..Reset is a result of the watchdog time-out event.
78714  */
78715 #define SRC_GENERAL_SRSR_BBSM_WDOG2_RST_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_WDOG2_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_WDOG2_RST_B_MASK)
78716 
78717 #define SRC_GENERAL_SRSR_BBSM_WDOG3_RST_B_MASK   (0x8U)
78718 #define SRC_GENERAL_SRSR_BBSM_WDOG3_RST_B_SHIFT  (3U)
78719 /*! WDOG3_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out
78720  *  0b0..Reset is not a result of the watchdog3 time-out event.
78721  *  0b1..Reset is a result of the watchdog3 time-out event.
78722  */
78723 #define SRC_GENERAL_SRSR_BBSM_WDOG3_RST_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_WDOG3_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_WDOG3_RST_B_MASK)
78724 
78725 #define SRC_GENERAL_SRSR_BBSM_WDOG4_RST_B_MASK   (0x10U)
78726 #define SRC_GENERAL_SRSR_BBSM_WDOG4_RST_B_SHIFT  (4U)
78727 /*! WDOG4_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog4 time-out
78728  *  0b0..Reset is not a result of the watchdog time-out event.
78729  *  0b1..Reset is a result of the watchdog time-out event.
78730  */
78731 #define SRC_GENERAL_SRSR_BBSM_WDOG4_RST_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_WDOG4_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_WDOG4_RST_B_MASK)
78732 
78733 #define SRC_GENERAL_SRSR_BBSM_WDOG5_RST_B_MASK   (0x20U)
78734 #define SRC_GENERAL_SRSR_BBSM_WDOG5_RST_B_SHIFT  (5U)
78735 /*! WDOG5_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog5 time-out
78736  *  0b0..Reset is not a result of the watchdog time-out event.
78737  *  0b1..Reset is a result of the watchdog time-out event.
78738  */
78739 #define SRC_GENERAL_SRSR_BBSM_WDOG5_RST_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_WDOG5_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_WDOG5_RST_B_MASK)
78740 
78741 #define SRC_GENERAL_SRSR_BBSM_TEMPSENSE_RST_B_MASK (0x40U)
78742 #define SRC_GENERAL_SRSR_BBSM_TEMPSENSE_RST_B_SHIFT (6U)
78743 /*! TEMPSENSE_RST_B - TempSensor software reset. Indicates whether the reset was the result of software reset from on-chip Temperature Sensor.
78744  *  0b0..Reset is not a result of software reset from Temperature Sensor.
78745  *  0b1..Reset is a result of software reset from Temperature Sensor.
78746  */
78747 #define SRC_GENERAL_SRSR_BBSM_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_TEMPSENSE_RST_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_TEMPSENSE_RST_B_MASK)
78748 
78749 #define SRC_GENERAL_SRSR_BBSM_EDGELOCK_RESET_B_MASK (0x80U)
78750 #define SRC_GENERAL_SRSR_BBSM_EDGELOCK_RESET_B_SHIFT (7U)
78751 /*! EDGELOCK_RESET_B - Indicates whether the reset was the result of the Edgelock's reset input.
78752  *  0b0..Reset is not a result of the Edgelock's reset event.
78753  *  0b1..Reset is a result of the Edgelock's reset event.
78754  */
78755 #define SRC_GENERAL_SRSR_BBSM_EDGELOCK_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_EDGELOCK_RESET_B_SHIFT)) & SRC_GENERAL_SRSR_BBSM_EDGELOCK_RESET_B_MASK)
78756 
78757 #define SRC_GENERAL_SRSR_BBSM_JTAG_SW_RST_MASK   (0x100U)
78758 #define SRC_GENERAL_SRSR_BBSM_JTAG_SW_RST_SHIFT  (8U)
78759 /*! JTAG_SW_RST - JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
78760  *  0b0..Reset is not a result of software reset from JTAG.
78761  *  0b1..Reset is a result of software reset from JTAG.
78762  */
78763 #define SRC_GENERAL_SRSR_BBSM_JTAG_SW_RST(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_JTAG_SW_RST_SHIFT)) & SRC_GENERAL_SRSR_BBSM_JTAG_SW_RST_MASK)
78764 
78765 #define SRC_GENERAL_SRSR_BBSM_CM33_REQUEST_MASK  (0x200U)
78766 #define SRC_GENERAL_SRSR_BBSM_CM33_REQUEST_SHIFT (9U)
78767 /*! CM33_REQUEST - Indicates whether reset was the result of cm33 reset request
78768  *  0b0..Reset is not a result of cm33 reset request.
78769  *  0b1..Reset is a result of cm33 reset request.
78770  */
78771 #define SRC_GENERAL_SRSR_BBSM_CM33_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_CM33_REQUEST_SHIFT)) & SRC_GENERAL_SRSR_BBSM_CM33_REQUEST_MASK)
78772 
78773 #define SRC_GENERAL_SRSR_BBSM_CM33_LOCKUP_MASK   (0x400U)
78774 #define SRC_GENERAL_SRSR_BBSM_CM33_LOCKUP_SHIFT  (10U)
78775 /*! CM33_LOCKUP - Indicates a reset has been caused by cm33 CPU lockup
78776  *  0b0..Reset is not a result of the cm33 lockup.
78777  *  0b1..Reset is a result of the cm33 lockup.
78778  */
78779 #define SRC_GENERAL_SRSR_BBSM_CM33_LOCKUP(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_CM33_LOCKUP_SHIFT)) & SRC_GENERAL_SRSR_BBSM_CM33_LOCKUP_MASK)
78780 
78781 #define SRC_GENERAL_SRSR_BBSM_CM7_REQUEST_MASK   (0x800U)
78782 #define SRC_GENERAL_SRSR_BBSM_CM7_REQUEST_SHIFT  (11U)
78783 /*! CM7_REQUEST - Indicates whether reset was the result of cm7 reset request
78784  *  0b0..Reset is not a result of cm7 reset request.
78785  *  0b1..Reset is a result of cm7 reset request.
78786  */
78787 #define SRC_GENERAL_SRSR_BBSM_CM7_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_CM7_REQUEST_SHIFT)) & SRC_GENERAL_SRSR_BBSM_CM7_REQUEST_MASK)
78788 
78789 #define SRC_GENERAL_SRSR_BBSM_CM7_LOCKUP_MASK    (0x1000U)
78790 #define SRC_GENERAL_SRSR_BBSM_CM7_LOCKUP_SHIFT   (12U)
78791 /*! CM7_LOCKUP - Indicates a reset has been caused by CM7 CPU
78792  *  0b0..Reset is not a result of the cm7 lockup.
78793  *  0b1..Reset is a result of the cm7 lockup.
78794  */
78795 #define SRC_GENERAL_SRSR_BBSM_CM7_LOCKUP(x)      (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_CM7_LOCKUP_SHIFT)) & SRC_GENERAL_SRSR_BBSM_CM7_LOCKUP_MASK)
78796 
78797 #define SRC_GENERAL_SRSR_BBSM_DCDC_OVVT_MASK     (0x2000U)
78798 #define SRC_GENERAL_SRSR_BBSM_DCDC_OVVT_SHIFT    (13U)
78799 /*! DCDC_OVVT - Indicates a reset has been caused by DCDC over voltage
78800  *  0b0..Reset is not a result of the DCDC over voltage.
78801  *  0b1..Reset is a result of the DCDC over voltage.
78802  */
78803 #define SRC_GENERAL_SRSR_BBSM_DCDC_OVVT(x)       (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_DCDC_OVVT_SHIFT)) & SRC_GENERAL_SRSR_BBSM_DCDC_OVVT_MASK)
78804 
78805 #define SRC_GENERAL_SRSR_BBSM_ECAT_RSTO_MASK     (0x4000U)
78806 #define SRC_GENERAL_SRSR_BBSM_ECAT_RSTO_SHIFT    (14U)
78807 /*! ECAT_RSTO - Indicates a reset has been caused by ECAT reset output
78808  *  0b0..Reset is not a result of the ECAT reset output.
78809  *  0b1..Reset is a result of the ECAT reset output.
78810  */
78811 #define SRC_GENERAL_SRSR_BBSM_ECAT_RSTO(x)       (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_BBSM_ECAT_RSTO_SHIFT)) & SRC_GENERAL_SRSR_BBSM_ECAT_RSTO_MASK)
78812 /*! @} */
78813 
78814 /*! @name SRSR - SRC Reset Status Register */
78815 /*! @{ */
78816 
78817 #define SRC_GENERAL_SRSR_POR_RST_MASK            (0x1U)
78818 #define SRC_GENERAL_SRSR_POR_RST_SHIFT           (0U)
78819 /*! POR_RST - Indicates whether the reset was the result of POR.
78820  *  0b0..Reset is not a result of POR.
78821  *  0b1..Reset is a result of POR.
78822  */
78823 #define SRC_GENERAL_SRSR_POR_RST(x)              (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_POR_RST_SHIFT)) & SRC_GENERAL_SRSR_POR_RST_MASK)
78824 
78825 #define SRC_GENERAL_SRSR_WDOG1_RST_B_MASK        (0x2U)
78826 #define SRC_GENERAL_SRSR_WDOG1_RST_B_SHIFT       (1U)
78827 /*! WDOG1_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog1 time-out event.
78828  *  0b0..Reset is not a result of the watchdog time-out event.
78829  *  0b1..Reset is a result of the watchdog time-out event.
78830  */
78831 #define SRC_GENERAL_SRSR_WDOG1_RST_B(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_WDOG1_RST_B_SHIFT)) & SRC_GENERAL_SRSR_WDOG1_RST_B_MASK)
78832 
78833 #define SRC_GENERAL_SRSR_WDOG2_RST_B_MASK        (0x4U)
78834 #define SRC_GENERAL_SRSR_WDOG2_RST_B_SHIFT       (2U)
78835 /*! WDOG2_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event.
78836  *  0b0..Reset is not a result of the watchdog time-out event.
78837  *  0b1..Reset is a result of the watchdog time-out event.
78838  */
78839 #define SRC_GENERAL_SRSR_WDOG2_RST_B(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_WDOG2_RST_B_SHIFT)) & SRC_GENERAL_SRSR_WDOG2_RST_B_MASK)
78840 
78841 #define SRC_GENERAL_SRSR_WDOG3_RST_B_MASK        (0x8U)
78842 #define SRC_GENERAL_SRSR_WDOG3_RST_B_SHIFT       (3U)
78843 /*! WDOG3_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out
78844  *  0b0..Reset is not a result of the watchdog3 time-out event.
78845  *  0b1..Reset is a result of the watchdog3 time-out event.
78846  */
78847 #define SRC_GENERAL_SRSR_WDOG3_RST_B(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_WDOG3_RST_B_SHIFT)) & SRC_GENERAL_SRSR_WDOG3_RST_B_MASK)
78848 
78849 #define SRC_GENERAL_SRSR_WDOG4_RST_B_MASK        (0x10U)
78850 #define SRC_GENERAL_SRSR_WDOG4_RST_B_SHIFT       (4U)
78851 /*! WDOG4_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog4 time-out
78852  *  0b0..Reset is not a result of the watchdog time-out event.
78853  *  0b1..Reset is a result of the watchdog time-out event.
78854  */
78855 #define SRC_GENERAL_SRSR_WDOG4_RST_B(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_WDOG4_RST_B_SHIFT)) & SRC_GENERAL_SRSR_WDOG4_RST_B_MASK)
78856 
78857 #define SRC_GENERAL_SRSR_WDOG5_RST_B_MASK        (0x20U)
78858 #define SRC_GENERAL_SRSR_WDOG5_RST_B_SHIFT       (5U)
78859 /*! WDOG5_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog5 time-out
78860  *  0b0..Reset is not a result of the watchdog time-out event.
78861  *  0b1..Reset is a result of the watchdog time-out event.
78862  */
78863 #define SRC_GENERAL_SRSR_WDOG5_RST_B(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_WDOG5_RST_B_SHIFT)) & SRC_GENERAL_SRSR_WDOG5_RST_B_MASK)
78864 
78865 #define SRC_GENERAL_SRSR_TEMPSENSE_RST_B_MASK    (0x40U)
78866 #define SRC_GENERAL_SRSR_TEMPSENSE_RST_B_SHIFT   (6U)
78867 /*! TEMPSENSE_RST_B - Temper Sensor software reset. Indicates whether the reset was the result of
78868  *    software reset from on-chip Temperature Sensor.
78869  *  0b0..Reset is not a result of software reset from Temperature Sensor.
78870  *  0b1..Reset is a result of software reset from Temperature Sensor.
78871  */
78872 #define SRC_GENERAL_SRSR_TEMPSENSE_RST_B(x)      (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_GENERAL_SRSR_TEMPSENSE_RST_B_MASK)
78873 
78874 #define SRC_GENERAL_SRSR_EDGELOCK_RESET_B_MASK   (0x80U)
78875 #define SRC_GENERAL_SRSR_EDGELOCK_RESET_B_SHIFT  (7U)
78876 /*! EDGELOCK_RESET_B - Indicates whether the reset was the result of the Edgelock's reset input.
78877  *  0b0..Reset is not a result of the Edgelock's reset event.
78878  *  0b1..Reset is a result of the Edgelock's reset event.
78879  */
78880 #define SRC_GENERAL_SRSR_EDGELOCK_RESET_B(x)     (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_EDGELOCK_RESET_B_SHIFT)) & SRC_GENERAL_SRSR_EDGELOCK_RESET_B_MASK)
78881 
78882 #define SRC_GENERAL_SRSR_JTAG_SW_RST_MASK        (0x100U)
78883 #define SRC_GENERAL_SRSR_JTAG_SW_RST_SHIFT       (8U)
78884 /*! JTAG_SW_RST - JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
78885  *  0b0..Reset is not a result of software reset from JTAG.
78886  *  0b1..Reset is a result of software reset from JTAG.
78887  */
78888 #define SRC_GENERAL_SRSR_JTAG_SW_RST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_JTAG_SW_RST_SHIFT)) & SRC_GENERAL_SRSR_JTAG_SW_RST_MASK)
78889 
78890 #define SRC_GENERAL_SRSR_CM33_REQUEST_MASK       (0x200U)
78891 #define SRC_GENERAL_SRSR_CM33_REQUEST_SHIFT      (9U)
78892 /*! CM33_REQUEST - Indicates whether reset was the result of cm33 reset request
78893  *  0b0..Reset is not a result of cm33 reset request.
78894  *  0b1..Reset is a result of cm33 reset request.
78895  */
78896 #define SRC_GENERAL_SRSR_CM33_REQUEST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_CM33_REQUEST_SHIFT)) & SRC_GENERAL_SRSR_CM33_REQUEST_MASK)
78897 
78898 #define SRC_GENERAL_SRSR_CM33_LOCKUP_MASK        (0x400U)
78899 #define SRC_GENERAL_SRSR_CM33_LOCKUP_SHIFT       (10U)
78900 /*! CM33_LOCKUP - Indicates a reset has been caused by cm33 CPU lockup
78901  *  0b0..Reset is not a result of the cm33 lockup.
78902  *  0b1..Reset is a result of the cm33 lockup.
78903  */
78904 #define SRC_GENERAL_SRSR_CM33_LOCKUP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_CM33_LOCKUP_SHIFT)) & SRC_GENERAL_SRSR_CM33_LOCKUP_MASK)
78905 
78906 #define SRC_GENERAL_SRSR_CM7_REQUEST_MASK        (0x800U)
78907 #define SRC_GENERAL_SRSR_CM7_REQUEST_SHIFT       (11U)
78908 /*! CM7_REQUEST - Indicates whether reset was the result of cm7 reset request
78909  *  0b0..Reset is not a result of cm7 reset request.
78910  *  0b1..Reset is a result of cm7 reset request.
78911  */
78912 #define SRC_GENERAL_SRSR_CM7_REQUEST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_CM7_REQUEST_SHIFT)) & SRC_GENERAL_SRSR_CM7_REQUEST_MASK)
78913 
78914 #define SRC_GENERAL_SRSR_CM7_LOCKUP_MASK         (0x1000U)
78915 #define SRC_GENERAL_SRSR_CM7_LOCKUP_SHIFT        (12U)
78916 /*! CM7_LOCKUP - Indicates a reset has been caused by CM7 CPU
78917  *  0b0..Reset is not a result of the cm7 lockup.
78918  *  0b1..Reset is a result of the cm7 lockup.
78919  */
78920 #define SRC_GENERAL_SRSR_CM7_LOCKUP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_CM7_LOCKUP_SHIFT)) & SRC_GENERAL_SRSR_CM7_LOCKUP_MASK)
78921 
78922 #define SRC_GENERAL_SRSR_DCDC_OVVT_MASK          (0x2000U)
78923 #define SRC_GENERAL_SRSR_DCDC_OVVT_SHIFT         (13U)
78924 /*! DCDC_OVVT - Indicates a reset has been caused by DCDC over voltage
78925  *  0b0..Reset is not a result of the DCDC over voltage.
78926  *  0b1..Reset is a result of the DCDC over voltage.
78927  */
78928 #define SRC_GENERAL_SRSR_DCDC_OVVT(x)            (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_DCDC_OVVT_SHIFT)) & SRC_GENERAL_SRSR_DCDC_OVVT_MASK)
78929 
78930 #define SRC_GENERAL_SRSR_ECAT_RSTO_MASK          (0x4000U)
78931 #define SRC_GENERAL_SRSR_ECAT_RSTO_SHIFT         (14U)
78932 /*! ECAT_RSTO - Indicates a reset has been caused by ECAT reset output
78933  *  0b0..Reset is not a result of the ECAT reset output.
78934  *  0b1..Reset is a result of the ECAT reset output.
78935  */
78936 #define SRC_GENERAL_SRSR_ECAT_RSTO(x)            (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_ECAT_RSTO_SHIFT)) & SRC_GENERAL_SRSR_ECAT_RSTO_MASK)
78937 
78938 #define SRC_GENERAL_SRSR_IPP_POR_B_MASK          (0x10000U)
78939 #define SRC_GENERAL_SRSR_IPP_POR_B_SHIFT         (16U)
78940 /*! IPP_POR_B - Indicates whether the reset was the result of chip PAD POR_B.
78941  *  0b0..Reset is not a result of chip PAD POR_B.
78942  *  0b1..Reset is a result of chip PAD POR_B.
78943  */
78944 #define SRC_GENERAL_SRSR_IPP_POR_B(x)            (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_SRSR_IPP_POR_B_SHIFT)) & SRC_GENERAL_SRSR_IPP_POR_B_MASK)
78945 /*! @} */
78946 
78947 /*! @name GPR - SRC General Purpose Register */
78948 /*! @{ */
78949 
78950 #define SRC_GENERAL_GPR_GPR_MASK                 (0xFFFFFFFFU)
78951 #define SRC_GENERAL_GPR_GPR_SHIFT                (0U)
78952 /*! GPR - General Purpose Register. */
78953 #define SRC_GENERAL_GPR_GPR(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_GPR_GPR_SHIFT)) & SRC_GENERAL_GPR_GPR_MASK)
78954 /*! @} */
78955 
78956 /* The count of SRC_GENERAL_GPR */
78957 #define SRC_GENERAL_GPR_COUNT                    (20U)
78958 
78959 
78960 /*!
78961  * @}
78962  */ /* end of group SRC_GENERAL_Register_Masks */
78963 
78964 
78965 /* SRC_GENERAL - Peripheral instance base addresses */
78966 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
78967   /** Peripheral SRC_GENERAL_REG base address */
78968   #define SRC_GENERAL_REG_BASE                     (0x54460000u)
78969   /** Peripheral SRC_GENERAL_REG base address */
78970   #define SRC_GENERAL_REG_BASE_NS                  (0x44460000u)
78971   /** Peripheral SRC_GENERAL_REG base pointer */
78972   #define SRC_GENERAL_REG                          ((SRC_GENERAL_Type *)SRC_GENERAL_REG_BASE)
78973   /** Peripheral SRC_GENERAL_REG base pointer */
78974   #define SRC_GENERAL_REG_NS                       ((SRC_GENERAL_Type *)SRC_GENERAL_REG_BASE_NS)
78975   /** Array initializer of SRC_GENERAL peripheral base addresses */
78976   #define SRC_GENERAL_BASE_ADDRS                   { SRC_GENERAL_REG_BASE }
78977   /** Array initializer of SRC_GENERAL peripheral base pointers */
78978   #define SRC_GENERAL_BASE_PTRS                    { SRC_GENERAL_REG }
78979   /** Array initializer of SRC_GENERAL peripheral base addresses */
78980   #define SRC_GENERAL_BASE_ADDRS_NS                { SRC_GENERAL_REG_BASE_NS }
78981   /** Array initializer of SRC_GENERAL peripheral base pointers */
78982   #define SRC_GENERAL_BASE_PTRS_NS                 { SRC_GENERAL_REG_NS }
78983 #else
78984   /** Peripheral SRC_GENERAL_REG base address */
78985   #define SRC_GENERAL_REG_BASE                     (0x44460000u)
78986   /** Peripheral SRC_GENERAL_REG base pointer */
78987   #define SRC_GENERAL_REG                          ((SRC_GENERAL_Type *)SRC_GENERAL_REG_BASE)
78988   /** Array initializer of SRC_GENERAL peripheral base addresses */
78989   #define SRC_GENERAL_BASE_ADDRS                   { SRC_GENERAL_REG_BASE }
78990   /** Array initializer of SRC_GENERAL peripheral base pointers */
78991   #define SRC_GENERAL_BASE_PTRS                    { SRC_GENERAL_REG }
78992 #endif
78993 
78994 /*!
78995  * @}
78996  */ /* end of group SRC_GENERAL_Peripheral_Access_Layer */
78997 
78998 
78999 /* ----------------------------------------------------------------------------
79000    -- SRC_MIF_LN28FDSOI_SPLLRAM Peripheral Access Layer
79001    ---------------------------------------------------------------------------- */
79002 
79003 /*!
79004  * @addtogroup SRC_MIF_LN28FDSOI_SPLLRAM_Peripheral_Access_Layer SRC_MIF_LN28FDSOI_SPLLRAM Peripheral Access Layer
79005  * @{
79006  */
79007 
79008 /** SRC_MIF_LN28FDSOI_SPLLRAM - Register Layout Typedef */
79009 typedef struct {
79010        uint8_t RESERVED_0[4];
79011   __IO uint32_t MIF_CTRL;                          /**< MPC Control, offset: 0x4 */
79012   __I  uint32_t MIF_STAT;                          /**< MIF Status, offset: 0x8 */
79013        uint8_t RESERVED_1[20];
79014   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of IG, offset: 0x20 */
79015   __IO uint32_t MIF_DLY_IG;                        /**< MIF Delay of IG, offset: 0x24 */
79016        uint8_t RESERVED_2[8];
79017   __IO uint32_t MIF_MLPL_WLPD;                     /**< MIF MLPL control of WLPD, offset: 0x30 */
79018   __IO uint32_t MIF_DLY_WLPD;                      /**< MIF Delay of WLPD, offset: 0x34 */
79019        uint8_t RESERVED_3[8];
79020   __IO uint32_t MIF_MLPL_PD_B;                     /**< MIF MLPL control of PD_B, offset: 0x40 */
79021   __IO uint32_t MIF_DLY_PD_B;                      /**< MIF Delay of PD_B, offset: 0x44 */
79022 } SRC_MIF_LN28FDSOI_SPLLRAM_Type;
79023 
79024 /* ----------------------------------------------------------------------------
79025    -- SRC_MIF_LN28FDSOI_SPLLRAM Register Masks
79026    ---------------------------------------------------------------------------- */
79027 
79028 /*!
79029  * @addtogroup SRC_MIF_LN28FDSOI_SPLLRAM_Register_Masks SRC_MIF_LN28FDSOI_SPLLRAM Register Masks
79030  * @{
79031  */
79032 
79033 /*! @name MIF_CTRL - MPC Control */
79034 /*! @{ */
79035 
79036 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_SW_CTRL_PIN_MASK (0x1U)
79037 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_SW_CTRL_PIN_SHIFT (0U)
79038 /*! SW_CTRL_PIN - Memory low power pins controlled by SW
79039  *  0b0..Use CURRENT_MLPL field to select MLPL_CTRL to control low power signal.
79040  *  0b1..Use SW_* field to control low power signal directly.
79041  */
79042 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_SW_CTRL_PIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_SW_CTRL_PIN_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_SW_CTRL_PIN_MASK)
79043 
79044 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_MEM_PWR_ST_EN_MASK (0x2U)
79045 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_MEM_PWR_ST_EN_SHIFT (1U)
79046 /*! MEM_PWR_ST_EN - Memory power status will be considered when determining slice power status.
79047  *  0b0..Memory power status will not be considered when determining slice power status.
79048  *  0b1..Memory power status will be considered when determining slice power status.
79049  */
79050 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_MEM_PWR_ST_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_MEM_PWR_ST_EN_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_MEM_PWR_ST_EN_MASK)
79051 
79052 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_LOCK_CFG_MASK (0x100000U)
79053 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_LOCK_CFG_SHIFT (20U)
79054 /*! LOCK_CFG - Configuration lock
79055  *  0b0..The fields are not locked.
79056  *  0b1..The fields are locked.
79057  */
79058 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_LOCK_CFG_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_CTRL_LOCK_CFG_MASK)
79059 /*! @} */
79060 
79061 /*! @name MIF_STAT - MIF Status */
79062 /*! @{ */
79063 
79064 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_MLPL_STATE_MASK (0x7U)
79065 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_MLPL_STATE_SHIFT (0U)
79066 /*! MLPL_STATE - Current state of CURRENT_MLPL */
79067 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_MLPL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_MLPL_STATE_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_MLPL_STATE_MASK)
79068 
79069 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_IG_STATE_MASK (0x8U)
79070 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_IG_STATE_SHIFT (3U)
79071 /*! IG_STATE - Current state of IG
79072  *  0b0..IG is 0.
79073  *  0b1..IG is 1.
79074  */
79075 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_IG_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_IG_STATE_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_IG_STATE_MASK)
79076 
79077 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_WLPD_STATE_MASK (0x10U)
79078 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_WLPD_STATE_SHIFT (4U)
79079 /*! WLPD_STATE - Current state of WLPD
79080  *  0b0..WLPD is 0.
79081  *  0b1..WLPD is 1.
79082  */
79083 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_WLPD_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_WLPD_STATE_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_WLPD_STATE_MASK)
79084 
79085 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_PD_B_STATE_MASK (0x20U)
79086 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_PD_B_STATE_SHIFT (5U)
79087 /*! PD_B_STATE - Current state of PD_B
79088  *  0b0..PD_B is 0.
79089  *  0b1..PD_B is 1.
79090  */
79091 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_PD_B_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_PD_B_STATE_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_STAT_PD_B_STATE_MASK)
79092 /*! @} */
79093 
79094 /*! @name MIF_MLPL_IG - MIF MLPL control of IG */
79095 /*! @{ */
79096 
79097 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFU)
79098 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U)
79099 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79100 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_MLPL_CTRL_MASK)
79101 
79102 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_SW_IG_MASK (0x10000U)
79103 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_SW_IG_SHIFT (16U)
79104 /*! SW_IG - Software control IG
79105  *  0b0..IG is 0.
79106  *  0b1..IG is 1.
79107  */
79108 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_SW_IG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_SW_IG_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_IG_SW_IG_MASK)
79109 /*! @} */
79110 
79111 /*! @name MIF_DLY_IG - MIF Delay of IG */
79112 /*! @{ */
79113 
79114 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_HI_DLY_MASK (0xFFFFU)
79115 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_HI_DLY_SHIFT (0U)
79116 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79117 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_HI_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_HI_DLY_MASK)
79118 
79119 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_LO_DLY_MASK (0xFFFF0000U)
79120 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_LO_DLY_SHIFT (16U)
79121 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79122 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_LO_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_IG_PRE_LO_DLY_MASK)
79123 /*! @} */
79124 
79125 /*! @name MIF_MLPL_WLPD - MIF MLPL control of WLPD */
79126 /*! @{ */
79127 
79128 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_MLPL_CTRL_MASK (0xFFU)
79129 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_MLPL_CTRL_SHIFT (0U)
79130 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79131 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_MLPL_CTRL_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_MLPL_CTRL_MASK)
79132 
79133 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_SW_WLPD_MASK (0x10000U)
79134 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_SW_WLPD_SHIFT (16U)
79135 /*! SW_WLPD - Software control WLPD
79136  *  0b1..WLPD is 1.
79137  *  0b0..WLPD is 0.
79138  */
79139 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_SW_WLPD(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_SW_WLPD_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_WLPD_SW_WLPD_MASK)
79140 /*! @} */
79141 
79142 /*! @name MIF_DLY_WLPD - MIF Delay of WLPD */
79143 /*! @{ */
79144 
79145 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_HI_DLY_MASK (0xFFFFU)
79146 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_HI_DLY_SHIFT (0U)
79147 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79148 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_HI_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_HI_DLY_MASK)
79149 
79150 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_LO_DLY_MASK (0xFFFF0000U)
79151 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_LO_DLY_SHIFT (16U)
79152 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79153 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_LO_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_WLPD_PRE_LO_DLY_MASK)
79154 /*! @} */
79155 
79156 /*! @name MIF_MLPL_PD_B - MIF MLPL control of PD_B */
79157 /*! @{ */
79158 
79159 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_MLPL_CTRL_MASK (0xFFU)
79160 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_MLPL_CTRL_SHIFT (0U)
79161 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79162 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_MLPL_CTRL_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_MLPL_CTRL_MASK)
79163 
79164 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_SW_PD_B_MASK (0x10000U)
79165 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_SW_PD_B_SHIFT (16U)
79166 /*! SW_PD_B - software control PD_B
79167  *  0b1..PD_B is 1.
79168  *  0b0..PD_B is 0.
79169  */
79170 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_SW_PD_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_SW_PD_B_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_MLPL_PD_B_SW_PD_B_MASK)
79171 /*! @} */
79172 
79173 /*! @name MIF_DLY_PD_B - MIF Delay of PD_B */
79174 /*! @{ */
79175 
79176 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_HI_DLY_MASK (0xFFFFU)
79177 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_HI_DLY_SHIFT (0U)
79178 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79179 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_HI_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_HI_DLY_MASK)
79180 
79181 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_LO_DLY_MASK (0xFFFF0000U)
79182 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_LO_DLY_SHIFT (16U)
79183 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79184 #define SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_LO_DLY_SHIFT)) & SRC_MIF_LN28FDSOI_SPLLRAM_MIF_DLY_PD_B_PRE_LO_DLY_MASK)
79185 /*! @} */
79186 
79187 
79188 /*!
79189  * @}
79190  */ /* end of group SRC_MIF_LN28FDSOI_SPLLRAM_Register_Masks */
79191 
79192 
79193 /* SRC_MIF_LN28FDSOI_SPLLRAM - Peripheral instance base addresses */
79194 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
79195   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base address */
79196   #define AON_MIF_LN28FDSOI_SPLLRAM_BASE           (0x54462400u)
79197   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base address */
79198   #define AON_MIF_LN28FDSOI_SPLLRAM_BASE_NS        (0x44462400u)
79199   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base pointer */
79200   #define AON_MIF_LN28FDSOI_SPLLRAM                ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)AON_MIF_LN28FDSOI_SPLLRAM_BASE)
79201   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base pointer */
79202   #define AON_MIF_LN28FDSOI_SPLLRAM_NS             ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)AON_MIF_LN28FDSOI_SPLLRAM_BASE_NS)
79203   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base address */
79204   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE        (0x54462C00u)
79205   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base address */
79206   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE_NS     (0x44462C00u)
79207   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base pointer */
79208   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM             ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE)
79209   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base pointer */
79210   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM_NS          ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE_NS)
79211   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base address */
79212   #define MEGA_MIF_LN28FDSOI_SPLLRAM_BASE          (0x54463400u)
79213   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base address */
79214   #define MEGA_MIF_LN28FDSOI_SPLLRAM_BASE_NS       (0x44463400u)
79215   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base pointer */
79216   #define MEGA_MIF_LN28FDSOI_SPLLRAM               ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)MEGA_MIF_LN28FDSOI_SPLLRAM_BASE)
79217   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base pointer */
79218   #define MEGA_MIF_LN28FDSOI_SPLLRAM_NS            ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)MEGA_MIF_LN28FDSOI_SPLLRAM_BASE_NS)
79219   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base address */
79220   #define NETC_MIF_LN28FDSOI_SPLLRAM_BASE          (0x54463C00u)
79221   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base address */
79222   #define NETC_MIF_LN28FDSOI_SPLLRAM_BASE_NS       (0x44463C00u)
79223   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base pointer */
79224   #define NETC_MIF_LN28FDSOI_SPLLRAM               ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)NETC_MIF_LN28FDSOI_SPLLRAM_BASE)
79225   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base pointer */
79226   #define NETC_MIF_LN28FDSOI_SPLLRAM_NS            ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)NETC_MIF_LN28FDSOI_SPLLRAM_BASE_NS)
79227   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base addresses */
79228   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_ADDRS     { AON_MIF_LN28FDSOI_SPLLRAM_BASE, WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE, MEGA_MIF_LN28FDSOI_SPLLRAM_BASE, NETC_MIF_LN28FDSOI_SPLLRAM_BASE }
79229   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base pointers */
79230   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_PTRS      { AON_MIF_LN28FDSOI_SPLLRAM, WAKEUP_MIF_LN28FDSOI_SPLLRAM, MEGA_MIF_LN28FDSOI_SPLLRAM, NETC_MIF_LN28FDSOI_SPLLRAM }
79231   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base addresses */
79232   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_ADDRS_NS  { AON_MIF_LN28FDSOI_SPLLRAM_BASE_NS, WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE_NS, MEGA_MIF_LN28FDSOI_SPLLRAM_BASE_NS, NETC_MIF_LN28FDSOI_SPLLRAM_BASE_NS }
79233   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base pointers */
79234   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_PTRS_NS   { AON_MIF_LN28FDSOI_SPLLRAM_NS, WAKEUP_MIF_LN28FDSOI_SPLLRAM_NS, MEGA_MIF_LN28FDSOI_SPLLRAM_NS, NETC_MIF_LN28FDSOI_SPLLRAM_NS }
79235 #else
79236   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base address */
79237   #define AON_MIF_LN28FDSOI_SPLLRAM_BASE           (0x44462400u)
79238   /** Peripheral AON_MIF_LN28FDSOI_SPLLRAM base pointer */
79239   #define AON_MIF_LN28FDSOI_SPLLRAM                ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)AON_MIF_LN28FDSOI_SPLLRAM_BASE)
79240   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base address */
79241   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE        (0x44462C00u)
79242   /** Peripheral WAKEUP_MIF_LN28FDSOI_SPLLRAM base pointer */
79243   #define WAKEUP_MIF_LN28FDSOI_SPLLRAM             ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE)
79244   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base address */
79245   #define MEGA_MIF_LN28FDSOI_SPLLRAM_BASE          (0x44463400u)
79246   /** Peripheral MEGA_MIF_LN28FDSOI_SPLLRAM base pointer */
79247   #define MEGA_MIF_LN28FDSOI_SPLLRAM               ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)MEGA_MIF_LN28FDSOI_SPLLRAM_BASE)
79248   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base address */
79249   #define NETC_MIF_LN28FDSOI_SPLLRAM_BASE          (0x44463C00u)
79250   /** Peripheral NETC_MIF_LN28FDSOI_SPLLRAM base pointer */
79251   #define NETC_MIF_LN28FDSOI_SPLLRAM               ((SRC_MIF_LN28FDSOI_SPLLRAM_Type *)NETC_MIF_LN28FDSOI_SPLLRAM_BASE)
79252   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base addresses */
79253   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_ADDRS     { AON_MIF_LN28FDSOI_SPLLRAM_BASE, WAKEUP_MIF_LN28FDSOI_SPLLRAM_BASE, MEGA_MIF_LN28FDSOI_SPLLRAM_BASE, NETC_MIF_LN28FDSOI_SPLLRAM_BASE }
79254   /** Array initializer of SRC_MIF_LN28FDSOI_SPLLRAM peripheral base pointers */
79255   #define SRC_MIF_LN28FDSOI_SPLLRAM_BASE_PTRS      { AON_MIF_LN28FDSOI_SPLLRAM, WAKEUP_MIF_LN28FDSOI_SPLLRAM, MEGA_MIF_LN28FDSOI_SPLLRAM, NETC_MIF_LN28FDSOI_SPLLRAM }
79256 #endif
79257 
79258 /*!
79259  * @}
79260  */ /* end of group SRC_MIF_LN28FDSOI_SPLLRAM_Peripheral_Access_Layer */
79261 
79262 
79263 /* ----------------------------------------------------------------------------
79264    -- SRC_MIF_S28SPREGH Peripheral Access Layer
79265    ---------------------------------------------------------------------------- */
79266 
79267 /*!
79268  * @addtogroup SRC_MIF_S28SPREGH_Peripheral_Access_Layer SRC_MIF_S28SPREGH Peripheral Access Layer
79269  * @{
79270  */
79271 
79272 /** SRC_MIF_S28SPREGH - Register Layout Typedef */
79273 typedef struct {
79274        uint8_t RESERVED_0[4];
79275   __IO uint32_t MIF_CTRL;                          /**< MPC Control, offset: 0x4 */
79276   __I  uint32_t MIF_STAT;                          /**< MIF Status, offset: 0x8 */
79277        uint8_t RESERVED_1[4];
79278   __IO uint32_t MIF_MLPL_LS;                       /**< MIF MLPL control of LS, offset: 0x10 */
79279   __IO uint32_t MIF_DLY_LS;                        /**< MIF Delay of LS, offset: 0x14 */
79280        uint8_t RESERVED_2[8];
79281   __IO uint32_t MIF_MLPL_HS;                       /**< MIF MLPL control of HS, offset: 0x20 */
79282   __IO uint32_t MIF_DLY_HS;                        /**< MIF Delay of HS, offset: 0x24 */
79283        uint8_t RESERVED_3[8];
79284   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of Input Gating (IG), offset: 0x30 */
79285   __IO uint32_t MIF_DLY_IG;                        /**< MIF Delay of IG, offset: 0x34 */
79286        uint8_t RESERVED_4[8];
79287   __IO uint32_t MIF_MLPL_STDBY;                    /**< MIF MLPL control of STDBY, offset: 0x40 */
79288   __IO uint32_t MIF_DLY_STDBY;                     /**< MIF Delay of STDBY, offset: 0x44 */
79289 } SRC_MIF_S28SPREGH_Type;
79290 
79291 /* ----------------------------------------------------------------------------
79292    -- SRC_MIF_S28SPREGH Register Masks
79293    ---------------------------------------------------------------------------- */
79294 
79295 /*!
79296  * @addtogroup SRC_MIF_S28SPREGH_Register_Masks SRC_MIF_S28SPREGH Register Masks
79297  * @{
79298  */
79299 
79300 /*! @name MIF_CTRL - MPC Control */
79301 /*! @{ */
79302 
79303 #define SRC_MIF_S28SPREGH_MIF_CTRL_SW_CTRL_PIN_MASK (0x1U)
79304 #define SRC_MIF_S28SPREGH_MIF_CTRL_SW_CTRL_PIN_SHIFT (0U)
79305 /*! SW_CTRL_PIN - Memory low power pins controlled by software (SW)
79306  *  0b0..Uses CURRENT_MLPL field to select MLPL_CTRL to control low power signal.
79307  *  0b1..Uses SW_* field to control low power signal directly.
79308  */
79309 #define SRC_MIF_S28SPREGH_MIF_CTRL_SW_CTRL_PIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_CTRL_SW_CTRL_PIN_SHIFT)) & SRC_MIF_S28SPREGH_MIF_CTRL_SW_CTRL_PIN_MASK)
79310 
79311 #define SRC_MIF_S28SPREGH_MIF_CTRL_MEM_PWR_ST_EN_MASK (0x2U)
79312 #define SRC_MIF_S28SPREGH_MIF_CTRL_MEM_PWR_ST_EN_SHIFT (1U)
79313 /*! MEM_PWR_ST_EN - Memory power status will be considered when determining slice power status.
79314  *  0b1..Memory power status will be considered when determining slice power status.
79315  *  0b0..Memory power status will not be considered when determining slice power status.
79316  */
79317 #define SRC_MIF_S28SPREGH_MIF_CTRL_MEM_PWR_ST_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_CTRL_MEM_PWR_ST_EN_SHIFT)) & SRC_MIF_S28SPREGH_MIF_CTRL_MEM_PWR_ST_EN_MASK)
79318 
79319 #define SRC_MIF_S28SPREGH_MIF_CTRL_LOCK_CFG_MASK (0x100000U)
79320 #define SRC_MIF_S28SPREGH_MIF_CTRL_LOCK_CFG_SHIFT (20U)
79321 /*! LOCK_CFG - Configuration lock
79322  *  0b0..The fields are not locked.
79323  *  0b1..The fields are locked.
79324  */
79325 #define SRC_MIF_S28SPREGH_MIF_CTRL_LOCK_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_CTRL_LOCK_CFG_SHIFT)) & SRC_MIF_S28SPREGH_MIF_CTRL_LOCK_CFG_MASK)
79326 /*! @} */
79327 
79328 /*! @name MIF_STAT - MIF Status */
79329 /*! @{ */
79330 
79331 #define SRC_MIF_S28SPREGH_MIF_STAT_MLPL_STATE_MASK (0x7U)
79332 #define SRC_MIF_S28SPREGH_MIF_STAT_MLPL_STATE_SHIFT (0U)
79333 /*! MLPL_STATE - Current state of CURRENT_MLPL */
79334 #define SRC_MIF_S28SPREGH_MIF_STAT_MLPL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_STAT_MLPL_STATE_SHIFT)) & SRC_MIF_S28SPREGH_MIF_STAT_MLPL_STATE_MASK)
79335 
79336 #define SRC_MIF_S28SPREGH_MIF_STAT_LS_STATE_MASK (0x8U)
79337 #define SRC_MIF_S28SPREGH_MIF_STAT_LS_STATE_SHIFT (3U)
79338 /*! LS_STATE - Current state of LS
79339  *  0b0..LS is 0.
79340  *  0b1..LS is 1.
79341  */
79342 #define SRC_MIF_S28SPREGH_MIF_STAT_LS_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_STAT_LS_STATE_SHIFT)) & SRC_MIF_S28SPREGH_MIF_STAT_LS_STATE_MASK)
79343 
79344 #define SRC_MIF_S28SPREGH_MIF_STAT_HS_STATE_MASK (0x10U)
79345 #define SRC_MIF_S28SPREGH_MIF_STAT_HS_STATE_SHIFT (4U)
79346 /*! HS_STATE - Current state of HS
79347  *  0b0..HS is 0.
79348  *  0b1..HS is 1.
79349  */
79350 #define SRC_MIF_S28SPREGH_MIF_STAT_HS_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_STAT_HS_STATE_SHIFT)) & SRC_MIF_S28SPREGH_MIF_STAT_HS_STATE_MASK)
79351 
79352 #define SRC_MIF_S28SPREGH_MIF_STAT_IG_STATE_MASK (0x20U)
79353 #define SRC_MIF_S28SPREGH_MIF_STAT_IG_STATE_SHIFT (5U)
79354 /*! IG_STATE - Current state of IG
79355  *  0b0..IG is 0.
79356  *  0b1..IG is 1.
79357  */
79358 #define SRC_MIF_S28SPREGH_MIF_STAT_IG_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_STAT_IG_STATE_SHIFT)) & SRC_MIF_S28SPREGH_MIF_STAT_IG_STATE_MASK)
79359 
79360 #define SRC_MIF_S28SPREGH_MIF_STAT_STDBY_STATE_MASK (0x40U)
79361 #define SRC_MIF_S28SPREGH_MIF_STAT_STDBY_STATE_SHIFT (6U)
79362 /*! STDBY_STATE - Current state of STDBY
79363  *  0b0..STDBY is 0.
79364  *  0b1..STDBY is 1.
79365  */
79366 #define SRC_MIF_S28SPREGH_MIF_STAT_STDBY_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_STAT_STDBY_STATE_SHIFT)) & SRC_MIF_S28SPREGH_MIF_STAT_STDBY_STATE_MASK)
79367 /*! @} */
79368 
79369 /*! @name MIF_MLPL_LS - MIF MLPL control of LS */
79370 /*! @{ */
79371 
79372 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFU)
79373 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U)
79374 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79375 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_LS_MLPL_CTRL_MASK)
79376 
79377 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_SW_LS_MASK (0x10000U)
79378 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_SW_LS_SHIFT (16U)
79379 /*! SW_LS - Software control LS
79380  *  0b0..LS is 0.
79381  *  0b1..LS is 1.
79382  */
79383 #define SRC_MIF_S28SPREGH_MIF_MLPL_LS_SW_LS(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_LS_SW_LS_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_LS_SW_LS_MASK)
79384 /*! @} */
79385 
79386 /*! @name MIF_DLY_LS - MIF Delay of LS */
79387 /*! @{ */
79388 
79389 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_HI_DLY_MASK (0xFFFFU)
79390 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_HI_DLY_SHIFT (0U)
79391 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79392 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_HI_DLY_MASK)
79393 
79394 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_LO_DLY_MASK (0xFFFF0000U)
79395 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_LO_DLY_SHIFT (16U)
79396 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79397 #define SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_LS_PRE_LO_DLY_MASK)
79398 /*! @} */
79399 
79400 /*! @name MIF_MLPL_HS - MIF MLPL control of HS */
79401 /*! @{ */
79402 
79403 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFU)
79404 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U)
79405 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79406 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_HS_MLPL_CTRL_MASK)
79407 
79408 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_SW_HS_MASK (0x10000U)
79409 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_SW_HS_SHIFT (16U)
79410 /*! SW_HS - software control HS
79411  *  0b0..HS is 0.
79412  *  0b1..HS is 1.
79413  */
79414 #define SRC_MIF_S28SPREGH_MIF_MLPL_HS_SW_HS(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_HS_SW_HS_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_HS_SW_HS_MASK)
79415 /*! @} */
79416 
79417 /*! @name MIF_DLY_HS - MIF Delay of HS */
79418 /*! @{ */
79419 
79420 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_HI_DLY_MASK (0xFFFFU)
79421 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_HI_DLY_SHIFT (0U)
79422 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79423 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_HI_DLY_MASK)
79424 
79425 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_LO_DLY_MASK (0xFFFF0000U)
79426 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_LO_DLY_SHIFT (16U)
79427 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79428 #define SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_HS_PRE_LO_DLY_MASK)
79429 /*! @} */
79430 
79431 /*! @name MIF_MLPL_IG - MIF MLPL control of Input Gating (IG) */
79432 /*! @{ */
79433 
79434 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFU)
79435 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U)
79436 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79437 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_IG_MLPL_CTRL_MASK)
79438 
79439 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_SW_IG_MASK (0x10000U)
79440 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_SW_IG_SHIFT (16U)
79441 /*! SW_IG - Software control IG
79442  *  0b0..IG is 0.
79443  *  0b1..IG is 1.
79444  */
79445 #define SRC_MIF_S28SPREGH_MIF_MLPL_IG_SW_IG(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_IG_SW_IG_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_IG_SW_IG_MASK)
79446 /*! @} */
79447 
79448 /*! @name MIF_DLY_IG - MIF Delay of IG */
79449 /*! @{ */
79450 
79451 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_HI_DLY_MASK (0xFFFFU)
79452 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_HI_DLY_SHIFT (0U)
79453 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79454 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_HI_DLY_MASK)
79455 
79456 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_LO_DLY_MASK (0xFFFF0000U)
79457 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_LO_DLY_SHIFT (16U)
79458 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79459 #define SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_IG_PRE_LO_DLY_MASK)
79460 /*! @} */
79461 
79462 /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
79463 /*! @{ */
79464 
79465 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFU)
79466 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U)
79467 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79468 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
79469 
79470 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_SW_STDBY_MASK (0x10000U)
79471 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_SW_STDBY_SHIFT (16U)
79472 /*! SW_STDBY - Software control STDBY
79473  *  0b0..STDBY is 0.
79474  *  0b1..STDBY is 1.
79475  */
79476 #define SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_SW_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_SW_STDBY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_MLPL_STDBY_SW_STDBY_MASK)
79477 /*! @} */
79478 
79479 /*! @name MIF_DLY_STDBY - MIF Delay of STDBY */
79480 /*! @{ */
79481 
79482 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_HI_DLY_MASK (0xFFFFU)
79483 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT (0U)
79484 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79485 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_HI_DLY_MASK)
79486 
79487 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_LO_DLY_MASK (0xFFFF0000U)
79488 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT (16U)
79489 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79490 #define SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_MIF_DLY_STDBY_PRE_LO_DLY_MASK)
79491 /*! @} */
79492 
79493 
79494 /*!
79495  * @}
79496  */ /* end of group SRC_MIF_S28SPREGH_Register_Masks */
79497 
79498 
79499 /* SRC_MIF_S28SPREGH - Peripheral instance base addresses */
79500 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
79501   /** Peripheral AON_MIF_S28SPREGH base address */
79502   #define AON_MIF_S28SPREGH_BASE                   (0x54462000u)
79503   /** Peripheral AON_MIF_S28SPREGH base address */
79504   #define AON_MIF_S28SPREGH_BASE_NS                (0x44462000u)
79505   /** Peripheral AON_MIF_S28SPREGH base pointer */
79506   #define AON_MIF_S28SPREGH                        ((SRC_MIF_S28SPREGH_Type *)AON_MIF_S28SPREGH_BASE)
79507   /** Peripheral AON_MIF_S28SPREGH base pointer */
79508   #define AON_MIF_S28SPREGH_NS                     ((SRC_MIF_S28SPREGH_Type *)AON_MIF_S28SPREGH_BASE_NS)
79509   /** Peripheral WAKEUP_MIF_S28SPREGH base address */
79510   #define WAKEUP_MIF_S28SPREGH_BASE                (0x54462800u)
79511   /** Peripheral WAKEUP_MIF_S28SPREGH base address */
79512   #define WAKEUP_MIF_S28SPREGH_BASE_NS             (0x44462800u)
79513   /** Peripheral WAKEUP_MIF_S28SPREGH base pointer */
79514   #define WAKEUP_MIF_S28SPREGH                     ((SRC_MIF_S28SPREGH_Type *)WAKEUP_MIF_S28SPREGH_BASE)
79515   /** Peripheral WAKEUP_MIF_S28SPREGH base pointer */
79516   #define WAKEUP_MIF_S28SPREGH_NS                  ((SRC_MIF_S28SPREGH_Type *)WAKEUP_MIF_S28SPREGH_BASE_NS)
79517   /** Peripheral MEGA_MIF_S28SPREGH base address */
79518   #define MEGA_MIF_S28SPREGH_BASE                  (0x54463000u)
79519   /** Peripheral MEGA_MIF_S28SPREGH base address */
79520   #define MEGA_MIF_S28SPREGH_BASE_NS               (0x44463000u)
79521   /** Peripheral MEGA_MIF_S28SPREGH base pointer */
79522   #define MEGA_MIF_S28SPREGH                       ((SRC_MIF_S28SPREGH_Type *)MEGA_MIF_S28SPREGH_BASE)
79523   /** Peripheral MEGA_MIF_S28SPREGH base pointer */
79524   #define MEGA_MIF_S28SPREGH_NS                    ((SRC_MIF_S28SPREGH_Type *)MEGA_MIF_S28SPREGH_BASE_NS)
79525   /** Peripheral NETC_MIF_S28SPREGH base address */
79526   #define NETC_MIF_S28SPREGH_BASE                  (0x54463800u)
79527   /** Peripheral NETC_MIF_S28SPREGH base address */
79528   #define NETC_MIF_S28SPREGH_BASE_NS               (0x44463800u)
79529   /** Peripheral NETC_MIF_S28SPREGH base pointer */
79530   #define NETC_MIF_S28SPREGH                       ((SRC_MIF_S28SPREGH_Type *)NETC_MIF_S28SPREGH_BASE)
79531   /** Peripheral NETC_MIF_S28SPREGH base pointer */
79532   #define NETC_MIF_S28SPREGH_NS                    ((SRC_MIF_S28SPREGH_Type *)NETC_MIF_S28SPREGH_BASE_NS)
79533   /** Peripheral CM33PLATFORM_CACHE base address */
79534   #define CM33PLATFORM_CACHE_BASE                  (0x54464000u)
79535   /** Peripheral CM33PLATFORM_CACHE base address */
79536   #define CM33PLATFORM_CACHE_BASE_NS               (0x44464000u)
79537   /** Peripheral CM33PLATFORM_CACHE base pointer */
79538   #define CM33PLATFORM_CACHE                       ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_CACHE_BASE)
79539   /** Peripheral CM33PLATFORM_CACHE base pointer */
79540   #define CM33PLATFORM_CACHE_NS                    ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_CACHE_BASE_NS)
79541   /** Peripheral CM7PLATFORM_CACHE base address */
79542   #define CM7PLATFORM_CACHE_BASE                   (0x54464800u)
79543   /** Peripheral CM7PLATFORM_CACHE base address */
79544   #define CM7PLATFORM_CACHE_BASE_NS                (0x44464800u)
79545   /** Peripheral CM7PLATFORM_CACHE base pointer */
79546   #define CM7PLATFORM_CACHE                        ((SRC_MIF_S28SPREGH_Type *)CM7PLATFORM_CACHE_BASE)
79547   /** Peripheral CM7PLATFORM_CACHE base pointer */
79548   #define CM7PLATFORM_CACHE_NS                     ((SRC_MIF_S28SPREGH_Type *)CM7PLATFORM_CACHE_BASE_NS)
79549   /** Peripheral CM33PLATFORM_TCM base address */
79550   #define CM33PLATFORM_TCM_BASE                    (0x54464400u)
79551   /** Peripheral CM33PLATFORM_TCM base address */
79552   #define CM33PLATFORM_TCM_BASE_NS                 (0x44464400u)
79553   /** Peripheral CM33PLATFORM_TCM base pointer */
79554   #define CM33PLATFORM_TCM                         ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_TCM_BASE)
79555   /** Peripheral CM33PLATFORM_TCM base pointer */
79556   #define CM33PLATFORM_TCM_NS                      ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_TCM_BASE_NS)
79557   /** Array initializer of SRC_MIF_S28SPREGH peripheral base addresses */
79558   #define SRC_MIF_S28SPREGH_BASE_ADDRS             { AON_MIF_S28SPREGH_BASE, WAKEUP_MIF_S28SPREGH_BASE, MEGA_MIF_S28SPREGH_BASE, NETC_MIF_S28SPREGH_BASE, CM33PLATFORM_CACHE_BASE, CM7PLATFORM_CACHE_BASE, CM33PLATFORM_TCM_BASE }
79559   /** Array initializer of SRC_MIF_S28SPREGH peripheral base pointers */
79560   #define SRC_MIF_S28SPREGH_BASE_PTRS              { AON_MIF_S28SPREGH, WAKEUP_MIF_S28SPREGH, MEGA_MIF_S28SPREGH, NETC_MIF_S28SPREGH, CM33PLATFORM_CACHE, CM7PLATFORM_CACHE, CM33PLATFORM_TCM }
79561   /** Array initializer of SRC_MIF_S28SPREGH peripheral base addresses */
79562   #define SRC_MIF_S28SPREGH_BASE_ADDRS_NS          { AON_MIF_S28SPREGH_BASE_NS, WAKEUP_MIF_S28SPREGH_BASE_NS, MEGA_MIF_S28SPREGH_BASE_NS, NETC_MIF_S28SPREGH_BASE_NS, CM33PLATFORM_CACHE_BASE_NS, CM7PLATFORM_CACHE_BASE_NS, CM33PLATFORM_TCM_BASE_NS }
79563   /** Array initializer of SRC_MIF_S28SPREGH peripheral base pointers */
79564   #define SRC_MIF_S28SPREGH_BASE_PTRS_NS           { AON_MIF_S28SPREGH_NS, WAKEUP_MIF_S28SPREGH_NS, MEGA_MIF_S28SPREGH_NS, NETC_MIF_S28SPREGH_NS, CM33PLATFORM_CACHE_NS, CM7PLATFORM_CACHE_NS, CM33PLATFORM_TCM_NS }
79565 #else
79566   /** Peripheral AON_MIF_S28SPREGH base address */
79567   #define AON_MIF_S28SPREGH_BASE                   (0x44462000u)
79568   /** Peripheral AON_MIF_S28SPREGH base pointer */
79569   #define AON_MIF_S28SPREGH                        ((SRC_MIF_S28SPREGH_Type *)AON_MIF_S28SPREGH_BASE)
79570   /** Peripheral WAKEUP_MIF_S28SPREGH base address */
79571   #define WAKEUP_MIF_S28SPREGH_BASE                (0x44462800u)
79572   /** Peripheral WAKEUP_MIF_S28SPREGH base pointer */
79573   #define WAKEUP_MIF_S28SPREGH                     ((SRC_MIF_S28SPREGH_Type *)WAKEUP_MIF_S28SPREGH_BASE)
79574   /** Peripheral MEGA_MIF_S28SPREGH base address */
79575   #define MEGA_MIF_S28SPREGH_BASE                  (0x44463000u)
79576   /** Peripheral MEGA_MIF_S28SPREGH base pointer */
79577   #define MEGA_MIF_S28SPREGH                       ((SRC_MIF_S28SPREGH_Type *)MEGA_MIF_S28SPREGH_BASE)
79578   /** Peripheral NETC_MIF_S28SPREGH base address */
79579   #define NETC_MIF_S28SPREGH_BASE                  (0x44463800u)
79580   /** Peripheral NETC_MIF_S28SPREGH base pointer */
79581   #define NETC_MIF_S28SPREGH                       ((SRC_MIF_S28SPREGH_Type *)NETC_MIF_S28SPREGH_BASE)
79582   /** Peripheral CM33PLATFORM_CACHE base address */
79583   #define CM33PLATFORM_CACHE_BASE                  (0x44464000u)
79584   /** Peripheral CM33PLATFORM_CACHE base pointer */
79585   #define CM33PLATFORM_CACHE                       ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_CACHE_BASE)
79586   /** Peripheral CM7PLATFORM_CACHE base address */
79587   #define CM7PLATFORM_CACHE_BASE                   (0x44464800u)
79588   /** Peripheral CM7PLATFORM_CACHE base pointer */
79589   #define CM7PLATFORM_CACHE                        ((SRC_MIF_S28SPREGH_Type *)CM7PLATFORM_CACHE_BASE)
79590   /** Peripheral CM33PLATFORM_TCM base address */
79591   #define CM33PLATFORM_TCM_BASE                    (0x44464400u)
79592   /** Peripheral CM33PLATFORM_TCM base pointer */
79593   #define CM33PLATFORM_TCM                         ((SRC_MIF_S28SPREGH_Type *)CM33PLATFORM_TCM_BASE)
79594   /** Array initializer of SRC_MIF_S28SPREGH peripheral base addresses */
79595   #define SRC_MIF_S28SPREGH_BASE_ADDRS             { AON_MIF_S28SPREGH_BASE, WAKEUP_MIF_S28SPREGH_BASE, MEGA_MIF_S28SPREGH_BASE, NETC_MIF_S28SPREGH_BASE, CM33PLATFORM_CACHE_BASE, CM7PLATFORM_CACHE_BASE, CM33PLATFORM_TCM_BASE }
79596   /** Array initializer of SRC_MIF_S28SPREGH peripheral base pointers */
79597   #define SRC_MIF_S28SPREGH_BASE_PTRS              { AON_MIF_S28SPREGH, WAKEUP_MIF_S28SPREGH, MEGA_MIF_S28SPREGH, NETC_MIF_S28SPREGH, CM33PLATFORM_CACHE, CM7PLATFORM_CACHE, CM33PLATFORM_TCM }
79598 #endif
79599 
79600 /*!
79601  * @}
79602  */ /* end of group SRC_MIF_S28SPREGH_Peripheral_Access_Layer */
79603 
79604 
79605 /* ----------------------------------------------------------------------------
79606    -- SRC_MIF_S28SPREGH_PSWA Peripheral Access Layer
79607    ---------------------------------------------------------------------------- */
79608 
79609 /*!
79610  * @addtogroup SRC_MIF_S28SPREGH_PSWA_Peripheral_Access_Layer SRC_MIF_S28SPREGH_PSWA Peripheral Access Layer
79611  * @{
79612  */
79613 
79614 /** SRC_MIF_S28SPREGH_PSWA - Register Layout Typedef */
79615 typedef struct {
79616        uint8_t RESERVED_0[4];
79617   __IO uint32_t MIF_CTRL;                          /**< MPC Control, offset: 0x4 */
79618   __I  uint32_t MIF_STAT;                          /**< MIF Status, offset: 0x8 */
79619        uint8_t RESERVED_1[4];
79620   __IO uint32_t MIF_MLPL_LS;                       /**< MIF MLPL control of LS, offset: 0x10 */
79621   __IO uint32_t MIF_DLY_LS;                        /**< MIF Delay of LS, offset: 0x14 */
79622        uint8_t RESERVED_2[8];
79623   __IO uint32_t MIF_MLPL_HS;                       /**< MIF MLPL control of HS, offset: 0x20 */
79624   __IO uint32_t MIF_DLY_HS;                        /**< MIF Delay of HS, offset: 0x24 */
79625        uint8_t RESERVED_3[8];
79626   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of Input Gating (IG), offset: 0x30 */
79627   __IO uint32_t MIF_DLY_IG;                        /**< MIF Delay of IG, offset: 0x34 */
79628        uint8_t RESERVED_4[8];
79629   __IO uint32_t MIF_MLPL_STDBY;                    /**< MIF MLPL control of STDBY, offset: 0x40 */
79630   __IO uint32_t MIF_DLY_STDBY;                     /**< MIF Delay of STDBY, offset: 0x44 */
79631        uint8_t RESERVED_5[8];
79632   __IO uint32_t MIF_MLPL_SLEEP;                    /**< MIF MLPL control of SLEEP, offset: 0x50 */
79633   __IO uint32_t MIF_DLY_SLEEP;                     /**< MIF Delay of SLEEP, offset: 0x54 */
79634        uint8_t RESERVED_6[8];
79635   __IO uint32_t MIF_MLPL_ARR_PDN;                  /**< MIF MLPL control of array power down, offset: 0x60 */
79636   __IO uint32_t MIF_DLY_ARR_HF;                    /**< MIF Delay of array high-fanout power switch, offset: 0x64 */
79637 } SRC_MIF_S28SPREGH_PSWA_Type;
79638 
79639 /* ----------------------------------------------------------------------------
79640    -- SRC_MIF_S28SPREGH_PSWA Register Masks
79641    ---------------------------------------------------------------------------- */
79642 
79643 /*!
79644  * @addtogroup SRC_MIF_S28SPREGH_PSWA_Register_Masks SRC_MIF_S28SPREGH_PSWA Register Masks
79645  * @{
79646  */
79647 
79648 /*! @name MIF_CTRL - MPC Control */
79649 /*! @{ */
79650 
79651 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_SW_CTRL_PIN_MASK (0x1U)
79652 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_SW_CTRL_PIN_SHIFT (0U)
79653 /*! SW_CTRL_PIN - Memory low power pins controlled by SW
79654  *  0b0..Use CURRENT_MLPL field to select MLPL_CTRL to control low power signal.
79655  *  0b1..Use SW_* field to control low power signal directly.
79656  */
79657 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_SW_CTRL_PIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_SW_CTRL_PIN_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_SW_CTRL_PIN_MASK)
79658 
79659 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_MEM_PWR_ST_EN_MASK (0x2U)
79660 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_MEM_PWR_ST_EN_SHIFT (1U)
79661 /*! MEM_PWR_ST_EN - Memory power status will be considered when determining slice power status.
79662  *  0b1..Memory power status will be considered when determining slice power status.
79663  *  0b0..Memory power status will not be considered when determining slice power status.
79664  */
79665 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_MEM_PWR_ST_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_MEM_PWR_ST_EN_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_MEM_PWR_ST_EN_MASK)
79666 
79667 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_LOCK_CFG_MASK (0x100000U)
79668 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_LOCK_CFG_SHIFT (20U)
79669 /*! LOCK_CFG - Configuration lock
79670  *  0b0..The fields are not locked.
79671  *  0b1..The fields are locked.
79672  */
79673 #define SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_LOCK_CFG_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_CTRL_LOCK_CFG_MASK)
79674 /*! @} */
79675 
79676 /*! @name MIF_STAT - MIF Status */
79677 /*! @{ */
79678 
79679 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_MLPL_STATE_MASK (0x7U)
79680 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_MLPL_STATE_SHIFT (0U)
79681 /*! MLPL_STATE - Current state of CURRENT_MLPL */
79682 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_MLPL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_MLPL_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_MLPL_STATE_MASK)
79683 
79684 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_LS_STATE_MASK (0x8U)
79685 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_LS_STATE_SHIFT (3U)
79686 /*! LS_STATE - Current state of LS
79687  *  0b0..LS is 0.
79688  *  0b1..LS is 1.
79689  */
79690 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_LS_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_LS_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_LS_STATE_MASK)
79691 
79692 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_HS_STATE_MASK (0x10U)
79693 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_HS_STATE_SHIFT (4U)
79694 /*! HS_STATE - Current state of HS
79695  *  0b0..HS is 0.
79696  *  0b1..HS is 1.
79697  */
79698 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_HS_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_HS_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_HS_STATE_MASK)
79699 
79700 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_IG_STATE_MASK (0x20U)
79701 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_IG_STATE_SHIFT (5U)
79702 /*! IG_STATE - Current state of IG
79703  *  0b0..IG is 0.
79704  *  0b1..IG is 1.
79705  */
79706 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_IG_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_IG_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_IG_STATE_MASK)
79707 
79708 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_STDBY_STATE_MASK (0x40U)
79709 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_STDBY_STATE_SHIFT (6U)
79710 /*! STDBY_STATE - Current state of STDBY
79711  *  0b0..STDBY is 0.
79712  *  0b1..STDBY is 1.
79713  */
79714 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_STDBY_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_STDBY_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_STDBY_STATE_MASK)
79715 
79716 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_SLEEP_STATE_MASK (0x80U)
79717 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_SLEEP_STATE_SHIFT (7U)
79718 /*! SLEEP_STATE - SLEEP status
79719  *  0b0..SLEEP is 0.
79720  *  0b1..SLEEP is 1.
79721  */
79722 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_SLEEP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_SLEEP_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_SLEEP_STATE_MASK)
79723 
79724 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_ARR_HF_STATE_MASK (0x100U)
79725 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_ARR_HF_STATE_SHIFT (8U)
79726 /*! ARR_HF_STATE - ARR_HF_OFF status
79727  *  0b0..ARR_HS is 0.
79728  *  0b1..ARR_HS is 1.
79729  */
79730 #define SRC_MIF_S28SPREGH_PSWA_MIF_STAT_ARR_HF_STATE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_STAT_ARR_HF_STATE_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_STAT_ARR_HF_STATE_MASK)
79731 /*! @} */
79732 
79733 /*! @name MIF_MLPL_LS - MIF MLPL control of LS */
79734 /*! @{ */
79735 
79736 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFU)
79737 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U)
79738 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79739 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_MLPL_CTRL_MASK)
79740 
79741 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_SW_LS_MASK (0x10000U)
79742 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_SW_LS_SHIFT (16U)
79743 /*! SW_LS - Software control LS
79744  *  0b0..LS is 0.
79745  *  0b1..LS is 1.
79746  */
79747 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_SW_LS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_SW_LS_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_LS_SW_LS_MASK)
79748 /*! @} */
79749 
79750 /*! @name MIF_DLY_LS - MIF Delay of LS */
79751 /*! @{ */
79752 
79753 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_HI_DLY_MASK (0xFFFFU)
79754 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_HI_DLY_SHIFT (0U)
79755 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79756 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_HI_DLY_MASK)
79757 
79758 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_LO_DLY_MASK (0xFFFF0000U)
79759 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_LO_DLY_SHIFT (16U)
79760 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79761 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_LS_PRE_LO_DLY_MASK)
79762 /*! @} */
79763 
79764 /*! @name MIF_MLPL_HS - MIF MLPL control of HS */
79765 /*! @{ */
79766 
79767 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFU)
79768 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U)
79769 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79770 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_MLPL_CTRL_MASK)
79771 
79772 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_SW_HS_MASK (0x10000U)
79773 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_SW_HS_SHIFT (16U)
79774 /*! SW_HS - software control HS
79775  *  0b0..HS is 0.
79776  *  0b1..HS is 1.
79777  */
79778 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_SW_HS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_SW_HS_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_HS_SW_HS_MASK)
79779 /*! @} */
79780 
79781 /*! @name MIF_DLY_HS - MIF Delay of HS */
79782 /*! @{ */
79783 
79784 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_HI_DLY_MASK (0xFFFFU)
79785 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_HI_DLY_SHIFT (0U)
79786 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79787 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_HI_DLY_MASK)
79788 
79789 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_LO_DLY_MASK (0xFFFF0000U)
79790 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_LO_DLY_SHIFT (16U)
79791 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79792 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_HS_PRE_LO_DLY_MASK)
79793 /*! @} */
79794 
79795 /*! @name MIF_MLPL_IG - MIF MLPL control of Input Gating (IG) */
79796 /*! @{ */
79797 
79798 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFU)
79799 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U)
79800 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79801 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_MLPL_CTRL_MASK)
79802 
79803 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_SW_IG_MASK (0x10000U)
79804 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_SW_IG_SHIFT (16U)
79805 /*! SW_IG - Software control IG
79806  *  0b0..IG is 0.
79807  *  0b1..IG is 1.
79808  */
79809 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_SW_IG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_SW_IG_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_IG_SW_IG_MASK)
79810 /*! @} */
79811 
79812 /*! @name MIF_DLY_IG - MIF Delay of IG */
79813 /*! @{ */
79814 
79815 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_HI_DLY_MASK (0xFFFFU)
79816 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_HI_DLY_SHIFT (0U)
79817 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79818 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_HI_DLY_MASK)
79819 
79820 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_LO_DLY_MASK (0xFFFF0000U)
79821 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_LO_DLY_SHIFT (16U)
79822 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79823 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_IG_PRE_LO_DLY_MASK)
79824 /*! @} */
79825 
79826 /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
79827 /*! @{ */
79828 
79829 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFU)
79830 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U)
79831 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79832 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
79833 
79834 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_SW_STDBY_MASK (0x10000U)
79835 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_SW_STDBY_SHIFT (16U)
79836 /*! SW_STDBY - Software control STDBY
79837  *  0b0..STDBY is 0.
79838  *  0b1..STDBY is 1.
79839  */
79840 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_SW_STDBY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_SW_STDBY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_STDBY_SW_STDBY_MASK)
79841 /*! @} */
79842 
79843 /*! @name MIF_DLY_STDBY - MIF Delay of STDBY */
79844 /*! @{ */
79845 
79846 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_HI_DLY_MASK (0xFFFFU)
79847 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT (0U)
79848 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field */
79849 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_HI_DLY_MASK)
79850 
79851 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_LO_DLY_MASK (0xFFFF0000U)
79852 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT (16U)
79853 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field */
79854 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_STDBY_PRE_LO_DLY_MASK)
79855 /*! @} */
79856 
79857 /*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */
79858 /*! @{ */
79859 
79860 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_MLPL_CTRL_MASK (0xFFU)
79861 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT (0U)
79862 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79863 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
79864 
79865 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_SW_SLEEP_MASK (0x10000U)
79866 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_SW_SLEEP_SHIFT (16U)
79867 /*! SW_SLEEP - Software control SLEEP
79868  *  0b0..SLEEP is 0.
79869  *  0b1..SLEEP is 1.
79870  */
79871 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_SW_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_SW_SLEEP_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_SLEEP_SW_SLEEP_MASK)
79872 /*! @} */
79873 
79874 /*! @name MIF_DLY_SLEEP - MIF Delay of SLEEP */
79875 /*! @{ */
79876 
79877 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_HI_DLY_MASK (0xFFFFU)
79878 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_HI_DLY_SHIFT (0U)
79879 /*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field. */
79880 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_HI_DLY_MASK)
79881 
79882 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_LO_DLY_MASK (0xFFFF0000U)
79883 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_LO_DLY_SHIFT (16U)
79884 /*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field. */
79885 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_SLEEP_PRE_LO_DLY_MASK)
79886 /*! @} */
79887 
79888 /*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */
79889 /*! @{ */
79890 
79891 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFU)
79892 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
79893 /*! MLPL_CTRL - Signal behavior at 8 different MLPL settings */
79894 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
79895 
79896 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_SW_ARR_PDN_MASK (0x10000U)
79897 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_SW_ARR_PDN_SHIFT (16U)
79898 /*! SW_ARR_PDN - Software control arr pdn
79899  *  0b0..ARR_PDN is 0.
79900  *  0b1..ARR_PDN is 1.
79901  */
79902 #define SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_SW_ARR_PDN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_SW_ARR_PDN_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_MLPL_ARR_PDN_SW_ARR_PDN_MASK)
79903 /*! @} */
79904 
79905 /*! @name MIF_DLY_ARR_HF - MIF Delay of array high-fanout power switch */
79906 /*! @{ */
79907 
79908 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_HI_DLY_MASK (0xFFFFU)
79909 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_HI_DLY_SHIFT (0U)
79910 /*! PRE_HI_DLY - Delay before turn off the high-fanout power switch, locked by LOCK_CFG field */
79911 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_HI_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_HI_DLY_MASK)
79912 
79913 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_LO_DLY_MASK (0xFFFF0000U)
79914 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_LO_DLY_SHIFT (16U)
79915 /*! PRE_LO_DLY - Delay before turn on the high-fanout power switch, locked by LOCK_CFG field */
79916 #define SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_LO_DLY_SHIFT)) & SRC_MIF_S28SPREGH_PSWA_MIF_DLY_ARR_HF_PRE_LO_DLY_MASK)
79917 /*! @} */
79918 
79919 
79920 /*!
79921  * @}
79922  */ /* end of group SRC_MIF_S28SPREGH_PSWA_Register_Masks */
79923 
79924 
79925 /* SRC_MIF_S28SPREGH_PSWA - Peripheral instance base addresses */
79926 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
79927   /** Peripheral CM7PLATFORM_TCM base address */
79928   #define CM7PLATFORM_TCM_BASE                     (0x54464C00u)
79929   /** Peripheral CM7PLATFORM_TCM base address */
79930   #define CM7PLATFORM_TCM_BASE_NS                  (0x44464C00u)
79931   /** Peripheral CM7PLATFORM_TCM base pointer */
79932   #define CM7PLATFORM_TCM                          ((SRC_MIF_S28SPREGH_PSWA_Type *)CM7PLATFORM_TCM_BASE)
79933   /** Peripheral CM7PLATFORM_TCM base pointer */
79934   #define CM7PLATFORM_TCM_NS                       ((SRC_MIF_S28SPREGH_PSWA_Type *)CM7PLATFORM_TCM_BASE_NS)
79935   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base addresses */
79936   #define SRC_MIF_S28SPREGH_PSWA_BASE_ADDRS        { CM7PLATFORM_TCM_BASE }
79937   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base pointers */
79938   #define SRC_MIF_S28SPREGH_PSWA_BASE_PTRS         { CM7PLATFORM_TCM }
79939   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base addresses */
79940   #define SRC_MIF_S28SPREGH_PSWA_BASE_ADDRS_NS     { CM7PLATFORM_TCM_BASE_NS }
79941   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base pointers */
79942   #define SRC_MIF_S28SPREGH_PSWA_BASE_PTRS_NS      { CM7PLATFORM_TCM_NS }
79943 #else
79944   /** Peripheral CM7PLATFORM_TCM base address */
79945   #define CM7PLATFORM_TCM_BASE                     (0x44464C00u)
79946   /** Peripheral CM7PLATFORM_TCM base pointer */
79947   #define CM7PLATFORM_TCM                          ((SRC_MIF_S28SPREGH_PSWA_Type *)CM7PLATFORM_TCM_BASE)
79948   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base addresses */
79949   #define SRC_MIF_S28SPREGH_PSWA_BASE_ADDRS        { CM7PLATFORM_TCM_BASE }
79950   /** Array initializer of SRC_MIF_S28SPREGH_PSWA peripheral base pointers */
79951   #define SRC_MIF_S28SPREGH_PSWA_BASE_PTRS         { CM7PLATFORM_TCM }
79952 #endif
79953 
79954 /*!
79955  * @}
79956  */ /* end of group SRC_MIF_S28SPREGH_PSWA_Peripheral_Access_Layer */
79957 
79958 
79959 /* ----------------------------------------------------------------------------
79960    -- SRC_MIX_SLICE Peripheral Access Layer
79961    ---------------------------------------------------------------------------- */
79962 
79963 /*!
79964  * @addtogroup SRC_MIX_SLICE_Peripheral_Access_Layer SRC_MIX_SLICE Peripheral Access Layer
79965  * @{
79966  */
79967 
79968 /** SRC_MIX_SLICE - Register Layout Typedef */
79969 typedef struct {
79970        uint8_t RESERVED_0[4];
79971   __IO uint32_t AUTHEN_CTRL;                       /**< Authentication Control, offset: 0x4 */
79972        uint8_t RESERVED_1[8];
79973   __IO uint32_t SLICE_SW_CTRL;                     /**< SLICE Software Control, offset: 0x10 */
79974   __I  uint32_t FUNC_STAT;                         /**< Function Status, offset: 0x14 */
79975        uint8_t RESERVED_2[8];
79976   __I  uint32_t UPI_STAT_0;                        /**< UPI Status 0, offset: 0x20 */
79977   __I  uint32_t UPI_STAT_1;                        /**< UPI Status 1, offset: 0x24 */
79978        uint8_t RESERVED_3[8];
79979   __IO uint32_t LPM_SETTING_0;                     /**< Low Power Mode Setting 0, offset: 0x30 */
79980   __IO uint32_t LPM_SETTING_1;                     /**< Low Power Mode Setting 1, offset: 0x34 */
79981   __IO uint32_t LPM_SETTING_2;                     /**< Low Power Mode Setting 2, offset: 0x38 */
79982        uint8_t RESERVED_4[4];
79983   __IO uint32_t EDGELOCK_HDSK_CTRL;                /**< Edgelock Handshake Control, offset: 0x40 */
79984   __I  uint32_t EDGELOCK_HDSK_STAT;                /**< Edgelock Handshake Status, offset: 0x44 */
79985   __IO uint32_t EDGELOCK_HDSK_CNT_CFG;             /**< Edgelock Handshake Counter Config, offset: 0x48 */
79986   __I  uint32_t EDGELOCK_HDSK_CNT_STAT;            /**< Edgelock Handshake Counter Status, offset: 0x4C */
79987   __IO uint32_t ISO_DLY_PRE;                       /**< ISO Delay Pre control, offset: 0x50 */
79988   __IO uint32_t PSW_DLY_PRE_HF;                    /**< PSW Delay Pre for HF, offset: 0x54 */
79989   __IO uint32_t PSW_DLY_PRE_LF;                    /**< PSW Delay Pre for LF, offset: 0x58 */
79990   __IO uint32_t PSW_CTRL;                          /**< PSW Control, offset: 0x5C */
79991   __I  uint32_t PSW_STAT;                          /**< PSW Status, offset: 0x60 */
79992   __IO uint32_t PSW_CNT_CFG_HF;                    /**< PSW Counter Config for HF, offset: 0x64 */
79993   __I  uint32_t PSW_CNT_STAT_HF;                   /**< PSW Counter Status for HF, offset: 0x68 */
79994   __IO uint32_t PSW_CNT_CFG_LF;                    /**< PSW Counter Config for LF, offset: 0x6C */
79995   __I  uint32_t PSW_CNT_STAT_LF;                   /**< PSW Counter Status for LF, offset: 0x70 */
79996        uint8_t RESERVED_5[12];
79997   __IO uint32_t MLPL_TRIG_CTRL;                    /**< Memory Low Power Level Trigger Control, offset: 0x80 */
79998   __IO uint32_t MLPL_CFG;                          /**< Memory Low Power Level Config, offset: 0x84 */
79999   __I  uint32_t MLPL_STAT;                         /**< Memory Low Power Level Status, offset: 0x88 */
80000 } SRC_MIX_SLICE_Type;
80001 
80002 /* ----------------------------------------------------------------------------
80003    -- SRC_MIX_SLICE Register Masks
80004    ---------------------------------------------------------------------------- */
80005 
80006 /*!
80007  * @addtogroup SRC_MIX_SLICE_Register_Masks SRC_MIX_SLICE Register Masks
80008  * @{
80009  */
80010 
80011 /*! @name AUTHEN_CTRL - Authentication Control */
80012 /*! @{ */
80013 
80014 #define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK  (0x4U)
80015 #define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT (2U)
80016 /*! LPM_MODE - HW low power mode
80017  *  0b0..Low power mode controlled by software. SLICE_SW_CTRL register can be updated. LPM_SETTING_0 register cannot be updated.
80018  *  0b1..Low power mode controlled by GPC. SLICE_SW_CTRL register cannot be updated. LPM_SETTING_0 register can be updated.
80019  */
80020 #define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE(x)    (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK)
80021 
80022 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK  (0x80U)
80023 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U)
80024 /*! LOCK_CFG - Configuration lock
80025  *  0b0..Registers are not locked.
80026  *  0b1..Fields and registers in the list are locked.
80027  */
80028 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG(x)    (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK)
80029 
80030 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK   (0x100U)
80031 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT  (8U)
80032 /*! TZ_USER - Allow user mode write
80033  *  0b0..The MIX SLICE registers and its MEM Type I/II registers can only be written in privilege mode.
80034  *  0b1..The MIX SLICE registers and its MEM Type I/II registers can be written either in privilege mode or user mode.
80035  */
80036 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK)
80037 
80038 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK     (0x200U)
80039 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT    (9U)
80040 /*! TZ_NS - Allow non-secure mode access
80041  *  0b0..The MIX SLICE registers and its MEM Type I/II registers can only be written in secure mode.
80042  *  0b1..The MIX SLICE registers and its MEM Type I/II registers can be written either in secure mode or non-secure mode.
80043  */
80044 #define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK)
80045 
80046 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK   (0x800U)
80047 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT  (11U)
80048 /*! LOCK_TZ - Lock TZ_NS and TZ_USER
80049  *  0b0..TZ_NS and TZ_USER value can be changed.
80050  *  0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed.
80051  */
80052 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK)
80053 
80054 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U)
80055 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U)
80056 /*! LOCK_LIST - White list lock
80057  *  0b0..WHITE_LIST value can be changed.
80058  *  0b1..LOCK_LIST and WHITE_LIST value cannot be changed.
80059  */
80060 #define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK)
80061 
80062 #define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U)
80063 #define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U)
80064 /*! WHITE_LIST - Domain ID white list
80065  *  0b0000000000000001..Core with domain ID=0 can write SRC MIX SLICE registers.
80066  *  0b0000000000000010..Core with domain ID=1 can write SRC MIX SLICE registers.
80067  *  0b0000000000000100..Core with domain ID=2 can write SRC MIX SLICE registers.
80068  *  0b0000000000001000..Core with domain ID=3 can write SRC MIX SLICE registers.
80069  *  0b0000000000010000..Core with domain ID=4 can write SRC MIX SLICE registers.
80070  *  0b0000000000100000..Core with domain ID=5 can write SRC MIX SLICE registers.
80071  *  0b0000000001000000..Core with domain ID=6 can write SRC MIX SLICE registers.
80072  *  0b0000000010000000..Core with domain ID=7 can write SRC MIX SLICE registers.
80073  *  0b0000000100000000..Core with domain ID=8 can write SRC MIX SLICE registers.
80074  *  0b0000001000000000..Core with domain ID=9 can write SRC MIX SLICE registers.
80075  *  0b0000010000000000..Core with domain ID=10 can write SRC MIX SLICE registers.
80076  *  0b0000100000000000..Core with domain ID=11 can write SRC MIX SLICE registers.
80077  *  0b0001000000000000..Core with domain ID=12 can write SRC MIX SLICE registers.
80078  *  0b0010000000000000..Core with domain ID=13 can write SRC MIX SLICE registers.
80079  *  0b0100000000000000..Core with domain ID=14 can write SRC MIX SLICE registers.
80080  *  0b1000000000000000..Core with domain ID=15 can write SRC MIX SLICE registers.
80081  */
80082 #define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK)
80083 /*! @} */
80084 
80085 /*! @name SLICE_SW_CTRL - SLICE Software Control */
80086 /*! @{ */
80087 
80088 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_OFF_SOFT_MASK (0x1U)
80089 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_OFF_SOFT_SHIFT (0U)
80090 /*! PSW_OFF_SOFT - Software power off control. This field can only be updated while LPM_MODE=0.
80091  *  0b0..Clear to 0 to trigger power switch on
80092  *  0b1..Write 1 to trigger power switch off
80093  */
80094 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_OFF_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_OFF_SOFT_MASK)
80095 
80096 #define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK (0x4U)
80097 #define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT (2U)
80098 /*! RST_CTRL_SOFT - Software reset control. This field can only be updated while LPM_MODE=0.
80099  *  0b0..Clear to 0 to trigger reset deassert
80100  *  0b1..Write 1 to trigger reset assert
80101  */
80102 #define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK)
80103 
80104 #define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_ON_SOFT_MASK (0x10U)
80105 #define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_ON_SOFT_SHIFT (4U)
80106 /*! ISO_ON_SOFT - Software isolation on control. This field can only be updated while LPM_MODE=0.
80107  *  0b0..Clear to 0 to trigger isolation off
80108  *  0b1..Write 1 to trigger isolation on
80109  */
80110 #define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_ON_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_ON_SOFT_MASK)
80111 
80112 #define SRC_MIX_SLICE_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT_MASK (0x40U)
80113 #define SRC_MIX_SLICE_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT_SHIFT (6U)
80114 /*! EDGELOCK_HDSK_SOFT - Software Edgelock handshake control. This field can only be updated while LPM_MODE=0.
80115  *  0b0..Clear to 0 to trigger Edgelock handshake for power on.
80116  *  0b1..Write to 1 to trigger Edgelock handshake for power off.
80117  */
80118 #define SRC_MIX_SLICE_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT_MASK)
80119 
80120 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK (0x80000000U)
80121 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT (31U)
80122 /*! PDN_SOFT - By flow sequence, Software power down sequence includes Edgelock handshake for power
80123  *    down, isolation on, reset assert, power off; Software power up sequence includes power up,
80124  *    reset deassert, isolation off, Edgelock handshake for power up. This bit can only be updated
80125  *    while LPM_MODE=0.
80126  *  0b0..Clear to 0 to trigger a power up sequence.
80127  *  0b1..Write 1 to trigger a power down sequence.
80128  */
80129 #define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK)
80130 /*! @} */
80131 
80132 /*! @name FUNC_STAT - Function Status */
80133 /*! @{ */
80134 
80135 #define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK    (0x1U)
80136 #define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT   (0U)
80137 /*! PSW_STAT - power switch status
80138  *  0b0..power switch on
80139  *  0b1..power switch off
80140  */
80141 #define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT(x)      (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK)
80142 
80143 #define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK    (0x4U)
80144 #define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT   (2U)
80145 /*! RST_STAT - reset status
80146  *  0b0..reset asserted
80147  *  0b1..reset released
80148  */
80149 #define SRC_MIX_SLICE_FUNC_STAT_RST_STAT(x)      (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK)
80150 
80151 #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK    (0x10U)
80152 #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT   (4U)
80153 /*! ISO_STAT - isolation status
80154  *  0b0..isolation off
80155  *  0b1..isolation on
80156  */
80157 #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT(x)      (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK)
80158 
80159 #define SRC_MIX_SLICE_FUNC_STAT_EDGELOCK_HDSK_STAT_MASK (0x40U)
80160 #define SRC_MIX_SLICE_FUNC_STAT_EDGELOCK_HDSK_STAT_SHIFT (6U)
80161 /*! EDGELOCK_HDSK_STAT - Edgelock handshake status
80162  *  0b0..no effect or power up handshake with Edgelock done
80163  *  0b1..power down handshake with Edgelock done
80164  */
80165 #define SRC_MIX_SLICE_FUNC_STAT_EDGELOCK_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_EDGELOCK_HDSK_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_EDGELOCK_HDSK_STAT_MASK)
80166 /*! @} */
80167 
80168 /*! @name UPI_STAT_0 - UPI Status 0 */
80169 /*! @{ */
80170 
80171 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK (0xFFFFU)
80172 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT (0U)
80173 /*! UPI_ISO_REQUEST - CPU mode transfer to trigger isolation change request of 16 domains */
80174 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK)
80175 
80176 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_EDGELOCK_HDSK_REQUEST_MASK (0xFFFF0000U)
80177 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_EDGELOCK_HDSK_REQUEST_SHIFT (16U)
80178 /*! UPI_EDGELOCK_HDSK_REQUEST - CPU mode transfer to trigger Edgelock handshake request of 16 domains */
80179 #define SRC_MIX_SLICE_UPI_STAT_0_UPI_EDGELOCK_HDSK_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_EDGELOCK_HDSK_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_EDGELOCK_HDSK_REQUEST_MASK)
80180 /*! @} */
80181 
80182 /*! @name UPI_STAT_1 - UPI Status 1 */
80183 /*! @{ */
80184 
80185 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_POWER_REQUEST_MASK (0xFFFFU)
80186 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_POWER_REQUEST_SHIFT (0U)
80187 /*! UPI_POWER_REQUEST - CPU mode transfer to trigger power switch request of 16 domains */
80188 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_POWER_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_POWER_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_POWER_REQUEST_MASK)
80189 
80190 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK (0xFFFF0000U)
80191 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT (16U)
80192 /*! UPI_RESET_REQUEST - CPU mode transfer to trigger reset change request of 16 domains */
80193 #define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK)
80194 /*! @} */
80195 
80196 /*! @name LPM_SETTING_0 - Low Power Mode Setting 0 */
80197 /*! @{ */
80198 
80199 #define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK (0x7U)
80200 #define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT (0U)
80201 /*! LPM_SETTING_CD - LPM setting of current domain */
80202 #define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK)
80203 /*! @} */
80204 
80205 /*! @name LPM_SETTING_1 - Low Power Mode Setting 1 */
80206 /*! @{ */
80207 
80208 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK (0x7U)
80209 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT (0U)
80210 /*! LPM_SETTING_D0 - LPM setting of domain 0
80211  *  0b000..Not used. Do not write this value.
80212  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80213  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80214  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80215  *  0b100-0b111..power always on
80216  */
80217 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK)
80218 
80219 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK (0x70U)
80220 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT (4U)
80221 /*! LPM_SETTING_D1 - LPM setting of domain 1
80222  *  0b000..Not used. Do not write this value.
80223  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80224  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80225  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80226  *  0b100-0b111..power always on
80227  */
80228 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK)
80229 
80230 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK (0x700U)
80231 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT (8U)
80232 /*! LPM_SETTING_D2 - LPM setting of domain 2
80233  *  0b000..Not used. Do not write this value.
80234  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80235  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80236  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80237  *  0b100-0b111..power always on
80238  */
80239 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK)
80240 
80241 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK (0x7000U)
80242 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT (12U)
80243 /*! LPM_SETTING_D3 - LPM setting of domain 3
80244  *  0b000..Not used. Do not write this value.
80245  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80246  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80247  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80248  *  0b100-0b111..power always on
80249  */
80250 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK)
80251 
80252 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK (0x70000U)
80253 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT (16U)
80254 /*! LPM_SETTING_D4 - LPM setting of domain 4
80255  *  0b000..Not used. Do not write this value.
80256  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80257  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80258  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80259  *  0b100-0b111..power always on
80260  */
80261 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK)
80262 
80263 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK (0x700000U)
80264 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT (20U)
80265 /*! LPM_SETTING_D5 - LPM setting of domain 5
80266  *  0b000..Not used. Do not write this value.
80267  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80268  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80269  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80270  *  0b100-0b111..power always on
80271  */
80272 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK)
80273 
80274 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK (0x7000000U)
80275 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT (24U)
80276 /*! LPM_SETTING_D6 - LPM setting of domain 6
80277  *  0b000..Not used. Do not write this value.
80278  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80279  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80280  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80281  *  0b100-0b111..power always on
80282  */
80283 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK)
80284 
80285 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK (0x70000000U)
80286 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT (28U)
80287 /*! LPM_SETTING_D7 - LPM setting of domain 7
80288  *  0b000..Not used. Do not write this value.
80289  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80290  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80291  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80292  *  0b100-0b111..power always on
80293  */
80294 #define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK)
80295 /*! @} */
80296 
80297 /*! @name LPM_SETTING_2 - Low Power Mode Setting 2 */
80298 /*! @{ */
80299 
80300 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK (0x7U)
80301 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT (0U)
80302 /*! LPM_SETTING_D8 - LPM setting of domain 8
80303  *  0b000..Not used. Do not write this value.
80304  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80305  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80306  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80307  *  0b100-0b111..power always on
80308  */
80309 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK)
80310 
80311 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK (0x70U)
80312 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT (4U)
80313 /*! LPM_SETTING_D9 - LPM setting of domain 9
80314  *  0b000..Not used. Do not write this value.
80315  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80316  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80317  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80318  *  0b100-0b111..power always on
80319  */
80320 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK)
80321 
80322 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK (0x700U)
80323 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT (8U)
80324 /*! LPM_SETTING_D10 - LPM setting of domain 10
80325  *  0b000..Not used. Do not write this value.
80326  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80327  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80328  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80329  *  0b100-0b111..power always on
80330  */
80331 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK)
80332 
80333 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK (0x7000U)
80334 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT (12U)
80335 /*! LPM_SETTING_D11 - LPM setting of domain 11
80336  *  0b000..Not used. Do not write this value.
80337  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80338  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80339  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80340  *  0b100-0b111..power always on
80341  */
80342 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK)
80343 
80344 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK (0x70000U)
80345 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT (16U)
80346 /*! LPM_SETTING_D12 - LPM setting of domain 12
80347  *  0b000..Not used. Do not write this value.
80348  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80349  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80350  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80351  *  0b100-0b111..power always on
80352  */
80353 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK)
80354 
80355 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK (0x700000U)
80356 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT (20U)
80357 /*! LPM_SETTING_D13 - LPM setting of domain 13
80358  *  0b000..Not used. Do not write this value.
80359  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80360  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80361  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80362  *  0b100-0b111..power always on
80363  */
80364 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK)
80365 
80366 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK (0x7000000U)
80367 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT (24U)
80368 /*! LPM_SETTING_D14 - LPM setting of domain 14
80369  *  0b000..Not used. Do not write this value.
80370  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80371  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80372  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80373  *  0b100-0b111..power always on
80374  */
80375 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK)
80376 
80377 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK (0x70000000U)
80378 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT (28U)
80379 /*! LPM_SETTING_D15 - LPM setting of domain 15
80380  *  0b000..Not used. Do not write this value.
80381  *  0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND
80382  *  0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND
80383  *  0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND
80384  *  0b100-0b111..power always on
80385  */
80386 #define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK)
80387 /*! @} */
80388 
80389 /*! @name EDGELOCK_HDSK_CTRL - Edgelock Handshake Control */
80390 /*! @{ */
80391 
80392 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_PON_CNT_MODE_MASK (0xC000U)
80393 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_PON_CNT_MODE_SHIFT (14U)
80394 /*! PON_CNT_MODE - Configures the acknowledge counter for power up working mode, locked by LOCK_CFG field
80395  *  0b00..Not use counter, raise Edgelock handshake done to GPC once get Edgelock ack
80396  *  0b01..Delay after receiving Edgelock ack, delay cycle number is PON_CNT_CFG
80397  *  0b10..Ignore Edgelock ack, raise Edgelock handshake done to GPC when counting to PON_CNT_CFG value
80398  *  0b11..Time out mode, raise Edgelock handshake done to GPC when either Edgelock ack received or counting to PON_CNT_CFG value
80399  */
80400 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_PON_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_PON_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_PON_CNT_MODE_MASK)
80401 
80402 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_POFF_CNT_MODE_MASK (0xC0000000U)
80403 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_POFF_CNT_MODE_SHIFT (30U)
80404 /*! POFF_CNT_MODE - Configures the acknowledge counter for power down working mode, locked by LOCK_CFG field
80405  *  0b00..Not use counter, raise Edgelock handshake done to GPC once get Edgelock ack
80406  *  0b01..Delay after receiving Edgelock ack, delay cycle number is POFF_CNT_CFG
80407  *  0b10..Ignore Edgelock ack, raise Edgelock handshake done to GPC when counting to POFF_CNT_CFG value
80408  *  0b11..Time out mode, raise Edgelock handshake done to GPC when either Edgelock ack received or counting to POFF_CNT_CFG value
80409  */
80410 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_POFF_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_POFF_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CTRL_POFF_CNT_MODE_MASK)
80411 /*! @} */
80412 
80413 /*! @name EDGELOCK_HDSK_STAT - Edgelock Handshake Status */
80414 /*! @{ */
80415 
80416 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_ACK_MASK (0x1U)
80417 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_ACK_SHIFT (0U)
80418 /*! PON_ACK - Indicates this mix power up sequence has accepted Edgelock ack
80419  *  0b0..Does not get Edgelock ack for power up.
80420  *  0b1..Gets Edgelock ack for power up.
80421  */
80422 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_ACK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_ACK_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_ACK_MASK)
80423 
80424 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_BUSY_MASK (0x2U)
80425 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_BUSY_SHIFT (1U)
80426 /*! PON_BUSY - Busy requesting Edgelock handshake for power up
80427  *  0b0..Does not send Edgelock handshake for power up.
80428  *  0b1..Sends Edgelock handshake for power up.
80429  */
80430 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_BUSY_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_PON_BUSY_MASK)
80431 
80432 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_ACK_MASK (0x10000U)
80433 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_ACK_SHIFT (16U)
80434 /*! POFF_ACK - Indicates this mix power down sequence has accepted Edgelock ack
80435  *  0b0..Does not get Edgelock ack for power down.
80436  *  0b1..Gets Edgelock ack for power down.
80437  */
80438 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_ACK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_ACK_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_ACK_MASK)
80439 
80440 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_BUSY_MASK (0x20000U)
80441 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_BUSY_SHIFT (17U)
80442 /*! POFF_BUSY - Busy requesting Edgelock handshake for power down
80443  *  0b1..Sends Edgelock handshake for power down.
80444  *  0b0..Does not send Edgelock handshake for power down.
80445  */
80446 #define SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_BUSY_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_STAT_POFF_BUSY_MASK)
80447 /*! @} */
80448 
80449 /*! @name EDGELOCK_HDSK_CNT_CFG - Edgelock Handshake Counter Config */
80450 /*! @{ */
80451 
80452 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_PON_CNT_CFG_MASK (0xFFFFU)
80453 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_PON_CNT_CFG_SHIFT (0U)
80454 /*! PON_CNT_CFG - Edgelock handshake ack count for power up config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80455 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_PON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_PON_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_PON_CNT_CFG_MASK)
80456 
80457 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_POFF_CNT_CFG_MASK (0xFFFF0000U)
80458 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_POFF_CNT_CFG_SHIFT (16U)
80459 /*! POFF_CNT_CFG - Edgelock handshake ack count for power down config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80460 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_POFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_POFF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_CFG_POFF_CNT_CFG_MASK)
80461 /*! @} */
80462 
80463 /*! @name EDGELOCK_HDSK_CNT_STAT - Edgelock Handshake Counter Status */
80464 /*! @{ */
80465 
80466 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_PON_CNT_MASK (0xFFFFU)
80467 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_PON_CNT_SHIFT (0U)
80468 /*! PON_CNT - Edgelock handshake for power up acknowledge count, record the delay from stat change to acknowledge received */
80469 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_PON_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_PON_CNT_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_PON_CNT_MASK)
80470 
80471 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_POFF_CNT_MASK (0xFFFF0000U)
80472 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_POFF_CNT_SHIFT (16U)
80473 /*! POFF_CNT - Edgelock handshake for power down acknowledge count, record the delay from stat change to acknowledge received */
80474 #define SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_POFF_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_POFF_CNT_SHIFT)) & SRC_MIX_SLICE_EDGELOCK_HDSK_CNT_STAT_POFF_CNT_MASK)
80475 /*! @} */
80476 
80477 /*! @name ISO_DLY_PRE - ISO Delay Pre control */
80478 /*! @{ */
80479 
80480 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_OFF_CNT_MASK (0xFFFFU)
80481 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_OFF_CNT_SHIFT (0U)
80482 /*! ISO_OFF_CNT - Delay from receiving iso off request to isolation disable, locked by LOCK_CFG field */
80483 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_OFF_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_DLY_PRE_ISO_OFF_CNT_SHIFT)) & SRC_MIX_SLICE_ISO_DLY_PRE_ISO_OFF_CNT_MASK)
80484 
80485 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_ON_CNT_MASK (0xFFFF0000U)
80486 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_ON_CNT_SHIFT (16U)
80487 /*! ISO_ON_CNT - Delay from receiving iso_on request to isolation enable, locked by LOCK_CFG field */
80488 #define SRC_MIX_SLICE_ISO_DLY_PRE_ISO_ON_CNT(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_DLY_PRE_ISO_ON_CNT_SHIFT)) & SRC_MIX_SLICE_ISO_DLY_PRE_ISO_ON_CNT_MASK)
80489 /*! @} */
80490 
80491 /*! @name PSW_DLY_PRE_HF - PSW Delay Pre for HF */
80492 /*! @{ */
80493 
80494 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_ON_MASK (0xFFFFU)
80495 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_ON_SHIFT (0U)
80496 /*! PSW_ON - Delay from receiving power on hf request to power switch turn on, locked by LOCK_CFG field */
80497 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_ON(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_ON_SHIFT)) & SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_ON_MASK)
80498 
80499 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_OFF_MASK (0xFFFF0000U)
80500 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_OFF_SHIFT (16U)
80501 /*! PSW_OFF - Delay from receiving power off hf request to power switch shut off, locked by LOCK_CFG field */
80502 #define SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_OFF(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_OFF_SHIFT)) & SRC_MIX_SLICE_PSW_DLY_PRE_HF_PSW_OFF_MASK)
80503 /*! @} */
80504 
80505 /*! @name PSW_DLY_PRE_LF - PSW Delay Pre for LF */
80506 /*! @{ */
80507 
80508 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_ON_MASK (0xFFFFU)
80509 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_ON_SHIFT (0U)
80510 /*! PSW_ON - Delay from receiving power on lf request to power switch turn on, locked by LOCK_CFG field */
80511 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_ON(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_ON_SHIFT)) & SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_ON_MASK)
80512 
80513 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_OFF_MASK (0xFFFF0000U)
80514 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_OFF_SHIFT (16U)
80515 /*! PSW_OFF - Delay from receiving power off lf request to power switch shut off, locked by LOCK_CFG field */
80516 #define SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_OFF(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_OFF_SHIFT)) & SRC_MIX_SLICE_PSW_DLY_PRE_LF_PSW_OFF_MASK)
80517 /*! @} */
80518 
80519 /*! @name PSW_CTRL - PSW Control */
80520 /*! @{ */
80521 
80522 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_LF_MASK (0x1U)
80523 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_LF_SHIFT (0U)
80524 /*! ACK_INVERT_LF - Acknowledge for low fanout value is inverted from power switch control, locked by LOCK_CFG field
80525  *  0b0..Use original signal as ack
80526  *  0b1..Use inverted original signal as ack
80527  */
80528 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_LF(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_LF_SHIFT)) & SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_LF_MASK)
80529 
80530 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_HF_MASK (0x2U)
80531 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_HF_SHIFT (1U)
80532 /*! ACK_INVERT_HF - Acknowledge for high fanout value is inverted from power switch control, locked by LOCK_CFG field
80533  *  0b0..Use original signal as ack
80534  *  0b1..Use inverted original signal as ack
80535  */
80536 #define SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_HF(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_HF_SHIFT)) & SRC_MIX_SLICE_PSW_CTRL_ACK_INVERT_HF_MASK)
80537 
80538 #define SRC_MIX_SLICE_PSW_CTRL_PON_CNT_MODE_MASK (0xC000U)
80539 #define SRC_MIX_SLICE_PSW_CTRL_PON_CNT_MODE_SHIFT (14U)
80540 /*! PON_CNT_MODE - Configure the acknowledge counter for power up working mode, locked by LOCK_CFG field
80541  *  0b00..Not use counter, raise power_on/off done to GPC once get psw ack
80542  *  0b01..Delay after receiving psw ack, delay cycle number is PON_CNT_CFG
80543  *  0b10..Ignore psw ack, raise power_on/off done to GPC when counting to PON_CNT_CFG value
80544  *  0b11..Time out mode, raise power_on/off done to GPC when either psw ack received or counting to PON_CNT_CFG value
80545  */
80546 #define SRC_MIX_SLICE_PSW_CTRL_PON_CNT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CTRL_PON_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_PSW_CTRL_PON_CNT_MODE_MASK)
80547 
80548 #define SRC_MIX_SLICE_PSW_CTRL_POFF_CNT_MODE_MASK (0xC0000000U)
80549 #define SRC_MIX_SLICE_PSW_CTRL_POFF_CNT_MODE_SHIFT (30U)
80550 /*! POFF_CNT_MODE - Configures the acknowledge counter for power down working mode, locked by LOCK_CFG field
80551  *  0b00..Not use counter, raise power_on/off done to GPC once get psw ack
80552  *  0b01..Delay after receiving psw ack, delay cycle number is POFF_CNT_CFG. When POFF_CNT_CFG value in HF/LF is different, bigger value will be used.
80553  *  0b10..Ignore psw ack, raise power_on/off done to GPC when counting to POFF_CNT_CFG value. When POFF_CNT_CFG
80554  *        value in HF/LF is different, bigger value will be used.
80555  *  0b11..Time out mode, raise power_on/off done to GPC when either psw ack received or counting to POFF_CNT_CFG
80556  *        value. When POFF_CNT_CFG value in HF/LF is different, bigger value will be used.
80557  */
80558 #define SRC_MIX_SLICE_PSW_CTRL_POFF_CNT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CTRL_POFF_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_PSW_CTRL_POFF_CNT_MODE_MASK)
80559 /*! @} */
80560 
80561 /*! @name PSW_STAT - PSW Status */
80562 /*! @{ */
80563 
80564 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_LF_MASK  (0x1U)
80565 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_LF_SHIFT (0U)
80566 /*! ACK_STAT_LF - Power switch acknowledge status for low fanout
80567  *  0b0..Does not get ack for power switch
80568  *  0b1..Gets ack for power switch
80569  */
80570 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_LF(x)    (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_STAT_ACK_STAT_LF_SHIFT)) & SRC_MIX_SLICE_PSW_STAT_ACK_STAT_LF_MASK)
80571 
80572 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_HF_MASK  (0x2U)
80573 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_HF_SHIFT (1U)
80574 /*! ACK_STAT_HF - Power switch acknowledge status for high fanout
80575  *  0b0..Does not get ack for power switch
80576  *  0b1..Gets ack for power switch
80577  */
80578 #define SRC_MIX_SLICE_PSW_STAT_ACK_STAT_HF(x)    (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_STAT_ACK_STAT_HF_SHIFT)) & SRC_MIX_SLICE_PSW_STAT_ACK_STAT_HF_MASK)
80579 /*! @} */
80580 
80581 /*! @name PSW_CNT_CFG_HF - PSW Counter Config for HF */
80582 /*! @{ */
80583 
80584 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_PON_CNT_CFG_MASK (0xFFFFU)
80585 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_PON_CNT_CFG_SHIFT (0U)
80586 /*! PON_CNT_CFG - PUP HF Count config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80587 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_PON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_CFG_HF_PON_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_CFG_HF_PON_CNT_CFG_MASK)
80588 
80589 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_POFF_CNT_CFG_MASK (0xFFFF0000U)
80590 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_POFF_CNT_CFG_SHIFT (16U)
80591 /*! POFF_CNT_CFG - PDN HF Count config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80592 #define SRC_MIX_SLICE_PSW_CNT_CFG_HF_POFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_CFG_HF_POFF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_CFG_HF_POFF_CNT_CFG_MASK)
80593 /*! @} */
80594 
80595 /*! @name PSW_CNT_STAT_HF - PSW Counter Status for HF */
80596 /*! @{ */
80597 
80598 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_PON_CNT_MASK (0xFFFFU)
80599 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_PON_CNT_SHIFT (0U)
80600 /*! PON_CNT - HF PSW acknowledge count for power up, record the delay from power switch change to acknowledge received */
80601 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_PON_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_STAT_HF_PON_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_STAT_HF_PON_CNT_MASK)
80602 
80603 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_POFF_CNT_MASK (0xFFFF0000U)
80604 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_POFF_CNT_SHIFT (16U)
80605 /*! POFF_CNT - HF PSW acknowledge count for power down, record the delay from power switch change to acknowledge received */
80606 #define SRC_MIX_SLICE_PSW_CNT_STAT_HF_POFF_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_STAT_HF_POFF_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_STAT_HF_POFF_CNT_MASK)
80607 /*! @} */
80608 
80609 /*! @name PSW_CNT_CFG_LF - PSW Counter Config for LF */
80610 /*! @{ */
80611 
80612 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_PON_CNT_CFG_MASK (0xFFFFU)
80613 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_PON_CNT_CFG_SHIFT (0U)
80614 /*! PON_CNT_CFG - PUP LF Count config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80615 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_PON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_CFG_LF_PON_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_CFG_LF_PON_CNT_CFG_MASK)
80616 
80617 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_POFF_CNT_CFG_MASK (0xFFFF0000U)
80618 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_POFF_CNT_CFG_SHIFT (16U)
80619 /*! POFF_CNT_CFG - PDN LF Count config: usage depends on CNT_MODE, locked by LOCK_CFG field */
80620 #define SRC_MIX_SLICE_PSW_CNT_CFG_LF_POFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_CFG_LF_POFF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_CFG_LF_POFF_CNT_CFG_MASK)
80621 /*! @} */
80622 
80623 /*! @name PSW_CNT_STAT_LF - PSW Counter Status for LF */
80624 /*! @{ */
80625 
80626 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_PON_CNT_MASK (0xFFFFU)
80627 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_PON_CNT_SHIFT (0U)
80628 /*! PON_CNT - LF PSW acknowledge count for power up, record the delay from power switch change to acknowledge received */
80629 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_PON_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_STAT_LF_PON_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_STAT_LF_PON_CNT_MASK)
80630 
80631 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_POFF_CNT_MASK (0xFFFF0000U)
80632 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_POFF_CNT_SHIFT (16U)
80633 /*! POFF_CNT - LF PSW acknowledge count for power down, record the delay from power switch change to acknowledge received */
80634 #define SRC_MIX_SLICE_PSW_CNT_STAT_LF_POFF_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_CNT_STAT_LF_POFF_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_CNT_STAT_LF_POFF_CNT_MASK)
80635 /*! @} */
80636 
80637 /*! @name MLPL_TRIG_CTRL - Memory Low Power Level Trigger Control */
80638 /*! @{ */
80639 
80640 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_LMEM_MLPL_TRANS_MASK (0x10000U)
80641 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_LMEM_MLPL_TRANS_SHIFT (16U)
80642 /*! SW_TRIG_LMEM_MLPL_TRANS - Software trigger local memory (MEM Type I with PSW or MEM Type I
80643  *    except for CM33PLATFORM_CACHE or CM7PLATFORM_CACHE, depending on which MIX of the register) update
80644  *    low power level
80645  *  0b0..No trigger
80646  *  0b1..Software trigger local memory update low power level
80647  */
80648 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_LMEM_MLPL_TRANS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_LMEM_MLPL_TRANS_SHIFT)) & SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_LMEM_MLPL_TRANS_MASK)
80649 
80650 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_CACHE_MLPL_TRANS_MASK (0x20000U)
80651 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_CACHE_MLPL_TRANS_SHIFT (17U)
80652 /*! SW_TRIG_CACHE_MLPL_TRANS - Software trigger CACHE memory (MEM Type II or MEM Type I's
80653  *    CM33PLATFORM_CACHE or CM7PLATFORM_CACHE, depending on which MIX of the register) update low power level
80654  *  0b0..No trigger
80655  *  0b1..Software trigger CACHE memory update low power level
80656  */
80657 #define SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_CACHE_MLPL_TRANS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_CACHE_MLPL_TRANS_SHIFT)) & SRC_MIX_SLICE_MLPL_TRIG_CTRL_SW_TRIG_CACHE_MLPL_TRANS_MASK)
80658 /*! @} */
80659 
80660 /*! @name MLPL_CFG - Memory Low Power Level Config */
80661 /*! @{ */
80662 
80663 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_LMEM_MASK (0x7U)
80664 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_LMEM_SHIFT (0U)
80665 /*! MLPL_HW_PDN_LMEM - Memory(MEM Type I with PSW or MEM Type I except for CM33PLATFORM_CACHE or
80666  *    CM7PLATFORM_CACHE, depending on which MIX of the register) low power level when hw power down
80667  */
80668 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_LMEM(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_LMEM_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_LMEM_MASK)
80669 
80670 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_LMEM_MASK (0x70U)
80671 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_LMEM_SHIFT (4U)
80672 /*! MLPL_HW_PUP_LMEM - Memory(MEM Type I with PSW or MEM Type I except for CM33PLATFORM_CACHE or
80673  *    CM7PLATFORM_CACHE, depending on which MIX of the register) low power level when hw power up
80674  */
80675 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_LMEM(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_LMEM_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_LMEM_MASK)
80676 
80677 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_LMEM_MASK (0x7000U)
80678 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_LMEM_SHIFT (12U)
80679 /*! MLPL_SW_LMEM - Memory(MEM Type I with PSW or MEM Type I except for CM33PLATFORM_CACHE or
80680  *    CM7PLATFORM_CACHE, depending on which MIX of the register) low power level when sw trigger memory
80681  *    update power level
80682  */
80683 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_LMEM(x)   (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_LMEM_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_LMEM_MASK)
80684 
80685 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_CACHE_MASK (0x70000U)
80686 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_CACHE_SHIFT (16U)
80687 /*! MLPL_HW_PDN_CACHE - Memory(MEM Type II or MEM Type I's CM33PLATFORM_CACHE or CM7PLATFORM_CACHE,
80688  *    depending on which MIX of the register) low power level when hw power down
80689  */
80690 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_CACHE_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PDN_CACHE_MASK)
80691 
80692 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_CACHE_MASK (0x700000U)
80693 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_CACHE_SHIFT (20U)
80694 /*! MLPL_HW_PUP_CACHE - Memory(MEM Type II or MEM Type I's CM33PLATFORM_CACHE or CM7PLATFORM_CACHE,
80695  *    depending on which MIX of the register) low power level when hw power up
80696  */
80697 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_CACHE_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_HW_PUP_CACHE_MASK)
80698 
80699 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_CACHE_MASK (0x70000000U)
80700 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_CACHE_SHIFT (28U)
80701 /*! MLPL_SW_CACHE - Memory(MEM Type II or MEM Type I's CM33PLATFORM_CACHE or CM7PLATFORM_CACHE,
80702  *    depending on which MIX of the register) low power level when sw trigger memory update power level
80703  */
80704 #define SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_CACHE(x)  (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_CACHE_SHIFT)) & SRC_MIX_SLICE_MLPL_CFG_MLPL_SW_CACHE_MASK)
80705 /*! @} */
80706 
80707 /*! @name MLPL_STAT - Memory Low Power Level Status */
80708 /*! @{ */
80709 
80710 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_LMEM_MASK (0x7U)
80711 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_LMEM_SHIFT (0U)
80712 /*! CURRENT_MLPL_LMEM - Current memory (MEM Type I with PSW or MEM Type I except for
80713  *    CM33PLATFORM_CACHE or CM7PLATFORM_CACHE, depending on which MIX of the register) low power level
80714  */
80715 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_LMEM(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_LMEM_SHIFT)) & SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_LMEM_MASK)
80716 
80717 #define SRC_MIX_SLICE_MLPL_STAT_LMEM_BUSY_MASK   (0x8U)
80718 #define SRC_MIX_SLICE_MLPL_STAT_LMEM_BUSY_SHIFT  (3U)
80719 /*! LMEM_BUSY - Busy requesting low power level of memory (MEM Type I with PSW or MEM Type I except
80720  *    for CM33PLATFORM_CACHE or CM7PLATFORM_CACHE, depending on which MIX of the register)
80721  */
80722 #define SRC_MIX_SLICE_MLPL_STAT_LMEM_BUSY(x)     (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_STAT_LMEM_BUSY_SHIFT)) & SRC_MIX_SLICE_MLPL_STAT_LMEM_BUSY_MASK)
80723 
80724 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_CACHE_MASK (0x70U)
80725 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_CACHE_SHIFT (4U)
80726 /*! CURRENT_MLPL_CACHE - Current memory (MEM Type II or MEM Type I's CM33PLATFORM_CACHE or
80727  *    CM7PLATFORM_CACHE, depending on which MIX of the register) low power level
80728  */
80729 #define SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_CACHE_SHIFT)) & SRC_MIX_SLICE_MLPL_STAT_CURRENT_MLPL_CACHE_MASK)
80730 
80731 #define SRC_MIX_SLICE_MLPL_STAT_CACHE_BUSY_MASK  (0x80U)
80732 #define SRC_MIX_SLICE_MLPL_STAT_CACHE_BUSY_SHIFT (7U)
80733 /*! CACHE_BUSY - Busy requesting low power level of memory (MEM Type II or MEM Type I's
80734  *    CM33PLATFORM_CACHE or CM7PLATFORM_CACHE, depending on which MIX of the register)
80735  */
80736 #define SRC_MIX_SLICE_MLPL_STAT_CACHE_BUSY(x)    (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MLPL_STAT_CACHE_BUSY_SHIFT)) & SRC_MIX_SLICE_MLPL_STAT_CACHE_BUSY_MASK)
80737 /*! @} */
80738 
80739 
80740 /*!
80741  * @}
80742  */ /* end of group SRC_MIX_SLICE_Register_Masks */
80743 
80744 
80745 /* SRC_MIX_SLICE - Peripheral instance base addresses */
80746 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
80747   /** Peripheral AON_MIX_SLICE base address */
80748   #define AON_MIX_SLICE_BASE                       (0x54460800u)
80749   /** Peripheral AON_MIX_SLICE base address */
80750   #define AON_MIX_SLICE_BASE_NS                    (0x44460800u)
80751   /** Peripheral AON_MIX_SLICE base pointer */
80752   #define AON_MIX_SLICE                            ((SRC_MIX_SLICE_Type *)AON_MIX_SLICE_BASE)
80753   /** Peripheral AON_MIX_SLICE base pointer */
80754   #define AON_MIX_SLICE_NS                         ((SRC_MIX_SLICE_Type *)AON_MIX_SLICE_BASE_NS)
80755   /** Peripheral WAKEUP_MIX_SLICE base address */
80756   #define WAKEUP_MIX_SLICE_BASE                    (0x54460C00u)
80757   /** Peripheral WAKEUP_MIX_SLICE base address */
80758   #define WAKEUP_MIX_SLICE_BASE_NS                 (0x44460C00u)
80759   /** Peripheral WAKEUP_MIX_SLICE base pointer */
80760   #define WAKEUP_MIX_SLICE                         ((SRC_MIX_SLICE_Type *)WAKEUP_MIX_SLICE_BASE)
80761   /** Peripheral WAKEUP_MIX_SLICE base pointer */
80762   #define WAKEUP_MIX_SLICE_NS                      ((SRC_MIX_SLICE_Type *)WAKEUP_MIX_SLICE_BASE_NS)
80763   /** Peripheral MEGA_MIX_SLICE base address */
80764   #define MEGA_MIX_SLICE_BASE                      (0x54461000u)
80765   /** Peripheral MEGA_MIX_SLICE base address */
80766   #define MEGA_MIX_SLICE_BASE_NS                   (0x44461000u)
80767   /** Peripheral MEGA_MIX_SLICE base pointer */
80768   #define MEGA_MIX_SLICE                           ((SRC_MIX_SLICE_Type *)MEGA_MIX_SLICE_BASE)
80769   /** Peripheral MEGA_MIX_SLICE base pointer */
80770   #define MEGA_MIX_SLICE_NS                        ((SRC_MIX_SLICE_Type *)MEGA_MIX_SLICE_BASE_NS)
80771   /** Peripheral NETC_MIX_SLICE base address */
80772   #define NETC_MIX_SLICE_BASE                      (0x54461400u)
80773   /** Peripheral NETC_MIX_SLICE base address */
80774   #define NETC_MIX_SLICE_BASE_NS                   (0x44461400u)
80775   /** Peripheral NETC_MIX_SLICE base pointer */
80776   #define NETC_MIX_SLICE                           ((SRC_MIX_SLICE_Type *)NETC_MIX_SLICE_BASE)
80777   /** Peripheral NETC_MIX_SLICE base pointer */
80778   #define NETC_MIX_SLICE_NS                        ((SRC_MIX_SLICE_Type *)NETC_MIX_SLICE_BASE_NS)
80779   /** Peripheral CM33PLATFORM_MIX_SLICE base address */
80780   #define CM33PLATFORM_MIX_SLICE_BASE              (0x54461800u)
80781   /** Peripheral CM33PLATFORM_MIX_SLICE base address */
80782   #define CM33PLATFORM_MIX_SLICE_BASE_NS           (0x44461800u)
80783   /** Peripheral CM33PLATFORM_MIX_SLICE base pointer */
80784   #define CM33PLATFORM_MIX_SLICE                   ((SRC_MIX_SLICE_Type *)CM33PLATFORM_MIX_SLICE_BASE)
80785   /** Peripheral CM33PLATFORM_MIX_SLICE base pointer */
80786   #define CM33PLATFORM_MIX_SLICE_NS                ((SRC_MIX_SLICE_Type *)CM33PLATFORM_MIX_SLICE_BASE_NS)
80787   /** Peripheral CM7PLATFORM_MIX_SLICE base address */
80788   #define CM7PLATFORM_MIX_SLICE_BASE               (0x54461C00u)
80789   /** Peripheral CM7PLATFORM_MIX_SLICE base address */
80790   #define CM7PLATFORM_MIX_SLICE_BASE_NS            (0x44461C00u)
80791   /** Peripheral CM7PLATFORM_MIX_SLICE base pointer */
80792   #define CM7PLATFORM_MIX_SLICE                    ((SRC_MIX_SLICE_Type *)CM7PLATFORM_MIX_SLICE_BASE)
80793   /** Peripheral CM7PLATFORM_MIX_SLICE base pointer */
80794   #define CM7PLATFORM_MIX_SLICE_NS                 ((SRC_MIX_SLICE_Type *)CM7PLATFORM_MIX_SLICE_BASE_NS)
80795   /** Array initializer of SRC_MIX_SLICE peripheral base addresses */
80796   #define SRC_MIX_SLICE_BASE_ADDRS                 { AON_MIX_SLICE_BASE, WAKEUP_MIX_SLICE_BASE, MEGA_MIX_SLICE_BASE, NETC_MIX_SLICE_BASE, CM33PLATFORM_MIX_SLICE_BASE, CM7PLATFORM_MIX_SLICE_BASE }
80797   /** Array initializer of SRC_MIX_SLICE peripheral base pointers */
80798   #define SRC_MIX_SLICE_BASE_PTRS                  { AON_MIX_SLICE, WAKEUP_MIX_SLICE, MEGA_MIX_SLICE, NETC_MIX_SLICE, CM33PLATFORM_MIX_SLICE, CM7PLATFORM_MIX_SLICE }
80799   /** Array initializer of SRC_MIX_SLICE peripheral base addresses */
80800   #define SRC_MIX_SLICE_BASE_ADDRS_NS              { AON_MIX_SLICE_BASE_NS, WAKEUP_MIX_SLICE_BASE_NS, MEGA_MIX_SLICE_BASE_NS, NETC_MIX_SLICE_BASE_NS, CM33PLATFORM_MIX_SLICE_BASE_NS, CM7PLATFORM_MIX_SLICE_BASE_NS }
80801   /** Array initializer of SRC_MIX_SLICE peripheral base pointers */
80802   #define SRC_MIX_SLICE_BASE_PTRS_NS               { AON_MIX_SLICE_NS, WAKEUP_MIX_SLICE_NS, MEGA_MIX_SLICE_NS, NETC_MIX_SLICE_NS, CM33PLATFORM_MIX_SLICE_NS, CM7PLATFORM_MIX_SLICE_NS }
80803 #else
80804   /** Peripheral AON_MIX_SLICE base address */
80805   #define AON_MIX_SLICE_BASE                       (0x44460800u)
80806   /** Peripheral AON_MIX_SLICE base pointer */
80807   #define AON_MIX_SLICE                            ((SRC_MIX_SLICE_Type *)AON_MIX_SLICE_BASE)
80808   /** Peripheral WAKEUP_MIX_SLICE base address */
80809   #define WAKEUP_MIX_SLICE_BASE                    (0x44460C00u)
80810   /** Peripheral WAKEUP_MIX_SLICE base pointer */
80811   #define WAKEUP_MIX_SLICE                         ((SRC_MIX_SLICE_Type *)WAKEUP_MIX_SLICE_BASE)
80812   /** Peripheral MEGA_MIX_SLICE base address */
80813   #define MEGA_MIX_SLICE_BASE                      (0x44461000u)
80814   /** Peripheral MEGA_MIX_SLICE base pointer */
80815   #define MEGA_MIX_SLICE                           ((SRC_MIX_SLICE_Type *)MEGA_MIX_SLICE_BASE)
80816   /** Peripheral NETC_MIX_SLICE base address */
80817   #define NETC_MIX_SLICE_BASE                      (0x44461400u)
80818   /** Peripheral NETC_MIX_SLICE base pointer */
80819   #define NETC_MIX_SLICE                           ((SRC_MIX_SLICE_Type *)NETC_MIX_SLICE_BASE)
80820   /** Peripheral CM33PLATFORM_MIX_SLICE base address */
80821   #define CM33PLATFORM_MIX_SLICE_BASE              (0x44461800u)
80822   /** Peripheral CM33PLATFORM_MIX_SLICE base pointer */
80823   #define CM33PLATFORM_MIX_SLICE                   ((SRC_MIX_SLICE_Type *)CM33PLATFORM_MIX_SLICE_BASE)
80824   /** Peripheral CM7PLATFORM_MIX_SLICE base address */
80825   #define CM7PLATFORM_MIX_SLICE_BASE               (0x44461C00u)
80826   /** Peripheral CM7PLATFORM_MIX_SLICE base pointer */
80827   #define CM7PLATFORM_MIX_SLICE                    ((SRC_MIX_SLICE_Type *)CM7PLATFORM_MIX_SLICE_BASE)
80828   /** Array initializer of SRC_MIX_SLICE peripheral base addresses */
80829   #define SRC_MIX_SLICE_BASE_ADDRS                 { AON_MIX_SLICE_BASE, WAKEUP_MIX_SLICE_BASE, MEGA_MIX_SLICE_BASE, NETC_MIX_SLICE_BASE, CM33PLATFORM_MIX_SLICE_BASE, CM7PLATFORM_MIX_SLICE_BASE }
80830   /** Array initializer of SRC_MIX_SLICE peripheral base pointers */
80831   #define SRC_MIX_SLICE_BASE_PTRS                  { AON_MIX_SLICE, WAKEUP_MIX_SLICE, MEGA_MIX_SLICE, NETC_MIX_SLICE, CM33PLATFORM_MIX_SLICE, CM7PLATFORM_MIX_SLICE }
80832 #endif
80833 
80834 /*!
80835  * @}
80836  */ /* end of group SRC_MIX_SLICE_Peripheral_Access_Layer */
80837 
80838 
80839 /* ----------------------------------------------------------------------------
80840    -- SYSPM Peripheral Access Layer
80841    ---------------------------------------------------------------------------- */
80842 
80843 /*!
80844  * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer
80845  * @{
80846  */
80847 
80848 /** SYSPM - Register Layout Typedef */
80849 typedef struct {
80850   struct {                                         /* offset: 0x0, array step: 0x30 */
80851     __IO uint32_t PMCR;                              /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */
80852          uint8_t RESERVED_0[12];
80853     __I  uint8_t PMICTR_HI;                          /**< Performance Monitor Instruction Counter, array offset: 0x10, array step: 0x30 */
80854          uint8_t RESERVED_1[3];
80855     __I  uint32_t PMICTR_LO;                         /**< Performance Monitor Instruction Counter, array offset: 0x14, array step: 0x30 */
80856     struct {                                         /* offset: 0x18, array step: index*0x30, index2*0x8 */
80857       __I  uint8_t HI;                                 /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */
80858            uint8_t RESERVED_0[3];
80859       __I  uint32_t LO;                                /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */
80860     } PMECTR[3];
80861   } PMCR[1];
80862 } SYSPM_Type;
80863 
80864 /* ----------------------------------------------------------------------------
80865    -- SYSPM Register Masks
80866    ---------------------------------------------------------------------------- */
80867 
80868 /*!
80869  * @addtogroup SYSPM_Register_Masks SYSPM Register Masks
80870  * @{
80871  */
80872 
80873 /*! @name PMCR - Performance Monitor Control */
80874 /*! @{ */
80875 
80876 #define SYSPM_PMCR_MENB_MASK                     (0x1U)
80877 #define SYSPM_PMCR_MENB_SHIFT                    (0U)
80878 /*! MENB - Module Is Enabled
80879  *  0b0..Disabled
80880  *  0b1..Enabled
80881  */
80882 #define SYSPM_PMCR_MENB(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK)
80883 
80884 #define SYSPM_PMCR_SSC_MASK                      (0xEU)
80885 #define SYSPM_PMCR_SSC_SHIFT                     (1U)
80886 /*! SSC - Start and Stop Control
80887  *  0b000..Idle or no-op
80888  *  0b001..Local stop
80889  *  0b010, 0b011..Local start
80890  *  0b100..
80891  *  0b101..
80892  *  0b110, 0b111..
80893  */
80894 #define SYSPM_PMCR_SSC(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK)
80895 
80896 #define SYSPM_PMCR_CMODE_MASK                    (0x30U)
80897 #define SYSPM_PMCR_CMODE_SHIFT                   (4U)
80898 /*! CMODE - Count Mode
80899  *  0b00..Counted in both User and Privileged modes
80900  *  0b01..
80901  *  0b10..Counted only in User mode
80902  *  0b11..Counted only in Privileged mode
80903  */
80904 #define SYSPM_PMCR_CMODE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK)
80905 
80906 #define SYSPM_PMCR_DCIFSH_MASK                   (0x40U)
80907 #define SYSPM_PMCR_DCIFSH_SHIFT                  (6U)
80908 /*! DCIFSH - Disable Counters if Stopped or Halted
80909  *  0b0..Continue
80910  *  0b1..Stop
80911  */
80912 #define SYSPM_PMCR_DCIFSH(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_DCIFSH_SHIFT)) & SYSPM_PMCR_DCIFSH_MASK)
80913 
80914 #define SYSPM_PMCR_RICTR_MASK                    (0x80U)
80915 #define SYSPM_PMCR_RICTR_SHIFT                   (7U)
80916 /*! RICTR - Reset Instruction Counter
80917  *  0b0..Do not reset
80918  *  0b1..Clear
80919  */
80920 #define SYSPM_PMCR_RICTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RICTR_SHIFT)) & SYSPM_PMCR_RICTR_MASK)
80921 
80922 #define SYSPM_PMCR_RECTR1_MASK                   (0x100U)
80923 #define SYSPM_PMCR_RECTR1_SHIFT                  (8U)
80924 /*! RECTR1 - Reset Event Counter 1
80925  *  0b0..Run normally
80926  *  0b1..Reset
80927  */
80928 #define SYSPM_PMCR_RECTR1(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK)
80929 
80930 #define SYSPM_PMCR_RECTR2_MASK                   (0x200U)
80931 #define SYSPM_PMCR_RECTR2_SHIFT                  (9U)
80932 /*! RECTR2 - Reset Event Counter 2
80933  *  0b0..Run normally
80934  *  0b1..Reset
80935  */
80936 #define SYSPM_PMCR_RECTR2(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK)
80937 
80938 #define SYSPM_PMCR_RECTR3_MASK                   (0x400U)
80939 #define SYSPM_PMCR_RECTR3_SHIFT                  (10U)
80940 /*! RECTR3 - Reset Event Counter 3
80941  *  0b0..Run normally
80942  *  0b1..Reset
80943  */
80944 #define SYSPM_PMCR_RECTR3(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK)
80945 
80946 #define SYSPM_PMCR_SELEVT1_MASK                  (0x3F800U)
80947 #define SYSPM_PMCR_SELEVT1_SHIFT                 (11U)
80948 /*! SELEVT1 - Select Event 1 */
80949 #define SYSPM_PMCR_SELEVT1(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK)
80950 
80951 #define SYSPM_PMCR_SELEVT2_MASK                  (0x1FC0000U)
80952 #define SYSPM_PMCR_SELEVT2_SHIFT                 (18U)
80953 /*! SELEVT2 - Select Event 2 */
80954 #define SYSPM_PMCR_SELEVT2(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK)
80955 
80956 #define SYSPM_PMCR_SELEVT3_MASK                  (0xFE000000U)
80957 #define SYSPM_PMCR_SELEVT3_SHIFT                 (25U)
80958 /*! SELEVT3 - Select Event 3 */
80959 #define SYSPM_PMCR_SELEVT3(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK)
80960 /*! @} */
80961 
80962 /* The count of SYSPM_PMCR */
80963 #define SYSPM_PMCR_COUNT                         (1U)
80964 
80965 /*! @name PMICTR_HI - Performance Monitor Instruction Counter */
80966 /*! @{ */
80967 
80968 #define SYSPM_PMICTR_HI_ICTR_MASK                (0xFFU)
80969 #define SYSPM_PMICTR_HI_ICTR_SHIFT               (0U)
80970 /*! ICTR - Instruction Counter */
80971 #define SYSPM_PMICTR_HI_ICTR(x)                  (((uint8_t)(((uint8_t)(x)) << SYSPM_PMICTR_HI_ICTR_SHIFT)) & SYSPM_PMICTR_HI_ICTR_MASK)
80972 /*! @} */
80973 
80974 /* The count of SYSPM_PMICTR_HI */
80975 #define SYSPM_PMICTR_HI_COUNT                    (1U)
80976 
80977 /*! @name PMICTR_LO - Performance Monitor Instruction Counter */
80978 /*! @{ */
80979 
80980 #define SYSPM_PMICTR_LO_ICTR_MASK                (0xFFFFFFFFU)
80981 #define SYSPM_PMICTR_LO_ICTR_SHIFT               (0U)
80982 /*! ICTR - Instruction Counter */
80983 #define SYSPM_PMICTR_LO_ICTR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSPM_PMICTR_LO_ICTR_SHIFT)) & SYSPM_PMICTR_LO_ICTR_MASK)
80984 /*! @} */
80985 
80986 /* The count of SYSPM_PMICTR_LO */
80987 #define SYSPM_PMICTR_LO_COUNT                    (1U)
80988 
80989 /*! @name HI - Performance Monitor Event Counter */
80990 /*! @{ */
80991 
80992 #define SYSPM_HI_ECTR_MASK                       (0xFFU)
80993 #define SYSPM_HI_ECTR_SHIFT                      (0U)
80994 /*! ECTR - Event Counter */
80995 #define SYSPM_HI_ECTR(x)                         (((uint8_t)(((uint8_t)(x)) << SYSPM_HI_ECTR_SHIFT)) & SYSPM_HI_ECTR_MASK)
80996 /*! @} */
80997 
80998 /* The count of SYSPM_HI */
80999 #define SYSPM_HI_COUNT                           (1U)
81000 
81001 /* The count of SYSPM_HI */
81002 #define SYSPM_HI_COUNT2                          (3U)
81003 
81004 /*! @name LO - Performance Monitor Event Counter */
81005 /*! @{ */
81006 
81007 #define SYSPM_LO_ECTR_MASK                       (0xFFFFFFFFU)
81008 #define SYSPM_LO_ECTR_SHIFT                      (0U)
81009 /*! ECTR - Event Counter */
81010 #define SYSPM_LO_ECTR(x)                         (((uint32_t)(((uint32_t)(x)) << SYSPM_LO_ECTR_SHIFT)) & SYSPM_LO_ECTR_MASK)
81011 /*! @} */
81012 
81013 /* The count of SYSPM_LO */
81014 #define SYSPM_LO_COUNT                           (1U)
81015 
81016 /* The count of SYSPM_LO */
81017 #define SYSPM_LO_COUNT2                          (3U)
81018 
81019 
81020 /*!
81021  * @}
81022  */ /* end of group SYSPM_Register_Masks */
81023 
81024 
81025 /* SYSPM - Peripheral instance base addresses */
81026 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
81027   /** Peripheral M33_PCF1 base address */
81028   #define M33_PCF1_BASE                            (0x543E0000u)
81029   /** Peripheral M33_PCF1 base address */
81030   #define M33_PCF1_BASE_NS                         (0x443E0000u)
81031   /** Peripheral M33_PCF1 base pointer */
81032   #define M33_PCF1                                 ((SYSPM_Type *)M33_PCF1_BASE)
81033   /** Peripheral M33_PCF1 base pointer */
81034   #define M33_PCF1_NS                              ((SYSPM_Type *)M33_PCF1_BASE_NS)
81035   /** Peripheral M33_PSF1 base address */
81036   #define M33_PSF1_BASE                            (0x543F0000u)
81037   /** Peripheral M33_PSF1 base address */
81038   #define M33_PSF1_BASE_NS                         (0x443F0000u)
81039   /** Peripheral M33_PSF1 base pointer */
81040   #define M33_PSF1                                 ((SYSPM_Type *)M33_PSF1_BASE)
81041   /** Peripheral M33_PSF1 base pointer */
81042   #define M33_PSF1_NS                              ((SYSPM_Type *)M33_PSF1_BASE_NS)
81043   /** Array initializer of SYSPM peripheral base addresses */
81044   #define SYSPM_BASE_ADDRS                         { M33_PCF1_BASE, M33_PSF1_BASE }
81045   /** Array initializer of SYSPM peripheral base pointers */
81046   #define SYSPM_BASE_PTRS                          { M33_PCF1, M33_PSF1 }
81047   /** Array initializer of SYSPM peripheral base addresses */
81048   #define SYSPM_BASE_ADDRS_NS                      { M33_PCF1_BASE_NS, M33_PSF1_BASE_NS }
81049   /** Array initializer of SYSPM peripheral base pointers */
81050   #define SYSPM_BASE_PTRS_NS                       { M33_PCF1_NS, M33_PSF1_NS }
81051 #else
81052   /** Peripheral M33_PCF1 base address */
81053   #define M33_PCF1_BASE                            (0x443E0000u)
81054   /** Peripheral M33_PCF1 base pointer */
81055   #define M33_PCF1                                 ((SYSPM_Type *)M33_PCF1_BASE)
81056   /** Peripheral M33_PSF1 base address */
81057   #define M33_PSF1_BASE                            (0x443F0000u)
81058   /** Peripheral M33_PSF1 base pointer */
81059   #define M33_PSF1                                 ((SYSPM_Type *)M33_PSF1_BASE)
81060   /** Array initializer of SYSPM peripheral base addresses */
81061   #define SYSPM_BASE_ADDRS                         { M33_PCF1_BASE, M33_PSF1_BASE }
81062   /** Array initializer of SYSPM peripheral base pointers */
81063   #define SYSPM_BASE_PTRS                          { M33_PCF1, M33_PSF1 }
81064 #endif
81065 
81066 /*!
81067  * @}
81068  */ /* end of group SYSPM_Peripheral_Access_Layer */
81069 
81070 
81071 /* ----------------------------------------------------------------------------
81072    -- SYS_CTR_COMPARE Peripheral Access Layer
81073    ---------------------------------------------------------------------------- */
81074 
81075 /*!
81076  * @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer
81077  * @{
81078  */
81079 
81080 /** SYS_CTR_COMPARE - Register Layout Typedef */
81081 typedef struct {
81082        uint8_t RESERVED_0[32];
81083   __IO uint32_t CMPCVL0;                           /**< Compare Count Value Low, offset: 0x20 */
81084   __IO uint32_t CMPCVH0;                           /**< Compare Count Value High, offset: 0x24 */
81085        uint8_t RESERVED_1[4];
81086   __IO uint32_t CMPCR0;                            /**< Compare Control, offset: 0x2C */
81087        uint8_t RESERVED_2[240];
81088   __IO uint32_t CMPCVL1;                           /**< Compare Count Value Low, offset: 0x120 */
81089   __IO uint32_t CMPCVH1;                           /**< Compare Count Value High, offset: 0x124 */
81090        uint8_t RESERVED_3[4];
81091   __IO uint32_t CMPCR1;                            /**< Compare Control, offset: 0x12C */
81092        uint8_t RESERVED_4[3744];
81093   __I  uint32_t CNTID0;                            /**< Counter ID, offset: 0xFD0 */
81094 } SYS_CTR_COMPARE_Type;
81095 
81096 /* ----------------------------------------------------------------------------
81097    -- SYS_CTR_COMPARE Register Masks
81098    ---------------------------------------------------------------------------- */
81099 
81100 /*!
81101  * @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks
81102  * @{
81103  */
81104 
81105 /*! @name CMPCVL0 - Compare Count Value Low */
81106 /*! @{ */
81107 
81108 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK      (0xFFFFFFFFU)
81109 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT     (0U)
81110 /*! CMPCV0 - Compare Count Value Bits [31:0] */
81111 #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK)
81112 /*! @} */
81113 
81114 /*! @name CMPCVH0 - Compare Count Value High */
81115 /*! @{ */
81116 
81117 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK      (0xFFFFFFU)
81118 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT     (0U)
81119 /*! CMPCV1 - Compare Count Value Bits [55:32] */
81120 #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK)
81121 /*! @} */
81122 
81123 /*! @name CMPCR0 - Compare Control */
81124 /*! @{ */
81125 
81126 #define SYS_CTR_COMPARE_CMPCR0_EN_MASK           (0x1U)
81127 #define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT          (0U)
81128 /*! EN - Compare Enable
81129  *  0b0..Disable
81130  *  0b1..Enable
81131  */
81132 #define SYS_CTR_COMPARE_CMPCR0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK)
81133 
81134 #define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK        (0x2U)
81135 #define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT       (1U)
81136 /*! IMASK - Interrupt Request Mask
81137  *  0b0..Not masked
81138  *  0b1..Masked
81139  */
81140 #define SYS_CTR_COMPARE_CMPCR0_IMASK(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK)
81141 
81142 #define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK        (0x4U)
81143 #define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT       (2U)
81144 /*! ISTAT - Compare Interrupt Status
81145  *  0b0..Either less than the compare value or compare is disabled
81146  *  0b1..Greater than or equal to the compare value and compare is enabled
81147  */
81148 #define SYS_CTR_COMPARE_CMPCR0_ISTAT(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK)
81149 /*! @} */
81150 
81151 /*! @name CMPCVL1 - Compare Count Value Low */
81152 /*! @{ */
81153 
81154 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK      (0xFFFFFFFFU)
81155 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT     (0U)
81156 /*! CMPCV0 - Compare Count Value Bits [31:0] */
81157 #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK)
81158 /*! @} */
81159 
81160 /*! @name CMPCVH1 - Compare Count Value High */
81161 /*! @{ */
81162 
81163 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK      (0xFFFFFFU)
81164 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT     (0U)
81165 /*! CMPCV1 - Compare Count Value Bits [55:32] */
81166 #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK)
81167 /*! @} */
81168 
81169 /*! @name CMPCR1 - Compare Control */
81170 /*! @{ */
81171 
81172 #define SYS_CTR_COMPARE_CMPCR1_EN_MASK           (0x1U)
81173 #define SYS_CTR_COMPARE_CMPCR1_EN_SHIFT          (0U)
81174 /*! EN - Compare Enable
81175  *  0b0..Disable
81176  *  0b1..Enable
81177  */
81178 #define SYS_CTR_COMPARE_CMPCR1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_EN_MASK)
81179 
81180 #define SYS_CTR_COMPARE_CMPCR1_IMASK_MASK        (0x2U)
81181 #define SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT       (1U)
81182 /*! IMASK - Interrupt Request Mask
81183  *  0b0..Not masked
81184  *  0b1..Masked
81185  */
81186 #define SYS_CTR_COMPARE_CMPCR1_IMASK(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_IMASK_MASK)
81187 
81188 #define SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK        (0x4U)
81189 #define SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT       (2U)
81190 /*! ISTAT - Compare Interrupt Status
81191  *  0b0..Either less than the compare value or compare is disabled
81192  *  0b1..Greater than or equal to the compare value and compare is enabled
81193  */
81194 #define SYS_CTR_COMPARE_CMPCR1_ISTAT(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK)
81195 /*! @} */
81196 
81197 /*! @name CNTID0 - Counter ID */
81198 /*! @{ */
81199 
81200 #define SYS_CTR_COMPARE_CNTID0_CNTID_MASK        (0xFFFFFFFFU)
81201 #define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT       (0U)
81202 /*! CNTID - Counter Identification */
81203 #define SYS_CTR_COMPARE_CNTID0_CNTID(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK)
81204 /*! @} */
81205 
81206 
81207 /*!
81208  * @}
81209  */ /* end of group SYS_CTR_COMPARE_Register_Masks */
81210 
81211 
81212 /* SYS_CTR_COMPARE - Peripheral instance base addresses */
81213 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
81214   /** Peripheral SYS_CTR_COMPARE base address */
81215   #define SYS_CTR_COMPARE_BASE                     (0x542A0000u)
81216   /** Peripheral SYS_CTR_COMPARE base address */
81217   #define SYS_CTR_COMPARE_BASE_NS                  (0x442A0000u)
81218   /** Peripheral SYS_CTR_COMPARE base pointer */
81219   #define SYS_CTR_COMPARE                          ((SYS_CTR_COMPARE_Type *)SYS_CTR_COMPARE_BASE)
81220   /** Peripheral SYS_CTR_COMPARE base pointer */
81221   #define SYS_CTR_COMPARE_NS                       ((SYS_CTR_COMPARE_Type *)SYS_CTR_COMPARE_BASE_NS)
81222   /** Array initializer of SYS_CTR_COMPARE peripheral base addresses */
81223   #define SYS_CTR_COMPARE_BASE_ADDRS               { SYS_CTR_COMPARE_BASE }
81224   /** Array initializer of SYS_CTR_COMPARE peripheral base pointers */
81225   #define SYS_CTR_COMPARE_BASE_PTRS                { SYS_CTR_COMPARE }
81226   /** Array initializer of SYS_CTR_COMPARE peripheral base addresses */
81227   #define SYS_CTR_COMPARE_BASE_ADDRS_NS            { SYS_CTR_COMPARE_BASE_NS }
81228   /** Array initializer of SYS_CTR_COMPARE peripheral base pointers */
81229   #define SYS_CTR_COMPARE_BASE_PTRS_NS             { SYS_CTR_COMPARE_NS }
81230 #else
81231   /** Peripheral SYS_CTR_COMPARE base address */
81232   #define SYS_CTR_COMPARE_BASE                     (0x442A0000u)
81233   /** Peripheral SYS_CTR_COMPARE base pointer */
81234   #define SYS_CTR_COMPARE                          ((SYS_CTR_COMPARE_Type *)SYS_CTR_COMPARE_BASE)
81235   /** Array initializer of SYS_CTR_COMPARE peripheral base addresses */
81236   #define SYS_CTR_COMPARE_BASE_ADDRS               { SYS_CTR_COMPARE_BASE }
81237   /** Array initializer of SYS_CTR_COMPARE peripheral base pointers */
81238   #define SYS_CTR_COMPARE_BASE_PTRS                { SYS_CTR_COMPARE }
81239 #endif
81240 
81241 /*!
81242  * @}
81243  */ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */
81244 
81245 
81246 /* ----------------------------------------------------------------------------
81247    -- SYS_CTR_CONTROL Peripheral Access Layer
81248    ---------------------------------------------------------------------------- */
81249 
81250 /*!
81251  * @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer
81252  * @{
81253  */
81254 
81255 /** SYS_CTR_CONTROL - Register Layout Typedef */
81256 typedef struct {
81257   __IO uint32_t CNTCR;                             /**< Counter Control, offset: 0x0 */
81258   __I  uint32_t CNTSR;                             /**< Counter Status, offset: 0x4 */
81259   __IO uint32_t CNTCV0;                            /**< Counter Count Value Low, offset: 0x8 */
81260   __IO uint32_t CNTCV1;                            /**< Counter Count Value High, offset: 0xC */
81261        uint8_t RESERVED_0[16];
81262   __I  uint32_t CNTFID0;                           /**< Frequency-Modes Table 0, offset: 0x20 */
81263   __I  uint32_t CNTFID1;                           /**< Frequency-Modes Table 1, offset: 0x24 */
81264   __I  uint32_t CNTFID2;                           /**< Frequency-Modes Table 2, offset: 0x28 */
81265        uint8_t RESERVED_1[148];
81266   __IO uint32_t CNTCR2;                            /**< Counter Control 2, offset: 0xC0 */
81267        uint8_t RESERVED_2[3852];
81268   __I  uint32_t CNTID0;                            /**< Counter ID, offset: 0xFD0 */
81269 } SYS_CTR_CONTROL_Type;
81270 
81271 /* ----------------------------------------------------------------------------
81272    -- SYS_CTR_CONTROL Register Masks
81273    ---------------------------------------------------------------------------- */
81274 
81275 /*!
81276  * @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks
81277  * @{
81278  */
81279 
81280 /*! @name CNTCR - Counter Control */
81281 /*! @{ */
81282 
81283 #define SYS_CTR_CONTROL_CNTCR_EN_MASK            (0x1U)
81284 #define SYS_CTR_CONTROL_CNTCR_EN_SHIFT           (0U)
81285 /*! EN - Enable Counting
81286  *  0b0..Disable
81287  *  0b1..Enable
81288  */
81289 #define SYS_CTR_CONTROL_CNTCR_EN(x)              (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK)
81290 
81291 #define SYS_CTR_CONTROL_CNTCR_HDBG_MASK          (0x2U)
81292 #define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT         (1U)
81293 /*! HDBG - Enable Debug Halt
81294  *  0b0..Ignored
81295  *  0b1..Causes SYS_CTR to halt
81296  */
81297 #define SYS_CTR_CONTROL_CNTCR_HDBG(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK)
81298 
81299 #define SYS_CTR_CONTROL_CNTCR_FCR0_MASK          (0x100U)
81300 #define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT         (8U)
81301 /*! FCR0 - Frequency Change Request, ID 0
81302  *  0b0..No change
81303  *  0b1..Base frequency
81304  */
81305 #define SYS_CTR_CONTROL_CNTCR_FCR0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK)
81306 
81307 #define SYS_CTR_CONTROL_CNTCR_FCR1_MASK          (0x200U)
81308 #define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT         (9U)
81309 /*! FCR1 - Frequency Change Request, ID 1
81310  *  0b0..No change
81311  *  0b1..Base frequency
81312  */
81313 #define SYS_CTR_CONTROL_CNTCR_FCR1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK)
81314 /*! @} */
81315 
81316 /*! @name CNTSR - Counter Status */
81317 /*! @{ */
81318 
81319 #define SYS_CTR_CONTROL_CNTSR_DBGH_MASK          (0x1U)
81320 #define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT         (0U)
81321 /*! DBGH - Debug Halt
81322  *  0b0..Did not halt
81323  *  0b1..Halted
81324  */
81325 #define SYS_CTR_CONTROL_CNTSR_DBGH(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK)
81326 
81327 #define SYS_CTR_CONTROL_CNTSR_FCA0_MASK          (0x100U)
81328 #define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT         (8U)
81329 /*! FCA0 - Frequency Change Acknowledge, ID 0
81330  *  0b0..Not selected
81331  *  0b1..Selected
81332  */
81333 #define SYS_CTR_CONTROL_CNTSR_FCA0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK)
81334 
81335 #define SYS_CTR_CONTROL_CNTSR_FCA1_MASK          (0x200U)
81336 #define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT         (9U)
81337 /*! FCA1 - Frequency Change Acknowledge, ID 1
81338  *  0b0..Not selected
81339  *  0b1..Selected
81340  */
81341 #define SYS_CTR_CONTROL_CNTSR_FCA1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK)
81342 /*! @} */
81343 
81344 /*! @name CNTCV0 - Counter Count Value Low */
81345 /*! @{ */
81346 
81347 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK       (0xFFFFFFFFU)
81348 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT      (0U)
81349 /*! CNTCV0 - Counter Count Value Bits [31:0] */
81350 #define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x)         (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK)
81351 /*! @} */
81352 
81353 /*! @name CNTCV1 - Counter Count Value High */
81354 /*! @{ */
81355 
81356 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK       (0xFFFFFFU)
81357 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT      (0U)
81358 /*! CNTCV1 - Counter Count Value Bits [55:32] */
81359 #define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x)         (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK)
81360 /*! @} */
81361 
81362 /*! @name CNTFID0 - Frequency-Modes Table 0 */
81363 /*! @{ */
81364 
81365 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK     (0xFFFFFFFFU)
81366 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT    (0U)
81367 /*! CNTFID0 - Counter Frequency ID 0 */
81368 #define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK)
81369 /*! @} */
81370 
81371 /*! @name CNTFID1 - Frequency-Modes Table 1 */
81372 /*! @{ */
81373 
81374 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK     (0xFFFFFFFFU)
81375 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT    (0U)
81376 /*! CNTFID1 - Counter Frequency ID 1 */
81377 #define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK)
81378 /*! @} */
81379 
81380 /*! @name CNTFID2 - Frequency-Modes Table 2 */
81381 /*! @{ */
81382 
81383 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK     (0xFFFFFFFFU)
81384 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT    (0U)
81385 /*! CNTFID2 - Counter Frequency ID 2 */
81386 #define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x)       (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK)
81387 /*! @} */
81388 
81389 /*! @name CNTCR2 - Counter Control 2 */
81390 /*! @{ */
81391 
81392 #define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK      (0x1U)
81393 #define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT     (0U)
81394 /*! HWFC_EN - Hardware Frequency Change Enable
81395  *  0b0..No effect
81396  *  0b1..Same as performed via software
81397  */
81398 #define SYS_CTR_CONTROL_CNTCR2_HWFC_EN(x)        (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK)
81399 /*! @} */
81400 
81401 /*! @name CNTID0 - Counter ID */
81402 /*! @{ */
81403 
81404 #define SYS_CTR_CONTROL_CNTID0_CNTID_MASK        (0xFFFFFFFFU)
81405 #define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT       (0U)
81406 /*! CNTID - Counter Identification */
81407 #define SYS_CTR_CONTROL_CNTID0_CNTID(x)          (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK)
81408 /*! @} */
81409 
81410 
81411 /*!
81412  * @}
81413  */ /* end of group SYS_CTR_CONTROL_Register_Masks */
81414 
81415 
81416 /* SYS_CTR_CONTROL - Peripheral instance base addresses */
81417 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
81418   /** Peripheral SYS_CTR_CONTROL base address */
81419   #define SYS_CTR_CONTROL_BASE                     (0x54290000u)
81420   /** Peripheral SYS_CTR_CONTROL base address */
81421   #define SYS_CTR_CONTROL_BASE_NS                  (0x44290000u)
81422   /** Peripheral SYS_CTR_CONTROL base pointer */
81423   #define SYS_CTR_CONTROL                          ((SYS_CTR_CONTROL_Type *)SYS_CTR_CONTROL_BASE)
81424   /** Peripheral SYS_CTR_CONTROL base pointer */
81425   #define SYS_CTR_CONTROL_NS                       ((SYS_CTR_CONTROL_Type *)SYS_CTR_CONTROL_BASE_NS)
81426   /** Array initializer of SYS_CTR_CONTROL peripheral base addresses */
81427   #define SYS_CTR_CONTROL_BASE_ADDRS               { SYS_CTR_CONTROL_BASE }
81428   /** Array initializer of SYS_CTR_CONTROL peripheral base pointers */
81429   #define SYS_CTR_CONTROL_BASE_PTRS                { SYS_CTR_CONTROL }
81430   /** Array initializer of SYS_CTR_CONTROL peripheral base addresses */
81431   #define SYS_CTR_CONTROL_BASE_ADDRS_NS            { SYS_CTR_CONTROL_BASE_NS }
81432   /** Array initializer of SYS_CTR_CONTROL peripheral base pointers */
81433   #define SYS_CTR_CONTROL_BASE_PTRS_NS             { SYS_CTR_CONTROL_NS }
81434 #else
81435   /** Peripheral SYS_CTR_CONTROL base address */
81436   #define SYS_CTR_CONTROL_BASE                     (0x44290000u)
81437   /** Peripheral SYS_CTR_CONTROL base pointer */
81438   #define SYS_CTR_CONTROL                          ((SYS_CTR_CONTROL_Type *)SYS_CTR_CONTROL_BASE)
81439   /** Array initializer of SYS_CTR_CONTROL peripheral base addresses */
81440   #define SYS_CTR_CONTROL_BASE_ADDRS               { SYS_CTR_CONTROL_BASE }
81441   /** Array initializer of SYS_CTR_CONTROL peripheral base pointers */
81442   #define SYS_CTR_CONTROL_BASE_PTRS                { SYS_CTR_CONTROL }
81443 #endif
81444 
81445 /*!
81446  * @}
81447  */ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */
81448 
81449 
81450 /* ----------------------------------------------------------------------------
81451    -- SYS_CTR_READ Peripheral Access Layer
81452    ---------------------------------------------------------------------------- */
81453 
81454 /*!
81455  * @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer
81456  * @{
81457  */
81458 
81459 /** SYS_CTR_READ - Register Layout Typedef */
81460 typedef struct {
81461        uint8_t RESERVED_0[8];
81462   __I  uint32_t CNTCV0;                            /**< Counter Count Value Low, offset: 0x8 */
81463   __I  uint32_t CNTCV1;                            /**< Counter Count Value High, offset: 0xC */
81464        uint8_t RESERVED_1[4032];
81465   __I  uint32_t CNTID0;                            /**< Counter ID, offset: 0xFD0 */
81466 } SYS_CTR_READ_Type;
81467 
81468 /* ----------------------------------------------------------------------------
81469    -- SYS_CTR_READ Register Masks
81470    ---------------------------------------------------------------------------- */
81471 
81472 /*!
81473  * @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks
81474  * @{
81475  */
81476 
81477 /*! @name CNTCV0 - Counter Count Value Low */
81478 /*! @{ */
81479 
81480 #define SYS_CTR_READ_CNTCV0_CNTCV0_MASK          (0xFFFFFFFFU)
81481 #define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT         (0U)
81482 /*! CNTCV0 - Counter Count Value Bits [31:0] */
81483 #define SYS_CTR_READ_CNTCV0_CNTCV0(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK)
81484 /*! @} */
81485 
81486 /*! @name CNTCV1 - Counter Count Value High */
81487 /*! @{ */
81488 
81489 #define SYS_CTR_READ_CNTCV1_CNTCV1_MASK          (0xFFFFFFU)
81490 #define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT         (0U)
81491 /*! CNTCV1 - Counter Count Value Bits [55:32] */
81492 #define SYS_CTR_READ_CNTCV1_CNTCV1(x)            (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK)
81493 /*! @} */
81494 
81495 /*! @name CNTID0 - Counter ID */
81496 /*! @{ */
81497 
81498 #define SYS_CTR_READ_CNTID0_CNTID_MASK           (0xFFFFFFFFU)
81499 #define SYS_CTR_READ_CNTID0_CNTID_SHIFT          (0U)
81500 /*! CNTID - Counter Identification */
81501 #define SYS_CTR_READ_CNTID0_CNTID(x)             (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK)
81502 /*! @} */
81503 
81504 
81505 /*!
81506  * @}
81507  */ /* end of group SYS_CTR_READ_Register_Masks */
81508 
81509 
81510 /* SYS_CTR_READ - Peripheral instance base addresses */
81511 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
81512   /** Peripheral SYS_CTR_READ base address */
81513   #define SYS_CTR_READ_BASE                        (0x542B0000u)
81514   /** Peripheral SYS_CTR_READ base address */
81515   #define SYS_CTR_READ_BASE_NS                     (0x442B0000u)
81516   /** Peripheral SYS_CTR_READ base pointer */
81517   #define SYS_CTR_READ                             ((SYS_CTR_READ_Type *)SYS_CTR_READ_BASE)
81518   /** Peripheral SYS_CTR_READ base pointer */
81519   #define SYS_CTR_READ_NS                          ((SYS_CTR_READ_Type *)SYS_CTR_READ_BASE_NS)
81520   /** Array initializer of SYS_CTR_READ peripheral base addresses */
81521   #define SYS_CTR_READ_BASE_ADDRS                  { SYS_CTR_READ_BASE }
81522   /** Array initializer of SYS_CTR_READ peripheral base pointers */
81523   #define SYS_CTR_READ_BASE_PTRS                   { SYS_CTR_READ }
81524   /** Array initializer of SYS_CTR_READ peripheral base addresses */
81525   #define SYS_CTR_READ_BASE_ADDRS_NS               { SYS_CTR_READ_BASE_NS }
81526   /** Array initializer of SYS_CTR_READ peripheral base pointers */
81527   #define SYS_CTR_READ_BASE_PTRS_NS                { SYS_CTR_READ_NS }
81528 #else
81529   /** Peripheral SYS_CTR_READ base address */
81530   #define SYS_CTR_READ_BASE                        (0x442B0000u)
81531   /** Peripheral SYS_CTR_READ base pointer */
81532   #define SYS_CTR_READ                             ((SYS_CTR_READ_Type *)SYS_CTR_READ_BASE)
81533   /** Array initializer of SYS_CTR_READ peripheral base addresses */
81534   #define SYS_CTR_READ_BASE_ADDRS                  { SYS_CTR_READ_BASE }
81535   /** Array initializer of SYS_CTR_READ peripheral base pointers */
81536   #define SYS_CTR_READ_BASE_PTRS                   { SYS_CTR_READ }
81537 #endif
81538 
81539 /*!
81540  * @}
81541  */ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */
81542 
81543 
81544 /* ----------------------------------------------------------------------------
81545    -- TCM_ECC_MCM Peripheral Access Layer
81546    ---------------------------------------------------------------------------- */
81547 
81548 /*!
81549  * @addtogroup TCM_ECC_MCM_Peripheral_Access_Layer TCM_ECC_MCM Peripheral Access Layer
81550  * @{
81551  */
81552 
81553 /** TCM_ECC_MCM - Register Layout Typedef */
81554 typedef struct {
81555        uint8_t RESERVED_0[4];
81556   __IO uint32_t TCMECCR;                           /**< TCM ECC Control, offset: 0x4 */
81557        uint8_t RESERVED_1[24];
81558   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x20 */
81559   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable, offset: 0x24 */
81560   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable, offset: 0x28 */
81561        uint8_t RESERVED_2[48];
81562   __I  uint32_t CODE_TCM_ECC_SINGLE_ERROR_INFO;    /**< Code TCM Single-Bit ECC Error Information, offset: 0x5C */
81563   __I  uint32_t CODE_TCM_ECC_SINGLE_ERROR_ADDR;    /**< Code TCM Single-Bit ECC Error Address, offset: 0x60 */
81564        uint8_t RESERVED_3[4];
81565   __I  uint32_t CODE_TCM_ECC_MULTI_ERROR_INFO;     /**< Code TCM Multibit ECC Error Information, offset: 0x68 */
81566   __I  uint32_t CODE_TCM_ECC_MULTI_ERROR_ADDR;     /**< Code TCM Multibit ECC Error Address, offset: 0x6C */
81567        uint8_t RESERVED_4[4];
81568   __I  uint32_t SYS_TCM_ECC_SINGLE_ERROR_INFO;     /**< System TCM Single-Bit ECC Error Information, offset: 0x74 */
81569   __I  uint32_t SYS_TCM_ECC_SINGLE_ERROR_ADDR;     /**< System TCM Single-Bit ECC Error Address, offset: 0x78 */
81570        uint8_t RESERVED_5[4];
81571   __I  uint32_t SYS_TCM_ECC_MULTI_ERROR_INFO;      /**< System TCM Multibit ECC Error Information, offset: 0x80 */
81572   __I  uint32_t SYS_TCM_ECC_MULTI_ERROR_ADDR;      /**< System TCM Multibit ECC Error Address, offset: 0x84 */
81573        uint8_t RESERVED_6[12];
81574   __IO uint32_t CODE_TCM_ECC_ERROR_INJEC;          /**< Code TCM ECC Error Injection, offset: 0x94 */
81575   __IO uint32_t SYS_TCM_ECC_ERROR_INJEC;           /**< System TCM ECC Error Injection, offset: 0x98 */
81576 } TCM_ECC_MCM_Type;
81577 
81578 /* ----------------------------------------------------------------------------
81579    -- TCM_ECC_MCM Register Masks
81580    ---------------------------------------------------------------------------- */
81581 
81582 /*!
81583  * @addtogroup TCM_ECC_MCM_Register_Masks TCM_ECC_MCM Register Masks
81584  * @{
81585  */
81586 
81587 /*! @name TCMECCR - TCM ECC Control */
81588 /*! @{ */
81589 
81590 #define TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK        (0x1U)
81591 #define TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT       (0U)
81592 /*! WECC_DIS - TCM ECC Write Generation Disable
81593  *  0b1..Disable
81594  *  0b0..Enable
81595  */
81596 #define TCM_ECC_MCM_TCMECCR_WECC_DIS(x)          (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK)
81597 
81598 #define TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK        (0x2U)
81599 #define TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT       (1U)
81600 /*! RECC_DIS - TCM ECC Read Check Disable
81601  *  0b1..Disable
81602  *  0b0..Enable
81603  */
81604 #define TCM_ECC_MCM_TCMECCR_RECC_DIS(x)          (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK)
81605 /*! @} */
81606 
81607 /*! @name INT_STATUS - Interrupt Status */
81608 /*! @{ */
81609 
81610 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK (0x400U)
81611 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT (10U)
81612 /*! CODE_TCM_ECC_ERRM_INT - Code TCM Access Multibit ECC Error Interrupt Status
81613  *  0b0..No error
81614  *  0b1..Error
81615  *  0b0..No effect
81616  *  0b1..Clear the flag
81617  */
81618 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK)
81619 
81620 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK (0x800U)
81621 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT (11U)
81622 /*! CODE_TCM_ECC_ERRS_INT - Code TCM Access Single-Bit ECC Error Interrupt Status
81623  *  0b0..No error
81624  *  0b1..Error
81625  *  0b0..No effect
81626  *  0b1..Clear the flag
81627  */
81628 #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK)
81629 
81630 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK (0x1000U)
81631 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT (12U)
81632 /*! SYS_TCM_ECC_ERRM_INT - System TCM Access Multibit ECC Error Interrupt Status
81633  *  0b0..No error
81634  *  0b1..Error
81635  *  0b0..No effect
81636  *  0b1..Clear the flag
81637  */
81638 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK)
81639 
81640 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK (0x2000U)
81641 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT (13U)
81642 /*! SYS_TCM_ECC_ERRS_INT - System TCM Access Single-Bit ECC Error Interrupt Status
81643  *  0b0..No error
81644  *  0b1..Error
81645  *  0b0..No effect
81646  *  0b1..Clear the flag
81647  */
81648 #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK)
81649 /*! @} */
81650 
81651 /*! @name INT_STAT_EN - Interrupt Status Enable */
81652 /*! @{ */
81653 
81654 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_MASK (0x400U)
81655 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_SHIFT (10U)
81656 /*! CODE_TCM_ERRM_INT_EN - Code TCM Access Multibit ECC Error Interrupt Status Enable
81657  *  0b0..Mask
81658  *  0b1..Enable
81659  */
81660 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_MASK)
81661 
81662 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_MASK (0x800U)
81663 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_SHIFT (11U)
81664 /*! CODE_TCM_ERRS_INT_EN - Code TCM Access Single-Bit ECC Error Interrupt Status Enable
81665  *  0b0..Mask
81666  *  0b1..Enable
81667  */
81668 #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_MASK)
81669 
81670 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_MASK (0x1000U)
81671 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_SHIFT (12U)
81672 /*! SYS_TCM_ERRM_INT_EN - System TCM Access Multibit ECC Error Interrupt Status Enable
81673  *  0b0..Mask
81674  *  0b1..Enable
81675  */
81676 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_MASK)
81677 
81678 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_MASK (0x2000U)
81679 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_SHIFT (13U)
81680 /*! SYS_TCM_ERRS_INT_EN - System TCM Access Single-Bit ECC Error Interrupt Status Enable
81681  *  0b0..Mask
81682  *  0b1..Enable
81683  */
81684 #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_MASK)
81685 /*! @} */
81686 
81687 /*! @name INT_SIG_EN - Interrupt Enable */
81688 /*! @{ */
81689 
81690 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_MASK (0x400U)
81691 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_SHIFT (10U)
81692 /*! CODE_TCM_ERRM_INT_SIG_EN - Code TCM Access Multibit ECC Error Interrupt Signal Enable
81693  *  0b0..Mask
81694  *  0b1..Enable
81695  */
81696 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_MASK)
81697 
81698 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_MASK (0x800U)
81699 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_SHIFT (11U)
81700 /*! CODE_TCM_ERRS_INT_SIG_EN - Code TCM Access Single-Bit ECC Error Interrupt Signal Enable
81701  *  0b0..Mask
81702  *  0b1..Enable
81703  */
81704 #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_MASK)
81705 
81706 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
81707 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_SHIFT (12U)
81708 /*! SYS_TCM_ERRM_INT_SIG_EN - System TCM Access Multibit ECC Error Interrupt Signal Enable
81709  *  0b0..Mask
81710  *  0b1..Enable
81711  */
81712 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_MASK)
81713 
81714 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
81715 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_SHIFT (13U)
81716 /*! SYS_TCM_ERRS_INT_SIG_EN - System TCM Access Single-Bit ECC Error Interrupt Signal Enable
81717  *  0b0..Mask
81718  *  0b1..Enable
81719  */
81720 #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_MASK)
81721 /*! @} */
81722 
81723 /*! @name CODE_TCM_ECC_SINGLE_ERROR_INFO - Code TCM Single-Bit ECC Error Information */
81724 /*! @{ */
81725 
81726 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_MASK (0xEU)
81727 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_SHIFT (1U)
81728 /*! CODE_TCM_ECCS_EFSIZ - Code TCM Single-Bit ECC Error for Corresponding TCM Access Size */
81729 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_MASK)
81730 
81731 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_MASK (0xF0U)
81732 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_SHIFT (4U)
81733 /*! CODE_TCM_ECCS_EFMST - Code TCM Single-Bit ECC Error for Corresponding TCM Master */
81734 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_MASK)
81735 
81736 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_MASK (0xF00U)
81737 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_SHIFT (8U)
81738 /*! CODE_TCM_ECCS_EFPRT - Code TCM Single-Bit ECC Error for Corresponding TCM Access Protection */
81739 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_MASK)
81740 
81741 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_MASK (0x7F000U)
81742 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_SHIFT (12U)
81743 /*! CODE_TCM_ECCS_EFSYN - Code TCM Single-Bit ECC Error Corresponding Syndrome */
81744 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_MASK)
81745 /*! @} */
81746 
81747 /*! @name CODE_TCM_ECC_SINGLE_ERROR_ADDR - Code TCM Single-Bit ECC Error Address */
81748 /*! @{ */
81749 
81750 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
81751 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_SHIFT (0U)
81752 /*! CODE_TCM_ECCS_ERRED_ADDR - Code TCM Single-Bit ECC Error Address */
81753 #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_MASK)
81754 /*! @} */
81755 
81756 /*! @name CODE_TCM_ECC_MULTI_ERROR_INFO - Code TCM Multibit ECC Error Information */
81757 /*! @{ */
81758 
81759 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_MASK (0xEU)
81760 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_SHIFT (1U)
81761 /*! CODE_TCM_ECCM_EFSIZ - Code TCM Multibit ECC Error for Corresponding TCM Access Size */
81762 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_MASK)
81763 
81764 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_MASK (0xF0U)
81765 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_SHIFT (4U)
81766 /*! CODE_TCM_ECCM_EFMST - Code TCM Multibit ECC Error for Corresponding TCM Master */
81767 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_MASK)
81768 
81769 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_MASK (0xF00U)
81770 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_SHIFT (8U)
81771 /*! CODE_TCM_ECCM_EFPRT - CODE_TCM Multibit ECC Error for Corresponding Access Protection Attribute */
81772 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_MASK)
81773 
81774 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_MASK (0x7F000U)
81775 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_SHIFT (12U)
81776 /*! CODE_TCM_ECCM_EFSYN - Code TCM Multibit ECC Error for Corresponding Syndrome */
81777 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_MASK)
81778 /*! @} */
81779 
81780 /*! @name CODE_TCM_ECC_MULTI_ERROR_ADDR - Code TCM Multibit ECC Error Address */
81781 /*! @{ */
81782 
81783 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
81784 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_SHIFT (0U)
81785 /*! CODE_TCM_ECCM_ERRED_ADDR - Code TCM Multibit ECC Error Address */
81786 #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_MASK)
81787 /*! @} */
81788 
81789 /*! @name SYS_TCM_ECC_SINGLE_ERROR_INFO - System TCM Single-Bit ECC Error Information */
81790 /*! @{ */
81791 
81792 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_MASK (0xEU)
81793 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_SHIFT (1U)
81794 /*! SYS_TCM_ECCS_EFSIZ - System TCM Single-Bit ECC Error for Corresponding TCM Access Size */
81795 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_MASK)
81796 
81797 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_MASK (0xF0U)
81798 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_SHIFT (4U)
81799 /*! SYS_TCM_ECCS_EFMST - System TCM Single-Bit ECC Error for Corresponding TCM Master */
81800 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_MASK)
81801 
81802 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_MASK (0xF00U)
81803 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_SHIFT (8U)
81804 /*! SYS_TCM_ECCS_EFPRT - System TCM Single-Bit ECC Error for Corresponding Access Protection Attribute */
81805 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_MASK)
81806 
81807 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_MASK (0x7F000U)
81808 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_SHIFT (12U)
81809 /*! SYS_TCM_ECCS_EFSYN - System TCM Single-Bit ECC Error for Corresponding Syndrome */
81810 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_MASK)
81811 /*! @} */
81812 
81813 /*! @name SYS_TCM_ECC_SINGLE_ERROR_ADDR - System TCM Single-Bit ECC Error Address */
81814 /*! @{ */
81815 
81816 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
81817 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_SHIFT (0U)
81818 /*! SYS_TCM_ECCS_ERRED_ADDR - System TCM Single-Bit ECC Error Address */
81819 #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_MASK)
81820 /*! @} */
81821 
81822 /*! @name SYS_TCM_ECC_MULTI_ERROR_INFO - System TCM Multibit ECC Error Information */
81823 /*! @{ */
81824 
81825 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_MASK (0xEU)
81826 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_SHIFT (1U)
81827 /*! SYS_TCM_ECCM_EFSIZ - System TCM Multibit ECC Error for Corresponding TCM Access Size */
81828 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_MASK)
81829 
81830 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_MASK (0xF0U)
81831 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_SHIFT (4U)
81832 /*! SYS_TCM_ECCM_EFMST - System TCM Multibit ECC Error for Corresponding TCM Master */
81833 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_MASK)
81834 
81835 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_MASK (0xF00U)
81836 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_SHIFT (8U)
81837 /*! SYS_TCM_ECCM_EFPRT - System TCM Multibit ECC Error for Corresponding Access Protection Attribute */
81838 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_MASK)
81839 
81840 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_MASK (0x7F000U)
81841 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_SHIFT (12U)
81842 /*! SYS_TCM_ECCM_EFSYN - System TCM Multibit ECC Error for Corresponding Syndrome */
81843 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_MASK)
81844 /*! @} */
81845 
81846 /*! @name SYS_TCM_ECC_MULTI_ERROR_ADDR - System TCM Multibit ECC Error Address */
81847 /*! @{ */
81848 
81849 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
81850 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_SHIFT (0U)
81851 /*! SYS_TCM_ECCM_ERRED_ADDR - System TCM Multibit ECC Error Address */
81852 #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_MASK)
81853 /*! @} */
81854 
81855 /*! @name CODE_TCM_ECC_ERROR_INJEC - Code TCM ECC Error Injection */
81856 /*! @{ */
81857 
81858 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_MASK (0xFFU)
81859 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_SHIFT (0U)
81860 /*! CODE_TCM_ERR1BIT - Position of First Bit to Inject ECC Error */
81861 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_MASK)
81862 
81863 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_MASK (0xFF00U)
81864 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_SHIFT (8U)
81865 /*! CODE_TCM_ERR2BIT - Position of Second Bit to Inject ECC Error */
81866 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_MASK)
81867 
81868 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_MASK (0x10000U)
81869 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_SHIFT (16U)
81870 /*! CODE_TCM_FR11BI - Force One 1-Bit Data Inversion on Code TCM Write Access
81871  *  0b0..Disable injection
81872  *  0b1..Enable injection
81873  */
81874 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_MASK)
81875 
81876 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_MASK (0x20000U)
81877 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_SHIFT (17U)
81878 /*! CODE_TCM_FR1NCI - Force One Noncorrectable Data Inversion on Code TCM Write Access
81879  *  0b0..Disable injection
81880  *  0b1..Enable injection
81881  */
81882 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_MASK)
81883 
81884 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_MASK (0x40000U)
81885 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_SHIFT (18U)
81886 /*! CODE_TCM_FRC1BI - Force Continuous 1-Bit Data Inversions on Code TCM Write Access
81887  *  0b0..Disable injection
81888  *  0b1..Enable injection
81889  */
81890 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_MASK)
81891 
81892 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_MASK (0x80000U)
81893 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_SHIFT (19U)
81894 /*! CODE_TCM_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code TCM Write Access
81895  *  0b0..Disable injection
81896  *  0b1..Enable injection
81897  */
81898 #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_MASK)
81899 /*! @} */
81900 
81901 /*! @name SYS_TCM_ECC_ERROR_INJEC - System TCM ECC Error Injection */
81902 /*! @{ */
81903 
81904 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_MASK (0xFFU)
81905 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_SHIFT (0U)
81906 /*! SYS_TCM_ERR1BIT - Position of First Bit to Inject ECC Error */
81907 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_MASK)
81908 
81909 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_MASK (0xFF00U)
81910 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_SHIFT (8U)
81911 /*! SYS_TCM_ERR2BIT - Position of Second Bit to Inject ECC Error */
81912 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_MASK)
81913 
81914 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_MASK (0x10000U)
81915 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_SHIFT (16U)
81916 /*! SYS_TCM_FR11BI - Force One 1-Bit Data Inversion on System TCM Write Access
81917  *  0b0..Disable injection
81918  *  0b1..Enable injection
81919  */
81920 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_MASK)
81921 
81922 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_MASK (0x20000U)
81923 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_SHIFT (17U)
81924 /*! SYS_TCM_FR1NCI - Force One Noncorrectable Data Inversion on System TCM Write Access
81925  *  0b0..Disable injection
81926  *  0b1..Enable injection
81927  */
81928 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_MASK)
81929 
81930 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_MASK (0x40000U)
81931 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_SHIFT (18U)
81932 /*! SYS_TCM_FRC1BI - Force Continuous 1-Bit Data Inversions on System TCM Write Access
81933  *  0b0..Disable injection
81934  *  0b1..Enable injection
81935  */
81936 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_MASK)
81937 
81938 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_MASK (0x80000U)
81939 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_SHIFT (19U)
81940 /*! SYS_TCM_FRCNCI - Force Continuous Noncorrectable Data Inversions on System TCM Write Access
81941  *  0b0..Disable injection
81942  *  0b1..Enable injection
81943  */
81944 #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_MASK)
81945 /*! @} */
81946 
81947 
81948 /*!
81949  * @}
81950  */ /* end of group TCM_ECC_MCM_Register_Masks */
81951 
81952 
81953 /* TCM_ECC_MCM - Peripheral instance base addresses */
81954 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
81955   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base address */
81956   #define CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE       (0x54420000u)
81957   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base address */
81958   #define CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE_NS    (0x44420000u)
81959   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base pointer */
81960   #define CP_CM33_IMX9RTC__CM33_TCM_MCM            ((TCM_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE)
81961   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base pointer */
81962   #define CP_CM33_IMX9RTC__CM33_TCM_MCM_NS         ((TCM_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE_NS)
81963   /** Array initializer of TCM_ECC_MCM peripheral base addresses */
81964   #define TCM_ECC_MCM_BASE_ADDRS                   { CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE }
81965   /** Array initializer of TCM_ECC_MCM peripheral base pointers */
81966   #define TCM_ECC_MCM_BASE_PTRS                    { CP_CM33_IMX9RTC__CM33_TCM_MCM }
81967   /** Array initializer of TCM_ECC_MCM peripheral base addresses */
81968   #define TCM_ECC_MCM_BASE_ADDRS_NS                { CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE_NS }
81969   /** Array initializer of TCM_ECC_MCM peripheral base pointers */
81970   #define TCM_ECC_MCM_BASE_PTRS_NS                 { CP_CM33_IMX9RTC__CM33_TCM_MCM_NS }
81971 #else
81972   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base address */
81973   #define CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE       (0x44420000u)
81974   /** Peripheral CP_CM33_IMX9RTC__CM33_TCM_MCM base pointer */
81975   #define CP_CM33_IMX9RTC__CM33_TCM_MCM            ((TCM_ECC_MCM_Type *)CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE)
81976   /** Array initializer of TCM_ECC_MCM peripheral base addresses */
81977   #define TCM_ECC_MCM_BASE_ADDRS                   { CP_CM33_IMX9RTC__CM33_TCM_MCM_BASE }
81978   /** Array initializer of TCM_ECC_MCM peripheral base pointers */
81979   #define TCM_ECC_MCM_BASE_PTRS                    { CP_CM33_IMX9RTC__CM33_TCM_MCM }
81980 #endif
81981 
81982 /*!
81983  * @}
81984  */ /* end of group TCM_ECC_MCM_Peripheral_Access_Layer */
81985 
81986 
81987 /* ----------------------------------------------------------------------------
81988    -- TMPSNS Peripheral Access Layer
81989    ---------------------------------------------------------------------------- */
81990 
81991 /*!
81992  * @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer
81993  * @{
81994  */
81995 
81996 /** TMPSNS - Register Layout Typedef */
81997 typedef struct {
81998        uint8_t RESERVED_0[16];
81999   __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x10 */
82000   __IO uint32_t CTRL1_SET;                         /**< Control 1, offset: 0x14 */
82001   __IO uint32_t CTRL1_CLR;                         /**< Control 1, offset: 0x18 */
82002   __IO uint32_t CTRL1_TOG;                         /**< Control 1, offset: 0x1C */
82003   __IO uint32_t RANGE0;                            /**< Range 0, offset: 0x20 */
82004   __IO uint32_t RANGE0_SET;                        /**< Range 0, offset: 0x24 */
82005   __IO uint32_t RANGE0_CLR;                        /**< Range 0, offset: 0x28 */
82006   __IO uint32_t RANGE0_TOG;                        /**< Range 0, offset: 0x2C */
82007   __IO uint32_t RANGE1;                            /**< Range 1, offset: 0x30 */
82008   __IO uint32_t RANGE1_SET;                        /**< Range 1, offset: 0x34 */
82009   __IO uint32_t RANGE1_CLR;                        /**< Range 1, offset: 0x38 */
82010   __IO uint32_t RANGE1_TOG;                        /**< Range 1, offset: 0x3C */
82011        uint8_t RESERVED_1[16];
82012   __IO uint32_t STATUS0;                           /**< Status 0, offset: 0x50 */
82013 } TMPSNS_Type;
82014 
82015 /* ----------------------------------------------------------------------------
82016    -- TMPSNS Register Masks
82017    ---------------------------------------------------------------------------- */
82018 
82019 /*!
82020  * @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks
82021  * @{
82022  */
82023 
82024 /*! @name CTRL1 - Control 1 */
82025 /*! @{ */
82026 
82027 #define TMPSNS_CTRL1_FREQ_MASK                   (0xFFFFU)
82028 #define TMPSNS_CTRL1_FREQ_SHIFT                  (0U)
82029 /*! FREQ - Temperature Measurement Frequency
82030  *  0b0000000000000000..Single Reading Mode. A new reading is available every time you change START from 0 to 1.
82031  *  0b0000000000000001-0b1111111111111111..Continuous Reading Mode. TMPSNS takes the next temperature reading when
82032  *                                         it completes the programmed number of cycles after the current reading.
82033  */
82034 #define TMPSNS_CTRL1_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
82035 
82036 #define TMPSNS_CTRL1_FINISH_IE_MASK              (0x10000U)
82037 #define TMPSNS_CTRL1_FINISH_IE_SHIFT             (16U)
82038 /*! FINISH_IE - Measurement Finished Interrupt Enable
82039  *  0b0..Disable
82040  *  0b1..Enable
82041  */
82042 #define TMPSNS_CTRL1_FINISH_IE(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
82043 
82044 #define TMPSNS_CTRL1_LOW_TEMP_IE_MASK            (0x20000U)
82045 #define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT           (17U)
82046 /*! LOW_TEMP_IE - Low Temperature Interrupt Enable
82047  *  0b0..Disable
82048  *  0b1..Enable
82049  */
82050 #define TMPSNS_CTRL1_LOW_TEMP_IE(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
82051 
82052 #define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK           (0x40000U)
82053 #define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT          (18U)
82054 /*! HIGH_TEMP_IE - High Temperature Interrupt Enable
82055  *  0b0..Disable
82056  *  0b1..Enable
82057  */
82058 #define TMPSNS_CTRL1_HIGH_TEMP_IE(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
82059 
82060 #define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK          (0x80000U)
82061 #define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT         (19U)
82062 /*! PANIC_TEMP_IE - Panic Temperature Interrupt Enable
82063  *  0b0..Disable
82064  *  0b1..Enable
82065  */
82066 #define TMPSNS_CTRL1_PANIC_TEMP_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
82067 
82068 #define TMPSNS_CTRL1_START_MASK                  (0x400000U)
82069 #define TMPSNS_CTRL1_START_SHIFT                 (22U)
82070 /*! START - Start Temperature Measurement
82071  *  0b0..No read
82072  *  0b1..New read
82073  */
82074 #define TMPSNS_CTRL1_START(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
82075 
82076 #define TMPSNS_CTRL1_PWD_MASK                    (0x800000U)
82077 #define TMPSNS_CTRL1_PWD_SHIFT                   (23U)
82078 /*! PWD - Power Down Except Bias Current
82079  *  0b0..Active
82080  *  0b1..Inactive
82081  */
82082 #define TMPSNS_CTRL1_PWD(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
82083 
82084 #define TMPSNS_CTRL1_PWD_FULL_MASK               (0x80000000U)
82085 #define TMPSNS_CTRL1_PWD_FULL_SHIFT              (31U)
82086 /*! PWD_FULL - Power Down
82087  *  0b0..Active
82088  *  0b1..Inactive
82089  */
82090 #define TMPSNS_CTRL1_PWD_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
82091 /*! @} */
82092 
82093 /*! @name CTRL1_SET - Control 1 */
82094 /*! @{ */
82095 
82096 #define TMPSNS_CTRL1_SET_FREQ_MASK               (0xFFFFU)
82097 #define TMPSNS_CTRL1_SET_FREQ_SHIFT              (0U)
82098 /*! FREQ - Temperature Measurement Frequency */
82099 #define TMPSNS_CTRL1_SET_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
82100 
82101 #define TMPSNS_CTRL1_SET_FINISH_IE_MASK          (0x10000U)
82102 #define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT         (16U)
82103 /*! FINISH_IE - Measurement Finished Interrupt Enable */
82104 #define TMPSNS_CTRL1_SET_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
82105 
82106 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK        (0x20000U)
82107 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT       (17U)
82108 /*! LOW_TEMP_IE - Low Temperature Interrupt Enable */
82109 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
82110 
82111 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK       (0x40000U)
82112 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT      (18U)
82113 /*! HIGH_TEMP_IE - High Temperature Interrupt Enable */
82114 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
82115 
82116 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK      (0x80000U)
82117 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT     (19U)
82118 /*! PANIC_TEMP_IE - Panic Temperature Interrupt Enable */
82119 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
82120 
82121 #define TMPSNS_CTRL1_SET_START_MASK              (0x400000U)
82122 #define TMPSNS_CTRL1_SET_START_SHIFT             (22U)
82123 /*! START - Start Temperature Measurement */
82124 #define TMPSNS_CTRL1_SET_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
82125 
82126 #define TMPSNS_CTRL1_SET_PWD_MASK                (0x800000U)
82127 #define TMPSNS_CTRL1_SET_PWD_SHIFT               (23U)
82128 /*! PWD - Power Down Except Bias Current */
82129 #define TMPSNS_CTRL1_SET_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
82130 
82131 #define TMPSNS_CTRL1_SET_PWD_FULL_MASK           (0x80000000U)
82132 #define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT          (31U)
82133 /*! PWD_FULL - Power Down */
82134 #define TMPSNS_CTRL1_SET_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
82135 /*! @} */
82136 
82137 /*! @name CTRL1_CLR - Control 1 */
82138 /*! @{ */
82139 
82140 #define TMPSNS_CTRL1_CLR_FREQ_MASK               (0xFFFFU)
82141 #define TMPSNS_CTRL1_CLR_FREQ_SHIFT              (0U)
82142 /*! FREQ - Temperature Measurement Frequency */
82143 #define TMPSNS_CTRL1_CLR_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
82144 
82145 #define TMPSNS_CTRL1_CLR_FINISH_IE_MASK          (0x10000U)
82146 #define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT         (16U)
82147 /*! FINISH_IE - Measurement Finished Interrupt Enable */
82148 #define TMPSNS_CTRL1_CLR_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
82149 
82150 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK        (0x20000U)
82151 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT       (17U)
82152 /*! LOW_TEMP_IE - Low Temperature Interrupt Enable */
82153 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
82154 
82155 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK       (0x40000U)
82156 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT      (18U)
82157 /*! HIGH_TEMP_IE - High Temperature Interrupt Enable */
82158 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
82159 
82160 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK      (0x80000U)
82161 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT     (19U)
82162 /*! PANIC_TEMP_IE - Panic Temperature Interrupt Enable */
82163 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
82164 
82165 #define TMPSNS_CTRL1_CLR_START_MASK              (0x400000U)
82166 #define TMPSNS_CTRL1_CLR_START_SHIFT             (22U)
82167 /*! START - Start Temperature Measurement */
82168 #define TMPSNS_CTRL1_CLR_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
82169 
82170 #define TMPSNS_CTRL1_CLR_PWD_MASK                (0x800000U)
82171 #define TMPSNS_CTRL1_CLR_PWD_SHIFT               (23U)
82172 /*! PWD - Power Down Except Bias Current */
82173 #define TMPSNS_CTRL1_CLR_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
82174 
82175 #define TMPSNS_CTRL1_CLR_PWD_FULL_MASK           (0x80000000U)
82176 #define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT          (31U)
82177 /*! PWD_FULL - Power Down */
82178 #define TMPSNS_CTRL1_CLR_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
82179 /*! @} */
82180 
82181 /*! @name CTRL1_TOG - Control 1 */
82182 /*! @{ */
82183 
82184 #define TMPSNS_CTRL1_TOG_FREQ_MASK               (0xFFFFU)
82185 #define TMPSNS_CTRL1_TOG_FREQ_SHIFT              (0U)
82186 /*! FREQ - Temperature Measurement Frequency */
82187 #define TMPSNS_CTRL1_TOG_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
82188 
82189 #define TMPSNS_CTRL1_TOG_FINISH_IE_MASK          (0x10000U)
82190 #define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT         (16U)
82191 /*! FINISH_IE - Measurement Finished Interrupt Enable */
82192 #define TMPSNS_CTRL1_TOG_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
82193 
82194 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK        (0x20000U)
82195 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT       (17U)
82196 /*! LOW_TEMP_IE - Low Temperature Interrupt Enable */
82197 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
82198 
82199 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK       (0x40000U)
82200 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT      (18U)
82201 /*! HIGH_TEMP_IE - High Temperature Interrupt Enable */
82202 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
82203 
82204 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK      (0x80000U)
82205 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT     (19U)
82206 /*! PANIC_TEMP_IE - Panic Temperature Interrupt Enable */
82207 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
82208 
82209 #define TMPSNS_CTRL1_TOG_START_MASK              (0x400000U)
82210 #define TMPSNS_CTRL1_TOG_START_SHIFT             (22U)
82211 /*! START - Start Temperature Measurement */
82212 #define TMPSNS_CTRL1_TOG_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
82213 
82214 #define TMPSNS_CTRL1_TOG_PWD_MASK                (0x800000U)
82215 #define TMPSNS_CTRL1_TOG_PWD_SHIFT               (23U)
82216 /*! PWD - Power Down Except Bias Current */
82217 #define TMPSNS_CTRL1_TOG_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
82218 
82219 #define TMPSNS_CTRL1_TOG_PWD_FULL_MASK           (0x80000000U)
82220 #define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT          (31U)
82221 /*! PWD_FULL - Power Down */
82222 #define TMPSNS_CTRL1_TOG_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
82223 /*! @} */
82224 
82225 /*! @name RANGE0 - Range 0 */
82226 /*! @{ */
82227 
82228 #define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK          (0xFFFU)
82229 #define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT         (0U)
82230 /*! LOW_TEMP_VAL - Low Temperature Threshold Value */
82231 #define TMPSNS_RANGE0_LOW_TEMP_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
82232 
82233 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK         (0xFFF0000U)
82234 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT        (16U)
82235 /*! HIGH_TEMP_VAL - High Temperature Threshold Value */
82236 #define TMPSNS_RANGE0_HIGH_TEMP_VAL(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
82237 /*! @} */
82238 
82239 /*! @name RANGE0_SET - Range 0 */
82240 /*! @{ */
82241 
82242 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK      (0xFFFU)
82243 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT     (0U)
82244 /*! LOW_TEMP_VAL - Low Temperature Threshold Value */
82245 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
82246 
82247 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
82248 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT    (16U)
82249 /*! HIGH_TEMP_VAL - High Temperature Threshold Value */
82250 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
82251 /*! @} */
82252 
82253 /*! @name RANGE0_CLR - Range 0 */
82254 /*! @{ */
82255 
82256 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK      (0xFFFU)
82257 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT     (0U)
82258 /*! LOW_TEMP_VAL - Low Temperature Threshold Value */
82259 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
82260 
82261 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
82262 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT    (16U)
82263 /*! HIGH_TEMP_VAL - High Temperature Threshold Value */
82264 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
82265 /*! @} */
82266 
82267 /*! @name RANGE0_TOG - Range 0 */
82268 /*! @{ */
82269 
82270 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK      (0xFFFU)
82271 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT     (0U)
82272 /*! LOW_TEMP_VAL - Low Temperature Threshold Value */
82273 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
82274 
82275 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
82276 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT    (16U)
82277 /*! HIGH_TEMP_VAL - High Temperature Threshold Value */
82278 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
82279 /*! @} */
82280 
82281 /*! @name RANGE1 - Range 1 */
82282 /*! @{ */
82283 
82284 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK        (0xFFFU)
82285 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT       (0U)
82286 /*! PANIC_TEMP_VAL - Panic Temperature Threshold Value */
82287 #define TMPSNS_RANGE1_PANIC_TEMP_VAL(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
82288 /*! @} */
82289 
82290 /*! @name RANGE1_SET - Range 1 */
82291 /*! @{ */
82292 
82293 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK    (0xFFFU)
82294 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT   (0U)
82295 /*! PANIC_TEMP_VAL - Panic Temperature Threshold Value */
82296 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
82297 /*! @} */
82298 
82299 /*! @name RANGE1_CLR - Range 1 */
82300 /*! @{ */
82301 
82302 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK    (0xFFFU)
82303 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT   (0U)
82304 /*! PANIC_TEMP_VAL - Panic Temperature Threshold Value */
82305 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
82306 /*! @} */
82307 
82308 /*! @name RANGE1_TOG - Range 1 */
82309 /*! @{ */
82310 
82311 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK    (0xFFFU)
82312 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT   (0U)
82313 /*! PANIC_TEMP_VAL - Panic Temperature Threshold Value */
82314 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
82315 /*! @} */
82316 
82317 /*! @name STATUS0 - Status 0 */
82318 /*! @{ */
82319 
82320 #define TMPSNS_STATUS0_TEMP_VAL_MASK             (0xFFFU)
82321 #define TMPSNS_STATUS0_TEMP_VAL_SHIFT            (0U)
82322 /*! TEMP_VAL - Measured Temperature Value */
82323 #define TMPSNS_STATUS0_TEMP_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
82324 
82325 #define TMPSNS_STATUS0_FINISH_MASK               (0x10000U)
82326 #define TMPSNS_STATUS0_FINISH_SHIFT              (16U)
82327 /*! FINISH - Temperature Measurement Complete
82328  *  0b0..No read
82329  *  0b1..New read
82330  */
82331 #define TMPSNS_STATUS0_FINISH(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
82332 
82333 #define TMPSNS_STATUS0_LOW_TEMP_MASK             (0x20000U)
82334 #define TMPSNS_STATUS0_LOW_TEMP_SHIFT            (17U)
82335 /*! LOW_TEMP - Low Temperature Alarm
82336  *  0b0..No alert
82337  *  0b1..Alert
82338  */
82339 #define TMPSNS_STATUS0_LOW_TEMP(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
82340 
82341 #define TMPSNS_STATUS0_HIGH_TEMP_MASK            (0x40000U)
82342 #define TMPSNS_STATUS0_HIGH_TEMP_SHIFT           (18U)
82343 /*! HIGH_TEMP - High Temperature Alarm
82344  *  0b0..No alert
82345  *  0b1..Alert
82346  */
82347 #define TMPSNS_STATUS0_HIGH_TEMP(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
82348 
82349 #define TMPSNS_STATUS0_PANIC_TEMP_MASK           (0x80000U)
82350 #define TMPSNS_STATUS0_PANIC_TEMP_SHIFT          (19U)
82351 /*! PANIC_TEMP - Panic Temperature Alarm
82352  *  0b0..No alert
82353  *  0b1..Alert
82354  */
82355 #define TMPSNS_STATUS0_PANIC_TEMP(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK)
82356 /*! @} */
82357 
82358 
82359 /*!
82360  * @}
82361  */ /* end of group TMPSNS_Register_Masks */
82362 
82363 
82364 /* TMPSNS - Peripheral instance base addresses */
82365 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82366   /** Peripheral TMPSNS base address */
82367   #define TMPSNS_BASE                              (0x54484580u)
82368   /** Peripheral TMPSNS base address */
82369   #define TMPSNS_BASE_NS                           (0x44484580u)
82370   /** Peripheral TMPSNS base pointer */
82371   #define TMPSNS                                   ((TMPSNS_Type *)TMPSNS_BASE)
82372   /** Peripheral TMPSNS base pointer */
82373   #define TMPSNS_NS                                ((TMPSNS_Type *)TMPSNS_BASE_NS)
82374   /** Array initializer of TMPSNS peripheral base addresses */
82375   #define TMPSNS_BASE_ADDRS                        { TMPSNS_BASE }
82376   /** Array initializer of TMPSNS peripheral base pointers */
82377   #define TMPSNS_BASE_PTRS                         { TMPSNS }
82378   /** Array initializer of TMPSNS peripheral base addresses */
82379   #define TMPSNS_BASE_ADDRS_NS                     { TMPSNS_BASE_NS }
82380   /** Array initializer of TMPSNS peripheral base pointers */
82381   #define TMPSNS_BASE_PTRS_NS                      { TMPSNS_NS }
82382 #else
82383   /** Peripheral TMPSNS base address */
82384   #define TMPSNS_BASE                              (0x44484580u)
82385   /** Peripheral TMPSNS base pointer */
82386   #define TMPSNS                                   ((TMPSNS_Type *)TMPSNS_BASE)
82387   /** Array initializer of TMPSNS peripheral base addresses */
82388   #define TMPSNS_BASE_ADDRS                        { TMPSNS_BASE }
82389   /** Array initializer of TMPSNS peripheral base pointers */
82390   #define TMPSNS_BASE_PTRS                         { TMPSNS }
82391 #endif
82392 
82393 /*!
82394  * @}
82395  */ /* end of group TMPSNS_Peripheral_Access_Layer */
82396 
82397 
82398 /* ----------------------------------------------------------------------------
82399    -- TMR Peripheral Access Layer
82400    ---------------------------------------------------------------------------- */
82401 
82402 /*!
82403  * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
82404  * @{
82405  */
82406 
82407 /** TMR - Register Layout Typedef */
82408 typedef struct {
82409   struct {                                         /* offset: 0x0, array step: 0x20 */
82410     __IO uint16_t COMP1;                             /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
82411     __IO uint16_t COMP2;                             /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
82412     __IO uint16_t CAPT;                              /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
82413     __IO uint16_t LOAD;                              /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
82414     __IO uint16_t HOLD;                              /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
82415     __IO uint16_t CNTR;                              /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
82416     __IO uint16_t CTRL;                              /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
82417     __IO uint16_t SCTRL;                             /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
82418     __IO uint16_t CMPLD1;                            /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
82419     __IO uint16_t CMPLD2;                            /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
82420     __IO uint16_t CSCTRL;                            /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
82421     __IO uint16_t FILT;                              /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
82422     __IO uint16_t DMA;                               /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
82423          uint8_t RESERVED_0[4];
82424     __IO uint16_t ENBL;                              /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, valid indices: [0] */
82425   } CHANNEL[4];
82426 } TMR_Type;
82427 
82428 /* ----------------------------------------------------------------------------
82429    -- TMR Register Masks
82430    ---------------------------------------------------------------------------- */
82431 
82432 /*!
82433  * @addtogroup TMR_Register_Masks TMR Register Masks
82434  * @{
82435  */
82436 
82437 /*! @name COMP1 - Timer Channel Compare Register 1 */
82438 /*! @{ */
82439 
82440 #define TMR_COMP1_COMPARISON_1_MASK              (0xFFFFU)
82441 #define TMR_COMP1_COMPARISON_1_SHIFT             (0U)
82442 /*! COMPARISON_1 - Comparison Value 1 */
82443 #define TMR_COMP1_COMPARISON_1(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
82444 /*! @} */
82445 
82446 /* The count of TMR_COMP1 */
82447 #define TMR_COMP1_COUNT                          (4U)
82448 
82449 /*! @name COMP2 - Timer Channel Compare Register 2 */
82450 /*! @{ */
82451 
82452 #define TMR_COMP2_COMPARISON_2_MASK              (0xFFFFU)
82453 #define TMR_COMP2_COMPARISON_2_SHIFT             (0U)
82454 /*! COMPARISON_2 - Comparison Value 2 */
82455 #define TMR_COMP2_COMPARISON_2(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
82456 /*! @} */
82457 
82458 /* The count of TMR_COMP2 */
82459 #define TMR_COMP2_COUNT                          (4U)
82460 
82461 /*! @name CAPT - Timer Channel Capture Register */
82462 /*! @{ */
82463 
82464 #define TMR_CAPT_CAPTURE_MASK                    (0xFFFFU)
82465 #define TMR_CAPT_CAPTURE_SHIFT                   (0U)
82466 /*! CAPTURE - Capture Value */
82467 #define TMR_CAPT_CAPTURE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
82468 /*! @} */
82469 
82470 /* The count of TMR_CAPT */
82471 #define TMR_CAPT_COUNT                           (4U)
82472 
82473 /*! @name LOAD - Timer Channel Load Register */
82474 /*! @{ */
82475 
82476 #define TMR_LOAD_LOAD_MASK                       (0xFFFFU)
82477 #define TMR_LOAD_LOAD_SHIFT                      (0U)
82478 /*! LOAD - Timer Load Register */
82479 #define TMR_LOAD_LOAD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
82480 /*! @} */
82481 
82482 /* The count of TMR_LOAD */
82483 #define TMR_LOAD_COUNT                           (4U)
82484 
82485 /*! @name HOLD - Timer Channel Hold Register */
82486 /*! @{ */
82487 
82488 #define TMR_HOLD_HOLD_MASK                       (0xFFFFU)
82489 #define TMR_HOLD_HOLD_SHIFT                      (0U)
82490 /*! HOLD - HOLD */
82491 #define TMR_HOLD_HOLD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
82492 /*! @} */
82493 
82494 /* The count of TMR_HOLD */
82495 #define TMR_HOLD_COUNT                           (4U)
82496 
82497 /*! @name CNTR - Timer Channel Counter Register */
82498 /*! @{ */
82499 
82500 #define TMR_CNTR_COUNTER_MASK                    (0xFFFFU)
82501 #define TMR_CNTR_COUNTER_SHIFT                   (0U)
82502 /*! COUNTER - COUNTER */
82503 #define TMR_CNTR_COUNTER(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
82504 /*! @} */
82505 
82506 /* The count of TMR_CNTR */
82507 #define TMR_CNTR_COUNT                           (4U)
82508 
82509 /*! @name CTRL - Timer Channel Control Register */
82510 /*! @{ */
82511 
82512 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
82513 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
82514 /*! OUTMODE - Output Mode
82515  *  0b000..Asserted while counter is active
82516  *  0b001..Clear OFLAG output on successful compare
82517  *  0b010..Set OFLAG output on successful compare
82518  *  0b011..Toggle OFLAG output on successful compare
82519  *  0b100..Toggle OFLAG output using alternating compare registers
82520  *  0b101..Set on compare, cleared on secondary source input edge
82521  *  0b110..Set on compare, cleared on counter rollover
82522  *  0b111..Enable gated clock output while counter is active
82523  */
82524 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
82525 
82526 #define TMR_CTRL_COINIT_MASK                     (0x8U)
82527 #define TMR_CTRL_COINIT_SHIFT                    (3U)
82528 /*! COINIT - Co-Channel Initialization
82529  *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
82530  *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
82531  */
82532 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
82533 
82534 #define TMR_CTRL_DIR_MASK                        (0x10U)
82535 #define TMR_CTRL_DIR_SHIFT                       (4U)
82536 /*! DIR - Count Direction
82537  *  0b0..Count up.
82538  *  0b1..Count down.
82539  */
82540 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
82541 
82542 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
82543 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
82544 /*! LENGTH - Count Length
82545  *  0b0..Count until roll over at $FFFF and then continue by re-initializing the counter from the LOAD register.
82546  *  0b1..Count until compare, then re-initialize using the LOAD register. If counting up, a successful compare
82547  *       occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter
82548  *       reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to
82549  *       generate successful comparisons. For example, the counter counts until a COMP1 value is reached,
82550  *       re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
82551  */
82552 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
82553 
82554 #define TMR_CTRL_ONCE_MASK                       (0x40U)
82555 #define TMR_CTRL_ONCE_SHIFT                      (6U)
82556 /*! ONCE - Count Once
82557  *  0b0..Count repeatedly.
82558  *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
82559  *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
82560  *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
82561  *       the COMP2 value, and then stops.
82562  */
82563 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
82564 
82565 #define TMR_CTRL_SCS_MASK                        (0x180U)
82566 #define TMR_CTRL_SCS_SHIFT                       (7U)
82567 /*! SCS - Secondary Count Source
82568  *  0b00..Counter 0 input pin
82569  *  0b01..Counter 1 input pin
82570  *  0b10..Counter 2 input pin
82571  *  0b11..Counter 3 input pin
82572  */
82573 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
82574 
82575 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
82576 #define TMR_CTRL_PCS_SHIFT                       (9U)
82577 /*! PCS - Primary Count Source
82578  *  0b0000..Counter 0 input pin
82579  *  0b0001..Counter 1 input pin
82580  *  0b0010..Counter 2 input pin
82581  *  0b0011..Counter 3 input pin
82582  *  0b0100..Counter 0 output
82583  *  0b0101..Counter 1 output
82584  *  0b0110..Counter 2 output
82585  *  0b0111..Counter 3 output
82586  *  0b1000..IP bus clock divide by 1 prescaler
82587  *  0b1001..IP bus clock divide by 2 prescaler
82588  *  0b1010..IP bus clock divide by 4 prescaler
82589  *  0b1011..IP bus clock divide by 8 prescaler
82590  *  0b1100..IP bus clock divide by 16 prescaler
82591  *  0b1101..IP bus clock divide by 32 prescaler
82592  *  0b1110..IP bus clock divide by 64 prescaler
82593  *  0b1111..IP bus clock divide by 128 prescaler
82594  */
82595 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
82596 
82597 #define TMR_CTRL_CM_MASK                         (0xE000U)
82598 #define TMR_CTRL_CM_SHIFT                        (13U)
82599 /*! CM - Count Mode
82600  *  0b000..No operation
82601  *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
82602  *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
82603  *         edges are counted regardless of the value of SCTRL[IPS].
82604  *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
82605  *  0b011..Count rising edges of primary source while secondary input high active
82606  *  0b100..Quadrature count mode, uses primary and secondary sources
82607  *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
82608  *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
82609  *  0b110..Edge of secondary source triggers primary count until compare
82610  *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
82611  */
82612 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
82613 /*! @} */
82614 
82615 /* The count of TMR_CTRL */
82616 #define TMR_CTRL_COUNT                           (4U)
82617 
82618 /*! @name SCTRL - Timer Channel Status and Control Register */
82619 /*! @{ */
82620 
82621 #define TMR_SCTRL_OEN_MASK                       (0x1U)
82622 #define TMR_SCTRL_OEN_SHIFT                      (0U)
82623 /*! OEN - Output Enable
82624  *  0b0..The external pin is configured as an input.
82625  *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
82626  *       their input see the driven value. The polarity of the signal is determined by OPS.
82627  */
82628 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
82629 
82630 #define TMR_SCTRL_OPS_MASK                       (0x2U)
82631 #define TMR_SCTRL_OPS_SHIFT                      (1U)
82632 /*! OPS - Output Polarity Select
82633  *  0b0..True polarity.
82634  *  0b1..Inverted polarity.
82635  */
82636 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
82637 
82638 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
82639 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
82640 /*! FORCE - Force OFLAG Output */
82641 #define TMR_SCTRL_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
82642 
82643 #define TMR_SCTRL_VAL_MASK                       (0x8U)
82644 #define TMR_SCTRL_VAL_SHIFT                      (3U)
82645 /*! VAL - Forced OFLAG Value */
82646 #define TMR_SCTRL_VAL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
82647 
82648 #define TMR_SCTRL_EEOF_MASK                      (0x10U)
82649 #define TMR_SCTRL_EEOF_SHIFT                     (4U)
82650 /*! EEOF - Enable External OFLAG Force */
82651 #define TMR_SCTRL_EEOF(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
82652 
82653 #define TMR_SCTRL_MSTR_MASK                      (0x20U)
82654 #define TMR_SCTRL_MSTR_SHIFT                     (5U)
82655 /*! MSTR - Master Mode */
82656 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
82657 
82658 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
82659 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
82660 /*! CAPTURE_MODE - Input Capture Mode
82661  *  0b00..Capture function is disabled
82662  *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
82663  *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
82664  *  0b11..Load capture register on both edges of input
82665  */
82666 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
82667 
82668 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
82669 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
82670 /*! INPUT - External Input Signal */
82671 #define TMR_SCTRL_INPUT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
82672 
82673 #define TMR_SCTRL_IPS_MASK                       (0x200U)
82674 #define TMR_SCTRL_IPS_SHIFT                      (9U)
82675 /*! IPS - Input Polarity Select */
82676 #define TMR_SCTRL_IPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
82677 
82678 #define TMR_SCTRL_IEFIE_MASK                     (0x400U)
82679 #define TMR_SCTRL_IEFIE_SHIFT                    (10U)
82680 /*! IEFIE - Input Edge Flag Interrupt Enable */
82681 #define TMR_SCTRL_IEFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
82682 
82683 #define TMR_SCTRL_IEF_MASK                       (0x800U)
82684 #define TMR_SCTRL_IEF_SHIFT                      (11U)
82685 /*! IEF - Input Edge Flag */
82686 #define TMR_SCTRL_IEF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
82687 
82688 #define TMR_SCTRL_TOFIE_MASK                     (0x1000U)
82689 #define TMR_SCTRL_TOFIE_SHIFT                    (12U)
82690 /*! TOFIE - Timer Overflow Flag Interrupt Enable */
82691 #define TMR_SCTRL_TOFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
82692 
82693 #define TMR_SCTRL_TOF_MASK                       (0x2000U)
82694 #define TMR_SCTRL_TOF_SHIFT                      (13U)
82695 /*! TOF - Timer Overflow Flag */
82696 #define TMR_SCTRL_TOF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
82697 
82698 #define TMR_SCTRL_TCFIE_MASK                     (0x4000U)
82699 #define TMR_SCTRL_TCFIE_SHIFT                    (14U)
82700 /*! TCFIE - Timer Compare Flag Interrupt Enable */
82701 #define TMR_SCTRL_TCFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
82702 
82703 #define TMR_SCTRL_TCF_MASK                       (0x8000U)
82704 #define TMR_SCTRL_TCF_SHIFT                      (15U)
82705 /*! TCF - Timer Compare Flag */
82706 #define TMR_SCTRL_TCF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
82707 /*! @} */
82708 
82709 /* The count of TMR_SCTRL */
82710 #define TMR_SCTRL_COUNT                          (4U)
82711 
82712 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
82713 /*! @{ */
82714 
82715 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK        (0xFFFFU)
82716 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT       (0U)
82717 /*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1 */
82718 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
82719 /*! @} */
82720 
82721 /* The count of TMR_CMPLD1 */
82722 #define TMR_CMPLD1_COUNT                         (4U)
82723 
82724 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
82725 /*! @{ */
82726 
82727 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK        (0xFFFFU)
82728 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT       (0U)
82729 /*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2 */
82730 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
82731 /*! @} */
82732 
82733 /* The count of TMR_CMPLD2 */
82734 #define TMR_CMPLD2_COUNT                         (4U)
82735 
82736 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
82737 /*! @{ */
82738 
82739 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
82740 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
82741 /*! CL1 - Compare Load Control 1
82742  *  0b00..Never preload
82743  *  0b01..Load upon successful compare with the value in COMP1
82744  *  0b10..Load upon successful compare with the value in COMP2
82745  *  0b11..Reserved
82746  */
82747 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
82748 
82749 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
82750 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
82751 /*! CL2 - Compare Load Control 2
82752  *  0b00..Never preload
82753  *  0b01..Load upon successful compare with the value in COMP1
82754  *  0b10..Load upon successful compare with the value in COMP2
82755  *  0b11..Reserved
82756  */
82757 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
82758 
82759 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
82760 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
82761 /*! TCF1 - Timer Compare 1 Interrupt Flag */
82762 #define TMR_CSCTRL_TCF1(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
82763 
82764 #define TMR_CSCTRL_TCF2_MASK                     (0x20U)
82765 #define TMR_CSCTRL_TCF2_SHIFT                    (5U)
82766 /*! TCF2 - Timer Compare 2 Interrupt Flag */
82767 #define TMR_CSCTRL_TCF2(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
82768 
82769 #define TMR_CSCTRL_TCF1EN_MASK                   (0x40U)
82770 #define TMR_CSCTRL_TCF1EN_SHIFT                  (6U)
82771 /*! TCF1EN - Timer Compare 1 Interrupt Enable */
82772 #define TMR_CSCTRL_TCF1EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
82773 
82774 #define TMR_CSCTRL_TCF2EN_MASK                   (0x80U)
82775 #define TMR_CSCTRL_TCF2EN_SHIFT                  (7U)
82776 /*! TCF2EN - Timer Compare 2 Interrupt Enable */
82777 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
82778 
82779 #define TMR_CSCTRL_UP_MASK                       (0x200U)
82780 #define TMR_CSCTRL_UP_SHIFT                      (9U)
82781 /*! UP - Counting Direction Indicator
82782  *  0b0..The last count was in the DOWN direction.
82783  *  0b1..The last count was in the UP direction.
82784  */
82785 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
82786 
82787 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
82788 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
82789 /*! TCI - Triggered Count Initialization Control
82790  *  0b0..Stop the counter upon receiving a second trigger event while still counting from the first trigger event.
82791  *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
82792  */
82793 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
82794 
82795 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
82796 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
82797 /*! ROC - Reload on Capture
82798  *  0b0..Disables
82799  *  0b1..Enables
82800  */
82801 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
82802 
82803 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
82804 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
82805 /*! ALT_LOAD - Alternative Load Enable
82806  *  0b0..Counter can be re-initialized only with the LOAD register.
82807  *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
82808  */
82809 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
82810 
82811 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
82812 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
82813 /*! FAULT - Fault Enable
82814  *  0b0..Disables
82815  *  0b1..Enables
82816  */
82817 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
82818 
82819 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
82820 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
82821 /*! DBG_EN - Debug Actions Enable
82822  *  0b00..Continue with normal operation during debug mode. (default)
82823  *  0b01..Halt TMR counter during debug mode.
82824  *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
82825  *  0b11..Both halt counter and force output to 0 during debug mode.
82826  */
82827 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
82828 /*! @} */
82829 
82830 /* The count of TMR_CSCTRL */
82831 #define TMR_CSCTRL_COUNT                         (4U)
82832 
82833 /*! @name FILT - Timer Channel Input Filter Register */
82834 /*! @{ */
82835 
82836 #define TMR_FILT_FILT_PER_MASK                   (0xFFU)
82837 #define TMR_FILT_FILT_PER_SHIFT                  (0U)
82838 /*! FILT_PER - Input Filter Sample Period */
82839 #define TMR_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
82840 
82841 #define TMR_FILT_FILT_CNT_MASK                   (0x700U)
82842 #define TMR_FILT_FILT_CNT_SHIFT                  (8U)
82843 /*! FILT_CNT - Input Filter Sample Count */
82844 #define TMR_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
82845 /*! @} */
82846 
82847 /* The count of TMR_FILT */
82848 #define TMR_FILT_COUNT                           (4U)
82849 
82850 /*! @name DMA - Timer Channel DMA Enable Register */
82851 /*! @{ */
82852 
82853 #define TMR_DMA_IEFDE_MASK                       (0x1U)
82854 #define TMR_DMA_IEFDE_SHIFT                      (0U)
82855 /*! IEFDE - Input Edge Flag DMA Enable */
82856 #define TMR_DMA_IEFDE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
82857 
82858 #define TMR_DMA_CMPLD1DE_MASK                    (0x2U)
82859 #define TMR_DMA_CMPLD1DE_SHIFT                   (1U)
82860 /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable */
82861 #define TMR_DMA_CMPLD1DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
82862 
82863 #define TMR_DMA_CMPLD2DE_MASK                    (0x4U)
82864 #define TMR_DMA_CMPLD2DE_SHIFT                   (2U)
82865 /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable */
82866 #define TMR_DMA_CMPLD2DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
82867 /*! @} */
82868 
82869 /* The count of TMR_DMA */
82870 #define TMR_DMA_COUNT                            (4U)
82871 
82872 /*! @name ENBL - Timer Channel Enable Register */
82873 /*! @{ */
82874 
82875 #define TMR_ENBL_ENBL_MASK                       (0xFU)
82876 #define TMR_ENBL_ENBL_SHIFT                      (0U)
82877 /*! ENBL - Timer Channel Enable
82878  *  0b0000..Disables the timer channel.
82879  *  0b0001..Enables the timer channel. (default)
82880  */
82881 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
82882 /*! @} */
82883 
82884 /* The count of TMR_ENBL */
82885 #define TMR_ENBL_COUNT                           (4U)
82886 
82887 
82888 /*!
82889  * @}
82890  */ /* end of group TMR_Register_Masks */
82891 
82892 
82893 /* TMR - Peripheral instance base addresses */
82894 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82895   /** Peripheral TMR1 base address */
82896   #define TMR1_BASE                                (0x52690000u)
82897   /** Peripheral TMR1 base address */
82898   #define TMR1_BASE_NS                             (0x42690000u)
82899   /** Peripheral TMR1 base pointer */
82900   #define TMR1                                     ((TMR_Type *)TMR1_BASE)
82901   /** Peripheral TMR1 base pointer */
82902   #define TMR1_NS                                  ((TMR_Type *)TMR1_BASE_NS)
82903   /** Peripheral TMR2 base address */
82904   #define TMR2_BASE                                (0x526A0000u)
82905   /** Peripheral TMR2 base address */
82906   #define TMR2_BASE_NS                             (0x426A0000u)
82907   /** Peripheral TMR2 base pointer */
82908   #define TMR2                                     ((TMR_Type *)TMR2_BASE)
82909   /** Peripheral TMR2 base pointer */
82910   #define TMR2_NS                                  ((TMR_Type *)TMR2_BASE_NS)
82911   /** Peripheral TMR3 base address */
82912   #define TMR3_BASE                                (0x526B0000u)
82913   /** Peripheral TMR3 base address */
82914   #define TMR3_BASE_NS                             (0x426B0000u)
82915   /** Peripheral TMR3 base pointer */
82916   #define TMR3                                     ((TMR_Type *)TMR3_BASE)
82917   /** Peripheral TMR3 base pointer */
82918   #define TMR3_NS                                  ((TMR_Type *)TMR3_BASE_NS)
82919   /** Peripheral TMR4 base address */
82920   #define TMR4_BASE                                (0x526C0000u)
82921   /** Peripheral TMR4 base address */
82922   #define TMR4_BASE_NS                             (0x426C0000u)
82923   /** Peripheral TMR4 base pointer */
82924   #define TMR4                                     ((TMR_Type *)TMR4_BASE)
82925   /** Peripheral TMR4 base pointer */
82926   #define TMR4_NS                                  ((TMR_Type *)TMR4_BASE_NS)
82927   /** Array initializer of TMR peripheral base addresses */
82928   #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
82929   /** Array initializer of TMR peripheral base pointers */
82930   #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
82931   /** Array initializer of TMR peripheral base addresses */
82932   #define TMR_BASE_ADDRS_NS                        { 0u, TMR1_BASE_NS, TMR2_BASE_NS, TMR3_BASE_NS, TMR4_BASE_NS }
82933   /** Array initializer of TMR peripheral base pointers */
82934   #define TMR_BASE_PTRS_NS                         { (TMR_Type *)0u, TMR1_NS, TMR2_NS, TMR3_NS, TMR4_NS }
82935 #else
82936   /** Peripheral TMR1 base address */
82937   #define TMR1_BASE                                (0x42690000u)
82938   /** Peripheral TMR1 base pointer */
82939   #define TMR1                                     ((TMR_Type *)TMR1_BASE)
82940   /** Peripheral TMR2 base address */
82941   #define TMR2_BASE                                (0x426A0000u)
82942   /** Peripheral TMR2 base pointer */
82943   #define TMR2                                     ((TMR_Type *)TMR2_BASE)
82944   /** Peripheral TMR3 base address */
82945   #define TMR3_BASE                                (0x426B0000u)
82946   /** Peripheral TMR3 base pointer */
82947   #define TMR3                                     ((TMR_Type *)TMR3_BASE)
82948   /** Peripheral TMR4 base address */
82949   #define TMR4_BASE                                (0x426C0000u)
82950   /** Peripheral TMR4 base pointer */
82951   #define TMR4                                     ((TMR_Type *)TMR4_BASE)
82952   /** Array initializer of TMR peripheral base addresses */
82953   #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
82954   /** Array initializer of TMR peripheral base pointers */
82955   #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
82956 #endif
82957 /** Interrupt vectors for the TMR peripheral type */
82958 #define TMR_IRQS                                 { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
82959 
82960 /*!
82961  * @}
82962  */ /* end of group TMR_Peripheral_Access_Layer */
82963 
82964 
82965 /* ----------------------------------------------------------------------------
82966    -- TPM Peripheral Access Layer
82967    ---------------------------------------------------------------------------- */
82968 
82969 /*!
82970  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
82971  * @{
82972  */
82973 
82974 /** TPM - Register Layout Typedef */
82975 typedef struct {
82976   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
82977   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
82978   __IO uint32_t GLOBAL;                            /**< TPM Global, offset: 0x8 */
82979        uint8_t RESERVED_0[4];
82980   __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
82981   __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
82982   __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
82983   __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
82984   struct {                                         /* offset: 0x20, array step: 0x8 */
82985     __IO uint32_t CnSC;                              /**< Channel n Status and Control, array offset: 0x20, array step: 0x8 */
82986     __IO uint32_t CnV;                               /**< Channel n Value, array offset: 0x24, array step: 0x8 */
82987   } CONTROLS[4];
82988        uint8_t RESERVED_1[36];
82989   __IO uint32_t COMBINE;                           /**< Combine Channel, offset: 0x64 */
82990        uint8_t RESERVED_2[4];
82991   __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
82992   __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
82993        uint8_t RESERVED_3[4];
82994   __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
82995        uint8_t RESERVED_4[4];
82996   __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
82997   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
82998 } TPM_Type;
82999 
83000 /* ----------------------------------------------------------------------------
83001    -- TPM Register Masks
83002    ---------------------------------------------------------------------------- */
83003 
83004 /*!
83005  * @addtogroup TPM_Register_Masks TPM Register Masks
83006  * @{
83007  */
83008 
83009 /*! @name VERID - Version ID */
83010 /*! @{ */
83011 
83012 #define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
83013 #define TPM_VERID_FEATURE_SHIFT                  (0U)
83014 /*! FEATURE - Feature Identification Number
83015  *  0b0000000000000001..Standard feature set
83016  *  0b0000000000000011..Standard feature set with the filter and combine registers implemented
83017  *  0b0000000000000101..Standard feature set with the quadrature register implemented
83018  *  0b0000000000000111..Standard feature set with the filter, combine, and quadrature registers implemented
83019  */
83020 #define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
83021 
83022 #define TPM_VERID_MINOR_MASK                     (0xFF0000U)
83023 #define TPM_VERID_MINOR_SHIFT                    (16U)
83024 /*! MINOR - Minor Version Number */
83025 #define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
83026 
83027 #define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
83028 #define TPM_VERID_MAJOR_SHIFT                    (24U)
83029 /*! MAJOR - Major Version Number */
83030 #define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
83031 /*! @} */
83032 
83033 /*! @name PARAM - Parameter */
83034 /*! @{ */
83035 
83036 #define TPM_PARAM_CHAN_MASK                      (0xFFU)
83037 #define TPM_PARAM_CHAN_SHIFT                     (0U)
83038 /*! CHAN - Channel Count */
83039 #define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
83040 
83041 #define TPM_PARAM_TRIG_MASK                      (0xFF00U)
83042 #define TPM_PARAM_TRIG_SHIFT                     (8U)
83043 /*! TRIG - Trigger Count */
83044 #define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
83045 
83046 #define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
83047 #define TPM_PARAM_WIDTH_SHIFT                    (16U)
83048 /*! WIDTH - Counter Width */
83049 #define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
83050 /*! @} */
83051 
83052 /*! @name GLOBAL - TPM Global */
83053 /*! @{ */
83054 
83055 #define TPM_GLOBAL_NOUPDATE_MASK                 (0x1U)
83056 #define TPM_GLOBAL_NOUPDATE_SHIFT                (0U)
83057 /*! NOUPDATE - No Update
83058  *  0b0..Internal double-buffered registers update as normal
83059  *  0b1..Internal double-buffered registers do not update
83060  */
83061 #define TPM_GLOBAL_NOUPDATE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK)
83062 
83063 #define TPM_GLOBAL_RST_MASK                      (0x2U)
83064 #define TPM_GLOBAL_RST_SHIFT                     (1U)
83065 /*! RST - Software Reset
83066  *  0b0..Module is not reset
83067  *  0b1..Module is reset
83068  */
83069 #define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
83070 /*! @} */
83071 
83072 /*! @name SC - Status and Control */
83073 /*! @{ */
83074 
83075 #define TPM_SC_PS_MASK                           (0x7U)
83076 #define TPM_SC_PS_SHIFT                          (0U)
83077 /*! PS - Prescale Factor Selection
83078  *  0b000..Divide by 1
83079  *  0b001..Divide by 2
83080  *  0b010..Divide by 4
83081  *  0b011..Divide by 8
83082  *  0b100..Divide by 16
83083  *  0b101..Divide by 32
83084  *  0b110..Divide by 64
83085  *  0b111..Divide by 128
83086  */
83087 #define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
83088 
83089 #define TPM_SC_CMOD_MASK                         (0x18U)
83090 #define TPM_SC_CMOD_SHIFT                        (3U)
83091 /*! CMOD - Clock Mode Selection
83092  *  0b00..TPM counter is disabled
83093  *  0b01..TPM counter increments on every TPM counter clock
83094  *  0b10..TPM counter increments on the rising edge of EXTCLK synchronized to the TPM counter clock
83095  *  0b11..TPM counter increments on the rising edge of the selected external input trigger
83096  */
83097 #define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
83098 
83099 #define TPM_SC_CPWMS_MASK                        (0x20U)
83100 #define TPM_SC_CPWMS_SHIFT                       (5U)
83101 /*! CPWMS - Center-Aligned PWM Select
83102  *  0b0..Up counting mode
83103  *  0b1..Up-down counting mode
83104  */
83105 #define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
83106 
83107 #define TPM_SC_TOIE_MASK                         (0x40U)
83108 #define TPM_SC_TOIE_SHIFT                        (6U)
83109 /*! TOIE - Timer Overflow Interrupt Enable
83110  *  0b0..Disable
83111  *  0b1..Enable
83112  */
83113 #define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
83114 
83115 #define TPM_SC_TOF_MASK                          (0x80U)
83116 #define TPM_SC_TOF_SHIFT                         (7U)
83117 /*! TOF - Timer Overflow Flag
83118  *  0b0..No overflow
83119  *  0b1..Overflow
83120  */
83121 #define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
83122 
83123 #define TPM_SC_DMA_MASK                          (0x100U)
83124 #define TPM_SC_DMA_SHIFT                         (8U)
83125 /*! DMA - DMA Enable
83126  *  0b0..Disable
83127  *  0b1..Enable
83128  */
83129 #define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
83130 /*! @} */
83131 
83132 /*! @name CNT - Counter */
83133 /*! @{ */
83134 
83135 #define TPM_CNT_COUNT_MASK                       (0xFFFFFFFFU)
83136 #define TPM_CNT_COUNT_SHIFT                      (0U)
83137 /*! COUNT - Counter Value */
83138 #define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
83139 /*! @} */
83140 
83141 /*! @name MOD - Modulo */
83142 /*! @{ */
83143 
83144 #define TPM_MOD_MOD_MASK                         (0xFFFFFFFFU)
83145 #define TPM_MOD_MOD_SHIFT                        (0U)
83146 /*! MOD - Modulo Value */
83147 #define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
83148 /*! @} */
83149 
83150 /*! @name STATUS - Capture and Compare Status */
83151 /*! @{ */
83152 
83153 #define TPM_STATUS_CH0F_MASK                     (0x1U)
83154 #define TPM_STATUS_CH0F_SHIFT                    (0U)
83155 /*! CH0F - Channel 0 Flag
83156  *  0b0..Event not occurred
83157  *  0b1..Event occurred
83158  */
83159 #define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
83160 
83161 #define TPM_STATUS_CH1F_MASK                     (0x2U)
83162 #define TPM_STATUS_CH1F_SHIFT                    (1U)
83163 /*! CH1F - Channel 1 Flag
83164  *  0b0..Event not occurred
83165  *  0b1..Event occurred
83166  */
83167 #define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
83168 
83169 #define TPM_STATUS_CH2F_MASK                     (0x4U)
83170 #define TPM_STATUS_CH2F_SHIFT                    (2U)
83171 /*! CH2F - Channel 2 Flag
83172  *  0b0..Event not occurred
83173  *  0b1..Event occurred
83174  */
83175 #define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
83176 
83177 #define TPM_STATUS_CH3F_MASK                     (0x8U)
83178 #define TPM_STATUS_CH3F_SHIFT                    (3U)
83179 /*! CH3F - Channel 3 Flag
83180  *  0b0..Event not occurred
83181  *  0b1..Event occurred
83182  */
83183 #define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
83184 
83185 #define TPM_STATUS_TOF_MASK                      (0x100U)
83186 #define TPM_STATUS_TOF_SHIFT                     (8U)
83187 /*! TOF - Timer Overflow Flag
83188  *  0b0..No overflow
83189  *  0b1..Overflow
83190  */
83191 #define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
83192 /*! @} */
83193 
83194 /*! @name CnSC - Channel n Status and Control */
83195 /*! @{ */
83196 
83197 #define TPM_CnSC_DMA_MASK                        (0x1U)
83198 #define TPM_CnSC_DMA_SHIFT                       (0U)
83199 /*! DMA - DMA Enable
83200  *  0b0..Disable
83201  *  0b1..Enable
83202  */
83203 #define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
83204 
83205 #define TPM_CnSC_ELSA_MASK                       (0x4U)
83206 #define TPM_CnSC_ELSA_SHIFT                      (2U)
83207 /*! ELSA - Edge or Level Select A */
83208 #define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
83209 
83210 #define TPM_CnSC_ELSB_MASK                       (0x8U)
83211 #define TPM_CnSC_ELSB_SHIFT                      (3U)
83212 /*! ELSB - Edge or Level Select B */
83213 #define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
83214 
83215 #define TPM_CnSC_MSA_MASK                        (0x10U)
83216 #define TPM_CnSC_MSA_SHIFT                       (4U)
83217 /*! MSA - Channel Mode Select A */
83218 #define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
83219 
83220 #define TPM_CnSC_MSB_MASK                        (0x20U)
83221 #define TPM_CnSC_MSB_SHIFT                       (5U)
83222 /*! MSB - Channel Mode Select B */
83223 #define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
83224 
83225 #define TPM_CnSC_CHIE_MASK                       (0x40U)
83226 #define TPM_CnSC_CHIE_SHIFT                      (6U)
83227 /*! CHIE - Channel Interrupt Enable
83228  *  0b0..Disable
83229  *  0b1..Enable
83230  */
83231 #define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
83232 
83233 #define TPM_CnSC_CHF_MASK                        (0x80U)
83234 #define TPM_CnSC_CHF_SHIFT                       (7U)
83235 /*! CHF - Channel Flag
83236  *  0b0..Event not occurred
83237  *  0b1..Event occurred
83238  */
83239 #define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
83240 /*! @} */
83241 
83242 /* The count of TPM_CnSC */
83243 #define TPM_CnSC_COUNT                           (4U)
83244 
83245 /*! @name CnV - Channel n Value */
83246 /*! @{ */
83247 
83248 #define TPM_CnV_VAL_MASK                         (0xFFFFFFFFU)
83249 #define TPM_CnV_VAL_SHIFT                        (0U)
83250 /*! VAL - Channel Value */
83251 #define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
83252 /*! @} */
83253 
83254 /* The count of TPM_CnV */
83255 #define TPM_CnV_COUNT                            (4U)
83256 
83257 /*! @name COMBINE - Combine Channel */
83258 /*! @{ */
83259 
83260 #define TPM_COMBINE_COMBINE0_MASK                (0x1U)
83261 #define TPM_COMBINE_COMBINE0_SHIFT               (0U)
83262 /*! COMBINE0 - Combine Channels 0 and 1
83263  *  0b0..Independent
83264  *  0b1..Combined
83265  */
83266 #define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
83267 
83268 #define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
83269 #define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
83270 /*! COMSWAP0 - Combine Channel 0 and 1 Swap
83271  *  0b0..Even channel
83272  *  0b1..Odd channel
83273  */
83274 #define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
83275 
83276 #define TPM_COMBINE_COMBINE1_MASK                (0x100U)
83277 #define TPM_COMBINE_COMBINE1_SHIFT               (8U)
83278 /*! COMBINE1 - Combine Channels 2 and 3
83279  *  0b0..Independent
83280  *  0b1..Combined
83281  */
83282 #define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
83283 
83284 #define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
83285 #define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
83286 /*! COMSWAP1 - Combine Channels 2 and 3 Swap
83287  *  0b0..Even channel
83288  *  0b1..Odd channel
83289  */
83290 #define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
83291 /*! @} */
83292 
83293 /*! @name TRIG - Channel Trigger */
83294 /*! @{ */
83295 
83296 #define TPM_TRIG_TRIG0_MASK                      (0x1U)
83297 #define TPM_TRIG_TRIG0_SHIFT                     (0U)
83298 /*! TRIG0 - Channel 0 Trigger
83299  *  0b0..No effect
83300  *  0b1..Configures trigger input 0 to be used by channel 0
83301  */
83302 #define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
83303 
83304 #define TPM_TRIG_TRIG1_MASK                      (0x2U)
83305 #define TPM_TRIG_TRIG1_SHIFT                     (1U)
83306 /*! TRIG1 - Channel 1 Trigger
83307  *  0b0..No effect
83308  *  0b1..Configures trigger input 1 to be used by channel 1
83309  */
83310 #define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
83311 
83312 #define TPM_TRIG_TRIG2_MASK                      (0x4U)
83313 #define TPM_TRIG_TRIG2_SHIFT                     (2U)
83314 /*! TRIG2 - Channel 2 Trigger
83315  *  0b0..No effect
83316  *  0b1..Configures trigger input 0 to be used by channel 2
83317  */
83318 #define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
83319 
83320 #define TPM_TRIG_TRIG3_MASK                      (0x8U)
83321 #define TPM_TRIG_TRIG3_SHIFT                     (3U)
83322 /*! TRIG3 - Channel 3 Trigger
83323  *  0b0..No effect
83324  *  0b1..Configures trigger input 1 to be used by channel 3
83325  */
83326 #define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
83327 /*! @} */
83328 
83329 /*! @name POL - Channel Polarity */
83330 /*! @{ */
83331 
83332 #define TPM_POL_POL0_MASK                        (0x1U)
83333 #define TPM_POL_POL0_SHIFT                       (0U)
83334 /*! POL0 - Channel 0 Polarity
83335  *  0b0..Active high
83336  *  0b1..Active low
83337  */
83338 #define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
83339 
83340 #define TPM_POL_POL1_MASK                        (0x2U)
83341 #define TPM_POL_POL1_SHIFT                       (1U)
83342 /*! POL1 - Channel 1 Polarity
83343  *  0b0..Active high
83344  *  0b1..Active low
83345  */
83346 #define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
83347 
83348 #define TPM_POL_POL2_MASK                        (0x4U)
83349 #define TPM_POL_POL2_SHIFT                       (2U)
83350 /*! POL2 - Channel 2 Polarity
83351  *  0b0..Active high
83352  *  0b1..Active low
83353  */
83354 #define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
83355 
83356 #define TPM_POL_POL3_MASK                        (0x8U)
83357 #define TPM_POL_POL3_SHIFT                       (3U)
83358 /*! POL3 - Channel 3 Polarity
83359  *  0b0..Active high
83360  *  0b1..Active low
83361  */
83362 #define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
83363 /*! @} */
83364 
83365 /*! @name FILTER - Filter Control */
83366 /*! @{ */
83367 
83368 #define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
83369 #define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
83370 /*! CH0FVAL - Channel 0 Filter Value */
83371 #define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
83372 
83373 #define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
83374 #define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
83375 /*! CH1FVAL - Channel 1 Filter Value */
83376 #define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
83377 
83378 #define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
83379 #define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
83380 /*! CH2FVAL - Channel 2 Filter Value */
83381 #define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
83382 
83383 #define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
83384 #define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
83385 /*! CH3FVAL - Channel 3 Filter Value */
83386 #define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
83387 /*! @} */
83388 
83389 /*! @name QDCTRL - Quadrature Decoder Control and Status */
83390 /*! @{ */
83391 
83392 #define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
83393 #define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
83394 /*! QUADEN - Quadrature Decoder Enable
83395  *  0b0..Disable
83396  *  0b1..Enable
83397  */
83398 #define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
83399 
83400 #define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
83401 #define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
83402 /*! TOFDIR - Timer Overflow Direction
83403  *  0b0..Bottom of counting
83404  *  0b1..Top of counting
83405  */
83406 #define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
83407 
83408 #define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
83409 #define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
83410 /*! QUADIR - Counter Direction in Quadrature Decode Mode
83411  *  0b0..Decreasing (counter decrement)
83412  *  0b1..Increasing (counter increment)
83413  */
83414 #define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
83415 
83416 #define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
83417 #define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
83418 /*! QUADMODE - Quadrature Decoder Mode
83419  *  0b0..Phase encoding mode
83420  *  0b1..Count and direction encoding mode
83421  */
83422 #define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
83423 /*! @} */
83424 
83425 /*! @name CONF - Configuration */
83426 /*! @{ */
83427 
83428 #define TPM_CONF_DOZEEN_MASK                     (0x20U)
83429 #define TPM_CONF_DOZEEN_SHIFT                    (5U)
83430 /*! DOZEEN - Doze Enable
83431  *  0b0..TPM counter continues
83432  *  0b1..TPM counter pauses
83433  */
83434 #define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
83435 
83436 #define TPM_CONF_DBGMODE_MASK                    (0xC0U)
83437 #define TPM_CONF_DBGMODE_SHIFT                   (6U)
83438 /*! DBGMODE - Debug Mode
83439  *  0b00..TPM counter pauses
83440  *  0b11..TPM counter continues
83441  */
83442 #define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
83443 
83444 #define TPM_CONF_GTBSYNC_MASK                    (0x100U)
83445 #define TPM_CONF_GTBSYNC_SHIFT                   (8U)
83446 /*! GTBSYNC - GTB Synchronization
83447  *  0b0..Disable
83448  *  0b1..Enable
83449  */
83450 #define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
83451 
83452 #define TPM_CONF_GTBEEN_MASK                     (0x200U)
83453 #define TPM_CONF_GTBEEN_SHIFT                    (9U)
83454 /*! GTBEEN - GTB Enable
83455  *  0b0..Internally generated TPM counter
83456  *  0b1..Externally generated GTB counter
83457  */
83458 #define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
83459 
83460 #define TPM_CONF_CSOT_MASK                       (0x10000U)
83461 #define TPM_CONF_CSOT_SHIFT                      (16U)
83462 /*! CSOT - Counter Start on Trigger
83463  *  0b0..Counter starts immediately
83464  *  0b1..Counter starts after detection of a rising edge on the selected input trigger
83465  */
83466 #define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
83467 
83468 #define TPM_CONF_CSOO_MASK                       (0x20000U)
83469 #define TPM_CONF_CSOO_SHIFT                      (17U)
83470 /*! CSOO - Counter Stop on Overflow
83471  *  0b0..TPM counter continues
83472  *  0b1..TPM counter stops
83473  */
83474 #define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
83475 
83476 #define TPM_CONF_CROT_MASK                       (0x40000U)
83477 #define TPM_CONF_CROT_SHIFT                      (18U)
83478 /*! CROT - Counter Reload on Trigger
83479  *  0b0..No reload
83480  *  0b1..Reload
83481  */
83482 #define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
83483 
83484 #define TPM_CONF_CPOT_MASK                       (0x80000U)
83485 #define TPM_CONF_CPOT_SHIFT                      (19U)
83486 /*! CPOT - Counter Pause on Trigger
83487  *  0b0..TPM counter continues
83488  *  0b1..TPM counter pauses
83489  */
83490 #define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
83491 
83492 #define TPM_CONF_TRGPOL_MASK                     (0x400000U)
83493 #define TPM_CONF_TRGPOL_SHIFT                    (22U)
83494 /*! TRGPOL - Trigger Polarity
83495  *  0b0..Active high
83496  *  0b1..Active low
83497  */
83498 #define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
83499 
83500 #define TPM_CONF_TRGSRC_MASK                     (0x800000U)
83501 #define TPM_CONF_TRGSRC_SHIFT                    (23U)
83502 /*! TRGSRC - Trigger Source
83503  *  0b0..External
83504  *  0b1..Internal (channel pin input capture)
83505  */
83506 #define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
83507 
83508 #define TPM_CONF_TRGSEL_MASK                     (0x3000000U)
83509 #define TPM_CONF_TRGSEL_SHIFT                    (24U)
83510 /*! TRGSEL - Trigger Select
83511  *  0b01..Channel 0 pin input capture
83512  *  0b10..Channel 1 pin input capture
83513  *  0b11..Channel 0 or channel 1 pin input capture
83514  */
83515 #define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
83516 /*! @} */
83517 
83518 
83519 /*!
83520  * @}
83521  */ /* end of group TPM_Register_Masks */
83522 
83523 
83524 /* TPM - Peripheral instance base addresses */
83525 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
83526   /** Peripheral TPM1 base address */
83527   #define TPM1_BASE                                (0x54310000u)
83528   /** Peripheral TPM1 base address */
83529   #define TPM1_BASE_NS                             (0x44310000u)
83530   /** Peripheral TPM1 base pointer */
83531   #define TPM1                                     ((TPM_Type *)TPM1_BASE)
83532   /** Peripheral TPM1 base pointer */
83533   #define TPM1_NS                                  ((TPM_Type *)TPM1_BASE_NS)
83534   /** Peripheral TPM2 base address */
83535   #define TPM2_BASE                                (0x54320000u)
83536   /** Peripheral TPM2 base address */
83537   #define TPM2_BASE_NS                             (0x44320000u)
83538   /** Peripheral TPM2 base pointer */
83539   #define TPM2                                     ((TPM_Type *)TPM2_BASE)
83540   /** Peripheral TPM2 base pointer */
83541   #define TPM2_NS                                  ((TPM_Type *)TPM2_BASE_NS)
83542   /** Peripheral TPM3 base address */
83543   #define TPM3_BASE                                (0x524E0000u)
83544   /** Peripheral TPM3 base address */
83545   #define TPM3_BASE_NS                             (0x424E0000u)
83546   /** Peripheral TPM3 base pointer */
83547   #define TPM3                                     ((TPM_Type *)TPM3_BASE)
83548   /** Peripheral TPM3 base pointer */
83549   #define TPM3_NS                                  ((TPM_Type *)TPM3_BASE_NS)
83550   /** Array initializer of TPM peripheral base addresses */
83551   #define TPM_BASE_ADDRS                           { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE }
83552   /** Array initializer of TPM peripheral base pointers */
83553   #define TPM_BASE_PTRS                            { (TPM_Type *)0u, TPM1, TPM2, TPM3 }
83554   /** Array initializer of TPM peripheral base addresses */
83555   #define TPM_BASE_ADDRS_NS                        { 0u, TPM1_BASE_NS, TPM2_BASE_NS, TPM3_BASE_NS }
83556   /** Array initializer of TPM peripheral base pointers */
83557   #define TPM_BASE_PTRS_NS                         { (TPM_Type *)0u, TPM1_NS, TPM2_NS, TPM3_NS }
83558 #else
83559   /** Peripheral TPM1 base address */
83560   #define TPM1_BASE                                (0x44310000u)
83561   /** Peripheral TPM1 base pointer */
83562   #define TPM1                                     ((TPM_Type *)TPM1_BASE)
83563   /** Peripheral TPM2 base address */
83564   #define TPM2_BASE                                (0x44320000u)
83565   /** Peripheral TPM2 base pointer */
83566   #define TPM2                                     ((TPM_Type *)TPM2_BASE)
83567   /** Peripheral TPM3 base address */
83568   #define TPM3_BASE                                (0x424E0000u)
83569   /** Peripheral TPM3 base pointer */
83570   #define TPM3                                     ((TPM_Type *)TPM3_BASE)
83571   /** Array initializer of TPM peripheral base addresses */
83572   #define TPM_BASE_ADDRS                           { 0u, TPM1_BASE, TPM2_BASE, TPM3_BASE }
83573   /** Array initializer of TPM peripheral base pointers */
83574   #define TPM_BASE_PTRS                            { (TPM_Type *)0u, TPM1, TPM2, TPM3 }
83575 #endif
83576 /** Interrupt vectors for the TPM peripheral type */
83577 #define TPM_IRQS                                 { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn }
83578 
83579 /*!
83580  * @}
83581  */ /* end of group TPM_Peripheral_Access_Layer */
83582 
83583 
83584 /* ----------------------------------------------------------------------------
83585    -- TRDC Peripheral Access Layer
83586    ---------------------------------------------------------------------------- */
83587 
83588 /*!
83589  * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer
83590  * @{
83591  */
83592 
83593 /** TRDC - Register Layout Typedef */
83594 typedef struct {
83595   __IO uint32_t TRDC_CR;                           /**< TRDC Register, offset: 0x0 */
83596        uint8_t RESERVED_0[236];
83597   __I  uint32_t TRDC_HWCFG0;                       /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */
83598   __I  uint32_t TRDC_HWCFG1;                       /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */
83599   __I  uint32_t TRDC_HWCFG2;                       /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */
83600   __I  uint32_t TRDC_HWCFG3;                       /**< TRDC Hardware Configuration Register 3, offset: 0xFC */
83601   __I  uint8_t DACFG[6];                           /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1, irregular array, not all indices are valid */
83602        uint8_t RESERVED_1[186];
83603   __IO uint32_t TRDC_IDAU_CR;                      /**< TRDC IDAU Control Register, offset: 0x1C0 */
83604        uint8_t RESERVED_2[28];
83605   __IO uint32_t TRDC_FLW_CTL;                      /**< TRDC FLW Control, offset: 0x1E0 */
83606   __I  uint32_t TRDC_FLW_PBASE;                    /**< TRDC FLW Physical Base, offset: 0x1E4 */
83607   __IO uint32_t TRDC_FLW_ABASE;                    /**< TRDC FLW Array Base, offset: 0x1E8 */
83608   __IO uint32_t TRDC_FLW_BCNT;                     /**< TRDC FLW Block Count, offset: 0x1EC */
83609        uint8_t RESERVED_3[12];
83610   __IO uint32_t TRDC_FDID;                         /**< TRDC Fault Domain ID, offset: 0x1FC */
83611   __I  uint32_t TRDC_DERRLOC[16];                  /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */
83612        uint8_t RESERVED_4[448];
83613   struct {                                         /* offset: 0x400, array step: 0x10 */
83614     __I  uint32_t W0;                                /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83615     __I  uint32_t W1;                                /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83616          uint8_t RESERVED_0[4];
83617     __O  uint32_t W3;                                /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83618   } MBC_DERR[2];
83619        uint8_t RESERVED_5[96];
83620   struct {                                         /* offset: 0x480, array step: 0x10 */
83621     __I  uint32_t W0;                                /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10, irregular array, not all indices are valid */
83622     __I  uint32_t W1;                                /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10, irregular array, not all indices are valid */
83623          uint8_t RESERVED_0[4];
83624     __O  uint32_t W3;                                /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10, irregular array, not all indices are valid */
83625   } MRC_DERR[7];
83626        uint8_t RESERVED_6[528];
83627   __IO uint32_t PID[2];                            /**< Process Identifier, array offset: 0x700, array step: 0x4, available only on: TRDC1 (missing on TRDC2, TRDC3) */
83628        uint8_t RESERVED_7[248];
83629   union {                                          /* offset: 0x800 */
83630     struct {                                         /* offset: 0x800, array step: 0x20 */
83631       __IO uint32_t MDA_W_DFMT0[7];                    /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, irregular array, not all indices are valid */
83632            uint8_t RESERVED_0[4];
83633     } MDA_DFMT0[6];
83634     struct {                                         /* offset: 0x800, array step: 0x20 */
83635       __IO uint32_t MDA_W_DFMT1[1];                    /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, irregular array, not all indices are valid */
83636            uint8_t RESERVED_0[28];
83637     } MDA_DFMT1[5];
83638   };
83639        uint8_t RESERVED_8[63296];
83640   struct {                                         /* offset: 0x10000, array step: 0x2000 */
83641     __I  uint32_t MBC_MEM_GLBCFG[4];                 /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83642     __IO uint32_t MBC_NSE_BLK_INDEX;                 /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83643     __O  uint32_t MBC_NSE_BLK_SET;                   /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83644     __O  uint32_t MBC_NSE_BLK_CLR;                   /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83645     __O  uint32_t MBC_NSE_BLK_CLR_ALL;               /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83646     __IO uint32_t MBC_MEMN_GLBAC[8];                 /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83647     __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83648          uint8_t RESERVED_0[192];
83649     __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83650          uint8_t RESERVED_1[48];
83651     __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83652          uint8_t RESERVED_2[16];
83653     __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83654          uint8_t RESERVED_3[4];
83655     __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83656          uint8_t RESERVED_4[28];
83657     __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83658          uint8_t RESERVED_5[4];
83659     __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83660          uint8_t RESERVED_6[20];
83661     __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83662          uint8_t RESERVED_7[76];
83663     __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83664          uint8_t RESERVED_8[192];
83665     __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83666          uint8_t RESERVED_9[48];
83667     __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83668          uint8_t RESERVED_10[16];
83669     __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83670          uint8_t RESERVED_11[4];
83671     __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83672          uint8_t RESERVED_12[28];
83673     __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83674          uint8_t RESERVED_13[4];
83675     __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83676          uint8_t RESERVED_14[20];
83677     __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83678          uint8_t RESERVED_15[76];
83679     __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83680          uint8_t RESERVED_16[192];
83681     __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83682          uint8_t RESERVED_17[48];
83683     __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83684          uint8_t RESERVED_18[16];
83685     __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83686          uint8_t RESERVED_19[4];
83687     __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83688          uint8_t RESERVED_20[28];
83689     __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83690          uint8_t RESERVED_21[4];
83691     __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83692          uint8_t RESERVED_22[20];
83693     __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83694          uint8_t RESERVED_23[76];
83695     __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83696          uint8_t RESERVED_24[192];
83697     __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83698          uint8_t RESERVED_25[48];
83699     __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83700          uint8_t RESERVED_26[16];
83701     __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83702          uint8_t RESERVED_27[4];
83703     __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83704          uint8_t RESERVED_28[28];
83705     __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83706          uint8_t RESERVED_29[4];
83707     __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83708          uint8_t RESERVED_30[20];
83709     __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83710          uint8_t RESERVED_31[76];
83711     __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83712          uint8_t RESERVED_32[192];
83713     __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83714          uint8_t RESERVED_33[48];
83715     __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83716          uint8_t RESERVED_34[16];
83717     __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83718          uint8_t RESERVED_35[4];
83719     __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83720          uint8_t RESERVED_36[28];
83721     __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83722          uint8_t RESERVED_37[4];
83723     __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83724          uint8_t RESERVED_38[20];
83725     __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83726          uint8_t RESERVED_39[76];
83727     __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83728          uint8_t RESERVED_40[192];
83729     __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83730          uint8_t RESERVED_41[48];
83731     __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83732          uint8_t RESERVED_42[16];
83733     __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83734          uint8_t RESERVED_43[4];
83735     __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83736          uint8_t RESERVED_44[28];
83737     __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83738          uint8_t RESERVED_45[4];
83739     __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83740          uint8_t RESERVED_46[20];
83741     __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83742          uint8_t RESERVED_47[76];
83743     __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83744          uint8_t RESERVED_48[192];
83745     __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83746          uint8_t RESERVED_49[48];
83747     __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83748          uint8_t RESERVED_50[16];
83749     __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83750          uint8_t RESERVED_51[4];
83751     __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83752          uint8_t RESERVED_52[28];
83753     __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83754          uint8_t RESERVED_53[4];
83755     __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83756          uint8_t RESERVED_54[20];
83757     __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83758          uint8_t RESERVED_55[76];
83759     __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83760          uint8_t RESERVED_56[192];
83761     __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83762          uint8_t RESERVED_57[48];
83763     __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83764          uint8_t RESERVED_58[16];
83765     __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83766          uint8_t RESERVED_59[4];
83767     __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83768          uint8_t RESERVED_60[28];
83769     __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83770          uint8_t RESERVED_61[4];
83771     __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83772          uint8_t RESERVED_62[20];
83773     __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83774          uint8_t RESERVED_63[76];
83775     __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83776          uint8_t RESERVED_64[192];
83777     __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83778          uint8_t RESERVED_65[48];
83779     __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83780          uint8_t RESERVED_66[16];
83781     __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83782          uint8_t RESERVED_67[4];
83783     __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83784          uint8_t RESERVED_68[28];
83785     __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83786          uint8_t RESERVED_69[4];
83787     __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83788          uint8_t RESERVED_70[20];
83789     __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83790          uint8_t RESERVED_71[76];
83791     __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[16];       /**< MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83792          uint8_t RESERVED_72[192];
83793     __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[4];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83794          uint8_t RESERVED_73[48];
83795     __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[4];        /**< MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83796          uint8_t RESERVED_74[16];
83797     __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83798          uint8_t RESERVED_75[4];
83799     __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83800          uint8_t RESERVED_76[28];
83801     __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83802          uint8_t RESERVED_77[4];
83803     __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[3];        /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83804          uint8_t RESERVED_78[20];
83805     __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83806          uint8_t RESERVED_79[76];
83807     __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83808          uint8_t RESERVED_80[192];
83809     __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83810          uint8_t RESERVED_81[48];
83811     __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83812          uint8_t RESERVED_82[16];
83813     __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83814          uint8_t RESERVED_83[4];
83815     __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83816          uint8_t RESERVED_84[28];
83817     __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83818          uint8_t RESERVED_85[4];
83819     __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83820          uint8_t RESERVED_86[20];
83821     __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83822          uint8_t RESERVED_87[76];
83823     __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83824          uint8_t RESERVED_88[192];
83825     __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83826          uint8_t RESERVED_89[48];
83827     __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83828          uint8_t RESERVED_90[16];
83829     __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83830          uint8_t RESERVED_91[4];
83831     __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83832          uint8_t RESERVED_92[28];
83833     __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83834          uint8_t RESERVED_93[4];
83835     __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83836          uint8_t RESERVED_94[20];
83837     __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83838          uint8_t RESERVED_95[76];
83839     __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83840          uint8_t RESERVED_96[192];
83841     __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83842          uint8_t RESERVED_97[48];
83843     __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83844          uint8_t RESERVED_98[16];
83845     __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83846          uint8_t RESERVED_99[4];
83847     __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83848          uint8_t RESERVED_100[28];
83849     __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83850          uint8_t RESERVED_101[4];
83851     __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83852          uint8_t RESERVED_102[20];
83853     __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83854          uint8_t RESERVED_103[76];
83855     __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83856          uint8_t RESERVED_104[192];
83857     __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83858          uint8_t RESERVED_105[48];
83859     __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83860          uint8_t RESERVED_106[16];
83861     __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83862          uint8_t RESERVED_107[4];
83863     __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83864          uint8_t RESERVED_108[28];
83865     __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83866          uint8_t RESERVED_109[4];
83867     __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83868          uint8_t RESERVED_110[20];
83869     __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83870          uint8_t RESERVED_111[76];
83871     __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83872          uint8_t RESERVED_112[192];
83873     __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83874          uint8_t RESERVED_113[48];
83875     __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83876          uint8_t RESERVED_114[16];
83877     __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83878          uint8_t RESERVED_115[4];
83879     __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83880          uint8_t RESERVED_116[28];
83881     __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83882          uint8_t RESERVED_117[4];
83883     __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83884          uint8_t RESERVED_118[20];
83885     __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83886          uint8_t RESERVED_119[76];
83887     __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[16];      /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83888          uint8_t RESERVED_120[192];
83889     __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[4];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83890          uint8_t RESERVED_121[48];
83891     __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[4];       /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83892          uint8_t RESERVED_122[16];
83893     __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4, available only on: TRDC1, TRDC2 (missing on TRDC3) */
83894          uint8_t RESERVED_123[4];
83895     __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[1];       /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83896          uint8_t RESERVED_124[28];
83897     __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83898          uint8_t RESERVED_125[4];
83899     __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[3];       /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83900          uint8_t RESERVED_126[20];
83901     __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[1];       /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */
83902          uint8_t RESERVED_127[12];
83903   } MBC_INDEX[2];
83904   struct {                                         /* offset: 0x14000, array step: 0x1000 */
83905     __I  uint32_t MRC_GLBCFG;                        /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000, irregular array, not all indices are valid */
83906          uint8_t RESERVED_0[12];
83907     __IO uint32_t MRC_NSE_RGN_INDIRECT;              /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000, irregular array, not all indices are valid */
83908     __O  uint32_t MRC_NSE_RGN_SET;                   /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000, irregular array, not all indices are valid */
83909     __O  uint32_t MRC_NSE_RGN_CLR;                   /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000, irregular array, not all indices are valid */
83910     __O  uint32_t MRC_NSE_RGN_CLR_ALL;               /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000, irregular array, not all indices are valid */
83911     __IO uint32_t MRC_GLBAC[8];                      /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4, irregular array, not all indices are valid */
83912     __IO uint32_t MRC_DOM0_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83913     __IO uint32_t MRC_DOM0_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000, irregular array, not all indices are valid */
83914          uint8_t RESERVED_1[124];
83915     __IO uint32_t MRC_DOM1_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83916     __IO uint32_t MRC_DOM1_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000, irregular array, not all indices are valid */
83917          uint8_t RESERVED_2[124];
83918     __IO uint32_t MRC_DOM2_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83919     __IO uint32_t MRC_DOM2_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000, irregular array, not all indices are valid */
83920          uint8_t RESERVED_3[124];
83921     __IO uint32_t MRC_DOM3_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83922     __IO uint32_t MRC_DOM3_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000, irregular array, not all indices are valid */
83923          uint8_t RESERVED_4[124];
83924     __IO uint32_t MRC_DOM4_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83925     __IO uint32_t MRC_DOM4_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000, irregular array, not all indices are valid */
83926          uint8_t RESERVED_5[124];
83927     __IO uint32_t MRC_DOM5_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83928     __IO uint32_t MRC_DOM5_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000, irregular array, not all indices are valid */
83929          uint8_t RESERVED_6[124];
83930     __IO uint32_t MRC_DOM6_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83931     __IO uint32_t MRC_DOM6_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000, irregular array, not all indices are valid */
83932          uint8_t RESERVED_7[124];
83933     __IO uint32_t MRC_DOM7_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83934     __IO uint32_t MRC_DOM7_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000, irregular array, not all indices are valid */
83935          uint8_t RESERVED_8[124];
83936     __IO uint32_t MRC_DOM8_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83937     __IO uint32_t MRC_DOM8_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000, irregular array, not all indices are valid */
83938          uint8_t RESERVED_9[124];
83939     __IO uint32_t MRC_DOM9_RGD_W[16][2];             /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83940     __IO uint32_t MRC_DOM9_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000, irregular array, not all indices are valid */
83941          uint8_t RESERVED_10[124];
83942     __IO uint32_t MRC_DOM10_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83943     __IO uint32_t MRC_DOM10_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000, irregular array, not all indices are valid */
83944          uint8_t RESERVED_11[124];
83945     __IO uint32_t MRC_DOM11_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83946     __IO uint32_t MRC_DOM11_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000, irregular array, not all indices are valid */
83947          uint8_t RESERVED_12[124];
83948     __IO uint32_t MRC_DOM12_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83949     __IO uint32_t MRC_DOM12_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000, irregular array, not all indices are valid */
83950          uint8_t RESERVED_13[124];
83951     __IO uint32_t MRC_DOM13_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83952     __IO uint32_t MRC_DOM13_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000, irregular array, not all indices are valid */
83953          uint8_t RESERVED_14[124];
83954     __IO uint32_t MRC_DOM14_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83955     __IO uint32_t MRC_DOM14_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000, irregular array, not all indices are valid */
83956          uint8_t RESERVED_15[124];
83957     __IO uint32_t MRC_DOM15_RGD_W[16][2];            /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4, irregular array, not all indices are valid */
83958     __IO uint32_t MRC_DOM15_RGD_NSE;                 /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000, irregular array, not all indices are valid */
83959          uint8_t RESERVED_16[60];
83960   } MRC_INDEX[7];
83961 } TRDC_Type;
83962 
83963 /* ----------------------------------------------------------------------------
83964    -- TRDC Register Masks
83965    ---------------------------------------------------------------------------- */
83966 
83967 /*!
83968  * @addtogroup TRDC_Register_Masks TRDC Register Masks
83969  * @{
83970  */
83971 
83972 /*! @name TRDC_CR - TRDC Register */
83973 /*! @{ */
83974 
83975 #define TRDC_TRDC_CR_GVLDM_MASK                  (0x1U)
83976 #define TRDC_TRDC_CR_GVLDM_SHIFT                 (0U)
83977 /*! GVLDM - Global Valid for Domain Assignment Controllers
83978  *  0b0..TRDC DACs are disabled.
83979  *  0b1..TRDC DACs are enabled.
83980  */
83981 #define TRDC_TRDC_CR_GVLDM(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDM_SHIFT)) & TRDC_TRDC_CR_GVLDM_MASK)
83982 
83983 #define TRDC_TRDC_CR_HRL_MASK                    (0x1EU)
83984 #define TRDC_TRDC_CR_HRL_SHIFT                   (1U)
83985 /*! HRL - Hardware Revision Level */
83986 #define TRDC_TRDC_CR_HRL(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_HRL_SHIFT)) & TRDC_TRDC_CR_HRL_MASK)
83987 
83988 #define TRDC_TRDC_CR_GVLDB_MASK                  (0x4000U)
83989 #define TRDC_TRDC_CR_GVLDB_SHIFT                 (14U)
83990 /*! GVLDB - Global Valid for Memory Block Checkers
83991  *  0b0..TRDC MBCs are disabled.
83992  *  0b1..TRDC MBCs are enabled.
83993  */
83994 #define TRDC_TRDC_CR_GVLDB(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDB_SHIFT)) & TRDC_TRDC_CR_GVLDB_MASK)
83995 
83996 #define TRDC_TRDC_CR_GVLDR_MASK                  (0x8000U)
83997 #define TRDC_TRDC_CR_GVLDR_SHIFT                 (15U)
83998 /*! GVLDR - Global Valid for Memory Region Checkers
83999  *  0b0..TRDC MRCs are disabled.
84000  *  0b1..TRDC MRCs are enabled.
84001  */
84002 #define TRDC_TRDC_CR_GVLDR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDR_SHIFT)) & TRDC_TRDC_CR_GVLDR_MASK)
84003 
84004 #define TRDC_TRDC_CR_LK1_MASK                    (0x40000000U)
84005 #define TRDC_TRDC_CR_LK1_SHIFT                   (30U)
84006 /*! LK1 - Lock Status
84007  *  0b0..The CR can be written by any secure privileged write.
84008  *  0b1..The CR is locked (read-only) until the next reset.
84009  */
84010 #define TRDC_TRDC_CR_LK1(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_LK1_SHIFT)) & TRDC_TRDC_CR_LK1_MASK)
84011 /*! @} */
84012 
84013 /*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */
84014 /*! @{ */
84015 
84016 #define TRDC_TRDC_HWCFG0_NDID_MASK               (0x1FU)
84017 #define TRDC_TRDC_HWCFG0_NDID_SHIFT              (0U)
84018 /*! NDID - Number of domains */
84019 #define TRDC_TRDC_HWCFG0_NDID(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_TRDC_HWCFG0_NDID_MASK)
84020 
84021 #define TRDC_TRDC_HWCFG0_NMSTR_MASK              (0xFF00U)
84022 #define TRDC_TRDC_HWCFG0_NMSTR_SHIFT             (8U)
84023 /*! NMSTR - Number of bus masters */
84024 #define TRDC_TRDC_HWCFG0_NMSTR(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_TRDC_HWCFG0_NMSTR_MASK)
84025 
84026 #define TRDC_TRDC_HWCFG0_NMBC_MASK               (0xF0000U)
84027 #define TRDC_TRDC_HWCFG0_NMBC_SHIFT              (16U)
84028 /*! NMBC - Number of MBCs */
84029 #define TRDC_TRDC_HWCFG0_NMBC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_TRDC_HWCFG0_NMBC_MASK)
84030 
84031 #define TRDC_TRDC_HWCFG0_NMRC_MASK               (0x1F000000U)
84032 #define TRDC_TRDC_HWCFG0_NMRC_SHIFT              (24U)
84033 /*! NMRC - Number of MRCs */
84034 #define TRDC_TRDC_HWCFG0_NMRC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_TRDC_HWCFG0_NMRC_MASK)
84035 
84036 #define TRDC_TRDC_HWCFG0_MID_MASK                (0xE0000000U)
84037 #define TRDC_TRDC_HWCFG0_MID_SHIFT               (29U)
84038 /*! MID - Module ID */
84039 #define TRDC_TRDC_HWCFG0_MID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_MID_SHIFT)) & TRDC_TRDC_HWCFG0_MID_MASK)
84040 /*! @} */
84041 
84042 /*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */
84043 /*! @{ */
84044 
84045 #define TRDC_TRDC_HWCFG1_DID_MASK                (0xFU)
84046 #define TRDC_TRDC_HWCFG1_DID_SHIFT               (0U)
84047 /*! DID - Domain identifier number */
84048 #define TRDC_TRDC_HWCFG1_DID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG1_DID_SHIFT)) & TRDC_TRDC_HWCFG1_DID_MASK)
84049 /*! @} */
84050 
84051 /*! @name TRDC_HWCFG2 - TRDC Hardware Configuration Register 2 */
84052 /*! @{ */
84053 
84054 #define TRDC_TRDC_HWCFG2_PIDPn_MASK              (0xFFFFFFFFU)
84055 #define TRDC_TRDC_HWCFG2_PIDPn_SHIFT             (0U)
84056 /*! PIDPn - Process identifier present */
84057 #define TRDC_TRDC_HWCFG2_PIDPn(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG2_PIDPn_SHIFT)) & TRDC_TRDC_HWCFG2_PIDPn_MASK)
84058 /*! @} */
84059 
84060 /*! @name TRDC_HWCFG3 - TRDC Hardware Configuration Register 3 */
84061 /*! @{ */
84062 
84063 #define TRDC_TRDC_HWCFG3_PIDPn_MASK              (0xFFFFFFFFU)
84064 #define TRDC_TRDC_HWCFG3_PIDPn_SHIFT             (0U)
84065 /*! PIDPn - Process identifier present */
84066 #define TRDC_TRDC_HWCFG3_PIDPn(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG3_PIDPn_SHIFT)) & TRDC_TRDC_HWCFG3_PIDPn_MASK)
84067 /*! @} */
84068 
84069 /*! @name DACFG - Domain Assignment Configuration Register */
84070 /*! @{ */
84071 
84072 #define TRDC_DACFG_NMDAR_MASK                    (0xFU)
84073 #define TRDC_DACFG_NMDAR_SHIFT                   (0U)
84074 /*! NMDAR - Number of master domain assignment registers for bus master m */
84075 #define TRDC_DACFG_NMDAR(x)                      (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NMDAR_SHIFT)) & TRDC_DACFG_NMDAR_MASK)
84076 
84077 #define TRDC_DACFG_NCM_MASK                      (0x80U)
84078 #define TRDC_DACFG_NCM_SHIFT                     (7U)
84079 /*! NCM - Non-CPU Master
84080  *  0b0..Bus master is a processor.
84081  *  0b1..Bus master is a non-processor.
84082  */
84083 #define TRDC_DACFG_NCM(x)                        (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NCM_SHIFT)) & TRDC_DACFG_NCM_MASK)
84084 /*! @} */
84085 
84086 /* The count of TRDC_DACFG */
84087 #define TRDC_DACFG_COUNT                         (6U)
84088 
84089 /*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */
84090 /*! @{ */
84091 
84092 #define TRDC_TRDC_IDAU_CR_VLD_MASK               (0x1U)
84093 #define TRDC_TRDC_IDAU_CR_VLD_SHIFT              (0U)
84094 /*! VLD - Valid */
84095 #define TRDC_TRDC_IDAU_CR_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_TRDC_IDAU_CR_VLD_MASK)
84096 
84097 #define TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK         (0x8U)
84098 #define TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT        (3U)
84099 /*! CFGSECEXT - Configure Security Extension
84100  *  0b0..Armv8M Security Extension is disabled
84101  *  0b1..Armv8-M Security Extension is enabled
84102  */
84103 #define TRDC_TRDC_IDAU_CR_CFGSECEXT(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK)
84104 
84105 #define TRDC_TRDC_IDAU_CR_MPUSDIS_MASK           (0x10U)
84106 #define TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT          (4U)
84107 /*! MPUSDIS - Secure Memory Protection Unit Disabled
84108  *  0b0..Secure MPU is enabled
84109  *  0b1..Secure MPU is disabled
84110  */
84111 #define TRDC_TRDC_IDAU_CR_MPUSDIS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUSDIS_MASK)
84112 
84113 #define TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK          (0x20U)
84114 #define TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT         (5U)
84115 /*! MPUNSDIS - NonSecure Memory Protection Unit Disabled
84116  *  0b0..Nonsecure MPU is enabled
84117  *  0b1..Nonsecure MPU is disabled
84118  */
84119 #define TRDC_TRDC_IDAU_CR_MPUNSDIS(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK)
84120 
84121 #define TRDC_TRDC_IDAU_CR_SAUDIS_MASK            (0x40U)
84122 #define TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT           (6U)
84123 /*! SAUDIS - Security Attribution Unit Disable
84124  *  0b0..SAU is enabled
84125  *  0b1..SAU is disabled
84126  */
84127 #define TRDC_TRDC_IDAU_CR_SAUDIS(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_SAUDIS_MASK)
84128 
84129 #define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK        (0x100U)
84130 #define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT       (8U)
84131 /*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers
84132  *  0b0..Unlock these registers
84133  *  0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers
84134  */
84135 #define TRDC_TRDC_IDAU_CR_LKSVTAIRCR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK)
84136 
84137 #define TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK          (0x200U)
84138 #define TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT         (9U)
84139 /*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register
84140  *  0b0..Unlock this register
84141  *  0b1..Disable writes to the VTOR_NS register
84142  */
84143 #define TRDC_TRDC_IDAU_CR_LKNSVTOR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK)
84144 
84145 #define TRDC_TRDC_IDAU_CR_LKSMPU_MASK            (0x400U)
84146 #define TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT           (10U)
84147 /*! LKSMPU - Lock Secure MPU
84148  *  0b0..Unlock these registers
84149  *  0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or
84150  *       from a debug agent connected to the processor in Secure state
84151  */
84152 #define TRDC_TRDC_IDAU_CR_LKSMPU(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSMPU_MASK)
84153 
84154 #define TRDC_TRDC_IDAU_CR_LKNSMPU_MASK           (0x800U)
84155 #define TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT          (11U)
84156 /*! LKNSMPU - Lock Nonsecure MPU
84157  *  0b0..Unlock these registers
84158  *  0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and
84159  *       MPU_RLAR_A_NSn from software or from a debug agent connected to the processor
84160  */
84161 #define TRDC_TRDC_IDAU_CR_LKNSMPU(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSMPU_MASK)
84162 
84163 #define TRDC_TRDC_IDAU_CR_LKSAU_MASK             (0x1000U)
84164 #define TRDC_TRDC_IDAU_CR_LKSAU_SHIFT            (12U)
84165 /*! LKSAU - Lock SAU
84166  *  0b0..Unlock these registers
84167  *  0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor
84168  */
84169 #define TRDC_TRDC_IDAU_CR_LKSAU(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSAU_MASK)
84170 
84171 #define TRDC_TRDC_IDAU_CR_PCURRNS_MASK           (0x80000000U)
84172 #define TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT          (31U)
84173 /*! PCURRNS - Processor current security
84174  *  0b0..Processor is in Secure state
84175  *  0b1..Processor is in Nonsecure state
84176  */
84177 #define TRDC_TRDC_IDAU_CR_PCURRNS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_TRDC_IDAU_CR_PCURRNS_MASK)
84178 /*! @} */
84179 
84180 /*! @name TRDC_FLW_CTL - TRDC FLW Control */
84181 /*! @{ */
84182 
84183 #define TRDC_TRDC_FLW_CTL_LK_MASK                (0x40000000U)
84184 #define TRDC_TRDC_FLW_CTL_LK_SHIFT               (30U)
84185 /*! LK - Lock bit
84186  *  0b0..FLW registers may be modified.
84187  *  0b1..FLW registers are locked until the next reset.
84188  */
84189 #define TRDC_TRDC_FLW_CTL_LK(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_TRDC_FLW_CTL_LK_MASK)
84190 
84191 #define TRDC_TRDC_FLW_CTL_V_MASK                 (0x80000000U)
84192 #define TRDC_TRDC_FLW_CTL_V_SHIFT                (31U)
84193 /*! V - Valid bit
84194  *  0b0..FLW function is disabled.
84195  *  0b1..FLW function is enabled.
84196  */
84197 #define TRDC_TRDC_FLW_CTL_V(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_V_SHIFT)) & TRDC_TRDC_FLW_CTL_V_MASK)
84198 /*! @} */
84199 
84200 /*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */
84201 /*! @{ */
84202 
84203 #define TRDC_TRDC_FLW_PBASE_PBASE_MASK           (0xFFFFFFFFU)
84204 #define TRDC_TRDC_FLW_PBASE_PBASE_SHIFT          (0U)
84205 /*! PBASE - Physical base address */
84206 #define TRDC_TRDC_FLW_PBASE_PBASE(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_TRDC_FLW_PBASE_PBASE_MASK)
84207 /*! @} */
84208 
84209 /*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */
84210 /*! @{ */
84211 
84212 #define TRDC_TRDC_FLW_ABASE_ABASE_L_MASK         (0x3F8000U)
84213 #define TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT        (15U)
84214 /*! ABASE_L - Array base address low */
84215 #define TRDC_TRDC_FLW_ABASE_ABASE_L(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_L_MASK)
84216 
84217 #define TRDC_TRDC_FLW_ABASE_ABASE_H_MASK         (0xFFC00000U)
84218 #define TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT        (22U)
84219 /*! ABASE_H - Array base address high */
84220 #define TRDC_TRDC_FLW_ABASE_ABASE_H(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_H_MASK)
84221 /*! @} */
84222 
84223 /*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */
84224 /*! @{ */
84225 
84226 #define TRDC_TRDC_FLW_BCNT_BCNT_MASK             (0x7FFFU)
84227 #define TRDC_TRDC_FLW_BCNT_BCNT_SHIFT            (0U)
84228 /*! BCNT - Block Count */
84229 #define TRDC_TRDC_FLW_BCNT_BCNT(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_TRDC_FLW_BCNT_BCNT_MASK)
84230 /*! @} */
84231 
84232 /*! @name TRDC_FDID - TRDC Fault Domain ID */
84233 /*! @{ */
84234 
84235 #define TRDC_TRDC_FDID_FDID_MASK                 (0xFU)
84236 #define TRDC_TRDC_FDID_FDID_SHIFT                (0U)
84237 /*! FDID - Domain ID of Faulted Access */
84238 #define TRDC_TRDC_FDID_FDID(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FDID_FDID_SHIFT)) & TRDC_TRDC_FDID_FDID_MASK)
84239 /*! @} */
84240 
84241 /*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */
84242 /*! @{ */
84243 
84244 #define TRDC_TRDC_DERRLOC_MBCINST_MASK           (0xFFU)
84245 #define TRDC_TRDC_DERRLOC_MBCINST_SHIFT          (0U)
84246 /*! MBCINST - MBC instance */
84247 #define TRDC_TRDC_DERRLOC_MBCINST(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_TRDC_DERRLOC_MBCINST_MASK)
84248 
84249 #define TRDC_TRDC_DERRLOC_MRCINST_MASK           (0xFFFF0000U)
84250 #define TRDC_TRDC_DERRLOC_MRCINST_SHIFT          (16U)
84251 /*! MRCINST - MRC instance */
84252 #define TRDC_TRDC_DERRLOC_MRCINST(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_TRDC_DERRLOC_MRCINST_MASK)
84253 /*! @} */
84254 
84255 /* The count of TRDC_TRDC_DERRLOC */
84256 #define TRDC_TRDC_DERRLOC_COUNT                  (16U)
84257 
84258 /*! @name W0 - MBC Domain Error Word0 Register */
84259 /*! @{ */
84260 
84261 #define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
84262 #define TRDC_W0_EADDR_SHIFT                      (0U)
84263 /*! EADDR - Error address */
84264 #define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
84265 /*! @} */
84266 
84267 /* The count of TRDC_W0 */
84268 #define TRDC_W0_COUNT                            (2U)
84269 
84270 /*! @name W1 - MBC Domain Error Word1 Register */
84271 /*! @{ */
84272 
84273 #define TRDC_W1_EDID_MASK                        (0xFU)
84274 #define TRDC_W1_EDID_SHIFT                       (0U)
84275 /*! EDID - Error domain identifier */
84276 #define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)
84277 
84278 #define TRDC_W1_EATR_MASK                        (0x700U)
84279 #define TRDC_W1_EATR_SHIFT                       (8U)
84280 /*! EATR - Error attributes
84281  *  0b000..Secure user mode, instruction fetch access.
84282  *  0b001..Secure user mode, data access.
84283  *  0b010..Secure privileged mode, instruction fetch access.
84284  *  0b011..Secure privileged mode, data access.
84285  *  0b100..Nonsecure user mode, instruction fetch access.
84286  *  0b101..Nonsecure user mode, data access.
84287  *  0b110..Nonsecure privileged mode, instruction fetch access.
84288  *  0b111..Nonsecure privileged mode, data access.
84289  */
84290 #define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)
84291 
84292 #define TRDC_W1_ERW_MASK                         (0x800U)
84293 #define TRDC_W1_ERW_SHIFT                        (11U)
84294 /*! ERW - Error read/write
84295  *  0b0..Read access
84296  *  0b1..Write access
84297  */
84298 #define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)
84299 
84300 #define TRDC_W1_EPORT_MASK                       (0x7000000U)
84301 #define TRDC_W1_EPORT_SHIFT                      (24U)
84302 /*! EPORT - Error port
84303  *  0b000..mbcxslv0
84304  *  0b001..mbcxslv1
84305  *  0b010..mbcxslv2
84306  *  0b011..mbcxslv3
84307  */
84308 #define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)
84309 
84310 #define TRDC_W1_EST_MASK                         (0xC0000000U)
84311 #define TRDC_W1_EST_SHIFT                        (30U)
84312 /*! EST - Error state
84313  *  0b00..No access violation has been detected.
84314  *  0b01..No access violation has been detected.
84315  *  0b10..A single access violation has been detected.
84316  *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
84317  *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
84318  */
84319 #define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
84320 /*! @} */
84321 
84322 /* The count of TRDC_W1 */
84323 #define TRDC_W1_COUNT                            (2U)
84324 
84325 /*! @name W3 - MBC Domain Error Word3 Register */
84326 /*! @{ */
84327 
84328 #define TRDC_W3_RECR_MASK                        (0xC0000000U)
84329 #define TRDC_W3_RECR_SHIFT                       (30U)
84330 /*! RECR - Rearm Error Capture Registers */
84331 #define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
84332 /*! @} */
84333 
84334 /* The count of TRDC_W3 */
84335 #define TRDC_W3_COUNT                            (2U)
84336 
84337 /*! @name W0 - MRC Domain Error Word0 Register */
84338 /*! @{ */
84339 
84340 #define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
84341 #define TRDC_W0_EADDR_SHIFT                      (0U)
84342 /*! EADDR - Error address */
84343 #define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
84344 /*! @} */
84345 
84346 /* The count of TRDC_W0 */
84347 #define TRDC_MRC_DERR_W0_COUNT                   (7U)
84348 
84349 /*! @name W1 - MRC Domain Error Word1 Register */
84350 /*! @{ */
84351 
84352 #define TRDC_W1_EDID_MASK                        (0xFU)
84353 #define TRDC_W1_EDID_SHIFT                       (0U)
84354 /*! EDID - Error domain identifier */
84355 #define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)
84356 
84357 #define TRDC_W1_EATR_MASK                        (0x700U)
84358 #define TRDC_W1_EATR_SHIFT                       (8U)
84359 /*! EATR - Error attributes
84360  *  0b000..Secure user mode, instruction fetch access.
84361  *  0b001..Secure user mode, data access.
84362  *  0b010..Secure privileged mode, instruction fetch access.
84363  *  0b011..Secure privileged mode, data access.
84364  *  0b100..Nonsecure user mode, instruction fetch access.
84365  *  0b101..Nonsecure user mode, data access.
84366  *  0b110..Nonsecure privileged mode, instruction fetch access.
84367  *  0b111..Nonsecure privileged mode, data access.
84368  */
84369 #define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)
84370 
84371 #define TRDC_W1_ERW_MASK                         (0x800U)
84372 #define TRDC_W1_ERW_SHIFT                        (11U)
84373 /*! ERW - Error read/write
84374  *  0b0..Read access
84375  *  0b1..Write access
84376  */
84377 #define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)
84378 
84379 #define TRDC_W1_EPORT_MASK                       (0x7000000U)
84380 #define TRDC_W1_EPORT_SHIFT                      (24U)
84381 /*! EPORT - Error port */
84382 #define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)
84383 
84384 #define TRDC_W1_EST_MASK                         (0xC0000000U)
84385 #define TRDC_W1_EST_SHIFT                        (30U)
84386 /*! EST - Error state
84387  *  0b00..No access violation has been detected.
84388  *  0b01..No access violation has been detected.
84389  *  0b10..A single access violation has been detected.
84390  *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
84391  *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
84392  */
84393 #define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
84394 /*! @} */
84395 
84396 /* The count of TRDC_W1 */
84397 #define TRDC_MRC_DERR_W1_COUNT                   (7U)
84398 
84399 /*! @name W3 - MRC Domain Error Word3 Register */
84400 /*! @{ */
84401 
84402 #define TRDC_W3_RECR_MASK                        (0xC0000000U)
84403 #define TRDC_W3_RECR_SHIFT                       (30U)
84404 /*! RECR - Rearm Error Capture Registers */
84405 #define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
84406 /*! @} */
84407 
84408 /* The count of TRDC_W3 */
84409 #define TRDC_MRC_DERR_W3_COUNT                   (7U)
84410 
84411 /*! @name PID - Process Identifier */
84412 /*! @{ */
84413 
84414 #define TRDC_PID_PID_MASK                        (0x3FU)
84415 #define TRDC_PID_PID_SHIFT                       (0U)
84416 /*! PID - Process identifier */
84417 #define TRDC_PID_PID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_PID_PID_SHIFT)) & TRDC_PID_PID_MASK)
84418 
84419 #define TRDC_PID_LK2_MASK                        (0x60000000U)
84420 #define TRDC_PID_LK2_SHIFT                       (29U)
84421 /*! LK2 - Lock
84422  *  0b00..Register can be written by any secure privileged write.
84423  *  0b01..Register can be written by any secure privileged write.
84424  *  0b10..Register can only be written by a secure privileged write from the bus master that locked the register.
84425  *  0b11..Register is locked (read-only) until the next reset.
84426  */
84427 #define TRDC_PID_LK2(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_PID_LK2_SHIFT)) & TRDC_PID_LK2_MASK)
84428 /*! @} */
84429 
84430 /* The count of TRDC_PID */
84431 #define TRDC_PID_COUNT                           (2U)
84432 
84433 /*! @name MDA_W_DFMT0 - DAC Master Domain Assignment Register */
84434 /*! @{ */
84435 
84436 #define TRDC_MDA_W_DFMT0_DID_MASK                (0xFU)
84437 #define TRDC_MDA_W_DFMT0_DID_SHIFT               (0U)
84438 /*! DID - Domain identifier */
84439 #define TRDC_MDA_W_DFMT0_DID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_DID_SHIFT)) & TRDC_MDA_W_DFMT0_DID_MASK)
84440 
84441 #define TRDC_MDA_W_DFMT0_DIDS_MASK               (0x30U)
84442 #define TRDC_MDA_W_DFMT0_DIDS_SHIFT              (4U)
84443 /*! DIDS - DID Select
84444  *  0b00..Use MDAm[3:0] as the domain identifier.
84445  *  0b01..Use the input DID as the domain identifier.
84446  *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
84447  *  0b11..Reserved for future use.
84448  */
84449 #define TRDC_MDA_W_DFMT0_DIDS(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_DIDS_SHIFT)) & TRDC_MDA_W_DFMT0_DIDS_MASK)
84450 
84451 #define TRDC_MDA_W_DFMT0_PE_MASK                 (0xC0U)
84452 #define TRDC_MDA_W_DFMT0_PE_SHIFT                (6U)
84453 /*! PE - Process identifier enable
84454  *  0b00..No process identifier is included in the domain hit evaluation.
84455  *  0b01..No process identifier is included in the domain hit evaluation.
84456  *  0b10..PE = 2
84457  *  0b11..PE = 3
84458  */
84459 #define TRDC_MDA_W_DFMT0_PE(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_PE_SHIFT)) & TRDC_MDA_W_DFMT0_PE_MASK)
84460 
84461 #define TRDC_MDA_W_DFMT0_PIDM_MASK               (0x3F00U)
84462 #define TRDC_MDA_W_DFMT0_PIDM_SHIFT              (8U)
84463 /*! PIDM - Process Identifier Mask */
84464 #define TRDC_MDA_W_DFMT0_PIDM(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_PIDM_SHIFT)) & TRDC_MDA_W_DFMT0_PIDM_MASK)
84465 
84466 #define TRDC_MDA_W_DFMT0_SA_MASK                 (0xC000U)
84467 #define TRDC_MDA_W_DFMT0_SA_SHIFT                (14U)
84468 /*! SA - Secure attribute
84469  *  0b00..Force the bus attribute for this master to secure.
84470  *  0b01..Force the bus attribute for this master to nonsecure.
84471  *  0b10..Use the bus master's secure/nonsecure attribute directly.
84472  *  0b11..Use the bus master's secure/nonsecure attribute directly.
84473  */
84474 #define TRDC_MDA_W_DFMT0_SA(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_SA_SHIFT)) & TRDC_MDA_W_DFMT0_SA_MASK)
84475 
84476 #define TRDC_MDA_W_DFMT0_PID_MASK                (0x3F0000U)
84477 #define TRDC_MDA_W_DFMT0_PID_SHIFT               (16U)
84478 /*! PID - Process Identifier */
84479 #define TRDC_MDA_W_DFMT0_PID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_PID_SHIFT)) & TRDC_MDA_W_DFMT0_PID_MASK)
84480 
84481 #define TRDC_MDA_W_DFMT0_DFMT_MASK               (0x20000000U)
84482 #define TRDC_MDA_W_DFMT0_DFMT_SHIFT              (29U)
84483 /*! DFMT - Domain format
84484  *  0b0..Processor-core domain assignment
84485  *  0b1..Non-processor domain assignment
84486  */
84487 #define TRDC_MDA_W_DFMT0_DFMT(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_DFMT_SHIFT)) & TRDC_MDA_W_DFMT0_DFMT_MASK)
84488 
84489 #define TRDC_MDA_W_DFMT0_LK1_MASK                (0x40000000U)
84490 #define TRDC_MDA_W_DFMT0_LK1_SHIFT               (30U)
84491 /*! LK1 - 1-bit Lock
84492  *  0b0..Register can be written by any secure privileged write.
84493  *  0b1..Register is locked (read-only) until the next reset.
84494  */
84495 #define TRDC_MDA_W_DFMT0_LK1(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_LK1_SHIFT)) & TRDC_MDA_W_DFMT0_LK1_MASK)
84496 
84497 #define TRDC_MDA_W_DFMT0_VLD_MASK                (0x80000000U)
84498 #define TRDC_MDA_W_DFMT0_VLD_SHIFT               (31U)
84499 /*! VLD - Valid
84500  *  0b0..The Wr domain assignment is invalid.
84501  *  0b1..The Wr domain assignment is valid.
84502  */
84503 #define TRDC_MDA_W_DFMT0_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT0_VLD_SHIFT)) & TRDC_MDA_W_DFMT0_VLD_MASK)
84504 /*! @} */
84505 
84506 /* The count of TRDC_MDA_W_DFMT0 */
84507 #define TRDC_MDA_W_DFMT0_COUNT                   (6U)
84508 
84509 /* The count of TRDC_MDA_W_DFMT0 */
84510 #define TRDC_MDA_W_DFMT0_COUNT2                  (7U)
84511 
84512 /*! @name MDA_W_DFMT1 - DAC Master Domain Assignment Register */
84513 /*! @{ */
84514 
84515 #define TRDC_MDA_W_DFMT1_DID_MASK                (0xFU)
84516 #define TRDC_MDA_W_DFMT1_DID_SHIFT               (0U)
84517 /*! DID - Domain identifier */
84518 #define TRDC_MDA_W_DFMT1_DID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_DID_SHIFT)) & TRDC_MDA_W_DFMT1_DID_MASK)
84519 
84520 #define TRDC_MDA_W_DFMT1_PA_MASK                 (0x30U)
84521 #define TRDC_MDA_W_DFMT1_PA_SHIFT                (4U)
84522 /*! PA - Privileged attribute
84523  *  0b00..Force the bus attribute for this master to user.
84524  *  0b01..Force the bus attribute for this master to privileged.
84525  *  0b10..Use the bus master's privileged/user attribute directly.
84526  *  0b11..Use the bus master's privileged/user attribute directly.
84527  */
84528 #define TRDC_MDA_W_DFMT1_PA(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_PA_SHIFT)) & TRDC_MDA_W_DFMT1_PA_MASK)
84529 
84530 #define TRDC_MDA_W_DFMT1_SA_MASK                 (0xC0U)
84531 #define TRDC_MDA_W_DFMT1_SA_SHIFT                (6U)
84532 /*! SA - Secure attribute
84533  *  0b00..Force the bus attribute for this master to secure.
84534  *  0b01..Force the bus attribute for this master to nonsecure.
84535  *  0b10..Use the bus master's secure/nonsecure attribute directly.
84536  *  0b11..Use the bus master's secure/nonsecure attribute directly.
84537  */
84538 #define TRDC_MDA_W_DFMT1_SA(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_SA_SHIFT)) & TRDC_MDA_W_DFMT1_SA_MASK)
84539 
84540 #define TRDC_MDA_W_DFMT1_DIDB_MASK               (0x100U)
84541 #define TRDC_MDA_W_DFMT1_DIDB_SHIFT              (8U)
84542 /*! DIDB - DID Bypass
84543  *  0b0..Use MDAn[3:0] as the domain identifier.
84544  *  0b1..Use the DID input as the domain identifier.
84545  */
84546 #define TRDC_MDA_W_DFMT1_DIDB(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_DIDB_SHIFT)) & TRDC_MDA_W_DFMT1_DIDB_MASK)
84547 
84548 #define TRDC_MDA_W_DFMT1_DFMT_MASK               (0x20000000U)
84549 #define TRDC_MDA_W_DFMT1_DFMT_SHIFT              (29U)
84550 /*! DFMT - Domain format
84551  *  0b0..Processor-core domain assignment
84552  *  0b1..Non-processor domain assignment
84553  */
84554 #define TRDC_MDA_W_DFMT1_DFMT(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_DFMT_SHIFT)) & TRDC_MDA_W_DFMT1_DFMT_MASK)
84555 
84556 #define TRDC_MDA_W_DFMT1_LK1_MASK                (0x40000000U)
84557 #define TRDC_MDA_W_DFMT1_LK1_SHIFT               (30U)
84558 /*! LK1 - 1-bit Lock
84559  *  0b0..Register can be written by any secure privileged write.
84560  *  0b1..Register is locked (read-only) until the next reset.
84561  */
84562 #define TRDC_MDA_W_DFMT1_LK1(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_LK1_SHIFT)) & TRDC_MDA_W_DFMT1_LK1_MASK)
84563 
84564 #define TRDC_MDA_W_DFMT1_VLD_MASK                (0x80000000U)
84565 #define TRDC_MDA_W_DFMT1_VLD_SHIFT               (31U)
84566 /*! VLD - Valid
84567  *  0b0..The Wr domain assignment is invalid.
84568  *  0b1..The Wr domain assignment is valid.
84569  */
84570 #define TRDC_MDA_W_DFMT1_VLD(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W_DFMT1_VLD_SHIFT)) & TRDC_MDA_W_DFMT1_VLD_MASK)
84571 /*! @} */
84572 
84573 /* The count of TRDC_MDA_W_DFMT1 */
84574 #define TRDC_MDA_W_DFMT1_COUNT                   (5U)
84575 
84576 /* The count of TRDC_MDA_W_DFMT1 */
84577 #define TRDC_MDA_W_DFMT1_COUNT2                  (1U)
84578 
84579 /*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */
84580 /*! @{ */
84581 
84582 #define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK           (0x3FFU)
84583 #define TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT          (0U)
84584 /*! NBLKS - Number of blocks in this memory */
84585 #define TRDC_MBC_MEM_GLBCFG_NBLKS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK)
84586 
84587 #define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK       (0x1F0000U)
84588 #define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT      (16U)
84589 /*! SIZE_LOG2 - Log2 size per block */
84590 #define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK)
84591 /*! @} */
84592 
84593 /* The count of TRDC_MBC_MEM_GLBCFG */
84594 #define TRDC_MBC_MEM_GLBCFG_COUNT                (2U)
84595 
84596 /* The count of TRDC_MBC_MEM_GLBCFG */
84597 #define TRDC_MBC_MEM_GLBCFG_COUNT2               (4U)
84598 
84599 /*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
84600 /*! @{ */
84601 
84602 #define TRDC_MBC_NSE_BLK_INDEX_AI_MASK           (0x1U)
84603 #define TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT          (0U)
84604 /*! AI - Auto Increment
84605  *  0b0..No effect.
84606  *  0b1..Add 1 to the WNDX field after the register write.
84607  */
84608 #define TRDC_MBC_NSE_BLK_INDEX_AI(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_AI_MASK)
84609 
84610 #define TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK         (0x3CU)
84611 #define TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT        (2U)
84612 /*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */
84613 #define TRDC_MBC_NSE_BLK_INDEX_WNDX(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK)
84614 
84615 #define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK      (0xF00U)
84616 #define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT     (8U)
84617 /*! MEM_SEL - Memory Select */
84618 #define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK)
84619 
84620 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK     (0x10000U)
84621 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT    (16U)
84622 /*! DID_SEL0 - DID Select
84623  *  0b0..No effect.
84624  *  0b1..Selects NSE bits for this domain.
84625  */
84626 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK)
84627 
84628 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK     (0x20000U)
84629 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT    (17U)
84630 /*! DID_SEL1 - DID Select
84631  *  0b0..No effect.
84632  *  0b1..Selects NSE bits for this domain.
84633  */
84634 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK)
84635 
84636 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK     (0x40000U)
84637 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT    (18U)
84638 /*! DID_SEL2 - DID Select
84639  *  0b0..No effect.
84640  *  0b1..Selects NSE bits for this domain.
84641  */
84642 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK)
84643 
84644 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_MASK     (0x80000U)
84645 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT    (19U)
84646 /*! DID_SEL3 - DID Select
84647  *  0b0..No effect.
84648  *  0b1..Selects NSE bits for this domain.
84649  */
84650 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL3(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL3_MASK)
84651 
84652 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_MASK     (0x100000U)
84653 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT    (20U)
84654 /*! DID_SEL4 - DID Select
84655  *  0b0..No effect.
84656  *  0b1..Selects NSE bits for this domain.
84657  */
84658 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL4(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL4_MASK)
84659 
84660 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_MASK     (0x200000U)
84661 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT    (21U)
84662 /*! DID_SEL5 - DID Select
84663  *  0b0..No effect.
84664  *  0b1..Selects NSE bits for this domain.
84665  */
84666 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL5(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL5_MASK)
84667 
84668 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_MASK     (0x400000U)
84669 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT    (22U)
84670 /*! DID_SEL6 - DID Select
84671  *  0b0..No effect.
84672  *  0b1..Selects NSE bits for this domain.
84673  */
84674 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL6(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL6_MASK)
84675 
84676 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_MASK     (0x800000U)
84677 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT    (23U)
84678 /*! DID_SEL7 - DID Select
84679  *  0b0..No effect.
84680  *  0b1..Selects NSE bits for this domain.
84681  */
84682 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL7(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL7_MASK)
84683 
84684 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL8_MASK     (0x1000000U)
84685 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT    (24U)
84686 /*! DID_SEL8 - DID Select
84687  *  0b0..No effect.
84688  *  0b1..Selects NSE bits for this domain.
84689  */
84690 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL8(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL8_MASK)
84691 
84692 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL9_MASK     (0x2000000U)
84693 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT    (25U)
84694 /*! DID_SEL9 - DID Select
84695  *  0b0..No effect.
84696  *  0b1..Selects NSE bits for this domain.
84697  */
84698 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL9(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL9_MASK)
84699 
84700 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL10_MASK    (0x4000000U)
84701 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT   (26U)
84702 /*! DID_SEL10 - DID Select
84703  *  0b0..No effect.
84704  *  0b1..Selects NSE bits for this domain.
84705  */
84706 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL10(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL10_MASK)
84707 
84708 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL11_MASK    (0x8000000U)
84709 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT   (27U)
84710 /*! DID_SEL11 - DID Select
84711  *  0b0..No effect.
84712  *  0b1..Selects NSE bits for this domain.
84713  */
84714 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL11(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL11_MASK)
84715 
84716 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL12_MASK    (0x10000000U)
84717 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT   (28U)
84718 /*! DID_SEL12 - DID Select
84719  *  0b0..No effect.
84720  *  0b1..Selects NSE bits for this domain.
84721  */
84722 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL12(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL12_MASK)
84723 
84724 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL13_MASK    (0x20000000U)
84725 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT   (29U)
84726 /*! DID_SEL13 - DID Select
84727  *  0b0..No effect.
84728  *  0b1..Selects NSE bits for this domain.
84729  */
84730 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL13(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL13_MASK)
84731 
84732 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL14_MASK    (0x40000000U)
84733 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT   (30U)
84734 /*! DID_SEL14 - DID Select
84735  *  0b0..No effect.
84736  *  0b1..Selects NSE bits for this domain.
84737  */
84738 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL14(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL14_MASK)
84739 
84740 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL15_MASK    (0x80000000U)
84741 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT   (31U)
84742 /*! DID_SEL15 - DID Select
84743  *  0b0..No effect.
84744  *  0b1..Selects NSE bits for this domain.
84745  */
84746 #define TRDC_MBC_NSE_BLK_INDEX_DID_SEL15(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL15_MASK)
84747 /*! @} */
84748 
84749 /* The count of TRDC_MBC_NSE_BLK_INDEX */
84750 #define TRDC_MBC_NSE_BLK_INDEX_COUNT             (2U)
84751 
84752 /*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */
84753 /*! @{ */
84754 
84755 #define TRDC_MBC_NSE_BLK_SET_W1SET_MASK          (0xFFFFFFFFU)
84756 #define TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT         (0U)
84757 /*! W1SET - Write-1 Set */
84758 #define TRDC_MBC_NSE_BLK_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_NSE_BLK_SET_W1SET_MASK)
84759 /*! @} */
84760 
84761 /* The count of TRDC_MBC_NSE_BLK_SET */
84762 #define TRDC_MBC_NSE_BLK_SET_COUNT               (2U)
84763 
84764 /*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
84765 /*! @{ */
84766 
84767 #define TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK          (0xFFFFFFFFU)
84768 #define TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT         (0U)
84769 /*! W1CLR - Write-1 Clear */
84770 #define TRDC_MBC_NSE_BLK_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK)
84771 /*! @} */
84772 
84773 /* The count of TRDC_MBC_NSE_BLK_CLR */
84774 #define TRDC_MBC_NSE_BLK_CLR_COUNT               (2U)
84775 
84776 /*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
84777 /*! @{ */
84778 
84779 #define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK     (0xF00U)
84780 #define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT    (8U)
84781 /*! MEMSEL - Memory Select */
84782 #define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK)
84783 
84784 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK   (0x10000U)
84785 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT  (16U)
84786 /*! DID_SEL0 - DID Select
84787  *  0b0..No effect.
84788  *  0b1..Clear all NSE bits for this domain.
84789  */
84790 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK)
84791 
84792 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK   (0x20000U)
84793 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT  (17U)
84794 /*! DID_SEL1 - DID Select
84795  *  0b0..No effect.
84796  *  0b1..Clear all NSE bits for this domain.
84797  */
84798 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK)
84799 
84800 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK   (0x40000U)
84801 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT  (18U)
84802 /*! DID_SEL2 - DID Select
84803  *  0b0..No effect.
84804  *  0b1..Clear all NSE bits for this domain.
84805  */
84806 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK)
84807 
84808 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK   (0x80000U)
84809 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT  (19U)
84810 /*! DID_SEL3 - DID Select
84811  *  0b0..No effect.
84812  *  0b1..Clear all NSE bits for this domain.
84813  */
84814 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK)
84815 
84816 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK   (0x100000U)
84817 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT  (20U)
84818 /*! DID_SEL4 - DID Select
84819  *  0b0..No effect.
84820  *  0b1..Clear all NSE bits for this domain.
84821  */
84822 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK)
84823 
84824 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK   (0x200000U)
84825 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT  (21U)
84826 /*! DID_SEL5 - DID Select
84827  *  0b0..No effect.
84828  *  0b1..Clear all NSE bits for this domain.
84829  */
84830 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK)
84831 
84832 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK   (0x400000U)
84833 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT  (22U)
84834 /*! DID_SEL6 - DID Select
84835  *  0b0..No effect.
84836  *  0b1..Clear all NSE bits for this domain.
84837  */
84838 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK)
84839 
84840 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK   (0x800000U)
84841 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT  (23U)
84842 /*! DID_SEL7 - DID Select
84843  *  0b0..No effect.
84844  *  0b1..Clear all NSE bits for this domain.
84845  */
84846 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK)
84847 
84848 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK   (0x1000000U)
84849 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT  (24U)
84850 /*! DID_SEL8 - DID Select
84851  *  0b0..No effect.
84852  *  0b1..Clear all NSE bits for this domain.
84853  */
84854 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK)
84855 
84856 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK   (0x2000000U)
84857 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT  (25U)
84858 /*! DID_SEL9 - DID Select
84859  *  0b0..No effect.
84860  *  0b1..Clear all NSE bits for this domain.
84861  */
84862 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK)
84863 
84864 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK  (0x4000000U)
84865 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT (26U)
84866 /*! DID_SEL10 - DID Select
84867  *  0b0..No effect.
84868  *  0b1..Clear all NSE bits for this domain.
84869  */
84870 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK)
84871 
84872 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK  (0x8000000U)
84873 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT (27U)
84874 /*! DID_SEL11 - DID Select
84875  *  0b0..No effect.
84876  *  0b1..Clear all NSE bits for this domain.
84877  */
84878 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK)
84879 
84880 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK  (0x10000000U)
84881 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT (28U)
84882 /*! DID_SEL12 - DID Select
84883  *  0b0..No effect.
84884  *  0b1..Clear all NSE bits for this domain.
84885  */
84886 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK)
84887 
84888 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK  (0x20000000U)
84889 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT (29U)
84890 /*! DID_SEL13 - DID Select
84891  *  0b0..No effect.
84892  *  0b1..Clear all NSE bits for this domain.
84893  */
84894 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK)
84895 
84896 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK  (0x40000000U)
84897 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT (30U)
84898 /*! DID_SEL14 - DID Select
84899  *  0b0..No effect.
84900  *  0b1..Clear all NSE bits for this domain.
84901  */
84902 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK)
84903 
84904 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK  (0x80000000U)
84905 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT (31U)
84906 /*! DID_SEL15 - DID Select
84907  *  0b0..No effect.
84908  *  0b1..Clear all NSE bits for this domain.
84909  */
84910 #define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK)
84911 /*! @} */
84912 
84913 /* The count of TRDC_MBC_NSE_BLK_CLR_ALL */
84914 #define TRDC_MBC_NSE_BLK_CLR_ALL_COUNT           (2U)
84915 
84916 /*! @name MBC_MEMN_GLBAC - MBC Global Access Control */
84917 /*! @{ */
84918 
84919 #define TRDC_MBC_MEMN_GLBAC_NUX_MASK             (0x1U)
84920 #define TRDC_MBC_MEMN_GLBAC_NUX_SHIFT            (0U)
84921 /*! NUX - NonsecureUser Execute
84922  *  0b0..Execute access is not allowed in Nonsecure User mode.
84923  *  0b1..Execute access is allowed in Nonsecure User mode.
84924  */
84925 #define TRDC_MBC_MEMN_GLBAC_NUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUX_MASK)
84926 
84927 #define TRDC_MBC_MEMN_GLBAC_NUW_MASK             (0x2U)
84928 #define TRDC_MBC_MEMN_GLBAC_NUW_SHIFT            (1U)
84929 /*! NUW - NonsecureUser Write
84930  *  0b0..Write access is not allowed in Nonsecure User mode.
84931  *  0b1..Write access is allowed in Nonsecure User mode.
84932  */
84933 #define TRDC_MBC_MEMN_GLBAC_NUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUW_MASK)
84934 
84935 #define TRDC_MBC_MEMN_GLBAC_NUR_MASK             (0x4U)
84936 #define TRDC_MBC_MEMN_GLBAC_NUR_SHIFT            (2U)
84937 /*! NUR - NonsecureUser Read
84938  *  0b0..Read access is not allowed in Nonsecure User mode.
84939  *  0b1..Read access is allowed in Nonsecure User mode.
84940  */
84941 #define TRDC_MBC_MEMN_GLBAC_NUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUR_MASK)
84942 
84943 #define TRDC_MBC_MEMN_GLBAC_NPX_MASK             (0x10U)
84944 #define TRDC_MBC_MEMN_GLBAC_NPX_SHIFT            (4U)
84945 /*! NPX - NonsecurePriv Execute
84946  *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
84947  *  0b1..Execute access is allowed in Nonsecure Privilege mode.
84948  */
84949 #define TRDC_MBC_MEMN_GLBAC_NPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPX_MASK)
84950 
84951 #define TRDC_MBC_MEMN_GLBAC_NPW_MASK             (0x20U)
84952 #define TRDC_MBC_MEMN_GLBAC_NPW_SHIFT            (5U)
84953 /*! NPW - NonsecurePriv Write
84954  *  0b0..Write access is not allowed in Nonsecure Privilege mode.
84955  *  0b1..Write access is allowed in Nonsecure Privilege mode.
84956  */
84957 #define TRDC_MBC_MEMN_GLBAC_NPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPW_MASK)
84958 
84959 #define TRDC_MBC_MEMN_GLBAC_NPR_MASK             (0x40U)
84960 #define TRDC_MBC_MEMN_GLBAC_NPR_SHIFT            (6U)
84961 /*! NPR - NonsecurePriv Read
84962  *  0b0..Read access is not allowed in Nonsecure Privilege mode.
84963  *  0b1..Read access is allowed in Nonsecure Privilege mode.
84964  */
84965 #define TRDC_MBC_MEMN_GLBAC_NPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPR_MASK)
84966 
84967 #define TRDC_MBC_MEMN_GLBAC_SUX_MASK             (0x100U)
84968 #define TRDC_MBC_MEMN_GLBAC_SUX_SHIFT            (8U)
84969 /*! SUX - SecureUser Execute
84970  *  0b0..Execute access is not allowed in Secure User mode.
84971  *  0b1..Execute access is allowed in Secure User mode.
84972  */
84973 #define TRDC_MBC_MEMN_GLBAC_SUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUX_MASK)
84974 
84975 #define TRDC_MBC_MEMN_GLBAC_SUW_MASK             (0x200U)
84976 #define TRDC_MBC_MEMN_GLBAC_SUW_SHIFT            (9U)
84977 /*! SUW - SecureUser Write
84978  *  0b0..Write access is not allowed in Secure User mode.
84979  *  0b1..Write access is allowed in Secure User mode.
84980  */
84981 #define TRDC_MBC_MEMN_GLBAC_SUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUW_MASK)
84982 
84983 #define TRDC_MBC_MEMN_GLBAC_SUR_MASK             (0x400U)
84984 #define TRDC_MBC_MEMN_GLBAC_SUR_SHIFT            (10U)
84985 /*! SUR - SecureUser Read
84986  *  0b0..Read access is not allowed in Secure User mode.
84987  *  0b1..Read access is allowed in Secure User mode.
84988  */
84989 #define TRDC_MBC_MEMN_GLBAC_SUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUR_MASK)
84990 
84991 #define TRDC_MBC_MEMN_GLBAC_SPX_MASK             (0x1000U)
84992 #define TRDC_MBC_MEMN_GLBAC_SPX_SHIFT            (12U)
84993 /*! SPX - SecurePriv Execute
84994  *  0b0..Execute access is not allowed in Secure Privilege mode.
84995  *  0b1..Execute access is allowed in Secure Privilege mode.
84996  */
84997 #define TRDC_MBC_MEMN_GLBAC_SPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPX_MASK)
84998 
84999 #define TRDC_MBC_MEMN_GLBAC_SPW_MASK             (0x2000U)
85000 #define TRDC_MBC_MEMN_GLBAC_SPW_SHIFT            (13U)
85001 /*! SPW - SecurePriv Write
85002  *  0b0..Write access is not allowed in Secure Privilege mode.
85003  *  0b1..Write access is allowed in Secure Privilege mode.
85004  */
85005 #define TRDC_MBC_MEMN_GLBAC_SPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPW_MASK)
85006 
85007 #define TRDC_MBC_MEMN_GLBAC_SPR_MASK             (0x4000U)
85008 #define TRDC_MBC_MEMN_GLBAC_SPR_SHIFT            (14U)
85009 /*! SPR - SecurePriv Read
85010  *  0b0..Read access is not allowed in Secure Privilege mode.
85011  *  0b1..Read access is allowed in Secure Privilege mode.
85012  */
85013 #define TRDC_MBC_MEMN_GLBAC_SPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPR_MASK)
85014 
85015 #define TRDC_MBC_MEMN_GLBAC_LK_MASK              (0x80000000U)
85016 #define TRDC_MBC_MEMN_GLBAC_LK_SHIFT             (31U)
85017 /*! LK - LOCK
85018  *  0b0..This register is not locked and can be altered.
85019  *  0b1..This register is locked and cannot be altered.
85020  */
85021 #define TRDC_MBC_MEMN_GLBAC_LK(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_MEMN_GLBAC_LK_MASK)
85022 /*! @} */
85023 
85024 /* The count of TRDC_MBC_MEMN_GLBAC */
85025 #define TRDC_MBC_MEMN_GLBAC_COUNT                (2U)
85026 
85027 /* The count of TRDC_MBC_MEMN_GLBAC */
85028 #define TRDC_MBC_MEMN_GLBAC_COUNT2               (8U)
85029 
85030 /*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
85031 /*! @{ */
85032 
85033 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
85034 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
85035 /*! MBACSEL0 - Memory Block Access Control Select for block B
85036  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85037  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85038  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85039  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85040  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85041  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85042  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85043  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85044  */
85045 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK)
85046 
85047 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
85048 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
85049 /*! NSE0 - NonSecure Enable for block B
85050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85053  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85054  */
85055 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK)
85056 
85057 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
85058 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
85059 /*! MBACSEL1 - Memory Block Access Control Select for block B
85060  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85061  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85062  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85063  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85064  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85065  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85066  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85067  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85068  */
85069 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK)
85070 
85071 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
85072 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
85073 /*! NSE1 - NonSecure Enable for block B
85074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85077  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85078  */
85079 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK)
85080 
85081 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
85082 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
85083 /*! MBACSEL2 - Memory Block Access Control Select for block B
85084  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85085  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85086  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85087  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85088  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85089  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85090  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85091  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85092  */
85093 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK)
85094 
85095 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
85096 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
85097 /*! NSE2 - NonSecure Enable for block B
85098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85101  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85102  */
85103 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK)
85104 
85105 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
85106 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
85107 /*! MBACSEL3 - Memory Block Access Control Select for block B
85108  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85109  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85110  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85111  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85112  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85113  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85114  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85115  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85116  */
85117 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK)
85118 
85119 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
85120 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
85121 /*! NSE3 - NonSecure Enable for block B
85122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85125  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85126  */
85127 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK)
85128 
85129 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
85130 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
85131 /*! MBACSEL4 - Memory Block Access Control Select for block B
85132  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85133  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85134  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85135  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85136  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85137  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85138  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85139  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85140  */
85141 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK)
85142 
85143 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
85144 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
85145 /*! NSE4 - NonSecure Enable for block B
85146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85149  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85150  */
85151 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK)
85152 
85153 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
85154 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
85155 /*! MBACSEL5 - Memory Block Access Control Select for block B
85156  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85157  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85158  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85159  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85160  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85161  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85162  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85163  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85164  */
85165 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK)
85166 
85167 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
85168 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
85169 /*! NSE5 - NonSecure Enable for block B
85170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85173  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85174  */
85175 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK)
85176 
85177 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
85178 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
85179 /*! MBACSEL6 - Memory Block Access Control Select for block B
85180  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85181  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85182  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85183  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85184  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85185  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85186  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85187  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85188  */
85189 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK)
85190 
85191 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
85192 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
85193 /*! NSE6 - NonSecure Enable for block B
85194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85197  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85198  */
85199 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK)
85200 
85201 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
85202 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
85203 /*! MBACSEL7 - Memory Block Access Control Select for block B
85204  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85205  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85206  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85207  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85208  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85209  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85210  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85211  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85212  */
85213 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK)
85214 
85215 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
85216 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
85217 /*! NSE7 - NonSecure Enable for block B
85218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85221  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85222  */
85223 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK)
85224 /*! @} */
85225 
85226 /* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
85227 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT       (2U)
85228 
85229 /* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
85230 #define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2      (16U)
85231 
85232 /*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
85233 /*! @{ */
85234 
85235 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
85236 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
85237 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
85238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85241  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85242  */
85243 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK)
85244 
85245 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
85246 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
85247 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
85248  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85249  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85250  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85251  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85252  */
85253 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK)
85254 
85255 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
85256 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
85257 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
85258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85261  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85262  */
85263 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK)
85264 
85265 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
85266 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
85267 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
85268  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85269  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85270  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85271  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85272  */
85273 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK)
85274 
85275 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
85276 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
85277 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
85278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85281  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85282  */
85283 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK)
85284 
85285 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
85286 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
85287 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
85288  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85289  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85290  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85291  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85292  */
85293 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK)
85294 
85295 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
85296 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
85297 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
85298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85301  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85302  */
85303 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK)
85304 
85305 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
85306 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
85307 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
85308  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85309  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85310  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85311  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85312  */
85313 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK)
85314 
85315 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
85316 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
85317 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
85318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85321  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85322  */
85323 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK)
85324 
85325 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
85326 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
85327 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
85328  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85329  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85330  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85331  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85332  */
85333 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK)
85334 
85335 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
85336 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
85337 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
85338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85341  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85342  */
85343 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK)
85344 
85345 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
85346 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
85347 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
85348  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85349  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85350  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85351  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85352  */
85353 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK)
85354 
85355 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
85356 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
85357 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
85358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85361  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85362  */
85363 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK)
85364 
85365 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
85366 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
85367 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
85368  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85369  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85370  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85371  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85372  */
85373 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK)
85374 
85375 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
85376 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
85377 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
85378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85381  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85382  */
85383 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK)
85384 
85385 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
85386 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
85387 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
85388  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85389  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85390  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85391  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85392  */
85393 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK)
85394 
85395 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
85396 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
85397 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
85398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85401  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85402  */
85403 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK)
85404 
85405 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
85406 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
85407 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
85408  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85409  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85410  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85411  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85412  */
85413 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK)
85414 
85415 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
85416 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
85417 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
85418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85421  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85422  */
85423 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK)
85424 
85425 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
85426 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
85427 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
85428  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85429  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85430  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85431  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85432  */
85433 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK)
85434 
85435 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
85436 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
85437 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
85438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85441  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85442  */
85443 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK)
85444 
85445 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
85446 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
85447 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
85448  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85449  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85450  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85451  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85452  */
85453 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK)
85454 
85455 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
85456 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
85457 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
85458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85461  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85462  */
85463 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK)
85464 
85465 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
85466 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
85467 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
85468  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85469  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85470  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85471  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85472  */
85473 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK)
85474 
85475 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
85476 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
85477 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
85478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85481  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85482  */
85483 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK)
85484 
85485 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
85486 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
85487 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
85488  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85489  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85490  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85491  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85492  */
85493 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK)
85494 
85495 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
85496 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
85497 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
85498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85501  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85502  */
85503 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK)
85504 
85505 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
85506 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
85507 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
85508  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85509  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85510  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85511  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85512  */
85513 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK)
85514 
85515 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
85516 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
85517 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
85518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85521  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85522  */
85523 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK)
85524 
85525 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
85526 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
85527 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
85528  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85529  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85530  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85531  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85532  */
85533 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK)
85534 
85535 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
85536 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
85537 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
85538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85541  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85542  */
85543 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK)
85544 
85545 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
85546 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
85547 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
85548  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85549  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85550  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85551  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85552  */
85553 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK)
85554 /*! @} */
85555 
85556 /* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
85557 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT       (2U)
85558 
85559 /* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
85560 #define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2      (4U)
85561 
85562 /*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
85563 /*! @{ */
85564 
85565 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
85566 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
85567 /*! MBACSEL0 - Memory Block Access Control Select for block B
85568  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85569  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85570  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85571  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85572  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85573  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85574  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85575  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85576  */
85577 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK)
85578 
85579 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
85580 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
85581 /*! NSE0 - NonSecure Enable for block B
85582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85585  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85586  */
85587 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK)
85588 
85589 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
85590 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
85591 /*! MBACSEL1 - Memory Block Access Control Select for block B
85592  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85593  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85594  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85595  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85596  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85597  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85598  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85599  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85600  */
85601 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK)
85602 
85603 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
85604 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
85605 /*! NSE1 - NonSecure Enable for block B
85606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85609  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85610  */
85611 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK)
85612 
85613 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
85614 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
85615 /*! MBACSEL2 - Memory Block Access Control Select for block B
85616  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85617  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85618  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85619  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85620  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85621  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85622  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85623  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85624  */
85625 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK)
85626 
85627 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
85628 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
85629 /*! NSE2 - NonSecure Enable for block B
85630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85633  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85634  */
85635 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK)
85636 
85637 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
85638 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
85639 /*! MBACSEL3 - Memory Block Access Control Select for block B
85640  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85641  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85642  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85643  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85644  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85645  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85646  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85647  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85648  */
85649 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK)
85650 
85651 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
85652 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
85653 /*! NSE3 - NonSecure Enable for block B
85654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85657  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85658  */
85659 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK)
85660 
85661 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
85662 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
85663 /*! MBACSEL4 - Memory Block Access Control Select for block B
85664  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85665  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85666  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85667  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85668  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85669  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85670  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85671  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85672  */
85673 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK)
85674 
85675 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
85676 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
85677 /*! NSE4 - NonSecure Enable for block B
85678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85681  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85682  */
85683 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK)
85684 
85685 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
85686 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
85687 /*! MBACSEL5 - Memory Block Access Control Select for block B
85688  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85689  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85690  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85691  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85692  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85693  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85694  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85695  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85696  */
85697 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK)
85698 
85699 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
85700 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
85701 /*! NSE5 - NonSecure Enable for block B
85702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85705  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85706  */
85707 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK)
85708 
85709 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
85710 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
85711 /*! MBACSEL6 - Memory Block Access Control Select for block B
85712  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85713  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85714  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85715  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85716  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85717  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85718  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85719  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85720  */
85721 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK)
85722 
85723 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
85724 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
85725 /*! NSE6 - NonSecure Enable for block B
85726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85729  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85730  */
85731 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK)
85732 
85733 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
85734 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
85735 /*! MBACSEL7 - Memory Block Access Control Select for block B
85736  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
85737  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
85738  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
85739  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
85740  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
85741  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
85742  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
85743  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
85744  */
85745 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK)
85746 
85747 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
85748 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
85749 /*! NSE7 - NonSecure Enable for block B
85750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
85751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85753  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85754  */
85755 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK)
85756 /*! @} */
85757 
85758 /* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
85759 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT       (2U)
85760 
85761 /* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
85762 #define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2      (4U)
85763 
85764 /*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
85765 /*! @{ */
85766 
85767 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
85768 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
85769 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
85770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85774  */
85775 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK)
85776 
85777 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
85778 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
85779 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
85780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85784  */
85785 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK)
85786 
85787 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
85788 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
85789 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
85790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85794  */
85795 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK)
85796 
85797 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
85798 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
85799 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
85800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85804  */
85805 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK)
85806 
85807 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
85808 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
85809 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
85810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85814  */
85815 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK)
85816 
85817 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
85818 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
85819 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
85820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85824  */
85825 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK)
85826 
85827 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
85828 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
85829 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
85830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85834  */
85835 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK)
85836 
85837 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
85838 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
85839 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
85840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85844  */
85845 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK)
85846 
85847 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
85848 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
85849 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
85850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85854  */
85855 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK)
85856 
85857 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
85858 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
85859 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
85860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85864  */
85865 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK)
85866 
85867 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
85868 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
85869 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
85870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85874  */
85875 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK)
85876 
85877 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
85878 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
85879 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
85880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85884  */
85885 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK)
85886 
85887 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
85888 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
85889 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
85890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85894  */
85895 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK)
85896 
85897 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
85898 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
85899 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
85900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85904  */
85905 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK)
85906 
85907 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
85908 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
85909 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
85910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85914  */
85915 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK)
85916 
85917 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
85918 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
85919 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
85920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85924  */
85925 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK)
85926 
85927 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
85928 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
85929 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
85930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85934  */
85935 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK)
85936 
85937 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
85938 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
85939 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
85940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85944  */
85945 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK)
85946 
85947 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
85948 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
85949 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
85950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85954  */
85955 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK)
85956 
85957 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
85958 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
85959 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
85960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85964  */
85965 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK)
85966 
85967 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
85968 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
85969 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
85970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85974  */
85975 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK)
85976 
85977 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
85978 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
85979 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
85980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85984  */
85985 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK)
85986 
85987 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
85988 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
85989 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
85990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
85991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
85992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
85993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
85994  */
85995 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK)
85996 
85997 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
85998 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
85999 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
86000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86004  */
86005 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK)
86006 
86007 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
86008 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
86009 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
86010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86013  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86014  */
86015 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK)
86016 
86017 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
86018 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
86019 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
86020  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86021  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86022  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86023  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86024  */
86025 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK)
86026 
86027 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
86028 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
86029 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
86030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86033  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86034  */
86035 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK)
86036 
86037 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
86038 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
86039 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
86040  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86041  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86042  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86043  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86044  */
86045 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK)
86046 
86047 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
86048 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
86049 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
86050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86053  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86054  */
86055 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK)
86056 
86057 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
86058 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
86059 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
86060  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86061  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86062  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86063  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86064  */
86065 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK)
86066 
86067 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
86068 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
86069 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
86070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86073  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86074  */
86075 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK)
86076 
86077 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
86078 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
86079 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
86080  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86081  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86082  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86083  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86084  */
86085 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK)
86086 /*! @} */
86087 
86088 /* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
86089 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT       (2U)
86090 
86091 /* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
86092 #define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2      (1U)
86093 
86094 /*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
86095 /*! @{ */
86096 
86097 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
86098 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
86099 /*! MBACSEL0 - Memory Block Access Control Select for block B
86100  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86101  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86102  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86103  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86104  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86105  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86106  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86107  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86108  */
86109 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK)
86110 
86111 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
86112 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
86113 /*! NSE0 - NonSecure Enable for block B
86114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86117  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86118  */
86119 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK)
86120 
86121 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
86122 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
86123 /*! MBACSEL1 - Memory Block Access Control Select for block B
86124  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86125  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86126  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86127  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86128  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86129  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86130  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86131  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86132  */
86133 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK)
86134 
86135 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
86136 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
86137 /*! NSE1 - NonSecure Enable for block B
86138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86141  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86142  */
86143 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK)
86144 
86145 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
86146 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
86147 /*! MBACSEL2 - Memory Block Access Control Select for block B
86148  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86149  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86150  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86151  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86152  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86153  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86154  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86155  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86156  */
86157 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK)
86158 
86159 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
86160 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
86161 /*! NSE2 - NonSecure Enable for block B
86162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86165  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86166  */
86167 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK)
86168 
86169 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
86170 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
86171 /*! MBACSEL3 - Memory Block Access Control Select for block B
86172  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86173  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86174  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86175  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86176  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86177  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86178  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86179  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86180  */
86181 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK)
86182 
86183 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
86184 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
86185 /*! NSE3 - NonSecure Enable for block B
86186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86189  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86190  */
86191 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK)
86192 
86193 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
86194 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
86195 /*! MBACSEL4 - Memory Block Access Control Select for block B
86196  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86197  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86198  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86199  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86200  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86201  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86202  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86203  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86204  */
86205 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK)
86206 
86207 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
86208 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
86209 /*! NSE4 - NonSecure Enable for block B
86210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86213  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86214  */
86215 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK)
86216 
86217 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
86218 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
86219 /*! MBACSEL5 - Memory Block Access Control Select for block B
86220  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86221  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86222  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86223  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86224  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86225  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86226  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86227  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86228  */
86229 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK)
86230 
86231 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
86232 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
86233 /*! NSE5 - NonSecure Enable for block B
86234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86237  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86238  */
86239 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK)
86240 
86241 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
86242 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
86243 /*! MBACSEL6 - Memory Block Access Control Select for block B
86244  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86245  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86246  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86247  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86248  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86249  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86250  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86251  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86252  */
86253 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK)
86254 
86255 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
86256 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
86257 /*! NSE6 - NonSecure Enable for block B
86258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86261  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86262  */
86263 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK)
86264 
86265 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
86266 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
86267 /*! MBACSEL7 - Memory Block Access Control Select for block B
86268  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86269  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86270  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86271  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86272  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86273  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86274  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86275  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86276  */
86277 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK)
86278 
86279 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
86280 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
86281 /*! NSE7 - NonSecure Enable for block B
86282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86285  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86286  */
86287 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK)
86288 /*! @} */
86289 
86290 /* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
86291 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT       (2U)
86292 
86293 /* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
86294 #define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2      (1U)
86295 
86296 /*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
86297 /*! @{ */
86298 
86299 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
86300 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
86301 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
86302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86306  */
86307 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK)
86308 
86309 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
86310 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
86311 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
86312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86316  */
86317 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK)
86318 
86319 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
86320 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
86321 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
86322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86326  */
86327 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK)
86328 
86329 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
86330 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
86331 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
86332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86336  */
86337 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK)
86338 
86339 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
86340 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
86341 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
86342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86346  */
86347 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK)
86348 
86349 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
86350 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
86351 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
86352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86356  */
86357 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK)
86358 
86359 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
86360 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
86361 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
86362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86366  */
86367 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK)
86368 
86369 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
86370 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
86371 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
86372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86376  */
86377 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK)
86378 
86379 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
86380 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
86381 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
86382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86386  */
86387 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK)
86388 
86389 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
86390 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
86391 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
86392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86396  */
86397 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK)
86398 
86399 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
86400 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
86401 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
86402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86406  */
86407 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK)
86408 
86409 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
86410 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
86411 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
86412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86416  */
86417 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK)
86418 
86419 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
86420 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
86421 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
86422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86426  */
86427 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK)
86428 
86429 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
86430 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
86431 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
86432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86436  */
86437 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK)
86438 
86439 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
86440 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
86441 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
86442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86446  */
86447 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK)
86448 
86449 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
86450 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
86451 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
86452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86456  */
86457 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK)
86458 
86459 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
86460 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
86461 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
86462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86466  */
86467 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK)
86468 
86469 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
86470 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
86471 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
86472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86476  */
86477 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK)
86478 
86479 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
86480 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
86481 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
86482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86486  */
86487 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK)
86488 
86489 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
86490 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
86491 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
86492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86496  */
86497 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK)
86498 
86499 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
86500 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
86501 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
86502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86506  */
86507 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK)
86508 
86509 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
86510 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
86511 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
86512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86516  */
86517 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK)
86518 
86519 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
86520 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
86521 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
86522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86526  */
86527 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK)
86528 
86529 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
86530 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
86531 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
86532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86536  */
86537 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK)
86538 
86539 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
86540 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
86541 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
86542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86545  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86546  */
86547 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK)
86548 
86549 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
86550 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
86551 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
86552  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86553  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86554  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86555  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86556  */
86557 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK)
86558 
86559 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
86560 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
86561 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
86562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86565  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86566  */
86567 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK)
86568 
86569 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
86570 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
86571 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
86572  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86573  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86574  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86575  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86576  */
86577 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK)
86578 
86579 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
86580 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
86581 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
86582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86585  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86586  */
86587 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK)
86588 
86589 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
86590 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
86591 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
86592  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86593  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86594  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86595  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86596  */
86597 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK)
86598 
86599 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
86600 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
86601 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
86602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86605  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86606  */
86607 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK)
86608 
86609 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
86610 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
86611 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
86612  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86613  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86614  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86615  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86616  */
86617 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK)
86618 /*! @} */
86619 
86620 /* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
86621 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT       (2U)
86622 
86623 /* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
86624 #define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2      (1U)
86625 
86626 /*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
86627 /*! @{ */
86628 
86629 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
86630 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
86631 /*! MBACSEL0 - Memory Block Access Control Select for block B
86632  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86633  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86634  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86635  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86636  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86637  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86638  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86639  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86640  */
86641 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK)
86642 
86643 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
86644 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
86645 /*! NSE0 - NonSecure Enable for block B
86646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86649  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86650  */
86651 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK)
86652 
86653 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
86654 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
86655 /*! MBACSEL1 - Memory Block Access Control Select for block B
86656  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86657  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86658  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86659  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86660  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86661  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86662  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86663  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86664  */
86665 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK)
86666 
86667 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
86668 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
86669 /*! NSE1 - NonSecure Enable for block B
86670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86673  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86674  */
86675 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK)
86676 
86677 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
86678 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
86679 /*! MBACSEL2 - Memory Block Access Control Select for block B
86680  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86681  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86682  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86683  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86684  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86685  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86686  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86687  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86688  */
86689 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK)
86690 
86691 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
86692 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
86693 /*! NSE2 - NonSecure Enable for block B
86694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86697  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86698  */
86699 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK)
86700 
86701 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
86702 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
86703 /*! MBACSEL3 - Memory Block Access Control Select for block B
86704  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86705  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86706  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86707  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86708  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86709  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86710  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86711  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86712  */
86713 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK)
86714 
86715 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
86716 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
86717 /*! NSE3 - NonSecure Enable for block B
86718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86721  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86722  */
86723 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK)
86724 
86725 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
86726 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
86727 /*! MBACSEL4 - Memory Block Access Control Select for block B
86728  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86729  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86730  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86731  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86732  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86733  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86734  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86735  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86736  */
86737 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK)
86738 
86739 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
86740 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
86741 /*! NSE4 - NonSecure Enable for block B
86742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86745  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86746  */
86747 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK)
86748 
86749 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
86750 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
86751 /*! MBACSEL5 - Memory Block Access Control Select for block B
86752  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86753  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86754  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86755  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86756  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86757  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86758  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86759  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86760  */
86761 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK)
86762 
86763 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
86764 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
86765 /*! NSE5 - NonSecure Enable for block B
86766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86769  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86770  */
86771 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK)
86772 
86773 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
86774 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
86775 /*! MBACSEL6 - Memory Block Access Control Select for block B
86776  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86777  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86778  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86779  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86780  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86781  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86782  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86783  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86784  */
86785 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK)
86786 
86787 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
86788 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
86789 /*! NSE6 - NonSecure Enable for block B
86790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86793  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86794  */
86795 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK)
86796 
86797 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
86798 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
86799 /*! MBACSEL7 - Memory Block Access Control Select for block B
86800  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
86801  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
86802  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
86803  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
86804  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
86805  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
86806  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
86807  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
86808  */
86809 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK)
86810 
86811 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
86812 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
86813 /*! NSE7 - NonSecure Enable for block B
86814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
86815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86817  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86818  */
86819 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK)
86820 /*! @} */
86821 
86822 /* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
86823 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT       (2U)
86824 
86825 /* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
86826 #define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2      (3U)
86827 
86828 /*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
86829 /*! @{ */
86830 
86831 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
86832 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
86833 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
86834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86838  */
86839 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK)
86840 
86841 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
86842 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
86843 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
86844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86848  */
86849 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK)
86850 
86851 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
86852 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
86853 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
86854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86858  */
86859 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK)
86860 
86861 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
86862 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
86863 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
86864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86868  */
86869 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK)
86870 
86871 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
86872 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
86873 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
86874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86878  */
86879 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK)
86880 
86881 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
86882 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
86883 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
86884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86888  */
86889 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK)
86890 
86891 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
86892 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
86893 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
86894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86898  */
86899 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK)
86900 
86901 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
86902 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
86903 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
86904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86908  */
86909 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK)
86910 
86911 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
86912 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
86913 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
86914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86918  */
86919 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK)
86920 
86921 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
86922 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
86923 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
86924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86928  */
86929 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK)
86930 
86931 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
86932 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
86933 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
86934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86938  */
86939 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK)
86940 
86941 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
86942 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
86943 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
86944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86948  */
86949 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK)
86950 
86951 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
86952 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
86953 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
86954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86958  */
86959 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK)
86960 
86961 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
86962 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
86963 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
86964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86968  */
86969 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK)
86970 
86971 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
86972 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
86973 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
86974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86978  */
86979 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK)
86980 
86981 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
86982 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
86983 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
86984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86988  */
86989 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK)
86990 
86991 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
86992 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
86993 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
86994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
86995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
86996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
86997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
86998  */
86999 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK)
87000 
87001 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
87002 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
87003 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
87004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87008  */
87009 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK)
87010 
87011 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
87012 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
87013 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
87014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87018  */
87019 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK)
87020 
87021 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
87022 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
87023 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
87024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87028  */
87029 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK)
87030 
87031 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
87032 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
87033 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
87034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87038  */
87039 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK)
87040 
87041 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
87042 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
87043 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
87044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87048  */
87049 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK)
87050 
87051 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
87052 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
87053 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
87054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87058  */
87059 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK)
87060 
87061 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
87062 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
87063 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
87064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87068  */
87069 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK)
87070 
87071 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
87072 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
87073 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
87074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87077  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87078  */
87079 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK)
87080 
87081 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
87082 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
87083 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
87084  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87085  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87086  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87087  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87088  */
87089 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK)
87090 
87091 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
87092 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
87093 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
87094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87097  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87098  */
87099 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK)
87100 
87101 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
87102 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
87103 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
87104  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87105  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87106  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87107  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87108  */
87109 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK)
87110 
87111 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
87112 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
87113 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
87114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87117  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87118  */
87119 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK)
87120 
87121 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
87122 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
87123 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
87124  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87125  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87126  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87127  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87128  */
87129 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK)
87130 
87131 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
87132 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
87133 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
87134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87137  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87138  */
87139 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK)
87140 
87141 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
87142 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
87143 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
87144  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87145  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87146  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87147  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87148  */
87149 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK)
87150 /*! @} */
87151 
87152 /* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
87153 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT       (2U)
87154 
87155 /* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
87156 #define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2      (1U)
87157 
87158 /*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
87159 /*! @{ */
87160 
87161 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
87162 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
87163 /*! MBACSEL0 - Memory Block Access Control Select for block B
87164  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87165  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87166  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87167  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87168  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87169  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87170  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87171  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87172  */
87173 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK)
87174 
87175 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
87176 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
87177 /*! NSE0 - NonSecure Enable for block B
87178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87181  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87182  */
87183 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK)
87184 
87185 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
87186 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
87187 /*! MBACSEL1 - Memory Block Access Control Select for block B
87188  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87189  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87190  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87191  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87192  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87193  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87194  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87195  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87196  */
87197 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK)
87198 
87199 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
87200 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
87201 /*! NSE1 - NonSecure Enable for block B
87202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87205  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87206  */
87207 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK)
87208 
87209 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
87210 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
87211 /*! MBACSEL2 - Memory Block Access Control Select for block B
87212  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87213  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87214  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87215  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87216  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87217  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87218  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87219  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87220  */
87221 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK)
87222 
87223 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
87224 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
87225 /*! NSE2 - NonSecure Enable for block B
87226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87229  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87230  */
87231 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK)
87232 
87233 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
87234 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
87235 /*! MBACSEL3 - Memory Block Access Control Select for block B
87236  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87237  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87238  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87239  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87240  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87241  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87242  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87243  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87244  */
87245 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK)
87246 
87247 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
87248 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
87249 /*! NSE3 - NonSecure Enable for block B
87250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87253  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87254  */
87255 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK)
87256 
87257 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
87258 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
87259 /*! MBACSEL4 - Memory Block Access Control Select for block B
87260  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87261  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87262  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87263  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87264  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87265  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87266  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87267  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87268  */
87269 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK)
87270 
87271 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
87272 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
87273 /*! NSE4 - NonSecure Enable for block B
87274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87277  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87278  */
87279 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK)
87280 
87281 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
87282 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
87283 /*! MBACSEL5 - Memory Block Access Control Select for block B
87284  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87285  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87286  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87287  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87288  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87289  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87290  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87291  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87292  */
87293 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK)
87294 
87295 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
87296 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
87297 /*! NSE5 - NonSecure Enable for block B
87298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87301  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87302  */
87303 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK)
87304 
87305 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
87306 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
87307 /*! MBACSEL6 - Memory Block Access Control Select for block B
87308  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87309  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87310  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87311  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87312  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87313  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87314  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87315  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87316  */
87317 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK)
87318 
87319 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
87320 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
87321 /*! NSE6 - NonSecure Enable for block B
87322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87325  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87326  */
87327 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK)
87328 
87329 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
87330 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
87331 /*! MBACSEL7 - Memory Block Access Control Select for block B
87332  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87333  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87334  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87335  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87336  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87337  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87338  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87339  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87340  */
87341 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK)
87342 
87343 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
87344 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
87345 /*! NSE7 - NonSecure Enable for block B
87346  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87347  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87348  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87349  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87350  */
87351 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK)
87352 /*! @} */
87353 
87354 /* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
87355 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT       (2U)
87356 
87357 /* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
87358 #define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2      (16U)
87359 
87360 /*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
87361 /*! @{ */
87362 
87363 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
87364 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
87365 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
87366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87369  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87370  */
87371 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK)
87372 
87373 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
87374 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
87375 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
87376  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87377  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87378  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87379  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87380  */
87381 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK)
87382 
87383 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
87384 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
87385 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
87386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87389  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87390  */
87391 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK)
87392 
87393 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
87394 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
87395 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
87396  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87397  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87398  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87399  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87400  */
87401 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK)
87402 
87403 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
87404 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
87405 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
87406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87409  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87410  */
87411 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK)
87412 
87413 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
87414 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
87415 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
87416  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87417  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87418  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87419  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87420  */
87421 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK)
87422 
87423 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
87424 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
87425 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
87426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87429  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87430  */
87431 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK)
87432 
87433 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
87434 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
87435 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
87436  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87437  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87438  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87439  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87440  */
87441 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK)
87442 
87443 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
87444 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
87445 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
87446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87449  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87450  */
87451 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK)
87452 
87453 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
87454 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
87455 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
87456  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87457  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87458  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87459  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87460  */
87461 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK)
87462 
87463 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
87464 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
87465 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
87466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87469  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87470  */
87471 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK)
87472 
87473 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
87474 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
87475 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
87476  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87477  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87478  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87479  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87480  */
87481 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK)
87482 
87483 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
87484 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
87485 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
87486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87489  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87490  */
87491 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK)
87492 
87493 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
87494 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
87495 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
87496  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87497  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87498  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87499  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87500  */
87501 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK)
87502 
87503 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
87504 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
87505 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
87506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87509  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87510  */
87511 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK)
87512 
87513 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
87514 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
87515 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
87516  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87517  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87518  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87519  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87520  */
87521 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK)
87522 
87523 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
87524 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
87525 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
87526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87529  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87530  */
87531 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK)
87532 
87533 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
87534 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
87535 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
87536  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87537  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87538  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87539  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87540  */
87541 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK)
87542 
87543 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
87544 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
87545 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
87546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87549  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87550  */
87551 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK)
87552 
87553 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
87554 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
87555 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
87556  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87557  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87558  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87559  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87560  */
87561 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK)
87562 
87563 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
87564 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
87565 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
87566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87569  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87570  */
87571 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK)
87572 
87573 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
87574 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
87575 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
87576  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87577  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87578  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87579  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87580  */
87581 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK)
87582 
87583 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
87584 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
87585 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
87586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87589  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87590  */
87591 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK)
87592 
87593 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
87594 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
87595 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
87596  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87597  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87598  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87599  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87600  */
87601 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK)
87602 
87603 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
87604 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
87605 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
87606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87609  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87610  */
87611 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK)
87612 
87613 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
87614 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
87615 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
87616  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87617  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87618  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87619  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87620  */
87621 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK)
87622 
87623 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
87624 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
87625 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
87626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87629  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87630  */
87631 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK)
87632 
87633 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
87634 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
87635 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
87636  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87637  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87638  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87639  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87640  */
87641 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK)
87642 
87643 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
87644 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
87645 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
87646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87649  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87650  */
87651 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK)
87652 
87653 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
87654 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
87655 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
87656  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87657  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87658  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87659  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87660  */
87661 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK)
87662 
87663 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
87664 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
87665 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
87666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87669  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87670  */
87671 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK)
87672 
87673 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
87674 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
87675 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
87676  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87677  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87678  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87679  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87680  */
87681 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK)
87682 /*! @} */
87683 
87684 /* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
87685 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT       (2U)
87686 
87687 /* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
87688 #define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2      (4U)
87689 
87690 /*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
87691 /*! @{ */
87692 
87693 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
87694 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
87695 /*! MBACSEL0 - Memory Block Access Control Select for block B
87696  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87697  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87698  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87699  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87700  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87701  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87702  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87703  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87704  */
87705 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK)
87706 
87707 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
87708 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
87709 /*! NSE0 - NonSecure Enable for block B
87710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87713  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87714  */
87715 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK)
87716 
87717 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
87718 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
87719 /*! MBACSEL1 - Memory Block Access Control Select for block B
87720  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87721  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87722  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87723  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87724  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87725  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87726  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87727  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87728  */
87729 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK)
87730 
87731 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
87732 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
87733 /*! NSE1 - NonSecure Enable for block B
87734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87737  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87738  */
87739 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK)
87740 
87741 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
87742 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
87743 /*! MBACSEL2 - Memory Block Access Control Select for block B
87744  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87745  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87746  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87747  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87748  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87749  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87750  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87751  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87752  */
87753 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK)
87754 
87755 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
87756 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
87757 /*! NSE2 - NonSecure Enable for block B
87758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87761  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87762  */
87763 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK)
87764 
87765 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
87766 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
87767 /*! MBACSEL3 - Memory Block Access Control Select for block B
87768  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87769  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87770  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87771  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87772  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87773  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87774  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87775  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87776  */
87777 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK)
87778 
87779 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
87780 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
87781 /*! NSE3 - NonSecure Enable for block B
87782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87785  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87786  */
87787 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK)
87788 
87789 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
87790 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
87791 /*! MBACSEL4 - Memory Block Access Control Select for block B
87792  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87793  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87794  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87795  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87796  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87797  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87798  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87799  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87800  */
87801 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK)
87802 
87803 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
87804 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
87805 /*! NSE4 - NonSecure Enable for block B
87806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87809  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87810  */
87811 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK)
87812 
87813 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
87814 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
87815 /*! MBACSEL5 - Memory Block Access Control Select for block B
87816  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87817  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87818  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87819  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87820  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87821  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87822  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87823  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87824  */
87825 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK)
87826 
87827 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
87828 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
87829 /*! NSE5 - NonSecure Enable for block B
87830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87833  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87834  */
87835 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK)
87836 
87837 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
87838 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
87839 /*! MBACSEL6 - Memory Block Access Control Select for block B
87840  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87841  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87842  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87843  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87844  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87845  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87846  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87847  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87848  */
87849 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK)
87850 
87851 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
87852 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
87853 /*! NSE6 - NonSecure Enable for block B
87854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87857  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87858  */
87859 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK)
87860 
87861 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
87862 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
87863 /*! MBACSEL7 - Memory Block Access Control Select for block B
87864  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
87865  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
87866  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
87867  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
87868  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
87869  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
87870  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
87871  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
87872  */
87873 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK)
87874 
87875 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
87876 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
87877 /*! NSE7 - NonSecure Enable for block B
87878  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
87879  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87880  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87881  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87882  */
87883 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK)
87884 /*! @} */
87885 
87886 /* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
87887 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT       (2U)
87888 
87889 /* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
87890 #define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2      (4U)
87891 
87892 /*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
87893 /*! @{ */
87894 
87895 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
87896 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
87897 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
87898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87901  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87902  */
87903 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK)
87904 
87905 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
87906 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
87907 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
87908  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87909  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87910  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87911  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87912  */
87913 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK)
87914 
87915 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
87916 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
87917 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
87918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87921  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87922  */
87923 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK)
87924 
87925 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
87926 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
87927 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
87928  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87929  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87930  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87931  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87932  */
87933 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK)
87934 
87935 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
87936 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
87937 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
87938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87941  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87942  */
87943 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK)
87944 
87945 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
87946 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
87947 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
87948  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87949  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87950  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87951  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87952  */
87953 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK)
87954 
87955 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
87956 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
87957 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
87958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87961  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87962  */
87963 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK)
87964 
87965 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
87966 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
87967 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
87968  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87969  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87970  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87971  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87972  */
87973 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK)
87974 
87975 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
87976 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
87977 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
87978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87981  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87982  */
87983 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK)
87984 
87985 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
87986 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
87987 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
87988  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87989  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
87990  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
87991  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
87992  */
87993 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK)
87994 
87995 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
87996 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
87997 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
87998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
87999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88001  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88002  */
88003 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK)
88004 
88005 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
88006 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
88007 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
88008  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88009  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88010  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88011  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88012  */
88013 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK)
88014 
88015 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
88016 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
88017 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
88018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88021  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88022  */
88023 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK)
88024 
88025 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
88026 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
88027 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
88028  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88029  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88030  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88031  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88032  */
88033 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK)
88034 
88035 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
88036 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
88037 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
88038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88041  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88042  */
88043 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK)
88044 
88045 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
88046 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
88047 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
88048  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88049  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88050  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88051  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88052  */
88053 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK)
88054 
88055 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
88056 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
88057 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
88058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88061  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88062  */
88063 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK)
88064 
88065 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
88066 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
88067 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
88068  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88069  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88070  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88071  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88072  */
88073 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK)
88074 
88075 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
88076 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
88077 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
88078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88081  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88082  */
88083 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK)
88084 
88085 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
88086 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
88087 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
88088  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88089  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88090  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88091  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88092  */
88093 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK)
88094 
88095 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
88096 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
88097 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
88098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88101  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88102  */
88103 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK)
88104 
88105 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
88106 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
88107 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
88108  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88109  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88110  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88111  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88112  */
88113 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK)
88114 
88115 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
88116 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
88117 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
88118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88121  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88122  */
88123 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK)
88124 
88125 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
88126 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
88127 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
88128  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88129  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88130  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88131  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88132  */
88133 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK)
88134 
88135 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
88136 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
88137 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
88138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88141  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88142  */
88143 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK)
88144 
88145 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
88146 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
88147 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
88148  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88149  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88150  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88151  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88152  */
88153 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK)
88154 
88155 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
88156 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
88157 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
88158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88161  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88162  */
88163 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK)
88164 
88165 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
88166 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
88167 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
88168  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88169  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88170  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88171  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88172  */
88173 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK)
88174 
88175 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
88176 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
88177 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
88178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88181  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88182  */
88183 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK)
88184 
88185 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
88186 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
88187 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
88188  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88189  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88190  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88191  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88192  */
88193 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK)
88194 
88195 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
88196 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
88197 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
88198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88201  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88202  */
88203 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK)
88204 
88205 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
88206 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
88207 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
88208  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88209  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88210  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88211  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88212  */
88213 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK)
88214 /*! @} */
88215 
88216 /* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
88217 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT       (2U)
88218 
88219 /* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
88220 #define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2      (1U)
88221 
88222 /*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
88223 /*! @{ */
88224 
88225 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
88226 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
88227 /*! MBACSEL0 - Memory Block Access Control Select for block B
88228  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88229  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88230  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88231  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88232  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88233  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88234  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88235  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88236  */
88237 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK)
88238 
88239 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
88240 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
88241 /*! NSE0 - NonSecure Enable for block B
88242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88245  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88246  */
88247 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK)
88248 
88249 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
88250 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
88251 /*! MBACSEL1 - Memory Block Access Control Select for block B
88252  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88253  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88254  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88255  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88256  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88257  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88258  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88259  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88260  */
88261 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK)
88262 
88263 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
88264 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
88265 /*! NSE1 - NonSecure Enable for block B
88266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88269  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88270  */
88271 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK)
88272 
88273 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
88274 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
88275 /*! MBACSEL2 - Memory Block Access Control Select for block B
88276  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88277  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88278  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88279  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88280  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88281  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88282  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88283  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88284  */
88285 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK)
88286 
88287 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
88288 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
88289 /*! NSE2 - NonSecure Enable for block B
88290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88293  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88294  */
88295 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK)
88296 
88297 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
88298 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
88299 /*! MBACSEL3 - Memory Block Access Control Select for block B
88300  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88301  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88302  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88303  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88304  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88305  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88306  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88307  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88308  */
88309 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK)
88310 
88311 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
88312 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
88313 /*! NSE3 - NonSecure Enable for block B
88314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88317  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88318  */
88319 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK)
88320 
88321 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
88322 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
88323 /*! MBACSEL4 - Memory Block Access Control Select for block B
88324  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88325  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88326  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88327  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88328  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88329  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88330  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88331  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88332  */
88333 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK)
88334 
88335 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
88336 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
88337 /*! NSE4 - NonSecure Enable for block B
88338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88341  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88342  */
88343 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK)
88344 
88345 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
88346 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
88347 /*! MBACSEL5 - Memory Block Access Control Select for block B
88348  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88349  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88350  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88351  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88352  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88353  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88354  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88355  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88356  */
88357 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK)
88358 
88359 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
88360 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
88361 /*! NSE5 - NonSecure Enable for block B
88362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88365  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88366  */
88367 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK)
88368 
88369 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
88370 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
88371 /*! MBACSEL6 - Memory Block Access Control Select for block B
88372  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88373  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88374  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88375  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88376  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88377  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88378  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88379  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88380  */
88381 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK)
88382 
88383 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
88384 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
88385 /*! NSE6 - NonSecure Enable for block B
88386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88389  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88390  */
88391 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK)
88392 
88393 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
88394 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
88395 /*! MBACSEL7 - Memory Block Access Control Select for block B
88396  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88397  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88398  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88399  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88400  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88401  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88402  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88403  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88404  */
88405 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK)
88406 
88407 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
88408 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
88409 /*! NSE7 - NonSecure Enable for block B
88410  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88411  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88412  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88413  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88414  */
88415 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK)
88416 /*! @} */
88417 
88418 /* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
88419 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT       (2U)
88420 
88421 /* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
88422 #define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2      (1U)
88423 
88424 /*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
88425 /*! @{ */
88426 
88427 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
88428 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
88429 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
88430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88433  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88434  */
88435 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK)
88436 
88437 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
88438 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
88439 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
88440  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88441  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88442  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88443  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88444  */
88445 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK)
88446 
88447 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
88448 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
88449 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
88450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88453  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88454  */
88455 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK)
88456 
88457 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
88458 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
88459 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
88460  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88461  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88462  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88463  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88464  */
88465 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK)
88466 
88467 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
88468 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
88469 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
88470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88473  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88474  */
88475 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK)
88476 
88477 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
88478 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
88479 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
88480  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88481  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88482  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88483  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88484  */
88485 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK)
88486 
88487 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
88488 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
88489 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
88490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88493  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88494  */
88495 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK)
88496 
88497 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
88498 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
88499 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
88500  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88501  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88502  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88503  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88504  */
88505 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK)
88506 
88507 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
88508 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
88509 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
88510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88513  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88514  */
88515 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK)
88516 
88517 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
88518 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
88519 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
88520  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88521  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88522  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88523  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88524  */
88525 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK)
88526 
88527 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
88528 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
88529 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
88530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88533  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88534  */
88535 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK)
88536 
88537 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
88538 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
88539 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
88540  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88541  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88542  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88543  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88544  */
88545 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK)
88546 
88547 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
88548 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
88549 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
88550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88553  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88554  */
88555 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK)
88556 
88557 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
88558 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
88559 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
88560  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88561  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88562  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88563  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88564  */
88565 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK)
88566 
88567 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
88568 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
88569 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
88570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88573  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88574  */
88575 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK)
88576 
88577 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
88578 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
88579 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
88580  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88581  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88582  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88583  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88584  */
88585 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK)
88586 
88587 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
88588 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
88589 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
88590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88593  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88594  */
88595 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK)
88596 
88597 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
88598 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
88599 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
88600  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88601  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88602  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88603  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88604  */
88605 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK)
88606 
88607 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
88608 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
88609 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
88610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88613  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88614  */
88615 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK)
88616 
88617 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
88618 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
88619 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
88620  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88621  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88622  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88623  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88624  */
88625 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK)
88626 
88627 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
88628 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
88629 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
88630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88633  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88634  */
88635 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK)
88636 
88637 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
88638 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
88639 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
88640  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88641  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88642  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88643  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88644  */
88645 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK)
88646 
88647 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
88648 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
88649 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
88650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88653  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88654  */
88655 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK)
88656 
88657 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
88658 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
88659 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
88660  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88661  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88662  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88663  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88664  */
88665 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK)
88666 
88667 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
88668 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
88669 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
88670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88673  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88674  */
88675 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK)
88676 
88677 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
88678 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
88679 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
88680  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88681  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88682  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88683  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88684  */
88685 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK)
88686 
88687 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
88688 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
88689 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
88690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88693  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88694  */
88695 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK)
88696 
88697 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
88698 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
88699 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
88700  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88701  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88702  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88703  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88704  */
88705 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK)
88706 
88707 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
88708 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
88709 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
88710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88713  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88714  */
88715 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK)
88716 
88717 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
88718 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
88719 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
88720  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88721  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88722  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88723  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88724  */
88725 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK)
88726 
88727 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
88728 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
88729 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
88730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88733  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88734  */
88735 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK)
88736 
88737 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
88738 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
88739 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
88740  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88741  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88742  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88743  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88744  */
88745 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK)
88746 /*! @} */
88747 
88748 /* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
88749 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT       (2U)
88750 
88751 /* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
88752 #define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2      (1U)
88753 
88754 /*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
88755 /*! @{ */
88756 
88757 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
88758 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
88759 /*! MBACSEL0 - Memory Block Access Control Select for block B
88760  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88761  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88762  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88763  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88764  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88765  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88766  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88767  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88768  */
88769 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK)
88770 
88771 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
88772 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
88773 /*! NSE0 - NonSecure Enable for block B
88774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88777  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88778  */
88779 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK)
88780 
88781 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
88782 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
88783 /*! MBACSEL1 - Memory Block Access Control Select for block B
88784  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88785  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88786  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88787  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88788  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88789  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88790  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88791  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88792  */
88793 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK)
88794 
88795 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
88796 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
88797 /*! NSE1 - NonSecure Enable for block B
88798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88801  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88802  */
88803 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK)
88804 
88805 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
88806 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
88807 /*! MBACSEL2 - Memory Block Access Control Select for block B
88808  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88809  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88810  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88811  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88812  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88813  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88814  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88815  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88816  */
88817 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK)
88818 
88819 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
88820 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
88821 /*! NSE2 - NonSecure Enable for block B
88822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88825  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88826  */
88827 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK)
88828 
88829 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
88830 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
88831 /*! MBACSEL3 - Memory Block Access Control Select for block B
88832  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88833  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88834  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88835  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88836  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88837  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88838  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88839  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88840  */
88841 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK)
88842 
88843 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
88844 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
88845 /*! NSE3 - NonSecure Enable for block B
88846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88849  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88850  */
88851 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK)
88852 
88853 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
88854 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
88855 /*! MBACSEL4 - Memory Block Access Control Select for block B
88856  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88857  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88858  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88859  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88860  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88861  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88862  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88863  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88864  */
88865 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK)
88866 
88867 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
88868 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
88869 /*! NSE4 - NonSecure Enable for block B
88870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88873  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88874  */
88875 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK)
88876 
88877 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
88878 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
88879 /*! MBACSEL5 - Memory Block Access Control Select for block B
88880  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88881  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88882  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88883  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88884  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88885  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88886  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88887  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88888  */
88889 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK)
88890 
88891 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
88892 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
88893 /*! NSE5 - NonSecure Enable for block B
88894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88897  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88898  */
88899 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK)
88900 
88901 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
88902 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
88903 /*! MBACSEL6 - Memory Block Access Control Select for block B
88904  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88905  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88906  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88907  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88908  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88909  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88910  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88911  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88912  */
88913 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK)
88914 
88915 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
88916 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
88917 /*! NSE6 - NonSecure Enable for block B
88918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88921  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88922  */
88923 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK)
88924 
88925 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
88926 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
88927 /*! MBACSEL7 - Memory Block Access Control Select for block B
88928  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
88929  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
88930  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
88931  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
88932  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
88933  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
88934  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
88935  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
88936  */
88937 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK)
88938 
88939 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
88940 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
88941 /*! NSE7 - NonSecure Enable for block B
88942  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
88943  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88944  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88945  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88946  */
88947 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK)
88948 /*! @} */
88949 
88950 /* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
88951 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT       (2U)
88952 
88953 /* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
88954 #define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2      (3U)
88955 
88956 /*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
88957 /*! @{ */
88958 
88959 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
88960 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
88961 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
88962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88965  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88966  */
88967 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK)
88968 
88969 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
88970 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
88971 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
88972  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88973  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88974  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88975  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88976  */
88977 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK)
88978 
88979 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
88980 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
88981 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
88982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88985  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88986  */
88987 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK)
88988 
88989 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
88990 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
88991 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
88992  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
88993  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
88994  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
88995  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
88996  */
88997 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK)
88998 
88999 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
89000 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
89001 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
89002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89005  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89006  */
89007 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK)
89008 
89009 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
89010 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
89011 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
89012  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89013  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89014  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89015  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89016  */
89017 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK)
89018 
89019 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
89020 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
89021 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
89022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89025  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89026  */
89027 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK)
89028 
89029 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
89030 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
89031 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
89032  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89033  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89034  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89035  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89036  */
89037 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK)
89038 
89039 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
89040 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
89041 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
89042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89045  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89046  */
89047 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK)
89048 
89049 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
89050 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
89051 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
89052  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89053  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89054  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89055  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89056  */
89057 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK)
89058 
89059 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
89060 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
89061 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
89062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89065  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89066  */
89067 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK)
89068 
89069 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
89070 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
89071 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
89072  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89073  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89074  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89075  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89076  */
89077 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK)
89078 
89079 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
89080 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
89081 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
89082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89085  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89086  */
89087 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK)
89088 
89089 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
89090 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
89091 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
89092  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89093  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89094  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89095  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89096  */
89097 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK)
89098 
89099 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
89100 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
89101 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
89102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89105  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89106  */
89107 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK)
89108 
89109 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
89110 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
89111 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
89112  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89113  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89114  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89115  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89116  */
89117 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK)
89118 
89119 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
89120 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
89121 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
89122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89125  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89126  */
89127 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK)
89128 
89129 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
89130 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
89131 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
89132  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89133  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89134  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89135  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89136  */
89137 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK)
89138 
89139 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
89140 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
89141 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
89142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89145  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89146  */
89147 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK)
89148 
89149 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
89150 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
89151 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
89152  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89153  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89154  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89155  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89156  */
89157 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK)
89158 
89159 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
89160 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
89161 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
89162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89165  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89166  */
89167 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK)
89168 
89169 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
89170 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
89171 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
89172  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89173  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89174  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89175  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89176  */
89177 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK)
89178 
89179 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
89180 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
89181 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
89182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89185  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89186  */
89187 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK)
89188 
89189 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
89190 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
89191 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
89192  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89193  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89194  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89195  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89196  */
89197 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK)
89198 
89199 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
89200 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
89201 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
89202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89205  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89206  */
89207 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK)
89208 
89209 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
89210 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
89211 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
89212  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89213  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89214  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89215  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89216  */
89217 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK)
89218 
89219 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
89220 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
89221 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
89222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89225  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89226  */
89227 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK)
89228 
89229 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
89230 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
89231 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
89232  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89233  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89234  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89235  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89236  */
89237 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK)
89238 
89239 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
89240 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
89241 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
89242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89245  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89246  */
89247 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK)
89248 
89249 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
89250 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
89251 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
89252  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89253  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89254  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89255  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89256  */
89257 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK)
89258 
89259 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
89260 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
89261 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
89262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89265  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89266  */
89267 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK)
89268 
89269 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
89270 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
89271 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
89272  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89273  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89274  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89275  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89276  */
89277 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK)
89278 /*! @} */
89279 
89280 /* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
89281 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT       (2U)
89282 
89283 /* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
89284 #define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2      (1U)
89285 
89286 /*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
89287 /*! @{ */
89288 
89289 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
89290 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
89291 /*! MBACSEL0 - Memory Block Access Control Select for block B
89292  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89293  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89294  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89295  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89296  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89297  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89298  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89299  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89300  */
89301 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK)
89302 
89303 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
89304 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
89305 /*! NSE0 - NonSecure Enable for block B
89306  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89307  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89308  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89309  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89310  */
89311 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK)
89312 
89313 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
89314 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
89315 /*! MBACSEL1 - Memory Block Access Control Select for block B
89316  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89317  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89318  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89319  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89320  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89321  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89322  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89323  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89324  */
89325 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK)
89326 
89327 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
89328 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
89329 /*! NSE1 - NonSecure Enable for block B
89330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89333  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89334  */
89335 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK)
89336 
89337 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
89338 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
89339 /*! MBACSEL2 - Memory Block Access Control Select for block B
89340  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89341  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89342  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89343  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89344  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89345  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89346  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89347  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89348  */
89349 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK)
89350 
89351 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
89352 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
89353 /*! NSE2 - NonSecure Enable for block B
89354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89357  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89358  */
89359 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK)
89360 
89361 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
89362 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
89363 /*! MBACSEL3 - Memory Block Access Control Select for block B
89364  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89365  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89366  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89367  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89368  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89369  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89370  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89371  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89372  */
89373 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK)
89374 
89375 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
89376 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
89377 /*! NSE3 - NonSecure Enable for block B
89378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89381  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89382  */
89383 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK)
89384 
89385 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
89386 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
89387 /*! MBACSEL4 - Memory Block Access Control Select for block B
89388  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89389  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89390  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89391  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89392  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89393  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89394  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89395  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89396  */
89397 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK)
89398 
89399 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
89400 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
89401 /*! NSE4 - NonSecure Enable for block B
89402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89405  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89406  */
89407 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK)
89408 
89409 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
89410 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
89411 /*! MBACSEL5 - Memory Block Access Control Select for block B
89412  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89413  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89414  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89415  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89416  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89417  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89418  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89419  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89420  */
89421 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK)
89422 
89423 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
89424 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
89425 /*! NSE5 - NonSecure Enable for block B
89426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89429  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89430  */
89431 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK)
89432 
89433 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
89434 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
89435 /*! MBACSEL6 - Memory Block Access Control Select for block B
89436  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89437  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89438  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89439  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89440  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89441  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89442  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89443  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89444  */
89445 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK)
89446 
89447 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
89448 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
89449 /*! NSE6 - NonSecure Enable for block B
89450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89453  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89454  */
89455 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK)
89456 
89457 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
89458 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
89459 /*! MBACSEL7 - Memory Block Access Control Select for block B
89460  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89461  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89462  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89463  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89464  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89465  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89466  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89467  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89468  */
89469 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK)
89470 
89471 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
89472 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
89473 /*! NSE7 - NonSecure Enable for block B
89474  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89475  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89476  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89477  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89478  */
89479 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK)
89480 /*! @} */
89481 
89482 /* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
89483 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT       (2U)
89484 
89485 /* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
89486 #define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2      (16U)
89487 
89488 /*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
89489 /*! @{ */
89490 
89491 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
89492 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
89493 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
89494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89497  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89498  */
89499 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK)
89500 
89501 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
89502 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
89503 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
89504  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89505  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89506  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89507  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89508  */
89509 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK)
89510 
89511 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
89512 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
89513 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
89514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89517  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89518  */
89519 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK)
89520 
89521 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
89522 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
89523 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
89524  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89525  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89526  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89527  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89528  */
89529 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK)
89530 
89531 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
89532 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
89533 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
89534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89537  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89538  */
89539 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK)
89540 
89541 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
89542 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
89543 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
89544  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89545  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89546  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89547  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89548  */
89549 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK)
89550 
89551 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
89552 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
89553 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
89554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89557  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89558  */
89559 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK)
89560 
89561 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
89562 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
89563 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
89564  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89565  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89566  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89567  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89568  */
89569 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK)
89570 
89571 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
89572 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
89573 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
89574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89577  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89578  */
89579 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK)
89580 
89581 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
89582 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
89583 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
89584  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89585  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89586  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89587  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89588  */
89589 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK)
89590 
89591 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
89592 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
89593 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
89594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89597  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89598  */
89599 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK)
89600 
89601 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
89602 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
89603 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
89604  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89605  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89606  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89607  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89608  */
89609 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK)
89610 
89611 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
89612 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
89613 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
89614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89617  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89618  */
89619 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK)
89620 
89621 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
89622 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
89623 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
89624  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89625  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89626  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89627  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89628  */
89629 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK)
89630 
89631 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
89632 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
89633 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
89634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89637  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89638  */
89639 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK)
89640 
89641 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
89642 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
89643 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
89644  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89645  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89646  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89647  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89648  */
89649 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK)
89650 
89651 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
89652 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
89653 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
89654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89657  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89658  */
89659 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK)
89660 
89661 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
89662 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
89663 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
89664  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89665  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89666  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89667  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89668  */
89669 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK)
89670 
89671 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
89672 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
89673 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
89674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89677  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89678  */
89679 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK)
89680 
89681 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
89682 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
89683 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
89684  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89685  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89686  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89687  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89688  */
89689 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK)
89690 
89691 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
89692 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
89693 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
89694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89697  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89698  */
89699 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK)
89700 
89701 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
89702 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
89703 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
89704  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89705  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89706  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89707  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89708  */
89709 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK)
89710 
89711 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
89712 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
89713 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
89714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89717  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89718  */
89719 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK)
89720 
89721 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
89722 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
89723 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
89724  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89725  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89726  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89727  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89728  */
89729 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK)
89730 
89731 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
89732 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
89733 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
89734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89737  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89738  */
89739 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK)
89740 
89741 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
89742 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
89743 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
89744  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89745  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89746  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89747  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89748  */
89749 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK)
89750 
89751 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
89752 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
89753 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
89754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89757  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89758  */
89759 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK)
89760 
89761 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
89762 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
89763 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
89764  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89765  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89766  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89767  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89768  */
89769 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK)
89770 
89771 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
89772 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
89773 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
89774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89777  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89778  */
89779 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK)
89780 
89781 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
89782 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
89783 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
89784  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89785  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89786  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89787  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89788  */
89789 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK)
89790 
89791 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
89792 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
89793 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
89794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89797  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89798  */
89799 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK)
89800 
89801 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
89802 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
89803 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
89804  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
89805  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89806  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89807  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89808  */
89809 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK)
89810 /*! @} */
89811 
89812 /* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
89813 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT       (2U)
89814 
89815 /* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
89816 #define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2      (4U)
89817 
89818 /*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
89819 /*! @{ */
89820 
89821 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
89822 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
89823 /*! MBACSEL0 - Memory Block Access Control Select for block B
89824  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89825  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89826  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89827  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89828  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89829  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89830  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89831  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89832  */
89833 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK)
89834 
89835 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
89836 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
89837 /*! NSE0 - NonSecure Enable for block B
89838  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89839  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89840  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89841  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89842  */
89843 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK)
89844 
89845 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
89846 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
89847 /*! MBACSEL1 - Memory Block Access Control Select for block B
89848  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89849  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89850  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89851  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89852  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89853  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89854  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89855  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89856  */
89857 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK)
89858 
89859 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
89860 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
89861 /*! NSE1 - NonSecure Enable for block B
89862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89865  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89866  */
89867 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK)
89868 
89869 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
89870 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
89871 /*! MBACSEL2 - Memory Block Access Control Select for block B
89872  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89873  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89874  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89875  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89876  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89877  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89878  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89879  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89880  */
89881 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK)
89882 
89883 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
89884 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
89885 /*! NSE2 - NonSecure Enable for block B
89886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89889  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89890  */
89891 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK)
89892 
89893 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
89894 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
89895 /*! MBACSEL3 - Memory Block Access Control Select for block B
89896  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89897  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89898  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89899  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89900  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89901  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89902  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89903  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89904  */
89905 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK)
89906 
89907 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
89908 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
89909 /*! NSE3 - NonSecure Enable for block B
89910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89913  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89914  */
89915 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK)
89916 
89917 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
89918 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
89919 /*! MBACSEL4 - Memory Block Access Control Select for block B
89920  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89921  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89922  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89923  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89924  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89925  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89926  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89927  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89928  */
89929 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK)
89930 
89931 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
89932 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
89933 /*! NSE4 - NonSecure Enable for block B
89934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89937  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89938  */
89939 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK)
89940 
89941 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
89942 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
89943 /*! MBACSEL5 - Memory Block Access Control Select for block B
89944  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89945  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89946  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89947  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89948  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89949  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89950  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89951  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89952  */
89953 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK)
89954 
89955 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
89956 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
89957 /*! NSE5 - NonSecure Enable for block B
89958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89961  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89962  */
89963 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK)
89964 
89965 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
89966 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
89967 /*! MBACSEL6 - Memory Block Access Control Select for block B
89968  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89969  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89970  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89971  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89972  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89973  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89974  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89975  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
89976  */
89977 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK)
89978 
89979 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
89980 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
89981 /*! NSE6 - NonSecure Enable for block B
89982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
89983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
89984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
89985  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
89986  */
89987 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK)
89988 
89989 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
89990 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
89991 /*! MBACSEL7 - Memory Block Access Control Select for block B
89992  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
89993  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
89994  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
89995  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
89996  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
89997  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
89998  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
89999  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90000  */
90001 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK)
90002 
90003 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
90004 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
90005 /*! NSE7 - NonSecure Enable for block B
90006  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90007  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90008  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90009  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90010  */
90011 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK)
90012 /*! @} */
90013 
90014 /* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
90015 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT       (2U)
90016 
90017 /* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
90018 #define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2      (4U)
90019 
90020 /*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
90021 /*! @{ */
90022 
90023 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
90024 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
90025 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
90026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90029  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90030  */
90031 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK)
90032 
90033 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
90034 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
90035 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
90036  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90037  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90038  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90039  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90040  */
90041 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK)
90042 
90043 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
90044 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
90045 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
90046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90049  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90050  */
90051 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK)
90052 
90053 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
90054 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
90055 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
90056  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90057  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90058  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90059  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90060  */
90061 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK)
90062 
90063 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
90064 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
90065 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
90066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90069  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90070  */
90071 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK)
90072 
90073 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
90074 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
90075 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
90076  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90077  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90078  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90079  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90080  */
90081 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK)
90082 
90083 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
90084 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
90085 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
90086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90089  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90090  */
90091 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK)
90092 
90093 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
90094 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
90095 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
90096  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90097  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90098  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90099  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90100  */
90101 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK)
90102 
90103 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
90104 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
90105 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
90106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90109  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90110  */
90111 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK)
90112 
90113 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
90114 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
90115 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
90116  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90117  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90118  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90119  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90120  */
90121 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK)
90122 
90123 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
90124 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
90125 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
90126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90129  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90130  */
90131 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK)
90132 
90133 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
90134 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
90135 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
90136  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90137  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90138  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90139  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90140  */
90141 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK)
90142 
90143 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
90144 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
90145 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
90146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90149  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90150  */
90151 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK)
90152 
90153 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
90154 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
90155 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
90156  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90157  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90158  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90159  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90160  */
90161 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK)
90162 
90163 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
90164 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
90165 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
90166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90169  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90170  */
90171 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK)
90172 
90173 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
90174 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
90175 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
90176  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90177  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90178  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90179  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90180  */
90181 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK)
90182 
90183 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
90184 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
90185 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
90186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90189  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90190  */
90191 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK)
90192 
90193 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
90194 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
90195 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
90196  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90197  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90198  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90199  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90200  */
90201 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK)
90202 
90203 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
90204 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
90205 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
90206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90209  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90210  */
90211 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK)
90212 
90213 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
90214 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
90215 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
90216  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90217  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90218  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90219  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90220  */
90221 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK)
90222 
90223 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
90224 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
90225 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
90226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90229  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90230  */
90231 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK)
90232 
90233 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
90234 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
90235 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
90236  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90237  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90238  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90239  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90240  */
90241 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK)
90242 
90243 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
90244 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
90245 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
90246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90249  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90250  */
90251 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK)
90252 
90253 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
90254 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
90255 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
90256  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90257  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90258  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90259  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90260  */
90261 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK)
90262 
90263 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
90264 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
90265 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
90266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90269  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90270  */
90271 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK)
90272 
90273 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
90274 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
90275 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
90276  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90277  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90278  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90279  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90280  */
90281 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK)
90282 
90283 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
90284 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
90285 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
90286  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90287  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90288  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90289  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90290  */
90291 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK)
90292 
90293 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
90294 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
90295 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
90296  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90297  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90298  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90299  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90300  */
90301 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK)
90302 
90303 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
90304 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
90305 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
90306  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90307  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90308  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90309  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90310  */
90311 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK)
90312 
90313 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
90314 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
90315 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
90316  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90317  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90318  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90319  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90320  */
90321 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK)
90322 
90323 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
90324 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
90325 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
90326  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90327  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90328  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90329  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90330  */
90331 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK)
90332 
90333 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
90334 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
90335 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
90336  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90337  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90338  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90339  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90340  */
90341 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK)
90342 /*! @} */
90343 
90344 /* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
90345 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT       (2U)
90346 
90347 /* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
90348 #define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2      (1U)
90349 
90350 /*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
90351 /*! @{ */
90352 
90353 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
90354 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
90355 /*! MBACSEL0 - Memory Block Access Control Select for block B
90356  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90357  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90358  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90359  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90360  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90361  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90362  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90363  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90364  */
90365 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK)
90366 
90367 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
90368 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
90369 /*! NSE0 - NonSecure Enable for block B
90370  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90371  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90372  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90373  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90374  */
90375 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK)
90376 
90377 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
90378 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
90379 /*! MBACSEL1 - Memory Block Access Control Select for block B
90380  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90381  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90382  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90383  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90384  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90385  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90386  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90387  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90388  */
90389 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK)
90390 
90391 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
90392 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
90393 /*! NSE1 - NonSecure Enable for block B
90394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90397  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90398  */
90399 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK)
90400 
90401 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
90402 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
90403 /*! MBACSEL2 - Memory Block Access Control Select for block B
90404  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90405  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90406  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90407  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90408  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90409  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90410  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90411  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90412  */
90413 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK)
90414 
90415 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
90416 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
90417 /*! NSE2 - NonSecure Enable for block B
90418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90421  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90422  */
90423 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK)
90424 
90425 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
90426 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
90427 /*! MBACSEL3 - Memory Block Access Control Select for block B
90428  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90429  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90430  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90431  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90432  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90433  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90434  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90435  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90436  */
90437 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK)
90438 
90439 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
90440 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
90441 /*! NSE3 - NonSecure Enable for block B
90442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90445  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90446  */
90447 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK)
90448 
90449 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
90450 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
90451 /*! MBACSEL4 - Memory Block Access Control Select for block B
90452  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90453  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90454  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90455  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90456  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90457  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90458  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90459  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90460  */
90461 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK)
90462 
90463 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
90464 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
90465 /*! NSE4 - NonSecure Enable for block B
90466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90469  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90470  */
90471 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK)
90472 
90473 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
90474 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
90475 /*! MBACSEL5 - Memory Block Access Control Select for block B
90476  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90477  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90478  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90479  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90480  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90481  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90482  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90483  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90484  */
90485 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK)
90486 
90487 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
90488 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
90489 /*! NSE5 - NonSecure Enable for block B
90490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90493  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90494  */
90495 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK)
90496 
90497 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
90498 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
90499 /*! MBACSEL6 - Memory Block Access Control Select for block B
90500  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90501  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90502  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90503  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90504  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90505  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90506  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90507  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90508  */
90509 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK)
90510 
90511 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
90512 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
90513 /*! NSE6 - NonSecure Enable for block B
90514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90517  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90518  */
90519 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK)
90520 
90521 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
90522 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
90523 /*! MBACSEL7 - Memory Block Access Control Select for block B
90524  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90525  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90526  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90527  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90528  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90529  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90530  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90531  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90532  */
90533 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK)
90534 
90535 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
90536 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
90537 /*! NSE7 - NonSecure Enable for block B
90538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90541  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90542  */
90543 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK)
90544 /*! @} */
90545 
90546 /* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
90547 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT       (2U)
90548 
90549 /* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
90550 #define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2      (1U)
90551 
90552 /*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
90553 /*! @{ */
90554 
90555 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
90556 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
90557 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
90558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90561  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90562  */
90563 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK)
90564 
90565 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
90566 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
90567 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
90568  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90569  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90570  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90571  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90572  */
90573 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK)
90574 
90575 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
90576 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
90577 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
90578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90581  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90582  */
90583 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK)
90584 
90585 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
90586 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
90587 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
90588  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90589  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90590  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90591  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90592  */
90593 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK)
90594 
90595 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
90596 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
90597 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
90598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90601  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90602  */
90603 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK)
90604 
90605 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
90606 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
90607 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
90608  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90609  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90610  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90611  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90612  */
90613 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK)
90614 
90615 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
90616 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
90617 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
90618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90621  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90622  */
90623 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK)
90624 
90625 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
90626 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
90627 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
90628  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90629  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90630  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90631  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90632  */
90633 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK)
90634 
90635 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
90636 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
90637 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
90638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90641  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90642  */
90643 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK)
90644 
90645 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
90646 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
90647 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
90648  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90649  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90650  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90651  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90652  */
90653 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK)
90654 
90655 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
90656 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
90657 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
90658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90661  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90662  */
90663 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK)
90664 
90665 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
90666 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
90667 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
90668  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90669  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90670  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90671  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90672  */
90673 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK)
90674 
90675 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
90676 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
90677 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
90678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90681  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90682  */
90683 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK)
90684 
90685 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
90686 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
90687 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
90688  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90689  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90690  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90691  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90692  */
90693 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK)
90694 
90695 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
90696 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
90697 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
90698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90701  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90702  */
90703 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK)
90704 
90705 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
90706 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
90707 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
90708  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90709  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90710  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90711  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90712  */
90713 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK)
90714 
90715 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
90716 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
90717 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
90718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90721  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90722  */
90723 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK)
90724 
90725 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
90726 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
90727 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
90728  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90729  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90730  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90731  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90732  */
90733 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK)
90734 
90735 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
90736 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
90737 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
90738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90741  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90742  */
90743 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK)
90744 
90745 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
90746 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
90747 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
90748  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90749  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90750  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90751  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90752  */
90753 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK)
90754 
90755 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
90756 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
90757 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
90758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90761  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90762  */
90763 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK)
90764 
90765 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
90766 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
90767 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
90768  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90769  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90770  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90771  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90772  */
90773 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK)
90774 
90775 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
90776 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
90777 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
90778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90781  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90782  */
90783 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK)
90784 
90785 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
90786 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
90787 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
90788  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90789  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90790  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90791  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90792  */
90793 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK)
90794 
90795 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
90796 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
90797 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
90798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90801  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90802  */
90803 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK)
90804 
90805 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
90806 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
90807 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
90808  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90809  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90810  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90811  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90812  */
90813 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK)
90814 
90815 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
90816 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
90817 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
90818  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90819  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90820  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90821  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90822  */
90823 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK)
90824 
90825 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
90826 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
90827 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
90828  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90829  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90830  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90831  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90832  */
90833 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK)
90834 
90835 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
90836 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
90837 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
90838  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90839  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90840  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90841  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90842  */
90843 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK)
90844 
90845 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
90846 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
90847 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
90848  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90849  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90850  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90851  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90852  */
90853 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK)
90854 
90855 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
90856 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
90857 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
90858  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90859  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90860  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90861  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90862  */
90863 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK)
90864 
90865 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
90866 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
90867 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
90868  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
90869  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90870  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90871  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90872  */
90873 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK)
90874 /*! @} */
90875 
90876 /* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
90877 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT       (2U)
90878 
90879 /* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
90880 #define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2      (1U)
90881 
90882 /*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
90883 /*! @{ */
90884 
90885 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
90886 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
90887 /*! MBACSEL0 - Memory Block Access Control Select for block B
90888  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90889  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90890  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90891  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90892  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90893  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90894  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90895  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90896  */
90897 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK)
90898 
90899 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
90900 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
90901 /*! NSE0 - NonSecure Enable for block B
90902  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90903  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90904  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90905  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90906  */
90907 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK)
90908 
90909 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
90910 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
90911 /*! MBACSEL1 - Memory Block Access Control Select for block B
90912  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90913  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90914  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90915  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90916  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90917  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90918  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90919  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90920  */
90921 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK)
90922 
90923 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
90924 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
90925 /*! NSE1 - NonSecure Enable for block B
90926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90929  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90930  */
90931 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK)
90932 
90933 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
90934 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
90935 /*! MBACSEL2 - Memory Block Access Control Select for block B
90936  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90937  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90938  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90939  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90940  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90941  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90942  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90943  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90944  */
90945 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK)
90946 
90947 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
90948 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
90949 /*! NSE2 - NonSecure Enable for block B
90950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90953  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90954  */
90955 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK)
90956 
90957 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
90958 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
90959 /*! MBACSEL3 - Memory Block Access Control Select for block B
90960  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90961  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90962  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90963  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90964  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90965  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90966  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90967  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90968  */
90969 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK)
90970 
90971 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
90972 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
90973 /*! NSE3 - NonSecure Enable for block B
90974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
90976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
90977  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
90978  */
90979 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK)
90980 
90981 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
90982 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
90983 /*! MBACSEL4 - Memory Block Access Control Select for block B
90984  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
90985  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
90986  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
90987  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
90988  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
90989  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
90990  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
90991  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
90992  */
90993 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK)
90994 
90995 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
90996 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
90997 /*! NSE4 - NonSecure Enable for block B
90998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
90999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91001  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91002  */
91003 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK)
91004 
91005 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
91006 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
91007 /*! MBACSEL5 - Memory Block Access Control Select for block B
91008  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91009  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91010  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91011  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91012  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91013  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91014  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91015  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91016  */
91017 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK)
91018 
91019 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
91020 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
91021 /*! NSE5 - NonSecure Enable for block B
91022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91025  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91026  */
91027 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK)
91028 
91029 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
91030 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
91031 /*! MBACSEL6 - Memory Block Access Control Select for block B
91032  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91033  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91034  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91035  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91036  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91037  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91038  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91039  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91040  */
91041 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK)
91042 
91043 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
91044 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
91045 /*! NSE6 - NonSecure Enable for block B
91046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91049  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91050  */
91051 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK)
91052 
91053 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
91054 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
91055 /*! MBACSEL7 - Memory Block Access Control Select for block B
91056  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91057  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91058  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91059  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91060  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91061  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91062  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91063  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91064  */
91065 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK)
91066 
91067 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
91068 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
91069 /*! NSE7 - NonSecure Enable for block B
91070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91073  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91074  */
91075 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK)
91076 /*! @} */
91077 
91078 /* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
91079 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT       (2U)
91080 
91081 /* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
91082 #define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2      (3U)
91083 
91084 /*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
91085 /*! @{ */
91086 
91087 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
91088 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
91089 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
91090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91093  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91094  */
91095 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK)
91096 
91097 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
91098 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
91099 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
91100  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91101  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91102  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91103  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91104  */
91105 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK)
91106 
91107 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
91108 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
91109 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
91110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91113  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91114  */
91115 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK)
91116 
91117 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
91118 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
91119 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
91120  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91121  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91122  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91123  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91124  */
91125 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK)
91126 
91127 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
91128 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
91129 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
91130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91133  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91134  */
91135 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK)
91136 
91137 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
91138 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
91139 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
91140  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91141  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91142  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91143  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91144  */
91145 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK)
91146 
91147 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
91148 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
91149 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
91150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91153  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91154  */
91155 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK)
91156 
91157 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
91158 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
91159 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
91160  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91161  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91162  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91163  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91164  */
91165 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK)
91166 
91167 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
91168 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
91169 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
91170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91173  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91174  */
91175 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK)
91176 
91177 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
91178 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
91179 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
91180  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91181  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91182  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91183  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91184  */
91185 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK)
91186 
91187 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
91188 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
91189 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
91190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91193  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91194  */
91195 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK)
91196 
91197 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
91198 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
91199 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
91200  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91201  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91202  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91203  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91204  */
91205 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK)
91206 
91207 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
91208 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
91209 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
91210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91213  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91214  */
91215 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK)
91216 
91217 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
91218 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
91219 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
91220  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91221  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91222  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91223  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91224  */
91225 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK)
91226 
91227 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
91228 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
91229 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
91230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91233  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91234  */
91235 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK)
91236 
91237 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
91238 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
91239 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
91240  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91241  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91242  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91243  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91244  */
91245 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK)
91246 
91247 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
91248 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
91249 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
91250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91253  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91254  */
91255 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK)
91256 
91257 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
91258 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
91259 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
91260  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91261  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91262  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91263  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91264  */
91265 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK)
91266 
91267 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
91268 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
91269 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
91270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91273  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91274  */
91275 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK)
91276 
91277 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
91278 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
91279 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
91280  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91281  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91282  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91283  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91284  */
91285 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK)
91286 
91287 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
91288 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
91289 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
91290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91293  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91294  */
91295 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK)
91296 
91297 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
91298 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
91299 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
91300  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91301  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91302  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91303  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91304  */
91305 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK)
91306 
91307 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
91308 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
91309 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
91310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91313  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91314  */
91315 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK)
91316 
91317 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
91318 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
91319 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
91320  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91321  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91322  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91323  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91324  */
91325 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK)
91326 
91327 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
91328 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
91329 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
91330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91333  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91334  */
91335 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK)
91336 
91337 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
91338 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
91339 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
91340  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91341  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91342  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91343  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91344  */
91345 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK)
91346 
91347 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
91348 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
91349 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
91350  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91351  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91352  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91353  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91354  */
91355 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK)
91356 
91357 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
91358 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
91359 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
91360  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91361  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91362  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91363  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91364  */
91365 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK)
91366 
91367 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
91368 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
91369 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
91370  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91371  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91372  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91373  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91374  */
91375 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK)
91376 
91377 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
91378 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
91379 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
91380  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91381  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91382  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91383  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91384  */
91385 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK)
91386 
91387 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
91388 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
91389 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
91390  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91391  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91392  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91393  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91394  */
91395 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK)
91396 
91397 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
91398 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
91399 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
91400  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91401  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91402  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91403  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91404  */
91405 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK)
91406 /*! @} */
91407 
91408 /* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
91409 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT       (2U)
91410 
91411 /* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
91412 #define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2      (1U)
91413 
91414 /*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
91415 /*! @{ */
91416 
91417 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
91418 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
91419 /*! MBACSEL0 - Memory Block Access Control Select for block B
91420  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91421  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91422  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91423  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91424  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91425  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91426  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91427  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91428  */
91429 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK)
91430 
91431 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
91432 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
91433 /*! NSE0 - NonSecure Enable for block B
91434  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91435  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91436  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91437  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91438  */
91439 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK)
91440 
91441 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
91442 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
91443 /*! MBACSEL1 - Memory Block Access Control Select for block B
91444  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91445  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91446  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91447  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91448  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91449  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91450  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91451  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91452  */
91453 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK)
91454 
91455 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
91456 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
91457 /*! NSE1 - NonSecure Enable for block B
91458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91461  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91462  */
91463 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK)
91464 
91465 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
91466 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
91467 /*! MBACSEL2 - Memory Block Access Control Select for block B
91468  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91469  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91470  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91471  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91472  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91473  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91474  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91475  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91476  */
91477 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK)
91478 
91479 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
91480 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
91481 /*! NSE2 - NonSecure Enable for block B
91482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91485  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91486  */
91487 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK)
91488 
91489 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
91490 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
91491 /*! MBACSEL3 - Memory Block Access Control Select for block B
91492  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91493  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91494  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91495  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91496  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91497  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91498  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91499  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91500  */
91501 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK)
91502 
91503 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
91504 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
91505 /*! NSE3 - NonSecure Enable for block B
91506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91509  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91510  */
91511 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK)
91512 
91513 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
91514 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
91515 /*! MBACSEL4 - Memory Block Access Control Select for block B
91516  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91517  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91518  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91519  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91520  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91521  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91522  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91523  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91524  */
91525 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK)
91526 
91527 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
91528 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
91529 /*! NSE4 - NonSecure Enable for block B
91530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91533  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91534  */
91535 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK)
91536 
91537 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
91538 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
91539 /*! MBACSEL5 - Memory Block Access Control Select for block B
91540  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91541  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91542  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91543  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91544  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91545  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91546  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91547  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91548  */
91549 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK)
91550 
91551 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
91552 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
91553 /*! NSE5 - NonSecure Enable for block B
91554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91557  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91558  */
91559 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK)
91560 
91561 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
91562 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
91563 /*! MBACSEL6 - Memory Block Access Control Select for block B
91564  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91565  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91566  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91567  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91568  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91569  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91570  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91571  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91572  */
91573 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK)
91574 
91575 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
91576 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
91577 /*! NSE6 - NonSecure Enable for block B
91578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91581  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91582  */
91583 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK)
91584 
91585 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
91586 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
91587 /*! MBACSEL7 - Memory Block Access Control Select for block B
91588  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91589  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91590  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91591  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91592  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91593  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91594  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91595  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91596  */
91597 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK)
91598 
91599 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
91600 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
91601 /*! NSE7 - NonSecure Enable for block B
91602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91605  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91606  */
91607 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK)
91608 /*! @} */
91609 
91610 /* The count of TRDC_MBC_DOM3_MEM0_BLK_CFG_W */
91611 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_COUNT       (2U)
91612 
91613 /* The count of TRDC_MBC_DOM3_MEM0_BLK_CFG_W */
91614 #define TRDC_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2      (16U)
91615 
91616 /*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
91617 /*! @{ */
91618 
91619 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
91620 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
91621 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
91622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91625  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91626  */
91627 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK)
91628 
91629 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
91630 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
91631 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
91632  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91633  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91634  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91635  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91636  */
91637 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK)
91638 
91639 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
91640 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
91641 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
91642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91645  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91646  */
91647 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK)
91648 
91649 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
91650 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
91651 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
91652  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91653  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91654  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91655  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91656  */
91657 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK)
91658 
91659 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
91660 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
91661 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
91662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91665  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91666  */
91667 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK)
91668 
91669 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
91670 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
91671 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
91672  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91673  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91674  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91675  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91676  */
91677 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK)
91678 
91679 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
91680 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
91681 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
91682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91685  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91686  */
91687 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK)
91688 
91689 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
91690 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
91691 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
91692  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91693  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91694  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91695  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91696  */
91697 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK)
91698 
91699 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
91700 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
91701 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
91702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91705  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91706  */
91707 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK)
91708 
91709 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
91710 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
91711 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
91712  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91713  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91714  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91715  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91716  */
91717 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK)
91718 
91719 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
91720 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
91721 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
91722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91725  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91726  */
91727 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK)
91728 
91729 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
91730 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
91731 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
91732  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91733  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91734  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91735  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91736  */
91737 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK)
91738 
91739 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
91740 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
91741 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
91742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91745  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91746  */
91747 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK)
91748 
91749 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
91750 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
91751 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
91752  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91753  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91754  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91755  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91756  */
91757 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK)
91758 
91759 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
91760 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
91761 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
91762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91765  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91766  */
91767 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK)
91768 
91769 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
91770 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
91771 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
91772  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91773  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91774  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91775  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91776  */
91777 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK)
91778 
91779 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
91780 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
91781 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
91782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91785  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91786  */
91787 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK)
91788 
91789 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
91790 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
91791 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
91792  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91793  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91794  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91795  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91796  */
91797 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK)
91798 
91799 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
91800 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
91801 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
91802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91805  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91806  */
91807 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK)
91808 
91809 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
91810 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
91811 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
91812  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91813  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91814  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91815  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91816  */
91817 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK)
91818 
91819 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
91820 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
91821 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
91822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91825  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91826  */
91827 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK)
91828 
91829 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
91830 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
91831 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
91832  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91833  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91834  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91835  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91836  */
91837 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK)
91838 
91839 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
91840 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
91841 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
91842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91845  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91846  */
91847 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK)
91848 
91849 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
91850 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
91851 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
91852  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91853  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91854  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91855  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91856  */
91857 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK)
91858 
91859 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
91860 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
91861 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
91862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91865  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91866  */
91867 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK)
91868 
91869 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
91870 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
91871 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
91872  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91873  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91874  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91875  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91876  */
91877 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK)
91878 
91879 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
91880 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
91881 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
91882  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91883  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91884  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91885  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91886  */
91887 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK)
91888 
91889 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
91890 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
91891 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
91892  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91893  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91894  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91895  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91896  */
91897 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK)
91898 
91899 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
91900 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
91901 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
91902  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91903  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91904  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91905  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91906  */
91907 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK)
91908 
91909 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
91910 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
91911 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
91912  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91913  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91914  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91915  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91916  */
91917 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK)
91918 
91919 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
91920 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
91921 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
91922  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91923  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91924  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91925  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91926  */
91927 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK)
91928 
91929 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
91930 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
91931 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
91932  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
91933  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91934  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91935  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91936  */
91937 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK)
91938 /*! @} */
91939 
91940 /* The count of TRDC_MBC_DOM3_MEM0_BLK_NSE_W */
91941 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_COUNT       (2U)
91942 
91943 /* The count of TRDC_MBC_DOM3_MEM0_BLK_NSE_W */
91944 #define TRDC_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2      (4U)
91945 
91946 /*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
91947 /*! @{ */
91948 
91949 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
91950 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
91951 /*! MBACSEL0 - Memory Block Access Control Select for block B
91952  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91953  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91954  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91955  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91956  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91957  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91958  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91959  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91960  */
91961 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK)
91962 
91963 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
91964 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
91965 /*! NSE0 - NonSecure Enable for block B
91966  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91967  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91968  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91969  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91970  */
91971 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK)
91972 
91973 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
91974 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
91975 /*! MBACSEL1 - Memory Block Access Control Select for block B
91976  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
91977  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
91978  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
91979  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
91980  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
91981  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
91982  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
91983  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
91984  */
91985 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK)
91986 
91987 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
91988 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
91989 /*! NSE1 - NonSecure Enable for block B
91990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
91991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
91992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
91993  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
91994  */
91995 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK)
91996 
91997 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
91998 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
91999 /*! MBACSEL2 - Memory Block Access Control Select for block B
92000  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92001  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92002  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92003  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92004  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92005  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92006  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92007  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92008  */
92009 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK)
92010 
92011 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
92012 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
92013 /*! NSE2 - NonSecure Enable for block B
92014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92017  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92018  */
92019 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK)
92020 
92021 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
92022 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
92023 /*! MBACSEL3 - Memory Block Access Control Select for block B
92024  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92025  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92026  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92027  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92028  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92029  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92030  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92031  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92032  */
92033 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK)
92034 
92035 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
92036 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
92037 /*! NSE3 - NonSecure Enable for block B
92038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92041  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92042  */
92043 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK)
92044 
92045 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
92046 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
92047 /*! MBACSEL4 - Memory Block Access Control Select for block B
92048  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92049  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92050  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92051  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92052  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92053  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92054  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92055  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92056  */
92057 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK)
92058 
92059 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
92060 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
92061 /*! NSE4 - NonSecure Enable for block B
92062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92065  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92066  */
92067 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK)
92068 
92069 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
92070 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
92071 /*! MBACSEL5 - Memory Block Access Control Select for block B
92072  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92073  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92074  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92075  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92076  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92077  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92078  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92079  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92080  */
92081 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK)
92082 
92083 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
92084 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
92085 /*! NSE5 - NonSecure Enable for block B
92086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92089  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92090  */
92091 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK)
92092 
92093 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
92094 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
92095 /*! MBACSEL6 - Memory Block Access Control Select for block B
92096  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92097  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92098  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92099  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92100  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92101  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92102  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92103  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92104  */
92105 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK)
92106 
92107 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
92108 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
92109 /*! NSE6 - NonSecure Enable for block B
92110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92113  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92114  */
92115 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK)
92116 
92117 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
92118 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
92119 /*! MBACSEL7 - Memory Block Access Control Select for block B
92120  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92121  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92122  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92123  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92124  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92125  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92126  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92127  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92128  */
92129 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK)
92130 
92131 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
92132 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
92133 /*! NSE7 - NonSecure Enable for block B
92134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92137  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92138  */
92139 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK)
92140 /*! @} */
92141 
92142 /* The count of TRDC_MBC_DOM3_MEM1_BLK_CFG_W */
92143 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_COUNT       (2U)
92144 
92145 /* The count of TRDC_MBC_DOM3_MEM1_BLK_CFG_W */
92146 #define TRDC_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2      (4U)
92147 
92148 /*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
92149 /*! @{ */
92150 
92151 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
92152 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
92153 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
92154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92157  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92158  */
92159 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK)
92160 
92161 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
92162 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
92163 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
92164  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92165  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92166  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92167  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92168  */
92169 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK)
92170 
92171 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
92172 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
92173 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
92174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92177  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92178  */
92179 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK)
92180 
92181 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
92182 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
92183 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
92184  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92185  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92186  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92187  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92188  */
92189 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK)
92190 
92191 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
92192 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
92193 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
92194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92197  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92198  */
92199 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK)
92200 
92201 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
92202 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
92203 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
92204  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92205  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92206  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92207  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92208  */
92209 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK)
92210 
92211 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
92212 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
92213 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
92214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92217  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92218  */
92219 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK)
92220 
92221 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
92222 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
92223 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
92224  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92225  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92226  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92227  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92228  */
92229 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK)
92230 
92231 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
92232 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
92233 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
92234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92237  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92238  */
92239 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK)
92240 
92241 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
92242 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
92243 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
92244  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92245  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92246  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92247  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92248  */
92249 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK)
92250 
92251 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
92252 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
92253 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
92254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92257  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92258  */
92259 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK)
92260 
92261 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
92262 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
92263 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
92264  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92265  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92266  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92267  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92268  */
92269 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK)
92270 
92271 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
92272 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
92273 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
92274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92277  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92278  */
92279 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK)
92280 
92281 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
92282 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
92283 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
92284  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92285  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92286  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92287  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92288  */
92289 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK)
92290 
92291 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
92292 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
92293 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
92294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92297  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92298  */
92299 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK)
92300 
92301 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
92302 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
92303 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
92304  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92305  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92306  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92307  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92308  */
92309 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK)
92310 
92311 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
92312 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
92313 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
92314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92317  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92318  */
92319 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK)
92320 
92321 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
92322 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
92323 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
92324  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92325  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92326  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92327  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92328  */
92329 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK)
92330 
92331 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
92332 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
92333 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
92334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92337  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92338  */
92339 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK)
92340 
92341 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
92342 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
92343 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
92344  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92345  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92346  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92347  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92348  */
92349 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK)
92350 
92351 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
92352 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
92353 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
92354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92357  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92358  */
92359 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK)
92360 
92361 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
92362 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
92363 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
92364  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92365  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92366  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92367  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92368  */
92369 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK)
92370 
92371 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
92372 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
92373 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
92374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92377  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92378  */
92379 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK)
92380 
92381 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
92382 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
92383 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
92384  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92385  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92386  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92387  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92388  */
92389 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK)
92390 
92391 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
92392 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
92393 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
92394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92397  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92398  */
92399 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK)
92400 
92401 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
92402 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
92403 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
92404  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92405  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92406  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92407  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92408  */
92409 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK)
92410 
92411 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
92412 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
92413 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
92414  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92415  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92416  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92417  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92418  */
92419 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK)
92420 
92421 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
92422 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
92423 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
92424  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92425  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92426  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92427  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92428  */
92429 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK)
92430 
92431 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
92432 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
92433 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
92434  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92435  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92436  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92437  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92438  */
92439 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK)
92440 
92441 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
92442 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
92443 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
92444  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92445  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92446  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92447  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92448  */
92449 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK)
92450 
92451 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
92452 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
92453 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
92454  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92455  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92456  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92457  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92458  */
92459 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK)
92460 
92461 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
92462 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
92463 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
92464  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92465  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92466  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92467  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92468  */
92469 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK)
92470 /*! @} */
92471 
92472 /* The count of TRDC_MBC_DOM3_MEM1_BLK_NSE_W */
92473 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_COUNT       (2U)
92474 
92475 /* The count of TRDC_MBC_DOM3_MEM1_BLK_NSE_W */
92476 #define TRDC_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2      (1U)
92477 
92478 /*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
92479 /*! @{ */
92480 
92481 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
92482 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
92483 /*! MBACSEL0 - Memory Block Access Control Select for block B
92484  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92485  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92486  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92487  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92488  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92489  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92490  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92491  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92492  */
92493 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK)
92494 
92495 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
92496 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
92497 /*! NSE0 - NonSecure Enable for block B
92498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92501  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92502  */
92503 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK)
92504 
92505 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
92506 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
92507 /*! MBACSEL1 - Memory Block Access Control Select for block B
92508  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92509  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92510  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92511  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92512  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92513  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92514  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92515  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92516  */
92517 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK)
92518 
92519 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
92520 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
92521 /*! NSE1 - NonSecure Enable for block B
92522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92525  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92526  */
92527 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK)
92528 
92529 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
92530 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
92531 /*! MBACSEL2 - Memory Block Access Control Select for block B
92532  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92533  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92534  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92535  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92536  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92537  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92538  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92539  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92540  */
92541 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK)
92542 
92543 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
92544 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
92545 /*! NSE2 - NonSecure Enable for block B
92546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92549  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92550  */
92551 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK)
92552 
92553 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
92554 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
92555 /*! MBACSEL3 - Memory Block Access Control Select for block B
92556  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92557  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92558  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92559  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92560  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92561  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92562  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92563  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92564  */
92565 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK)
92566 
92567 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
92568 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
92569 /*! NSE3 - NonSecure Enable for block B
92570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92573  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92574  */
92575 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK)
92576 
92577 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
92578 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
92579 /*! MBACSEL4 - Memory Block Access Control Select for block B
92580  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92581  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92582  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92583  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92584  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92585  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92586  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92587  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92588  */
92589 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK)
92590 
92591 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
92592 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
92593 /*! NSE4 - NonSecure Enable for block B
92594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92597  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92598  */
92599 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK)
92600 
92601 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
92602 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
92603 /*! MBACSEL5 - Memory Block Access Control Select for block B
92604  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92605  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92606  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92607  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92608  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92609  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92610  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92611  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92612  */
92613 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK)
92614 
92615 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
92616 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
92617 /*! NSE5 - NonSecure Enable for block B
92618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92621  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92622  */
92623 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK)
92624 
92625 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
92626 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
92627 /*! MBACSEL6 - Memory Block Access Control Select for block B
92628  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92629  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92630  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92631  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92632  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92633  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92634  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92635  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92636  */
92637 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK)
92638 
92639 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
92640 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
92641 /*! NSE6 - NonSecure Enable for block B
92642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92645  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92646  */
92647 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK)
92648 
92649 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
92650 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
92651 /*! MBACSEL7 - Memory Block Access Control Select for block B
92652  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
92653  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
92654  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
92655  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
92656  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
92657  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
92658  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
92659  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
92660  */
92661 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK)
92662 
92663 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
92664 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
92665 /*! NSE7 - NonSecure Enable for block B
92666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
92667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92669  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92670  */
92671 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK)
92672 /*! @} */
92673 
92674 /* The count of TRDC_MBC_DOM3_MEM2_BLK_CFG_W */
92675 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_COUNT       (2U)
92676 
92677 /* The count of TRDC_MBC_DOM3_MEM2_BLK_CFG_W */
92678 #define TRDC_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2      (1U)
92679 
92680 /*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
92681 /*! @{ */
92682 
92683 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
92684 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
92685 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
92686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92689  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92690  */
92691 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK)
92692 
92693 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
92694 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
92695 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
92696  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92697  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92698  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92699  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92700  */
92701 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK)
92702 
92703 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
92704 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
92705 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
92706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92709  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92710  */
92711 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK)
92712 
92713 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
92714 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
92715 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
92716  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92717  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92718  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92719  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92720  */
92721 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK)
92722 
92723 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
92724 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
92725 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
92726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92729  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92730  */
92731 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK)
92732 
92733 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
92734 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
92735 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
92736  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92737  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92738  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92739  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92740  */
92741 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK)
92742 
92743 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
92744 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
92745 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
92746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92749  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92750  */
92751 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK)
92752 
92753 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
92754 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
92755 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
92756  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92757  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92758  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92759  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92760  */
92761 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK)
92762 
92763 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
92764 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
92765 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
92766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92769  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92770  */
92771 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK)
92772 
92773 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
92774 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
92775 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
92776  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92777  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92778  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92779  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92780  */
92781 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK)
92782 
92783 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
92784 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
92785 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
92786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92789  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92790  */
92791 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK)
92792 
92793 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
92794 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
92795 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
92796  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92797  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92798  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92799  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92800  */
92801 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK)
92802 
92803 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
92804 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
92805 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
92806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92809  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92810  */
92811 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK)
92812 
92813 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
92814 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
92815 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
92816  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92817  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92818  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92819  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92820  */
92821 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK)
92822 
92823 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
92824 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
92825 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
92826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92829  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92830  */
92831 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK)
92832 
92833 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
92834 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
92835 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
92836  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92837  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92838  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92839  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92840  */
92841 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK)
92842 
92843 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
92844 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
92845 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
92846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92849  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92850  */
92851 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK)
92852 
92853 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
92854 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
92855 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
92856  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92857  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92858  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92859  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92860  */
92861 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK)
92862 
92863 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
92864 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
92865 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
92866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92869  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92870  */
92871 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK)
92872 
92873 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
92874 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
92875 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
92876  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92877  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92878  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92879  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92880  */
92881 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK)
92882 
92883 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
92884 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
92885 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
92886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92889  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92890  */
92891 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK)
92892 
92893 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
92894 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
92895 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
92896  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92897  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92898  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92899  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92900  */
92901 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK)
92902 
92903 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
92904 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
92905 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
92906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92909  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92910  */
92911 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK)
92912 
92913 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
92914 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
92915 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
92916  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92917  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92918  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92919  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92920  */
92921 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK)
92922 
92923 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
92924 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
92925 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
92926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92929  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92930  */
92931 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK)
92932 
92933 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
92934 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
92935 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
92936  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92937  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92938  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92939  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92940  */
92941 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK)
92942 
92943 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
92944 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
92945 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
92946  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92947  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92948  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92949  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92950  */
92951 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK)
92952 
92953 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
92954 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
92955 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
92956  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92957  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92958  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92959  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92960  */
92961 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK)
92962 
92963 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
92964 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
92965 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
92966  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92967  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92968  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92969  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92970  */
92971 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK)
92972 
92973 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
92974 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
92975 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
92976  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92977  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92978  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92979  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92980  */
92981 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK)
92982 
92983 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
92984 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
92985 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
92986  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92987  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92988  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92989  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
92990  */
92991 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK)
92992 
92993 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
92994 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
92995 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
92996  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
92997  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
92998  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
92999  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93000  */
93001 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK)
93002 /*! @} */
93003 
93004 /* The count of TRDC_MBC_DOM3_MEM2_BLK_NSE_W */
93005 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_COUNT       (2U)
93006 
93007 /* The count of TRDC_MBC_DOM3_MEM2_BLK_NSE_W */
93008 #define TRDC_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2      (1U)
93009 
93010 /*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
93011 /*! @{ */
93012 
93013 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
93014 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
93015 /*! MBACSEL0 - Memory Block Access Control Select for block B
93016  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93017  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93018  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93019  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93020  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93021  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93022  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93023  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93024  */
93025 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK)
93026 
93027 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
93028 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
93029 /*! NSE0 - NonSecure Enable for block B
93030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93033  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93034  */
93035 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK)
93036 
93037 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
93038 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
93039 /*! MBACSEL1 - Memory Block Access Control Select for block B
93040  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93041  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93042  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93043  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93044  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93045  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93046  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93047  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93048  */
93049 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK)
93050 
93051 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
93052 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
93053 /*! NSE1 - NonSecure Enable for block B
93054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93057  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93058  */
93059 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK)
93060 
93061 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
93062 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
93063 /*! MBACSEL2 - Memory Block Access Control Select for block B
93064  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93065  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93066  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93067  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93068  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93069  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93070  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93071  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93072  */
93073 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK)
93074 
93075 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
93076 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
93077 /*! NSE2 - NonSecure Enable for block B
93078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93081  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93082  */
93083 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK)
93084 
93085 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
93086 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
93087 /*! MBACSEL3 - Memory Block Access Control Select for block B
93088  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93089  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93090  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93091  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93092  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93093  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93094  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93095  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93096  */
93097 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK)
93098 
93099 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
93100 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
93101 /*! NSE3 - NonSecure Enable for block B
93102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93105  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93106  */
93107 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK)
93108 
93109 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
93110 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
93111 /*! MBACSEL4 - Memory Block Access Control Select for block B
93112  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93113  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93114  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93115  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93116  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93117  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93118  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93119  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93120  */
93121 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK)
93122 
93123 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
93124 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
93125 /*! NSE4 - NonSecure Enable for block B
93126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93129  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93130  */
93131 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK)
93132 
93133 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
93134 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
93135 /*! MBACSEL5 - Memory Block Access Control Select for block B
93136  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93137  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93138  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93139  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93140  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93141  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93142  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93143  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93144  */
93145 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK)
93146 
93147 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
93148 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
93149 /*! NSE5 - NonSecure Enable for block B
93150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93153  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93154  */
93155 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK)
93156 
93157 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
93158 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
93159 /*! MBACSEL6 - Memory Block Access Control Select for block B
93160  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93161  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93162  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93163  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93164  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93165  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93166  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93167  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93168  */
93169 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK)
93170 
93171 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
93172 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
93173 /*! NSE6 - NonSecure Enable for block B
93174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93177  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93178  */
93179 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK)
93180 
93181 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
93182 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
93183 /*! MBACSEL7 - Memory Block Access Control Select for block B
93184  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93185  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93186  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93187  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93188  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93189  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93190  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93191  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93192  */
93193 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK)
93194 
93195 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
93196 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
93197 /*! NSE7 - NonSecure Enable for block B
93198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93201  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93202  */
93203 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK)
93204 /*! @} */
93205 
93206 /* The count of TRDC_MBC_DOM3_MEM3_BLK_CFG_W */
93207 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_COUNT       (2U)
93208 
93209 /* The count of TRDC_MBC_DOM3_MEM3_BLK_CFG_W */
93210 #define TRDC_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2      (3U)
93211 
93212 /*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
93213 /*! @{ */
93214 
93215 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
93216 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
93217 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
93218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93221  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93222  */
93223 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK)
93224 
93225 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
93226 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
93227 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
93228  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93229  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93230  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93231  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93232  */
93233 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK)
93234 
93235 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
93236 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
93237 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
93238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93241  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93242  */
93243 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK)
93244 
93245 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
93246 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
93247 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
93248  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93249  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93250  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93251  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93252  */
93253 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK)
93254 
93255 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
93256 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
93257 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
93258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93261  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93262  */
93263 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK)
93264 
93265 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
93266 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
93267 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
93268  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93269  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93270  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93271  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93272  */
93273 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK)
93274 
93275 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
93276 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
93277 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
93278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93281  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93282  */
93283 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK)
93284 
93285 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
93286 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
93287 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
93288  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93289  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93290  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93291  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93292  */
93293 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK)
93294 
93295 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
93296 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
93297 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
93298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93301  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93302  */
93303 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK)
93304 
93305 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
93306 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
93307 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
93308  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93309  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93310  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93311  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93312  */
93313 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK)
93314 
93315 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
93316 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
93317 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
93318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93321  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93322  */
93323 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK)
93324 
93325 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
93326 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
93327 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
93328  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93329  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93330  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93331  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93332  */
93333 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK)
93334 
93335 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
93336 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
93337 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
93338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93341  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93342  */
93343 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK)
93344 
93345 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
93346 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
93347 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
93348  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93349  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93350  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93351  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93352  */
93353 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK)
93354 
93355 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
93356 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
93357 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
93358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93361  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93362  */
93363 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK)
93364 
93365 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
93366 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
93367 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
93368  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93369  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93370  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93371  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93372  */
93373 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK)
93374 
93375 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
93376 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
93377 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
93378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93381  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93382  */
93383 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK)
93384 
93385 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
93386 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
93387 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
93388  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93389  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93390  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93391  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93392  */
93393 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK)
93394 
93395 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
93396 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
93397 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
93398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93401  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93402  */
93403 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK)
93404 
93405 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
93406 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
93407 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
93408  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93409  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93410  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93411  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93412  */
93413 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK)
93414 
93415 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
93416 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
93417 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
93418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93421  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93422  */
93423 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK)
93424 
93425 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
93426 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
93427 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
93428  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93429  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93430  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93431  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93432  */
93433 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK)
93434 
93435 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
93436 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
93437 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
93438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93441  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93442  */
93443 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK)
93444 
93445 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
93446 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
93447 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
93448  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93449  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93450  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93451  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93452  */
93453 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK)
93454 
93455 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
93456 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
93457 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
93458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93461  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93462  */
93463 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK)
93464 
93465 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
93466 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
93467 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
93468  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93469  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93470  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93471  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93472  */
93473 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK)
93474 
93475 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
93476 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
93477 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
93478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93481  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93482  */
93483 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK)
93484 
93485 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
93486 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
93487 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
93488  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93489  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93490  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93491  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93492  */
93493 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK)
93494 
93495 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
93496 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
93497 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
93498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93501  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93502  */
93503 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK)
93504 
93505 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
93506 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
93507 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
93508  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93509  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93510  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93511  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93512  */
93513 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK)
93514 
93515 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
93516 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
93517 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
93518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93521  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93522  */
93523 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK)
93524 
93525 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
93526 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
93527 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
93528  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93529  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93530  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93531  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93532  */
93533 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK)
93534 /*! @} */
93535 
93536 /* The count of TRDC_MBC_DOM3_MEM3_BLK_NSE_W */
93537 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_COUNT       (2U)
93538 
93539 /* The count of TRDC_MBC_DOM3_MEM3_BLK_NSE_W */
93540 #define TRDC_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2      (1U)
93541 
93542 /*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
93543 /*! @{ */
93544 
93545 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
93546 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
93547 /*! MBACSEL0 - Memory Block Access Control Select for block B
93548  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93549  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93550  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93551  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93552  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93553  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93554  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93555  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93556  */
93557 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK)
93558 
93559 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
93560 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
93561 /*! NSE0 - NonSecure Enable for block B
93562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93565  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93566  */
93567 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK)
93568 
93569 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
93570 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
93571 /*! MBACSEL1 - Memory Block Access Control Select for block B
93572  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93573  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93574  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93575  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93576  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93577  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93578  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93579  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93580  */
93581 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK)
93582 
93583 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
93584 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
93585 /*! NSE1 - NonSecure Enable for block B
93586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93589  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93590  */
93591 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK)
93592 
93593 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
93594 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
93595 /*! MBACSEL2 - Memory Block Access Control Select for block B
93596  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93597  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93598  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93599  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93600  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93601  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93602  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93603  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93604  */
93605 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK)
93606 
93607 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
93608 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
93609 /*! NSE2 - NonSecure Enable for block B
93610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93613  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93614  */
93615 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK)
93616 
93617 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
93618 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
93619 /*! MBACSEL3 - Memory Block Access Control Select for block B
93620  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93621  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93622  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93623  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93624  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93625  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93626  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93627  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93628  */
93629 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK)
93630 
93631 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
93632 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
93633 /*! NSE3 - NonSecure Enable for block B
93634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93637  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93638  */
93639 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK)
93640 
93641 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
93642 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
93643 /*! MBACSEL4 - Memory Block Access Control Select for block B
93644  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93645  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93646  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93647  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93648  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93649  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93650  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93651  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93652  */
93653 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK)
93654 
93655 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
93656 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
93657 /*! NSE4 - NonSecure Enable for block B
93658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93661  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93662  */
93663 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK)
93664 
93665 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
93666 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
93667 /*! MBACSEL5 - Memory Block Access Control Select for block B
93668  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93669  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93670  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93671  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93672  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93673  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93674  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93675  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93676  */
93677 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK)
93678 
93679 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
93680 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
93681 /*! NSE5 - NonSecure Enable for block B
93682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93685  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93686  */
93687 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK)
93688 
93689 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
93690 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
93691 /*! MBACSEL6 - Memory Block Access Control Select for block B
93692  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93693  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93694  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93695  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93696  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93697  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93698  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93699  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93700  */
93701 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK)
93702 
93703 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
93704 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
93705 /*! NSE6 - NonSecure Enable for block B
93706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93709  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93710  */
93711 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK)
93712 
93713 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
93714 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
93715 /*! MBACSEL7 - Memory Block Access Control Select for block B
93716  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
93717  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
93718  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
93719  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
93720  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
93721  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
93722  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
93723  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
93724  */
93725 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK)
93726 
93727 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
93728 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
93729 /*! NSE7 - NonSecure Enable for block B
93730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
93731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93733  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93734  */
93735 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK)
93736 /*! @} */
93737 
93738 /* The count of TRDC_MBC_DOM4_MEM0_BLK_CFG_W */
93739 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_COUNT       (2U)
93740 
93741 /* The count of TRDC_MBC_DOM4_MEM0_BLK_CFG_W */
93742 #define TRDC_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2      (16U)
93743 
93744 /*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
93745 /*! @{ */
93746 
93747 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
93748 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
93749 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
93750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93753  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93754  */
93755 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK)
93756 
93757 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
93758 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
93759 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
93760  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93761  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93762  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93763  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93764  */
93765 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK)
93766 
93767 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
93768 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
93769 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
93770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93774  */
93775 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK)
93776 
93777 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
93778 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
93779 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
93780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93784  */
93785 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK)
93786 
93787 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
93788 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
93789 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
93790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93794  */
93795 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK)
93796 
93797 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
93798 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
93799 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
93800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93804  */
93805 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK)
93806 
93807 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
93808 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
93809 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
93810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93814  */
93815 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK)
93816 
93817 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
93818 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
93819 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
93820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93824  */
93825 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK)
93826 
93827 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
93828 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
93829 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
93830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93834  */
93835 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK)
93836 
93837 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
93838 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
93839 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
93840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93844  */
93845 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK)
93846 
93847 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
93848 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
93849 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
93850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93854  */
93855 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK)
93856 
93857 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
93858 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
93859 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
93860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93864  */
93865 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK)
93866 
93867 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
93868 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
93869 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
93870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93874  */
93875 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK)
93876 
93877 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
93878 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
93879 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
93880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93884  */
93885 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK)
93886 
93887 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
93888 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
93889 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
93890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93894  */
93895 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK)
93896 
93897 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
93898 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
93899 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
93900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93904  */
93905 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK)
93906 
93907 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
93908 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
93909 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
93910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93914  */
93915 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK)
93916 
93917 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
93918 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
93919 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
93920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93924  */
93925 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK)
93926 
93927 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
93928 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
93929 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
93930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93934  */
93935 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK)
93936 
93937 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
93938 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
93939 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
93940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93944  */
93945 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK)
93946 
93947 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
93948 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
93949 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
93950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93954  */
93955 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK)
93956 
93957 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
93958 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
93959 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
93960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93964  */
93965 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK)
93966 
93967 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
93968 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
93969 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
93970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93974  */
93975 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK)
93976 
93977 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
93978 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
93979 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
93980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93984  */
93985 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK)
93986 
93987 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
93988 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
93989 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
93990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
93991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
93992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
93993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
93994  */
93995 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK)
93996 
93997 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
93998 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
93999 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
94000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94004  */
94005 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK)
94006 
94007 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
94008 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
94009 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
94010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94013  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94014  */
94015 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK)
94016 
94017 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
94018 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
94019 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
94020  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94021  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94022  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94023  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94024  */
94025 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK)
94026 
94027 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
94028 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
94029 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
94030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94033  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94034  */
94035 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK)
94036 
94037 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
94038 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
94039 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
94040  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94041  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94042  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94043  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94044  */
94045 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK)
94046 
94047 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
94048 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
94049 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
94050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94053  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94054  */
94055 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK)
94056 
94057 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
94058 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
94059 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
94060  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94061  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94062  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94063  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94064  */
94065 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK)
94066 /*! @} */
94067 
94068 /* The count of TRDC_MBC_DOM4_MEM0_BLK_NSE_W */
94069 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_COUNT       (2U)
94070 
94071 /* The count of TRDC_MBC_DOM4_MEM0_BLK_NSE_W */
94072 #define TRDC_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2      (4U)
94073 
94074 /*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
94075 /*! @{ */
94076 
94077 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
94078 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
94079 /*! MBACSEL0 - Memory Block Access Control Select for block B
94080  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94081  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94082  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94083  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94084  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94085  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94086  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94087  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94088  */
94089 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK)
94090 
94091 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
94092 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
94093 /*! NSE0 - NonSecure Enable for block B
94094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94097  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94098  */
94099 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK)
94100 
94101 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
94102 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
94103 /*! MBACSEL1 - Memory Block Access Control Select for block B
94104  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94105  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94106  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94107  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94108  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94109  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94110  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94111  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94112  */
94113 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK)
94114 
94115 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
94116 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
94117 /*! NSE1 - NonSecure Enable for block B
94118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94121  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94122  */
94123 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK)
94124 
94125 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
94126 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
94127 /*! MBACSEL2 - Memory Block Access Control Select for block B
94128  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94129  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94130  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94131  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94132  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94133  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94134  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94135  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94136  */
94137 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK)
94138 
94139 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
94140 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
94141 /*! NSE2 - NonSecure Enable for block B
94142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94145  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94146  */
94147 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK)
94148 
94149 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
94150 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
94151 /*! MBACSEL3 - Memory Block Access Control Select for block B
94152  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94153  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94154  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94155  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94156  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94157  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94158  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94159  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94160  */
94161 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK)
94162 
94163 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
94164 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
94165 /*! NSE3 - NonSecure Enable for block B
94166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94169  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94170  */
94171 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK)
94172 
94173 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
94174 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
94175 /*! MBACSEL4 - Memory Block Access Control Select for block B
94176  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94177  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94178  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94179  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94180  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94181  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94182  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94183  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94184  */
94185 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK)
94186 
94187 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
94188 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
94189 /*! NSE4 - NonSecure Enable for block B
94190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94193  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94194  */
94195 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK)
94196 
94197 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
94198 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
94199 /*! MBACSEL5 - Memory Block Access Control Select for block B
94200  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94201  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94202  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94203  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94204  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94205  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94206  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94207  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94208  */
94209 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK)
94210 
94211 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
94212 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
94213 /*! NSE5 - NonSecure Enable for block B
94214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94217  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94218  */
94219 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK)
94220 
94221 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
94222 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
94223 /*! MBACSEL6 - Memory Block Access Control Select for block B
94224  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94225  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94226  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94227  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94228  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94229  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94230  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94231  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94232  */
94233 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK)
94234 
94235 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
94236 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
94237 /*! NSE6 - NonSecure Enable for block B
94238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94241  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94242  */
94243 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK)
94244 
94245 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
94246 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
94247 /*! MBACSEL7 - Memory Block Access Control Select for block B
94248  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94249  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94250  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94251  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94252  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94253  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94254  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94255  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94256  */
94257 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK)
94258 
94259 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
94260 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
94261 /*! NSE7 - NonSecure Enable for block B
94262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94265  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94266  */
94267 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK)
94268 /*! @} */
94269 
94270 /* The count of TRDC_MBC_DOM4_MEM1_BLK_CFG_W */
94271 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_COUNT       (2U)
94272 
94273 /* The count of TRDC_MBC_DOM4_MEM1_BLK_CFG_W */
94274 #define TRDC_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2      (4U)
94275 
94276 /*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
94277 /*! @{ */
94278 
94279 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
94280 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
94281 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
94282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94285  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94286  */
94287 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK)
94288 
94289 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
94290 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
94291 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
94292  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94293  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94294  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94295  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94296  */
94297 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK)
94298 
94299 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
94300 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
94301 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
94302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94306  */
94307 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK)
94308 
94309 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
94310 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
94311 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
94312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94316  */
94317 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK)
94318 
94319 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
94320 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
94321 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
94322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94326  */
94327 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK)
94328 
94329 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
94330 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
94331 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
94332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94336  */
94337 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK)
94338 
94339 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
94340 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
94341 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
94342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94346  */
94347 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK)
94348 
94349 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
94350 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
94351 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
94352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94356  */
94357 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK)
94358 
94359 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
94360 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
94361 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
94362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94366  */
94367 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK)
94368 
94369 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
94370 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
94371 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
94372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94376  */
94377 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK)
94378 
94379 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
94380 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
94381 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
94382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94386  */
94387 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK)
94388 
94389 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
94390 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
94391 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
94392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94396  */
94397 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK)
94398 
94399 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
94400 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
94401 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
94402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94406  */
94407 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK)
94408 
94409 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
94410 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
94411 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
94412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94416  */
94417 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK)
94418 
94419 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
94420 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
94421 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
94422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94426  */
94427 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK)
94428 
94429 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
94430 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
94431 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
94432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94436  */
94437 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK)
94438 
94439 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
94440 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
94441 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
94442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94446  */
94447 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK)
94448 
94449 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
94450 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
94451 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
94452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94456  */
94457 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK)
94458 
94459 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
94460 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
94461 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
94462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94466  */
94467 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK)
94468 
94469 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
94470 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
94471 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
94472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94476  */
94477 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK)
94478 
94479 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
94480 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
94481 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
94482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94486  */
94487 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK)
94488 
94489 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
94490 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
94491 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
94492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94496  */
94497 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK)
94498 
94499 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
94500 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
94501 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
94502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94506  */
94507 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK)
94508 
94509 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
94510 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
94511 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
94512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94516  */
94517 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK)
94518 
94519 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
94520 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
94521 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
94522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94526  */
94527 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK)
94528 
94529 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
94530 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
94531 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
94532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94536  */
94537 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK)
94538 
94539 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
94540 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
94541 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
94542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94545  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94546  */
94547 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK)
94548 
94549 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
94550 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
94551 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
94552  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94553  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94554  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94555  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94556  */
94557 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK)
94558 
94559 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
94560 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
94561 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
94562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94565  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94566  */
94567 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK)
94568 
94569 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
94570 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
94571 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
94572  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94573  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94574  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94575  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94576  */
94577 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK)
94578 
94579 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
94580 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
94581 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
94582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94585  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94586  */
94587 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK)
94588 
94589 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
94590 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
94591 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
94592  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94593  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94594  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94595  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94596  */
94597 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK)
94598 /*! @} */
94599 
94600 /* The count of TRDC_MBC_DOM4_MEM1_BLK_NSE_W */
94601 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_COUNT       (2U)
94602 
94603 /* The count of TRDC_MBC_DOM4_MEM1_BLK_NSE_W */
94604 #define TRDC_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2      (1U)
94605 
94606 /*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
94607 /*! @{ */
94608 
94609 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
94610 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
94611 /*! MBACSEL0 - Memory Block Access Control Select for block B
94612  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94613  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94614  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94615  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94616  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94617  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94618  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94619  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94620  */
94621 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK)
94622 
94623 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
94624 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
94625 /*! NSE0 - NonSecure Enable for block B
94626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94629  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94630  */
94631 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK)
94632 
94633 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
94634 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
94635 /*! MBACSEL1 - Memory Block Access Control Select for block B
94636  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94637  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94638  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94639  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94640  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94641  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94642  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94643  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94644  */
94645 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK)
94646 
94647 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
94648 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
94649 /*! NSE1 - NonSecure Enable for block B
94650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94653  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94654  */
94655 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK)
94656 
94657 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
94658 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
94659 /*! MBACSEL2 - Memory Block Access Control Select for block B
94660  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94661  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94662  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94663  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94664  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94665  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94666  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94667  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94668  */
94669 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK)
94670 
94671 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
94672 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
94673 /*! NSE2 - NonSecure Enable for block B
94674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94677  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94678  */
94679 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK)
94680 
94681 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
94682 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
94683 /*! MBACSEL3 - Memory Block Access Control Select for block B
94684  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94685  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94686  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94687  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94688  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94689  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94690  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94691  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94692  */
94693 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK)
94694 
94695 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
94696 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
94697 /*! NSE3 - NonSecure Enable for block B
94698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94701  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94702  */
94703 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK)
94704 
94705 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
94706 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
94707 /*! MBACSEL4 - Memory Block Access Control Select for block B
94708  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94709  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94710  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94711  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94712  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94713  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94714  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94715  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94716  */
94717 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK)
94718 
94719 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
94720 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
94721 /*! NSE4 - NonSecure Enable for block B
94722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94725  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94726  */
94727 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK)
94728 
94729 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
94730 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
94731 /*! MBACSEL5 - Memory Block Access Control Select for block B
94732  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94733  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94734  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94735  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94736  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94737  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94738  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94739  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94740  */
94741 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK)
94742 
94743 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
94744 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
94745 /*! NSE5 - NonSecure Enable for block B
94746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94749  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94750  */
94751 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK)
94752 
94753 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
94754 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
94755 /*! MBACSEL6 - Memory Block Access Control Select for block B
94756  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94757  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94758  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94759  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94760  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94761  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94762  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94763  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94764  */
94765 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK)
94766 
94767 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
94768 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
94769 /*! NSE6 - NonSecure Enable for block B
94770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94773  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94774  */
94775 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK)
94776 
94777 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
94778 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
94779 /*! MBACSEL7 - Memory Block Access Control Select for block B
94780  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
94781  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
94782  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
94783  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
94784  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
94785  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
94786  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
94787  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
94788  */
94789 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK)
94790 
94791 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
94792 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
94793 /*! NSE7 - NonSecure Enable for block B
94794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
94795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94797  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94798  */
94799 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK)
94800 /*! @} */
94801 
94802 /* The count of TRDC_MBC_DOM4_MEM2_BLK_CFG_W */
94803 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_COUNT       (2U)
94804 
94805 /* The count of TRDC_MBC_DOM4_MEM2_BLK_CFG_W */
94806 #define TRDC_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2      (1U)
94807 
94808 /*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
94809 /*! @{ */
94810 
94811 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
94812 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
94813 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
94814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94817  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94818  */
94819 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK)
94820 
94821 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
94822 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
94823 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
94824  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94825  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94826  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94827  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94828  */
94829 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK)
94830 
94831 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
94832 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
94833 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
94834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94838  */
94839 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK)
94840 
94841 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
94842 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
94843 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
94844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94848  */
94849 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK)
94850 
94851 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
94852 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
94853 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
94854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94858  */
94859 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK)
94860 
94861 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
94862 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
94863 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
94864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94868  */
94869 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK)
94870 
94871 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
94872 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
94873 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
94874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94878  */
94879 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK)
94880 
94881 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
94882 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
94883 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
94884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94888  */
94889 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK)
94890 
94891 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
94892 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
94893 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
94894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94898  */
94899 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK)
94900 
94901 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
94902 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
94903 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
94904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94908  */
94909 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK)
94910 
94911 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
94912 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
94913 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
94914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94918  */
94919 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK)
94920 
94921 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
94922 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
94923 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
94924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94928  */
94929 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK)
94930 
94931 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
94932 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
94933 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
94934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94938  */
94939 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK)
94940 
94941 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
94942 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
94943 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
94944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94948  */
94949 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK)
94950 
94951 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
94952 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
94953 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
94954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94958  */
94959 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK)
94960 
94961 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
94962 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
94963 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
94964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94968  */
94969 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK)
94970 
94971 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
94972 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
94973 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
94974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94978  */
94979 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK)
94980 
94981 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
94982 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
94983 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
94984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94988  */
94989 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK)
94990 
94991 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
94992 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
94993 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
94994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
94995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
94996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
94997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
94998  */
94999 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK)
95000 
95001 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
95002 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
95003 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
95004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95008  */
95009 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK)
95010 
95011 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
95012 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
95013 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
95014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95018  */
95019 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK)
95020 
95021 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
95022 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
95023 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
95024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95028  */
95029 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK)
95030 
95031 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
95032 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
95033 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
95034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95038  */
95039 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK)
95040 
95041 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
95042 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
95043 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
95044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95048  */
95049 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK)
95050 
95051 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
95052 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
95053 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
95054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95058  */
95059 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK)
95060 
95061 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
95062 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
95063 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
95064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95068  */
95069 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK)
95070 
95071 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
95072 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
95073 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
95074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95077  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95078  */
95079 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK)
95080 
95081 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
95082 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
95083 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
95084  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95085  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95086  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95087  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95088  */
95089 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK)
95090 
95091 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
95092 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
95093 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
95094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95097  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95098  */
95099 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK)
95100 
95101 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
95102 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
95103 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
95104  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95105  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95106  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95107  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95108  */
95109 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK)
95110 
95111 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
95112 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
95113 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
95114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95117  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95118  */
95119 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK)
95120 
95121 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
95122 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
95123 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
95124  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95125  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95126  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95127  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95128  */
95129 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK)
95130 /*! @} */
95131 
95132 /* The count of TRDC_MBC_DOM4_MEM2_BLK_NSE_W */
95133 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_COUNT       (2U)
95134 
95135 /* The count of TRDC_MBC_DOM4_MEM2_BLK_NSE_W */
95136 #define TRDC_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2      (1U)
95137 
95138 /*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
95139 /*! @{ */
95140 
95141 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
95142 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
95143 /*! MBACSEL0 - Memory Block Access Control Select for block B
95144  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95145  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95146  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95147  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95148  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95149  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95150  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95151  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95152  */
95153 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK)
95154 
95155 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
95156 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
95157 /*! NSE0 - NonSecure Enable for block B
95158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95161  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95162  */
95163 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK)
95164 
95165 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
95166 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
95167 /*! MBACSEL1 - Memory Block Access Control Select for block B
95168  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95169  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95170  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95171  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95172  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95173  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95174  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95175  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95176  */
95177 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK)
95178 
95179 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
95180 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
95181 /*! NSE1 - NonSecure Enable for block B
95182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95185  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95186  */
95187 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK)
95188 
95189 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
95190 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
95191 /*! MBACSEL2 - Memory Block Access Control Select for block B
95192  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95193  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95194  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95195  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95196  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95197  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95198  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95199  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95200  */
95201 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK)
95202 
95203 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
95204 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
95205 /*! NSE2 - NonSecure Enable for block B
95206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95209  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95210  */
95211 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK)
95212 
95213 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
95214 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
95215 /*! MBACSEL3 - Memory Block Access Control Select for block B
95216  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95217  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95218  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95219  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95220  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95221  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95222  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95223  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95224  */
95225 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK)
95226 
95227 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
95228 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
95229 /*! NSE3 - NonSecure Enable for block B
95230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95233  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95234  */
95235 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK)
95236 
95237 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
95238 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
95239 /*! MBACSEL4 - Memory Block Access Control Select for block B
95240  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95241  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95242  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95243  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95244  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95245  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95246  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95247  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95248  */
95249 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK)
95250 
95251 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
95252 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
95253 /*! NSE4 - NonSecure Enable for block B
95254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95257  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95258  */
95259 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK)
95260 
95261 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
95262 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
95263 /*! MBACSEL5 - Memory Block Access Control Select for block B
95264  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95265  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95266  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95267  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95268  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95269  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95270  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95271  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95272  */
95273 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK)
95274 
95275 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
95276 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
95277 /*! NSE5 - NonSecure Enable for block B
95278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95281  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95282  */
95283 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK)
95284 
95285 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
95286 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
95287 /*! MBACSEL6 - Memory Block Access Control Select for block B
95288  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95289  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95290  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95291  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95292  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95293  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95294  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95295  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95296  */
95297 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK)
95298 
95299 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
95300 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
95301 /*! NSE6 - NonSecure Enable for block B
95302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95305  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95306  */
95307 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK)
95308 
95309 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
95310 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
95311 /*! MBACSEL7 - Memory Block Access Control Select for block B
95312  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95313  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95314  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95315  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95316  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95317  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95318  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95319  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95320  */
95321 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK)
95322 
95323 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
95324 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
95325 /*! NSE7 - NonSecure Enable for block B
95326  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95327  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95328  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95329  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95330  */
95331 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK)
95332 /*! @} */
95333 
95334 /* The count of TRDC_MBC_DOM4_MEM3_BLK_CFG_W */
95335 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_COUNT       (2U)
95336 
95337 /* The count of TRDC_MBC_DOM4_MEM3_BLK_CFG_W */
95338 #define TRDC_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2      (3U)
95339 
95340 /*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
95341 /*! @{ */
95342 
95343 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
95344 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
95345 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
95346  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95347  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95348  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95349  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95350  */
95351 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK)
95352 
95353 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
95354 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
95355 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
95356  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95357  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95358  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95359  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95360  */
95361 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK)
95362 
95363 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
95364 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
95365 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
95366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95369  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95370  */
95371 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK)
95372 
95373 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
95374 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
95375 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
95376  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95377  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95378  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95379  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95380  */
95381 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK)
95382 
95383 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
95384 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
95385 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
95386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95389  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95390  */
95391 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK)
95392 
95393 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
95394 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
95395 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
95396  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95397  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95398  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95399  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95400  */
95401 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK)
95402 
95403 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
95404 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
95405 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
95406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95409  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95410  */
95411 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK)
95412 
95413 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
95414 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
95415 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
95416  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95417  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95418  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95419  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95420  */
95421 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK)
95422 
95423 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
95424 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
95425 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
95426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95429  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95430  */
95431 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK)
95432 
95433 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
95434 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
95435 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
95436  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95437  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95438  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95439  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95440  */
95441 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK)
95442 
95443 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
95444 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
95445 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
95446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95449  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95450  */
95451 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK)
95452 
95453 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
95454 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
95455 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
95456  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95457  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95458  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95459  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95460  */
95461 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK)
95462 
95463 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
95464 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
95465 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
95466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95469  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95470  */
95471 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK)
95472 
95473 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
95474 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
95475 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
95476  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95477  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95478  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95479  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95480  */
95481 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK)
95482 
95483 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
95484 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
95485 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
95486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95489  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95490  */
95491 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK)
95492 
95493 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
95494 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
95495 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
95496  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95497  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95498  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95499  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95500  */
95501 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK)
95502 
95503 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
95504 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
95505 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
95506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95509  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95510  */
95511 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK)
95512 
95513 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
95514 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
95515 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
95516  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95517  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95518  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95519  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95520  */
95521 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK)
95522 
95523 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
95524 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
95525 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
95526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95529  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95530  */
95531 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK)
95532 
95533 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
95534 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
95535 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
95536  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95537  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95538  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95539  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95540  */
95541 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK)
95542 
95543 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
95544 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
95545 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
95546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95549  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95550  */
95551 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK)
95552 
95553 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
95554 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
95555 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
95556  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95557  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95558  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95559  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95560  */
95561 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK)
95562 
95563 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
95564 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
95565 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
95566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95569  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95570  */
95571 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK)
95572 
95573 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
95574 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
95575 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
95576  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95577  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95578  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95579  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95580  */
95581 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK)
95582 
95583 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
95584 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
95585 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
95586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95589  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95590  */
95591 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK)
95592 
95593 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
95594 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
95595 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
95596  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95597  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95598  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95599  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95600  */
95601 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK)
95602 
95603 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
95604 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
95605 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
95606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95609  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95610  */
95611 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK)
95612 
95613 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
95614 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
95615 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
95616  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95617  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95618  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95619  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95620  */
95621 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK)
95622 
95623 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
95624 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
95625 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
95626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95629  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95630  */
95631 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK)
95632 
95633 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
95634 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
95635 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
95636  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95637  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95638  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95639  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95640  */
95641 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK)
95642 
95643 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
95644 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
95645 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
95646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95649  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95650  */
95651 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK)
95652 
95653 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
95654 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
95655 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
95656  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95657  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95658  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95659  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95660  */
95661 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK)
95662 /*! @} */
95663 
95664 /* The count of TRDC_MBC_DOM4_MEM3_BLK_NSE_W */
95665 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_COUNT       (2U)
95666 
95667 /* The count of TRDC_MBC_DOM4_MEM3_BLK_NSE_W */
95668 #define TRDC_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2      (1U)
95669 
95670 /*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
95671 /*! @{ */
95672 
95673 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
95674 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
95675 /*! MBACSEL0 - Memory Block Access Control Select for block B
95676  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95677  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95678  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95679  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95680  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95681  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95682  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95683  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95684  */
95685 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK)
95686 
95687 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
95688 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
95689 /*! NSE0 - NonSecure Enable for block B
95690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95693  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95694  */
95695 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK)
95696 
95697 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
95698 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
95699 /*! MBACSEL1 - Memory Block Access Control Select for block B
95700  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95701  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95702  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95703  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95704  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95705  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95706  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95707  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95708  */
95709 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK)
95710 
95711 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
95712 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
95713 /*! NSE1 - NonSecure Enable for block B
95714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95717  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95718  */
95719 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK)
95720 
95721 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
95722 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
95723 /*! MBACSEL2 - Memory Block Access Control Select for block B
95724  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95725  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95726  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95727  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95728  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95729  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95730  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95731  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95732  */
95733 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK)
95734 
95735 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
95736 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
95737 /*! NSE2 - NonSecure Enable for block B
95738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95741  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95742  */
95743 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK)
95744 
95745 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
95746 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
95747 /*! MBACSEL3 - Memory Block Access Control Select for block B
95748  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95749  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95750  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95751  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95752  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95753  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95754  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95755  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95756  */
95757 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK)
95758 
95759 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
95760 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
95761 /*! NSE3 - NonSecure Enable for block B
95762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95765  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95766  */
95767 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK)
95768 
95769 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
95770 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
95771 /*! MBACSEL4 - Memory Block Access Control Select for block B
95772  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95773  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95774  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95775  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95776  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95777  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95778  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95779  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95780  */
95781 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK)
95782 
95783 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
95784 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
95785 /*! NSE4 - NonSecure Enable for block B
95786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95789  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95790  */
95791 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK)
95792 
95793 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
95794 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
95795 /*! MBACSEL5 - Memory Block Access Control Select for block B
95796  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95797  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95798  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95799  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95800  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95801  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95802  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95803  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95804  */
95805 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK)
95806 
95807 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
95808 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
95809 /*! NSE5 - NonSecure Enable for block B
95810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95813  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95814  */
95815 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK)
95816 
95817 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
95818 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
95819 /*! MBACSEL6 - Memory Block Access Control Select for block B
95820  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95821  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95822  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95823  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95824  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95825  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95826  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95827  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95828  */
95829 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK)
95830 
95831 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
95832 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
95833 /*! NSE6 - NonSecure Enable for block B
95834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95837  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95838  */
95839 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK)
95840 
95841 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
95842 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
95843 /*! MBACSEL7 - Memory Block Access Control Select for block B
95844  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
95845  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
95846  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
95847  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
95848  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
95849  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
95850  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
95851  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
95852  */
95853 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK)
95854 
95855 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
95856 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
95857 /*! NSE7 - NonSecure Enable for block B
95858  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
95859  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95860  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95861  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95862  */
95863 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK)
95864 /*! @} */
95865 
95866 /* The count of TRDC_MBC_DOM5_MEM0_BLK_CFG_W */
95867 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_COUNT       (2U)
95868 
95869 /* The count of TRDC_MBC_DOM5_MEM0_BLK_CFG_W */
95870 #define TRDC_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2      (16U)
95871 
95872 /*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
95873 /*! @{ */
95874 
95875 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
95876 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
95877 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
95878  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95879  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95880  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95881  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95882  */
95883 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK)
95884 
95885 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
95886 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
95887 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
95888  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95889  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95890  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95891  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95892  */
95893 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK)
95894 
95895 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
95896 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
95897 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
95898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95901  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95902  */
95903 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK)
95904 
95905 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
95906 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
95907 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
95908  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95909  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95910  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95911  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95912  */
95913 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK)
95914 
95915 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
95916 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
95917 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
95918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95921  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95922  */
95923 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK)
95924 
95925 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
95926 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
95927 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
95928  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95929  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95930  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95931  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95932  */
95933 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK)
95934 
95935 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
95936 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
95937 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
95938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95941  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95942  */
95943 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK)
95944 
95945 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
95946 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
95947 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
95948  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95949  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95950  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95951  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95952  */
95953 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK)
95954 
95955 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
95956 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
95957 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
95958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95961  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95962  */
95963 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK)
95964 
95965 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
95966 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
95967 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
95968  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95969  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95970  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95971  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95972  */
95973 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK)
95974 
95975 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
95976 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
95977 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
95978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95981  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95982  */
95983 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK)
95984 
95985 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
95986 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
95987 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
95988  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95989  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
95990  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
95991  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
95992  */
95993 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK)
95994 
95995 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
95996 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
95997 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
95998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
95999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96001  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96002  */
96003 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK)
96004 
96005 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
96006 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
96007 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
96008  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96009  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96010  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96011  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96012  */
96013 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK)
96014 
96015 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
96016 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
96017 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
96018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96021  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96022  */
96023 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK)
96024 
96025 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
96026 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
96027 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
96028  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96029  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96030  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96031  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96032  */
96033 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK)
96034 
96035 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
96036 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
96037 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
96038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96041  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96042  */
96043 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK)
96044 
96045 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
96046 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
96047 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
96048  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96049  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96050  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96051  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96052  */
96053 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK)
96054 
96055 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
96056 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
96057 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
96058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96061  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96062  */
96063 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK)
96064 
96065 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
96066 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
96067 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
96068  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96069  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96070  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96071  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96072  */
96073 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK)
96074 
96075 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
96076 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
96077 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
96078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96081  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96082  */
96083 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK)
96084 
96085 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
96086 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
96087 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
96088  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96089  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96090  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96091  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96092  */
96093 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK)
96094 
96095 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
96096 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
96097 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
96098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96101  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96102  */
96103 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK)
96104 
96105 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
96106 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
96107 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
96108  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96109  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96110  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96111  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96112  */
96113 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK)
96114 
96115 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
96116 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
96117 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
96118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96121  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96122  */
96123 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK)
96124 
96125 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
96126 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
96127 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
96128  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96129  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96130  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96131  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96132  */
96133 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK)
96134 
96135 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
96136 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
96137 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
96138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96141  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96142  */
96143 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK)
96144 
96145 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
96146 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
96147 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
96148  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96149  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96150  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96151  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96152  */
96153 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK)
96154 
96155 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
96156 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
96157 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
96158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96161  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96162  */
96163 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK)
96164 
96165 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
96166 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
96167 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
96168  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96169  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96170  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96171  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96172  */
96173 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK)
96174 
96175 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
96176 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
96177 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
96178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96181  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96182  */
96183 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK)
96184 
96185 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
96186 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
96187 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
96188  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96189  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96190  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96191  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96192  */
96193 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK)
96194 /*! @} */
96195 
96196 /* The count of TRDC_MBC_DOM5_MEM0_BLK_NSE_W */
96197 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_COUNT       (2U)
96198 
96199 /* The count of TRDC_MBC_DOM5_MEM0_BLK_NSE_W */
96200 #define TRDC_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2      (4U)
96201 
96202 /*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
96203 /*! @{ */
96204 
96205 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
96206 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
96207 /*! MBACSEL0 - Memory Block Access Control Select for block B
96208  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96209  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96210  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96211  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96212  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96213  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96214  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96215  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96216  */
96217 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK)
96218 
96219 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
96220 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
96221 /*! NSE0 - NonSecure Enable for block B
96222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96225  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96226  */
96227 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK)
96228 
96229 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
96230 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
96231 /*! MBACSEL1 - Memory Block Access Control Select for block B
96232  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96233  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96234  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96235  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96236  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96237  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96238  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96239  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96240  */
96241 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK)
96242 
96243 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
96244 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
96245 /*! NSE1 - NonSecure Enable for block B
96246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96249  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96250  */
96251 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK)
96252 
96253 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
96254 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
96255 /*! MBACSEL2 - Memory Block Access Control Select for block B
96256  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96257  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96258  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96259  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96260  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96261  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96262  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96263  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96264  */
96265 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK)
96266 
96267 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
96268 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
96269 /*! NSE2 - NonSecure Enable for block B
96270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96273  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96274  */
96275 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK)
96276 
96277 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
96278 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
96279 /*! MBACSEL3 - Memory Block Access Control Select for block B
96280  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96281  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96282  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96283  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96284  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96285  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96286  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96287  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96288  */
96289 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK)
96290 
96291 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
96292 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
96293 /*! NSE3 - NonSecure Enable for block B
96294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96297  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96298  */
96299 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK)
96300 
96301 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
96302 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
96303 /*! MBACSEL4 - Memory Block Access Control Select for block B
96304  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96305  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96306  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96307  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96308  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96309  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96310  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96311  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96312  */
96313 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK)
96314 
96315 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
96316 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
96317 /*! NSE4 - NonSecure Enable for block B
96318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96321  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96322  */
96323 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK)
96324 
96325 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
96326 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
96327 /*! MBACSEL5 - Memory Block Access Control Select for block B
96328  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96329  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96330  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96331  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96332  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96333  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96334  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96335  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96336  */
96337 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK)
96338 
96339 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
96340 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
96341 /*! NSE5 - NonSecure Enable for block B
96342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96345  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96346  */
96347 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK)
96348 
96349 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
96350 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
96351 /*! MBACSEL6 - Memory Block Access Control Select for block B
96352  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96353  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96354  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96355  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96356  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96357  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96358  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96359  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96360  */
96361 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK)
96362 
96363 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
96364 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
96365 /*! NSE6 - NonSecure Enable for block B
96366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96369  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96370  */
96371 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK)
96372 
96373 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
96374 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
96375 /*! MBACSEL7 - Memory Block Access Control Select for block B
96376  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96377  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96378  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96379  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96380  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96381  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96382  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96383  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96384  */
96385 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK)
96386 
96387 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
96388 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
96389 /*! NSE7 - NonSecure Enable for block B
96390  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96391  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96392  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96393  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96394  */
96395 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK)
96396 /*! @} */
96397 
96398 /* The count of TRDC_MBC_DOM5_MEM1_BLK_CFG_W */
96399 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_COUNT       (2U)
96400 
96401 /* The count of TRDC_MBC_DOM5_MEM1_BLK_CFG_W */
96402 #define TRDC_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2      (4U)
96403 
96404 /*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
96405 /*! @{ */
96406 
96407 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
96408 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
96409 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
96410  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96411  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96412  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96413  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96414  */
96415 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK)
96416 
96417 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
96418 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
96419 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
96420  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96421  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96422  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96423  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96424  */
96425 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK)
96426 
96427 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
96428 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
96429 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
96430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96433  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96434  */
96435 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK)
96436 
96437 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
96438 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
96439 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
96440  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96441  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96442  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96443  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96444  */
96445 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK)
96446 
96447 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
96448 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
96449 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
96450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96453  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96454  */
96455 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK)
96456 
96457 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
96458 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
96459 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
96460  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96461  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96462  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96463  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96464  */
96465 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK)
96466 
96467 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
96468 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
96469 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
96470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96473  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96474  */
96475 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK)
96476 
96477 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
96478 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
96479 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
96480  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96481  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96482  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96483  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96484  */
96485 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK)
96486 
96487 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
96488 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
96489 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
96490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96493  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96494  */
96495 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK)
96496 
96497 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
96498 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
96499 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
96500  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96501  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96502  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96503  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96504  */
96505 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK)
96506 
96507 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
96508 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
96509 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
96510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96513  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96514  */
96515 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK)
96516 
96517 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
96518 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
96519 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
96520  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96521  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96522  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96523  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96524  */
96525 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK)
96526 
96527 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
96528 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
96529 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
96530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96533  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96534  */
96535 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK)
96536 
96537 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
96538 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
96539 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
96540  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96541  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96542  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96543  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96544  */
96545 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK)
96546 
96547 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
96548 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
96549 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
96550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96553  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96554  */
96555 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK)
96556 
96557 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
96558 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
96559 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
96560  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96561  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96562  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96563  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96564  */
96565 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK)
96566 
96567 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
96568 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
96569 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
96570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96573  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96574  */
96575 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK)
96576 
96577 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
96578 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
96579 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
96580  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96581  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96582  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96583  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96584  */
96585 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK)
96586 
96587 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
96588 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
96589 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
96590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96593  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96594  */
96595 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK)
96596 
96597 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
96598 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
96599 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
96600  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96601  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96602  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96603  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96604  */
96605 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK)
96606 
96607 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
96608 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
96609 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
96610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96613  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96614  */
96615 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK)
96616 
96617 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
96618 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
96619 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
96620  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96621  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96622  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96623  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96624  */
96625 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK)
96626 
96627 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
96628 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
96629 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
96630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96633  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96634  */
96635 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK)
96636 
96637 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
96638 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
96639 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
96640  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96641  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96642  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96643  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96644  */
96645 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK)
96646 
96647 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
96648 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
96649 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
96650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96653  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96654  */
96655 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK)
96656 
96657 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
96658 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
96659 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
96660  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96661  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96662  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96663  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96664  */
96665 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK)
96666 
96667 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
96668 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
96669 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
96670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96673  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96674  */
96675 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK)
96676 
96677 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
96678 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
96679 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
96680  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96681  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96682  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96683  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96684  */
96685 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK)
96686 
96687 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
96688 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
96689 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
96690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96693  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96694  */
96695 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK)
96696 
96697 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
96698 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
96699 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
96700  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96701  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96702  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96703  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96704  */
96705 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK)
96706 
96707 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
96708 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
96709 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
96710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96713  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96714  */
96715 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK)
96716 
96717 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
96718 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
96719 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
96720  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96721  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96722  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96723  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96724  */
96725 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK)
96726 /*! @} */
96727 
96728 /* The count of TRDC_MBC_DOM5_MEM1_BLK_NSE_W */
96729 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_COUNT       (2U)
96730 
96731 /* The count of TRDC_MBC_DOM5_MEM1_BLK_NSE_W */
96732 #define TRDC_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2      (1U)
96733 
96734 /*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
96735 /*! @{ */
96736 
96737 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
96738 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
96739 /*! MBACSEL0 - Memory Block Access Control Select for block B
96740  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96741  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96742  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96743  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96744  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96745  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96746  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96747  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96748  */
96749 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK)
96750 
96751 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
96752 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
96753 /*! NSE0 - NonSecure Enable for block B
96754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96757  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96758  */
96759 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK)
96760 
96761 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
96762 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
96763 /*! MBACSEL1 - Memory Block Access Control Select for block B
96764  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96765  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96766  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96767  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96768  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96769  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96770  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96771  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96772  */
96773 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK)
96774 
96775 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
96776 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
96777 /*! NSE1 - NonSecure Enable for block B
96778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96781  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96782  */
96783 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK)
96784 
96785 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
96786 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
96787 /*! MBACSEL2 - Memory Block Access Control Select for block B
96788  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96789  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96790  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96791  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96792  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96793  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96794  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96795  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96796  */
96797 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK)
96798 
96799 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
96800 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
96801 /*! NSE2 - NonSecure Enable for block B
96802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96805  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96806  */
96807 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK)
96808 
96809 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
96810 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
96811 /*! MBACSEL3 - Memory Block Access Control Select for block B
96812  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96813  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96814  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96815  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96816  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96817  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96818  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96819  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96820  */
96821 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK)
96822 
96823 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
96824 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
96825 /*! NSE3 - NonSecure Enable for block B
96826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96829  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96830  */
96831 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK)
96832 
96833 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
96834 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
96835 /*! MBACSEL4 - Memory Block Access Control Select for block B
96836  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96837  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96838  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96839  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96840  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96841  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96842  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96843  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96844  */
96845 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK)
96846 
96847 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
96848 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
96849 /*! NSE4 - NonSecure Enable for block B
96850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96853  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96854  */
96855 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK)
96856 
96857 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
96858 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
96859 /*! MBACSEL5 - Memory Block Access Control Select for block B
96860  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96861  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96862  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96863  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96864  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96865  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96866  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96867  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96868  */
96869 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK)
96870 
96871 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
96872 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
96873 /*! NSE5 - NonSecure Enable for block B
96874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96877  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96878  */
96879 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK)
96880 
96881 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
96882 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
96883 /*! MBACSEL6 - Memory Block Access Control Select for block B
96884  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96885  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96886  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96887  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96888  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96889  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96890  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96891  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96892  */
96893 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK)
96894 
96895 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
96896 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
96897 /*! NSE6 - NonSecure Enable for block B
96898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96901  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96902  */
96903 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK)
96904 
96905 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
96906 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
96907 /*! MBACSEL7 - Memory Block Access Control Select for block B
96908  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
96909  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
96910  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
96911  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
96912  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
96913  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
96914  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
96915  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
96916  */
96917 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK)
96918 
96919 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
96920 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
96921 /*! NSE7 - NonSecure Enable for block B
96922  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
96923  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96924  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96925  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96926  */
96927 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK)
96928 /*! @} */
96929 
96930 /* The count of TRDC_MBC_DOM5_MEM2_BLK_CFG_W */
96931 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_COUNT       (2U)
96932 
96933 /* The count of TRDC_MBC_DOM5_MEM2_BLK_CFG_W */
96934 #define TRDC_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2      (1U)
96935 
96936 /*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
96937 /*! @{ */
96938 
96939 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
96940 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
96941 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
96942  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96943  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96944  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96945  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96946  */
96947 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK)
96948 
96949 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
96950 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
96951 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
96952  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96953  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96954  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96955  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96956  */
96957 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK)
96958 
96959 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
96960 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
96961 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
96962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96965  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96966  */
96967 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK)
96968 
96969 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
96970 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
96971 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
96972  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96973  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96974  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96975  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96976  */
96977 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK)
96978 
96979 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
96980 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
96981 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
96982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96985  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96986  */
96987 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK)
96988 
96989 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
96990 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
96991 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
96992  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
96993  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
96994  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
96995  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
96996  */
96997 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK)
96998 
96999 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
97000 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
97001 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
97002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97005  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97006  */
97007 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK)
97008 
97009 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
97010 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
97011 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
97012  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97013  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97014  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97015  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97016  */
97017 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK)
97018 
97019 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
97020 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
97021 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
97022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97025  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97026  */
97027 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK)
97028 
97029 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
97030 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
97031 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
97032  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97033  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97034  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97035  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97036  */
97037 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK)
97038 
97039 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
97040 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
97041 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
97042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97045  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97046  */
97047 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK)
97048 
97049 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
97050 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
97051 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
97052  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97053  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97054  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97055  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97056  */
97057 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK)
97058 
97059 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
97060 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
97061 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
97062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97065  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97066  */
97067 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK)
97068 
97069 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
97070 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
97071 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
97072  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97073  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97074  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97075  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97076  */
97077 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK)
97078 
97079 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
97080 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
97081 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
97082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97085  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97086  */
97087 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK)
97088 
97089 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
97090 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
97091 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
97092  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97093  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97094  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97095  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97096  */
97097 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK)
97098 
97099 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
97100 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
97101 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
97102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97105  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97106  */
97107 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK)
97108 
97109 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
97110 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
97111 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
97112  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97113  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97114  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97115  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97116  */
97117 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK)
97118 
97119 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
97120 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
97121 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
97122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97125  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97126  */
97127 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK)
97128 
97129 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
97130 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
97131 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
97132  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97133  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97134  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97135  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97136  */
97137 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK)
97138 
97139 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
97140 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
97141 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
97142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97145  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97146  */
97147 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK)
97148 
97149 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
97150 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
97151 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
97152  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97153  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97154  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97155  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97156  */
97157 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK)
97158 
97159 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
97160 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
97161 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
97162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97165  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97166  */
97167 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK)
97168 
97169 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
97170 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
97171 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
97172  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97173  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97174  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97175  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97176  */
97177 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK)
97178 
97179 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
97180 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
97181 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
97182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97185  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97186  */
97187 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK)
97188 
97189 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
97190 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
97191 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
97192  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97193  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97194  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97195  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97196  */
97197 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK)
97198 
97199 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
97200 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
97201 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
97202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97205  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97206  */
97207 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK)
97208 
97209 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
97210 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
97211 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
97212  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97213  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97214  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97215  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97216  */
97217 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK)
97218 
97219 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
97220 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
97221 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
97222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97225  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97226  */
97227 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK)
97228 
97229 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
97230 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
97231 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
97232  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97233  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97234  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97235  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97236  */
97237 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK)
97238 
97239 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
97240 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
97241 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
97242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97245  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97246  */
97247 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK)
97248 
97249 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
97250 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
97251 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
97252  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97253  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97254  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97255  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97256  */
97257 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK)
97258 /*! @} */
97259 
97260 /* The count of TRDC_MBC_DOM5_MEM2_BLK_NSE_W */
97261 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_COUNT       (2U)
97262 
97263 /* The count of TRDC_MBC_DOM5_MEM2_BLK_NSE_W */
97264 #define TRDC_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2      (1U)
97265 
97266 /*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
97267 /*! @{ */
97268 
97269 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
97270 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
97271 /*! MBACSEL0 - Memory Block Access Control Select for block B
97272  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97273  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97274  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97275  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97276  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97277  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97278  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97279  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97280  */
97281 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK)
97282 
97283 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
97284 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
97285 /*! NSE0 - NonSecure Enable for block B
97286  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97287  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97288  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97289  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97290  */
97291 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK)
97292 
97293 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
97294 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
97295 /*! MBACSEL1 - Memory Block Access Control Select for block B
97296  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97297  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97298  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97299  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97300  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97301  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97302  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97303  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97304  */
97305 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK)
97306 
97307 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
97308 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
97309 /*! NSE1 - NonSecure Enable for block B
97310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97313  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97314  */
97315 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK)
97316 
97317 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
97318 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
97319 /*! MBACSEL2 - Memory Block Access Control Select for block B
97320  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97321  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97322  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97323  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97324  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97325  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97326  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97327  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97328  */
97329 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK)
97330 
97331 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
97332 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
97333 /*! NSE2 - NonSecure Enable for block B
97334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97337  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97338  */
97339 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK)
97340 
97341 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
97342 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
97343 /*! MBACSEL3 - Memory Block Access Control Select for block B
97344  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97345  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97346  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97347  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97348  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97349  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97350  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97351  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97352  */
97353 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK)
97354 
97355 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
97356 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
97357 /*! NSE3 - NonSecure Enable for block B
97358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97361  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97362  */
97363 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK)
97364 
97365 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
97366 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
97367 /*! MBACSEL4 - Memory Block Access Control Select for block B
97368  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97369  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97370  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97371  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97372  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97373  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97374  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97375  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97376  */
97377 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK)
97378 
97379 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
97380 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
97381 /*! NSE4 - NonSecure Enable for block B
97382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97385  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97386  */
97387 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK)
97388 
97389 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
97390 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
97391 /*! MBACSEL5 - Memory Block Access Control Select for block B
97392  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97393  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97394  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97395  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97396  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97397  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97398  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97399  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97400  */
97401 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK)
97402 
97403 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
97404 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
97405 /*! NSE5 - NonSecure Enable for block B
97406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97409  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97410  */
97411 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK)
97412 
97413 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
97414 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
97415 /*! MBACSEL6 - Memory Block Access Control Select for block B
97416  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97417  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97418  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97419  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97420  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97421  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97422  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97423  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97424  */
97425 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK)
97426 
97427 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
97428 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
97429 /*! NSE6 - NonSecure Enable for block B
97430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97433  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97434  */
97435 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK)
97436 
97437 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
97438 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
97439 /*! MBACSEL7 - Memory Block Access Control Select for block B
97440  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97441  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97442  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97443  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97444  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97445  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97446  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97447  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97448  */
97449 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK)
97450 
97451 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
97452 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
97453 /*! NSE7 - NonSecure Enable for block B
97454  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97455  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97456  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97457  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97458  */
97459 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK)
97460 /*! @} */
97461 
97462 /* The count of TRDC_MBC_DOM5_MEM3_BLK_CFG_W */
97463 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_COUNT       (2U)
97464 
97465 /* The count of TRDC_MBC_DOM5_MEM3_BLK_CFG_W */
97466 #define TRDC_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2      (3U)
97467 
97468 /*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
97469 /*! @{ */
97470 
97471 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
97472 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
97473 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
97474  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97475  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97476  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97477  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97478  */
97479 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK)
97480 
97481 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
97482 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
97483 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
97484  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97485  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97486  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97487  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97488  */
97489 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK)
97490 
97491 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
97492 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
97493 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
97494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97497  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97498  */
97499 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK)
97500 
97501 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
97502 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
97503 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
97504  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97505  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97506  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97507  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97508  */
97509 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK)
97510 
97511 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
97512 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
97513 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
97514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97517  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97518  */
97519 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK)
97520 
97521 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
97522 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
97523 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
97524  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97525  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97526  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97527  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97528  */
97529 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK)
97530 
97531 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
97532 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
97533 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
97534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97537  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97538  */
97539 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK)
97540 
97541 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
97542 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
97543 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
97544  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97545  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97546  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97547  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97548  */
97549 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK)
97550 
97551 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
97552 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
97553 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
97554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97557  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97558  */
97559 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK)
97560 
97561 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
97562 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
97563 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
97564  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97565  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97566  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97567  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97568  */
97569 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK)
97570 
97571 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
97572 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
97573 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
97574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97577  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97578  */
97579 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK)
97580 
97581 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
97582 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
97583 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
97584  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97585  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97586  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97587  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97588  */
97589 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK)
97590 
97591 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
97592 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
97593 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
97594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97597  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97598  */
97599 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK)
97600 
97601 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
97602 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
97603 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
97604  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97605  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97606  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97607  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97608  */
97609 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK)
97610 
97611 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
97612 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
97613 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
97614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97617  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97618  */
97619 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK)
97620 
97621 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
97622 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
97623 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
97624  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97625  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97626  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97627  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97628  */
97629 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK)
97630 
97631 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
97632 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
97633 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
97634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97637  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97638  */
97639 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK)
97640 
97641 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
97642 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
97643 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
97644  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97645  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97646  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97647  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97648  */
97649 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK)
97650 
97651 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
97652 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
97653 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
97654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97657  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97658  */
97659 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK)
97660 
97661 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
97662 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
97663 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
97664  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97665  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97666  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97667  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97668  */
97669 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK)
97670 
97671 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
97672 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
97673 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
97674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97677  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97678  */
97679 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK)
97680 
97681 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
97682 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
97683 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
97684  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97685  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97686  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97687  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97688  */
97689 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK)
97690 
97691 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
97692 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
97693 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
97694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97697  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97698  */
97699 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK)
97700 
97701 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
97702 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
97703 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
97704  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97705  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97706  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97707  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97708  */
97709 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK)
97710 
97711 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
97712 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
97713 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
97714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97717  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97718  */
97719 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK)
97720 
97721 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
97722 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
97723 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
97724  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97725  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97726  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97727  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97728  */
97729 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK)
97730 
97731 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
97732 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
97733 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
97734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97737  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97738  */
97739 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK)
97740 
97741 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
97742 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
97743 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
97744  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97745  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97746  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97747  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97748  */
97749 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK)
97750 
97751 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
97752 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
97753 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
97754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97757  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97758  */
97759 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK)
97760 
97761 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
97762 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
97763 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
97764  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97765  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97766  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97767  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97768  */
97769 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK)
97770 
97771 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
97772 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
97773 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
97774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97777  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97778  */
97779 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK)
97780 
97781 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
97782 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
97783 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
97784  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
97785  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97786  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97787  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97788  */
97789 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK)
97790 /*! @} */
97791 
97792 /* The count of TRDC_MBC_DOM5_MEM3_BLK_NSE_W */
97793 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_COUNT       (2U)
97794 
97795 /* The count of TRDC_MBC_DOM5_MEM3_BLK_NSE_W */
97796 #define TRDC_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2      (1U)
97797 
97798 /*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
97799 /*! @{ */
97800 
97801 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
97802 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
97803 /*! MBACSEL0 - Memory Block Access Control Select for block B
97804  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97805  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97806  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97807  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97808  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97809  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97810  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97811  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97812  */
97813 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK)
97814 
97815 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
97816 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
97817 /*! NSE0 - NonSecure Enable for block B
97818  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97819  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97820  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97821  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97822  */
97823 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK)
97824 
97825 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
97826 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
97827 /*! MBACSEL1 - Memory Block Access Control Select for block B
97828  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97829  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97830  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97831  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97832  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97833  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97834  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97835  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97836  */
97837 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK)
97838 
97839 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
97840 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
97841 /*! NSE1 - NonSecure Enable for block B
97842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97845  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97846  */
97847 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK)
97848 
97849 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
97850 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
97851 /*! MBACSEL2 - Memory Block Access Control Select for block B
97852  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97853  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97854  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97855  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97856  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97857  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97858  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97859  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97860  */
97861 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK)
97862 
97863 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
97864 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
97865 /*! NSE2 - NonSecure Enable for block B
97866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97869  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97870  */
97871 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK)
97872 
97873 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
97874 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
97875 /*! MBACSEL3 - Memory Block Access Control Select for block B
97876  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97877  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97878  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97879  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97880  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97881  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97882  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97883  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97884  */
97885 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK)
97886 
97887 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
97888 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
97889 /*! NSE3 - NonSecure Enable for block B
97890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97893  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97894  */
97895 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK)
97896 
97897 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
97898 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
97899 /*! MBACSEL4 - Memory Block Access Control Select for block B
97900  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97901  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97902  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97903  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97904  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97905  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97906  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97907  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97908  */
97909 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK)
97910 
97911 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
97912 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
97913 /*! NSE4 - NonSecure Enable for block B
97914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97917  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97918  */
97919 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK)
97920 
97921 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
97922 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
97923 /*! MBACSEL5 - Memory Block Access Control Select for block B
97924  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97925  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97926  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97927  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97928  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97929  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97930  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97931  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97932  */
97933 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK)
97934 
97935 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
97936 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
97937 /*! NSE5 - NonSecure Enable for block B
97938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97941  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97942  */
97943 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK)
97944 
97945 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
97946 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
97947 /*! MBACSEL6 - Memory Block Access Control Select for block B
97948  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97949  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97950  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97951  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97952  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97953  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97954  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97955  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97956  */
97957 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK)
97958 
97959 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
97960 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
97961 /*! NSE6 - NonSecure Enable for block B
97962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97965  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97966  */
97967 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK)
97968 
97969 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
97970 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
97971 /*! MBACSEL7 - Memory Block Access Control Select for block B
97972  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
97973  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
97974  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
97975  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
97976  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
97977  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
97978  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
97979  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
97980  */
97981 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK)
97982 
97983 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
97984 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
97985 /*! NSE7 - NonSecure Enable for block B
97986  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
97987  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
97988  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
97989  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
97990  */
97991 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK)
97992 /*! @} */
97993 
97994 /* The count of TRDC_MBC_DOM6_MEM0_BLK_CFG_W */
97995 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_COUNT       (2U)
97996 
97997 /* The count of TRDC_MBC_DOM6_MEM0_BLK_CFG_W */
97998 #define TRDC_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2      (16U)
97999 
98000 /*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
98001 /*! @{ */
98002 
98003 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
98004 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
98005 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
98006  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98007  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98008  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98009  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98010  */
98011 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK)
98012 
98013 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
98014 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
98015 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
98016  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98017  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98018  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98019  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98020  */
98021 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK)
98022 
98023 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
98024 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
98025 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
98026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98029  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98030  */
98031 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK)
98032 
98033 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
98034 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
98035 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
98036  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98037  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98038  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98039  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98040  */
98041 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK)
98042 
98043 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
98044 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
98045 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
98046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98049  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98050  */
98051 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK)
98052 
98053 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
98054 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
98055 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
98056  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98057  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98058  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98059  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98060  */
98061 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK)
98062 
98063 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
98064 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
98065 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
98066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98069  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98070  */
98071 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK)
98072 
98073 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
98074 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
98075 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
98076  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98077  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98078  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98079  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98080  */
98081 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK)
98082 
98083 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
98084 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
98085 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
98086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98089  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98090  */
98091 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK)
98092 
98093 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
98094 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
98095 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
98096  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98097  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98098  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98099  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98100  */
98101 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK)
98102 
98103 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
98104 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
98105 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
98106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98109  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98110  */
98111 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK)
98112 
98113 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
98114 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
98115 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
98116  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98117  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98118  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98119  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98120  */
98121 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK)
98122 
98123 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
98124 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
98125 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
98126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98129  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98130  */
98131 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK)
98132 
98133 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
98134 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
98135 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
98136  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98137  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98138  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98139  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98140  */
98141 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK)
98142 
98143 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
98144 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
98145 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
98146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98149  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98150  */
98151 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK)
98152 
98153 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
98154 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
98155 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
98156  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98157  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98158  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98159  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98160  */
98161 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK)
98162 
98163 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
98164 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
98165 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
98166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98169  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98170  */
98171 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK)
98172 
98173 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
98174 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
98175 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
98176  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98177  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98178  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98179  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98180  */
98181 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK)
98182 
98183 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
98184 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
98185 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
98186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98189  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98190  */
98191 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK)
98192 
98193 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
98194 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
98195 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
98196  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98197  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98198  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98199  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98200  */
98201 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK)
98202 
98203 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
98204 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
98205 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
98206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98209  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98210  */
98211 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK)
98212 
98213 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
98214 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
98215 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
98216  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98217  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98218  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98219  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98220  */
98221 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK)
98222 
98223 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
98224 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
98225 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
98226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98229  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98230  */
98231 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK)
98232 
98233 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
98234 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
98235 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
98236  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98237  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98238  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98239  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98240  */
98241 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK)
98242 
98243 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
98244 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
98245 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
98246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98249  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98250  */
98251 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK)
98252 
98253 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
98254 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
98255 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
98256  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98257  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98258  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98259  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98260  */
98261 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK)
98262 
98263 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
98264 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
98265 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
98266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98269  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98270  */
98271 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK)
98272 
98273 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
98274 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
98275 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
98276  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98277  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98278  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98279  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98280  */
98281 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK)
98282 
98283 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
98284 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
98285 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
98286  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98287  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98288  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98289  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98290  */
98291 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK)
98292 
98293 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
98294 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
98295 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
98296  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98297  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98298  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98299  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98300  */
98301 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK)
98302 
98303 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
98304 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
98305 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
98306  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98307  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98308  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98309  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98310  */
98311 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK)
98312 
98313 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
98314 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
98315 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
98316  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98317  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98318  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98319  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98320  */
98321 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK)
98322 /*! @} */
98323 
98324 /* The count of TRDC_MBC_DOM6_MEM0_BLK_NSE_W */
98325 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_COUNT       (2U)
98326 
98327 /* The count of TRDC_MBC_DOM6_MEM0_BLK_NSE_W */
98328 #define TRDC_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2      (4U)
98329 
98330 /*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
98331 /*! @{ */
98332 
98333 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
98334 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
98335 /*! MBACSEL0 - Memory Block Access Control Select for block B
98336  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98337  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98338  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98339  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98340  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98341  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98342  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98343  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98344  */
98345 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK)
98346 
98347 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
98348 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
98349 /*! NSE0 - NonSecure Enable for block B
98350  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98351  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98352  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98353  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98354  */
98355 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK)
98356 
98357 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
98358 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
98359 /*! MBACSEL1 - Memory Block Access Control Select for block B
98360  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98361  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98362  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98363  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98364  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98365  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98366  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98367  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98368  */
98369 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK)
98370 
98371 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
98372 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
98373 /*! NSE1 - NonSecure Enable for block B
98374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98377  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98378  */
98379 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK)
98380 
98381 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
98382 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
98383 /*! MBACSEL2 - Memory Block Access Control Select for block B
98384  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98385  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98386  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98387  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98388  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98389  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98390  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98391  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98392  */
98393 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK)
98394 
98395 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
98396 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
98397 /*! NSE2 - NonSecure Enable for block B
98398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98401  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98402  */
98403 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK)
98404 
98405 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
98406 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
98407 /*! MBACSEL3 - Memory Block Access Control Select for block B
98408  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98409  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98410  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98411  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98412  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98413  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98414  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98415  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98416  */
98417 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK)
98418 
98419 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
98420 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
98421 /*! NSE3 - NonSecure Enable for block B
98422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98425  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98426  */
98427 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK)
98428 
98429 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
98430 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
98431 /*! MBACSEL4 - Memory Block Access Control Select for block B
98432  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98433  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98434  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98435  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98436  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98437  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98438  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98439  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98440  */
98441 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK)
98442 
98443 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
98444 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
98445 /*! NSE4 - NonSecure Enable for block B
98446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98449  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98450  */
98451 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK)
98452 
98453 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
98454 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
98455 /*! MBACSEL5 - Memory Block Access Control Select for block B
98456  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98457  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98458  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98459  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98460  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98461  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98462  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98463  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98464  */
98465 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK)
98466 
98467 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
98468 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
98469 /*! NSE5 - NonSecure Enable for block B
98470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98473  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98474  */
98475 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK)
98476 
98477 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
98478 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
98479 /*! MBACSEL6 - Memory Block Access Control Select for block B
98480  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98481  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98482  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98483  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98484  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98485  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98486  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98487  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98488  */
98489 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK)
98490 
98491 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
98492 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
98493 /*! NSE6 - NonSecure Enable for block B
98494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98497  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98498  */
98499 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK)
98500 
98501 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
98502 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
98503 /*! MBACSEL7 - Memory Block Access Control Select for block B
98504  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98505  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98506  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98507  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98508  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98509  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98510  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98511  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98512  */
98513 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK)
98514 
98515 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
98516 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
98517 /*! NSE7 - NonSecure Enable for block B
98518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98521  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98522  */
98523 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK)
98524 /*! @} */
98525 
98526 /* The count of TRDC_MBC_DOM6_MEM1_BLK_CFG_W */
98527 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_COUNT       (2U)
98528 
98529 /* The count of TRDC_MBC_DOM6_MEM1_BLK_CFG_W */
98530 #define TRDC_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2      (4U)
98531 
98532 /*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
98533 /*! @{ */
98534 
98535 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
98536 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
98537 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
98538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98541  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98542  */
98543 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK)
98544 
98545 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
98546 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
98547 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
98548  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98549  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98550  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98551  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98552  */
98553 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK)
98554 
98555 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
98556 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
98557 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
98558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98561  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98562  */
98563 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK)
98564 
98565 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
98566 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
98567 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
98568  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98569  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98570  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98571  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98572  */
98573 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK)
98574 
98575 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
98576 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
98577 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
98578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98581  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98582  */
98583 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK)
98584 
98585 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
98586 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
98587 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
98588  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98589  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98590  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98591  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98592  */
98593 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK)
98594 
98595 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
98596 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
98597 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
98598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98601  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98602  */
98603 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK)
98604 
98605 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
98606 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
98607 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
98608  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98609  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98610  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98611  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98612  */
98613 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK)
98614 
98615 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
98616 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
98617 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
98618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98621  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98622  */
98623 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK)
98624 
98625 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
98626 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
98627 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
98628  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98629  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98630  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98631  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98632  */
98633 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK)
98634 
98635 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
98636 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
98637 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
98638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98641  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98642  */
98643 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK)
98644 
98645 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
98646 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
98647 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
98648  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98649  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98650  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98651  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98652  */
98653 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK)
98654 
98655 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
98656 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
98657 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
98658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98661  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98662  */
98663 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK)
98664 
98665 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
98666 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
98667 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
98668  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98669  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98670  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98671  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98672  */
98673 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK)
98674 
98675 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
98676 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
98677 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
98678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98681  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98682  */
98683 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK)
98684 
98685 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
98686 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
98687 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
98688  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98689  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98690  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98691  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98692  */
98693 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK)
98694 
98695 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
98696 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
98697 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
98698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98701  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98702  */
98703 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK)
98704 
98705 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
98706 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
98707 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
98708  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98709  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98710  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98711  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98712  */
98713 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK)
98714 
98715 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
98716 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
98717 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
98718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98721  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98722  */
98723 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK)
98724 
98725 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
98726 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
98727 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
98728  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98729  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98730  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98731  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98732  */
98733 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK)
98734 
98735 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
98736 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
98737 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
98738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98741  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98742  */
98743 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK)
98744 
98745 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
98746 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
98747 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
98748  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98749  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98750  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98751  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98752  */
98753 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK)
98754 
98755 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
98756 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
98757 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
98758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98761  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98762  */
98763 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK)
98764 
98765 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
98766 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
98767 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
98768  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98769  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98770  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98771  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98772  */
98773 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK)
98774 
98775 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
98776 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
98777 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
98778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98781  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98782  */
98783 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK)
98784 
98785 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
98786 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
98787 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
98788  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98789  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98790  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98791  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98792  */
98793 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK)
98794 
98795 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
98796 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
98797 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
98798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98801  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98802  */
98803 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK)
98804 
98805 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
98806 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
98807 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
98808  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98809  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98810  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98811  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98812  */
98813 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK)
98814 
98815 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
98816 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
98817 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
98818  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98819  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98820  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98821  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98822  */
98823 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK)
98824 
98825 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
98826 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
98827 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
98828  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98829  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98830  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98831  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98832  */
98833 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK)
98834 
98835 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
98836 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
98837 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
98838  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98839  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98840  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98841  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98842  */
98843 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK)
98844 
98845 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
98846 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
98847 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
98848  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
98849  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98850  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98851  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98852  */
98853 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK)
98854 /*! @} */
98855 
98856 /* The count of TRDC_MBC_DOM6_MEM1_BLK_NSE_W */
98857 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_COUNT       (2U)
98858 
98859 /* The count of TRDC_MBC_DOM6_MEM1_BLK_NSE_W */
98860 #define TRDC_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2      (1U)
98861 
98862 /*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
98863 /*! @{ */
98864 
98865 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
98866 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
98867 /*! MBACSEL0 - Memory Block Access Control Select for block B
98868  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98869  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98870  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98871  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98872  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98873  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98874  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98875  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98876  */
98877 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK)
98878 
98879 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
98880 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
98881 /*! NSE0 - NonSecure Enable for block B
98882  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98883  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98884  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98885  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98886  */
98887 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK)
98888 
98889 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
98890 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
98891 /*! MBACSEL1 - Memory Block Access Control Select for block B
98892  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98893  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98894  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98895  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98896  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98897  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98898  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98899  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98900  */
98901 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK)
98902 
98903 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
98904 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
98905 /*! NSE1 - NonSecure Enable for block B
98906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98909  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98910  */
98911 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK)
98912 
98913 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
98914 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
98915 /*! MBACSEL2 - Memory Block Access Control Select for block B
98916  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98917  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98918  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98919  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98920  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98921  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98922  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98923  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98924  */
98925 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK)
98926 
98927 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
98928 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
98929 /*! NSE2 - NonSecure Enable for block B
98930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98933  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98934  */
98935 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK)
98936 
98937 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
98938 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
98939 /*! MBACSEL3 - Memory Block Access Control Select for block B
98940  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98941  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98942  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98943  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98944  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98945  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98946  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98947  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98948  */
98949 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK)
98950 
98951 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
98952 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
98953 /*! NSE3 - NonSecure Enable for block B
98954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98957  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98958  */
98959 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK)
98960 
98961 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
98962 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
98963 /*! MBACSEL4 - Memory Block Access Control Select for block B
98964  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98965  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98966  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98967  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98968  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98969  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98970  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98971  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98972  */
98973 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK)
98974 
98975 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
98976 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
98977 /*! NSE4 - NonSecure Enable for block B
98978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
98979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
98980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
98981  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
98982  */
98983 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK)
98984 
98985 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
98986 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
98987 /*! MBACSEL5 - Memory Block Access Control Select for block B
98988  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
98989  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
98990  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
98991  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
98992  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
98993  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
98994  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
98995  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
98996  */
98997 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK)
98998 
98999 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
99000 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
99001 /*! NSE5 - NonSecure Enable for block B
99002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99005  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99006  */
99007 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK)
99008 
99009 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
99010 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
99011 /*! MBACSEL6 - Memory Block Access Control Select for block B
99012  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99013  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99014  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99015  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99016  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99017  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99018  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99019  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99020  */
99021 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK)
99022 
99023 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
99024 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
99025 /*! NSE6 - NonSecure Enable for block B
99026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99029  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99030  */
99031 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK)
99032 
99033 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
99034 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
99035 /*! MBACSEL7 - Memory Block Access Control Select for block B
99036  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99037  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99038  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99039  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99040  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99041  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99042  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99043  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99044  */
99045 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK)
99046 
99047 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
99048 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
99049 /*! NSE7 - NonSecure Enable for block B
99050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99053  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99054  */
99055 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK)
99056 /*! @} */
99057 
99058 /* The count of TRDC_MBC_DOM6_MEM2_BLK_CFG_W */
99059 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_COUNT       (2U)
99060 
99061 /* The count of TRDC_MBC_DOM6_MEM2_BLK_CFG_W */
99062 #define TRDC_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2      (1U)
99063 
99064 /*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
99065 /*! @{ */
99066 
99067 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
99068 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
99069 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
99070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99073  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99074  */
99075 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK)
99076 
99077 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
99078 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
99079 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
99080  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99081  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99082  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99083  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99084  */
99085 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK)
99086 
99087 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
99088 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
99089 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
99090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99093  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99094  */
99095 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK)
99096 
99097 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
99098 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
99099 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
99100  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99101  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99102  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99103  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99104  */
99105 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK)
99106 
99107 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
99108 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
99109 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
99110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99113  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99114  */
99115 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK)
99116 
99117 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
99118 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
99119 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
99120  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99121  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99122  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99123  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99124  */
99125 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK)
99126 
99127 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
99128 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
99129 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
99130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99133  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99134  */
99135 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK)
99136 
99137 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
99138 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
99139 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
99140  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99141  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99142  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99143  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99144  */
99145 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK)
99146 
99147 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
99148 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
99149 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
99150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99153  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99154  */
99155 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK)
99156 
99157 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
99158 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
99159 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
99160  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99161  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99162  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99163  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99164  */
99165 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK)
99166 
99167 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
99168 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
99169 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
99170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99173  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99174  */
99175 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK)
99176 
99177 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
99178 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
99179 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
99180  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99181  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99182  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99183  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99184  */
99185 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK)
99186 
99187 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
99188 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
99189 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
99190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99193  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99194  */
99195 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK)
99196 
99197 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
99198 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
99199 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
99200  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99201  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99202  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99203  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99204  */
99205 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK)
99206 
99207 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
99208 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
99209 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
99210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99213  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99214  */
99215 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK)
99216 
99217 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
99218 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
99219 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
99220  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99221  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99222  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99223  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99224  */
99225 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK)
99226 
99227 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
99228 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
99229 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
99230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99233  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99234  */
99235 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK)
99236 
99237 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
99238 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
99239 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
99240  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99241  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99242  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99243  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99244  */
99245 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK)
99246 
99247 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
99248 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
99249 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
99250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99253  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99254  */
99255 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK)
99256 
99257 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
99258 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
99259 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
99260  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99261  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99262  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99263  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99264  */
99265 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK)
99266 
99267 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
99268 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
99269 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
99270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99273  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99274  */
99275 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK)
99276 
99277 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
99278 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
99279 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
99280  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99281  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99282  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99283  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99284  */
99285 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK)
99286 
99287 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
99288 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
99289 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
99290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99293  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99294  */
99295 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK)
99296 
99297 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
99298 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
99299 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
99300  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99301  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99302  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99303  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99304  */
99305 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK)
99306 
99307 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
99308 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
99309 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
99310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99313  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99314  */
99315 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK)
99316 
99317 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
99318 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
99319 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
99320  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99321  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99322  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99323  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99324  */
99325 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK)
99326 
99327 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
99328 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
99329 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
99330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99333  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99334  */
99335 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK)
99336 
99337 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
99338 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
99339 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
99340  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99341  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99342  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99343  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99344  */
99345 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK)
99346 
99347 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
99348 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
99349 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
99350  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99351  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99352  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99353  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99354  */
99355 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK)
99356 
99357 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
99358 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
99359 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
99360  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99361  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99362  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99363  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99364  */
99365 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK)
99366 
99367 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
99368 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
99369 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
99370  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99371  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99372  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99373  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99374  */
99375 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK)
99376 
99377 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
99378 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
99379 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
99380  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99381  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99382  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99383  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99384  */
99385 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK)
99386 /*! @} */
99387 
99388 /* The count of TRDC_MBC_DOM6_MEM2_BLK_NSE_W */
99389 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_COUNT       (2U)
99390 
99391 /* The count of TRDC_MBC_DOM6_MEM2_BLK_NSE_W */
99392 #define TRDC_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2      (1U)
99393 
99394 /*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
99395 /*! @{ */
99396 
99397 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
99398 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
99399 /*! MBACSEL0 - Memory Block Access Control Select for block B
99400  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99401  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99402  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99403  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99404  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99405  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99406  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99407  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99408  */
99409 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK)
99410 
99411 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
99412 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
99413 /*! NSE0 - NonSecure Enable for block B
99414  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99415  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99416  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99417  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99418  */
99419 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK)
99420 
99421 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
99422 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
99423 /*! MBACSEL1 - Memory Block Access Control Select for block B
99424  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99425  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99426  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99427  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99428  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99429  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99430  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99431  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99432  */
99433 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK)
99434 
99435 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
99436 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
99437 /*! NSE1 - NonSecure Enable for block B
99438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99441  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99442  */
99443 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK)
99444 
99445 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
99446 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
99447 /*! MBACSEL2 - Memory Block Access Control Select for block B
99448  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99449  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99450  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99451  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99452  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99453  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99454  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99455  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99456  */
99457 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK)
99458 
99459 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
99460 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
99461 /*! NSE2 - NonSecure Enable for block B
99462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99465  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99466  */
99467 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK)
99468 
99469 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
99470 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
99471 /*! MBACSEL3 - Memory Block Access Control Select for block B
99472  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99473  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99474  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99475  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99476  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99477  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99478  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99479  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99480  */
99481 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK)
99482 
99483 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
99484 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
99485 /*! NSE3 - NonSecure Enable for block B
99486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99489  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99490  */
99491 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK)
99492 
99493 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
99494 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
99495 /*! MBACSEL4 - Memory Block Access Control Select for block B
99496  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99497  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99498  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99499  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99500  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99501  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99502  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99503  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99504  */
99505 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK)
99506 
99507 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
99508 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
99509 /*! NSE4 - NonSecure Enable for block B
99510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99513  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99514  */
99515 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK)
99516 
99517 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
99518 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
99519 /*! MBACSEL5 - Memory Block Access Control Select for block B
99520  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99521  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99522  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99523  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99524  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99525  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99526  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99527  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99528  */
99529 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK)
99530 
99531 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
99532 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
99533 /*! NSE5 - NonSecure Enable for block B
99534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99537  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99538  */
99539 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK)
99540 
99541 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
99542 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
99543 /*! MBACSEL6 - Memory Block Access Control Select for block B
99544  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99545  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99546  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99547  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99548  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99549  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99550  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99551  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99552  */
99553 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK)
99554 
99555 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
99556 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
99557 /*! NSE6 - NonSecure Enable for block B
99558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99561  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99562  */
99563 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK)
99564 
99565 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
99566 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
99567 /*! MBACSEL7 - Memory Block Access Control Select for block B
99568  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99569  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99570  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99571  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99572  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99573  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99574  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99575  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99576  */
99577 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK)
99578 
99579 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
99580 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
99581 /*! NSE7 - NonSecure Enable for block B
99582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99585  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99586  */
99587 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK)
99588 /*! @} */
99589 
99590 /* The count of TRDC_MBC_DOM6_MEM3_BLK_CFG_W */
99591 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_COUNT       (2U)
99592 
99593 /* The count of TRDC_MBC_DOM6_MEM3_BLK_CFG_W */
99594 #define TRDC_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2      (3U)
99595 
99596 /*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
99597 /*! @{ */
99598 
99599 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
99600 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
99601 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
99602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99605  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99606  */
99607 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK)
99608 
99609 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
99610 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
99611 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
99612  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99613  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99614  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99615  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99616  */
99617 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK)
99618 
99619 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
99620 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
99621 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
99622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99625  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99626  */
99627 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK)
99628 
99629 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
99630 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
99631 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
99632  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99633  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99634  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99635  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99636  */
99637 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK)
99638 
99639 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
99640 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
99641 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
99642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99645  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99646  */
99647 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK)
99648 
99649 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
99650 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
99651 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
99652  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99653  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99654  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99655  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99656  */
99657 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK)
99658 
99659 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
99660 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
99661 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
99662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99665  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99666  */
99667 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK)
99668 
99669 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
99670 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
99671 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
99672  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99673  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99674  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99675  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99676  */
99677 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK)
99678 
99679 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
99680 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
99681 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
99682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99685  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99686  */
99687 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK)
99688 
99689 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
99690 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
99691 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
99692  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99693  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99694  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99695  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99696  */
99697 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK)
99698 
99699 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
99700 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
99701 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
99702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99705  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99706  */
99707 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK)
99708 
99709 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
99710 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
99711 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
99712  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99713  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99714  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99715  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99716  */
99717 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK)
99718 
99719 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
99720 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
99721 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
99722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99725  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99726  */
99727 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK)
99728 
99729 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
99730 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
99731 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
99732  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99733  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99734  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99735  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99736  */
99737 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK)
99738 
99739 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
99740 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
99741 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
99742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99745  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99746  */
99747 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK)
99748 
99749 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
99750 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
99751 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
99752  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99753  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99754  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99755  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99756  */
99757 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK)
99758 
99759 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
99760 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
99761 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
99762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99765  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99766  */
99767 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK)
99768 
99769 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
99770 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
99771 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
99772  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99773  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99774  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99775  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99776  */
99777 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK)
99778 
99779 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
99780 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
99781 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
99782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99785  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99786  */
99787 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK)
99788 
99789 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
99790 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
99791 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
99792  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99793  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99794  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99795  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99796  */
99797 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK)
99798 
99799 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
99800 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
99801 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
99802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99805  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99806  */
99807 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK)
99808 
99809 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
99810 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
99811 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
99812  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99813  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99814  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99815  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99816  */
99817 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK)
99818 
99819 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
99820 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
99821 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
99822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99825  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99826  */
99827 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK)
99828 
99829 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
99830 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
99831 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
99832  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99833  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99834  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99835  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99836  */
99837 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK)
99838 
99839 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
99840 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
99841 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
99842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99845  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99846  */
99847 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK)
99848 
99849 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
99850 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
99851 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
99852  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99853  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99854  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99855  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99856  */
99857 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK)
99858 
99859 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
99860 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
99861 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
99862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99865  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99866  */
99867 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK)
99868 
99869 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
99870 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
99871 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
99872  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99873  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99874  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99875  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99876  */
99877 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK)
99878 
99879 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
99880 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
99881 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
99882  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99883  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99884  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99885  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99886  */
99887 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK)
99888 
99889 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
99890 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
99891 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
99892  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99893  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99894  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99895  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99896  */
99897 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK)
99898 
99899 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
99900 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
99901 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
99902  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99903  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99904  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99905  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99906  */
99907 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK)
99908 
99909 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
99910 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
99911 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
99912  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
99913  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99914  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99915  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99916  */
99917 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK)
99918 /*! @} */
99919 
99920 /* The count of TRDC_MBC_DOM6_MEM3_BLK_NSE_W */
99921 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_COUNT       (2U)
99922 
99923 /* The count of TRDC_MBC_DOM6_MEM3_BLK_NSE_W */
99924 #define TRDC_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2      (1U)
99925 
99926 /*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
99927 /*! @{ */
99928 
99929 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
99930 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
99931 /*! MBACSEL0 - Memory Block Access Control Select for block B
99932  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99933  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99934  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99935  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99936  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99937  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99938  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99939  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99940  */
99941 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK)
99942 
99943 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
99944 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
99945 /*! NSE0 - NonSecure Enable for block B
99946  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99947  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99948  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99949  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99950  */
99951 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK)
99952 
99953 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
99954 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
99955 /*! MBACSEL1 - Memory Block Access Control Select for block B
99956  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99957  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99958  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99959  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99960  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99961  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99962  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99963  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99964  */
99965 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK)
99966 
99967 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
99968 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
99969 /*! NSE1 - NonSecure Enable for block B
99970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99973  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99974  */
99975 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK)
99976 
99977 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
99978 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
99979 /*! MBACSEL2 - Memory Block Access Control Select for block B
99980  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
99981  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
99982  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
99983  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
99984  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
99985  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
99986  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
99987  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
99988  */
99989 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK)
99990 
99991 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
99992 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
99993 /*! NSE2 - NonSecure Enable for block B
99994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
99995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
99996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
99997  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
99998  */
99999 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK)
100000 
100001 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
100002 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
100003 /*! MBACSEL3 - Memory Block Access Control Select for block B
100004  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100005  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100006  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100007  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100008  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100009  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100010  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100011  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100012  */
100013 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK)
100014 
100015 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
100016 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
100017 /*! NSE3 - NonSecure Enable for block B
100018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100021  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100022  */
100023 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK)
100024 
100025 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
100026 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
100027 /*! MBACSEL4 - Memory Block Access Control Select for block B
100028  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100029  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100030  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100031  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100032  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100033  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100034  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100035  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100036  */
100037 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK)
100038 
100039 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
100040 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
100041 /*! NSE4 - NonSecure Enable for block B
100042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100045  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100046  */
100047 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK)
100048 
100049 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
100050 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
100051 /*! MBACSEL5 - Memory Block Access Control Select for block B
100052  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100053  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100054  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100055  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100056  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100057  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100058  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100059  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100060  */
100061 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK)
100062 
100063 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
100064 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
100065 /*! NSE5 - NonSecure Enable for block B
100066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100069  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100070  */
100071 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK)
100072 
100073 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
100074 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
100075 /*! MBACSEL6 - Memory Block Access Control Select for block B
100076  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100077  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100078  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100079  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100080  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100081  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100082  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100083  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100084  */
100085 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK)
100086 
100087 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
100088 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
100089 /*! NSE6 - NonSecure Enable for block B
100090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100093  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100094  */
100095 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK)
100096 
100097 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
100098 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
100099 /*! MBACSEL7 - Memory Block Access Control Select for block B
100100  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100101  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100102  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100103  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100104  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100105  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100106  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100107  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100108  */
100109 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK)
100110 
100111 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
100112 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
100113 /*! NSE7 - NonSecure Enable for block B
100114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100117  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100118  */
100119 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK)
100120 /*! @} */
100121 
100122 /* The count of TRDC_MBC_DOM7_MEM0_BLK_CFG_W */
100123 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_COUNT       (2U)
100124 
100125 /* The count of TRDC_MBC_DOM7_MEM0_BLK_CFG_W */
100126 #define TRDC_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2      (16U)
100127 
100128 /*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
100129 /*! @{ */
100130 
100131 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
100132 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
100133 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
100134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100137  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100138  */
100139 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK)
100140 
100141 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
100142 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
100143 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
100144  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100145  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100146  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100147  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100148  */
100149 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK)
100150 
100151 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
100152 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
100153 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
100154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100157  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100158  */
100159 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK)
100160 
100161 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
100162 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
100163 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
100164  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100165  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100166  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100167  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100168  */
100169 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK)
100170 
100171 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
100172 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
100173 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
100174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100177  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100178  */
100179 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK)
100180 
100181 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
100182 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
100183 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
100184  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100185  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100186  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100187  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100188  */
100189 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK)
100190 
100191 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
100192 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
100193 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
100194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100197  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100198  */
100199 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK)
100200 
100201 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
100202 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
100203 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
100204  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100205  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100206  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100207  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100208  */
100209 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK)
100210 
100211 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
100212 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
100213 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
100214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100217  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100218  */
100219 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK)
100220 
100221 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
100222 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
100223 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
100224  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100225  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100226  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100227  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100228  */
100229 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK)
100230 
100231 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
100232 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
100233 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
100234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100237  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100238  */
100239 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK)
100240 
100241 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
100242 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
100243 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
100244  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100245  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100246  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100247  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100248  */
100249 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK)
100250 
100251 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
100252 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
100253 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
100254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100257  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100258  */
100259 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK)
100260 
100261 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
100262 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
100263 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
100264  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100265  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100266  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100267  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100268  */
100269 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK)
100270 
100271 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
100272 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
100273 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
100274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100277  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100278  */
100279 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK)
100280 
100281 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
100282 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
100283 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
100284  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100285  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100286  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100287  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100288  */
100289 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK)
100290 
100291 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
100292 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
100293 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
100294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100297  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100298  */
100299 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK)
100300 
100301 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
100302 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
100303 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
100304  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100305  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100306  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100307  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100308  */
100309 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK)
100310 
100311 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
100312 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
100313 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
100314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100317  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100318  */
100319 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK)
100320 
100321 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
100322 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
100323 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
100324  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100325  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100326  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100327  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100328  */
100329 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK)
100330 
100331 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
100332 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
100333 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
100334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100337  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100338  */
100339 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK)
100340 
100341 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
100342 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
100343 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
100344  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100345  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100346  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100347  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100348  */
100349 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK)
100350 
100351 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
100352 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
100353 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
100354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100357  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100358  */
100359 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK)
100360 
100361 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
100362 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
100363 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
100364  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100365  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100366  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100367  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100368  */
100369 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK)
100370 
100371 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
100372 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
100373 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
100374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100377  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100378  */
100379 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK)
100380 
100381 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
100382 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
100383 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
100384  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100385  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100386  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100387  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100388  */
100389 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK)
100390 
100391 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
100392 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
100393 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
100394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100397  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100398  */
100399 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK)
100400 
100401 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
100402 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
100403 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
100404  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100405  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100406  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100407  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100408  */
100409 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK)
100410 
100411 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
100412 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
100413 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
100414  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100415  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100416  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100417  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100418  */
100419 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK)
100420 
100421 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
100422 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
100423 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
100424  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100425  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100426  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100427  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100428  */
100429 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK)
100430 
100431 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
100432 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
100433 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
100434  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100435  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100436  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100437  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100438  */
100439 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK)
100440 
100441 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
100442 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
100443 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
100444  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100445  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100446  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100447  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100448  */
100449 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK)
100450 /*! @} */
100451 
100452 /* The count of TRDC_MBC_DOM7_MEM0_BLK_NSE_W */
100453 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_COUNT       (2U)
100454 
100455 /* The count of TRDC_MBC_DOM7_MEM0_BLK_NSE_W */
100456 #define TRDC_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2      (4U)
100457 
100458 /*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
100459 /*! @{ */
100460 
100461 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
100462 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
100463 /*! MBACSEL0 - Memory Block Access Control Select for block B
100464  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100465  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100466  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100467  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100468  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100469  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100470  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100471  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100472  */
100473 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK)
100474 
100475 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
100476 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
100477 /*! NSE0 - NonSecure Enable for block B
100478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100481  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100482  */
100483 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK)
100484 
100485 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
100486 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
100487 /*! MBACSEL1 - Memory Block Access Control Select for block B
100488  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100489  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100490  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100491  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100492  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100493  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100494  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100495  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100496  */
100497 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK)
100498 
100499 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
100500 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
100501 /*! NSE1 - NonSecure Enable for block B
100502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100505  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100506  */
100507 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK)
100508 
100509 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
100510 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
100511 /*! MBACSEL2 - Memory Block Access Control Select for block B
100512  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100513  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100514  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100515  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100516  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100517  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100518  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100519  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100520  */
100521 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK)
100522 
100523 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
100524 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
100525 /*! NSE2 - NonSecure Enable for block B
100526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100529  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100530  */
100531 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK)
100532 
100533 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
100534 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
100535 /*! MBACSEL3 - Memory Block Access Control Select for block B
100536  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100537  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100538  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100539  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100540  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100541  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100542  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100543  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100544  */
100545 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK)
100546 
100547 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
100548 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
100549 /*! NSE3 - NonSecure Enable for block B
100550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100553  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100554  */
100555 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK)
100556 
100557 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
100558 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
100559 /*! MBACSEL4 - Memory Block Access Control Select for block B
100560  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100561  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100562  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100563  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100564  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100565  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100566  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100567  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100568  */
100569 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK)
100570 
100571 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
100572 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
100573 /*! NSE4 - NonSecure Enable for block B
100574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100577  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100578  */
100579 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK)
100580 
100581 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
100582 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
100583 /*! MBACSEL5 - Memory Block Access Control Select for block B
100584  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100585  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100586  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100587  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100588  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100589  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100590  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100591  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100592  */
100593 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK)
100594 
100595 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
100596 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
100597 /*! NSE5 - NonSecure Enable for block B
100598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100601  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100602  */
100603 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK)
100604 
100605 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
100606 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
100607 /*! MBACSEL6 - Memory Block Access Control Select for block B
100608  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100609  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100610  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100611  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100612  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100613  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100614  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100615  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100616  */
100617 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK)
100618 
100619 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
100620 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
100621 /*! NSE6 - NonSecure Enable for block B
100622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100625  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100626  */
100627 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK)
100628 
100629 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
100630 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
100631 /*! MBACSEL7 - Memory Block Access Control Select for block B
100632  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100633  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100634  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100635  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
100636  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
100637  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
100638  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
100639  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
100640  */
100641 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK)
100642 
100643 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
100644 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
100645 /*! NSE7 - NonSecure Enable for block B
100646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
100647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100649  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100650  */
100651 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK)
100652 /*! @} */
100653 
100654 /* The count of TRDC_MBC_DOM7_MEM1_BLK_CFG_W */
100655 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_COUNT       (2U)
100656 
100657 /* The count of TRDC_MBC_DOM7_MEM1_BLK_CFG_W */
100658 #define TRDC_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2      (4U)
100659 
100660 /*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
100661 /*! @{ */
100662 
100663 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
100664 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
100665 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
100666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100669  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100670  */
100671 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK)
100672 
100673 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
100674 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
100675 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
100676  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100677  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100678  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100679  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100680  */
100681 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK)
100682 
100683 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
100684 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
100685 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
100686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100689  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100690  */
100691 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK)
100692 
100693 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
100694 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
100695 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
100696  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100697  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100698  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100699  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100700  */
100701 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK)
100702 
100703 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
100704 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
100705 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
100706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100709  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100710  */
100711 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK)
100712 
100713 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
100714 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
100715 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
100716  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100717  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100718  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100719  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100720  */
100721 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK)
100722 
100723 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
100724 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
100725 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
100726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100729  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100730  */
100731 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK)
100732 
100733 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
100734 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
100735 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
100736  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100737  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100738  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100739  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100740  */
100741 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK)
100742 
100743 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
100744 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
100745 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
100746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100749  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100750  */
100751 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK)
100752 
100753 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
100754 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
100755 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
100756  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100757  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100758  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100759  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100760  */
100761 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK)
100762 
100763 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
100764 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
100765 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
100766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100769  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100770  */
100771 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK)
100772 
100773 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
100774 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
100775 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
100776  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100777  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100778  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100779  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100780  */
100781 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK)
100782 
100783 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
100784 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
100785 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
100786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100789  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100790  */
100791 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK)
100792 
100793 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
100794 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
100795 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
100796  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100797  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100798  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100799  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100800  */
100801 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK)
100802 
100803 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
100804 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
100805 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
100806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100809  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100810  */
100811 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK)
100812 
100813 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
100814 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
100815 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
100816  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100817  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100818  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100819  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100820  */
100821 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK)
100822 
100823 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
100824 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
100825 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
100826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100829  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100830  */
100831 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK)
100832 
100833 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
100834 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
100835 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
100836  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100837  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100838  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100839  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100840  */
100841 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK)
100842 
100843 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
100844 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
100845 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
100846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100849  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100850  */
100851 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK)
100852 
100853 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
100854 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
100855 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
100856  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100857  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100858  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100859  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100860  */
100861 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK)
100862 
100863 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
100864 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
100865 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
100866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100869  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100870  */
100871 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK)
100872 
100873 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
100874 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
100875 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
100876  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100877  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100878  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100879  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100880  */
100881 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK)
100882 
100883 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
100884 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
100885 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
100886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100889  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100890  */
100891 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK)
100892 
100893 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
100894 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
100895 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
100896  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100897  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100898  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100899  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100900  */
100901 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK)
100902 
100903 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
100904 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
100905 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
100906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100909  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100910  */
100911 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK)
100912 
100913 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
100914 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
100915 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
100916  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100917  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100918  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100919  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100920  */
100921 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK)
100922 
100923 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
100924 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
100925 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
100926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100929  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100930  */
100931 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK)
100932 
100933 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
100934 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
100935 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
100936  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100937  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100938  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100939  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100940  */
100941 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK)
100942 
100943 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
100944 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
100945 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
100946  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100947  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100948  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100949  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100950  */
100951 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK)
100952 
100953 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
100954 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
100955 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
100956  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100957  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100958  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100959  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100960  */
100961 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK)
100962 
100963 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
100964 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
100965 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
100966  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100967  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100968  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100969  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100970  */
100971 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK)
100972 
100973 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
100974 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
100975 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
100976  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
100977  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
100978  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
100979  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
100980  */
100981 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK)
100982 /*! @} */
100983 
100984 /* The count of TRDC_MBC_DOM7_MEM1_BLK_NSE_W */
100985 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_COUNT       (2U)
100986 
100987 /* The count of TRDC_MBC_DOM7_MEM1_BLK_NSE_W */
100988 #define TRDC_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2      (1U)
100989 
100990 /*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
100991 /*! @{ */
100992 
100993 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
100994 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
100995 /*! MBACSEL0 - Memory Block Access Control Select for block B
100996  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
100997  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
100998  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
100999  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101000  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101001  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101002  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101003  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101004  */
101005 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK)
101006 
101007 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
101008 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
101009 /*! NSE0 - NonSecure Enable for block B
101010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101013  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101014  */
101015 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK)
101016 
101017 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
101018 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
101019 /*! MBACSEL1 - Memory Block Access Control Select for block B
101020  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101021  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101022  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101023  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101024  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101025  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101026  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101027  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101028  */
101029 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK)
101030 
101031 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
101032 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
101033 /*! NSE1 - NonSecure Enable for block B
101034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101037  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101038  */
101039 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK)
101040 
101041 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
101042 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
101043 /*! MBACSEL2 - Memory Block Access Control Select for block B
101044  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101045  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101046  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101047  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101048  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101049  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101050  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101051  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101052  */
101053 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK)
101054 
101055 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
101056 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
101057 /*! NSE2 - NonSecure Enable for block B
101058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101061  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101062  */
101063 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK)
101064 
101065 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
101066 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
101067 /*! MBACSEL3 - Memory Block Access Control Select for block B
101068  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101069  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101070  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101071  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101072  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101073  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101074  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101075  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101076  */
101077 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK)
101078 
101079 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
101080 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
101081 /*! NSE3 - NonSecure Enable for block B
101082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101085  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101086  */
101087 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK)
101088 
101089 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
101090 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
101091 /*! MBACSEL4 - Memory Block Access Control Select for block B
101092  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101093  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101094  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101095  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101096  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101097  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101098  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101099  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101100  */
101101 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK)
101102 
101103 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
101104 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
101105 /*! NSE4 - NonSecure Enable for block B
101106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101109  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101110  */
101111 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK)
101112 
101113 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
101114 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
101115 /*! MBACSEL5 - Memory Block Access Control Select for block B
101116  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101117  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101118  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101119  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101120  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101121  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101122  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101123  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101124  */
101125 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK)
101126 
101127 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
101128 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
101129 /*! NSE5 - NonSecure Enable for block B
101130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101133  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101134  */
101135 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK)
101136 
101137 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
101138 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
101139 /*! MBACSEL6 - Memory Block Access Control Select for block B
101140  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101141  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101142  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101143  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101144  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101145  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101146  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101147  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101148  */
101149 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK)
101150 
101151 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
101152 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
101153 /*! NSE6 - NonSecure Enable for block B
101154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101157  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101158  */
101159 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK)
101160 
101161 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
101162 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
101163 /*! MBACSEL7 - Memory Block Access Control Select for block B
101164  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101165  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101166  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101167  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101168  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101169  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101170  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101171  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101172  */
101173 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK)
101174 
101175 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
101176 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
101177 /*! NSE7 - NonSecure Enable for block B
101178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101181  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101182  */
101183 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK)
101184 /*! @} */
101185 
101186 /* The count of TRDC_MBC_DOM7_MEM2_BLK_CFG_W */
101187 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_COUNT       (2U)
101188 
101189 /* The count of TRDC_MBC_DOM7_MEM2_BLK_CFG_W */
101190 #define TRDC_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2      (1U)
101191 
101192 /*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
101193 /*! @{ */
101194 
101195 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
101196 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
101197 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
101198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101201  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101202  */
101203 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK)
101204 
101205 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
101206 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
101207 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
101208  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101209  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101210  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101211  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101212  */
101213 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK)
101214 
101215 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
101216 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
101217 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
101218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101221  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101222  */
101223 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK)
101224 
101225 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
101226 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
101227 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
101228  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101229  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101230  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101231  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101232  */
101233 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK)
101234 
101235 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
101236 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
101237 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
101238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101241  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101242  */
101243 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK)
101244 
101245 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
101246 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
101247 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
101248  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101249  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101250  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101251  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101252  */
101253 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK)
101254 
101255 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
101256 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
101257 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
101258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101261  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101262  */
101263 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK)
101264 
101265 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
101266 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
101267 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
101268  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101269  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101270  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101271  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101272  */
101273 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK)
101274 
101275 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
101276 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
101277 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
101278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101281  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101282  */
101283 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK)
101284 
101285 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
101286 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
101287 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
101288  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101289  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101290  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101291  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101292  */
101293 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK)
101294 
101295 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
101296 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
101297 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
101298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101301  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101302  */
101303 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK)
101304 
101305 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
101306 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
101307 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
101308  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101309  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101310  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101311  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101312  */
101313 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK)
101314 
101315 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
101316 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
101317 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
101318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101321  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101322  */
101323 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK)
101324 
101325 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
101326 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
101327 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
101328  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101329  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101330  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101331  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101332  */
101333 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK)
101334 
101335 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
101336 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
101337 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
101338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101341  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101342  */
101343 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK)
101344 
101345 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
101346 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
101347 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
101348  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101349  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101350  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101351  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101352  */
101353 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK)
101354 
101355 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
101356 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
101357 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
101358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101361  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101362  */
101363 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK)
101364 
101365 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
101366 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
101367 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
101368  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101369  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101370  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101371  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101372  */
101373 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK)
101374 
101375 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
101376 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
101377 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
101378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101381  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101382  */
101383 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK)
101384 
101385 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
101386 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
101387 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
101388  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101389  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101390  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101391  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101392  */
101393 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK)
101394 
101395 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
101396 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
101397 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
101398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101401  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101402  */
101403 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK)
101404 
101405 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
101406 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
101407 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
101408  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101409  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101410  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101411  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101412  */
101413 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK)
101414 
101415 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
101416 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
101417 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
101418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101421  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101422  */
101423 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK)
101424 
101425 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
101426 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
101427 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
101428  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101429  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101430  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101431  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101432  */
101433 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK)
101434 
101435 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
101436 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
101437 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
101438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101441  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101442  */
101443 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK)
101444 
101445 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
101446 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
101447 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
101448  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101449  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101450  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101451  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101452  */
101453 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK)
101454 
101455 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
101456 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
101457 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
101458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101461  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101462  */
101463 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK)
101464 
101465 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
101466 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
101467 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
101468  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101469  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101470  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101471  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101472  */
101473 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK)
101474 
101475 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
101476 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
101477 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
101478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101481  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101482  */
101483 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK)
101484 
101485 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
101486 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
101487 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
101488  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101489  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101490  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101491  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101492  */
101493 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK)
101494 
101495 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
101496 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
101497 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
101498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101501  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101502  */
101503 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK)
101504 
101505 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
101506 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
101507 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
101508  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101509  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101510  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101511  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101512  */
101513 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK)
101514 /*! @} */
101515 
101516 /* The count of TRDC_MBC_DOM7_MEM2_BLK_NSE_W */
101517 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_COUNT       (2U)
101518 
101519 /* The count of TRDC_MBC_DOM7_MEM2_BLK_NSE_W */
101520 #define TRDC_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2      (1U)
101521 
101522 /*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
101523 /*! @{ */
101524 
101525 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
101526 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
101527 /*! MBACSEL0 - Memory Block Access Control Select for block B
101528  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101529  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101530  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101531  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101532  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101533  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101534  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101535  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101536  */
101537 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK)
101538 
101539 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
101540 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
101541 /*! NSE0 - NonSecure Enable for block B
101542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101545  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101546  */
101547 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK)
101548 
101549 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
101550 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
101551 /*! MBACSEL1 - Memory Block Access Control Select for block B
101552  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101553  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101554  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101555  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101556  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101557  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101558  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101559  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101560  */
101561 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK)
101562 
101563 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
101564 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
101565 /*! NSE1 - NonSecure Enable for block B
101566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101569  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101570  */
101571 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK)
101572 
101573 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
101574 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
101575 /*! MBACSEL2 - Memory Block Access Control Select for block B
101576  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101577  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101578  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101579  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101580  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101581  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101582  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101583  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101584  */
101585 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK)
101586 
101587 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
101588 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
101589 /*! NSE2 - NonSecure Enable for block B
101590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101593  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101594  */
101595 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK)
101596 
101597 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
101598 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
101599 /*! MBACSEL3 - Memory Block Access Control Select for block B
101600  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101601  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101602  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101603  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101604  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101605  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101606  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101607  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101608  */
101609 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK)
101610 
101611 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
101612 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
101613 /*! NSE3 - NonSecure Enable for block B
101614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101617  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101618  */
101619 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK)
101620 
101621 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
101622 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
101623 /*! MBACSEL4 - Memory Block Access Control Select for block B
101624  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101625  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101626  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101627  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101628  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101629  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101630  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101631  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101632  */
101633 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK)
101634 
101635 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
101636 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
101637 /*! NSE4 - NonSecure Enable for block B
101638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101641  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101642  */
101643 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK)
101644 
101645 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
101646 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
101647 /*! MBACSEL5 - Memory Block Access Control Select for block B
101648  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101649  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101650  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101651  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101652  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101653  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101654  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101655  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101656  */
101657 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK)
101658 
101659 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
101660 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
101661 /*! NSE5 - NonSecure Enable for block B
101662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101665  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101666  */
101667 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK)
101668 
101669 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
101670 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
101671 /*! MBACSEL6 - Memory Block Access Control Select for block B
101672  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101673  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101674  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101675  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101676  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101677  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101678  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101679  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101680  */
101681 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK)
101682 
101683 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
101684 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
101685 /*! NSE6 - NonSecure Enable for block B
101686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101689  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101690  */
101691 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK)
101692 
101693 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
101694 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
101695 /*! MBACSEL7 - Memory Block Access Control Select for block B
101696  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
101697  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
101698  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
101699  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
101700  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
101701  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
101702  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
101703  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
101704  */
101705 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK)
101706 
101707 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
101708 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
101709 /*! NSE7 - NonSecure Enable for block B
101710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
101711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101713  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101714  */
101715 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK)
101716 /*! @} */
101717 
101718 /* The count of TRDC_MBC_DOM7_MEM3_BLK_CFG_W */
101719 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_COUNT       (2U)
101720 
101721 /* The count of TRDC_MBC_DOM7_MEM3_BLK_CFG_W */
101722 #define TRDC_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2      (3U)
101723 
101724 /*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
101725 /*! @{ */
101726 
101727 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
101728 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
101729 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
101730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101733  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101734  */
101735 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK)
101736 
101737 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
101738 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
101739 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
101740  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101741  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101742  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101743  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101744  */
101745 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK)
101746 
101747 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
101748 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
101749 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
101750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101753  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101754  */
101755 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK)
101756 
101757 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
101758 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
101759 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
101760  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101761  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101762  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101763  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101764  */
101765 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK)
101766 
101767 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
101768 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
101769 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
101770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101774  */
101775 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK)
101776 
101777 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
101778 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
101779 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
101780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101784  */
101785 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK)
101786 
101787 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
101788 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
101789 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
101790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101794  */
101795 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK)
101796 
101797 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
101798 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
101799 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
101800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101804  */
101805 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK)
101806 
101807 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
101808 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
101809 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
101810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101814  */
101815 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK)
101816 
101817 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
101818 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
101819 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
101820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101824  */
101825 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK)
101826 
101827 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
101828 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
101829 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
101830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101834  */
101835 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK)
101836 
101837 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
101838 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
101839 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
101840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101844  */
101845 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK)
101846 
101847 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
101848 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
101849 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
101850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101854  */
101855 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK)
101856 
101857 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
101858 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
101859 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
101860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101864  */
101865 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK)
101866 
101867 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
101868 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
101869 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
101870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101874  */
101875 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK)
101876 
101877 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
101878 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
101879 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
101880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101884  */
101885 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK)
101886 
101887 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
101888 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
101889 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
101890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101894  */
101895 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK)
101896 
101897 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
101898 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
101899 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
101900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101904  */
101905 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK)
101906 
101907 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
101908 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
101909 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
101910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101914  */
101915 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK)
101916 
101917 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
101918 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
101919 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
101920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101924  */
101925 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK)
101926 
101927 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
101928 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
101929 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
101930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101934  */
101935 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK)
101936 
101937 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
101938 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
101939 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
101940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101944  */
101945 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK)
101946 
101947 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
101948 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
101949 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
101950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101954  */
101955 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK)
101956 
101957 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
101958 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
101959 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
101960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101964  */
101965 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK)
101966 
101967 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
101968 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
101969 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
101970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101974  */
101975 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK)
101976 
101977 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
101978 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
101979 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
101980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101984  */
101985 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK)
101986 
101987 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
101988 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
101989 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
101990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
101991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
101992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
101993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
101994  */
101995 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK)
101996 
101997 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
101998 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
101999 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
102000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102004  */
102005 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK)
102006 
102007 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
102008 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
102009 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
102010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102013  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102014  */
102015 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK)
102016 
102017 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
102018 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
102019 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
102020  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102021  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102022  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102023  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102024  */
102025 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK)
102026 
102027 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
102028 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
102029 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
102030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102033  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102034  */
102035 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK)
102036 
102037 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
102038 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
102039 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
102040  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102041  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102042  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102043  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102044  */
102045 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK)
102046 /*! @} */
102047 
102048 /* The count of TRDC_MBC_DOM7_MEM3_BLK_NSE_W */
102049 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_COUNT       (2U)
102050 
102051 /* The count of TRDC_MBC_DOM7_MEM3_BLK_NSE_W */
102052 #define TRDC_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2      (1U)
102053 
102054 /*! @name MBC_DOM8_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
102055 /*! @{ */
102056 
102057 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
102058 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
102059 /*! MBACSEL0 - Memory Block Access Control Select for block B
102060  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102061  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102062  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102063  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102064  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102065  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102066  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102067  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102068  */
102069 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK)
102070 
102071 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
102072 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
102073 /*! NSE0 - NonSecure Enable for block B
102074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102077  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102078  */
102079 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK)
102080 
102081 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
102082 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
102083 /*! MBACSEL1 - Memory Block Access Control Select for block B
102084  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102085  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102086  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102087  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102088  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102089  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102090  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102091  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102092  */
102093 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK)
102094 
102095 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
102096 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
102097 /*! NSE1 - NonSecure Enable for block B
102098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102101  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102102  */
102103 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK)
102104 
102105 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
102106 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
102107 /*! MBACSEL2 - Memory Block Access Control Select for block B
102108  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102109  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102110  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102111  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102112  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102113  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102114  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102115  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102116  */
102117 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK)
102118 
102119 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
102120 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
102121 /*! NSE2 - NonSecure Enable for block B
102122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102125  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102126  */
102127 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK)
102128 
102129 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
102130 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
102131 /*! MBACSEL3 - Memory Block Access Control Select for block B
102132  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102133  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102134  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102135  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102136  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102137  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102138  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102139  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102140  */
102141 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK)
102142 
102143 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
102144 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
102145 /*! NSE3 - NonSecure Enable for block B
102146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102149  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102150  */
102151 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK)
102152 
102153 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
102154 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
102155 /*! MBACSEL4 - Memory Block Access Control Select for block B
102156  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102157  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102158  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102159  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102160  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102161  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102162  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102163  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102164  */
102165 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK)
102166 
102167 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
102168 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
102169 /*! NSE4 - NonSecure Enable for block B
102170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102173  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102174  */
102175 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK)
102176 
102177 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
102178 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
102179 /*! MBACSEL5 - Memory Block Access Control Select for block B
102180  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102181  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102182  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102183  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102184  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102185  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102186  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102187  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102188  */
102189 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK)
102190 
102191 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
102192 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
102193 /*! NSE5 - NonSecure Enable for block B
102194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102197  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102198  */
102199 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK)
102200 
102201 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
102202 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
102203 /*! MBACSEL6 - Memory Block Access Control Select for block B
102204  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102205  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102206  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102207  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102208  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102209  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102210  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102211  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102212  */
102213 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK)
102214 
102215 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
102216 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
102217 /*! NSE6 - NonSecure Enable for block B
102218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102221  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102222  */
102223 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK)
102224 
102225 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
102226 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
102227 /*! MBACSEL7 - Memory Block Access Control Select for block B
102228  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102229  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102230  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102231  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102232  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102233  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102234  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102235  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102236  */
102237 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK)
102238 
102239 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
102240 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
102241 /*! NSE7 - NonSecure Enable for block B
102242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102245  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102246  */
102247 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK)
102248 /*! @} */
102249 
102250 /* The count of TRDC_MBC_DOM8_MEM0_BLK_CFG_W */
102251 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_COUNT       (2U)
102252 
102253 /* The count of TRDC_MBC_DOM8_MEM0_BLK_CFG_W */
102254 #define TRDC_MBC_DOM8_MEM0_BLK_CFG_W_COUNT2      (16U)
102255 
102256 /*! @name MBC_DOM8_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
102257 /*! @{ */
102258 
102259 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
102260 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
102261 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
102262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102265  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102266  */
102267 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK)
102268 
102269 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
102270 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
102271 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
102272  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102273  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102274  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102275  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102276  */
102277 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK)
102278 
102279 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
102280 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
102281 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
102282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102285  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102286  */
102287 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK)
102288 
102289 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
102290 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
102291 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
102292  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102293  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102294  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102295  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102296  */
102297 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK)
102298 
102299 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
102300 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
102301 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
102302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102306  */
102307 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK)
102308 
102309 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
102310 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
102311 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
102312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102316  */
102317 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK)
102318 
102319 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
102320 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
102321 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
102322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102326  */
102327 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK)
102328 
102329 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
102330 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
102331 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
102332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102336  */
102337 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK)
102338 
102339 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
102340 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
102341 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
102342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102346  */
102347 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK)
102348 
102349 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
102350 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
102351 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
102352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102356  */
102357 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK)
102358 
102359 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
102360 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
102361 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
102362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102366  */
102367 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK)
102368 
102369 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
102370 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
102371 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
102372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102376  */
102377 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK)
102378 
102379 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
102380 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
102381 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
102382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102386  */
102387 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK)
102388 
102389 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
102390 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
102391 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
102392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102396  */
102397 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK)
102398 
102399 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
102400 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
102401 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
102402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102406  */
102407 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK)
102408 
102409 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
102410 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
102411 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
102412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102416  */
102417 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK)
102418 
102419 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
102420 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
102421 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
102422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102426  */
102427 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK)
102428 
102429 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
102430 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
102431 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
102432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102436  */
102437 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK)
102438 
102439 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
102440 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
102441 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
102442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102446  */
102447 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK)
102448 
102449 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
102450 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
102451 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
102452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102456  */
102457 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK)
102458 
102459 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
102460 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
102461 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
102462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102466  */
102467 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK)
102468 
102469 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
102470 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
102471 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
102472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102476  */
102477 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK)
102478 
102479 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
102480 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
102481 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
102482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102486  */
102487 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK)
102488 
102489 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
102490 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
102491 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
102492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102496  */
102497 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK)
102498 
102499 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
102500 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
102501 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
102502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102506  */
102507 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK)
102508 
102509 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
102510 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
102511 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
102512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102516  */
102517 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK)
102518 
102519 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
102520 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
102521 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
102522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102526  */
102527 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK)
102528 
102529 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
102530 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
102531 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
102532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102536  */
102537 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK)
102538 
102539 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
102540 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
102541 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
102542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102545  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102546  */
102547 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK)
102548 
102549 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
102550 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
102551 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
102552  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102553  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102554  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102555  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102556  */
102557 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK)
102558 
102559 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
102560 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
102561 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
102562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102565  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102566  */
102567 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK)
102568 
102569 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
102570 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
102571 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
102572  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102573  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102574  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102575  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102576  */
102577 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK)
102578 /*! @} */
102579 
102580 /* The count of TRDC_MBC_DOM8_MEM0_BLK_NSE_W */
102581 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_COUNT       (2U)
102582 
102583 /* The count of TRDC_MBC_DOM8_MEM0_BLK_NSE_W */
102584 #define TRDC_MBC_DOM8_MEM0_BLK_NSE_W_COUNT2      (4U)
102585 
102586 /*! @name MBC_DOM8_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
102587 /*! @{ */
102588 
102589 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
102590 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
102591 /*! MBACSEL0 - Memory Block Access Control Select for block B
102592  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102593  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102594  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102595  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102596  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102597  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102598  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102599  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102600  */
102601 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK)
102602 
102603 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
102604 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
102605 /*! NSE0 - NonSecure Enable for block B
102606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102609  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102610  */
102611 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK)
102612 
102613 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
102614 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
102615 /*! MBACSEL1 - Memory Block Access Control Select for block B
102616  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102617  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102618  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102619  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102620  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102621  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102622  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102623  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102624  */
102625 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK)
102626 
102627 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
102628 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
102629 /*! NSE1 - NonSecure Enable for block B
102630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102633  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102634  */
102635 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK)
102636 
102637 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
102638 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
102639 /*! MBACSEL2 - Memory Block Access Control Select for block B
102640  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102641  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102642  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102643  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102644  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102645  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102646  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102647  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102648  */
102649 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK)
102650 
102651 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
102652 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
102653 /*! NSE2 - NonSecure Enable for block B
102654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102657  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102658  */
102659 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK)
102660 
102661 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
102662 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
102663 /*! MBACSEL3 - Memory Block Access Control Select for block B
102664  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102665  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102666  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102667  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102668  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102669  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102670  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102671  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102672  */
102673 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK)
102674 
102675 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
102676 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
102677 /*! NSE3 - NonSecure Enable for block B
102678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102681  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102682  */
102683 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK)
102684 
102685 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
102686 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
102687 /*! MBACSEL4 - Memory Block Access Control Select for block B
102688  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102689  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102690  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102691  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102692  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102693  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102694  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102695  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102696  */
102697 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK)
102698 
102699 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
102700 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
102701 /*! NSE4 - NonSecure Enable for block B
102702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102705  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102706  */
102707 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK)
102708 
102709 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
102710 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
102711 /*! MBACSEL5 - Memory Block Access Control Select for block B
102712  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102713  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102714  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102715  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102716  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102717  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102718  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102719  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102720  */
102721 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK)
102722 
102723 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
102724 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
102725 /*! NSE5 - NonSecure Enable for block B
102726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102729  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102730  */
102731 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK)
102732 
102733 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
102734 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
102735 /*! MBACSEL6 - Memory Block Access Control Select for block B
102736  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102737  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102738  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102739  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102740  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102741  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102742  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102743  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102744  */
102745 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK)
102746 
102747 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
102748 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
102749 /*! NSE6 - NonSecure Enable for block B
102750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102753  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102754  */
102755 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK)
102756 
102757 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
102758 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
102759 /*! MBACSEL7 - Memory Block Access Control Select for block B
102760  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
102761  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
102762  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
102763  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
102764  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
102765  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
102766  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
102767  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
102768  */
102769 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK)
102770 
102771 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
102772 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
102773 /*! NSE7 - NonSecure Enable for block B
102774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
102775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102777  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102778  */
102779 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK)
102780 /*! @} */
102781 
102782 /* The count of TRDC_MBC_DOM8_MEM1_BLK_CFG_W */
102783 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_COUNT       (2U)
102784 
102785 /* The count of TRDC_MBC_DOM8_MEM1_BLK_CFG_W */
102786 #define TRDC_MBC_DOM8_MEM1_BLK_CFG_W_COUNT2      (4U)
102787 
102788 /*! @name MBC_DOM8_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
102789 /*! @{ */
102790 
102791 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
102792 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
102793 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
102794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102797  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102798  */
102799 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK)
102800 
102801 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
102802 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
102803 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
102804  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102805  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102806  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102807  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102808  */
102809 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK)
102810 
102811 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
102812 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
102813 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
102814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102817  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102818  */
102819 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK)
102820 
102821 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
102822 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
102823 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
102824  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102825  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102826  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102827  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102828  */
102829 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK)
102830 
102831 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
102832 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
102833 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
102834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102838  */
102839 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK)
102840 
102841 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
102842 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
102843 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
102844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102848  */
102849 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK)
102850 
102851 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
102852 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
102853 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
102854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102858  */
102859 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK)
102860 
102861 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
102862 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
102863 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
102864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102868  */
102869 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK)
102870 
102871 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
102872 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
102873 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
102874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102878  */
102879 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK)
102880 
102881 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
102882 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
102883 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
102884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102888  */
102889 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK)
102890 
102891 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
102892 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
102893 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
102894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102898  */
102899 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK)
102900 
102901 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
102902 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
102903 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
102904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102908  */
102909 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK)
102910 
102911 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
102912 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
102913 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
102914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102918  */
102919 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK)
102920 
102921 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
102922 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
102923 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
102924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102928  */
102929 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK)
102930 
102931 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
102932 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
102933 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
102934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102938  */
102939 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK)
102940 
102941 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
102942 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
102943 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
102944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102948  */
102949 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK)
102950 
102951 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
102952 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
102953 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
102954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102958  */
102959 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK)
102960 
102961 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
102962 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
102963 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
102964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102968  */
102969 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK)
102970 
102971 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
102972 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
102973 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
102974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102978  */
102979 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK)
102980 
102981 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
102982 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
102983 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
102984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102988  */
102989 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK)
102990 
102991 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
102992 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
102993 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
102994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
102995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
102996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
102997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
102998  */
102999 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK)
103000 
103001 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
103002 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
103003 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
103004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103008  */
103009 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK)
103010 
103011 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
103012 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
103013 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
103014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103018  */
103019 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK)
103020 
103021 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
103022 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
103023 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
103024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103028  */
103029 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK)
103030 
103031 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
103032 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
103033 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
103034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103038  */
103039 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK)
103040 
103041 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
103042 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
103043 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
103044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103048  */
103049 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK)
103050 
103051 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
103052 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
103053 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
103054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103058  */
103059 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK)
103060 
103061 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
103062 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
103063 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
103064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103068  */
103069 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK)
103070 
103071 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
103072 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
103073 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
103074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103077  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103078  */
103079 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK)
103080 
103081 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
103082 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
103083 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
103084  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103085  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103086  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103087  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103088  */
103089 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK)
103090 
103091 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
103092 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
103093 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
103094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103097  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103098  */
103099 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK)
103100 
103101 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
103102 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
103103 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
103104  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103105  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103106  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103107  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103108  */
103109 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK)
103110 /*! @} */
103111 
103112 /* The count of TRDC_MBC_DOM8_MEM1_BLK_NSE_W */
103113 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_COUNT       (2U)
103114 
103115 /* The count of TRDC_MBC_DOM8_MEM1_BLK_NSE_W */
103116 #define TRDC_MBC_DOM8_MEM1_BLK_NSE_W_COUNT2      (1U)
103117 
103118 /*! @name MBC_DOM8_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
103119 /*! @{ */
103120 
103121 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
103122 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
103123 /*! MBACSEL0 - Memory Block Access Control Select for block B
103124  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103125  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103126  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103127  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103128  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103129  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103130  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103131  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103132  */
103133 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK)
103134 
103135 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
103136 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
103137 /*! NSE0 - NonSecure Enable for block B
103138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103141  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103142  */
103143 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK)
103144 
103145 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
103146 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
103147 /*! MBACSEL1 - Memory Block Access Control Select for block B
103148  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103149  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103150  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103151  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103152  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103153  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103154  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103155  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103156  */
103157 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK)
103158 
103159 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
103160 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
103161 /*! NSE1 - NonSecure Enable for block B
103162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103165  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103166  */
103167 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK)
103168 
103169 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
103170 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
103171 /*! MBACSEL2 - Memory Block Access Control Select for block B
103172  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103173  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103174  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103175  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103176  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103177  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103178  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103179  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103180  */
103181 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK)
103182 
103183 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
103184 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
103185 /*! NSE2 - NonSecure Enable for block B
103186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103189  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103190  */
103191 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK)
103192 
103193 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
103194 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
103195 /*! MBACSEL3 - Memory Block Access Control Select for block B
103196  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103197  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103198  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103199  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103200  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103201  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103202  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103203  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103204  */
103205 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK)
103206 
103207 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
103208 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
103209 /*! NSE3 - NonSecure Enable for block B
103210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103213  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103214  */
103215 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK)
103216 
103217 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
103218 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
103219 /*! MBACSEL4 - Memory Block Access Control Select for block B
103220  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103221  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103222  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103223  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103224  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103225  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103226  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103227  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103228  */
103229 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK)
103230 
103231 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
103232 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
103233 /*! NSE4 - NonSecure Enable for block B
103234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103237  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103238  */
103239 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK)
103240 
103241 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
103242 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
103243 /*! MBACSEL5 - Memory Block Access Control Select for block B
103244  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103245  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103246  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103247  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103248  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103249  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103250  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103251  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103252  */
103253 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK)
103254 
103255 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
103256 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
103257 /*! NSE5 - NonSecure Enable for block B
103258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103261  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103262  */
103263 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK)
103264 
103265 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
103266 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
103267 /*! MBACSEL6 - Memory Block Access Control Select for block B
103268  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103269  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103270  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103271  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103272  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103273  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103274  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103275  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103276  */
103277 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK)
103278 
103279 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
103280 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
103281 /*! NSE6 - NonSecure Enable for block B
103282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103285  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103286  */
103287 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK)
103288 
103289 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
103290 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
103291 /*! MBACSEL7 - Memory Block Access Control Select for block B
103292  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103293  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103294  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103295  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103296  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103297  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103298  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103299  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103300  */
103301 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK)
103302 
103303 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
103304 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
103305 /*! NSE7 - NonSecure Enable for block B
103306  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103307  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103308  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103309  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103310  */
103311 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK)
103312 /*! @} */
103313 
103314 /* The count of TRDC_MBC_DOM8_MEM2_BLK_CFG_W */
103315 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_COUNT       (2U)
103316 
103317 /* The count of TRDC_MBC_DOM8_MEM2_BLK_CFG_W */
103318 #define TRDC_MBC_DOM8_MEM2_BLK_CFG_W_COUNT2      (1U)
103319 
103320 /*! @name MBC_DOM8_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
103321 /*! @{ */
103322 
103323 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
103324 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
103325 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
103326  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103327  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103328  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103329  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103330  */
103331 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK)
103332 
103333 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
103334 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
103335 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
103336  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103337  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103338  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103339  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103340  */
103341 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK)
103342 
103343 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
103344 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
103345 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
103346  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103347  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103348  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103349  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103350  */
103351 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK)
103352 
103353 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
103354 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
103355 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
103356  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103357  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103358  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103359  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103360  */
103361 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK)
103362 
103363 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
103364 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
103365 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
103366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103369  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103370  */
103371 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK)
103372 
103373 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
103374 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
103375 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
103376  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103377  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103378  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103379  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103380  */
103381 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK)
103382 
103383 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
103384 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
103385 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
103386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103389  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103390  */
103391 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK)
103392 
103393 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
103394 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
103395 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
103396  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103397  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103398  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103399  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103400  */
103401 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK)
103402 
103403 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
103404 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
103405 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
103406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103409  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103410  */
103411 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK)
103412 
103413 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
103414 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
103415 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
103416  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103417  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103418  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103419  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103420  */
103421 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK)
103422 
103423 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
103424 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
103425 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
103426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103429  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103430  */
103431 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK)
103432 
103433 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
103434 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
103435 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
103436  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103437  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103438  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103439  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103440  */
103441 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK)
103442 
103443 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
103444 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
103445 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
103446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103449  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103450  */
103451 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK)
103452 
103453 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
103454 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
103455 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
103456  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103457  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103458  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103459  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103460  */
103461 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK)
103462 
103463 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
103464 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
103465 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
103466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103469  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103470  */
103471 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK)
103472 
103473 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
103474 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
103475 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
103476  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103477  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103478  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103479  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103480  */
103481 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK)
103482 
103483 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
103484 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
103485 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
103486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103489  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103490  */
103491 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK)
103492 
103493 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
103494 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
103495 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
103496  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103497  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103498  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103499  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103500  */
103501 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK)
103502 
103503 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
103504 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
103505 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
103506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103509  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103510  */
103511 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK)
103512 
103513 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
103514 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
103515 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
103516  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103517  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103518  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103519  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103520  */
103521 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK)
103522 
103523 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
103524 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
103525 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
103526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103529  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103530  */
103531 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK)
103532 
103533 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
103534 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
103535 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
103536  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103537  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103538  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103539  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103540  */
103541 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK)
103542 
103543 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
103544 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
103545 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
103546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103549  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103550  */
103551 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK)
103552 
103553 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
103554 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
103555 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
103556  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103557  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103558  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103559  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103560  */
103561 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK)
103562 
103563 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
103564 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
103565 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
103566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103569  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103570  */
103571 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK)
103572 
103573 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
103574 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
103575 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
103576  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103577  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103578  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103579  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103580  */
103581 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK)
103582 
103583 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
103584 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
103585 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
103586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103589  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103590  */
103591 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK)
103592 
103593 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
103594 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
103595 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
103596  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103597  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103598  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103599  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103600  */
103601 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK)
103602 
103603 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
103604 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
103605 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
103606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103609  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103610  */
103611 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK)
103612 
103613 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
103614 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
103615 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
103616  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103617  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103618  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103619  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103620  */
103621 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK)
103622 
103623 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
103624 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
103625 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
103626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103629  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103630  */
103631 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK)
103632 
103633 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
103634 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
103635 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
103636  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103637  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103638  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103639  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103640  */
103641 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK)
103642 /*! @} */
103643 
103644 /* The count of TRDC_MBC_DOM8_MEM2_BLK_NSE_W */
103645 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_COUNT       (2U)
103646 
103647 /* The count of TRDC_MBC_DOM8_MEM2_BLK_NSE_W */
103648 #define TRDC_MBC_DOM8_MEM2_BLK_NSE_W_COUNT2      (1U)
103649 
103650 /*! @name MBC_DOM8_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
103651 /*! @{ */
103652 
103653 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
103654 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
103655 /*! MBACSEL0 - Memory Block Access Control Select for block B
103656  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103657  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103658  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103659  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103660  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103661  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103662  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103663  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103664  */
103665 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK)
103666 
103667 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
103668 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
103669 /*! NSE0 - NonSecure Enable for block B
103670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103673  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103674  */
103675 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK)
103676 
103677 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
103678 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
103679 /*! MBACSEL1 - Memory Block Access Control Select for block B
103680  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103681  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103682  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103683  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103684  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103685  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103686  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103687  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103688  */
103689 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK)
103690 
103691 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
103692 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
103693 /*! NSE1 - NonSecure Enable for block B
103694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103697  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103698  */
103699 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK)
103700 
103701 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
103702 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
103703 /*! MBACSEL2 - Memory Block Access Control Select for block B
103704  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103705  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103706  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103707  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103708  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103709  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103710  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103711  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103712  */
103713 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK)
103714 
103715 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
103716 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
103717 /*! NSE2 - NonSecure Enable for block B
103718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103721  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103722  */
103723 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK)
103724 
103725 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
103726 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
103727 /*! MBACSEL3 - Memory Block Access Control Select for block B
103728  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103729  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103730  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103731  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103732  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103733  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103734  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103735  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103736  */
103737 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK)
103738 
103739 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
103740 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
103741 /*! NSE3 - NonSecure Enable for block B
103742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103745  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103746  */
103747 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK)
103748 
103749 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
103750 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
103751 /*! MBACSEL4 - Memory Block Access Control Select for block B
103752  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103753  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103754  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103755  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103756  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103757  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103758  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103759  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103760  */
103761 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK)
103762 
103763 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
103764 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
103765 /*! NSE4 - NonSecure Enable for block B
103766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103769  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103770  */
103771 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK)
103772 
103773 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
103774 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
103775 /*! MBACSEL5 - Memory Block Access Control Select for block B
103776  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103777  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103778  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103779  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103780  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103781  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103782  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103783  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103784  */
103785 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK)
103786 
103787 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
103788 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
103789 /*! NSE5 - NonSecure Enable for block B
103790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103793  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103794  */
103795 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK)
103796 
103797 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
103798 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
103799 /*! MBACSEL6 - Memory Block Access Control Select for block B
103800  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103801  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103802  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103803  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103804  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103805  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103806  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103807  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103808  */
103809 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK)
103810 
103811 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
103812 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
103813 /*! NSE6 - NonSecure Enable for block B
103814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103817  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103818  */
103819 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK)
103820 
103821 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
103822 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
103823 /*! MBACSEL7 - Memory Block Access Control Select for block B
103824  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
103825  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
103826  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
103827  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
103828  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
103829  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
103830  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
103831  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
103832  */
103833 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK)
103834 
103835 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
103836 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
103837 /*! NSE7 - NonSecure Enable for block B
103838  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
103839  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103840  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103841  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103842  */
103843 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK)
103844 /*! @} */
103845 
103846 /* The count of TRDC_MBC_DOM8_MEM3_BLK_CFG_W */
103847 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_COUNT       (2U)
103848 
103849 /* The count of TRDC_MBC_DOM8_MEM3_BLK_CFG_W */
103850 #define TRDC_MBC_DOM8_MEM3_BLK_CFG_W_COUNT2      (3U)
103851 
103852 /*! @name MBC_DOM8_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
103853 /*! @{ */
103854 
103855 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
103856 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
103857 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
103858  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103859  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103860  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103861  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103862  */
103863 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK)
103864 
103865 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
103866 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
103867 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
103868  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103869  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103870  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103871  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103872  */
103873 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK)
103874 
103875 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
103876 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
103877 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
103878  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103879  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103880  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103881  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103882  */
103883 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK)
103884 
103885 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
103886 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
103887 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
103888  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103889  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103890  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103891  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103892  */
103893 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK)
103894 
103895 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
103896 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
103897 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
103898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103901  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103902  */
103903 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK)
103904 
103905 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
103906 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
103907 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
103908  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103909  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103910  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103911  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103912  */
103913 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK)
103914 
103915 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
103916 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
103917 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
103918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103921  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103922  */
103923 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK)
103924 
103925 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
103926 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
103927 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
103928  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103929  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103930  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103931  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103932  */
103933 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK)
103934 
103935 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
103936 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
103937 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
103938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103941  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103942  */
103943 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK)
103944 
103945 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
103946 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
103947 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
103948  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103949  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103950  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103951  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103952  */
103953 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK)
103954 
103955 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
103956 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
103957 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
103958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103961  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103962  */
103963 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK)
103964 
103965 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
103966 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
103967 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
103968  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103969  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103970  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103971  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103972  */
103973 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK)
103974 
103975 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
103976 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
103977 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
103978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103981  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103982  */
103983 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK)
103984 
103985 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
103986 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
103987 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
103988  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103989  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
103990  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
103991  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
103992  */
103993 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK)
103994 
103995 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
103996 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
103997 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
103998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
103999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104001  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104002  */
104003 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK)
104004 
104005 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
104006 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
104007 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
104008  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104009  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104010  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104011  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104012  */
104013 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK)
104014 
104015 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
104016 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
104017 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
104018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104021  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104022  */
104023 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK)
104024 
104025 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
104026 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
104027 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
104028  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104029  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104030  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104031  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104032  */
104033 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK)
104034 
104035 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
104036 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
104037 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
104038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104041  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104042  */
104043 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK)
104044 
104045 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
104046 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
104047 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
104048  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104049  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104050  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104051  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104052  */
104053 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK)
104054 
104055 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
104056 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
104057 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
104058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104061  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104062  */
104063 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK)
104064 
104065 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
104066 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
104067 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
104068  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104069  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104070  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104071  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104072  */
104073 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK)
104074 
104075 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
104076 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
104077 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
104078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104081  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104082  */
104083 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK)
104084 
104085 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
104086 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
104087 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
104088  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104089  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104090  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104091  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104092  */
104093 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK)
104094 
104095 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
104096 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
104097 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
104098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104101  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104102  */
104103 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK)
104104 
104105 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
104106 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
104107 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
104108  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104109  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104110  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104111  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104112  */
104113 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK)
104114 
104115 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
104116 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
104117 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
104118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104121  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104122  */
104123 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK)
104124 
104125 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
104126 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
104127 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
104128  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104129  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104130  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104131  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104132  */
104133 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK)
104134 
104135 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
104136 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
104137 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
104138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104141  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104142  */
104143 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK)
104144 
104145 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
104146 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
104147 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
104148  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104149  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104150  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104151  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104152  */
104153 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK)
104154 
104155 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
104156 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
104157 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
104158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104161  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104162  */
104163 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK)
104164 
104165 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
104166 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
104167 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
104168  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104169  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104170  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104171  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104172  */
104173 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK)
104174 /*! @} */
104175 
104176 /* The count of TRDC_MBC_DOM8_MEM3_BLK_NSE_W */
104177 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_COUNT       (2U)
104178 
104179 /* The count of TRDC_MBC_DOM8_MEM3_BLK_NSE_W */
104180 #define TRDC_MBC_DOM8_MEM3_BLK_NSE_W_COUNT2      (1U)
104181 
104182 /*! @name MBC_DOM9_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
104183 /*! @{ */
104184 
104185 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
104186 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
104187 /*! MBACSEL0 - Memory Block Access Control Select for block B
104188  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104189  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104190  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104191  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104192  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104193  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104194  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104195  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104196  */
104197 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK)
104198 
104199 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
104200 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
104201 /*! NSE0 - NonSecure Enable for block B
104202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104205  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104206  */
104207 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK)
104208 
104209 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
104210 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
104211 /*! MBACSEL1 - Memory Block Access Control Select for block B
104212  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104213  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104214  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104215  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104216  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104217  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104218  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104219  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104220  */
104221 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK)
104222 
104223 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
104224 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
104225 /*! NSE1 - NonSecure Enable for block B
104226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104229  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104230  */
104231 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK)
104232 
104233 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
104234 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
104235 /*! MBACSEL2 - Memory Block Access Control Select for block B
104236  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104237  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104238  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104239  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104240  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104241  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104242  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104243  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104244  */
104245 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK)
104246 
104247 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
104248 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
104249 /*! NSE2 - NonSecure Enable for block B
104250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104253  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104254  */
104255 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK)
104256 
104257 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
104258 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
104259 /*! MBACSEL3 - Memory Block Access Control Select for block B
104260  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104261  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104262  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104263  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104264  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104265  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104266  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104267  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104268  */
104269 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK)
104270 
104271 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
104272 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
104273 /*! NSE3 - NonSecure Enable for block B
104274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104277  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104278  */
104279 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK)
104280 
104281 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
104282 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
104283 /*! MBACSEL4 - Memory Block Access Control Select for block B
104284  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104285  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104286  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104287  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104288  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104289  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104290  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104291  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104292  */
104293 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK)
104294 
104295 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
104296 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
104297 /*! NSE4 - NonSecure Enable for block B
104298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104301  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104302  */
104303 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK)
104304 
104305 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
104306 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
104307 /*! MBACSEL5 - Memory Block Access Control Select for block B
104308  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104309  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104310  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104311  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104312  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104313  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104314  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104315  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104316  */
104317 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK)
104318 
104319 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
104320 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
104321 /*! NSE5 - NonSecure Enable for block B
104322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104325  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104326  */
104327 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK)
104328 
104329 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
104330 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
104331 /*! MBACSEL6 - Memory Block Access Control Select for block B
104332  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104333  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104334  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104335  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104336  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104337  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104338  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104339  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104340  */
104341 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK)
104342 
104343 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
104344 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
104345 /*! NSE6 - NonSecure Enable for block B
104346  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104347  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104348  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104349  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104350  */
104351 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK)
104352 
104353 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
104354 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
104355 /*! MBACSEL7 - Memory Block Access Control Select for block B
104356  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104357  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104358  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104359  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104360  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104361  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104362  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104363  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104364  */
104365 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK)
104366 
104367 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
104368 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
104369 /*! NSE7 - NonSecure Enable for block B
104370  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104371  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104372  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104373  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104374  */
104375 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK)
104376 /*! @} */
104377 
104378 /* The count of TRDC_MBC_DOM9_MEM0_BLK_CFG_W */
104379 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_COUNT       (2U)
104380 
104381 /* The count of TRDC_MBC_DOM9_MEM0_BLK_CFG_W */
104382 #define TRDC_MBC_DOM9_MEM0_BLK_CFG_W_COUNT2      (16U)
104383 
104384 /*! @name MBC_DOM9_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
104385 /*! @{ */
104386 
104387 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
104388 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
104389 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
104390  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104391  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104392  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104393  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104394  */
104395 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK)
104396 
104397 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
104398 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
104399 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
104400  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104401  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104402  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104403  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104404  */
104405 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK)
104406 
104407 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
104408 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
104409 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
104410  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104411  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104412  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104413  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104414  */
104415 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK)
104416 
104417 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
104418 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
104419 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
104420  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104421  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104422  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104423  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104424  */
104425 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK)
104426 
104427 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
104428 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
104429 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
104430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104433  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104434  */
104435 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK)
104436 
104437 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
104438 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
104439 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
104440  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104441  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104442  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104443  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104444  */
104445 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK)
104446 
104447 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
104448 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
104449 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
104450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104453  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104454  */
104455 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK)
104456 
104457 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
104458 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
104459 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
104460  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104461  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104462  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104463  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104464  */
104465 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK)
104466 
104467 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
104468 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
104469 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
104470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104473  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104474  */
104475 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK)
104476 
104477 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
104478 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
104479 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
104480  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104481  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104482  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104483  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104484  */
104485 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK)
104486 
104487 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
104488 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
104489 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
104490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104493  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104494  */
104495 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK)
104496 
104497 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
104498 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
104499 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
104500  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104501  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104502  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104503  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104504  */
104505 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK)
104506 
104507 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
104508 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
104509 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
104510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104513  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104514  */
104515 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK)
104516 
104517 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
104518 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
104519 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
104520  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104521  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104522  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104523  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104524  */
104525 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK)
104526 
104527 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
104528 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
104529 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
104530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104533  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104534  */
104535 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK)
104536 
104537 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
104538 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
104539 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
104540  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104541  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104542  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104543  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104544  */
104545 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK)
104546 
104547 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
104548 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
104549 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
104550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104553  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104554  */
104555 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK)
104556 
104557 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
104558 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
104559 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
104560  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104561  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104562  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104563  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104564  */
104565 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK)
104566 
104567 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
104568 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
104569 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
104570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104573  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104574  */
104575 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK)
104576 
104577 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
104578 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
104579 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
104580  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104581  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104582  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104583  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104584  */
104585 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK)
104586 
104587 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
104588 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
104589 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
104590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104593  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104594  */
104595 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK)
104596 
104597 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
104598 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
104599 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
104600  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104601  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104602  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104603  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104604  */
104605 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK)
104606 
104607 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
104608 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
104609 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
104610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104613  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104614  */
104615 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK)
104616 
104617 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
104618 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
104619 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
104620  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104621  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104622  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104623  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104624  */
104625 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK)
104626 
104627 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
104628 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
104629 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
104630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104633  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104634  */
104635 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK)
104636 
104637 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
104638 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
104639 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
104640  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104641  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104642  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104643  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104644  */
104645 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK)
104646 
104647 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
104648 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
104649 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
104650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104653  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104654  */
104655 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK)
104656 
104657 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
104658 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
104659 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
104660  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104661  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104662  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104663  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104664  */
104665 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK)
104666 
104667 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
104668 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
104669 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
104670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104673  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104674  */
104675 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK)
104676 
104677 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
104678 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
104679 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
104680  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104681  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104682  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104683  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104684  */
104685 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK)
104686 
104687 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
104688 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
104689 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
104690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104693  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104694  */
104695 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK)
104696 
104697 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
104698 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
104699 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
104700  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104701  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104702  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104703  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104704  */
104705 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK)
104706 /*! @} */
104707 
104708 /* The count of TRDC_MBC_DOM9_MEM0_BLK_NSE_W */
104709 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_COUNT       (2U)
104710 
104711 /* The count of TRDC_MBC_DOM9_MEM0_BLK_NSE_W */
104712 #define TRDC_MBC_DOM9_MEM0_BLK_NSE_W_COUNT2      (4U)
104713 
104714 /*! @name MBC_DOM9_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
104715 /*! @{ */
104716 
104717 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
104718 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
104719 /*! MBACSEL0 - Memory Block Access Control Select for block B
104720  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104721  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104722  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104723  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104724  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104725  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104726  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104727  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104728  */
104729 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK)
104730 
104731 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
104732 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
104733 /*! NSE0 - NonSecure Enable for block B
104734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104737  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104738  */
104739 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK)
104740 
104741 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
104742 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
104743 /*! MBACSEL1 - Memory Block Access Control Select for block B
104744  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104745  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104746  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104747  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104748  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104749  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104750  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104751  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104752  */
104753 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK)
104754 
104755 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
104756 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
104757 /*! NSE1 - NonSecure Enable for block B
104758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104761  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104762  */
104763 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK)
104764 
104765 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
104766 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
104767 /*! MBACSEL2 - Memory Block Access Control Select for block B
104768  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104769  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104770  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104771  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104772  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104773  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104774  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104775  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104776  */
104777 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK)
104778 
104779 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
104780 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
104781 /*! NSE2 - NonSecure Enable for block B
104782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104785  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104786  */
104787 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK)
104788 
104789 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
104790 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
104791 /*! MBACSEL3 - Memory Block Access Control Select for block B
104792  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104793  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104794  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104795  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104796  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104797  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104798  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104799  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104800  */
104801 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK)
104802 
104803 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
104804 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
104805 /*! NSE3 - NonSecure Enable for block B
104806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104809  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104810  */
104811 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK)
104812 
104813 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
104814 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
104815 /*! MBACSEL4 - Memory Block Access Control Select for block B
104816  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104817  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104818  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104819  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104820  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104821  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104822  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104823  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104824  */
104825 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK)
104826 
104827 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
104828 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
104829 /*! NSE4 - NonSecure Enable for block B
104830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104833  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104834  */
104835 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK)
104836 
104837 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
104838 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
104839 /*! MBACSEL5 - Memory Block Access Control Select for block B
104840  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104841  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104842  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104843  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104844  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104845  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104846  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104847  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104848  */
104849 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK)
104850 
104851 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
104852 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
104853 /*! NSE5 - NonSecure Enable for block B
104854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104857  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104858  */
104859 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK)
104860 
104861 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
104862 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
104863 /*! MBACSEL6 - Memory Block Access Control Select for block B
104864  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104865  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104866  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104867  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104868  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104869  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104870  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104871  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104872  */
104873 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK)
104874 
104875 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
104876 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
104877 /*! NSE6 - NonSecure Enable for block B
104878  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104879  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104880  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104881  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104882  */
104883 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK)
104884 
104885 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
104886 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
104887 /*! MBACSEL7 - Memory Block Access Control Select for block B
104888  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
104889  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
104890  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
104891  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
104892  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
104893  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
104894  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
104895  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
104896  */
104897 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK)
104898 
104899 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
104900 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
104901 /*! NSE7 - NonSecure Enable for block B
104902  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
104903  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104904  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104905  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104906  */
104907 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK)
104908 /*! @} */
104909 
104910 /* The count of TRDC_MBC_DOM9_MEM1_BLK_CFG_W */
104911 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_COUNT       (2U)
104912 
104913 /* The count of TRDC_MBC_DOM9_MEM1_BLK_CFG_W */
104914 #define TRDC_MBC_DOM9_MEM1_BLK_CFG_W_COUNT2      (4U)
104915 
104916 /*! @name MBC_DOM9_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
104917 /*! @{ */
104918 
104919 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
104920 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
104921 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
104922  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104923  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104924  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104925  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104926  */
104927 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK)
104928 
104929 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
104930 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
104931 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
104932  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104933  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104934  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104935  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104936  */
104937 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK)
104938 
104939 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
104940 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
104941 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
104942  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104943  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104944  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104945  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104946  */
104947 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK)
104948 
104949 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
104950 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
104951 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
104952  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104953  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104954  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104955  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104956  */
104957 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK)
104958 
104959 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
104960 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
104961 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
104962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104965  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104966  */
104967 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK)
104968 
104969 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
104970 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
104971 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
104972  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104973  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104974  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104975  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104976  */
104977 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK)
104978 
104979 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
104980 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
104981 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
104982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104985  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104986  */
104987 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK)
104988 
104989 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
104990 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
104991 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
104992  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
104993  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
104994  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
104995  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
104996  */
104997 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK)
104998 
104999 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
105000 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
105001 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
105002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105005  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105006  */
105007 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK)
105008 
105009 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
105010 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
105011 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
105012  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105013  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105014  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105015  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105016  */
105017 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK)
105018 
105019 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
105020 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
105021 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
105022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105025  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105026  */
105027 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK)
105028 
105029 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
105030 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
105031 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
105032  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105033  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105034  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105035  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105036  */
105037 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK)
105038 
105039 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
105040 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
105041 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
105042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105045  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105046  */
105047 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK)
105048 
105049 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
105050 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
105051 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
105052  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105053  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105054  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105055  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105056  */
105057 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK)
105058 
105059 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
105060 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
105061 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
105062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105065  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105066  */
105067 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK)
105068 
105069 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
105070 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
105071 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
105072  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105073  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105074  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105075  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105076  */
105077 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK)
105078 
105079 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
105080 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
105081 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
105082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105085  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105086  */
105087 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK)
105088 
105089 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
105090 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
105091 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
105092  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105093  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105094  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105095  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105096  */
105097 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK)
105098 
105099 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
105100 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
105101 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
105102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105105  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105106  */
105107 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK)
105108 
105109 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
105110 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
105111 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
105112  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105113  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105114  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105115  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105116  */
105117 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK)
105118 
105119 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
105120 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
105121 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
105122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105125  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105126  */
105127 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK)
105128 
105129 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
105130 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
105131 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
105132  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105133  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105134  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105135  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105136  */
105137 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK)
105138 
105139 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
105140 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
105141 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
105142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105145  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105146  */
105147 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK)
105148 
105149 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
105150 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
105151 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
105152  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105153  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105154  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105155  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105156  */
105157 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK)
105158 
105159 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
105160 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
105161 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
105162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105165  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105166  */
105167 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK)
105168 
105169 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
105170 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
105171 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
105172  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105173  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105174  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105175  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105176  */
105177 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK)
105178 
105179 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
105180 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
105181 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
105182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105185  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105186  */
105187 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK)
105188 
105189 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
105190 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
105191 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
105192  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105193  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105194  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105195  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105196  */
105197 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK)
105198 
105199 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
105200 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
105201 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
105202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105205  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105206  */
105207 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK)
105208 
105209 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
105210 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
105211 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
105212  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105213  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105214  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105215  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105216  */
105217 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK)
105218 
105219 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
105220 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
105221 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
105222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105225  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105226  */
105227 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK)
105228 
105229 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
105230 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
105231 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
105232  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105233  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105234  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105235  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105236  */
105237 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK)
105238 /*! @} */
105239 
105240 /* The count of TRDC_MBC_DOM9_MEM1_BLK_NSE_W */
105241 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_COUNT       (2U)
105242 
105243 /* The count of TRDC_MBC_DOM9_MEM1_BLK_NSE_W */
105244 #define TRDC_MBC_DOM9_MEM1_BLK_NSE_W_COUNT2      (1U)
105245 
105246 /*! @name MBC_DOM9_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
105247 /*! @{ */
105248 
105249 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
105250 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
105251 /*! MBACSEL0 - Memory Block Access Control Select for block B
105252  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105253  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105254  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105255  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105256  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105257  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105258  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105259  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105260  */
105261 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK)
105262 
105263 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
105264 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
105265 /*! NSE0 - NonSecure Enable for block B
105266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105269  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105270  */
105271 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK)
105272 
105273 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
105274 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
105275 /*! MBACSEL1 - Memory Block Access Control Select for block B
105276  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105277  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105278  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105279  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105280  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105281  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105282  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105283  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105284  */
105285 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK)
105286 
105287 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
105288 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
105289 /*! NSE1 - NonSecure Enable for block B
105290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105293  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105294  */
105295 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK)
105296 
105297 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
105298 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
105299 /*! MBACSEL2 - Memory Block Access Control Select for block B
105300  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105301  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105302  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105303  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105304  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105305  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105306  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105307  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105308  */
105309 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK)
105310 
105311 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
105312 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
105313 /*! NSE2 - NonSecure Enable for block B
105314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105317  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105318  */
105319 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK)
105320 
105321 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
105322 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
105323 /*! MBACSEL3 - Memory Block Access Control Select for block B
105324  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105325  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105326  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105327  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105328  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105329  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105330  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105331  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105332  */
105333 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK)
105334 
105335 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
105336 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
105337 /*! NSE3 - NonSecure Enable for block B
105338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105341  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105342  */
105343 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK)
105344 
105345 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
105346 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
105347 /*! MBACSEL4 - Memory Block Access Control Select for block B
105348  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105349  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105350  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105351  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105352  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105353  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105354  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105355  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105356  */
105357 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK)
105358 
105359 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
105360 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
105361 /*! NSE4 - NonSecure Enable for block B
105362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105365  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105366  */
105367 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK)
105368 
105369 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
105370 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
105371 /*! MBACSEL5 - Memory Block Access Control Select for block B
105372  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105373  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105374  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105375  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105376  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105377  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105378  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105379  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105380  */
105381 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK)
105382 
105383 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
105384 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
105385 /*! NSE5 - NonSecure Enable for block B
105386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105389  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105390  */
105391 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK)
105392 
105393 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
105394 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
105395 /*! MBACSEL6 - Memory Block Access Control Select for block B
105396  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105397  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105398  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105399  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105400  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105401  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105402  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105403  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105404  */
105405 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK)
105406 
105407 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
105408 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
105409 /*! NSE6 - NonSecure Enable for block B
105410  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105411  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105412  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105413  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105414  */
105415 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK)
105416 
105417 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
105418 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
105419 /*! MBACSEL7 - Memory Block Access Control Select for block B
105420  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105421  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105422  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105423  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105424  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105425  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105426  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105427  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105428  */
105429 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK)
105430 
105431 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
105432 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
105433 /*! NSE7 - NonSecure Enable for block B
105434  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105435  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105436  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105437  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105438  */
105439 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK)
105440 /*! @} */
105441 
105442 /* The count of TRDC_MBC_DOM9_MEM2_BLK_CFG_W */
105443 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_COUNT       (2U)
105444 
105445 /* The count of TRDC_MBC_DOM9_MEM2_BLK_CFG_W */
105446 #define TRDC_MBC_DOM9_MEM2_BLK_CFG_W_COUNT2      (1U)
105447 
105448 /*! @name MBC_DOM9_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
105449 /*! @{ */
105450 
105451 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
105452 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
105453 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
105454  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105455  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105456  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105457  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105458  */
105459 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK)
105460 
105461 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
105462 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
105463 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
105464  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105465  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105466  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105467  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105468  */
105469 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK)
105470 
105471 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
105472 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
105473 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
105474  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105475  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105476  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105477  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105478  */
105479 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK)
105480 
105481 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
105482 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
105483 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
105484  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105485  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105486  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105487  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105488  */
105489 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK)
105490 
105491 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
105492 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
105493 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
105494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105497  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105498  */
105499 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK)
105500 
105501 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
105502 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
105503 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
105504  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105505  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105506  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105507  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105508  */
105509 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK)
105510 
105511 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
105512 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
105513 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
105514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105517  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105518  */
105519 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK)
105520 
105521 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
105522 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
105523 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
105524  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105525  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105526  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105527  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105528  */
105529 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK)
105530 
105531 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
105532 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
105533 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
105534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105537  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105538  */
105539 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK)
105540 
105541 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
105542 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
105543 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
105544  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105545  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105546  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105547  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105548  */
105549 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK)
105550 
105551 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
105552 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
105553 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
105554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105557  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105558  */
105559 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK)
105560 
105561 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
105562 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
105563 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
105564  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105565  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105566  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105567  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105568  */
105569 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK)
105570 
105571 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
105572 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
105573 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
105574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105577  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105578  */
105579 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK)
105580 
105581 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
105582 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
105583 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
105584  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105585  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105586  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105587  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105588  */
105589 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK)
105590 
105591 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
105592 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
105593 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
105594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105597  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105598  */
105599 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK)
105600 
105601 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
105602 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
105603 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
105604  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105605  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105606  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105607  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105608  */
105609 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK)
105610 
105611 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
105612 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
105613 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
105614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105617  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105618  */
105619 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK)
105620 
105621 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
105622 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
105623 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
105624  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105625  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105626  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105627  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105628  */
105629 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK)
105630 
105631 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
105632 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
105633 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
105634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105637  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105638  */
105639 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK)
105640 
105641 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
105642 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
105643 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
105644  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105645  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105646  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105647  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105648  */
105649 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK)
105650 
105651 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
105652 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
105653 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
105654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105657  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105658  */
105659 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK)
105660 
105661 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
105662 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
105663 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
105664  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105665  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105666  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105667  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105668  */
105669 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK)
105670 
105671 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
105672 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
105673 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
105674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105677  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105678  */
105679 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK)
105680 
105681 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
105682 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
105683 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
105684  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105685  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105686  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105687  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105688  */
105689 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK)
105690 
105691 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
105692 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
105693 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
105694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105697  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105698  */
105699 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK)
105700 
105701 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
105702 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
105703 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
105704  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105705  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105706  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105707  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105708  */
105709 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK)
105710 
105711 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
105712 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
105713 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
105714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105717  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105718  */
105719 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK)
105720 
105721 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
105722 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
105723 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
105724  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105725  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105726  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105727  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105728  */
105729 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK)
105730 
105731 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
105732 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
105733 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
105734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105737  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105738  */
105739 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK)
105740 
105741 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
105742 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
105743 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
105744  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105745  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105746  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105747  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105748  */
105749 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK)
105750 
105751 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
105752 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
105753 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
105754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105757  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105758  */
105759 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK)
105760 
105761 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
105762 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
105763 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
105764  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105765  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105766  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105767  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105768  */
105769 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK)
105770 /*! @} */
105771 
105772 /* The count of TRDC_MBC_DOM9_MEM2_BLK_NSE_W */
105773 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_COUNT       (2U)
105774 
105775 /* The count of TRDC_MBC_DOM9_MEM2_BLK_NSE_W */
105776 #define TRDC_MBC_DOM9_MEM2_BLK_NSE_W_COUNT2      (1U)
105777 
105778 /*! @name MBC_DOM9_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
105779 /*! @{ */
105780 
105781 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
105782 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
105783 /*! MBACSEL0 - Memory Block Access Control Select for block B
105784  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105785  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105786  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105787  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105788  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105789  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105790  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105791  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105792  */
105793 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK)
105794 
105795 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
105796 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
105797 /*! NSE0 - NonSecure Enable for block B
105798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105801  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105802  */
105803 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK)
105804 
105805 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
105806 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
105807 /*! MBACSEL1 - Memory Block Access Control Select for block B
105808  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105809  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105810  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105811  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105812  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105813  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105814  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105815  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105816  */
105817 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK)
105818 
105819 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
105820 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
105821 /*! NSE1 - NonSecure Enable for block B
105822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105825  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105826  */
105827 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK)
105828 
105829 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
105830 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
105831 /*! MBACSEL2 - Memory Block Access Control Select for block B
105832  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105833  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105834  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105835  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105836  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105837  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105838  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105839  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105840  */
105841 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK)
105842 
105843 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
105844 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
105845 /*! NSE2 - NonSecure Enable for block B
105846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105849  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105850  */
105851 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK)
105852 
105853 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
105854 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
105855 /*! MBACSEL3 - Memory Block Access Control Select for block B
105856  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105857  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105858  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105859  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105860  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105861  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105862  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105863  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105864  */
105865 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK)
105866 
105867 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
105868 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
105869 /*! NSE3 - NonSecure Enable for block B
105870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105873  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105874  */
105875 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK)
105876 
105877 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
105878 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
105879 /*! MBACSEL4 - Memory Block Access Control Select for block B
105880  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105881  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105882  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105883  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105884  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105885  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105886  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105887  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105888  */
105889 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK)
105890 
105891 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
105892 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
105893 /*! NSE4 - NonSecure Enable for block B
105894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105897  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105898  */
105899 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK)
105900 
105901 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
105902 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
105903 /*! MBACSEL5 - Memory Block Access Control Select for block B
105904  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105905  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105906  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105907  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105908  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105909  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105910  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105911  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105912  */
105913 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK)
105914 
105915 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
105916 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
105917 /*! NSE5 - NonSecure Enable for block B
105918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105921  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105922  */
105923 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK)
105924 
105925 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
105926 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
105927 /*! MBACSEL6 - Memory Block Access Control Select for block B
105928  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105929  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105930  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105931  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105932  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105933  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105934  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105935  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105936  */
105937 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK)
105938 
105939 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
105940 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
105941 /*! NSE6 - NonSecure Enable for block B
105942  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105943  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105944  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105945  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105946  */
105947 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK)
105948 
105949 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
105950 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
105951 /*! MBACSEL7 - Memory Block Access Control Select for block B
105952  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
105953  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
105954  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
105955  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
105956  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
105957  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
105958  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
105959  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
105960  */
105961 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK)
105962 
105963 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
105964 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
105965 /*! NSE7 - NonSecure Enable for block B
105966  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
105967  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105968  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105969  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105970  */
105971 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK)
105972 /*! @} */
105973 
105974 /* The count of TRDC_MBC_DOM9_MEM3_BLK_CFG_W */
105975 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_COUNT       (2U)
105976 
105977 /* The count of TRDC_MBC_DOM9_MEM3_BLK_CFG_W */
105978 #define TRDC_MBC_DOM9_MEM3_BLK_CFG_W_COUNT2      (3U)
105979 
105980 /*! @name MBC_DOM9_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
105981 /*! @{ */
105982 
105983 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
105984 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
105985 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
105986  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105987  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105988  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105989  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
105990  */
105991 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK)
105992 
105993 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
105994 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
105995 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
105996  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
105997  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
105998  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
105999  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106000  */
106001 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK)
106002 
106003 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
106004 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
106005 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
106006  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106007  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106008  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106009  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106010  */
106011 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK)
106012 
106013 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
106014 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
106015 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
106016  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106017  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106018  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106019  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106020  */
106021 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK)
106022 
106023 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
106024 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
106025 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
106026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106029  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106030  */
106031 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK)
106032 
106033 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
106034 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
106035 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
106036  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106037  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106038  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106039  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106040  */
106041 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK)
106042 
106043 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
106044 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
106045 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
106046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106049  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106050  */
106051 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK)
106052 
106053 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
106054 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
106055 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
106056  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106057  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106058  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106059  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106060  */
106061 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK)
106062 
106063 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
106064 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
106065 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
106066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106069  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106070  */
106071 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK)
106072 
106073 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
106074 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
106075 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
106076  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106077  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106078  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106079  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106080  */
106081 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK)
106082 
106083 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
106084 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
106085 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
106086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106089  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106090  */
106091 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK)
106092 
106093 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
106094 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
106095 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
106096  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106097  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106098  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106099  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106100  */
106101 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK)
106102 
106103 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
106104 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
106105 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
106106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106109  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106110  */
106111 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK)
106112 
106113 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
106114 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
106115 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
106116  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106117  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106118  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106119  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106120  */
106121 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK)
106122 
106123 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
106124 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
106125 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
106126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106129  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106130  */
106131 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK)
106132 
106133 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
106134 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
106135 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
106136  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106137  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106138  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106139  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106140  */
106141 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK)
106142 
106143 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
106144 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
106145 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
106146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106149  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106150  */
106151 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK)
106152 
106153 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
106154 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
106155 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
106156  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106157  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106158  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106159  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106160  */
106161 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK)
106162 
106163 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
106164 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
106165 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
106166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106169  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106170  */
106171 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK)
106172 
106173 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
106174 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
106175 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
106176  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106177  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106178  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106179  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106180  */
106181 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK)
106182 
106183 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
106184 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
106185 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
106186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106189  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106190  */
106191 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK)
106192 
106193 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
106194 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
106195 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
106196  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106197  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106198  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106199  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106200  */
106201 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK)
106202 
106203 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
106204 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
106205 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
106206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106209  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106210  */
106211 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK)
106212 
106213 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
106214 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
106215 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
106216  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106217  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106218  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106219  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106220  */
106221 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK)
106222 
106223 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
106224 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
106225 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
106226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106229  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106230  */
106231 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK)
106232 
106233 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
106234 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
106235 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
106236  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106237  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106238  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106239  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106240  */
106241 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK)
106242 
106243 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
106244 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
106245 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
106246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106249  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106250  */
106251 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK)
106252 
106253 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
106254 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
106255 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
106256  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106257  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106258  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106259  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106260  */
106261 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK)
106262 
106263 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
106264 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
106265 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
106266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106269  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106270  */
106271 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK)
106272 
106273 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
106274 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
106275 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
106276  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106277  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106278  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106279  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106280  */
106281 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK)
106282 
106283 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
106284 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
106285 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
106286  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106287  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106288  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106289  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106290  */
106291 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK)
106292 
106293 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
106294 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
106295 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
106296  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106297  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106298  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106299  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106300  */
106301 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK)
106302 /*! @} */
106303 
106304 /* The count of TRDC_MBC_DOM9_MEM3_BLK_NSE_W */
106305 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_COUNT       (2U)
106306 
106307 /* The count of TRDC_MBC_DOM9_MEM3_BLK_NSE_W */
106308 #define TRDC_MBC_DOM9_MEM3_BLK_NSE_W_COUNT2      (1U)
106309 
106310 /*! @name MBC_DOM10_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
106311 /*! @{ */
106312 
106313 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
106314 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
106315 /*! MBACSEL0 - Memory Block Access Control Select for block B
106316  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106317  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106318  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106319  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106320  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106321  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106322  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106323  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106324  */
106325 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK)
106326 
106327 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
106328 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
106329 /*! NSE0 - NonSecure Enable for block B
106330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106333  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106334  */
106335 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK)
106336 
106337 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
106338 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
106339 /*! MBACSEL1 - Memory Block Access Control Select for block B
106340  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106341  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106342  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106343  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106344  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106345  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106346  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106347  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106348  */
106349 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK)
106350 
106351 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
106352 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
106353 /*! NSE1 - NonSecure Enable for block B
106354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106357  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106358  */
106359 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK)
106360 
106361 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
106362 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
106363 /*! MBACSEL2 - Memory Block Access Control Select for block B
106364  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106365  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106366  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106367  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106368  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106369  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106370  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106371  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106372  */
106373 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK)
106374 
106375 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
106376 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
106377 /*! NSE2 - NonSecure Enable for block B
106378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106381  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106382  */
106383 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK)
106384 
106385 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
106386 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
106387 /*! MBACSEL3 - Memory Block Access Control Select for block B
106388  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106389  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106390  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106391  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106392  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106393  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106394  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106395  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106396  */
106397 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK)
106398 
106399 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
106400 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
106401 /*! NSE3 - NonSecure Enable for block B
106402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106405  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106406  */
106407 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK)
106408 
106409 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
106410 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
106411 /*! MBACSEL4 - Memory Block Access Control Select for block B
106412  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106413  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106414  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106415  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106416  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106417  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106418  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106419  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106420  */
106421 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK)
106422 
106423 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
106424 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
106425 /*! NSE4 - NonSecure Enable for block B
106426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106429  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106430  */
106431 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK)
106432 
106433 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
106434 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
106435 /*! MBACSEL5 - Memory Block Access Control Select for block B
106436  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106437  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106438  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106439  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106440  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106441  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106442  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106443  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106444  */
106445 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK)
106446 
106447 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
106448 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
106449 /*! NSE5 - NonSecure Enable for block B
106450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106453  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106454  */
106455 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK)
106456 
106457 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
106458 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
106459 /*! MBACSEL6 - Memory Block Access Control Select for block B
106460  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106461  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106462  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106463  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106464  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106465  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106466  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106467  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106468  */
106469 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK)
106470 
106471 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
106472 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
106473 /*! NSE6 - NonSecure Enable for block B
106474  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106475  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106476  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106477  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106478  */
106479 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK)
106480 
106481 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
106482 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
106483 /*! MBACSEL7 - Memory Block Access Control Select for block B
106484  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106485  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106486  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106487  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106488  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106489  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106490  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106491  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106492  */
106493 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK)
106494 
106495 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
106496 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
106497 /*! NSE7 - NonSecure Enable for block B
106498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106501  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106502  */
106503 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK)
106504 /*! @} */
106505 
106506 /* The count of TRDC_MBC_DOM10_MEM0_BLK_CFG_W */
106507 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_COUNT      (2U)
106508 
106509 /* The count of TRDC_MBC_DOM10_MEM0_BLK_CFG_W */
106510 #define TRDC_MBC_DOM10_MEM0_BLK_CFG_W_COUNT2     (16U)
106511 
106512 /*! @name MBC_DOM10_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
106513 /*! @{ */
106514 
106515 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
106516 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
106517 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
106518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106521  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106522  */
106523 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK)
106524 
106525 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
106526 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
106527 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
106528  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106529  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106530  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106531  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106532  */
106533 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK)
106534 
106535 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
106536 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
106537 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
106538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106541  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106542  */
106543 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK)
106544 
106545 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
106546 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
106547 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
106548  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106549  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106550  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106551  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106552  */
106553 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK)
106554 
106555 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
106556 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
106557 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
106558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106561  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106562  */
106563 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK)
106564 
106565 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
106566 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
106567 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
106568  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106569  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106570  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106571  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106572  */
106573 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK)
106574 
106575 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
106576 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
106577 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
106578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106581  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106582  */
106583 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK)
106584 
106585 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
106586 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
106587 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
106588  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106589  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106590  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106591  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106592  */
106593 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK)
106594 
106595 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
106596 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
106597 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
106598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106601  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106602  */
106603 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK)
106604 
106605 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
106606 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
106607 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
106608  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106609  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106610  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106611  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106612  */
106613 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK)
106614 
106615 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
106616 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
106617 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
106618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106621  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106622  */
106623 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK)
106624 
106625 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
106626 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
106627 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
106628  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106629  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106630  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106631  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106632  */
106633 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK)
106634 
106635 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
106636 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
106637 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
106638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106641  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106642  */
106643 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK)
106644 
106645 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
106646 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
106647 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
106648  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106649  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106650  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106651  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106652  */
106653 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK)
106654 
106655 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
106656 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
106657 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
106658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106661  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106662  */
106663 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK)
106664 
106665 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
106666 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
106667 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
106668  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106669  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106670  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106671  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106672  */
106673 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK)
106674 
106675 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
106676 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
106677 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
106678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106681  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106682  */
106683 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK)
106684 
106685 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
106686 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
106687 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
106688  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106689  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106690  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106691  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106692  */
106693 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK)
106694 
106695 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
106696 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
106697 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
106698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106701  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106702  */
106703 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK)
106704 
106705 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
106706 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
106707 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
106708  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106709  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106710  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106711  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106712  */
106713 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK)
106714 
106715 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
106716 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
106717 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
106718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106721  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106722  */
106723 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK)
106724 
106725 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
106726 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
106727 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
106728  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106729  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106730  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106731  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106732  */
106733 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK)
106734 
106735 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
106736 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
106737 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
106738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106741  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106742  */
106743 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK)
106744 
106745 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
106746 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
106747 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
106748  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106749  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106750  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106751  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106752  */
106753 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK)
106754 
106755 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
106756 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
106757 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
106758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106761  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106762  */
106763 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK)
106764 
106765 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
106766 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
106767 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
106768  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106769  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106770  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106771  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106772  */
106773 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK)
106774 
106775 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
106776 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
106777 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
106778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106781  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106782  */
106783 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK)
106784 
106785 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
106786 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
106787 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
106788  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106789  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106790  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106791  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106792  */
106793 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK)
106794 
106795 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
106796 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
106797 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
106798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106801  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106802  */
106803 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK)
106804 
106805 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
106806 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
106807 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
106808  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106809  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106810  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106811  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106812  */
106813 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK)
106814 
106815 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
106816 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
106817 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
106818  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106819  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106820  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106821  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106822  */
106823 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK)
106824 
106825 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
106826 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
106827 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
106828  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
106829  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106830  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106831  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106832  */
106833 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK)
106834 /*! @} */
106835 
106836 /* The count of TRDC_MBC_DOM10_MEM0_BLK_NSE_W */
106837 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_COUNT      (2U)
106838 
106839 /* The count of TRDC_MBC_DOM10_MEM0_BLK_NSE_W */
106840 #define TRDC_MBC_DOM10_MEM0_BLK_NSE_W_COUNT2     (4U)
106841 
106842 /*! @name MBC_DOM10_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
106843 /*! @{ */
106844 
106845 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
106846 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
106847 /*! MBACSEL0 - Memory Block Access Control Select for block B
106848  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106849  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106850  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106851  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106852  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106853  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106854  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106855  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106856  */
106857 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK)
106858 
106859 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
106860 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
106861 /*! NSE0 - NonSecure Enable for block B
106862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106865  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106866  */
106867 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK)
106868 
106869 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
106870 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
106871 /*! MBACSEL1 - Memory Block Access Control Select for block B
106872  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106873  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106874  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106875  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106876  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106877  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106878  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106879  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106880  */
106881 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK)
106882 
106883 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
106884 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
106885 /*! NSE1 - NonSecure Enable for block B
106886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106889  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106890  */
106891 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK)
106892 
106893 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
106894 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
106895 /*! MBACSEL2 - Memory Block Access Control Select for block B
106896  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106897  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106898  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106899  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106900  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106901  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106902  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106903  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106904  */
106905 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK)
106906 
106907 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
106908 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
106909 /*! NSE2 - NonSecure Enable for block B
106910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106913  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106914  */
106915 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK)
106916 
106917 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
106918 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
106919 /*! MBACSEL3 - Memory Block Access Control Select for block B
106920  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106921  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106922  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106923  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106924  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106925  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106926  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106927  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106928  */
106929 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK)
106930 
106931 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
106932 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
106933 /*! NSE3 - NonSecure Enable for block B
106934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106937  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106938  */
106939 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK)
106940 
106941 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
106942 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
106943 /*! MBACSEL4 - Memory Block Access Control Select for block B
106944  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106945  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106946  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106947  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106948  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106949  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106950  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106951  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106952  */
106953 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK)
106954 
106955 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
106956 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
106957 /*! NSE4 - NonSecure Enable for block B
106958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106961  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106962  */
106963 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK)
106964 
106965 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
106966 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
106967 /*! MBACSEL5 - Memory Block Access Control Select for block B
106968  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106969  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106970  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106971  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106972  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106973  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106974  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106975  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
106976  */
106977 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK)
106978 
106979 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
106980 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
106981 /*! NSE5 - NonSecure Enable for block B
106982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
106983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
106984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
106985  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
106986  */
106987 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK)
106988 
106989 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
106990 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
106991 /*! MBACSEL6 - Memory Block Access Control Select for block B
106992  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
106993  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
106994  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
106995  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
106996  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
106997  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
106998  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
106999  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107000  */
107001 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK)
107002 
107003 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
107004 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
107005 /*! NSE6 - NonSecure Enable for block B
107006  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107007  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107008  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107009  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107010  */
107011 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK)
107012 
107013 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
107014 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
107015 /*! MBACSEL7 - Memory Block Access Control Select for block B
107016  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107017  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107018  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107019  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107020  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107021  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107022  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107023  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107024  */
107025 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK)
107026 
107027 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
107028 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
107029 /*! NSE7 - NonSecure Enable for block B
107030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107033  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107034  */
107035 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK)
107036 /*! @} */
107037 
107038 /* The count of TRDC_MBC_DOM10_MEM1_BLK_CFG_W */
107039 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_COUNT      (2U)
107040 
107041 /* The count of TRDC_MBC_DOM10_MEM1_BLK_CFG_W */
107042 #define TRDC_MBC_DOM10_MEM1_BLK_CFG_W_COUNT2     (4U)
107043 
107044 /*! @name MBC_DOM10_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
107045 /*! @{ */
107046 
107047 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
107048 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
107049 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
107050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107053  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107054  */
107055 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK)
107056 
107057 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
107058 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
107059 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
107060  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107061  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107062  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107063  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107064  */
107065 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK)
107066 
107067 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
107068 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
107069 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
107070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107073  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107074  */
107075 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK)
107076 
107077 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
107078 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
107079 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
107080  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107081  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107082  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107083  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107084  */
107085 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK)
107086 
107087 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
107088 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
107089 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
107090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107093  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107094  */
107095 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK)
107096 
107097 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
107098 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
107099 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
107100  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107101  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107102  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107103  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107104  */
107105 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK)
107106 
107107 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
107108 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
107109 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
107110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107113  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107114  */
107115 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK)
107116 
107117 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
107118 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
107119 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
107120  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107121  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107122  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107123  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107124  */
107125 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK)
107126 
107127 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
107128 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
107129 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
107130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107133  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107134  */
107135 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK)
107136 
107137 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
107138 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
107139 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
107140  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107141  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107142  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107143  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107144  */
107145 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK)
107146 
107147 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
107148 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
107149 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
107150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107153  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107154  */
107155 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK)
107156 
107157 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
107158 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
107159 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
107160  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107161  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107162  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107163  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107164  */
107165 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK)
107166 
107167 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
107168 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
107169 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
107170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107173  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107174  */
107175 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK)
107176 
107177 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
107178 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
107179 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
107180  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107181  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107182  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107183  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107184  */
107185 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK)
107186 
107187 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
107188 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
107189 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
107190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107193  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107194  */
107195 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK)
107196 
107197 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
107198 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
107199 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
107200  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107201  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107202  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107203  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107204  */
107205 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK)
107206 
107207 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
107208 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
107209 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
107210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107213  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107214  */
107215 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK)
107216 
107217 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
107218 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
107219 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
107220  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107221  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107222  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107223  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107224  */
107225 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK)
107226 
107227 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
107228 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
107229 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
107230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107233  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107234  */
107235 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK)
107236 
107237 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
107238 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
107239 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
107240  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107241  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107242  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107243  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107244  */
107245 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK)
107246 
107247 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
107248 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
107249 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
107250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107253  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107254  */
107255 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK)
107256 
107257 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
107258 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
107259 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
107260  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107261  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107262  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107263  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107264  */
107265 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK)
107266 
107267 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
107268 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
107269 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
107270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107273  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107274  */
107275 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK)
107276 
107277 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
107278 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
107279 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
107280  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107281  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107282  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107283  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107284  */
107285 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK)
107286 
107287 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
107288 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
107289 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
107290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107293  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107294  */
107295 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK)
107296 
107297 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
107298 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
107299 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
107300  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107301  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107302  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107303  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107304  */
107305 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK)
107306 
107307 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
107308 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
107309 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
107310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107313  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107314  */
107315 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK)
107316 
107317 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
107318 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
107319 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
107320  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107321  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107322  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107323  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107324  */
107325 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK)
107326 
107327 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
107328 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
107329 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
107330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107333  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107334  */
107335 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK)
107336 
107337 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
107338 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
107339 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
107340  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107341  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107342  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107343  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107344  */
107345 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK)
107346 
107347 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
107348 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
107349 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
107350  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107351  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107352  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107353  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107354  */
107355 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK)
107356 
107357 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
107358 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
107359 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
107360  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107361  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107362  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107363  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107364  */
107365 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK)
107366 /*! @} */
107367 
107368 /* The count of TRDC_MBC_DOM10_MEM1_BLK_NSE_W */
107369 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_COUNT      (2U)
107370 
107371 /* The count of TRDC_MBC_DOM10_MEM1_BLK_NSE_W */
107372 #define TRDC_MBC_DOM10_MEM1_BLK_NSE_W_COUNT2     (1U)
107373 
107374 /*! @name MBC_DOM10_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
107375 /*! @{ */
107376 
107377 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
107378 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
107379 /*! MBACSEL0 - Memory Block Access Control Select for block B
107380  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107381  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107382  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107383  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107384  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107385  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107386  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107387  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107388  */
107389 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK)
107390 
107391 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
107392 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
107393 /*! NSE0 - NonSecure Enable for block B
107394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107397  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107398  */
107399 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK)
107400 
107401 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
107402 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
107403 /*! MBACSEL1 - Memory Block Access Control Select for block B
107404  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107405  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107406  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107407  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107408  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107409  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107410  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107411  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107412  */
107413 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK)
107414 
107415 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
107416 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
107417 /*! NSE1 - NonSecure Enable for block B
107418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107421  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107422  */
107423 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK)
107424 
107425 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
107426 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
107427 /*! MBACSEL2 - Memory Block Access Control Select for block B
107428  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107429  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107430  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107431  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107432  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107433  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107434  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107435  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107436  */
107437 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK)
107438 
107439 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
107440 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
107441 /*! NSE2 - NonSecure Enable for block B
107442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107445  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107446  */
107447 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK)
107448 
107449 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
107450 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
107451 /*! MBACSEL3 - Memory Block Access Control Select for block B
107452  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107453  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107454  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107455  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107456  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107457  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107458  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107459  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107460  */
107461 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK)
107462 
107463 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
107464 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
107465 /*! NSE3 - NonSecure Enable for block B
107466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107469  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107470  */
107471 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK)
107472 
107473 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
107474 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
107475 /*! MBACSEL4 - Memory Block Access Control Select for block B
107476  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107477  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107478  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107479  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107480  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107481  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107482  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107483  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107484  */
107485 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK)
107486 
107487 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
107488 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
107489 /*! NSE4 - NonSecure Enable for block B
107490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107493  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107494  */
107495 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK)
107496 
107497 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
107498 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
107499 /*! MBACSEL5 - Memory Block Access Control Select for block B
107500  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107501  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107502  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107503  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107504  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107505  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107506  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107507  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107508  */
107509 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK)
107510 
107511 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
107512 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
107513 /*! NSE5 - NonSecure Enable for block B
107514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107517  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107518  */
107519 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK)
107520 
107521 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
107522 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
107523 /*! MBACSEL6 - Memory Block Access Control Select for block B
107524  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107525  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107526  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107527  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107528  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107529  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107530  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107531  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107532  */
107533 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK)
107534 
107535 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
107536 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
107537 /*! NSE6 - NonSecure Enable for block B
107538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107541  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107542  */
107543 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK)
107544 
107545 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
107546 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
107547 /*! MBACSEL7 - Memory Block Access Control Select for block B
107548  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107549  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107550  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107551  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107552  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107553  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107554  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107555  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107556  */
107557 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK)
107558 
107559 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
107560 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
107561 /*! NSE7 - NonSecure Enable for block B
107562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107565  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107566  */
107567 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK)
107568 /*! @} */
107569 
107570 /* The count of TRDC_MBC_DOM10_MEM2_BLK_CFG_W */
107571 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_COUNT      (2U)
107572 
107573 /* The count of TRDC_MBC_DOM10_MEM2_BLK_CFG_W */
107574 #define TRDC_MBC_DOM10_MEM2_BLK_CFG_W_COUNT2     (1U)
107575 
107576 /*! @name MBC_DOM10_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
107577 /*! @{ */
107578 
107579 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
107580 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
107581 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
107582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107585  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107586  */
107587 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK)
107588 
107589 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
107590 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
107591 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
107592  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107593  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107594  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107595  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107596  */
107597 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK)
107598 
107599 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
107600 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
107601 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
107602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107605  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107606  */
107607 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK)
107608 
107609 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
107610 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
107611 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
107612  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107613  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107614  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107615  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107616  */
107617 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK)
107618 
107619 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
107620 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
107621 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
107622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107625  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107626  */
107627 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK)
107628 
107629 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
107630 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
107631 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
107632  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107633  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107634  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107635  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107636  */
107637 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK)
107638 
107639 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
107640 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
107641 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
107642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107645  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107646  */
107647 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK)
107648 
107649 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
107650 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
107651 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
107652  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107653  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107654  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107655  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107656  */
107657 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK)
107658 
107659 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
107660 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
107661 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
107662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107665  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107666  */
107667 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK)
107668 
107669 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
107670 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
107671 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
107672  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107673  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107674  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107675  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107676  */
107677 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK)
107678 
107679 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
107680 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
107681 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
107682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107685  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107686  */
107687 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK)
107688 
107689 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
107690 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
107691 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
107692  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107693  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107694  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107695  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107696  */
107697 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK)
107698 
107699 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
107700 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
107701 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
107702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107705  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107706  */
107707 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK)
107708 
107709 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
107710 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
107711 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
107712  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107713  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107714  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107715  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107716  */
107717 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK)
107718 
107719 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
107720 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
107721 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
107722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107725  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107726  */
107727 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK)
107728 
107729 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
107730 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
107731 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
107732  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107733  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107734  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107735  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107736  */
107737 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK)
107738 
107739 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
107740 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
107741 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
107742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107745  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107746  */
107747 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK)
107748 
107749 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
107750 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
107751 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
107752  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107753  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107754  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107755  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107756  */
107757 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK)
107758 
107759 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
107760 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
107761 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
107762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107765  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107766  */
107767 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK)
107768 
107769 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
107770 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
107771 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
107772  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107773  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107774  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107775  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107776  */
107777 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK)
107778 
107779 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
107780 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
107781 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
107782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107785  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107786  */
107787 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK)
107788 
107789 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
107790 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
107791 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
107792  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107793  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107794  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107795  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107796  */
107797 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK)
107798 
107799 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
107800 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
107801 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
107802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107805  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107806  */
107807 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK)
107808 
107809 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
107810 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
107811 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
107812  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107813  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107814  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107815  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107816  */
107817 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK)
107818 
107819 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
107820 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
107821 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
107822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107825  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107826  */
107827 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK)
107828 
107829 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
107830 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
107831 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
107832  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107833  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107834  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107835  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107836  */
107837 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK)
107838 
107839 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
107840 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
107841 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
107842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107845  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107846  */
107847 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK)
107848 
107849 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
107850 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
107851 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
107852  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107853  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107854  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107855  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107856  */
107857 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK)
107858 
107859 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
107860 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
107861 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
107862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107865  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107866  */
107867 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK)
107868 
107869 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
107870 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
107871 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
107872  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107873  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107874  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107875  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107876  */
107877 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK)
107878 
107879 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
107880 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
107881 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
107882  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107883  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107884  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107885  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107886  */
107887 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK)
107888 
107889 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
107890 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
107891 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
107892  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
107893  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107894  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107895  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107896  */
107897 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK)
107898 /*! @} */
107899 
107900 /* The count of TRDC_MBC_DOM10_MEM2_BLK_NSE_W */
107901 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_COUNT      (2U)
107902 
107903 /* The count of TRDC_MBC_DOM10_MEM2_BLK_NSE_W */
107904 #define TRDC_MBC_DOM10_MEM2_BLK_NSE_W_COUNT2     (1U)
107905 
107906 /*! @name MBC_DOM10_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
107907 /*! @{ */
107908 
107909 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
107910 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
107911 /*! MBACSEL0 - Memory Block Access Control Select for block B
107912  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107913  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107914  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107915  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107916  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107917  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107918  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107919  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107920  */
107921 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK)
107922 
107923 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
107924 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
107925 /*! NSE0 - NonSecure Enable for block B
107926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107929  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107930  */
107931 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK)
107932 
107933 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
107934 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
107935 /*! MBACSEL1 - Memory Block Access Control Select for block B
107936  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107937  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107938  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107939  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107940  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107941  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107942  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107943  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107944  */
107945 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK)
107946 
107947 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
107948 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
107949 /*! NSE1 - NonSecure Enable for block B
107950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107953  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107954  */
107955 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK)
107956 
107957 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
107958 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
107959 /*! MBACSEL2 - Memory Block Access Control Select for block B
107960  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107961  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107962  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107963  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107964  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107965  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107966  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107967  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107968  */
107969 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK)
107970 
107971 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
107972 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
107973 /*! NSE2 - NonSecure Enable for block B
107974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
107976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
107977  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
107978  */
107979 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK)
107980 
107981 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
107982 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
107983 /*! MBACSEL3 - Memory Block Access Control Select for block B
107984  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
107985  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
107986  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
107987  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
107988  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
107989  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
107990  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
107991  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
107992  */
107993 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK)
107994 
107995 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
107996 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
107997 /*! NSE3 - NonSecure Enable for block B
107998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
107999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108001  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108002  */
108003 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK)
108004 
108005 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
108006 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
108007 /*! MBACSEL4 - Memory Block Access Control Select for block B
108008  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108009  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108010  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108011  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108012  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108013  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108014  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108015  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108016  */
108017 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK)
108018 
108019 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
108020 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
108021 /*! NSE4 - NonSecure Enable for block B
108022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108025  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108026  */
108027 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK)
108028 
108029 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
108030 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
108031 /*! MBACSEL5 - Memory Block Access Control Select for block B
108032  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108033  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108034  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108035  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108036  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108037  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108038  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108039  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108040  */
108041 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK)
108042 
108043 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
108044 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
108045 /*! NSE5 - NonSecure Enable for block B
108046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108049  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108050  */
108051 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK)
108052 
108053 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
108054 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
108055 /*! MBACSEL6 - Memory Block Access Control Select for block B
108056  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108057  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108058  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108059  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108060  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108061  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108062  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108063  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108064  */
108065 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK)
108066 
108067 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
108068 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
108069 /*! NSE6 - NonSecure Enable for block B
108070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108073  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108074  */
108075 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK)
108076 
108077 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
108078 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
108079 /*! MBACSEL7 - Memory Block Access Control Select for block B
108080  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108081  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108082  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108083  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108084  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108085  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108086  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108087  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108088  */
108089 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK)
108090 
108091 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
108092 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
108093 /*! NSE7 - NonSecure Enable for block B
108094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108097  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108098  */
108099 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK)
108100 /*! @} */
108101 
108102 /* The count of TRDC_MBC_DOM10_MEM3_BLK_CFG_W */
108103 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_COUNT      (2U)
108104 
108105 /* The count of TRDC_MBC_DOM10_MEM3_BLK_CFG_W */
108106 #define TRDC_MBC_DOM10_MEM3_BLK_CFG_W_COUNT2     (3U)
108107 
108108 /*! @name MBC_DOM10_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
108109 /*! @{ */
108110 
108111 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
108112 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
108113 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
108114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108117  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108118  */
108119 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK)
108120 
108121 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
108122 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
108123 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
108124  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108125  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108126  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108127  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108128  */
108129 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK)
108130 
108131 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
108132 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
108133 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
108134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108137  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108138  */
108139 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK)
108140 
108141 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
108142 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
108143 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
108144  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108145  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108146  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108147  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108148  */
108149 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK)
108150 
108151 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
108152 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
108153 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
108154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108157  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108158  */
108159 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK)
108160 
108161 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
108162 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
108163 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
108164  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108165  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108166  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108167  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108168  */
108169 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK)
108170 
108171 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
108172 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
108173 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
108174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108177  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108178  */
108179 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK)
108180 
108181 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
108182 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
108183 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
108184  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108185  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108186  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108187  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108188  */
108189 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK)
108190 
108191 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
108192 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
108193 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
108194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108197  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108198  */
108199 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK)
108200 
108201 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
108202 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
108203 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
108204  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108205  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108206  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108207  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108208  */
108209 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK)
108210 
108211 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
108212 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
108213 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
108214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108217  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108218  */
108219 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK)
108220 
108221 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
108222 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
108223 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
108224  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108225  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108226  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108227  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108228  */
108229 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK)
108230 
108231 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
108232 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
108233 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
108234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108237  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108238  */
108239 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK)
108240 
108241 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
108242 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
108243 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
108244  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108245  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108246  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108247  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108248  */
108249 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK)
108250 
108251 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
108252 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
108253 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
108254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108257  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108258  */
108259 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK)
108260 
108261 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
108262 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
108263 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
108264  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108265  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108266  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108267  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108268  */
108269 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK)
108270 
108271 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
108272 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
108273 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
108274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108277  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108278  */
108279 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK)
108280 
108281 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
108282 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
108283 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
108284  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108285  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108286  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108287  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108288  */
108289 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK)
108290 
108291 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
108292 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
108293 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
108294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108297  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108298  */
108299 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK)
108300 
108301 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
108302 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
108303 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
108304  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108305  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108306  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108307  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108308  */
108309 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK)
108310 
108311 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
108312 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
108313 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
108314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108317  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108318  */
108319 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK)
108320 
108321 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
108322 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
108323 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
108324  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108325  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108326  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108327  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108328  */
108329 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK)
108330 
108331 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
108332 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
108333 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
108334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108337  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108338  */
108339 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK)
108340 
108341 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
108342 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
108343 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
108344  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108345  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108346  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108347  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108348  */
108349 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK)
108350 
108351 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
108352 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
108353 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
108354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108357  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108358  */
108359 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK)
108360 
108361 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
108362 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
108363 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
108364  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108365  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108366  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108367  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108368  */
108369 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK)
108370 
108371 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
108372 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
108373 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
108374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108377  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108378  */
108379 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK)
108380 
108381 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
108382 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
108383 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
108384  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108385  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108386  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108387  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108388  */
108389 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK)
108390 
108391 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
108392 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
108393 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
108394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108397  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108398  */
108399 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK)
108400 
108401 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
108402 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
108403 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
108404  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108405  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108406  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108407  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108408  */
108409 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK)
108410 
108411 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
108412 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
108413 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
108414  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108415  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108416  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108417  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108418  */
108419 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK)
108420 
108421 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
108422 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
108423 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
108424  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108425  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108426  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108427  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108428  */
108429 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK)
108430 /*! @} */
108431 
108432 /* The count of TRDC_MBC_DOM10_MEM3_BLK_NSE_W */
108433 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_COUNT      (2U)
108434 
108435 /* The count of TRDC_MBC_DOM10_MEM3_BLK_NSE_W */
108436 #define TRDC_MBC_DOM10_MEM3_BLK_NSE_W_COUNT2     (1U)
108437 
108438 /*! @name MBC_DOM11_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
108439 /*! @{ */
108440 
108441 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
108442 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
108443 /*! MBACSEL0 - Memory Block Access Control Select for block B
108444  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108445  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108446  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108447  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108448  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108449  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108450  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108451  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108452  */
108453 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK)
108454 
108455 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
108456 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
108457 /*! NSE0 - NonSecure Enable for block B
108458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108461  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108462  */
108463 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK)
108464 
108465 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
108466 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
108467 /*! MBACSEL1 - Memory Block Access Control Select for block B
108468  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108469  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108470  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108471  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108472  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108473  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108474  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108475  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108476  */
108477 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK)
108478 
108479 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
108480 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
108481 /*! NSE1 - NonSecure Enable for block B
108482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108485  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108486  */
108487 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK)
108488 
108489 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
108490 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
108491 /*! MBACSEL2 - Memory Block Access Control Select for block B
108492  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108493  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108494  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108495  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108496  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108497  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108498  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108499  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108500  */
108501 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK)
108502 
108503 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
108504 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
108505 /*! NSE2 - NonSecure Enable for block B
108506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108509  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108510  */
108511 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK)
108512 
108513 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
108514 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
108515 /*! MBACSEL3 - Memory Block Access Control Select for block B
108516  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108517  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108518  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108519  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108520  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108521  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108522  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108523  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108524  */
108525 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK)
108526 
108527 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
108528 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
108529 /*! NSE3 - NonSecure Enable for block B
108530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108533  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108534  */
108535 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK)
108536 
108537 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
108538 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
108539 /*! MBACSEL4 - Memory Block Access Control Select for block B
108540  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108541  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108542  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108543  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108544  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108545  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108546  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108547  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108548  */
108549 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK)
108550 
108551 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
108552 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
108553 /*! NSE4 - NonSecure Enable for block B
108554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108557  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108558  */
108559 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK)
108560 
108561 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
108562 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
108563 /*! MBACSEL5 - Memory Block Access Control Select for block B
108564  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108565  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108566  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108567  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108568  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108569  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108570  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108571  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108572  */
108573 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK)
108574 
108575 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
108576 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
108577 /*! NSE5 - NonSecure Enable for block B
108578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108581  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108582  */
108583 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK)
108584 
108585 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
108586 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
108587 /*! MBACSEL6 - Memory Block Access Control Select for block B
108588  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108589  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108590  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108591  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108592  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108593  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108594  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108595  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108596  */
108597 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK)
108598 
108599 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
108600 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
108601 /*! NSE6 - NonSecure Enable for block B
108602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108605  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108606  */
108607 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK)
108608 
108609 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
108610 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
108611 /*! MBACSEL7 - Memory Block Access Control Select for block B
108612  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108613  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108614  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108615  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108616  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108617  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108618  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108619  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108620  */
108621 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK)
108622 
108623 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
108624 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
108625 /*! NSE7 - NonSecure Enable for block B
108626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108629  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108630  */
108631 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK)
108632 /*! @} */
108633 
108634 /* The count of TRDC_MBC_DOM11_MEM0_BLK_CFG_W */
108635 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_COUNT      (2U)
108636 
108637 /* The count of TRDC_MBC_DOM11_MEM0_BLK_CFG_W */
108638 #define TRDC_MBC_DOM11_MEM0_BLK_CFG_W_COUNT2     (16U)
108639 
108640 /*! @name MBC_DOM11_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
108641 /*! @{ */
108642 
108643 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
108644 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
108645 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
108646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108649  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108650  */
108651 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK)
108652 
108653 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
108654 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
108655 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
108656  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108657  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108658  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108659  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108660  */
108661 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK)
108662 
108663 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
108664 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
108665 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
108666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108669  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108670  */
108671 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK)
108672 
108673 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
108674 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
108675 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
108676  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108677  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108678  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108679  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108680  */
108681 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK)
108682 
108683 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
108684 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
108685 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
108686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108689  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108690  */
108691 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK)
108692 
108693 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
108694 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
108695 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
108696  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108697  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108698  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108699  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108700  */
108701 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK)
108702 
108703 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
108704 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
108705 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
108706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108709  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108710  */
108711 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK)
108712 
108713 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
108714 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
108715 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
108716  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108717  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108718  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108719  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108720  */
108721 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK)
108722 
108723 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
108724 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
108725 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
108726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108729  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108730  */
108731 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK)
108732 
108733 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
108734 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
108735 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
108736  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108737  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108738  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108739  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108740  */
108741 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK)
108742 
108743 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
108744 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
108745 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
108746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108749  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108750  */
108751 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK)
108752 
108753 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
108754 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
108755 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
108756  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108757  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108758  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108759  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108760  */
108761 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK)
108762 
108763 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
108764 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
108765 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
108766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108769  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108770  */
108771 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK)
108772 
108773 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
108774 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
108775 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
108776  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108777  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108778  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108779  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108780  */
108781 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK)
108782 
108783 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
108784 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
108785 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
108786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108789  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108790  */
108791 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK)
108792 
108793 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
108794 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
108795 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
108796  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108797  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108798  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108799  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108800  */
108801 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK)
108802 
108803 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
108804 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
108805 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
108806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108809  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108810  */
108811 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK)
108812 
108813 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
108814 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
108815 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
108816  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108817  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108818  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108819  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108820  */
108821 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK)
108822 
108823 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
108824 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
108825 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
108826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108829  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108830  */
108831 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK)
108832 
108833 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
108834 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
108835 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
108836  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108837  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108838  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108839  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108840  */
108841 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK)
108842 
108843 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
108844 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
108845 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
108846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108849  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108850  */
108851 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK)
108852 
108853 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
108854 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
108855 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
108856  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108857  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108858  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108859  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108860  */
108861 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK)
108862 
108863 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
108864 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
108865 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
108866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108869  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108870  */
108871 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK)
108872 
108873 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
108874 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
108875 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
108876  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108877  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108878  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108879  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108880  */
108881 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK)
108882 
108883 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
108884 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
108885 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
108886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108889  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108890  */
108891 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK)
108892 
108893 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
108894 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
108895 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
108896  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108897  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108898  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108899  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108900  */
108901 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK)
108902 
108903 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
108904 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
108905 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
108906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108909  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108910  */
108911 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK)
108912 
108913 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
108914 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
108915 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
108916  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108917  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108918  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108919  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108920  */
108921 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK)
108922 
108923 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
108924 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
108925 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
108926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108929  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108930  */
108931 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK)
108932 
108933 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
108934 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
108935 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
108936  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108937  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108938  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108939  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108940  */
108941 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK)
108942 
108943 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
108944 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
108945 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
108946  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108947  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108948  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108949  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108950  */
108951 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK)
108952 
108953 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
108954 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
108955 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
108956  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
108957  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108958  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108959  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108960  */
108961 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK)
108962 /*! @} */
108963 
108964 /* The count of TRDC_MBC_DOM11_MEM0_BLK_NSE_W */
108965 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_COUNT      (2U)
108966 
108967 /* The count of TRDC_MBC_DOM11_MEM0_BLK_NSE_W */
108968 #define TRDC_MBC_DOM11_MEM0_BLK_NSE_W_COUNT2     (4U)
108969 
108970 /*! @name MBC_DOM11_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
108971 /*! @{ */
108972 
108973 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
108974 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
108975 /*! MBACSEL0 - Memory Block Access Control Select for block B
108976  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
108977  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
108978  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
108979  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
108980  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
108981  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
108982  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
108983  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
108984  */
108985 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK)
108986 
108987 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
108988 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
108989 /*! NSE0 - NonSecure Enable for block B
108990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
108991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
108992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
108993  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
108994  */
108995 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK)
108996 
108997 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
108998 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
108999 /*! MBACSEL1 - Memory Block Access Control Select for block B
109000  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109001  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109002  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109003  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109004  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109005  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109006  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109007  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109008  */
109009 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK)
109010 
109011 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
109012 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
109013 /*! NSE1 - NonSecure Enable for block B
109014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109017  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109018  */
109019 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK)
109020 
109021 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
109022 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
109023 /*! MBACSEL2 - Memory Block Access Control Select for block B
109024  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109025  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109026  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109027  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109028  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109029  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109030  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109031  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109032  */
109033 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK)
109034 
109035 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
109036 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
109037 /*! NSE2 - NonSecure Enable for block B
109038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109041  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109042  */
109043 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK)
109044 
109045 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
109046 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
109047 /*! MBACSEL3 - Memory Block Access Control Select for block B
109048  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109049  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109050  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109051  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109052  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109053  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109054  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109055  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109056  */
109057 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK)
109058 
109059 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
109060 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
109061 /*! NSE3 - NonSecure Enable for block B
109062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109065  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109066  */
109067 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK)
109068 
109069 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
109070 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
109071 /*! MBACSEL4 - Memory Block Access Control Select for block B
109072  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109073  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109074  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109075  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109076  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109077  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109078  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109079  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109080  */
109081 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK)
109082 
109083 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
109084 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
109085 /*! NSE4 - NonSecure Enable for block B
109086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109089  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109090  */
109091 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK)
109092 
109093 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
109094 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
109095 /*! MBACSEL5 - Memory Block Access Control Select for block B
109096  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109097  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109098  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109099  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109100  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109101  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109102  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109103  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109104  */
109105 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK)
109106 
109107 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
109108 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
109109 /*! NSE5 - NonSecure Enable for block B
109110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109113  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109114  */
109115 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK)
109116 
109117 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
109118 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
109119 /*! MBACSEL6 - Memory Block Access Control Select for block B
109120  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109121  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109122  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109123  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109124  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109125  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109126  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109127  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109128  */
109129 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK)
109130 
109131 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
109132 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
109133 /*! NSE6 - NonSecure Enable for block B
109134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109137  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109138  */
109139 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK)
109140 
109141 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
109142 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
109143 /*! MBACSEL7 - Memory Block Access Control Select for block B
109144  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109145  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109146  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109147  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109148  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109149  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109150  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109151  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109152  */
109153 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK)
109154 
109155 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
109156 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
109157 /*! NSE7 - NonSecure Enable for block B
109158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109161  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109162  */
109163 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK)
109164 /*! @} */
109165 
109166 /* The count of TRDC_MBC_DOM11_MEM1_BLK_CFG_W */
109167 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_COUNT      (2U)
109168 
109169 /* The count of TRDC_MBC_DOM11_MEM1_BLK_CFG_W */
109170 #define TRDC_MBC_DOM11_MEM1_BLK_CFG_W_COUNT2     (4U)
109171 
109172 /*! @name MBC_DOM11_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
109173 /*! @{ */
109174 
109175 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
109176 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
109177 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
109178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109181  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109182  */
109183 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK)
109184 
109185 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
109186 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
109187 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
109188  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109189  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109190  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109191  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109192  */
109193 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK)
109194 
109195 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
109196 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
109197 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
109198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109201  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109202  */
109203 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK)
109204 
109205 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
109206 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
109207 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
109208  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109209  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109210  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109211  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109212  */
109213 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK)
109214 
109215 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
109216 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
109217 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
109218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109221  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109222  */
109223 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK)
109224 
109225 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
109226 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
109227 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
109228  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109229  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109230  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109231  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109232  */
109233 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK)
109234 
109235 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
109236 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
109237 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
109238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109241  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109242  */
109243 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK)
109244 
109245 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
109246 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
109247 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
109248  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109249  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109250  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109251  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109252  */
109253 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK)
109254 
109255 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
109256 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
109257 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
109258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109261  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109262  */
109263 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK)
109264 
109265 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
109266 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
109267 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
109268  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109269  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109270  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109271  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109272  */
109273 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK)
109274 
109275 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
109276 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
109277 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
109278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109281  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109282  */
109283 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK)
109284 
109285 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
109286 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
109287 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
109288  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109289  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109290  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109291  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109292  */
109293 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK)
109294 
109295 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
109296 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
109297 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
109298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109301  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109302  */
109303 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK)
109304 
109305 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
109306 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
109307 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
109308  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109309  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109310  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109311  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109312  */
109313 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK)
109314 
109315 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
109316 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
109317 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
109318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109321  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109322  */
109323 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK)
109324 
109325 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
109326 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
109327 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
109328  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109329  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109330  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109331  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109332  */
109333 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK)
109334 
109335 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
109336 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
109337 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
109338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109341  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109342  */
109343 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK)
109344 
109345 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
109346 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
109347 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
109348  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109349  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109350  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109351  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109352  */
109353 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK)
109354 
109355 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
109356 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
109357 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
109358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109361  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109362  */
109363 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK)
109364 
109365 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
109366 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
109367 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
109368  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109369  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109370  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109371  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109372  */
109373 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK)
109374 
109375 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
109376 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
109377 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
109378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109381  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109382  */
109383 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK)
109384 
109385 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
109386 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
109387 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
109388  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109389  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109390  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109391  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109392  */
109393 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK)
109394 
109395 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
109396 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
109397 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
109398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109401  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109402  */
109403 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK)
109404 
109405 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
109406 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
109407 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
109408  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109409  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109410  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109411  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109412  */
109413 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK)
109414 
109415 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
109416 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
109417 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
109418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109421  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109422  */
109423 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK)
109424 
109425 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
109426 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
109427 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
109428  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109429  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109430  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109431  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109432  */
109433 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK)
109434 
109435 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
109436 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
109437 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
109438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109441  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109442  */
109443 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK)
109444 
109445 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
109446 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
109447 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
109448  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109449  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109450  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109451  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109452  */
109453 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK)
109454 
109455 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
109456 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
109457 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
109458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109461  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109462  */
109463 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK)
109464 
109465 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
109466 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
109467 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
109468  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109469  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109470  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109471  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109472  */
109473 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK)
109474 
109475 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
109476 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
109477 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
109478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109481  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109482  */
109483 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK)
109484 
109485 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
109486 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
109487 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
109488  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109489  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109490  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109491  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109492  */
109493 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK)
109494 /*! @} */
109495 
109496 /* The count of TRDC_MBC_DOM11_MEM1_BLK_NSE_W */
109497 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_COUNT      (2U)
109498 
109499 /* The count of TRDC_MBC_DOM11_MEM1_BLK_NSE_W */
109500 #define TRDC_MBC_DOM11_MEM1_BLK_NSE_W_COUNT2     (1U)
109501 
109502 /*! @name MBC_DOM11_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
109503 /*! @{ */
109504 
109505 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
109506 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
109507 /*! MBACSEL0 - Memory Block Access Control Select for block B
109508  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109509  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109510  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109511  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109512  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109513  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109514  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109515  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109516  */
109517 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK)
109518 
109519 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
109520 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
109521 /*! NSE0 - NonSecure Enable for block B
109522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109525  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109526  */
109527 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK)
109528 
109529 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
109530 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
109531 /*! MBACSEL1 - Memory Block Access Control Select for block B
109532  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109533  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109534  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109535  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109536  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109537  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109538  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109539  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109540  */
109541 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK)
109542 
109543 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
109544 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
109545 /*! NSE1 - NonSecure Enable for block B
109546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109549  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109550  */
109551 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK)
109552 
109553 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
109554 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
109555 /*! MBACSEL2 - Memory Block Access Control Select for block B
109556  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109557  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109558  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109559  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109560  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109561  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109562  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109563  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109564  */
109565 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK)
109566 
109567 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
109568 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
109569 /*! NSE2 - NonSecure Enable for block B
109570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109573  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109574  */
109575 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK)
109576 
109577 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
109578 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
109579 /*! MBACSEL3 - Memory Block Access Control Select for block B
109580  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109581  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109582  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109583  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109584  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109585  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109586  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109587  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109588  */
109589 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK)
109590 
109591 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
109592 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
109593 /*! NSE3 - NonSecure Enable for block B
109594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109597  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109598  */
109599 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK)
109600 
109601 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
109602 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
109603 /*! MBACSEL4 - Memory Block Access Control Select for block B
109604  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109605  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109606  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109607  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109608  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109609  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109610  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109611  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109612  */
109613 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK)
109614 
109615 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
109616 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
109617 /*! NSE4 - NonSecure Enable for block B
109618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109621  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109622  */
109623 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK)
109624 
109625 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
109626 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
109627 /*! MBACSEL5 - Memory Block Access Control Select for block B
109628  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109629  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109630  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109631  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109632  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109633  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109634  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109635  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109636  */
109637 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK)
109638 
109639 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
109640 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
109641 /*! NSE5 - NonSecure Enable for block B
109642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109645  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109646  */
109647 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK)
109648 
109649 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
109650 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
109651 /*! MBACSEL6 - Memory Block Access Control Select for block B
109652  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109653  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109654  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109655  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109656  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109657  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109658  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109659  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109660  */
109661 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK)
109662 
109663 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
109664 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
109665 /*! NSE6 - NonSecure Enable for block B
109666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109669  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109670  */
109671 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK)
109672 
109673 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
109674 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
109675 /*! MBACSEL7 - Memory Block Access Control Select for block B
109676  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
109677  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
109678  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
109679  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
109680  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
109681  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
109682  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
109683  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
109684  */
109685 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK)
109686 
109687 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
109688 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
109689 /*! NSE7 - NonSecure Enable for block B
109690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
109691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109693  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109694  */
109695 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK)
109696 /*! @} */
109697 
109698 /* The count of TRDC_MBC_DOM11_MEM2_BLK_CFG_W */
109699 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_COUNT      (2U)
109700 
109701 /* The count of TRDC_MBC_DOM11_MEM2_BLK_CFG_W */
109702 #define TRDC_MBC_DOM11_MEM2_BLK_CFG_W_COUNT2     (1U)
109703 
109704 /*! @name MBC_DOM11_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
109705 /*! @{ */
109706 
109707 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
109708 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
109709 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
109710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109713  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109714  */
109715 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK)
109716 
109717 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
109718 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
109719 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
109720  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109721  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109722  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109723  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109724  */
109725 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK)
109726 
109727 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
109728 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
109729 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
109730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109733  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109734  */
109735 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK)
109736 
109737 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
109738 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
109739 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
109740  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109741  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109742  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109743  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109744  */
109745 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK)
109746 
109747 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
109748 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
109749 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
109750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109753  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109754  */
109755 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK)
109756 
109757 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
109758 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
109759 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
109760  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109761  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109762  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109763  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109764  */
109765 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK)
109766 
109767 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
109768 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
109769 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
109770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109774  */
109775 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK)
109776 
109777 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
109778 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
109779 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
109780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109784  */
109785 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK)
109786 
109787 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
109788 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
109789 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
109790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109794  */
109795 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK)
109796 
109797 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
109798 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
109799 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
109800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109804  */
109805 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK)
109806 
109807 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
109808 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
109809 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
109810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109814  */
109815 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK)
109816 
109817 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
109818 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
109819 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
109820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109824  */
109825 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK)
109826 
109827 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
109828 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
109829 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
109830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109834  */
109835 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK)
109836 
109837 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
109838 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
109839 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
109840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109844  */
109845 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK)
109846 
109847 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
109848 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
109849 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
109850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109854  */
109855 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK)
109856 
109857 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
109858 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
109859 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
109860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109864  */
109865 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK)
109866 
109867 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
109868 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
109869 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
109870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109874  */
109875 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK)
109876 
109877 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
109878 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
109879 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
109880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109884  */
109885 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK)
109886 
109887 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
109888 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
109889 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
109890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109894  */
109895 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK)
109896 
109897 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
109898 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
109899 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
109900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109904  */
109905 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK)
109906 
109907 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
109908 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
109909 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
109910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109914  */
109915 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK)
109916 
109917 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
109918 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
109919 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
109920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109924  */
109925 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK)
109926 
109927 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
109928 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
109929 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
109930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109934  */
109935 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK)
109936 
109937 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
109938 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
109939 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
109940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109944  */
109945 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK)
109946 
109947 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
109948 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
109949 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
109950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109954  */
109955 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK)
109956 
109957 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
109958 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
109959 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
109960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109964  */
109965 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK)
109966 
109967 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
109968 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
109969 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
109970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109974  */
109975 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK)
109976 
109977 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
109978 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
109979 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
109980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109984  */
109985 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK)
109986 
109987 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
109988 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
109989 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
109990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
109991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
109992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
109993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
109994  */
109995 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK)
109996 
109997 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
109998 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
109999 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
110000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110004  */
110005 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK)
110006 
110007 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
110008 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
110009 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
110010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110013  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110014  */
110015 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK)
110016 
110017 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
110018 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
110019 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
110020  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110021  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110022  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110023  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110024  */
110025 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK)
110026 /*! @} */
110027 
110028 /* The count of TRDC_MBC_DOM11_MEM2_BLK_NSE_W */
110029 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_COUNT      (2U)
110030 
110031 /* The count of TRDC_MBC_DOM11_MEM2_BLK_NSE_W */
110032 #define TRDC_MBC_DOM11_MEM2_BLK_NSE_W_COUNT2     (1U)
110033 
110034 /*! @name MBC_DOM11_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
110035 /*! @{ */
110036 
110037 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
110038 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
110039 /*! MBACSEL0 - Memory Block Access Control Select for block B
110040  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110041  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110042  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110043  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110044  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110045  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110046  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110047  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110048  */
110049 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK)
110050 
110051 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
110052 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
110053 /*! NSE0 - NonSecure Enable for block B
110054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110057  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110058  */
110059 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK)
110060 
110061 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
110062 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
110063 /*! MBACSEL1 - Memory Block Access Control Select for block B
110064  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110065  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110066  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110067  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110068  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110069  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110070  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110071  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110072  */
110073 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK)
110074 
110075 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
110076 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
110077 /*! NSE1 - NonSecure Enable for block B
110078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110081  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110082  */
110083 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK)
110084 
110085 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
110086 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
110087 /*! MBACSEL2 - Memory Block Access Control Select for block B
110088  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110089  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110090  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110091  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110092  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110093  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110094  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110095  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110096  */
110097 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK)
110098 
110099 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
110100 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
110101 /*! NSE2 - NonSecure Enable for block B
110102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110105  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110106  */
110107 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK)
110108 
110109 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
110110 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
110111 /*! MBACSEL3 - Memory Block Access Control Select for block B
110112  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110113  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110114  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110115  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110116  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110117  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110118  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110119  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110120  */
110121 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK)
110122 
110123 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
110124 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
110125 /*! NSE3 - NonSecure Enable for block B
110126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110129  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110130  */
110131 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK)
110132 
110133 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
110134 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
110135 /*! MBACSEL4 - Memory Block Access Control Select for block B
110136  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110137  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110138  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110139  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110140  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110141  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110142  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110143  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110144  */
110145 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK)
110146 
110147 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
110148 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
110149 /*! NSE4 - NonSecure Enable for block B
110150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110153  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110154  */
110155 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK)
110156 
110157 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
110158 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
110159 /*! MBACSEL5 - Memory Block Access Control Select for block B
110160  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110161  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110162  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110163  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110164  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110165  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110166  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110167  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110168  */
110169 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK)
110170 
110171 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
110172 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
110173 /*! NSE5 - NonSecure Enable for block B
110174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110177  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110178  */
110179 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK)
110180 
110181 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
110182 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
110183 /*! MBACSEL6 - Memory Block Access Control Select for block B
110184  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110185  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110186  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110187  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110188  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110189  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110190  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110191  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110192  */
110193 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK)
110194 
110195 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
110196 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
110197 /*! NSE6 - NonSecure Enable for block B
110198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110201  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110202  */
110203 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK)
110204 
110205 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
110206 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
110207 /*! MBACSEL7 - Memory Block Access Control Select for block B
110208  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110209  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110210  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110211  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110212  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110213  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110214  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110215  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110216  */
110217 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK)
110218 
110219 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
110220 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
110221 /*! NSE7 - NonSecure Enable for block B
110222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110225  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110226  */
110227 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK)
110228 /*! @} */
110229 
110230 /* The count of TRDC_MBC_DOM11_MEM3_BLK_CFG_W */
110231 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_COUNT      (2U)
110232 
110233 /* The count of TRDC_MBC_DOM11_MEM3_BLK_CFG_W */
110234 #define TRDC_MBC_DOM11_MEM3_BLK_CFG_W_COUNT2     (3U)
110235 
110236 /*! @name MBC_DOM11_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
110237 /*! @{ */
110238 
110239 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
110240 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
110241 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
110242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110245  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110246  */
110247 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK)
110248 
110249 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
110250 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
110251 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
110252  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110253  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110254  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110255  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110256  */
110257 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK)
110258 
110259 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
110260 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
110261 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
110262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110265  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110266  */
110267 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK)
110268 
110269 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
110270 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
110271 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
110272  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110273  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110274  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110275  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110276  */
110277 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK)
110278 
110279 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
110280 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
110281 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
110282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110285  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110286  */
110287 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK)
110288 
110289 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
110290 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
110291 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
110292  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110293  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110294  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110295  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110296  */
110297 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK)
110298 
110299 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
110300 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
110301 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
110302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110306  */
110307 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK)
110308 
110309 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
110310 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
110311 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
110312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110316  */
110317 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK)
110318 
110319 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
110320 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
110321 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
110322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110326  */
110327 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK)
110328 
110329 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
110330 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
110331 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
110332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110336  */
110337 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK)
110338 
110339 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
110340 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
110341 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
110342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110346  */
110347 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK)
110348 
110349 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
110350 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
110351 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
110352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110356  */
110357 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK)
110358 
110359 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
110360 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
110361 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
110362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110366  */
110367 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK)
110368 
110369 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
110370 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
110371 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
110372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110376  */
110377 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK)
110378 
110379 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
110380 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
110381 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
110382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110386  */
110387 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK)
110388 
110389 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
110390 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
110391 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
110392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110396  */
110397 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK)
110398 
110399 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
110400 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
110401 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
110402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110406  */
110407 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK)
110408 
110409 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
110410 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
110411 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
110412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110416  */
110417 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK)
110418 
110419 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
110420 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
110421 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
110422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110426  */
110427 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK)
110428 
110429 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
110430 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
110431 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
110432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110436  */
110437 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK)
110438 
110439 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
110440 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
110441 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
110442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110446  */
110447 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK)
110448 
110449 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
110450 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
110451 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
110452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110456  */
110457 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK)
110458 
110459 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
110460 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
110461 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
110462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110466  */
110467 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK)
110468 
110469 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
110470 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
110471 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
110472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110476  */
110477 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK)
110478 
110479 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
110480 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
110481 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
110482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110486  */
110487 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK)
110488 
110489 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
110490 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
110491 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
110492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110496  */
110497 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK)
110498 
110499 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
110500 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
110501 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
110502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110506  */
110507 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK)
110508 
110509 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
110510 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
110511 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
110512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110516  */
110517 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK)
110518 
110519 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
110520 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
110521 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
110522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110526  */
110527 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK)
110528 
110529 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
110530 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
110531 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
110532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110536  */
110537 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK)
110538 
110539 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
110540 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
110541 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
110542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110545  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110546  */
110547 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK)
110548 
110549 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
110550 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
110551 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
110552  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110553  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110554  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110555  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110556  */
110557 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK)
110558 /*! @} */
110559 
110560 /* The count of TRDC_MBC_DOM11_MEM3_BLK_NSE_W */
110561 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_COUNT      (2U)
110562 
110563 /* The count of TRDC_MBC_DOM11_MEM3_BLK_NSE_W */
110564 #define TRDC_MBC_DOM11_MEM3_BLK_NSE_W_COUNT2     (1U)
110565 
110566 /*! @name MBC_DOM12_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
110567 /*! @{ */
110568 
110569 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
110570 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
110571 /*! MBACSEL0 - Memory Block Access Control Select for block B
110572  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110573  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110574  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110575  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110576  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110577  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110578  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110579  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110580  */
110581 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK)
110582 
110583 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
110584 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
110585 /*! NSE0 - NonSecure Enable for block B
110586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110589  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110590  */
110591 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK)
110592 
110593 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
110594 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
110595 /*! MBACSEL1 - Memory Block Access Control Select for block B
110596  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110597  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110598  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110599  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110600  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110601  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110602  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110603  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110604  */
110605 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK)
110606 
110607 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
110608 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
110609 /*! NSE1 - NonSecure Enable for block B
110610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110613  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110614  */
110615 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK)
110616 
110617 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
110618 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
110619 /*! MBACSEL2 - Memory Block Access Control Select for block B
110620  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110621  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110622  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110623  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110624  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110625  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110626  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110627  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110628  */
110629 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK)
110630 
110631 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
110632 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
110633 /*! NSE2 - NonSecure Enable for block B
110634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110637  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110638  */
110639 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK)
110640 
110641 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
110642 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
110643 /*! MBACSEL3 - Memory Block Access Control Select for block B
110644  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110645  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110646  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110647  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110648  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110649  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110650  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110651  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110652  */
110653 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK)
110654 
110655 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
110656 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
110657 /*! NSE3 - NonSecure Enable for block B
110658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110661  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110662  */
110663 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK)
110664 
110665 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
110666 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
110667 /*! MBACSEL4 - Memory Block Access Control Select for block B
110668  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110669  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110670  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110671  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110672  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110673  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110674  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110675  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110676  */
110677 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK)
110678 
110679 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
110680 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
110681 /*! NSE4 - NonSecure Enable for block B
110682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110685  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110686  */
110687 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK)
110688 
110689 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
110690 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
110691 /*! MBACSEL5 - Memory Block Access Control Select for block B
110692  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110693  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110694  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110695  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110696  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110697  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110698  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110699  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110700  */
110701 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK)
110702 
110703 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
110704 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
110705 /*! NSE5 - NonSecure Enable for block B
110706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110709  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110710  */
110711 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK)
110712 
110713 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
110714 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
110715 /*! MBACSEL6 - Memory Block Access Control Select for block B
110716  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110717  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110718  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110719  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110720  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110721  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110722  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110723  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110724  */
110725 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK)
110726 
110727 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
110728 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
110729 /*! NSE6 - NonSecure Enable for block B
110730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110733  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110734  */
110735 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK)
110736 
110737 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
110738 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
110739 /*! MBACSEL7 - Memory Block Access Control Select for block B
110740  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
110741  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
110742  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
110743  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
110744  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
110745  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
110746  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
110747  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
110748  */
110749 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK)
110750 
110751 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
110752 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
110753 /*! NSE7 - NonSecure Enable for block B
110754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
110755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110757  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110758  */
110759 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK)
110760 /*! @} */
110761 
110762 /* The count of TRDC_MBC_DOM12_MEM0_BLK_CFG_W */
110763 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_COUNT      (2U)
110764 
110765 /* The count of TRDC_MBC_DOM12_MEM0_BLK_CFG_W */
110766 #define TRDC_MBC_DOM12_MEM0_BLK_CFG_W_COUNT2     (16U)
110767 
110768 /*! @name MBC_DOM12_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
110769 /*! @{ */
110770 
110771 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
110772 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
110773 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
110774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110777  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110778  */
110779 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK)
110780 
110781 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
110782 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
110783 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
110784  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110785  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110786  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110787  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110788  */
110789 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK)
110790 
110791 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
110792 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
110793 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
110794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110797  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110798  */
110799 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK)
110800 
110801 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
110802 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
110803 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
110804  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110805  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110806  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110807  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110808  */
110809 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK)
110810 
110811 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
110812 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
110813 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
110814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110817  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110818  */
110819 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK)
110820 
110821 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
110822 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
110823 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
110824  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110825  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110826  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110827  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110828  */
110829 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK)
110830 
110831 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
110832 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
110833 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
110834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110838  */
110839 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK)
110840 
110841 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
110842 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
110843 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
110844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110848  */
110849 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK)
110850 
110851 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
110852 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
110853 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
110854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110858  */
110859 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK)
110860 
110861 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
110862 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
110863 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
110864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110868  */
110869 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK)
110870 
110871 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
110872 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
110873 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
110874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110878  */
110879 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK)
110880 
110881 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
110882 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
110883 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
110884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110888  */
110889 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK)
110890 
110891 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
110892 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
110893 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
110894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110898  */
110899 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK)
110900 
110901 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
110902 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
110903 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
110904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110908  */
110909 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK)
110910 
110911 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
110912 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
110913 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
110914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110918  */
110919 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK)
110920 
110921 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
110922 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
110923 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
110924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110928  */
110929 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK)
110930 
110931 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
110932 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
110933 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
110934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110938  */
110939 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK)
110940 
110941 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
110942 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
110943 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
110944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110948  */
110949 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK)
110950 
110951 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
110952 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
110953 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
110954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110958  */
110959 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK)
110960 
110961 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
110962 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
110963 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
110964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110968  */
110969 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK)
110970 
110971 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
110972 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
110973 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
110974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110978  */
110979 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK)
110980 
110981 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
110982 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
110983 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
110984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110988  */
110989 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK)
110990 
110991 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
110992 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
110993 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
110994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
110995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
110996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
110997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
110998  */
110999 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK)
111000 
111001 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
111002 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
111003 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
111004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111008  */
111009 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK)
111010 
111011 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
111012 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
111013 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
111014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111018  */
111019 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK)
111020 
111021 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
111022 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
111023 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
111024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111028  */
111029 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK)
111030 
111031 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
111032 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
111033 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
111034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111038  */
111039 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK)
111040 
111041 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
111042 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
111043 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
111044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111048  */
111049 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK)
111050 
111051 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
111052 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
111053 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
111054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111058  */
111059 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK)
111060 
111061 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
111062 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
111063 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
111064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111068  */
111069 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK)
111070 
111071 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
111072 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
111073 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
111074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111077  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111078  */
111079 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK)
111080 
111081 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
111082 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
111083 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
111084  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111085  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111086  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111087  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111088  */
111089 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK)
111090 /*! @} */
111091 
111092 /* The count of TRDC_MBC_DOM12_MEM0_BLK_NSE_W */
111093 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_COUNT      (2U)
111094 
111095 /* The count of TRDC_MBC_DOM12_MEM0_BLK_NSE_W */
111096 #define TRDC_MBC_DOM12_MEM0_BLK_NSE_W_COUNT2     (4U)
111097 
111098 /*! @name MBC_DOM12_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
111099 /*! @{ */
111100 
111101 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
111102 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
111103 /*! MBACSEL0 - Memory Block Access Control Select for block B
111104  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111105  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111106  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111107  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111108  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111109  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111110  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111111  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111112  */
111113 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK)
111114 
111115 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
111116 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
111117 /*! NSE0 - NonSecure Enable for block B
111118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111121  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111122  */
111123 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK)
111124 
111125 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
111126 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
111127 /*! MBACSEL1 - Memory Block Access Control Select for block B
111128  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111129  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111130  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111131  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111132  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111133  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111134  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111135  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111136  */
111137 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK)
111138 
111139 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
111140 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
111141 /*! NSE1 - NonSecure Enable for block B
111142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111145  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111146  */
111147 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK)
111148 
111149 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
111150 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
111151 /*! MBACSEL2 - Memory Block Access Control Select for block B
111152  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111153  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111154  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111155  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111156  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111157  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111158  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111159  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111160  */
111161 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK)
111162 
111163 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
111164 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
111165 /*! NSE2 - NonSecure Enable for block B
111166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111169  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111170  */
111171 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK)
111172 
111173 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
111174 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
111175 /*! MBACSEL3 - Memory Block Access Control Select for block B
111176  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111177  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111178  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111179  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111180  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111181  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111182  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111183  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111184  */
111185 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK)
111186 
111187 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
111188 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
111189 /*! NSE3 - NonSecure Enable for block B
111190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111193  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111194  */
111195 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK)
111196 
111197 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
111198 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
111199 /*! MBACSEL4 - Memory Block Access Control Select for block B
111200  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111201  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111202  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111203  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111204  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111205  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111206  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111207  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111208  */
111209 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK)
111210 
111211 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
111212 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
111213 /*! NSE4 - NonSecure Enable for block B
111214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111217  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111218  */
111219 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK)
111220 
111221 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
111222 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
111223 /*! MBACSEL5 - Memory Block Access Control Select for block B
111224  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111225  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111226  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111227  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111228  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111229  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111230  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111231  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111232  */
111233 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK)
111234 
111235 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
111236 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
111237 /*! NSE5 - NonSecure Enable for block B
111238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111241  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111242  */
111243 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK)
111244 
111245 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
111246 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
111247 /*! MBACSEL6 - Memory Block Access Control Select for block B
111248  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111249  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111250  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111251  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111252  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111253  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111254  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111255  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111256  */
111257 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK)
111258 
111259 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
111260 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
111261 /*! NSE6 - NonSecure Enable for block B
111262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111265  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111266  */
111267 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK)
111268 
111269 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
111270 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
111271 /*! MBACSEL7 - Memory Block Access Control Select for block B
111272  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111273  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111274  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111275  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111276  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111277  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111278  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111279  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111280  */
111281 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK)
111282 
111283 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
111284 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
111285 /*! NSE7 - NonSecure Enable for block B
111286  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111287  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111288  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111289  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111290  */
111291 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK)
111292 /*! @} */
111293 
111294 /* The count of TRDC_MBC_DOM12_MEM1_BLK_CFG_W */
111295 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_COUNT      (2U)
111296 
111297 /* The count of TRDC_MBC_DOM12_MEM1_BLK_CFG_W */
111298 #define TRDC_MBC_DOM12_MEM1_BLK_CFG_W_COUNT2     (4U)
111299 
111300 /*! @name MBC_DOM12_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
111301 /*! @{ */
111302 
111303 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
111304 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
111305 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
111306  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111307  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111308  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111309  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111310  */
111311 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK)
111312 
111313 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
111314 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
111315 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
111316  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111317  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111318  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111319  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111320  */
111321 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK)
111322 
111323 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
111324 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
111325 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
111326  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111327  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111328  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111329  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111330  */
111331 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK)
111332 
111333 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
111334 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
111335 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
111336  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111337  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111338  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111339  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111340  */
111341 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK)
111342 
111343 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
111344 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
111345 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
111346  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111347  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111348  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111349  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111350  */
111351 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK)
111352 
111353 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
111354 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
111355 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
111356  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111357  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111358  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111359  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111360  */
111361 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK)
111362 
111363 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
111364 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
111365 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
111366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111369  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111370  */
111371 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK)
111372 
111373 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
111374 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
111375 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
111376  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111377  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111378  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111379  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111380  */
111381 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK)
111382 
111383 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
111384 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
111385 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
111386  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111387  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111388  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111389  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111390  */
111391 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK)
111392 
111393 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
111394 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
111395 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
111396  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111397  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111398  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111399  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111400  */
111401 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK)
111402 
111403 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
111404 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
111405 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
111406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111409  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111410  */
111411 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK)
111412 
111413 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
111414 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
111415 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
111416  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111417  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111418  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111419  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111420  */
111421 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK)
111422 
111423 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
111424 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
111425 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
111426  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111427  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111428  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111429  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111430  */
111431 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK)
111432 
111433 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
111434 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
111435 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
111436  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111437  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111438  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111439  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111440  */
111441 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK)
111442 
111443 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
111444 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
111445 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
111446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111449  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111450  */
111451 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK)
111452 
111453 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
111454 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
111455 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
111456  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111457  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111458  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111459  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111460  */
111461 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK)
111462 
111463 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
111464 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
111465 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
111466  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111467  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111468  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111469  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111470  */
111471 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK)
111472 
111473 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
111474 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
111475 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
111476  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111477  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111478  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111479  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111480  */
111481 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK)
111482 
111483 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
111484 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
111485 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
111486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111489  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111490  */
111491 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK)
111492 
111493 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
111494 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
111495 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
111496  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111497  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111498  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111499  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111500  */
111501 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK)
111502 
111503 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
111504 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
111505 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
111506  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111507  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111508  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111509  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111510  */
111511 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK)
111512 
111513 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
111514 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
111515 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
111516  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111517  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111518  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111519  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111520  */
111521 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK)
111522 
111523 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
111524 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
111525 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
111526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111529  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111530  */
111531 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK)
111532 
111533 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
111534 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
111535 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
111536  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111537  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111538  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111539  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111540  */
111541 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK)
111542 
111543 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
111544 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
111545 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
111546  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111547  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111548  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111549  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111550  */
111551 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK)
111552 
111553 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
111554 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
111555 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
111556  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111557  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111558  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111559  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111560  */
111561 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK)
111562 
111563 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
111564 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
111565 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
111566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111569  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111570  */
111571 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK)
111572 
111573 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
111574 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
111575 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
111576  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111577  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111578  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111579  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111580  */
111581 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK)
111582 
111583 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
111584 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
111585 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
111586  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111587  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111588  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111589  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111590  */
111591 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK)
111592 
111593 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
111594 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
111595 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
111596  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111597  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111598  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111599  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111600  */
111601 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK)
111602 
111603 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
111604 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
111605 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
111606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111609  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111610  */
111611 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK)
111612 
111613 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
111614 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
111615 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
111616  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111617  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111618  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111619  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111620  */
111621 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK)
111622 /*! @} */
111623 
111624 /* The count of TRDC_MBC_DOM12_MEM1_BLK_NSE_W */
111625 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_COUNT      (2U)
111626 
111627 /* The count of TRDC_MBC_DOM12_MEM1_BLK_NSE_W */
111628 #define TRDC_MBC_DOM12_MEM1_BLK_NSE_W_COUNT2     (1U)
111629 
111630 /*! @name MBC_DOM12_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
111631 /*! @{ */
111632 
111633 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
111634 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
111635 /*! MBACSEL0 - Memory Block Access Control Select for block B
111636  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111637  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111638  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111639  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111640  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111641  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111642  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111643  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111644  */
111645 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK)
111646 
111647 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
111648 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
111649 /*! NSE0 - NonSecure Enable for block B
111650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111653  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111654  */
111655 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK)
111656 
111657 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
111658 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
111659 /*! MBACSEL1 - Memory Block Access Control Select for block B
111660  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111661  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111662  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111663  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111664  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111665  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111666  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111667  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111668  */
111669 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK)
111670 
111671 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
111672 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
111673 /*! NSE1 - NonSecure Enable for block B
111674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111677  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111678  */
111679 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK)
111680 
111681 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
111682 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
111683 /*! MBACSEL2 - Memory Block Access Control Select for block B
111684  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111685  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111686  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111687  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111688  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111689  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111690  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111691  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111692  */
111693 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK)
111694 
111695 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
111696 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
111697 /*! NSE2 - NonSecure Enable for block B
111698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111701  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111702  */
111703 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK)
111704 
111705 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
111706 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
111707 /*! MBACSEL3 - Memory Block Access Control Select for block B
111708  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111709  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111710  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111711  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111712  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111713  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111714  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111715  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111716  */
111717 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK)
111718 
111719 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
111720 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
111721 /*! NSE3 - NonSecure Enable for block B
111722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111725  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111726  */
111727 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK)
111728 
111729 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
111730 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
111731 /*! MBACSEL4 - Memory Block Access Control Select for block B
111732  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111733  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111734  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111735  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111736  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111737  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111738  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111739  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111740  */
111741 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK)
111742 
111743 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
111744 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
111745 /*! NSE4 - NonSecure Enable for block B
111746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111749  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111750  */
111751 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK)
111752 
111753 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
111754 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
111755 /*! MBACSEL5 - Memory Block Access Control Select for block B
111756  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111757  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111758  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111759  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111760  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111761  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111762  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111763  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111764  */
111765 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK)
111766 
111767 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
111768 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
111769 /*! NSE5 - NonSecure Enable for block B
111770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111773  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111774  */
111775 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK)
111776 
111777 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
111778 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
111779 /*! MBACSEL6 - Memory Block Access Control Select for block B
111780  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111781  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111782  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111783  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111784  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111785  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111786  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111787  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111788  */
111789 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK)
111790 
111791 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
111792 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
111793 /*! NSE6 - NonSecure Enable for block B
111794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111797  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111798  */
111799 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK)
111800 
111801 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
111802 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
111803 /*! MBACSEL7 - Memory Block Access Control Select for block B
111804  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
111805  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
111806  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
111807  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
111808  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
111809  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
111810  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
111811  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
111812  */
111813 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK)
111814 
111815 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
111816 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
111817 /*! NSE7 - NonSecure Enable for block B
111818  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
111819  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111820  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111821  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111822  */
111823 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK)
111824 /*! @} */
111825 
111826 /* The count of TRDC_MBC_DOM12_MEM2_BLK_CFG_W */
111827 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_COUNT      (2U)
111828 
111829 /* The count of TRDC_MBC_DOM12_MEM2_BLK_CFG_W */
111830 #define TRDC_MBC_DOM12_MEM2_BLK_CFG_W_COUNT2     (1U)
111831 
111832 /*! @name MBC_DOM12_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
111833 /*! @{ */
111834 
111835 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
111836 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
111837 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
111838  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111839  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111840  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111841  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111842  */
111843 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK)
111844 
111845 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
111846 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
111847 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
111848  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111849  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111850  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111851  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111852  */
111853 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK)
111854 
111855 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
111856 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
111857 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
111858  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111859  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111860  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111861  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111862  */
111863 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK)
111864 
111865 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
111866 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
111867 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
111868  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111869  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111870  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111871  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111872  */
111873 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK)
111874 
111875 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
111876 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
111877 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
111878  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111879  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111880  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111881  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111882  */
111883 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK)
111884 
111885 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
111886 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
111887 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
111888  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111889  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111890  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111891  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111892  */
111893 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK)
111894 
111895 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
111896 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
111897 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
111898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111901  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111902  */
111903 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK)
111904 
111905 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
111906 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
111907 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
111908  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111909  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111910  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111911  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111912  */
111913 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK)
111914 
111915 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
111916 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
111917 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
111918  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111919  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111920  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111921  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111922  */
111923 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK)
111924 
111925 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
111926 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
111927 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
111928  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111929  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111930  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111931  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111932  */
111933 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK)
111934 
111935 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
111936 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
111937 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
111938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111941  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111942  */
111943 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK)
111944 
111945 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
111946 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
111947 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
111948  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111949  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111950  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111951  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111952  */
111953 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK)
111954 
111955 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
111956 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
111957 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
111958  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111959  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111960  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111961  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111962  */
111963 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK)
111964 
111965 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
111966 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
111967 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
111968  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111969  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111970  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111971  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111972  */
111973 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK)
111974 
111975 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
111976 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
111977 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
111978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111981  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111982  */
111983 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK)
111984 
111985 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
111986 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
111987 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
111988  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111989  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
111990  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
111991  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
111992  */
111993 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK)
111994 
111995 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
111996 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
111997 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
111998  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
111999  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112000  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112001  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112002  */
112003 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK)
112004 
112005 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
112006 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
112007 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
112008  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112009  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112010  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112011  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112012  */
112013 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK)
112014 
112015 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
112016 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
112017 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
112018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112021  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112022  */
112023 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK)
112024 
112025 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
112026 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
112027 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
112028  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112029  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112030  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112031  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112032  */
112033 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK)
112034 
112035 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
112036 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
112037 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
112038  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112039  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112040  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112041  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112042  */
112043 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK)
112044 
112045 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
112046 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
112047 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
112048  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112049  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112050  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112051  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112052  */
112053 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK)
112054 
112055 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
112056 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
112057 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
112058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112061  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112062  */
112063 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK)
112064 
112065 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
112066 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
112067 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
112068  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112069  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112070  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112071  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112072  */
112073 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK)
112074 
112075 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
112076 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
112077 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
112078  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112079  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112080  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112081  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112082  */
112083 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK)
112084 
112085 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
112086 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
112087 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
112088  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112089  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112090  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112091  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112092  */
112093 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK)
112094 
112095 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
112096 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
112097 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
112098  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112099  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112100  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112101  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112102  */
112103 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK)
112104 
112105 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
112106 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
112107 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
112108  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112109  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112110  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112111  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112112  */
112113 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK)
112114 
112115 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
112116 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
112117 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
112118  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112119  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112120  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112121  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112122  */
112123 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK)
112124 
112125 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
112126 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
112127 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
112128  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112129  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112130  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112131  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112132  */
112133 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK)
112134 
112135 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
112136 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
112137 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
112138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112141  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112142  */
112143 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK)
112144 
112145 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
112146 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
112147 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
112148  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112149  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112150  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112151  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112152  */
112153 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK)
112154 /*! @} */
112155 
112156 /* The count of TRDC_MBC_DOM12_MEM2_BLK_NSE_W */
112157 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_COUNT      (2U)
112158 
112159 /* The count of TRDC_MBC_DOM12_MEM2_BLK_NSE_W */
112160 #define TRDC_MBC_DOM12_MEM2_BLK_NSE_W_COUNT2     (1U)
112161 
112162 /*! @name MBC_DOM12_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
112163 /*! @{ */
112164 
112165 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
112166 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
112167 /*! MBACSEL0 - Memory Block Access Control Select for block B
112168  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112169  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112170  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112171  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112172  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112173  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112174  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112175  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112176  */
112177 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK)
112178 
112179 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
112180 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
112181 /*! NSE0 - NonSecure Enable for block B
112182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112185  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112186  */
112187 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK)
112188 
112189 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
112190 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
112191 /*! MBACSEL1 - Memory Block Access Control Select for block B
112192  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112193  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112194  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112195  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112196  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112197  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112198  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112199  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112200  */
112201 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK)
112202 
112203 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
112204 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
112205 /*! NSE1 - NonSecure Enable for block B
112206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112209  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112210  */
112211 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK)
112212 
112213 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
112214 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
112215 /*! MBACSEL2 - Memory Block Access Control Select for block B
112216  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112217  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112218  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112219  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112220  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112221  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112222  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112223  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112224  */
112225 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK)
112226 
112227 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
112228 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
112229 /*! NSE2 - NonSecure Enable for block B
112230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112233  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112234  */
112235 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK)
112236 
112237 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
112238 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
112239 /*! MBACSEL3 - Memory Block Access Control Select for block B
112240  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112241  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112242  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112243  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112244  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112245  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112246  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112247  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112248  */
112249 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK)
112250 
112251 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
112252 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
112253 /*! NSE3 - NonSecure Enable for block B
112254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112257  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112258  */
112259 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK)
112260 
112261 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
112262 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
112263 /*! MBACSEL4 - Memory Block Access Control Select for block B
112264  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112265  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112266  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112267  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112268  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112269  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112270  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112271  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112272  */
112273 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK)
112274 
112275 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
112276 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
112277 /*! NSE4 - NonSecure Enable for block B
112278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112281  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112282  */
112283 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK)
112284 
112285 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
112286 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
112287 /*! MBACSEL5 - Memory Block Access Control Select for block B
112288  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112289  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112290  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112291  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112292  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112293  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112294  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112295  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112296  */
112297 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK)
112298 
112299 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
112300 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
112301 /*! NSE5 - NonSecure Enable for block B
112302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112305  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112306  */
112307 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK)
112308 
112309 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
112310 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
112311 /*! MBACSEL6 - Memory Block Access Control Select for block B
112312  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112313  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112314  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112315  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112316  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112317  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112318  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112319  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112320  */
112321 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK)
112322 
112323 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
112324 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
112325 /*! NSE6 - NonSecure Enable for block B
112326  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112327  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112328  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112329  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112330  */
112331 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK)
112332 
112333 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
112334 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
112335 /*! MBACSEL7 - Memory Block Access Control Select for block B
112336  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112337  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112338  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112339  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112340  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112341  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112342  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112343  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112344  */
112345 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK)
112346 
112347 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
112348 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
112349 /*! NSE7 - NonSecure Enable for block B
112350  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112351  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112352  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112353  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112354  */
112355 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK)
112356 /*! @} */
112357 
112358 /* The count of TRDC_MBC_DOM12_MEM3_BLK_CFG_W */
112359 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_COUNT      (2U)
112360 
112361 /* The count of TRDC_MBC_DOM12_MEM3_BLK_CFG_W */
112362 #define TRDC_MBC_DOM12_MEM3_BLK_CFG_W_COUNT2     (3U)
112363 
112364 /*! @name MBC_DOM12_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
112365 /*! @{ */
112366 
112367 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
112368 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
112369 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
112370  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112371  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112372  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112373  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112374  */
112375 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK)
112376 
112377 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
112378 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
112379 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
112380  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112381  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112382  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112383  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112384  */
112385 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK)
112386 
112387 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
112388 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
112389 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
112390  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112391  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112392  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112393  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112394  */
112395 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK)
112396 
112397 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
112398 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
112399 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
112400  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112401  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112402  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112403  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112404  */
112405 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK)
112406 
112407 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
112408 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
112409 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
112410  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112411  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112412  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112413  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112414  */
112415 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK)
112416 
112417 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
112418 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
112419 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
112420  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112421  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112422  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112423  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112424  */
112425 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK)
112426 
112427 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
112428 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
112429 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
112430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112433  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112434  */
112435 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK)
112436 
112437 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
112438 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
112439 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
112440  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112441  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112442  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112443  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112444  */
112445 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK)
112446 
112447 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
112448 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
112449 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
112450  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112451  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112452  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112453  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112454  */
112455 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK)
112456 
112457 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
112458 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
112459 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
112460  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112461  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112462  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112463  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112464  */
112465 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK)
112466 
112467 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
112468 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
112469 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
112470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112473  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112474  */
112475 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK)
112476 
112477 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
112478 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
112479 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
112480  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112481  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112482  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112483  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112484  */
112485 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK)
112486 
112487 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
112488 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
112489 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
112490  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112491  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112492  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112493  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112494  */
112495 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK)
112496 
112497 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
112498 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
112499 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
112500  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112501  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112502  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112503  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112504  */
112505 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK)
112506 
112507 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
112508 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
112509 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
112510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112513  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112514  */
112515 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK)
112516 
112517 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
112518 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
112519 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
112520  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112521  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112522  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112523  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112524  */
112525 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK)
112526 
112527 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
112528 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
112529 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
112530  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112531  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112532  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112533  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112534  */
112535 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK)
112536 
112537 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
112538 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
112539 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
112540  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112541  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112542  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112543  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112544  */
112545 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK)
112546 
112547 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
112548 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
112549 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
112550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112553  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112554  */
112555 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK)
112556 
112557 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
112558 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
112559 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
112560  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112561  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112562  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112563  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112564  */
112565 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK)
112566 
112567 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
112568 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
112569 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
112570  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112571  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112572  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112573  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112574  */
112575 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK)
112576 
112577 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
112578 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
112579 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
112580  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112581  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112582  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112583  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112584  */
112585 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK)
112586 
112587 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
112588 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
112589 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
112590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112593  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112594  */
112595 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK)
112596 
112597 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
112598 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
112599 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
112600  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112601  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112602  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112603  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112604  */
112605 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK)
112606 
112607 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
112608 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
112609 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
112610  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112611  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112612  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112613  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112614  */
112615 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK)
112616 
112617 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
112618 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
112619 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
112620  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112621  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112622  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112623  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112624  */
112625 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK)
112626 
112627 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
112628 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
112629 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
112630  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112631  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112632  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112633  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112634  */
112635 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK)
112636 
112637 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
112638 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
112639 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
112640  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112641  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112642  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112643  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112644  */
112645 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK)
112646 
112647 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
112648 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
112649 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
112650  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112651  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112652  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112653  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112654  */
112655 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK)
112656 
112657 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
112658 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
112659 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
112660  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112661  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112662  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112663  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112664  */
112665 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK)
112666 
112667 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
112668 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
112669 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
112670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112673  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112674  */
112675 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK)
112676 
112677 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
112678 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
112679 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
112680  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112681  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112682  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112683  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112684  */
112685 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK)
112686 /*! @} */
112687 
112688 /* The count of TRDC_MBC_DOM12_MEM3_BLK_NSE_W */
112689 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_COUNT      (2U)
112690 
112691 /* The count of TRDC_MBC_DOM12_MEM3_BLK_NSE_W */
112692 #define TRDC_MBC_DOM12_MEM3_BLK_NSE_W_COUNT2     (1U)
112693 
112694 /*! @name MBC_DOM13_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
112695 /*! @{ */
112696 
112697 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
112698 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
112699 /*! MBACSEL0 - Memory Block Access Control Select for block B
112700  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112701  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112702  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112703  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112704  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112705  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112706  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112707  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112708  */
112709 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK)
112710 
112711 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
112712 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
112713 /*! NSE0 - NonSecure Enable for block B
112714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112717  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112718  */
112719 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK)
112720 
112721 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
112722 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
112723 /*! MBACSEL1 - Memory Block Access Control Select for block B
112724  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112725  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112726  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112727  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112728  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112729  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112730  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112731  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112732  */
112733 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK)
112734 
112735 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
112736 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
112737 /*! NSE1 - NonSecure Enable for block B
112738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112741  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112742  */
112743 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK)
112744 
112745 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
112746 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
112747 /*! MBACSEL2 - Memory Block Access Control Select for block B
112748  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112749  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112750  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112751  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112752  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112753  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112754  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112755  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112756  */
112757 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK)
112758 
112759 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
112760 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
112761 /*! NSE2 - NonSecure Enable for block B
112762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112765  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112766  */
112767 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK)
112768 
112769 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
112770 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
112771 /*! MBACSEL3 - Memory Block Access Control Select for block B
112772  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112773  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112774  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112775  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112776  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112777  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112778  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112779  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112780  */
112781 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK)
112782 
112783 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
112784 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
112785 /*! NSE3 - NonSecure Enable for block B
112786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112789  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112790  */
112791 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK)
112792 
112793 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
112794 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
112795 /*! MBACSEL4 - Memory Block Access Control Select for block B
112796  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112797  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112798  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112799  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112800  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112801  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112802  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112803  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112804  */
112805 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK)
112806 
112807 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
112808 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
112809 /*! NSE4 - NonSecure Enable for block B
112810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112813  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112814  */
112815 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK)
112816 
112817 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
112818 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
112819 /*! MBACSEL5 - Memory Block Access Control Select for block B
112820  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112821  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112822  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112823  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112824  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112825  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112826  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112827  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112828  */
112829 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK)
112830 
112831 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
112832 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
112833 /*! NSE5 - NonSecure Enable for block B
112834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112837  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112838  */
112839 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK)
112840 
112841 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
112842 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
112843 /*! MBACSEL6 - Memory Block Access Control Select for block B
112844  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112845  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112846  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112847  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112848  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112849  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112850  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112851  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112852  */
112853 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK)
112854 
112855 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
112856 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
112857 /*! NSE6 - NonSecure Enable for block B
112858  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112859  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112860  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112861  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112862  */
112863 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK)
112864 
112865 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
112866 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
112867 /*! MBACSEL7 - Memory Block Access Control Select for block B
112868  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
112869  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
112870  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
112871  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
112872  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
112873  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
112874  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
112875  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
112876  */
112877 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK)
112878 
112879 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
112880 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
112881 /*! NSE7 - NonSecure Enable for block B
112882  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
112883  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112884  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112885  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112886  */
112887 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK)
112888 /*! @} */
112889 
112890 /* The count of TRDC_MBC_DOM13_MEM0_BLK_CFG_W */
112891 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_COUNT      (2U)
112892 
112893 /* The count of TRDC_MBC_DOM13_MEM0_BLK_CFG_W */
112894 #define TRDC_MBC_DOM13_MEM0_BLK_CFG_W_COUNT2     (16U)
112895 
112896 /*! @name MBC_DOM13_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
112897 /*! @{ */
112898 
112899 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
112900 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
112901 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
112902  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112903  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112904  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112905  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112906  */
112907 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK)
112908 
112909 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
112910 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
112911 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
112912  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112913  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112914  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112915  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112916  */
112917 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK)
112918 
112919 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
112920 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
112921 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
112922  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112923  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112924  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112925  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112926  */
112927 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK)
112928 
112929 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
112930 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
112931 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
112932  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112933  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112934  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112935  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112936  */
112937 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK)
112938 
112939 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
112940 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
112941 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
112942  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112943  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112944  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112945  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112946  */
112947 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK)
112948 
112949 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
112950 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
112951 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
112952  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112953  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112954  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112955  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112956  */
112957 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK)
112958 
112959 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
112960 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
112961 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
112962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112965  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112966  */
112967 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK)
112968 
112969 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
112970 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
112971 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
112972  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112973  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112974  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112975  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112976  */
112977 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK)
112978 
112979 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
112980 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
112981 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
112982  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112983  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112984  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112985  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112986  */
112987 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK)
112988 
112989 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
112990 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
112991 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
112992  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
112993  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
112994  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
112995  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
112996  */
112997 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK)
112998 
112999 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
113000 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
113001 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
113002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113005  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113006  */
113007 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK)
113008 
113009 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
113010 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
113011 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
113012  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113013  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113014  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113015  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113016  */
113017 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK)
113018 
113019 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
113020 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
113021 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
113022  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113023  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113024  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113025  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113026  */
113027 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK)
113028 
113029 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
113030 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
113031 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
113032  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113033  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113034  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113035  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113036  */
113037 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK)
113038 
113039 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
113040 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
113041 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
113042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113045  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113046  */
113047 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK)
113048 
113049 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
113050 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
113051 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
113052  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113053  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113054  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113055  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113056  */
113057 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK)
113058 
113059 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
113060 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
113061 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
113062  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113063  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113064  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113065  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113066  */
113067 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK)
113068 
113069 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
113070 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
113071 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
113072  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113073  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113074  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113075  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113076  */
113077 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK)
113078 
113079 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
113080 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
113081 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
113082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113085  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113086  */
113087 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK)
113088 
113089 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
113090 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
113091 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
113092  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113093  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113094  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113095  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113096  */
113097 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK)
113098 
113099 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
113100 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
113101 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
113102  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113103  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113104  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113105  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113106  */
113107 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK)
113108 
113109 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
113110 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
113111 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
113112  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113113  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113114  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113115  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113116  */
113117 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK)
113118 
113119 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
113120 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
113121 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
113122  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113123  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113124  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113125  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113126  */
113127 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK)
113128 
113129 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
113130 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
113131 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
113132  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113133  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113134  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113135  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113136  */
113137 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK)
113138 
113139 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
113140 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
113141 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
113142  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113143  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113144  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113145  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113146  */
113147 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK)
113148 
113149 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
113150 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
113151 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
113152  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113153  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113154  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113155  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113156  */
113157 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK)
113158 
113159 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
113160 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
113161 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
113162  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113163  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113164  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113165  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113166  */
113167 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK)
113168 
113169 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
113170 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
113171 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
113172  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113173  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113174  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113175  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113176  */
113177 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK)
113178 
113179 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
113180 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
113181 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
113182  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113183  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113184  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113185  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113186  */
113187 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK)
113188 
113189 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
113190 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
113191 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
113192  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113193  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113194  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113195  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113196  */
113197 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK)
113198 
113199 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
113200 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
113201 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
113202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113205  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113206  */
113207 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK)
113208 
113209 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
113210 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
113211 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
113212  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113213  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113214  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113215  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113216  */
113217 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK)
113218 /*! @} */
113219 
113220 /* The count of TRDC_MBC_DOM13_MEM0_BLK_NSE_W */
113221 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_COUNT      (2U)
113222 
113223 /* The count of TRDC_MBC_DOM13_MEM0_BLK_NSE_W */
113224 #define TRDC_MBC_DOM13_MEM0_BLK_NSE_W_COUNT2     (4U)
113225 
113226 /*! @name MBC_DOM13_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
113227 /*! @{ */
113228 
113229 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
113230 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
113231 /*! MBACSEL0 - Memory Block Access Control Select for block B
113232  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113233  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113234  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113235  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113236  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113237  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113238  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113239  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113240  */
113241 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK)
113242 
113243 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
113244 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
113245 /*! NSE0 - NonSecure Enable for block B
113246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113249  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113250  */
113251 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK)
113252 
113253 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
113254 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
113255 /*! MBACSEL1 - Memory Block Access Control Select for block B
113256  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113257  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113258  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113259  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113260  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113261  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113262  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113263  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113264  */
113265 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK)
113266 
113267 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
113268 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
113269 /*! NSE1 - NonSecure Enable for block B
113270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113273  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113274  */
113275 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK)
113276 
113277 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
113278 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
113279 /*! MBACSEL2 - Memory Block Access Control Select for block B
113280  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113281  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113282  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113283  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113284  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113285  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113286  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113287  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113288  */
113289 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK)
113290 
113291 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
113292 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
113293 /*! NSE2 - NonSecure Enable for block B
113294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113297  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113298  */
113299 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK)
113300 
113301 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
113302 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
113303 /*! MBACSEL3 - Memory Block Access Control Select for block B
113304  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113305  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113306  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113307  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113308  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113309  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113310  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113311  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113312  */
113313 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK)
113314 
113315 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
113316 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
113317 /*! NSE3 - NonSecure Enable for block B
113318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113321  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113322  */
113323 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK)
113324 
113325 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
113326 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
113327 /*! MBACSEL4 - Memory Block Access Control Select for block B
113328  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113329  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113330  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113331  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113332  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113333  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113334  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113335  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113336  */
113337 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK)
113338 
113339 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
113340 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
113341 /*! NSE4 - NonSecure Enable for block B
113342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113345  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113346  */
113347 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK)
113348 
113349 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
113350 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
113351 /*! MBACSEL5 - Memory Block Access Control Select for block B
113352  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113353  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113354  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113355  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113356  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113357  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113358  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113359  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113360  */
113361 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK)
113362 
113363 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
113364 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
113365 /*! NSE5 - NonSecure Enable for block B
113366  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113367  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113368  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113369  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113370  */
113371 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK)
113372 
113373 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
113374 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
113375 /*! MBACSEL6 - Memory Block Access Control Select for block B
113376  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113377  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113378  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113379  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113380  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113381  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113382  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113383  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113384  */
113385 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK)
113386 
113387 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
113388 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
113389 /*! NSE6 - NonSecure Enable for block B
113390  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113391  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113392  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113393  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113394  */
113395 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK)
113396 
113397 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
113398 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
113399 /*! MBACSEL7 - Memory Block Access Control Select for block B
113400  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113401  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113402  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113403  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113404  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113405  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113406  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113407  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113408  */
113409 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK)
113410 
113411 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
113412 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
113413 /*! NSE7 - NonSecure Enable for block B
113414  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113415  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113416  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113417  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113418  */
113419 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK)
113420 /*! @} */
113421 
113422 /* The count of TRDC_MBC_DOM13_MEM1_BLK_CFG_W */
113423 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_COUNT      (2U)
113424 
113425 /* The count of TRDC_MBC_DOM13_MEM1_BLK_CFG_W */
113426 #define TRDC_MBC_DOM13_MEM1_BLK_CFG_W_COUNT2     (4U)
113427 
113428 /*! @name MBC_DOM13_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
113429 /*! @{ */
113430 
113431 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
113432 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
113433 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
113434  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113435  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113436  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113437  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113438  */
113439 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK)
113440 
113441 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
113442 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
113443 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
113444  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113445  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113446  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113447  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113448  */
113449 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK)
113450 
113451 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
113452 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
113453 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
113454  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113455  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113456  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113457  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113458  */
113459 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK)
113460 
113461 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
113462 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
113463 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
113464  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113465  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113466  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113467  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113468  */
113469 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK)
113470 
113471 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
113472 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
113473 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
113474  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113475  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113476  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113477  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113478  */
113479 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK)
113480 
113481 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
113482 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
113483 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
113484  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113485  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113486  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113487  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113488  */
113489 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK)
113490 
113491 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
113492 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
113493 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
113494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113497  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113498  */
113499 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK)
113500 
113501 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
113502 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
113503 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
113504  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113505  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113506  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113507  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113508  */
113509 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK)
113510 
113511 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
113512 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
113513 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
113514  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113515  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113516  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113517  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113518  */
113519 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK)
113520 
113521 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
113522 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
113523 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
113524  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113525  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113526  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113527  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113528  */
113529 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK)
113530 
113531 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
113532 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
113533 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
113534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113537  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113538  */
113539 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK)
113540 
113541 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
113542 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
113543 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
113544  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113545  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113546  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113547  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113548  */
113549 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK)
113550 
113551 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
113552 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
113553 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
113554  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113555  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113556  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113557  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113558  */
113559 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK)
113560 
113561 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
113562 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
113563 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
113564  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113565  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113566  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113567  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113568  */
113569 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK)
113570 
113571 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
113572 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
113573 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
113574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113577  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113578  */
113579 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK)
113580 
113581 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
113582 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
113583 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
113584  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113585  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113586  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113587  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113588  */
113589 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK)
113590 
113591 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
113592 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
113593 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
113594  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113595  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113596  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113597  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113598  */
113599 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK)
113600 
113601 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
113602 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
113603 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
113604  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113605  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113606  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113607  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113608  */
113609 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK)
113610 
113611 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
113612 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
113613 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
113614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113617  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113618  */
113619 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK)
113620 
113621 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
113622 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
113623 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
113624  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113625  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113626  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113627  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113628  */
113629 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK)
113630 
113631 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
113632 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
113633 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
113634  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113635  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113636  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113637  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113638  */
113639 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK)
113640 
113641 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
113642 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
113643 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
113644  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113645  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113646  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113647  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113648  */
113649 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK)
113650 
113651 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
113652 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
113653 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
113654  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113655  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113656  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113657  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113658  */
113659 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK)
113660 
113661 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
113662 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
113663 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
113664  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113665  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113666  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113667  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113668  */
113669 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK)
113670 
113671 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
113672 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
113673 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
113674  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113675  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113676  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113677  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113678  */
113679 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK)
113680 
113681 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
113682 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
113683 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
113684  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113685  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113686  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113687  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113688  */
113689 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK)
113690 
113691 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
113692 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
113693 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
113694  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113695  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113696  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113697  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113698  */
113699 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK)
113700 
113701 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
113702 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
113703 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
113704  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113705  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113706  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113707  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113708  */
113709 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK)
113710 
113711 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
113712 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
113713 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
113714  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113715  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113716  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113717  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113718  */
113719 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK)
113720 
113721 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
113722 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
113723 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
113724  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113725  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113726  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113727  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113728  */
113729 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK)
113730 
113731 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
113732 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
113733 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
113734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113737  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113738  */
113739 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK)
113740 
113741 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
113742 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
113743 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
113744  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113745  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113746  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113747  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113748  */
113749 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK)
113750 /*! @} */
113751 
113752 /* The count of TRDC_MBC_DOM13_MEM1_BLK_NSE_W */
113753 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_COUNT      (2U)
113754 
113755 /* The count of TRDC_MBC_DOM13_MEM1_BLK_NSE_W */
113756 #define TRDC_MBC_DOM13_MEM1_BLK_NSE_W_COUNT2     (1U)
113757 
113758 /*! @name MBC_DOM13_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
113759 /*! @{ */
113760 
113761 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
113762 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
113763 /*! MBACSEL0 - Memory Block Access Control Select for block B
113764  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113765  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113766  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113767  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113768  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113769  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113770  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113771  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113772  */
113773 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK)
113774 
113775 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
113776 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
113777 /*! NSE0 - NonSecure Enable for block B
113778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113781  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113782  */
113783 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK)
113784 
113785 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
113786 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
113787 /*! MBACSEL1 - Memory Block Access Control Select for block B
113788  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113789  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113790  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113791  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113792  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113793  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113794  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113795  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113796  */
113797 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK)
113798 
113799 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
113800 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
113801 /*! NSE1 - NonSecure Enable for block B
113802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113805  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113806  */
113807 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK)
113808 
113809 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
113810 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
113811 /*! MBACSEL2 - Memory Block Access Control Select for block B
113812  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113813  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113814  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113815  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113816  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113817  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113818  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113819  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113820  */
113821 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK)
113822 
113823 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
113824 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
113825 /*! NSE2 - NonSecure Enable for block B
113826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113829  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113830  */
113831 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK)
113832 
113833 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
113834 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
113835 /*! MBACSEL3 - Memory Block Access Control Select for block B
113836  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113837  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113838  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113839  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113840  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113841  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113842  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113843  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113844  */
113845 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK)
113846 
113847 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
113848 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
113849 /*! NSE3 - NonSecure Enable for block B
113850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113853  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113854  */
113855 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK)
113856 
113857 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
113858 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
113859 /*! MBACSEL4 - Memory Block Access Control Select for block B
113860  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113861  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113862  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113863  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113864  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113865  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113866  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113867  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113868  */
113869 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK)
113870 
113871 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
113872 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
113873 /*! NSE4 - NonSecure Enable for block B
113874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113877  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113878  */
113879 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK)
113880 
113881 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
113882 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
113883 /*! MBACSEL5 - Memory Block Access Control Select for block B
113884  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113885  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113886  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113887  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113888  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113889  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113890  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113891  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113892  */
113893 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK)
113894 
113895 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
113896 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
113897 /*! NSE5 - NonSecure Enable for block B
113898  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113899  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113900  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113901  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113902  */
113903 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK)
113904 
113905 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
113906 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
113907 /*! MBACSEL6 - Memory Block Access Control Select for block B
113908  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113909  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113910  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113911  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113912  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113913  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113914  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113915  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113916  */
113917 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK)
113918 
113919 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
113920 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
113921 /*! NSE6 - NonSecure Enable for block B
113922  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113923  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113924  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113925  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113926  */
113927 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK)
113928 
113929 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
113930 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
113931 /*! MBACSEL7 - Memory Block Access Control Select for block B
113932  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
113933  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
113934  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
113935  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
113936  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
113937  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
113938  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
113939  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
113940  */
113941 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK)
113942 
113943 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
113944 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
113945 /*! NSE7 - NonSecure Enable for block B
113946  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
113947  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113948  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113949  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113950  */
113951 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK)
113952 /*! @} */
113953 
113954 /* The count of TRDC_MBC_DOM13_MEM2_BLK_CFG_W */
113955 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_COUNT      (2U)
113956 
113957 /* The count of TRDC_MBC_DOM13_MEM2_BLK_CFG_W */
113958 #define TRDC_MBC_DOM13_MEM2_BLK_CFG_W_COUNT2     (1U)
113959 
113960 /*! @name MBC_DOM13_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
113961 /*! @{ */
113962 
113963 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
113964 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
113965 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
113966  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113967  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113968  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113969  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113970  */
113971 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK)
113972 
113973 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
113974 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
113975 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
113976  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113977  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113978  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113979  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113980  */
113981 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK)
113982 
113983 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
113984 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
113985 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
113986  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113987  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113988  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113989  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
113990  */
113991 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK)
113992 
113993 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
113994 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
113995 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
113996  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
113997  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
113998  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
113999  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114000  */
114001 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK)
114002 
114003 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
114004 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
114005 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
114006  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114007  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114008  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114009  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114010  */
114011 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK)
114012 
114013 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
114014 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
114015 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
114016  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114017  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114018  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114019  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114020  */
114021 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK)
114022 
114023 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
114024 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
114025 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
114026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114029  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114030  */
114031 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK)
114032 
114033 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
114034 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
114035 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
114036  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114037  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114038  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114039  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114040  */
114041 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK)
114042 
114043 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
114044 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
114045 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
114046  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114047  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114048  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114049  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114050  */
114051 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK)
114052 
114053 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
114054 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
114055 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
114056  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114057  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114058  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114059  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114060  */
114061 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK)
114062 
114063 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
114064 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
114065 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
114066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114069  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114070  */
114071 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK)
114072 
114073 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
114074 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
114075 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
114076  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114077  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114078  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114079  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114080  */
114081 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK)
114082 
114083 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
114084 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
114085 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
114086  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114087  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114088  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114089  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114090  */
114091 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK)
114092 
114093 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
114094 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
114095 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
114096  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114097  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114098  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114099  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114100  */
114101 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK)
114102 
114103 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
114104 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
114105 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
114106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114109  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114110  */
114111 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK)
114112 
114113 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
114114 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
114115 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
114116  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114117  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114118  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114119  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114120  */
114121 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK)
114122 
114123 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
114124 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
114125 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
114126  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114127  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114128  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114129  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114130  */
114131 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK)
114132 
114133 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
114134 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
114135 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
114136  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114137  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114138  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114139  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114140  */
114141 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK)
114142 
114143 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
114144 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
114145 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
114146  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114147  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114148  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114149  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114150  */
114151 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK)
114152 
114153 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
114154 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
114155 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
114156  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114157  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114158  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114159  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114160  */
114161 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK)
114162 
114163 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
114164 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
114165 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
114166  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114167  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114168  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114169  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114170  */
114171 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK)
114172 
114173 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
114174 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
114175 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
114176  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114177  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114178  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114179  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114180  */
114181 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK)
114182 
114183 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
114184 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
114185 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
114186  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114187  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114188  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114189  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114190  */
114191 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK)
114192 
114193 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
114194 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
114195 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
114196  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114197  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114198  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114199  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114200  */
114201 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK)
114202 
114203 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
114204 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
114205 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
114206  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114207  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114208  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114209  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114210  */
114211 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK)
114212 
114213 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
114214 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
114215 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
114216  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114217  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114218  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114219  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114220  */
114221 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK)
114222 
114223 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
114224 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
114225 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
114226  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114227  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114228  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114229  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114230  */
114231 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK)
114232 
114233 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
114234 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
114235 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
114236  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114237  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114238  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114239  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114240  */
114241 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK)
114242 
114243 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
114244 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
114245 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
114246  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114247  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114248  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114249  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114250  */
114251 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK)
114252 
114253 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
114254 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
114255 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
114256  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114257  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114258  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114259  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114260  */
114261 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK)
114262 
114263 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
114264 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
114265 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
114266  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114267  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114268  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114269  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114270  */
114271 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK)
114272 
114273 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
114274 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
114275 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
114276  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114277  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114278  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114279  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114280  */
114281 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK)
114282 /*! @} */
114283 
114284 /* The count of TRDC_MBC_DOM13_MEM2_BLK_NSE_W */
114285 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_COUNT      (2U)
114286 
114287 /* The count of TRDC_MBC_DOM13_MEM2_BLK_NSE_W */
114288 #define TRDC_MBC_DOM13_MEM2_BLK_NSE_W_COUNT2     (1U)
114289 
114290 /*! @name MBC_DOM13_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
114291 /*! @{ */
114292 
114293 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
114294 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
114295 /*! MBACSEL0 - Memory Block Access Control Select for block B
114296  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114297  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114298  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114299  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114300  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114301  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114302  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114303  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114304  */
114305 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK)
114306 
114307 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
114308 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
114309 /*! NSE0 - NonSecure Enable for block B
114310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114313  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114314  */
114315 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK)
114316 
114317 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
114318 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
114319 /*! MBACSEL1 - Memory Block Access Control Select for block B
114320  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114321  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114322  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114323  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114324  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114325  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114326  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114327  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114328  */
114329 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK)
114330 
114331 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
114332 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
114333 /*! NSE1 - NonSecure Enable for block B
114334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114337  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114338  */
114339 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK)
114340 
114341 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
114342 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
114343 /*! MBACSEL2 - Memory Block Access Control Select for block B
114344  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114345  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114346  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114347  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114348  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114349  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114350  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114351  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114352  */
114353 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK)
114354 
114355 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
114356 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
114357 /*! NSE2 - NonSecure Enable for block B
114358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114361  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114362  */
114363 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK)
114364 
114365 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
114366 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
114367 /*! MBACSEL3 - Memory Block Access Control Select for block B
114368  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114369  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114370  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114371  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114372  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114373  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114374  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114375  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114376  */
114377 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK)
114378 
114379 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
114380 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
114381 /*! NSE3 - NonSecure Enable for block B
114382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114385  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114386  */
114387 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK)
114388 
114389 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
114390 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
114391 /*! MBACSEL4 - Memory Block Access Control Select for block B
114392  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114393  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114394  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114395  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114396  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114397  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114398  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114399  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114400  */
114401 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK)
114402 
114403 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
114404 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
114405 /*! NSE4 - NonSecure Enable for block B
114406  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114407  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114408  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114409  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114410  */
114411 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK)
114412 
114413 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
114414 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
114415 /*! MBACSEL5 - Memory Block Access Control Select for block B
114416  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114417  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114418  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114419  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114420  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114421  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114422  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114423  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114424  */
114425 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK)
114426 
114427 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
114428 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
114429 /*! NSE5 - NonSecure Enable for block B
114430  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114431  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114432  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114433  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114434  */
114435 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK)
114436 
114437 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
114438 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
114439 /*! MBACSEL6 - Memory Block Access Control Select for block B
114440  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114441  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114442  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114443  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114444  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114445  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114446  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114447  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114448  */
114449 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK)
114450 
114451 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
114452 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
114453 /*! NSE6 - NonSecure Enable for block B
114454  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114455  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114456  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114457  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114458  */
114459 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK)
114460 
114461 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
114462 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
114463 /*! MBACSEL7 - Memory Block Access Control Select for block B
114464  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114465  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114466  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114467  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114468  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114469  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114470  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114471  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114472  */
114473 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK)
114474 
114475 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
114476 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
114477 /*! NSE7 - NonSecure Enable for block B
114478  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114479  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114480  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114481  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114482  */
114483 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK)
114484 /*! @} */
114485 
114486 /* The count of TRDC_MBC_DOM13_MEM3_BLK_CFG_W */
114487 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_COUNT      (2U)
114488 
114489 /* The count of TRDC_MBC_DOM13_MEM3_BLK_CFG_W */
114490 #define TRDC_MBC_DOM13_MEM3_BLK_CFG_W_COUNT2     (3U)
114491 
114492 /*! @name MBC_DOM13_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
114493 /*! @{ */
114494 
114495 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
114496 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
114497 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
114498  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114499  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114500  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114501  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114502  */
114503 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK)
114504 
114505 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
114506 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
114507 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
114508  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114509  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114510  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114511  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114512  */
114513 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK)
114514 
114515 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
114516 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
114517 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
114518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114521  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114522  */
114523 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK)
114524 
114525 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
114526 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
114527 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
114528  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114529  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114530  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114531  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114532  */
114533 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK)
114534 
114535 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
114536 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
114537 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
114538  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114539  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114540  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114541  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114542  */
114543 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK)
114544 
114545 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
114546 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
114547 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
114548  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114549  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114550  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114551  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114552  */
114553 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK)
114554 
114555 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
114556 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
114557 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
114558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114561  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114562  */
114563 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK)
114564 
114565 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
114566 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
114567 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
114568  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114569  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114570  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114571  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114572  */
114573 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK)
114574 
114575 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
114576 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
114577 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
114578  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114579  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114580  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114581  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114582  */
114583 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK)
114584 
114585 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
114586 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
114587 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
114588  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114589  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114590  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114591  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114592  */
114593 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK)
114594 
114595 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
114596 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
114597 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
114598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114601  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114602  */
114603 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK)
114604 
114605 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
114606 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
114607 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
114608  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114609  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114610  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114611  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114612  */
114613 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK)
114614 
114615 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
114616 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
114617 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
114618  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114619  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114620  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114621  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114622  */
114623 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK)
114624 
114625 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
114626 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
114627 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
114628  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114629  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114630  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114631  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114632  */
114633 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK)
114634 
114635 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
114636 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
114637 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
114638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114641  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114642  */
114643 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK)
114644 
114645 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
114646 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
114647 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
114648  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114649  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114650  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114651  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114652  */
114653 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK)
114654 
114655 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
114656 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
114657 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
114658  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114659  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114660  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114661  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114662  */
114663 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK)
114664 
114665 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
114666 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
114667 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
114668  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114669  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114670  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114671  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114672  */
114673 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK)
114674 
114675 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
114676 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
114677 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
114678  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114679  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114680  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114681  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114682  */
114683 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK)
114684 
114685 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
114686 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
114687 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
114688  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114689  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114690  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114691  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114692  */
114693 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK)
114694 
114695 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
114696 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
114697 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
114698  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114699  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114700  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114701  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114702  */
114703 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK)
114704 
114705 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
114706 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
114707 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
114708  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114709  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114710  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114711  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114712  */
114713 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK)
114714 
114715 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
114716 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
114717 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
114718  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114719  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114720  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114721  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114722  */
114723 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK)
114724 
114725 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
114726 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
114727 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
114728  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114729  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114730  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114731  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114732  */
114733 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK)
114734 
114735 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
114736 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
114737 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
114738  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114739  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114740  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114741  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114742  */
114743 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK)
114744 
114745 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
114746 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
114747 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
114748  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114749  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114750  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114751  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114752  */
114753 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK)
114754 
114755 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
114756 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
114757 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
114758  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114759  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114760  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114761  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114762  */
114763 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK)
114764 
114765 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
114766 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
114767 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
114768  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114769  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114770  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114771  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114772  */
114773 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK)
114774 
114775 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
114776 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
114777 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
114778  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114779  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114780  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114781  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114782  */
114783 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK)
114784 
114785 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
114786 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
114787 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
114788  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114789  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114790  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114791  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114792  */
114793 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK)
114794 
114795 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
114796 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
114797 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
114798  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114799  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114800  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114801  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114802  */
114803 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK)
114804 
114805 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
114806 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
114807 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
114808  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
114809  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114810  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114811  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114812  */
114813 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK)
114814 /*! @} */
114815 
114816 /* The count of TRDC_MBC_DOM13_MEM3_BLK_NSE_W */
114817 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_COUNT      (2U)
114818 
114819 /* The count of TRDC_MBC_DOM13_MEM3_BLK_NSE_W */
114820 #define TRDC_MBC_DOM13_MEM3_BLK_NSE_W_COUNT2     (1U)
114821 
114822 /*! @name MBC_DOM14_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
114823 /*! @{ */
114824 
114825 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
114826 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
114827 /*! MBACSEL0 - Memory Block Access Control Select for block B
114828  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114829  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114830  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114831  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114832  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114833  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114834  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114835  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114836  */
114837 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK)
114838 
114839 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
114840 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
114841 /*! NSE0 - NonSecure Enable for block B
114842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114845  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114846  */
114847 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK)
114848 
114849 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
114850 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
114851 /*! MBACSEL1 - Memory Block Access Control Select for block B
114852  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114853  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114854  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114855  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114856  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114857  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114858  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114859  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114860  */
114861 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK)
114862 
114863 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
114864 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
114865 /*! NSE1 - NonSecure Enable for block B
114866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114869  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114870  */
114871 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK)
114872 
114873 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
114874 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
114875 /*! MBACSEL2 - Memory Block Access Control Select for block B
114876  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114877  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114878  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114879  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114880  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114881  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114882  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114883  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114884  */
114885 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK)
114886 
114887 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
114888 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
114889 /*! NSE2 - NonSecure Enable for block B
114890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114893  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114894  */
114895 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK)
114896 
114897 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
114898 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
114899 /*! MBACSEL3 - Memory Block Access Control Select for block B
114900  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114901  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114902  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114903  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114904  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114905  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114906  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114907  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114908  */
114909 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK)
114910 
114911 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
114912 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
114913 /*! NSE3 - NonSecure Enable for block B
114914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114917  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114918  */
114919 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK)
114920 
114921 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
114922 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
114923 /*! MBACSEL4 - Memory Block Access Control Select for block B
114924  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114925  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114926  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114927  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114928  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114929  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114930  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114931  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114932  */
114933 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK)
114934 
114935 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
114936 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
114937 /*! NSE4 - NonSecure Enable for block B
114938  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114939  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114940  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114941  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114942  */
114943 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK)
114944 
114945 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
114946 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
114947 /*! MBACSEL5 - Memory Block Access Control Select for block B
114948  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114949  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114950  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114951  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114952  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114953  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114954  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114955  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114956  */
114957 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK)
114958 
114959 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
114960 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
114961 /*! NSE5 - NonSecure Enable for block B
114962  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114963  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114964  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114965  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114966  */
114967 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK)
114968 
114969 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
114970 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
114971 /*! MBACSEL6 - Memory Block Access Control Select for block B
114972  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114973  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114974  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114975  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
114976  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
114977  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
114978  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
114979  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
114980  */
114981 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK)
114982 
114983 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
114984 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
114985 /*! NSE6 - NonSecure Enable for block B
114986  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
114987  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
114988  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
114989  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
114990  */
114991 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK)
114992 
114993 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
114994 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
114995 /*! MBACSEL7 - Memory Block Access Control Select for block B
114996  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
114997  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
114998  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
114999  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115000  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115001  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115002  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115003  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115004  */
115005 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK)
115006 
115007 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
115008 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
115009 /*! NSE7 - NonSecure Enable for block B
115010  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115011  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115012  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115013  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115014  */
115015 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK)
115016 /*! @} */
115017 
115018 /* The count of TRDC_MBC_DOM14_MEM0_BLK_CFG_W */
115019 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_COUNT      (2U)
115020 
115021 /* The count of TRDC_MBC_DOM14_MEM0_BLK_CFG_W */
115022 #define TRDC_MBC_DOM14_MEM0_BLK_CFG_W_COUNT2     (16U)
115023 
115024 /*! @name MBC_DOM14_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
115025 /*! @{ */
115026 
115027 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
115028 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
115029 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
115030  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115031  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115032  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115033  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115034  */
115035 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK)
115036 
115037 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
115038 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
115039 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
115040  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115041  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115042  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115043  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115044  */
115045 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK)
115046 
115047 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
115048 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
115049 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
115050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115053  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115054  */
115055 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK)
115056 
115057 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
115058 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
115059 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
115060  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115061  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115062  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115063  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115064  */
115065 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK)
115066 
115067 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
115068 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
115069 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
115070  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115071  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115072  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115073  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115074  */
115075 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK)
115076 
115077 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
115078 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
115079 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
115080  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115081  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115082  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115083  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115084  */
115085 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK)
115086 
115087 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
115088 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
115089 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
115090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115093  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115094  */
115095 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK)
115096 
115097 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
115098 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
115099 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
115100  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115101  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115102  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115103  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115104  */
115105 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK)
115106 
115107 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
115108 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
115109 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
115110  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115111  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115112  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115113  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115114  */
115115 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK)
115116 
115117 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
115118 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
115119 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
115120  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115121  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115122  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115123  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115124  */
115125 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK)
115126 
115127 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
115128 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
115129 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
115130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115133  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115134  */
115135 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK)
115136 
115137 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
115138 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
115139 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
115140  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115141  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115142  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115143  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115144  */
115145 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK)
115146 
115147 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
115148 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
115149 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
115150  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115151  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115152  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115153  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115154  */
115155 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK)
115156 
115157 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
115158 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
115159 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
115160  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115161  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115162  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115163  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115164  */
115165 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK)
115166 
115167 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
115168 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
115169 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
115170  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115171  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115172  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115173  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115174  */
115175 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK)
115176 
115177 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
115178 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
115179 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
115180  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115181  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115182  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115183  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115184  */
115185 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK)
115186 
115187 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
115188 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
115189 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
115190  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115191  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115192  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115193  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115194  */
115195 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK)
115196 
115197 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
115198 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
115199 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
115200  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115201  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115202  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115203  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115204  */
115205 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK)
115206 
115207 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
115208 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
115209 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
115210  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115211  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115212  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115213  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115214  */
115215 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK)
115216 
115217 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
115218 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
115219 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
115220  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115221  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115222  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115223  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115224  */
115225 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK)
115226 
115227 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
115228 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
115229 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
115230  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115231  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115232  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115233  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115234  */
115235 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK)
115236 
115237 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
115238 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
115239 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
115240  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115241  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115242  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115243  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115244  */
115245 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK)
115246 
115247 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
115248 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
115249 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
115250  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115251  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115252  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115253  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115254  */
115255 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK)
115256 
115257 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
115258 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
115259 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
115260  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115261  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115262  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115263  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115264  */
115265 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK)
115266 
115267 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
115268 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
115269 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
115270  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115271  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115272  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115273  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115274  */
115275 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK)
115276 
115277 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
115278 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
115279 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
115280  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115281  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115282  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115283  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115284  */
115285 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK)
115286 
115287 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
115288 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
115289 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
115290  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115291  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115292  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115293  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115294  */
115295 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK)
115296 
115297 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
115298 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
115299 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
115300  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115301  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115302  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115303  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115304  */
115305 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK)
115306 
115307 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
115308 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
115309 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
115310  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115311  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115312  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115313  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115314  */
115315 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK)
115316 
115317 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
115318 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
115319 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
115320  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115321  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115322  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115323  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115324  */
115325 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK)
115326 
115327 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
115328 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
115329 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
115330  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115331  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115332  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115333  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115334  */
115335 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK)
115336 
115337 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
115338 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
115339 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
115340  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115341  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115342  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115343  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115344  */
115345 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK)
115346 /*! @} */
115347 
115348 /* The count of TRDC_MBC_DOM14_MEM0_BLK_NSE_W */
115349 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_COUNT      (2U)
115350 
115351 /* The count of TRDC_MBC_DOM14_MEM0_BLK_NSE_W */
115352 #define TRDC_MBC_DOM14_MEM0_BLK_NSE_W_COUNT2     (4U)
115353 
115354 /*! @name MBC_DOM14_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
115355 /*! @{ */
115356 
115357 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
115358 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
115359 /*! MBACSEL0 - Memory Block Access Control Select for block B
115360  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115361  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115362  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115363  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115364  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115365  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115366  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115367  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115368  */
115369 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK)
115370 
115371 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
115372 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
115373 /*! NSE0 - NonSecure Enable for block B
115374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115377  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115378  */
115379 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK)
115380 
115381 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
115382 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
115383 /*! MBACSEL1 - Memory Block Access Control Select for block B
115384  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115385  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115386  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115387  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115388  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115389  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115390  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115391  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115392  */
115393 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK)
115394 
115395 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
115396 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
115397 /*! NSE1 - NonSecure Enable for block B
115398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115401  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115402  */
115403 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK)
115404 
115405 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
115406 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
115407 /*! MBACSEL2 - Memory Block Access Control Select for block B
115408  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115409  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115410  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115411  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115412  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115413  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115414  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115415  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115416  */
115417 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK)
115418 
115419 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
115420 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
115421 /*! NSE2 - NonSecure Enable for block B
115422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115425  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115426  */
115427 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK)
115428 
115429 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
115430 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
115431 /*! MBACSEL3 - Memory Block Access Control Select for block B
115432  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115433  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115434  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115435  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115436  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115437  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115438  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115439  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115440  */
115441 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK)
115442 
115443 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
115444 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
115445 /*! NSE3 - NonSecure Enable for block B
115446  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115447  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115448  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115449  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115450  */
115451 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK)
115452 
115453 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
115454 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
115455 /*! MBACSEL4 - Memory Block Access Control Select for block B
115456  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115457  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115458  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115459  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115460  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115461  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115462  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115463  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115464  */
115465 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK)
115466 
115467 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
115468 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
115469 /*! NSE4 - NonSecure Enable for block B
115470  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115471  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115472  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115473  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115474  */
115475 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK)
115476 
115477 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
115478 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
115479 /*! MBACSEL5 - Memory Block Access Control Select for block B
115480  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115481  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115482  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115483  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115484  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115485  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115486  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115487  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115488  */
115489 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK)
115490 
115491 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
115492 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
115493 /*! NSE5 - NonSecure Enable for block B
115494  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115495  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115496  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115497  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115498  */
115499 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK)
115500 
115501 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
115502 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
115503 /*! MBACSEL6 - Memory Block Access Control Select for block B
115504  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115505  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115506  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115507  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115508  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115509  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115510  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115511  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115512  */
115513 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK)
115514 
115515 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
115516 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
115517 /*! NSE6 - NonSecure Enable for block B
115518  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115519  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115520  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115521  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115522  */
115523 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK)
115524 
115525 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
115526 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
115527 /*! MBACSEL7 - Memory Block Access Control Select for block B
115528  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115529  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115530  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115531  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115532  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115533  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115534  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115535  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115536  */
115537 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK)
115538 
115539 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
115540 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
115541 /*! NSE7 - NonSecure Enable for block B
115542  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115543  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115544  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115545  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115546  */
115547 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK)
115548 /*! @} */
115549 
115550 /* The count of TRDC_MBC_DOM14_MEM1_BLK_CFG_W */
115551 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_COUNT      (2U)
115552 
115553 /* The count of TRDC_MBC_DOM14_MEM1_BLK_CFG_W */
115554 #define TRDC_MBC_DOM14_MEM1_BLK_CFG_W_COUNT2     (4U)
115555 
115556 /*! @name MBC_DOM14_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
115557 /*! @{ */
115558 
115559 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
115560 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
115561 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
115562  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115563  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115564  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115565  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115566  */
115567 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK)
115568 
115569 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
115570 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
115571 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
115572  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115573  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115574  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115575  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115576  */
115577 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK)
115578 
115579 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
115580 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
115581 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
115582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115585  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115586  */
115587 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK)
115588 
115589 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
115590 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
115591 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
115592  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115593  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115594  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115595  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115596  */
115597 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK)
115598 
115599 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
115600 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
115601 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
115602  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115603  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115604  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115605  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115606  */
115607 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK)
115608 
115609 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
115610 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
115611 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
115612  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115613  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115614  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115615  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115616  */
115617 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK)
115618 
115619 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
115620 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
115621 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
115622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115625  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115626  */
115627 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK)
115628 
115629 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
115630 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
115631 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
115632  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115633  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115634  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115635  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115636  */
115637 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK)
115638 
115639 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
115640 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
115641 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
115642  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115643  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115644  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115645  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115646  */
115647 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK)
115648 
115649 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
115650 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
115651 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
115652  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115653  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115654  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115655  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115656  */
115657 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK)
115658 
115659 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
115660 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
115661 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
115662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115665  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115666  */
115667 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK)
115668 
115669 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
115670 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
115671 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
115672  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115673  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115674  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115675  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115676  */
115677 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK)
115678 
115679 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
115680 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
115681 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
115682  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115683  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115684  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115685  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115686  */
115687 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK)
115688 
115689 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
115690 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
115691 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
115692  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115693  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115694  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115695  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115696  */
115697 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK)
115698 
115699 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
115700 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
115701 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
115702  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115703  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115704  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115705  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115706  */
115707 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK)
115708 
115709 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
115710 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
115711 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
115712  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115713  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115714  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115715  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115716  */
115717 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK)
115718 
115719 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
115720 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
115721 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
115722  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115723  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115724  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115725  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115726  */
115727 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK)
115728 
115729 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
115730 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
115731 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
115732  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115733  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115734  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115735  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115736  */
115737 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK)
115738 
115739 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
115740 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
115741 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
115742  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115743  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115744  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115745  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115746  */
115747 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK)
115748 
115749 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
115750 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
115751 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
115752  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115753  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115754  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115755  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115756  */
115757 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK)
115758 
115759 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
115760 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
115761 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
115762  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115763  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115764  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115765  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115766  */
115767 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK)
115768 
115769 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
115770 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
115771 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
115772  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115773  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115774  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115775  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115776  */
115777 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK)
115778 
115779 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
115780 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
115781 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
115782  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115783  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115784  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115785  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115786  */
115787 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK)
115788 
115789 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
115790 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
115791 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
115792  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115793  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115794  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115795  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115796  */
115797 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK)
115798 
115799 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
115800 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
115801 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
115802  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115803  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115804  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115805  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115806  */
115807 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK)
115808 
115809 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
115810 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
115811 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
115812  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115813  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115814  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115815  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115816  */
115817 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK)
115818 
115819 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
115820 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
115821 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
115822  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115823  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115824  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115825  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115826  */
115827 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK)
115828 
115829 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
115830 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
115831 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
115832  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115833  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115834  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115835  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115836  */
115837 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK)
115838 
115839 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
115840 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
115841 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
115842  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115843  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115844  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115845  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115846  */
115847 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK)
115848 
115849 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
115850 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
115851 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
115852  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115853  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115854  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115855  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115856  */
115857 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK)
115858 
115859 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
115860 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
115861 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
115862  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115863  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115864  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115865  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115866  */
115867 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK)
115868 
115869 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
115870 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
115871 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
115872  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
115873  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115874  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115875  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115876  */
115877 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK)
115878 /*! @} */
115879 
115880 /* The count of TRDC_MBC_DOM14_MEM1_BLK_NSE_W */
115881 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_COUNT      (2U)
115882 
115883 /* The count of TRDC_MBC_DOM14_MEM1_BLK_NSE_W */
115884 #define TRDC_MBC_DOM14_MEM1_BLK_NSE_W_COUNT2     (1U)
115885 
115886 /*! @name MBC_DOM14_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
115887 /*! @{ */
115888 
115889 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
115890 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
115891 /*! MBACSEL0 - Memory Block Access Control Select for block B
115892  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115893  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115894  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115895  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115896  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115897  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115898  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115899  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115900  */
115901 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK)
115902 
115903 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
115904 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
115905 /*! NSE0 - NonSecure Enable for block B
115906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115909  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115910  */
115911 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK)
115912 
115913 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
115914 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
115915 /*! MBACSEL1 - Memory Block Access Control Select for block B
115916  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115917  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115918  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115919  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115920  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115921  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115922  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115923  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115924  */
115925 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK)
115926 
115927 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
115928 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
115929 /*! NSE1 - NonSecure Enable for block B
115930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115933  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115934  */
115935 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK)
115936 
115937 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
115938 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
115939 /*! MBACSEL2 - Memory Block Access Control Select for block B
115940  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115941  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115942  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115943  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115944  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115945  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115946  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115947  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115948  */
115949 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK)
115950 
115951 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
115952 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
115953 /*! NSE2 - NonSecure Enable for block B
115954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115957  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115958  */
115959 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK)
115960 
115961 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
115962 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
115963 /*! MBACSEL3 - Memory Block Access Control Select for block B
115964  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115965  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115966  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115967  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115968  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115969  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115970  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115971  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115972  */
115973 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK)
115974 
115975 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
115976 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
115977 /*! NSE3 - NonSecure Enable for block B
115978  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
115979  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
115980  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
115981  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
115982  */
115983 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK)
115984 
115985 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
115986 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
115987 /*! MBACSEL4 - Memory Block Access Control Select for block B
115988  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
115989  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
115990  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
115991  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
115992  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
115993  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
115994  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
115995  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
115996  */
115997 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK)
115998 
115999 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
116000 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
116001 /*! NSE4 - NonSecure Enable for block B
116002  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116003  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116004  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116005  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116006  */
116007 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK)
116008 
116009 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
116010 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
116011 /*! MBACSEL5 - Memory Block Access Control Select for block B
116012  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116013  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116014  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116015  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116016  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116017  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116018  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116019  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116020  */
116021 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK)
116022 
116023 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
116024 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
116025 /*! NSE5 - NonSecure Enable for block B
116026  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116027  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116028  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116029  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116030  */
116031 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK)
116032 
116033 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
116034 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
116035 /*! MBACSEL6 - Memory Block Access Control Select for block B
116036  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116037  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116038  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116039  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116040  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116041  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116042  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116043  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116044  */
116045 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK)
116046 
116047 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
116048 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
116049 /*! NSE6 - NonSecure Enable for block B
116050  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116051  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116052  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116053  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116054  */
116055 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK)
116056 
116057 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
116058 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
116059 /*! MBACSEL7 - Memory Block Access Control Select for block B
116060  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116061  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116062  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116063  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116064  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116065  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116066  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116067  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116068  */
116069 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK)
116070 
116071 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
116072 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
116073 /*! NSE7 - NonSecure Enable for block B
116074  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116075  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116076  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116077  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116078  */
116079 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK)
116080 /*! @} */
116081 
116082 /* The count of TRDC_MBC_DOM14_MEM2_BLK_CFG_W */
116083 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_COUNT      (2U)
116084 
116085 /* The count of TRDC_MBC_DOM14_MEM2_BLK_CFG_W */
116086 #define TRDC_MBC_DOM14_MEM2_BLK_CFG_W_COUNT2     (1U)
116087 
116088 /*! @name MBC_DOM14_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
116089 /*! @{ */
116090 
116091 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
116092 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
116093 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
116094  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116095  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116096  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116097  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116098  */
116099 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK)
116100 
116101 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
116102 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
116103 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
116104  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116105  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116106  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116107  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116108  */
116109 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK)
116110 
116111 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
116112 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
116113 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
116114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116117  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116118  */
116119 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK)
116120 
116121 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
116122 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
116123 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
116124  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116125  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116126  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116127  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116128  */
116129 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK)
116130 
116131 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
116132 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
116133 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
116134  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116135  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116136  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116137  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116138  */
116139 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK)
116140 
116141 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
116142 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
116143 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
116144  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116145  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116146  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116147  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116148  */
116149 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK)
116150 
116151 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
116152 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
116153 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
116154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116157  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116158  */
116159 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK)
116160 
116161 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
116162 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
116163 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
116164  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116165  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116166  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116167  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116168  */
116169 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK)
116170 
116171 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
116172 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
116173 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
116174  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116175  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116176  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116177  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116178  */
116179 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK)
116180 
116181 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
116182 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
116183 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
116184  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116185  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116186  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116187  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116188  */
116189 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK)
116190 
116191 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
116192 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
116193 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
116194  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116195  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116196  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116197  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116198  */
116199 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK)
116200 
116201 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
116202 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
116203 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
116204  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116205  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116206  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116207  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116208  */
116209 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK)
116210 
116211 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
116212 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
116213 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
116214  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116215  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116216  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116217  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116218  */
116219 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK)
116220 
116221 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
116222 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
116223 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
116224  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116225  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116226  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116227  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116228  */
116229 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK)
116230 
116231 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
116232 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
116233 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
116234  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116235  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116236  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116237  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116238  */
116239 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK)
116240 
116241 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
116242 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
116243 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
116244  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116245  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116246  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116247  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116248  */
116249 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK)
116250 
116251 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
116252 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
116253 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
116254  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116255  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116256  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116257  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116258  */
116259 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK)
116260 
116261 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
116262 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
116263 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
116264  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116265  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116266  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116267  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116268  */
116269 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK)
116270 
116271 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
116272 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
116273 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
116274  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116275  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116276  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116277  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116278  */
116279 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK)
116280 
116281 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
116282 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
116283 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
116284  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116285  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116286  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116287  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116288  */
116289 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK)
116290 
116291 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
116292 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
116293 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
116294  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116295  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116296  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116297  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116298  */
116299 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK)
116300 
116301 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
116302 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
116303 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
116304  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116305  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116306  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116307  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116308  */
116309 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK)
116310 
116311 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
116312 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
116313 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
116314  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116315  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116316  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116317  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116318  */
116319 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK)
116320 
116321 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
116322 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
116323 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
116324  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116325  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116326  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116327  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116328  */
116329 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK)
116330 
116331 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
116332 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
116333 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
116334  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116335  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116336  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116337  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116338  */
116339 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK)
116340 
116341 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
116342 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
116343 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
116344  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116345  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116346  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116347  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116348  */
116349 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK)
116350 
116351 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
116352 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
116353 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
116354  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116355  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116356  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116357  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116358  */
116359 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK)
116360 
116361 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
116362 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
116363 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
116364  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116365  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116366  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116367  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116368  */
116369 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK)
116370 
116371 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
116372 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
116373 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
116374  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116375  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116376  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116377  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116378  */
116379 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK)
116380 
116381 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
116382 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
116383 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
116384  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116385  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116386  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116387  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116388  */
116389 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK)
116390 
116391 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
116392 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
116393 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
116394  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116395  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116396  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116397  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116398  */
116399 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK)
116400 
116401 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
116402 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
116403 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
116404  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116405  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116406  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116407  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116408  */
116409 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK)
116410 /*! @} */
116411 
116412 /* The count of TRDC_MBC_DOM14_MEM2_BLK_NSE_W */
116413 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_COUNT      (2U)
116414 
116415 /* The count of TRDC_MBC_DOM14_MEM2_BLK_NSE_W */
116416 #define TRDC_MBC_DOM14_MEM2_BLK_NSE_W_COUNT2     (1U)
116417 
116418 /*! @name MBC_DOM14_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
116419 /*! @{ */
116420 
116421 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
116422 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
116423 /*! MBACSEL0 - Memory Block Access Control Select for block B
116424  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116425  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116426  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116427  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116428  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116429  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116430  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116431  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116432  */
116433 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK)
116434 
116435 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
116436 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
116437 /*! NSE0 - NonSecure Enable for block B
116438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116441  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116442  */
116443 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK)
116444 
116445 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
116446 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
116447 /*! MBACSEL1 - Memory Block Access Control Select for block B
116448  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116449  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116450  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116451  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116452  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116453  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116454  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116455  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116456  */
116457 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK)
116458 
116459 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
116460 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
116461 /*! NSE1 - NonSecure Enable for block B
116462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116465  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116466  */
116467 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK)
116468 
116469 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
116470 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
116471 /*! MBACSEL2 - Memory Block Access Control Select for block B
116472  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116473  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116474  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116475  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116476  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116477  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116478  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116479  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116480  */
116481 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK)
116482 
116483 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
116484 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
116485 /*! NSE2 - NonSecure Enable for block B
116486  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116487  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116488  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116489  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116490  */
116491 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK)
116492 
116493 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
116494 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
116495 /*! MBACSEL3 - Memory Block Access Control Select for block B
116496  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116497  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116498  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116499  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116500  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116501  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116502  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116503  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116504  */
116505 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK)
116506 
116507 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
116508 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
116509 /*! NSE3 - NonSecure Enable for block B
116510  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116511  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116512  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116513  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116514  */
116515 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK)
116516 
116517 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
116518 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
116519 /*! MBACSEL4 - Memory Block Access Control Select for block B
116520  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116521  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116522  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116523  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116524  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116525  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116526  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116527  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116528  */
116529 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK)
116530 
116531 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
116532 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
116533 /*! NSE4 - NonSecure Enable for block B
116534  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116535  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116536  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116537  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116538  */
116539 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK)
116540 
116541 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
116542 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
116543 /*! MBACSEL5 - Memory Block Access Control Select for block B
116544  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116545  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116546  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116547  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116548  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116549  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116550  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116551  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116552  */
116553 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK)
116554 
116555 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
116556 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
116557 /*! NSE5 - NonSecure Enable for block B
116558  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116559  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116560  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116561  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116562  */
116563 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK)
116564 
116565 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
116566 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
116567 /*! MBACSEL6 - Memory Block Access Control Select for block B
116568  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116569  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116570  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116571  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116572  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116573  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116574  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116575  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116576  */
116577 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK)
116578 
116579 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
116580 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
116581 /*! NSE6 - NonSecure Enable for block B
116582  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116583  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116584  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116585  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116586  */
116587 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK)
116588 
116589 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
116590 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
116591 /*! MBACSEL7 - Memory Block Access Control Select for block B
116592  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116593  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116594  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116595  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116596  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116597  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116598  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116599  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116600  */
116601 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK)
116602 
116603 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
116604 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
116605 /*! NSE7 - NonSecure Enable for block B
116606  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116607  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116608  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116609  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116610  */
116611 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK)
116612 /*! @} */
116613 
116614 /* The count of TRDC_MBC_DOM14_MEM3_BLK_CFG_W */
116615 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_COUNT      (2U)
116616 
116617 /* The count of TRDC_MBC_DOM14_MEM3_BLK_CFG_W */
116618 #define TRDC_MBC_DOM14_MEM3_BLK_CFG_W_COUNT2     (3U)
116619 
116620 /*! @name MBC_DOM14_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
116621 /*! @{ */
116622 
116623 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
116624 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
116625 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
116626  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116627  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116628  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116629  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116630  */
116631 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK)
116632 
116633 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
116634 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
116635 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
116636  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116637  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116638  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116639  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116640  */
116641 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK)
116642 
116643 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
116644 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
116645 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
116646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116649  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116650  */
116651 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK)
116652 
116653 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
116654 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
116655 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
116656  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116657  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116658  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116659  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116660  */
116661 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK)
116662 
116663 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
116664 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
116665 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
116666  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116667  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116668  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116669  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116670  */
116671 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK)
116672 
116673 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
116674 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
116675 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
116676  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116677  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116678  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116679  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116680  */
116681 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK)
116682 
116683 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
116684 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
116685 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
116686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116689  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116690  */
116691 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK)
116692 
116693 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
116694 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
116695 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
116696  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116697  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116698  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116699  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116700  */
116701 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK)
116702 
116703 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
116704 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
116705 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
116706  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116707  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116708  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116709  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116710  */
116711 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK)
116712 
116713 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
116714 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
116715 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
116716  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116717  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116718  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116719  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116720  */
116721 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK)
116722 
116723 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
116724 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
116725 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
116726  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116727  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116728  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116729  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116730  */
116731 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK)
116732 
116733 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
116734 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
116735 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
116736  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116737  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116738  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116739  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116740  */
116741 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK)
116742 
116743 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
116744 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
116745 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
116746  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116747  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116748  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116749  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116750  */
116751 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK)
116752 
116753 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
116754 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
116755 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
116756  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116757  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116758  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116759  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116760  */
116761 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK)
116762 
116763 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
116764 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
116765 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
116766  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116767  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116768  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116769  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116770  */
116771 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK)
116772 
116773 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
116774 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
116775 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
116776  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116777  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116778  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116779  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116780  */
116781 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK)
116782 
116783 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
116784 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
116785 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
116786  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116787  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116788  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116789  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116790  */
116791 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK)
116792 
116793 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
116794 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
116795 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
116796  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116797  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116798  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116799  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116800  */
116801 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK)
116802 
116803 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
116804 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
116805 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
116806  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116807  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116808  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116809  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116810  */
116811 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK)
116812 
116813 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
116814 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
116815 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
116816  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116817  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116818  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116819  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116820  */
116821 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK)
116822 
116823 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
116824 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
116825 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
116826  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116827  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116828  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116829  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116830  */
116831 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK)
116832 
116833 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
116834 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
116835 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
116836  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116837  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116838  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116839  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116840  */
116841 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK)
116842 
116843 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
116844 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
116845 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
116846  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116847  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116848  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116849  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116850  */
116851 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK)
116852 
116853 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
116854 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
116855 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
116856  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116857  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116858  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116859  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116860  */
116861 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK)
116862 
116863 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
116864 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
116865 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
116866  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116867  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116868  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116869  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116870  */
116871 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK)
116872 
116873 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
116874 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
116875 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
116876  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116877  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116878  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116879  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116880  */
116881 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK)
116882 
116883 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
116884 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
116885 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
116886  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116887  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116888  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116889  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116890  */
116891 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK)
116892 
116893 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
116894 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
116895 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
116896  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116897  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116898  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116899  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116900  */
116901 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK)
116902 
116903 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
116904 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
116905 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
116906  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116907  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116908  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116909  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116910  */
116911 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK)
116912 
116913 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
116914 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
116915 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
116916  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116917  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116918  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116919  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116920  */
116921 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK)
116922 
116923 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
116924 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
116925 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
116926  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116927  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116928  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116929  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116930  */
116931 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK)
116932 
116933 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
116934 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
116935 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
116936  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
116937  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116938  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116939  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116940  */
116941 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK)
116942 /*! @} */
116943 
116944 /* The count of TRDC_MBC_DOM14_MEM3_BLK_NSE_W */
116945 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_COUNT      (2U)
116946 
116947 /* The count of TRDC_MBC_DOM14_MEM3_BLK_NSE_W */
116948 #define TRDC_MBC_DOM14_MEM3_BLK_NSE_W_COUNT2     (1U)
116949 
116950 /*! @name MBC_DOM15_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
116951 /*! @{ */
116952 
116953 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
116954 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
116955 /*! MBACSEL0 - Memory Block Access Control Select for block B
116956  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116957  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116958  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116959  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116960  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116961  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116962  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116963  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116964  */
116965 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK)
116966 
116967 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK  (0x8U)
116968 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT (3U)
116969 /*! NSE0 - NonSecure Enable for block B
116970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116973  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116974  */
116975 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK)
116976 
116977 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
116978 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
116979 /*! MBACSEL1 - Memory Block Access Control Select for block B
116980  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
116981  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
116982  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
116983  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
116984  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
116985  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
116986  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
116987  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
116988  */
116989 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK)
116990 
116991 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK  (0x80U)
116992 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT (7U)
116993 /*! NSE1 - NonSecure Enable for block B
116994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
116995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
116996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
116997  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
116998  */
116999 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK)
117000 
117001 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
117002 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
117003 /*! MBACSEL2 - Memory Block Access Control Select for block B
117004  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117005  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117006  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117007  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117008  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117009  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117010  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117011  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117012  */
117013 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK)
117014 
117015 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK  (0x800U)
117016 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT (11U)
117017 /*! NSE2 - NonSecure Enable for block B
117018  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117019  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117020  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117021  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117022  */
117023 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK)
117024 
117025 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
117026 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
117027 /*! MBACSEL3 - Memory Block Access Control Select for block B
117028  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117029  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117030  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117031  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117032  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117033  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117034  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117035  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117036  */
117037 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK)
117038 
117039 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK  (0x8000U)
117040 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT (15U)
117041 /*! NSE3 - NonSecure Enable for block B
117042  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117043  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117044  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117045  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117046  */
117047 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK)
117048 
117049 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
117050 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
117051 /*! MBACSEL4 - Memory Block Access Control Select for block B
117052  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117053  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117054  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117055  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117056  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117057  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117058  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117059  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117060  */
117061 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK)
117062 
117063 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK  (0x80000U)
117064 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT (19U)
117065 /*! NSE4 - NonSecure Enable for block B
117066  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117067  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117068  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117069  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117070  */
117071 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK)
117072 
117073 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
117074 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
117075 /*! MBACSEL5 - Memory Block Access Control Select for block B
117076  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117077  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117078  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117079  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117080  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117081  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117082  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117083  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117084  */
117085 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK)
117086 
117087 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK  (0x800000U)
117088 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT (23U)
117089 /*! NSE5 - NonSecure Enable for block B
117090  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117091  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117092  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117093  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117094  */
117095 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK)
117096 
117097 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
117098 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
117099 /*! MBACSEL6 - Memory Block Access Control Select for block B
117100  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117101  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117102  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117103  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117104  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117105  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117106  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117107  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117108  */
117109 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK)
117110 
117111 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK  (0x8000000U)
117112 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT (27U)
117113 /*! NSE6 - NonSecure Enable for block B
117114  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117115  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117116  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117117  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117118  */
117119 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK)
117120 
117121 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
117122 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
117123 /*! MBACSEL7 - Memory Block Access Control Select for block B
117124  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117125  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117126  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117127  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117128  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117129  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117130  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117131  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117132  */
117133 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK)
117134 
117135 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK  (0x80000000U)
117136 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT (31U)
117137 /*! NSE7 - NonSecure Enable for block B
117138  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117139  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117140  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117141  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117142  */
117143 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK)
117144 /*! @} */
117145 
117146 /* The count of TRDC_MBC_DOM15_MEM0_BLK_CFG_W */
117147 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_COUNT      (2U)
117148 
117149 /* The count of TRDC_MBC_DOM15_MEM0_BLK_CFG_W */
117150 #define TRDC_MBC_DOM15_MEM0_BLK_CFG_W_COUNT2     (16U)
117151 
117152 /*! @name MBC_DOM15_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
117153 /*! @{ */
117154 
117155 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK  (0x1U)
117156 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT (0U)
117157 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
117158  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117159  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117160  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117161  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117162  */
117163 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK)
117164 
117165 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK  (0x2U)
117166 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT (1U)
117167 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
117168  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117169  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117170  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117171  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117172  */
117173 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK)
117174 
117175 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK  (0x4U)
117176 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT (2U)
117177 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
117178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117181  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117182  */
117183 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK)
117184 
117185 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK  (0x8U)
117186 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT (3U)
117187 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
117188  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117189  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117190  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117191  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117192  */
117193 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK)
117194 
117195 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK  (0x10U)
117196 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT (4U)
117197 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
117198  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117199  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117200  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117201  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117202  */
117203 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK)
117204 
117205 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK  (0x20U)
117206 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT (5U)
117207 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
117208  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117209  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117210  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117211  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117212  */
117213 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK)
117214 
117215 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK  (0x40U)
117216 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT (6U)
117217 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
117218  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117219  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117220  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117221  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117222  */
117223 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK)
117224 
117225 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK  (0x80U)
117226 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT (7U)
117227 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
117228  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117229  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117230  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117231  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117232  */
117233 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK)
117234 
117235 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK  (0x100U)
117236 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT (8U)
117237 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
117238  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117239  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117240  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117241  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117242  */
117243 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK)
117244 
117245 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK  (0x200U)
117246 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT (9U)
117247 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
117248  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117249  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117250  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117251  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117252  */
117253 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK)
117254 
117255 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK (0x400U)
117256 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
117257 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
117258  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117259  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117260  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117261  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117262  */
117263 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK)
117264 
117265 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK (0x800U)
117266 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
117267 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
117268  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117269  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117270  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117271  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117272  */
117273 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK)
117274 
117275 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U)
117276 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
117277 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
117278  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117279  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117280  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117281  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117282  */
117283 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK)
117284 
117285 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U)
117286 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
117287 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
117288  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117289  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117290  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117291  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117292  */
117293 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK)
117294 
117295 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U)
117296 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
117297 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
117298  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117299  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117300  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117301  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117302  */
117303 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK)
117304 
117305 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U)
117306 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
117307 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
117308  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117309  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117310  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117311  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117312  */
117313 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK)
117314 
117315 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U)
117316 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
117317 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
117318  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117319  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117320  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117321  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117322  */
117323 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK)
117324 
117325 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U)
117326 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
117327 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
117328  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117329  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117330  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117331  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117332  */
117333 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK)
117334 
117335 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U)
117336 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
117337 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
117338  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117339  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117340  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117341  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117342  */
117343 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK)
117344 
117345 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U)
117346 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
117347 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
117348  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117349  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117350  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117351  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117352  */
117353 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK)
117354 
117355 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U)
117356 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
117357 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
117358  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117359  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117360  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117361  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117362  */
117363 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK)
117364 
117365 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U)
117366 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
117367 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
117368  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117369  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117370  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117371  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117372  */
117373 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK)
117374 
117375 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U)
117376 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
117377 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
117378  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117379  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117380  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117381  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117382  */
117383 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK)
117384 
117385 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U)
117386 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
117387 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
117388  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117389  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117390  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117391  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117392  */
117393 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK)
117394 
117395 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U)
117396 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
117397 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
117398  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117399  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117400  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117401  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117402  */
117403 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK)
117404 
117405 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U)
117406 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
117407 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
117408  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117409  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117410  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117411  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117412  */
117413 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK)
117414 
117415 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U)
117416 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
117417 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
117418  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117419  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117420  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117421  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117422  */
117423 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK)
117424 
117425 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U)
117426 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
117427 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
117428  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117429  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117430  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117431  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117432  */
117433 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK)
117434 
117435 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U)
117436 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
117437 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
117438  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117439  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117440  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117441  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117442  */
117443 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK)
117444 
117445 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U)
117446 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
117447 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
117448  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117449  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117450  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117451  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117452  */
117453 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK)
117454 
117455 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U)
117456 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
117457 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
117458  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117459  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117460  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117461  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117462  */
117463 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK)
117464 
117465 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U)
117466 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
117467 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
117468  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117469  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117470  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117471  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117472  */
117473 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK)
117474 /*! @} */
117475 
117476 /* The count of TRDC_MBC_DOM15_MEM0_BLK_NSE_W */
117477 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_COUNT      (2U)
117478 
117479 /* The count of TRDC_MBC_DOM15_MEM0_BLK_NSE_W */
117480 #define TRDC_MBC_DOM15_MEM0_BLK_NSE_W_COUNT2     (4U)
117481 
117482 /*! @name MBC_DOM15_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
117483 /*! @{ */
117484 
117485 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
117486 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
117487 /*! MBACSEL0 - Memory Block Access Control Select for block B
117488  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117489  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117490  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117491  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117492  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117493  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117494  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117495  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117496  */
117497 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK)
117498 
117499 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK  (0x8U)
117500 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT (3U)
117501 /*! NSE0 - NonSecure Enable for block B
117502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117505  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117506  */
117507 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK)
117508 
117509 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
117510 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
117511 /*! MBACSEL1 - Memory Block Access Control Select for block B
117512  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117513  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117514  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117515  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117516  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117517  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117518  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117519  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117520  */
117521 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK)
117522 
117523 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK  (0x80U)
117524 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT (7U)
117525 /*! NSE1 - NonSecure Enable for block B
117526  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117527  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117528  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117529  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117530  */
117531 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK)
117532 
117533 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
117534 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
117535 /*! MBACSEL2 - Memory Block Access Control Select for block B
117536  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117537  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117538  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117539  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117540  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117541  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117542  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117543  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117544  */
117545 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK)
117546 
117547 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK  (0x800U)
117548 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT (11U)
117549 /*! NSE2 - NonSecure Enable for block B
117550  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117551  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117552  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117553  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117554  */
117555 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK)
117556 
117557 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
117558 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
117559 /*! MBACSEL3 - Memory Block Access Control Select for block B
117560  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117561  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117562  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117563  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117564  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117565  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117566  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117567  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117568  */
117569 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK)
117570 
117571 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK  (0x8000U)
117572 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT (15U)
117573 /*! NSE3 - NonSecure Enable for block B
117574  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117575  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117576  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117577  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117578  */
117579 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK)
117580 
117581 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
117582 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
117583 /*! MBACSEL4 - Memory Block Access Control Select for block B
117584  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117585  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117586  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117587  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117588  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117589  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117590  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117591  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117592  */
117593 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK)
117594 
117595 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK  (0x80000U)
117596 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT (19U)
117597 /*! NSE4 - NonSecure Enable for block B
117598  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117599  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117600  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117601  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117602  */
117603 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK)
117604 
117605 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
117606 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
117607 /*! MBACSEL5 - Memory Block Access Control Select for block B
117608  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117609  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117610  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117611  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117612  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117613  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117614  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117615  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117616  */
117617 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK)
117618 
117619 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK  (0x800000U)
117620 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT (23U)
117621 /*! NSE5 - NonSecure Enable for block B
117622  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117623  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117624  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117625  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117626  */
117627 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK)
117628 
117629 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
117630 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
117631 /*! MBACSEL6 - Memory Block Access Control Select for block B
117632  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117633  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117634  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117635  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117636  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117637  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117638  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117639  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117640  */
117641 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK)
117642 
117643 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK  (0x8000000U)
117644 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT (27U)
117645 /*! NSE6 - NonSecure Enable for block B
117646  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117647  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117648  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117649  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117650  */
117651 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK)
117652 
117653 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
117654 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
117655 /*! MBACSEL7 - Memory Block Access Control Select for block B
117656  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
117657  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
117658  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
117659  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
117660  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
117661  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
117662  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
117663  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
117664  */
117665 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK)
117666 
117667 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK  (0x80000000U)
117668 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT (31U)
117669 /*! NSE7 - NonSecure Enable for block B
117670  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
117671  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117672  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117673  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117674  */
117675 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK)
117676 /*! @} */
117677 
117678 /* The count of TRDC_MBC_DOM15_MEM1_BLK_CFG_W */
117679 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_COUNT      (2U)
117680 
117681 /* The count of TRDC_MBC_DOM15_MEM1_BLK_CFG_W */
117682 #define TRDC_MBC_DOM15_MEM1_BLK_CFG_W_COUNT2     (4U)
117683 
117684 /*! @name MBC_DOM15_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
117685 /*! @{ */
117686 
117687 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK  (0x1U)
117688 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT (0U)
117689 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
117690  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117691  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117692  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117693  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117694  */
117695 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK)
117696 
117697 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK  (0x2U)
117698 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT (1U)
117699 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
117700  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117701  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117702  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117703  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117704  */
117705 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK)
117706 
117707 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK  (0x4U)
117708 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT (2U)
117709 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
117710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117713  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117714  */
117715 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK)
117716 
117717 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK  (0x8U)
117718 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT (3U)
117719 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
117720  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117721  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117722  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117723  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117724  */
117725 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK)
117726 
117727 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK  (0x10U)
117728 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT (4U)
117729 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
117730  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117731  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117732  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117733  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117734  */
117735 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK)
117736 
117737 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK  (0x20U)
117738 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT (5U)
117739 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
117740  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117741  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117742  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117743  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117744  */
117745 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK)
117746 
117747 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK  (0x40U)
117748 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT (6U)
117749 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
117750  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117751  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117752  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117753  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117754  */
117755 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK)
117756 
117757 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK  (0x80U)
117758 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT (7U)
117759 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
117760  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117761  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117762  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117763  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117764  */
117765 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK)
117766 
117767 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK  (0x100U)
117768 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT (8U)
117769 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
117770  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117771  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117772  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117773  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117774  */
117775 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK)
117776 
117777 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK  (0x200U)
117778 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT (9U)
117779 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
117780  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117781  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117782  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117783  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117784  */
117785 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK)
117786 
117787 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK (0x400U)
117788 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
117789 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
117790  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117791  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117792  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117793  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117794  */
117795 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK)
117796 
117797 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK (0x800U)
117798 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
117799 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
117800  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117801  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117802  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117803  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117804  */
117805 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK)
117806 
117807 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U)
117808 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
117809 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
117810  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117811  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117812  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117813  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117814  */
117815 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK)
117816 
117817 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U)
117818 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
117819 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
117820  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117821  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117822  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117823  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117824  */
117825 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK)
117826 
117827 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U)
117828 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
117829 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
117830  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117831  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117832  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117833  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117834  */
117835 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK)
117836 
117837 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U)
117838 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
117839 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
117840  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117841  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117842  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117843  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117844  */
117845 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK)
117846 
117847 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U)
117848 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
117849 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
117850  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117851  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117852  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117853  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117854  */
117855 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK)
117856 
117857 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U)
117858 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
117859 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
117860  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117861  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117862  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117863  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117864  */
117865 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK)
117866 
117867 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U)
117868 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
117869 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
117870  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117871  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117872  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117873  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117874  */
117875 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK)
117876 
117877 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U)
117878 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
117879 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
117880  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117881  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117882  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117883  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117884  */
117885 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK)
117886 
117887 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U)
117888 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
117889 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
117890  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117891  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117892  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117893  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117894  */
117895 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK)
117896 
117897 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U)
117898 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
117899 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
117900  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117901  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117902  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117903  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117904  */
117905 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK)
117906 
117907 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U)
117908 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
117909 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
117910  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117911  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117912  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117913  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117914  */
117915 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK)
117916 
117917 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U)
117918 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
117919 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
117920  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117921  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117922  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117923  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117924  */
117925 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK)
117926 
117927 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U)
117928 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
117929 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
117930  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117931  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117932  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117933  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117934  */
117935 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK)
117936 
117937 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U)
117938 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
117939 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
117940  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117941  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117942  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117943  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117944  */
117945 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK)
117946 
117947 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U)
117948 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
117949 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
117950  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117951  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117952  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117953  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117954  */
117955 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK)
117956 
117957 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U)
117958 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
117959 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
117960  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117961  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117962  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117963  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117964  */
117965 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK)
117966 
117967 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U)
117968 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
117969 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
117970  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117971  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117972  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117973  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117974  */
117975 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK)
117976 
117977 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U)
117978 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
117979 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
117980  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117981  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117982  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117983  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117984  */
117985 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK)
117986 
117987 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U)
117988 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
117989 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
117990  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
117991  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
117992  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
117993  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
117994  */
117995 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK)
117996 
117997 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U)
117998 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
117999 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
118000  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118001  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118002  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118003  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118004  */
118005 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK)
118006 /*! @} */
118007 
118008 /* The count of TRDC_MBC_DOM15_MEM1_BLK_NSE_W */
118009 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_COUNT      (2U)
118010 
118011 /* The count of TRDC_MBC_DOM15_MEM1_BLK_NSE_W */
118012 #define TRDC_MBC_DOM15_MEM1_BLK_NSE_W_COUNT2     (1U)
118013 
118014 /*! @name MBC_DOM15_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
118015 /*! @{ */
118016 
118017 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
118018 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
118019 /*! MBACSEL0 - Memory Block Access Control Select for block B
118020  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118021  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118022  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118023  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118024  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118025  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118026  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118027  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118028  */
118029 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK)
118030 
118031 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK  (0x8U)
118032 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT (3U)
118033 /*! NSE0 - NonSecure Enable for block B
118034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118037  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118038  */
118039 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK)
118040 
118041 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
118042 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
118043 /*! MBACSEL1 - Memory Block Access Control Select for block B
118044  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118045  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118046  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118047  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118048  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118049  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118050  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118051  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118052  */
118053 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK)
118054 
118055 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK  (0x80U)
118056 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT (7U)
118057 /*! NSE1 - NonSecure Enable for block B
118058  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118059  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118060  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118061  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118062  */
118063 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK)
118064 
118065 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
118066 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
118067 /*! MBACSEL2 - Memory Block Access Control Select for block B
118068  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118069  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118070  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118071  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118072  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118073  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118074  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118075  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118076  */
118077 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK)
118078 
118079 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK  (0x800U)
118080 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT (11U)
118081 /*! NSE2 - NonSecure Enable for block B
118082  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118083  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118084  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118085  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118086  */
118087 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK)
118088 
118089 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
118090 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
118091 /*! MBACSEL3 - Memory Block Access Control Select for block B
118092  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118093  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118094  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118095  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118096  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118097  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118098  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118099  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118100  */
118101 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK)
118102 
118103 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK  (0x8000U)
118104 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT (15U)
118105 /*! NSE3 - NonSecure Enable for block B
118106  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118107  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118108  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118109  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118110  */
118111 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK)
118112 
118113 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
118114 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
118115 /*! MBACSEL4 - Memory Block Access Control Select for block B
118116  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118117  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118118  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118119  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118120  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118121  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118122  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118123  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118124  */
118125 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK)
118126 
118127 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK  (0x80000U)
118128 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT (19U)
118129 /*! NSE4 - NonSecure Enable for block B
118130  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118131  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118132  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118133  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118134  */
118135 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK)
118136 
118137 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
118138 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
118139 /*! MBACSEL5 - Memory Block Access Control Select for block B
118140  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118141  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118142  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118143  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118144  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118145  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118146  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118147  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118148  */
118149 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK)
118150 
118151 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK  (0x800000U)
118152 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT (23U)
118153 /*! NSE5 - NonSecure Enable for block B
118154  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118155  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118156  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118157  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118158  */
118159 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK)
118160 
118161 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
118162 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
118163 /*! MBACSEL6 - Memory Block Access Control Select for block B
118164  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118165  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118166  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118167  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118168  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118169  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118170  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118171  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118172  */
118173 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK)
118174 
118175 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK  (0x8000000U)
118176 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT (27U)
118177 /*! NSE6 - NonSecure Enable for block B
118178  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118179  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118180  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118181  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118182  */
118183 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK)
118184 
118185 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
118186 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
118187 /*! MBACSEL7 - Memory Block Access Control Select for block B
118188  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118189  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118190  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118191  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118192  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118193  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118194  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118195  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118196  */
118197 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK)
118198 
118199 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK  (0x80000000U)
118200 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT (31U)
118201 /*! NSE7 - NonSecure Enable for block B
118202  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118203  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118204  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118205  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118206  */
118207 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK)
118208 /*! @} */
118209 
118210 /* The count of TRDC_MBC_DOM15_MEM2_BLK_CFG_W */
118211 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_COUNT      (2U)
118212 
118213 /* The count of TRDC_MBC_DOM15_MEM2_BLK_CFG_W */
118214 #define TRDC_MBC_DOM15_MEM2_BLK_CFG_W_COUNT2     (1U)
118215 
118216 /*! @name MBC_DOM15_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
118217 /*! @{ */
118218 
118219 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK  (0x1U)
118220 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT (0U)
118221 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
118222  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118223  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118224  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118225  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118226  */
118227 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK)
118228 
118229 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK  (0x2U)
118230 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT (1U)
118231 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
118232  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118233  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118234  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118235  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118236  */
118237 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK)
118238 
118239 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK  (0x4U)
118240 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT (2U)
118241 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
118242  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118243  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118244  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118245  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118246  */
118247 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK)
118248 
118249 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK  (0x8U)
118250 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT (3U)
118251 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
118252  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118253  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118254  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118255  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118256  */
118257 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK)
118258 
118259 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK  (0x10U)
118260 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT (4U)
118261 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
118262  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118263  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118264  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118265  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118266  */
118267 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK)
118268 
118269 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK  (0x20U)
118270 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT (5U)
118271 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
118272  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118273  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118274  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118275  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118276  */
118277 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK)
118278 
118279 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK  (0x40U)
118280 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT (6U)
118281 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
118282  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118283  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118284  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118285  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118286  */
118287 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK)
118288 
118289 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK  (0x80U)
118290 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT (7U)
118291 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
118292  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118293  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118294  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118295  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118296  */
118297 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK)
118298 
118299 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK  (0x100U)
118300 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT (8U)
118301 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
118302  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118303  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118304  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118305  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118306  */
118307 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK)
118308 
118309 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK  (0x200U)
118310 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT (9U)
118311 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
118312  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118313  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118314  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118315  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118316  */
118317 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK)
118318 
118319 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK (0x400U)
118320 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
118321 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
118322  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118323  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118324  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118325  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118326  */
118327 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK)
118328 
118329 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK (0x800U)
118330 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
118331 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
118332  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118333  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118334  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118335  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118336  */
118337 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK)
118338 
118339 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U)
118340 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
118341 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
118342  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118343  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118344  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118345  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118346  */
118347 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK)
118348 
118349 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U)
118350 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
118351 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
118352  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118353  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118354  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118355  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118356  */
118357 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK)
118358 
118359 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U)
118360 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
118361 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
118362  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118363  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118364  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118365  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118366  */
118367 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK)
118368 
118369 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U)
118370 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
118371 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
118372  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118373  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118374  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118375  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118376  */
118377 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK)
118378 
118379 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U)
118380 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
118381 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
118382  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118383  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118384  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118385  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118386  */
118387 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK)
118388 
118389 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U)
118390 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
118391 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
118392  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118393  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118394  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118395  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118396  */
118397 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK)
118398 
118399 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U)
118400 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
118401 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
118402  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118403  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118404  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118405  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118406  */
118407 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK)
118408 
118409 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U)
118410 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
118411 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
118412  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118413  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118414  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118415  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118416  */
118417 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK)
118418 
118419 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U)
118420 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
118421 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
118422  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118423  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118424  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118425  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118426  */
118427 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK)
118428 
118429 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U)
118430 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
118431 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
118432  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118433  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118434  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118435  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118436  */
118437 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK)
118438 
118439 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U)
118440 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
118441 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
118442  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118443  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118444  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118445  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118446  */
118447 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK)
118448 
118449 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U)
118450 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
118451 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
118452  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118453  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118454  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118455  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118456  */
118457 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK)
118458 
118459 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U)
118460 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
118461 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
118462  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118463  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118464  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118465  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118466  */
118467 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK)
118468 
118469 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U)
118470 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
118471 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
118472  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118473  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118474  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118475  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118476  */
118477 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK)
118478 
118479 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U)
118480 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
118481 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
118482  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118483  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118484  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118485  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118486  */
118487 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK)
118488 
118489 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U)
118490 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
118491 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
118492  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118493  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118494  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118495  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118496  */
118497 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK)
118498 
118499 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U)
118500 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
118501 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
118502  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118503  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118504  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118505  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118506  */
118507 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK)
118508 
118509 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U)
118510 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
118511 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
118512  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118513  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118514  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118515  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118516  */
118517 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK)
118518 
118519 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U)
118520 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
118521 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
118522  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118523  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118524  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118525  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118526  */
118527 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK)
118528 
118529 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U)
118530 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
118531 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
118532  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118533  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118534  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118535  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118536  */
118537 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK)
118538 /*! @} */
118539 
118540 /* The count of TRDC_MBC_DOM15_MEM2_BLK_NSE_W */
118541 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_COUNT      (2U)
118542 
118543 /* The count of TRDC_MBC_DOM15_MEM2_BLK_NSE_W */
118544 #define TRDC_MBC_DOM15_MEM2_BLK_NSE_W_COUNT2     (1U)
118545 
118546 /*! @name MBC_DOM15_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
118547 /*! @{ */
118548 
118549 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
118550 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
118551 /*! MBACSEL0 - Memory Block Access Control Select for block B
118552  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118553  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118554  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118555  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118556  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118557  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118558  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118559  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118560  */
118561 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK)
118562 
118563 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK  (0x8U)
118564 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT (3U)
118565 /*! NSE0 - NonSecure Enable for block B
118566  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118567  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118568  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118569  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118570  */
118571 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK)
118572 
118573 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
118574 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
118575 /*! MBACSEL1 - Memory Block Access Control Select for block B
118576  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118577  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118578  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118579  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118580  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118581  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118582  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118583  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118584  */
118585 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK)
118586 
118587 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK  (0x80U)
118588 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT (7U)
118589 /*! NSE1 - NonSecure Enable for block B
118590  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118591  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118592  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118593  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118594  */
118595 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK)
118596 
118597 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
118598 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
118599 /*! MBACSEL2 - Memory Block Access Control Select for block B
118600  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118601  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118602  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118603  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118604  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118605  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118606  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118607  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118608  */
118609 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK)
118610 
118611 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK  (0x800U)
118612 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT (11U)
118613 /*! NSE2 - NonSecure Enable for block B
118614  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118615  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118616  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118617  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118618  */
118619 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK)
118620 
118621 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
118622 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
118623 /*! MBACSEL3 - Memory Block Access Control Select for block B
118624  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118625  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118626  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118627  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118628  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118629  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118630  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118631  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118632  */
118633 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK)
118634 
118635 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK  (0x8000U)
118636 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT (15U)
118637 /*! NSE3 - NonSecure Enable for block B
118638  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118639  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118640  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118641  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118642  */
118643 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK)
118644 
118645 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
118646 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
118647 /*! MBACSEL4 - Memory Block Access Control Select for block B
118648  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118649  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118650  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118651  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118652  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118653  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118654  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118655  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118656  */
118657 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK)
118658 
118659 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK  (0x80000U)
118660 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT (19U)
118661 /*! NSE4 - NonSecure Enable for block B
118662  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118663  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118664  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118665  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118666  */
118667 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK)
118668 
118669 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
118670 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
118671 /*! MBACSEL5 - Memory Block Access Control Select for block B
118672  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118673  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118674  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118675  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118676  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118677  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118678  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118679  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118680  */
118681 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK)
118682 
118683 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK  (0x800000U)
118684 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT (23U)
118685 /*! NSE5 - NonSecure Enable for block B
118686  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118687  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118688  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118689  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118690  */
118691 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK)
118692 
118693 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
118694 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
118695 /*! MBACSEL6 - Memory Block Access Control Select for block B
118696  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118697  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118698  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118699  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118700  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118701  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118702  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118703  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118704  */
118705 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK)
118706 
118707 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK  (0x8000000U)
118708 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT (27U)
118709 /*! NSE6 - NonSecure Enable for block B
118710  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118711  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118712  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118713  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118714  */
118715 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK)
118716 
118717 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
118718 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
118719 /*! MBACSEL7 - Memory Block Access Control Select for block B
118720  *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
118721  *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
118722  *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
118723  *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
118724  *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
118725  *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
118726  *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
118727  *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
118728  */
118729 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK)
118730 
118731 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK  (0x80000000U)
118732 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT (31U)
118733 /*! NSE7 - NonSecure Enable for block B
118734  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
118735  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118736  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118737  *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118738  */
118739 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK)
118740 /*! @} */
118741 
118742 /* The count of TRDC_MBC_DOM15_MEM3_BLK_CFG_W */
118743 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_COUNT      (2U)
118744 
118745 /* The count of TRDC_MBC_DOM15_MEM3_BLK_CFG_W */
118746 #define TRDC_MBC_DOM15_MEM3_BLK_CFG_W_COUNT2     (3U)
118747 
118748 /*! @name MBC_DOM15_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
118749 /*! @{ */
118750 
118751 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK  (0x1U)
118752 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT (0U)
118753 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
118754  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118755  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118756  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118757  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118758  */
118759 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT0(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK)
118760 
118761 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK  (0x2U)
118762 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT (1U)
118763 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
118764  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118765  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118766  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118767  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118768  */
118769 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT1(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK)
118770 
118771 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK  (0x4U)
118772 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT (2U)
118773 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
118774  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118775  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118776  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118777  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118778  */
118779 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT2(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK)
118780 
118781 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK  (0x8U)
118782 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT (3U)
118783 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
118784  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118785  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118786  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118787  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118788  */
118789 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT3(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK)
118790 
118791 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK  (0x10U)
118792 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT (4U)
118793 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
118794  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118795  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118796  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118797  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118798  */
118799 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT4(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK)
118800 
118801 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK  (0x20U)
118802 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT (5U)
118803 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
118804  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118805  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118806  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118807  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118808  */
118809 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT5(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK)
118810 
118811 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK  (0x40U)
118812 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT (6U)
118813 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
118814  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118815  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118816  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118817  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118818  */
118819 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT6(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK)
118820 
118821 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK  (0x80U)
118822 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT (7U)
118823 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
118824  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118825  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118826  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118827  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118828  */
118829 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT7(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK)
118830 
118831 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK  (0x100U)
118832 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT (8U)
118833 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
118834  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118835  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118836  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118837  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118838  */
118839 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT8(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK)
118840 
118841 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK  (0x200U)
118842 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT (9U)
118843 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
118844  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118845  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118846  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118847  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118848  */
118849 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT9(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK)
118850 
118851 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK (0x400U)
118852 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
118853 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
118854  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118855  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118856  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118857  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118858  */
118859 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT10(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK)
118860 
118861 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK (0x800U)
118862 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
118863 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
118864  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118865  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118866  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118867  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118868  */
118869 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT11(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK)
118870 
118871 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U)
118872 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
118873 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
118874  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118875  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118876  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118877  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118878  */
118879 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT12(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK)
118880 
118881 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U)
118882 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
118883 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
118884  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118885  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118886  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118887  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118888  */
118889 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT13(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK)
118890 
118891 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U)
118892 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
118893 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
118894  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118895  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118896  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118897  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118898  */
118899 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT14(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK)
118900 
118901 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U)
118902 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
118903 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
118904  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118905  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118906  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118907  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118908  */
118909 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT15(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK)
118910 
118911 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U)
118912 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
118913 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
118914  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118915  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118916  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118917  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118918  */
118919 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT16(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK)
118920 
118921 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U)
118922 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
118923 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
118924  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118925  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118926  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118927  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118928  */
118929 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT17(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK)
118930 
118931 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U)
118932 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
118933 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
118934  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118935  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118936  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118937  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118938  */
118939 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT18(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK)
118940 
118941 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U)
118942 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
118943 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
118944  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118945  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118946  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118947  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118948  */
118949 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT19(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK)
118950 
118951 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U)
118952 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
118953 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
118954  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118955  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118956  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118957  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118958  */
118959 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT20(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK)
118960 
118961 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U)
118962 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
118963 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
118964  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118965  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118966  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118967  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118968  */
118969 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT21(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK)
118970 
118971 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U)
118972 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
118973 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
118974  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118975  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118976  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118977  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118978  */
118979 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT22(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK)
118980 
118981 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U)
118982 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
118983 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
118984  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118985  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118986  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118987  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118988  */
118989 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT23(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK)
118990 
118991 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U)
118992 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
118993 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
118994  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
118995  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
118996  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
118997  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
118998  */
118999 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT24(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK)
119000 
119001 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U)
119002 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
119003 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
119004  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119005  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119006  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119007  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119008  */
119009 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT25(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK)
119010 
119011 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U)
119012 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
119013 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
119014  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119015  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119016  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119017  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119018  */
119019 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT26(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK)
119020 
119021 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U)
119022 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
119023 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
119024  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119025  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119026  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119027  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119028  */
119029 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT27(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK)
119030 
119031 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U)
119032 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
119033 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
119034  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119035  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119036  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119037  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119038  */
119039 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT28(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK)
119040 
119041 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U)
119042 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
119043 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
119044  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119045  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119046  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119047  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119048  */
119049 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT29(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK)
119050 
119051 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U)
119052 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
119053 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
119054  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119055  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119056  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119057  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119058  */
119059 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT30(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK)
119060 
119061 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U)
119062 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
119063 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
119064  *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
119065  *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
119066  *  0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding
119067  *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
119068  */
119069 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT31(x)   (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK)
119070 /*! @} */
119071 
119072 /* The count of TRDC_MBC_DOM15_MEM3_BLK_NSE_W */
119073 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_COUNT      (2U)
119074 
119075 /* The count of TRDC_MBC_DOM15_MEM3_BLK_NSE_W */
119076 #define TRDC_MBC_DOM15_MEM3_BLK_NSE_W_COUNT2     (1U)
119077 
119078 /*! @name MRC_GLBCFG - MRC Global Configuration Register */
119079 /*! @{ */
119080 
119081 #define TRDC_MRC_GLBCFG_NRGNS_MASK               (0x1FU)
119082 #define TRDC_MRC_GLBCFG_NRGNS_SHIFT              (0U)
119083 /*! NRGNS - Number of regions [1-16] */
119084 #define TRDC_MRC_GLBCFG_NRGNS(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MRC_GLBCFG_NRGNS_MASK)
119085 /*! @} */
119086 
119087 /* The count of TRDC_MRC_GLBCFG */
119088 #define TRDC_MRC_GLBCFG_COUNT                    (7U)
119089 
119090 /*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */
119091 /*! @{ */
119092 
119093 #define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK   (0xFFFF0000U)
119094 #define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT  (16U)
119095 /*! DID_SEL - DID Select */
119096 #define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK)
119097 /*! @} */
119098 
119099 /* The count of TRDC_MRC_NSE_RGN_INDIRECT */
119100 #define TRDC_MRC_NSE_RGN_INDIRECT_COUNT          (7U)
119101 
119102 /*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */
119103 /*! @{ */
119104 
119105 #define TRDC_MRC_NSE_RGN_SET_W1SET_MASK          (0xFFFFU)
119106 #define TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT         (0U)
119107 /*! W1SET - Write-1 Set */
119108 #define TRDC_MRC_NSE_RGN_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MRC_NSE_RGN_SET_W1SET_MASK)
119109 /*! @} */
119110 
119111 /* The count of TRDC_MRC_NSE_RGN_SET */
119112 #define TRDC_MRC_NSE_RGN_SET_COUNT               (7U)
119113 
119114 /*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */
119115 /*! @{ */
119116 
119117 #define TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK          (0xFFFFU)
119118 #define TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT         (0U)
119119 /*! W1CLR - Write-1 Clear */
119120 #define TRDC_MRC_NSE_RGN_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK)
119121 /*! @} */
119122 
119123 /* The count of TRDC_MRC_NSE_RGN_CLR */
119124 #define TRDC_MRC_NSE_RGN_CLR_COUNT               (7U)
119125 
119126 /*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */
119127 /*! @{ */
119128 
119129 #define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK    (0xFFFF0000U)
119130 #define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT   (16U)
119131 /*! DID_SEL - DID Select */
119132 #define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK)
119133 /*! @} */
119134 
119135 /* The count of TRDC_MRC_NSE_RGN_CLR_ALL */
119136 #define TRDC_MRC_NSE_RGN_CLR_ALL_COUNT           (7U)
119137 
119138 /*! @name MRC_GLBAC - MRC Global Access Control */
119139 /*! @{ */
119140 
119141 #define TRDC_MRC_GLBAC_NUX_MASK                  (0x1U)
119142 #define TRDC_MRC_GLBAC_NUX_SHIFT                 (0U)
119143 /*! NUX - NonsecureUser Execute
119144  *  0b0..Execute access is not allowed in Nonsecure User mode.
119145  *  0b1..Execute access is allowed in Nonsecure User mode.
119146  */
119147 #define TRDC_MRC_GLBAC_NUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUX_SHIFT)) & TRDC_MRC_GLBAC_NUX_MASK)
119148 
119149 #define TRDC_MRC_GLBAC_NUW_MASK                  (0x2U)
119150 #define TRDC_MRC_GLBAC_NUW_SHIFT                 (1U)
119151 /*! NUW - NonsecureUser Write
119152  *  0b0..Write access is not allowed in Nonsecure User mode.
119153  *  0b1..Write access is allowed in Nonsecure User mode.
119154  */
119155 #define TRDC_MRC_GLBAC_NUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUW_SHIFT)) & TRDC_MRC_GLBAC_NUW_MASK)
119156 
119157 #define TRDC_MRC_GLBAC_NUR_MASK                  (0x4U)
119158 #define TRDC_MRC_GLBAC_NUR_SHIFT                 (2U)
119159 /*! NUR - NonsecureUser Read
119160  *  0b0..Read access is not allowed in Nonsecure User mode.
119161  *  0b1..Read access is allowed in Nonsecure User mode.
119162  */
119163 #define TRDC_MRC_GLBAC_NUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUR_SHIFT)) & TRDC_MRC_GLBAC_NUR_MASK)
119164 
119165 #define TRDC_MRC_GLBAC_NPX_MASK                  (0x10U)
119166 #define TRDC_MRC_GLBAC_NPX_SHIFT                 (4U)
119167 /*! NPX - NonsecurePriv Execute
119168  *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
119169  *  0b1..Execute access is allowed in Nonsecure Privilege mode.
119170  */
119171 #define TRDC_MRC_GLBAC_NPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPX_SHIFT)) & TRDC_MRC_GLBAC_NPX_MASK)
119172 
119173 #define TRDC_MRC_GLBAC_NPW_MASK                  (0x20U)
119174 #define TRDC_MRC_GLBAC_NPW_SHIFT                 (5U)
119175 /*! NPW - NonsecurePriv Write
119176  *  0b0..Write access is not allowed in Nonsecure Privilege mode.
119177  *  0b1..Write access is allowed in Nonsecure Privilege mode.
119178  */
119179 #define TRDC_MRC_GLBAC_NPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPW_SHIFT)) & TRDC_MRC_GLBAC_NPW_MASK)
119180 
119181 #define TRDC_MRC_GLBAC_NPR_MASK                  (0x40U)
119182 #define TRDC_MRC_GLBAC_NPR_SHIFT                 (6U)
119183 /*! NPR - NonsecurePriv Read
119184  *  0b0..Read access is not allowed in Nonsecure Privilege mode.
119185  *  0b1..Read access is allowed in Nonsecure Privilege mode.
119186  */
119187 #define TRDC_MRC_GLBAC_NPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPR_SHIFT)) & TRDC_MRC_GLBAC_NPR_MASK)
119188 
119189 #define TRDC_MRC_GLBAC_SUX_MASK                  (0x100U)
119190 #define TRDC_MRC_GLBAC_SUX_SHIFT                 (8U)
119191 /*! SUX - SecureUser Execute
119192  *  0b0..Execute access is not allowed in Secure User mode.
119193  *  0b1..Execute access is allowed in Secure User mode.
119194  */
119195 #define TRDC_MRC_GLBAC_SUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUX_SHIFT)) & TRDC_MRC_GLBAC_SUX_MASK)
119196 
119197 #define TRDC_MRC_GLBAC_SUW_MASK                  (0x200U)
119198 #define TRDC_MRC_GLBAC_SUW_SHIFT                 (9U)
119199 /*! SUW - SecureUser Write
119200  *  0b0..Write access is not allowed in Secure User mode.
119201  *  0b1..Write access is allowed in Secure User mode.
119202  */
119203 #define TRDC_MRC_GLBAC_SUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUW_SHIFT)) & TRDC_MRC_GLBAC_SUW_MASK)
119204 
119205 #define TRDC_MRC_GLBAC_SUR_MASK                  (0x400U)
119206 #define TRDC_MRC_GLBAC_SUR_SHIFT                 (10U)
119207 /*! SUR - SecureUser Read
119208  *  0b0..Read access is not allowed in Secure User mode.
119209  *  0b1..Read access is allowed in Secure User mode.
119210  */
119211 #define TRDC_MRC_GLBAC_SUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUR_SHIFT)) & TRDC_MRC_GLBAC_SUR_MASK)
119212 
119213 #define TRDC_MRC_GLBAC_SPX_MASK                  (0x1000U)
119214 #define TRDC_MRC_GLBAC_SPX_SHIFT                 (12U)
119215 /*! SPX - SecurePriv Execute
119216  *  0b0..Execute access is not allowed in Secure Privilege mode.
119217  *  0b1..Execute access is allowed in Secure Privilege mode.
119218  */
119219 #define TRDC_MRC_GLBAC_SPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPX_SHIFT)) & TRDC_MRC_GLBAC_SPX_MASK)
119220 
119221 #define TRDC_MRC_GLBAC_SPW_MASK                  (0x2000U)
119222 #define TRDC_MRC_GLBAC_SPW_SHIFT                 (13U)
119223 /*! SPW - SecurePriv Write
119224  *  0b0..Write access is not allowed in Secure Privilege mode.
119225  *  0b1..Write access is allowed in Secure Privilege mode.
119226  */
119227 #define TRDC_MRC_GLBAC_SPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPW_SHIFT)) & TRDC_MRC_GLBAC_SPW_MASK)
119228 
119229 #define TRDC_MRC_GLBAC_SPR_MASK                  (0x4000U)
119230 #define TRDC_MRC_GLBAC_SPR_SHIFT                 (14U)
119231 /*! SPR - SecurePriv Read
119232  *  0b0..Read access is not allowed in Secure Privilege mode.
119233  *  0b1..Read access is allowed in Secure Privilege mode.
119234  */
119235 #define TRDC_MRC_GLBAC_SPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPR_SHIFT)) & TRDC_MRC_GLBAC_SPR_MASK)
119236 
119237 #define TRDC_MRC_GLBAC_LK_MASK                   (0x80000000U)
119238 #define TRDC_MRC_GLBAC_LK_SHIFT                  (31U)
119239 /*! LK - LOCK
119240  *  0b0..This register is not locked and can be altered.
119241  *  0b1..This register is locked (read-only) and cannot be altered.
119242  */
119243 #define TRDC_MRC_GLBAC_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_LK_SHIFT)) & TRDC_MRC_GLBAC_LK_MASK)
119244 /*! @} */
119245 
119246 /* The count of TRDC_MRC_GLBAC */
119247 #define TRDC_MRC_GLBAC_COUNT                     (7U)
119248 
119249 /* The count of TRDC_MRC_GLBAC */
119250 #define TRDC_MRC_GLBAC_COUNT2                    (8U)
119251 
119252 /*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
119253 /*! @{ */
119254 
119255 #define TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK         (0x7U)
119256 #define TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT        (0U)
119257 /*! MRACSEL - Memory Region Access Control Select
119258  *  0b000..Select MRC_GLBAC0 access control policy
119259  *  0b001..Select MRC_GLBAC1 access control policy
119260  *  0b010..Select MRC_GLBAC2 access control policy
119261  *  0b011..Select MRC_GLBAC3 access control policy
119262  *  0b100..Select MRC_GLBAC4 access control policy
119263  *  0b101..Select MRC_GLBAC5 access control policy
119264  *  0b110..Select MRC_GLBAC6 access control policy
119265  *  0b111..Select MRC_GLBAC7 access control policy
119266  */
119267 #define TRDC_MRC_DOM0_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK)
119268 
119269 #define TRDC_MRC_DOM0_RGD_W_VLD_MASK             (0x1U)
119270 #define TRDC_MRC_DOM0_RGD_W_VLD_SHIFT            (0U)
119271 /*! VLD - Valid */
119272 #define TRDC_MRC_DOM0_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM0_RGD_W_VLD_MASK)
119273 
119274 #define TRDC_MRC_DOM0_RGD_W_NSE_MASK             (0x10U)
119275 #define TRDC_MRC_DOM0_RGD_W_NSE_SHIFT            (4U)
119276 /*! NSE - NonSecure Enable
119277  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119278  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119279  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119280  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119281  */
119282 #define TRDC_MRC_DOM0_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM0_RGD_W_NSE_MASK)
119283 
119284 #define TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
119285 #define TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT       (14U)
119286 /*! END_ADDR - End Address */
119287 #define TRDC_MRC_DOM0_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK)
119288 
119289 #define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
119290 #define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT      (14U)
119291 /*! STRT_ADDR - Start Address */
119292 #define TRDC_MRC_DOM0_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK)
119293 /*! @} */
119294 
119295 /* The count of TRDC_MRC_DOM0_RGD_W */
119296 #define TRDC_MRC_DOM0_RGD_W_COUNT                (7U)
119297 
119298 /* The count of TRDC_MRC_DOM0_RGD_W */
119299 #define TRDC_MRC_DOM0_RGD_W_COUNT2               (16U)
119300 
119301 /* The count of TRDC_MRC_DOM0_RGD_W */
119302 #define TRDC_MRC_DOM0_RGD_W_COUNT3               (2U)
119303 
119304 /*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */
119305 /*! @{ */
119306 
119307 #define TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK          (0x1U)
119308 #define TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT         (0U)
119309 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
119310  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119311  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119312  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119313  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119314  */
119315 #define TRDC_MRC_DOM0_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK)
119316 
119317 #define TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK          (0x2U)
119318 #define TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT         (1U)
119319 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
119320  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119321  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119322  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119323  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119324  */
119325 #define TRDC_MRC_DOM0_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK)
119326 
119327 #define TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK          (0x4U)
119328 #define TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT         (2U)
119329 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
119330  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119331  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119332  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119333  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119334  */
119335 #define TRDC_MRC_DOM0_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK)
119336 
119337 #define TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK          (0x8U)
119338 #define TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT         (3U)
119339 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
119340  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119341  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119342  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119343  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119344  */
119345 #define TRDC_MRC_DOM0_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK)
119346 
119347 #define TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK          (0x10U)
119348 #define TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT         (4U)
119349 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
119350  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119351  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119352  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119353  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119354  */
119355 #define TRDC_MRC_DOM0_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK)
119356 
119357 #define TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK          (0x20U)
119358 #define TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT         (5U)
119359 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
119360  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119361  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119362  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119363  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119364  */
119365 #define TRDC_MRC_DOM0_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK)
119366 
119367 #define TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK          (0x40U)
119368 #define TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT         (6U)
119369 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
119370  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119371  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119372  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119373  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119374  */
119375 #define TRDC_MRC_DOM0_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK)
119376 
119377 #define TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK          (0x80U)
119378 #define TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT         (7U)
119379 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
119380  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119381  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119382  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119383  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119384  */
119385 #define TRDC_MRC_DOM0_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK)
119386 
119387 #define TRDC_MRC_DOM0_RGD_NSE_BIT8_MASK          (0x100U)
119388 #define TRDC_MRC_DOM0_RGD_NSE_BIT8_SHIFT         (8U)
119389 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
119390  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119391  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119392  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119393  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119394  */
119395 #define TRDC_MRC_DOM0_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT8_MASK)
119396 
119397 #define TRDC_MRC_DOM0_RGD_NSE_BIT9_MASK          (0x200U)
119398 #define TRDC_MRC_DOM0_RGD_NSE_BIT9_SHIFT         (9U)
119399 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
119400  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119401  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119402  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119403  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119404  */
119405 #define TRDC_MRC_DOM0_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT9_MASK)
119406 
119407 #define TRDC_MRC_DOM0_RGD_NSE_BIT10_MASK         (0x400U)
119408 #define TRDC_MRC_DOM0_RGD_NSE_BIT10_SHIFT        (10U)
119409 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
119410  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119411  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119412  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119413  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119414  */
119415 #define TRDC_MRC_DOM0_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT10_MASK)
119416 
119417 #define TRDC_MRC_DOM0_RGD_NSE_BIT11_MASK         (0x800U)
119418 #define TRDC_MRC_DOM0_RGD_NSE_BIT11_SHIFT        (11U)
119419 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
119420  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119421  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119422  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119423  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119424  */
119425 #define TRDC_MRC_DOM0_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT11_MASK)
119426 
119427 #define TRDC_MRC_DOM0_RGD_NSE_BIT12_MASK         (0x1000U)
119428 #define TRDC_MRC_DOM0_RGD_NSE_BIT12_SHIFT        (12U)
119429 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
119430  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119431  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119432  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119433  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119434  */
119435 #define TRDC_MRC_DOM0_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT12_MASK)
119436 
119437 #define TRDC_MRC_DOM0_RGD_NSE_BIT13_MASK         (0x2000U)
119438 #define TRDC_MRC_DOM0_RGD_NSE_BIT13_SHIFT        (13U)
119439 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
119440  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119441  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119442  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119443  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119444  */
119445 #define TRDC_MRC_DOM0_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT13_MASK)
119446 
119447 #define TRDC_MRC_DOM0_RGD_NSE_BIT14_MASK         (0x4000U)
119448 #define TRDC_MRC_DOM0_RGD_NSE_BIT14_SHIFT        (14U)
119449 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
119450  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119451  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119452  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119453  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119454  */
119455 #define TRDC_MRC_DOM0_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT14_MASK)
119456 
119457 #define TRDC_MRC_DOM0_RGD_NSE_BIT15_MASK         (0x8000U)
119458 #define TRDC_MRC_DOM0_RGD_NSE_BIT15_SHIFT        (15U)
119459 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
119460  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119461  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119462  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119463  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119464  */
119465 #define TRDC_MRC_DOM0_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT15_MASK)
119466 /*! @} */
119467 
119468 /* The count of TRDC_MRC_DOM0_RGD_NSE */
119469 #define TRDC_MRC_DOM0_RGD_NSE_COUNT              (7U)
119470 
119471 /*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
119472 /*! @{ */
119473 
119474 #define TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK         (0x7U)
119475 #define TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT        (0U)
119476 /*! MRACSEL - Memory Region Access Control Select
119477  *  0b000..Select MRC_GLBAC0 access control policy
119478  *  0b001..Select MRC_GLBAC1 access control policy
119479  *  0b010..Select MRC_GLBAC2 access control policy
119480  *  0b011..Select MRC_GLBAC3 access control policy
119481  *  0b100..Select MRC_GLBAC4 access control policy
119482  *  0b101..Select MRC_GLBAC5 access control policy
119483  *  0b110..Select MRC_GLBAC6 access control policy
119484  *  0b111..Select MRC_GLBAC7 access control policy
119485  */
119486 #define TRDC_MRC_DOM1_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK)
119487 
119488 #define TRDC_MRC_DOM1_RGD_W_VLD_MASK             (0x1U)
119489 #define TRDC_MRC_DOM1_RGD_W_VLD_SHIFT            (0U)
119490 /*! VLD - Valid */
119491 #define TRDC_MRC_DOM1_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM1_RGD_W_VLD_MASK)
119492 
119493 #define TRDC_MRC_DOM1_RGD_W_NSE_MASK             (0x10U)
119494 #define TRDC_MRC_DOM1_RGD_W_NSE_SHIFT            (4U)
119495 /*! NSE - NonSecure Enable
119496  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119497  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119498  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119499  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119500  */
119501 #define TRDC_MRC_DOM1_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM1_RGD_W_NSE_MASK)
119502 
119503 #define TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
119504 #define TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT       (14U)
119505 /*! END_ADDR - End Address */
119506 #define TRDC_MRC_DOM1_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK)
119507 
119508 #define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
119509 #define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT      (14U)
119510 /*! STRT_ADDR - Start Address */
119511 #define TRDC_MRC_DOM1_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK)
119512 /*! @} */
119513 
119514 /* The count of TRDC_MRC_DOM1_RGD_W */
119515 #define TRDC_MRC_DOM1_RGD_W_COUNT                (7U)
119516 
119517 /* The count of TRDC_MRC_DOM1_RGD_W */
119518 #define TRDC_MRC_DOM1_RGD_W_COUNT2               (16U)
119519 
119520 /* The count of TRDC_MRC_DOM1_RGD_W */
119521 #define TRDC_MRC_DOM1_RGD_W_COUNT3               (2U)
119522 
119523 /*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */
119524 /*! @{ */
119525 
119526 #define TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK          (0x1U)
119527 #define TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT         (0U)
119528 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
119529  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119530  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119531  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119532  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119533  */
119534 #define TRDC_MRC_DOM1_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK)
119535 
119536 #define TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK          (0x2U)
119537 #define TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT         (1U)
119538 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
119539  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119540  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119541  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119542  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119543  */
119544 #define TRDC_MRC_DOM1_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK)
119545 
119546 #define TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK          (0x4U)
119547 #define TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT         (2U)
119548 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
119549  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119550  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119551  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119552  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119553  */
119554 #define TRDC_MRC_DOM1_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK)
119555 
119556 #define TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK          (0x8U)
119557 #define TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT         (3U)
119558 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
119559  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119560  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119561  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119562  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119563  */
119564 #define TRDC_MRC_DOM1_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK)
119565 
119566 #define TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK          (0x10U)
119567 #define TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT         (4U)
119568 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
119569  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119570  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119571  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119572  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119573  */
119574 #define TRDC_MRC_DOM1_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK)
119575 
119576 #define TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK          (0x20U)
119577 #define TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT         (5U)
119578 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
119579  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119580  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119581  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119582  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119583  */
119584 #define TRDC_MRC_DOM1_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK)
119585 
119586 #define TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK          (0x40U)
119587 #define TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT         (6U)
119588 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
119589  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119590  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119591  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119592  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119593  */
119594 #define TRDC_MRC_DOM1_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK)
119595 
119596 #define TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK          (0x80U)
119597 #define TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT         (7U)
119598 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
119599  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119600  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119601  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119602  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119603  */
119604 #define TRDC_MRC_DOM1_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK)
119605 
119606 #define TRDC_MRC_DOM1_RGD_NSE_BIT8_MASK          (0x100U)
119607 #define TRDC_MRC_DOM1_RGD_NSE_BIT8_SHIFT         (8U)
119608 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
119609  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119610  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119611  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119612  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119613  */
119614 #define TRDC_MRC_DOM1_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT8_MASK)
119615 
119616 #define TRDC_MRC_DOM1_RGD_NSE_BIT9_MASK          (0x200U)
119617 #define TRDC_MRC_DOM1_RGD_NSE_BIT9_SHIFT         (9U)
119618 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
119619  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119620  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119621  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119622  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119623  */
119624 #define TRDC_MRC_DOM1_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT9_MASK)
119625 
119626 #define TRDC_MRC_DOM1_RGD_NSE_BIT10_MASK         (0x400U)
119627 #define TRDC_MRC_DOM1_RGD_NSE_BIT10_SHIFT        (10U)
119628 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
119629  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119630  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119631  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119632  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119633  */
119634 #define TRDC_MRC_DOM1_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT10_MASK)
119635 
119636 #define TRDC_MRC_DOM1_RGD_NSE_BIT11_MASK         (0x800U)
119637 #define TRDC_MRC_DOM1_RGD_NSE_BIT11_SHIFT        (11U)
119638 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
119639  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119640  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119641  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119642  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119643  */
119644 #define TRDC_MRC_DOM1_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT11_MASK)
119645 
119646 #define TRDC_MRC_DOM1_RGD_NSE_BIT12_MASK         (0x1000U)
119647 #define TRDC_MRC_DOM1_RGD_NSE_BIT12_SHIFT        (12U)
119648 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
119649  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119650  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119651  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119652  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119653  */
119654 #define TRDC_MRC_DOM1_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT12_MASK)
119655 
119656 #define TRDC_MRC_DOM1_RGD_NSE_BIT13_MASK         (0x2000U)
119657 #define TRDC_MRC_DOM1_RGD_NSE_BIT13_SHIFT        (13U)
119658 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
119659  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119660  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119661  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119662  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119663  */
119664 #define TRDC_MRC_DOM1_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT13_MASK)
119665 
119666 #define TRDC_MRC_DOM1_RGD_NSE_BIT14_MASK         (0x4000U)
119667 #define TRDC_MRC_DOM1_RGD_NSE_BIT14_SHIFT        (14U)
119668 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
119669  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119670  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119671  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119672  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119673  */
119674 #define TRDC_MRC_DOM1_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT14_MASK)
119675 
119676 #define TRDC_MRC_DOM1_RGD_NSE_BIT15_MASK         (0x8000U)
119677 #define TRDC_MRC_DOM1_RGD_NSE_BIT15_SHIFT        (15U)
119678 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
119679  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119680  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119681  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119682  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119683  */
119684 #define TRDC_MRC_DOM1_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT15_MASK)
119685 /*! @} */
119686 
119687 /* The count of TRDC_MRC_DOM1_RGD_NSE */
119688 #define TRDC_MRC_DOM1_RGD_NSE_COUNT              (7U)
119689 
119690 /*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
119691 /*! @{ */
119692 
119693 #define TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK         (0x7U)
119694 #define TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT        (0U)
119695 /*! MRACSEL - Memory Region Access Control Select
119696  *  0b000..Select MRC_GLBAC0 access control policy
119697  *  0b001..Select MRC_GLBAC1 access control policy
119698  *  0b010..Select MRC_GLBAC2 access control policy
119699  *  0b011..Select MRC_GLBAC3 access control policy
119700  *  0b100..Select MRC_GLBAC4 access control policy
119701  *  0b101..Select MRC_GLBAC5 access control policy
119702  *  0b110..Select MRC_GLBAC6 access control policy
119703  *  0b111..Select MRC_GLBAC7 access control policy
119704  */
119705 #define TRDC_MRC_DOM2_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK)
119706 
119707 #define TRDC_MRC_DOM2_RGD_W_VLD_MASK             (0x1U)
119708 #define TRDC_MRC_DOM2_RGD_W_VLD_SHIFT            (0U)
119709 /*! VLD - Valid */
119710 #define TRDC_MRC_DOM2_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM2_RGD_W_VLD_MASK)
119711 
119712 #define TRDC_MRC_DOM2_RGD_W_NSE_MASK             (0x10U)
119713 #define TRDC_MRC_DOM2_RGD_W_NSE_SHIFT            (4U)
119714 /*! NSE - NonSecure Enable
119715  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119716  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119717  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119718  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119719  */
119720 #define TRDC_MRC_DOM2_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM2_RGD_W_NSE_MASK)
119721 
119722 #define TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
119723 #define TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT       (14U)
119724 /*! END_ADDR - End Address */
119725 #define TRDC_MRC_DOM2_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK)
119726 
119727 #define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
119728 #define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT      (14U)
119729 /*! STRT_ADDR - Start Address */
119730 #define TRDC_MRC_DOM2_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK)
119731 /*! @} */
119732 
119733 /* The count of TRDC_MRC_DOM2_RGD_W */
119734 #define TRDC_MRC_DOM2_RGD_W_COUNT                (7U)
119735 
119736 /* The count of TRDC_MRC_DOM2_RGD_W */
119737 #define TRDC_MRC_DOM2_RGD_W_COUNT2               (16U)
119738 
119739 /* The count of TRDC_MRC_DOM2_RGD_W */
119740 #define TRDC_MRC_DOM2_RGD_W_COUNT3               (2U)
119741 
119742 /*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */
119743 /*! @{ */
119744 
119745 #define TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK          (0x1U)
119746 #define TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT         (0U)
119747 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
119748  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119749  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119750  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119751  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119752  */
119753 #define TRDC_MRC_DOM2_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK)
119754 
119755 #define TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK          (0x2U)
119756 #define TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT         (1U)
119757 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
119758  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119759  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119760  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119761  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119762  */
119763 #define TRDC_MRC_DOM2_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK)
119764 
119765 #define TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK          (0x4U)
119766 #define TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT         (2U)
119767 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
119768  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119769  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119770  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119771  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119772  */
119773 #define TRDC_MRC_DOM2_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK)
119774 
119775 #define TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK          (0x8U)
119776 #define TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT         (3U)
119777 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
119778  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119779  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119780  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119781  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119782  */
119783 #define TRDC_MRC_DOM2_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK)
119784 
119785 #define TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK          (0x10U)
119786 #define TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT         (4U)
119787 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
119788  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119789  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119790  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119791  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119792  */
119793 #define TRDC_MRC_DOM2_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK)
119794 
119795 #define TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK          (0x20U)
119796 #define TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT         (5U)
119797 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
119798  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119799  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119800  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119801  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119802  */
119803 #define TRDC_MRC_DOM2_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK)
119804 
119805 #define TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK          (0x40U)
119806 #define TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT         (6U)
119807 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
119808  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119809  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119810  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119811  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119812  */
119813 #define TRDC_MRC_DOM2_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK)
119814 
119815 #define TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK          (0x80U)
119816 #define TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT         (7U)
119817 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
119818  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119819  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119820  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119821  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119822  */
119823 #define TRDC_MRC_DOM2_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK)
119824 
119825 #define TRDC_MRC_DOM2_RGD_NSE_BIT8_MASK          (0x100U)
119826 #define TRDC_MRC_DOM2_RGD_NSE_BIT8_SHIFT         (8U)
119827 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
119828  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119829  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119830  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119831  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119832  */
119833 #define TRDC_MRC_DOM2_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT8_MASK)
119834 
119835 #define TRDC_MRC_DOM2_RGD_NSE_BIT9_MASK          (0x200U)
119836 #define TRDC_MRC_DOM2_RGD_NSE_BIT9_SHIFT         (9U)
119837 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
119838  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119839  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119840  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119841  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119842  */
119843 #define TRDC_MRC_DOM2_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT9_MASK)
119844 
119845 #define TRDC_MRC_DOM2_RGD_NSE_BIT10_MASK         (0x400U)
119846 #define TRDC_MRC_DOM2_RGD_NSE_BIT10_SHIFT        (10U)
119847 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
119848  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119849  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119850  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119851  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119852  */
119853 #define TRDC_MRC_DOM2_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT10_MASK)
119854 
119855 #define TRDC_MRC_DOM2_RGD_NSE_BIT11_MASK         (0x800U)
119856 #define TRDC_MRC_DOM2_RGD_NSE_BIT11_SHIFT        (11U)
119857 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
119858  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119859  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119860  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119861  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119862  */
119863 #define TRDC_MRC_DOM2_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT11_MASK)
119864 
119865 #define TRDC_MRC_DOM2_RGD_NSE_BIT12_MASK         (0x1000U)
119866 #define TRDC_MRC_DOM2_RGD_NSE_BIT12_SHIFT        (12U)
119867 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
119868  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119869  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119870  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119871  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119872  */
119873 #define TRDC_MRC_DOM2_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT12_MASK)
119874 
119875 #define TRDC_MRC_DOM2_RGD_NSE_BIT13_MASK         (0x2000U)
119876 #define TRDC_MRC_DOM2_RGD_NSE_BIT13_SHIFT        (13U)
119877 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
119878  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119879  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119880  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119881  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119882  */
119883 #define TRDC_MRC_DOM2_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT13_MASK)
119884 
119885 #define TRDC_MRC_DOM2_RGD_NSE_BIT14_MASK         (0x4000U)
119886 #define TRDC_MRC_DOM2_RGD_NSE_BIT14_SHIFT        (14U)
119887 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
119888  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119889  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119890  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119891  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119892  */
119893 #define TRDC_MRC_DOM2_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT14_MASK)
119894 
119895 #define TRDC_MRC_DOM2_RGD_NSE_BIT15_MASK         (0x8000U)
119896 #define TRDC_MRC_DOM2_RGD_NSE_BIT15_SHIFT        (15U)
119897 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
119898  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119899  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119900  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119901  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119902  */
119903 #define TRDC_MRC_DOM2_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT15_MASK)
119904 /*! @} */
119905 
119906 /* The count of TRDC_MRC_DOM2_RGD_NSE */
119907 #define TRDC_MRC_DOM2_RGD_NSE_COUNT              (7U)
119908 
119909 /*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
119910 /*! @{ */
119911 
119912 #define TRDC_MRC_DOM3_RGD_W_MRACSEL_MASK         (0x7U)
119913 #define TRDC_MRC_DOM3_RGD_W_MRACSEL_SHIFT        (0U)
119914 /*! MRACSEL - Memory Region Access Control Select
119915  *  0b000..Select MRC_GLBAC0 access control policy
119916  *  0b001..Select MRC_GLBAC1 access control policy
119917  *  0b010..Select MRC_GLBAC2 access control policy
119918  *  0b011..Select MRC_GLBAC3 access control policy
119919  *  0b100..Select MRC_GLBAC4 access control policy
119920  *  0b101..Select MRC_GLBAC5 access control policy
119921  *  0b110..Select MRC_GLBAC6 access control policy
119922  *  0b111..Select MRC_GLBAC7 access control policy
119923  */
119924 #define TRDC_MRC_DOM3_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM3_RGD_W_MRACSEL_MASK)
119925 
119926 #define TRDC_MRC_DOM3_RGD_W_VLD_MASK             (0x1U)
119927 #define TRDC_MRC_DOM3_RGD_W_VLD_SHIFT            (0U)
119928 /*! VLD - Valid */
119929 #define TRDC_MRC_DOM3_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM3_RGD_W_VLD_MASK)
119930 
119931 #define TRDC_MRC_DOM3_RGD_W_NSE_MASK             (0x10U)
119932 #define TRDC_MRC_DOM3_RGD_W_NSE_SHIFT            (4U)
119933 /*! NSE - NonSecure Enable
119934  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119935  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119936  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119937  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119938  */
119939 #define TRDC_MRC_DOM3_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM3_RGD_W_NSE_MASK)
119940 
119941 #define TRDC_MRC_DOM3_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
119942 #define TRDC_MRC_DOM3_RGD_W_END_ADDR_SHIFT       (14U)
119943 /*! END_ADDR - End Address */
119944 #define TRDC_MRC_DOM3_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM3_RGD_W_END_ADDR_MASK)
119945 
119946 #define TRDC_MRC_DOM3_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
119947 #define TRDC_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT      (14U)
119948 /*! STRT_ADDR - Start Address */
119949 #define TRDC_MRC_DOM3_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM3_RGD_W_STRT_ADDR_MASK)
119950 /*! @} */
119951 
119952 /* The count of TRDC_MRC_DOM3_RGD_W */
119953 #define TRDC_MRC_DOM3_RGD_W_COUNT                (7U)
119954 
119955 /* The count of TRDC_MRC_DOM3_RGD_W */
119956 #define TRDC_MRC_DOM3_RGD_W_COUNT2               (16U)
119957 
119958 /* The count of TRDC_MRC_DOM3_RGD_W */
119959 #define TRDC_MRC_DOM3_RGD_W_COUNT3               (2U)
119960 
119961 /*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */
119962 /*! @{ */
119963 
119964 #define TRDC_MRC_DOM3_RGD_NSE_BIT0_MASK          (0x1U)
119965 #define TRDC_MRC_DOM3_RGD_NSE_BIT0_SHIFT         (0U)
119966 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
119967  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119968  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119969  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119970  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119971  */
119972 #define TRDC_MRC_DOM3_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT0_MASK)
119973 
119974 #define TRDC_MRC_DOM3_RGD_NSE_BIT1_MASK          (0x2U)
119975 #define TRDC_MRC_DOM3_RGD_NSE_BIT1_SHIFT         (1U)
119976 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
119977  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119978  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119979  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119980  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119981  */
119982 #define TRDC_MRC_DOM3_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT1_MASK)
119983 
119984 #define TRDC_MRC_DOM3_RGD_NSE_BIT2_MASK          (0x4U)
119985 #define TRDC_MRC_DOM3_RGD_NSE_BIT2_SHIFT         (2U)
119986 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
119987  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119988  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119989  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
119990  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
119991  */
119992 #define TRDC_MRC_DOM3_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT2_MASK)
119993 
119994 #define TRDC_MRC_DOM3_RGD_NSE_BIT3_MASK          (0x8U)
119995 #define TRDC_MRC_DOM3_RGD_NSE_BIT3_SHIFT         (3U)
119996 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
119997  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
119998  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
119999  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120000  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120001  */
120002 #define TRDC_MRC_DOM3_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT3_MASK)
120003 
120004 #define TRDC_MRC_DOM3_RGD_NSE_BIT4_MASK          (0x10U)
120005 #define TRDC_MRC_DOM3_RGD_NSE_BIT4_SHIFT         (4U)
120006 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
120007  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120008  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120009  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120010  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120011  */
120012 #define TRDC_MRC_DOM3_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT4_MASK)
120013 
120014 #define TRDC_MRC_DOM3_RGD_NSE_BIT5_MASK          (0x20U)
120015 #define TRDC_MRC_DOM3_RGD_NSE_BIT5_SHIFT         (5U)
120016 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
120017  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120018  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120019  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120020  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120021  */
120022 #define TRDC_MRC_DOM3_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT5_MASK)
120023 
120024 #define TRDC_MRC_DOM3_RGD_NSE_BIT6_MASK          (0x40U)
120025 #define TRDC_MRC_DOM3_RGD_NSE_BIT6_SHIFT         (6U)
120026 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
120027  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120028  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120029  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120030  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120031  */
120032 #define TRDC_MRC_DOM3_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT6_MASK)
120033 
120034 #define TRDC_MRC_DOM3_RGD_NSE_BIT7_MASK          (0x80U)
120035 #define TRDC_MRC_DOM3_RGD_NSE_BIT7_SHIFT         (7U)
120036 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
120037  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120038  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120039  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120040  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120041  */
120042 #define TRDC_MRC_DOM3_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT7_MASK)
120043 
120044 #define TRDC_MRC_DOM3_RGD_NSE_BIT8_MASK          (0x100U)
120045 #define TRDC_MRC_DOM3_RGD_NSE_BIT8_SHIFT         (8U)
120046 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
120047  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120048  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120049  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120050  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120051  */
120052 #define TRDC_MRC_DOM3_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT8_MASK)
120053 
120054 #define TRDC_MRC_DOM3_RGD_NSE_BIT9_MASK          (0x200U)
120055 #define TRDC_MRC_DOM3_RGD_NSE_BIT9_SHIFT         (9U)
120056 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
120057  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120058  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120059  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120060  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120061  */
120062 #define TRDC_MRC_DOM3_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT9_MASK)
120063 
120064 #define TRDC_MRC_DOM3_RGD_NSE_BIT10_MASK         (0x400U)
120065 #define TRDC_MRC_DOM3_RGD_NSE_BIT10_SHIFT        (10U)
120066 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
120067  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120068  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120069  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120070  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120071  */
120072 #define TRDC_MRC_DOM3_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT10_MASK)
120073 
120074 #define TRDC_MRC_DOM3_RGD_NSE_BIT11_MASK         (0x800U)
120075 #define TRDC_MRC_DOM3_RGD_NSE_BIT11_SHIFT        (11U)
120076 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
120077  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120078  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120079  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120080  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120081  */
120082 #define TRDC_MRC_DOM3_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT11_MASK)
120083 
120084 #define TRDC_MRC_DOM3_RGD_NSE_BIT12_MASK         (0x1000U)
120085 #define TRDC_MRC_DOM3_RGD_NSE_BIT12_SHIFT        (12U)
120086 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
120087  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120088  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120089  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120090  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120091  */
120092 #define TRDC_MRC_DOM3_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT12_MASK)
120093 
120094 #define TRDC_MRC_DOM3_RGD_NSE_BIT13_MASK         (0x2000U)
120095 #define TRDC_MRC_DOM3_RGD_NSE_BIT13_SHIFT        (13U)
120096 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
120097  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120098  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120099  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120100  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120101  */
120102 #define TRDC_MRC_DOM3_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT13_MASK)
120103 
120104 #define TRDC_MRC_DOM3_RGD_NSE_BIT14_MASK         (0x4000U)
120105 #define TRDC_MRC_DOM3_RGD_NSE_BIT14_SHIFT        (14U)
120106 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
120107  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120108  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120109  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120110  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120111  */
120112 #define TRDC_MRC_DOM3_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT14_MASK)
120113 
120114 #define TRDC_MRC_DOM3_RGD_NSE_BIT15_MASK         (0x8000U)
120115 #define TRDC_MRC_DOM3_RGD_NSE_BIT15_SHIFT        (15U)
120116 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
120117  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120118  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120119  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120120  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120121  */
120122 #define TRDC_MRC_DOM3_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM3_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM3_RGD_NSE_BIT15_MASK)
120123 /*! @} */
120124 
120125 /* The count of TRDC_MRC_DOM3_RGD_NSE */
120126 #define TRDC_MRC_DOM3_RGD_NSE_COUNT              (7U)
120127 
120128 /*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
120129 /*! @{ */
120130 
120131 #define TRDC_MRC_DOM4_RGD_W_MRACSEL_MASK         (0x7U)
120132 #define TRDC_MRC_DOM4_RGD_W_MRACSEL_SHIFT        (0U)
120133 /*! MRACSEL - Memory Region Access Control Select
120134  *  0b000..Select MRC_GLBAC0 access control policy
120135  *  0b001..Select MRC_GLBAC1 access control policy
120136  *  0b010..Select MRC_GLBAC2 access control policy
120137  *  0b011..Select MRC_GLBAC3 access control policy
120138  *  0b100..Select MRC_GLBAC4 access control policy
120139  *  0b101..Select MRC_GLBAC5 access control policy
120140  *  0b110..Select MRC_GLBAC6 access control policy
120141  *  0b111..Select MRC_GLBAC7 access control policy
120142  */
120143 #define TRDC_MRC_DOM4_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM4_RGD_W_MRACSEL_MASK)
120144 
120145 #define TRDC_MRC_DOM4_RGD_W_VLD_MASK             (0x1U)
120146 #define TRDC_MRC_DOM4_RGD_W_VLD_SHIFT            (0U)
120147 /*! VLD - Valid */
120148 #define TRDC_MRC_DOM4_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM4_RGD_W_VLD_MASK)
120149 
120150 #define TRDC_MRC_DOM4_RGD_W_NSE_MASK             (0x10U)
120151 #define TRDC_MRC_DOM4_RGD_W_NSE_SHIFT            (4U)
120152 /*! NSE - NonSecure Enable
120153  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120154  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120155  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120156  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120157  */
120158 #define TRDC_MRC_DOM4_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM4_RGD_W_NSE_MASK)
120159 
120160 #define TRDC_MRC_DOM4_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
120161 #define TRDC_MRC_DOM4_RGD_W_END_ADDR_SHIFT       (14U)
120162 /*! END_ADDR - End Address */
120163 #define TRDC_MRC_DOM4_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM4_RGD_W_END_ADDR_MASK)
120164 
120165 #define TRDC_MRC_DOM4_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
120166 #define TRDC_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT      (14U)
120167 /*! STRT_ADDR - Start Address */
120168 #define TRDC_MRC_DOM4_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM4_RGD_W_STRT_ADDR_MASK)
120169 /*! @} */
120170 
120171 /* The count of TRDC_MRC_DOM4_RGD_W */
120172 #define TRDC_MRC_DOM4_RGD_W_COUNT                (7U)
120173 
120174 /* The count of TRDC_MRC_DOM4_RGD_W */
120175 #define TRDC_MRC_DOM4_RGD_W_COUNT2               (16U)
120176 
120177 /* The count of TRDC_MRC_DOM4_RGD_W */
120178 #define TRDC_MRC_DOM4_RGD_W_COUNT3               (2U)
120179 
120180 /*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */
120181 /*! @{ */
120182 
120183 #define TRDC_MRC_DOM4_RGD_NSE_BIT0_MASK          (0x1U)
120184 #define TRDC_MRC_DOM4_RGD_NSE_BIT0_SHIFT         (0U)
120185 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
120186  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120187  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120188  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120189  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120190  */
120191 #define TRDC_MRC_DOM4_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT0_MASK)
120192 
120193 #define TRDC_MRC_DOM4_RGD_NSE_BIT1_MASK          (0x2U)
120194 #define TRDC_MRC_DOM4_RGD_NSE_BIT1_SHIFT         (1U)
120195 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
120196  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120197  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120198  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120199  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120200  */
120201 #define TRDC_MRC_DOM4_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT1_MASK)
120202 
120203 #define TRDC_MRC_DOM4_RGD_NSE_BIT2_MASK          (0x4U)
120204 #define TRDC_MRC_DOM4_RGD_NSE_BIT2_SHIFT         (2U)
120205 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
120206  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120207  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120208  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120209  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120210  */
120211 #define TRDC_MRC_DOM4_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT2_MASK)
120212 
120213 #define TRDC_MRC_DOM4_RGD_NSE_BIT3_MASK          (0x8U)
120214 #define TRDC_MRC_DOM4_RGD_NSE_BIT3_SHIFT         (3U)
120215 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
120216  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120217  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120218  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120219  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120220  */
120221 #define TRDC_MRC_DOM4_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT3_MASK)
120222 
120223 #define TRDC_MRC_DOM4_RGD_NSE_BIT4_MASK          (0x10U)
120224 #define TRDC_MRC_DOM4_RGD_NSE_BIT4_SHIFT         (4U)
120225 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
120226  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120227  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120228  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120229  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120230  */
120231 #define TRDC_MRC_DOM4_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT4_MASK)
120232 
120233 #define TRDC_MRC_DOM4_RGD_NSE_BIT5_MASK          (0x20U)
120234 #define TRDC_MRC_DOM4_RGD_NSE_BIT5_SHIFT         (5U)
120235 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
120236  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120237  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120238  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120239  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120240  */
120241 #define TRDC_MRC_DOM4_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT5_MASK)
120242 
120243 #define TRDC_MRC_DOM4_RGD_NSE_BIT6_MASK          (0x40U)
120244 #define TRDC_MRC_DOM4_RGD_NSE_BIT6_SHIFT         (6U)
120245 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
120246  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120247  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120248  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120249  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120250  */
120251 #define TRDC_MRC_DOM4_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT6_MASK)
120252 
120253 #define TRDC_MRC_DOM4_RGD_NSE_BIT7_MASK          (0x80U)
120254 #define TRDC_MRC_DOM4_RGD_NSE_BIT7_SHIFT         (7U)
120255 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
120256  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120257  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120258  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120259  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120260  */
120261 #define TRDC_MRC_DOM4_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT7_MASK)
120262 
120263 #define TRDC_MRC_DOM4_RGD_NSE_BIT8_MASK          (0x100U)
120264 #define TRDC_MRC_DOM4_RGD_NSE_BIT8_SHIFT         (8U)
120265 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
120266  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120267  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120268  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120269  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120270  */
120271 #define TRDC_MRC_DOM4_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT8_MASK)
120272 
120273 #define TRDC_MRC_DOM4_RGD_NSE_BIT9_MASK          (0x200U)
120274 #define TRDC_MRC_DOM4_RGD_NSE_BIT9_SHIFT         (9U)
120275 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
120276  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120277  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120278  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120279  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120280  */
120281 #define TRDC_MRC_DOM4_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT9_MASK)
120282 
120283 #define TRDC_MRC_DOM4_RGD_NSE_BIT10_MASK         (0x400U)
120284 #define TRDC_MRC_DOM4_RGD_NSE_BIT10_SHIFT        (10U)
120285 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
120286  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120287  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120288  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120289  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120290  */
120291 #define TRDC_MRC_DOM4_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT10_MASK)
120292 
120293 #define TRDC_MRC_DOM4_RGD_NSE_BIT11_MASK         (0x800U)
120294 #define TRDC_MRC_DOM4_RGD_NSE_BIT11_SHIFT        (11U)
120295 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
120296  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120297  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120298  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120299  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120300  */
120301 #define TRDC_MRC_DOM4_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT11_MASK)
120302 
120303 #define TRDC_MRC_DOM4_RGD_NSE_BIT12_MASK         (0x1000U)
120304 #define TRDC_MRC_DOM4_RGD_NSE_BIT12_SHIFT        (12U)
120305 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
120306  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120307  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120308  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120309  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120310  */
120311 #define TRDC_MRC_DOM4_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT12_MASK)
120312 
120313 #define TRDC_MRC_DOM4_RGD_NSE_BIT13_MASK         (0x2000U)
120314 #define TRDC_MRC_DOM4_RGD_NSE_BIT13_SHIFT        (13U)
120315 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
120316  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120317  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120318  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120319  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120320  */
120321 #define TRDC_MRC_DOM4_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT13_MASK)
120322 
120323 #define TRDC_MRC_DOM4_RGD_NSE_BIT14_MASK         (0x4000U)
120324 #define TRDC_MRC_DOM4_RGD_NSE_BIT14_SHIFT        (14U)
120325 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
120326  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120327  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120328  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120329  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120330  */
120331 #define TRDC_MRC_DOM4_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT14_MASK)
120332 
120333 #define TRDC_MRC_DOM4_RGD_NSE_BIT15_MASK         (0x8000U)
120334 #define TRDC_MRC_DOM4_RGD_NSE_BIT15_SHIFT        (15U)
120335 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
120336  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120337  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120338  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120339  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120340  */
120341 #define TRDC_MRC_DOM4_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM4_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM4_RGD_NSE_BIT15_MASK)
120342 /*! @} */
120343 
120344 /* The count of TRDC_MRC_DOM4_RGD_NSE */
120345 #define TRDC_MRC_DOM4_RGD_NSE_COUNT              (7U)
120346 
120347 /*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
120348 /*! @{ */
120349 
120350 #define TRDC_MRC_DOM5_RGD_W_MRACSEL_MASK         (0x7U)
120351 #define TRDC_MRC_DOM5_RGD_W_MRACSEL_SHIFT        (0U)
120352 /*! MRACSEL - Memory Region Access Control Select
120353  *  0b000..Select MRC_GLBAC0 access control policy
120354  *  0b001..Select MRC_GLBAC1 access control policy
120355  *  0b010..Select MRC_GLBAC2 access control policy
120356  *  0b011..Select MRC_GLBAC3 access control policy
120357  *  0b100..Select MRC_GLBAC4 access control policy
120358  *  0b101..Select MRC_GLBAC5 access control policy
120359  *  0b110..Select MRC_GLBAC6 access control policy
120360  *  0b111..Select MRC_GLBAC7 access control policy
120361  */
120362 #define TRDC_MRC_DOM5_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM5_RGD_W_MRACSEL_MASK)
120363 
120364 #define TRDC_MRC_DOM5_RGD_W_VLD_MASK             (0x1U)
120365 #define TRDC_MRC_DOM5_RGD_W_VLD_SHIFT            (0U)
120366 /*! VLD - Valid */
120367 #define TRDC_MRC_DOM5_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM5_RGD_W_VLD_MASK)
120368 
120369 #define TRDC_MRC_DOM5_RGD_W_NSE_MASK             (0x10U)
120370 #define TRDC_MRC_DOM5_RGD_W_NSE_SHIFT            (4U)
120371 /*! NSE - NonSecure Enable
120372  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120373  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120374  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120375  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120376  */
120377 #define TRDC_MRC_DOM5_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM5_RGD_W_NSE_MASK)
120378 
120379 #define TRDC_MRC_DOM5_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
120380 #define TRDC_MRC_DOM5_RGD_W_END_ADDR_SHIFT       (14U)
120381 /*! END_ADDR - End Address */
120382 #define TRDC_MRC_DOM5_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM5_RGD_W_END_ADDR_MASK)
120383 
120384 #define TRDC_MRC_DOM5_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
120385 #define TRDC_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT      (14U)
120386 /*! STRT_ADDR - Start Address */
120387 #define TRDC_MRC_DOM5_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM5_RGD_W_STRT_ADDR_MASK)
120388 /*! @} */
120389 
120390 /* The count of TRDC_MRC_DOM5_RGD_W */
120391 #define TRDC_MRC_DOM5_RGD_W_COUNT                (7U)
120392 
120393 /* The count of TRDC_MRC_DOM5_RGD_W */
120394 #define TRDC_MRC_DOM5_RGD_W_COUNT2               (16U)
120395 
120396 /* The count of TRDC_MRC_DOM5_RGD_W */
120397 #define TRDC_MRC_DOM5_RGD_W_COUNT3               (2U)
120398 
120399 /*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */
120400 /*! @{ */
120401 
120402 #define TRDC_MRC_DOM5_RGD_NSE_BIT0_MASK          (0x1U)
120403 #define TRDC_MRC_DOM5_RGD_NSE_BIT0_SHIFT         (0U)
120404 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
120405  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120406  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120407  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120408  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120409  */
120410 #define TRDC_MRC_DOM5_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT0_MASK)
120411 
120412 #define TRDC_MRC_DOM5_RGD_NSE_BIT1_MASK          (0x2U)
120413 #define TRDC_MRC_DOM5_RGD_NSE_BIT1_SHIFT         (1U)
120414 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
120415  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120416  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120417  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120418  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120419  */
120420 #define TRDC_MRC_DOM5_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT1_MASK)
120421 
120422 #define TRDC_MRC_DOM5_RGD_NSE_BIT2_MASK          (0x4U)
120423 #define TRDC_MRC_DOM5_RGD_NSE_BIT2_SHIFT         (2U)
120424 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
120425  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120426  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120427  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120428  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120429  */
120430 #define TRDC_MRC_DOM5_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT2_MASK)
120431 
120432 #define TRDC_MRC_DOM5_RGD_NSE_BIT3_MASK          (0x8U)
120433 #define TRDC_MRC_DOM5_RGD_NSE_BIT3_SHIFT         (3U)
120434 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
120435  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120436  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120437  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120438  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120439  */
120440 #define TRDC_MRC_DOM5_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT3_MASK)
120441 
120442 #define TRDC_MRC_DOM5_RGD_NSE_BIT4_MASK          (0x10U)
120443 #define TRDC_MRC_DOM5_RGD_NSE_BIT4_SHIFT         (4U)
120444 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
120445  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120446  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120447  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120448  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120449  */
120450 #define TRDC_MRC_DOM5_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT4_MASK)
120451 
120452 #define TRDC_MRC_DOM5_RGD_NSE_BIT5_MASK          (0x20U)
120453 #define TRDC_MRC_DOM5_RGD_NSE_BIT5_SHIFT         (5U)
120454 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
120455  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120456  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120457  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120458  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120459  */
120460 #define TRDC_MRC_DOM5_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT5_MASK)
120461 
120462 #define TRDC_MRC_DOM5_RGD_NSE_BIT6_MASK          (0x40U)
120463 #define TRDC_MRC_DOM5_RGD_NSE_BIT6_SHIFT         (6U)
120464 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
120465  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120466  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120467  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120468  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120469  */
120470 #define TRDC_MRC_DOM5_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT6_MASK)
120471 
120472 #define TRDC_MRC_DOM5_RGD_NSE_BIT7_MASK          (0x80U)
120473 #define TRDC_MRC_DOM5_RGD_NSE_BIT7_SHIFT         (7U)
120474 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
120475  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120476  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120477  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120478  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120479  */
120480 #define TRDC_MRC_DOM5_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT7_MASK)
120481 
120482 #define TRDC_MRC_DOM5_RGD_NSE_BIT8_MASK          (0x100U)
120483 #define TRDC_MRC_DOM5_RGD_NSE_BIT8_SHIFT         (8U)
120484 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
120485  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120486  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120487  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120488  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120489  */
120490 #define TRDC_MRC_DOM5_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT8_MASK)
120491 
120492 #define TRDC_MRC_DOM5_RGD_NSE_BIT9_MASK          (0x200U)
120493 #define TRDC_MRC_DOM5_RGD_NSE_BIT9_SHIFT         (9U)
120494 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
120495  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120496  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120497  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120498  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120499  */
120500 #define TRDC_MRC_DOM5_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT9_MASK)
120501 
120502 #define TRDC_MRC_DOM5_RGD_NSE_BIT10_MASK         (0x400U)
120503 #define TRDC_MRC_DOM5_RGD_NSE_BIT10_SHIFT        (10U)
120504 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
120505  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120506  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120507  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120508  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120509  */
120510 #define TRDC_MRC_DOM5_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT10_MASK)
120511 
120512 #define TRDC_MRC_DOM5_RGD_NSE_BIT11_MASK         (0x800U)
120513 #define TRDC_MRC_DOM5_RGD_NSE_BIT11_SHIFT        (11U)
120514 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
120515  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120516  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120517  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120518  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120519  */
120520 #define TRDC_MRC_DOM5_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT11_MASK)
120521 
120522 #define TRDC_MRC_DOM5_RGD_NSE_BIT12_MASK         (0x1000U)
120523 #define TRDC_MRC_DOM5_RGD_NSE_BIT12_SHIFT        (12U)
120524 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
120525  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120526  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120527  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120528  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120529  */
120530 #define TRDC_MRC_DOM5_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT12_MASK)
120531 
120532 #define TRDC_MRC_DOM5_RGD_NSE_BIT13_MASK         (0x2000U)
120533 #define TRDC_MRC_DOM5_RGD_NSE_BIT13_SHIFT        (13U)
120534 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
120535  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120536  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120537  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120538  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120539  */
120540 #define TRDC_MRC_DOM5_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT13_MASK)
120541 
120542 #define TRDC_MRC_DOM5_RGD_NSE_BIT14_MASK         (0x4000U)
120543 #define TRDC_MRC_DOM5_RGD_NSE_BIT14_SHIFT        (14U)
120544 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
120545  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120546  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120547  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120548  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120549  */
120550 #define TRDC_MRC_DOM5_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT14_MASK)
120551 
120552 #define TRDC_MRC_DOM5_RGD_NSE_BIT15_MASK         (0x8000U)
120553 #define TRDC_MRC_DOM5_RGD_NSE_BIT15_SHIFT        (15U)
120554 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
120555  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120556  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120557  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120558  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120559  */
120560 #define TRDC_MRC_DOM5_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM5_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM5_RGD_NSE_BIT15_MASK)
120561 /*! @} */
120562 
120563 /* The count of TRDC_MRC_DOM5_RGD_NSE */
120564 #define TRDC_MRC_DOM5_RGD_NSE_COUNT              (7U)
120565 
120566 /*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
120567 /*! @{ */
120568 
120569 #define TRDC_MRC_DOM6_RGD_W_MRACSEL_MASK         (0x7U)
120570 #define TRDC_MRC_DOM6_RGD_W_MRACSEL_SHIFT        (0U)
120571 /*! MRACSEL - Memory Region Access Control Select
120572  *  0b000..Select MRC_GLBAC0 access control policy
120573  *  0b001..Select MRC_GLBAC1 access control policy
120574  *  0b010..Select MRC_GLBAC2 access control policy
120575  *  0b011..Select MRC_GLBAC3 access control policy
120576  *  0b100..Select MRC_GLBAC4 access control policy
120577  *  0b101..Select MRC_GLBAC5 access control policy
120578  *  0b110..Select MRC_GLBAC6 access control policy
120579  *  0b111..Select MRC_GLBAC7 access control policy
120580  */
120581 #define TRDC_MRC_DOM6_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM6_RGD_W_MRACSEL_MASK)
120582 
120583 #define TRDC_MRC_DOM6_RGD_W_VLD_MASK             (0x1U)
120584 #define TRDC_MRC_DOM6_RGD_W_VLD_SHIFT            (0U)
120585 /*! VLD - Valid */
120586 #define TRDC_MRC_DOM6_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM6_RGD_W_VLD_MASK)
120587 
120588 #define TRDC_MRC_DOM6_RGD_W_NSE_MASK             (0x10U)
120589 #define TRDC_MRC_DOM6_RGD_W_NSE_SHIFT            (4U)
120590 /*! NSE - NonSecure Enable
120591  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120592  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120593  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120594  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120595  */
120596 #define TRDC_MRC_DOM6_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM6_RGD_W_NSE_MASK)
120597 
120598 #define TRDC_MRC_DOM6_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
120599 #define TRDC_MRC_DOM6_RGD_W_END_ADDR_SHIFT       (14U)
120600 /*! END_ADDR - End Address */
120601 #define TRDC_MRC_DOM6_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM6_RGD_W_END_ADDR_MASK)
120602 
120603 #define TRDC_MRC_DOM6_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
120604 #define TRDC_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT      (14U)
120605 /*! STRT_ADDR - Start Address */
120606 #define TRDC_MRC_DOM6_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM6_RGD_W_STRT_ADDR_MASK)
120607 /*! @} */
120608 
120609 /* The count of TRDC_MRC_DOM6_RGD_W */
120610 #define TRDC_MRC_DOM6_RGD_W_COUNT                (7U)
120611 
120612 /* The count of TRDC_MRC_DOM6_RGD_W */
120613 #define TRDC_MRC_DOM6_RGD_W_COUNT2               (16U)
120614 
120615 /* The count of TRDC_MRC_DOM6_RGD_W */
120616 #define TRDC_MRC_DOM6_RGD_W_COUNT3               (2U)
120617 
120618 /*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */
120619 /*! @{ */
120620 
120621 #define TRDC_MRC_DOM6_RGD_NSE_BIT0_MASK          (0x1U)
120622 #define TRDC_MRC_DOM6_RGD_NSE_BIT0_SHIFT         (0U)
120623 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
120624  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120625  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120626  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120627  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120628  */
120629 #define TRDC_MRC_DOM6_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT0_MASK)
120630 
120631 #define TRDC_MRC_DOM6_RGD_NSE_BIT1_MASK          (0x2U)
120632 #define TRDC_MRC_DOM6_RGD_NSE_BIT1_SHIFT         (1U)
120633 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
120634  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120635  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120636  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120637  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120638  */
120639 #define TRDC_MRC_DOM6_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT1_MASK)
120640 
120641 #define TRDC_MRC_DOM6_RGD_NSE_BIT2_MASK          (0x4U)
120642 #define TRDC_MRC_DOM6_RGD_NSE_BIT2_SHIFT         (2U)
120643 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
120644  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120645  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120646  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120647  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120648  */
120649 #define TRDC_MRC_DOM6_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT2_MASK)
120650 
120651 #define TRDC_MRC_DOM6_RGD_NSE_BIT3_MASK          (0x8U)
120652 #define TRDC_MRC_DOM6_RGD_NSE_BIT3_SHIFT         (3U)
120653 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
120654  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120655  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120656  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120657  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120658  */
120659 #define TRDC_MRC_DOM6_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT3_MASK)
120660 
120661 #define TRDC_MRC_DOM6_RGD_NSE_BIT4_MASK          (0x10U)
120662 #define TRDC_MRC_DOM6_RGD_NSE_BIT4_SHIFT         (4U)
120663 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
120664  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120665  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120666  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120667  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120668  */
120669 #define TRDC_MRC_DOM6_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT4_MASK)
120670 
120671 #define TRDC_MRC_DOM6_RGD_NSE_BIT5_MASK          (0x20U)
120672 #define TRDC_MRC_DOM6_RGD_NSE_BIT5_SHIFT         (5U)
120673 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
120674  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120675  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120676  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120677  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120678  */
120679 #define TRDC_MRC_DOM6_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT5_MASK)
120680 
120681 #define TRDC_MRC_DOM6_RGD_NSE_BIT6_MASK          (0x40U)
120682 #define TRDC_MRC_DOM6_RGD_NSE_BIT6_SHIFT         (6U)
120683 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
120684  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120685  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120686  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120687  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120688  */
120689 #define TRDC_MRC_DOM6_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT6_MASK)
120690 
120691 #define TRDC_MRC_DOM6_RGD_NSE_BIT7_MASK          (0x80U)
120692 #define TRDC_MRC_DOM6_RGD_NSE_BIT7_SHIFT         (7U)
120693 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
120694  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120695  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120696  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120697  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120698  */
120699 #define TRDC_MRC_DOM6_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT7_MASK)
120700 
120701 #define TRDC_MRC_DOM6_RGD_NSE_BIT8_MASK          (0x100U)
120702 #define TRDC_MRC_DOM6_RGD_NSE_BIT8_SHIFT         (8U)
120703 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
120704  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120705  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120706  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120707  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120708  */
120709 #define TRDC_MRC_DOM6_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT8_MASK)
120710 
120711 #define TRDC_MRC_DOM6_RGD_NSE_BIT9_MASK          (0x200U)
120712 #define TRDC_MRC_DOM6_RGD_NSE_BIT9_SHIFT         (9U)
120713 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
120714  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120715  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120716  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120717  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120718  */
120719 #define TRDC_MRC_DOM6_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT9_MASK)
120720 
120721 #define TRDC_MRC_DOM6_RGD_NSE_BIT10_MASK         (0x400U)
120722 #define TRDC_MRC_DOM6_RGD_NSE_BIT10_SHIFT        (10U)
120723 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
120724  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120725  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120726  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120727  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120728  */
120729 #define TRDC_MRC_DOM6_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT10_MASK)
120730 
120731 #define TRDC_MRC_DOM6_RGD_NSE_BIT11_MASK         (0x800U)
120732 #define TRDC_MRC_DOM6_RGD_NSE_BIT11_SHIFT        (11U)
120733 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
120734  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120735  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120736  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120737  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120738  */
120739 #define TRDC_MRC_DOM6_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT11_MASK)
120740 
120741 #define TRDC_MRC_DOM6_RGD_NSE_BIT12_MASK         (0x1000U)
120742 #define TRDC_MRC_DOM6_RGD_NSE_BIT12_SHIFT        (12U)
120743 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
120744  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120745  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120746  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120747  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120748  */
120749 #define TRDC_MRC_DOM6_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT12_MASK)
120750 
120751 #define TRDC_MRC_DOM6_RGD_NSE_BIT13_MASK         (0x2000U)
120752 #define TRDC_MRC_DOM6_RGD_NSE_BIT13_SHIFT        (13U)
120753 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
120754  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120755  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120756  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120757  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120758  */
120759 #define TRDC_MRC_DOM6_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT13_MASK)
120760 
120761 #define TRDC_MRC_DOM6_RGD_NSE_BIT14_MASK         (0x4000U)
120762 #define TRDC_MRC_DOM6_RGD_NSE_BIT14_SHIFT        (14U)
120763 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
120764  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120765  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120766  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120767  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120768  */
120769 #define TRDC_MRC_DOM6_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT14_MASK)
120770 
120771 #define TRDC_MRC_DOM6_RGD_NSE_BIT15_MASK         (0x8000U)
120772 #define TRDC_MRC_DOM6_RGD_NSE_BIT15_SHIFT        (15U)
120773 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
120774  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120775  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120776  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120777  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120778  */
120779 #define TRDC_MRC_DOM6_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM6_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM6_RGD_NSE_BIT15_MASK)
120780 /*! @} */
120781 
120782 /* The count of TRDC_MRC_DOM6_RGD_NSE */
120783 #define TRDC_MRC_DOM6_RGD_NSE_COUNT              (7U)
120784 
120785 /*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
120786 /*! @{ */
120787 
120788 #define TRDC_MRC_DOM7_RGD_W_MRACSEL_MASK         (0x7U)
120789 #define TRDC_MRC_DOM7_RGD_W_MRACSEL_SHIFT        (0U)
120790 /*! MRACSEL - Memory Region Access Control Select
120791  *  0b000..Select MRC_GLBAC0 access control policy
120792  *  0b001..Select MRC_GLBAC1 access control policy
120793  *  0b010..Select MRC_GLBAC2 access control policy
120794  *  0b011..Select MRC_GLBAC3 access control policy
120795  *  0b100..Select MRC_GLBAC4 access control policy
120796  *  0b101..Select MRC_GLBAC5 access control policy
120797  *  0b110..Select MRC_GLBAC6 access control policy
120798  *  0b111..Select MRC_GLBAC7 access control policy
120799  */
120800 #define TRDC_MRC_DOM7_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM7_RGD_W_MRACSEL_MASK)
120801 
120802 #define TRDC_MRC_DOM7_RGD_W_VLD_MASK             (0x1U)
120803 #define TRDC_MRC_DOM7_RGD_W_VLD_SHIFT            (0U)
120804 /*! VLD - Valid */
120805 #define TRDC_MRC_DOM7_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM7_RGD_W_VLD_MASK)
120806 
120807 #define TRDC_MRC_DOM7_RGD_W_NSE_MASK             (0x10U)
120808 #define TRDC_MRC_DOM7_RGD_W_NSE_SHIFT            (4U)
120809 /*! NSE - NonSecure Enable
120810  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120811  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120812  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120813  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120814  */
120815 #define TRDC_MRC_DOM7_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM7_RGD_W_NSE_MASK)
120816 
120817 #define TRDC_MRC_DOM7_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
120818 #define TRDC_MRC_DOM7_RGD_W_END_ADDR_SHIFT       (14U)
120819 /*! END_ADDR - End Address */
120820 #define TRDC_MRC_DOM7_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM7_RGD_W_END_ADDR_MASK)
120821 
120822 #define TRDC_MRC_DOM7_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
120823 #define TRDC_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT      (14U)
120824 /*! STRT_ADDR - Start Address */
120825 #define TRDC_MRC_DOM7_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM7_RGD_W_STRT_ADDR_MASK)
120826 /*! @} */
120827 
120828 /* The count of TRDC_MRC_DOM7_RGD_W */
120829 #define TRDC_MRC_DOM7_RGD_W_COUNT                (7U)
120830 
120831 /* The count of TRDC_MRC_DOM7_RGD_W */
120832 #define TRDC_MRC_DOM7_RGD_W_COUNT2               (16U)
120833 
120834 /* The count of TRDC_MRC_DOM7_RGD_W */
120835 #define TRDC_MRC_DOM7_RGD_W_COUNT3               (2U)
120836 
120837 /*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */
120838 /*! @{ */
120839 
120840 #define TRDC_MRC_DOM7_RGD_NSE_BIT0_MASK          (0x1U)
120841 #define TRDC_MRC_DOM7_RGD_NSE_BIT0_SHIFT         (0U)
120842 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
120843  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120844  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120845  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120846  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120847  */
120848 #define TRDC_MRC_DOM7_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT0_MASK)
120849 
120850 #define TRDC_MRC_DOM7_RGD_NSE_BIT1_MASK          (0x2U)
120851 #define TRDC_MRC_DOM7_RGD_NSE_BIT1_SHIFT         (1U)
120852 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
120853  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120854  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120855  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120856  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120857  */
120858 #define TRDC_MRC_DOM7_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT1_MASK)
120859 
120860 #define TRDC_MRC_DOM7_RGD_NSE_BIT2_MASK          (0x4U)
120861 #define TRDC_MRC_DOM7_RGD_NSE_BIT2_SHIFT         (2U)
120862 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
120863  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120864  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120865  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120866  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120867  */
120868 #define TRDC_MRC_DOM7_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT2_MASK)
120869 
120870 #define TRDC_MRC_DOM7_RGD_NSE_BIT3_MASK          (0x8U)
120871 #define TRDC_MRC_DOM7_RGD_NSE_BIT3_SHIFT         (3U)
120872 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
120873  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120874  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120875  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120876  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120877  */
120878 #define TRDC_MRC_DOM7_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT3_MASK)
120879 
120880 #define TRDC_MRC_DOM7_RGD_NSE_BIT4_MASK          (0x10U)
120881 #define TRDC_MRC_DOM7_RGD_NSE_BIT4_SHIFT         (4U)
120882 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
120883  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120884  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120885  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120886  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120887  */
120888 #define TRDC_MRC_DOM7_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT4_MASK)
120889 
120890 #define TRDC_MRC_DOM7_RGD_NSE_BIT5_MASK          (0x20U)
120891 #define TRDC_MRC_DOM7_RGD_NSE_BIT5_SHIFT         (5U)
120892 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
120893  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120894  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120895  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120896  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120897  */
120898 #define TRDC_MRC_DOM7_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT5_MASK)
120899 
120900 #define TRDC_MRC_DOM7_RGD_NSE_BIT6_MASK          (0x40U)
120901 #define TRDC_MRC_DOM7_RGD_NSE_BIT6_SHIFT         (6U)
120902 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
120903  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120904  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120905  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120906  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120907  */
120908 #define TRDC_MRC_DOM7_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT6_MASK)
120909 
120910 #define TRDC_MRC_DOM7_RGD_NSE_BIT7_MASK          (0x80U)
120911 #define TRDC_MRC_DOM7_RGD_NSE_BIT7_SHIFT         (7U)
120912 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
120913  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120914  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120915  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120916  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120917  */
120918 #define TRDC_MRC_DOM7_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT7_MASK)
120919 
120920 #define TRDC_MRC_DOM7_RGD_NSE_BIT8_MASK          (0x100U)
120921 #define TRDC_MRC_DOM7_RGD_NSE_BIT8_SHIFT         (8U)
120922 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
120923  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120924  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120925  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120926  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120927  */
120928 #define TRDC_MRC_DOM7_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT8_MASK)
120929 
120930 #define TRDC_MRC_DOM7_RGD_NSE_BIT9_MASK          (0x200U)
120931 #define TRDC_MRC_DOM7_RGD_NSE_BIT9_SHIFT         (9U)
120932 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
120933  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120934  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120935  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120936  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120937  */
120938 #define TRDC_MRC_DOM7_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT9_MASK)
120939 
120940 #define TRDC_MRC_DOM7_RGD_NSE_BIT10_MASK         (0x400U)
120941 #define TRDC_MRC_DOM7_RGD_NSE_BIT10_SHIFT        (10U)
120942 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
120943  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120944  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120945  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120946  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120947  */
120948 #define TRDC_MRC_DOM7_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT10_MASK)
120949 
120950 #define TRDC_MRC_DOM7_RGD_NSE_BIT11_MASK         (0x800U)
120951 #define TRDC_MRC_DOM7_RGD_NSE_BIT11_SHIFT        (11U)
120952 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
120953  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120954  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120955  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120956  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120957  */
120958 #define TRDC_MRC_DOM7_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT11_MASK)
120959 
120960 #define TRDC_MRC_DOM7_RGD_NSE_BIT12_MASK         (0x1000U)
120961 #define TRDC_MRC_DOM7_RGD_NSE_BIT12_SHIFT        (12U)
120962 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
120963  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120964  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120965  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120966  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120967  */
120968 #define TRDC_MRC_DOM7_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT12_MASK)
120969 
120970 #define TRDC_MRC_DOM7_RGD_NSE_BIT13_MASK         (0x2000U)
120971 #define TRDC_MRC_DOM7_RGD_NSE_BIT13_SHIFT        (13U)
120972 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
120973  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120974  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120975  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120976  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120977  */
120978 #define TRDC_MRC_DOM7_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT13_MASK)
120979 
120980 #define TRDC_MRC_DOM7_RGD_NSE_BIT14_MASK         (0x4000U)
120981 #define TRDC_MRC_DOM7_RGD_NSE_BIT14_SHIFT        (14U)
120982 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
120983  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120984  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120985  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120986  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120987  */
120988 #define TRDC_MRC_DOM7_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT14_MASK)
120989 
120990 #define TRDC_MRC_DOM7_RGD_NSE_BIT15_MASK         (0x8000U)
120991 #define TRDC_MRC_DOM7_RGD_NSE_BIT15_SHIFT        (15U)
120992 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
120993  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
120994  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
120995  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
120996  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
120997  */
120998 #define TRDC_MRC_DOM7_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM7_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM7_RGD_NSE_BIT15_MASK)
120999 /*! @} */
121000 
121001 /* The count of TRDC_MRC_DOM7_RGD_NSE */
121002 #define TRDC_MRC_DOM7_RGD_NSE_COUNT              (7U)
121003 
121004 /*! @name MRC_DOM8_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
121005 /*! @{ */
121006 
121007 #define TRDC_MRC_DOM8_RGD_W_MRACSEL_MASK         (0x7U)
121008 #define TRDC_MRC_DOM8_RGD_W_MRACSEL_SHIFT        (0U)
121009 /*! MRACSEL - Memory Region Access Control Select
121010  *  0b000..Select MRC_GLBAC0 access control policy
121011  *  0b001..Select MRC_GLBAC1 access control policy
121012  *  0b010..Select MRC_GLBAC2 access control policy
121013  *  0b011..Select MRC_GLBAC3 access control policy
121014  *  0b100..Select MRC_GLBAC4 access control policy
121015  *  0b101..Select MRC_GLBAC5 access control policy
121016  *  0b110..Select MRC_GLBAC6 access control policy
121017  *  0b111..Select MRC_GLBAC7 access control policy
121018  */
121019 #define TRDC_MRC_DOM8_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM8_RGD_W_MRACSEL_MASK)
121020 
121021 #define TRDC_MRC_DOM8_RGD_W_VLD_MASK             (0x1U)
121022 #define TRDC_MRC_DOM8_RGD_W_VLD_SHIFT            (0U)
121023 /*! VLD - Valid */
121024 #define TRDC_MRC_DOM8_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM8_RGD_W_VLD_MASK)
121025 
121026 #define TRDC_MRC_DOM8_RGD_W_NSE_MASK             (0x10U)
121027 #define TRDC_MRC_DOM8_RGD_W_NSE_SHIFT            (4U)
121028 /*! NSE - NonSecure Enable
121029  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121030  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121031  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121032  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121033  */
121034 #define TRDC_MRC_DOM8_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM8_RGD_W_NSE_MASK)
121035 
121036 #define TRDC_MRC_DOM8_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
121037 #define TRDC_MRC_DOM8_RGD_W_END_ADDR_SHIFT       (14U)
121038 /*! END_ADDR - End Address */
121039 #define TRDC_MRC_DOM8_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM8_RGD_W_END_ADDR_MASK)
121040 
121041 #define TRDC_MRC_DOM8_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
121042 #define TRDC_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT      (14U)
121043 /*! STRT_ADDR - Start Address */
121044 #define TRDC_MRC_DOM8_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM8_RGD_W_STRT_ADDR_MASK)
121045 /*! @} */
121046 
121047 /* The count of TRDC_MRC_DOM8_RGD_W */
121048 #define TRDC_MRC_DOM8_RGD_W_COUNT                (7U)
121049 
121050 /* The count of TRDC_MRC_DOM8_RGD_W */
121051 #define TRDC_MRC_DOM8_RGD_W_COUNT2               (16U)
121052 
121053 /* The count of TRDC_MRC_DOM8_RGD_W */
121054 #define TRDC_MRC_DOM8_RGD_W_COUNT3               (2U)
121055 
121056 /*! @name MRC_DOM8_RGD_NSE - MRC Region Descriptor NonSecure Enable */
121057 /*! @{ */
121058 
121059 #define TRDC_MRC_DOM8_RGD_NSE_BIT0_MASK          (0x1U)
121060 #define TRDC_MRC_DOM8_RGD_NSE_BIT0_SHIFT         (0U)
121061 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
121062  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121063  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121064  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121065  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121066  */
121067 #define TRDC_MRC_DOM8_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT0_MASK)
121068 
121069 #define TRDC_MRC_DOM8_RGD_NSE_BIT1_MASK          (0x2U)
121070 #define TRDC_MRC_DOM8_RGD_NSE_BIT1_SHIFT         (1U)
121071 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
121072  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121073  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121074  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121075  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121076  */
121077 #define TRDC_MRC_DOM8_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT1_MASK)
121078 
121079 #define TRDC_MRC_DOM8_RGD_NSE_BIT2_MASK          (0x4U)
121080 #define TRDC_MRC_DOM8_RGD_NSE_BIT2_SHIFT         (2U)
121081 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
121082  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121083  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121084  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121085  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121086  */
121087 #define TRDC_MRC_DOM8_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT2_MASK)
121088 
121089 #define TRDC_MRC_DOM8_RGD_NSE_BIT3_MASK          (0x8U)
121090 #define TRDC_MRC_DOM8_RGD_NSE_BIT3_SHIFT         (3U)
121091 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
121092  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121093  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121094  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121095  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121096  */
121097 #define TRDC_MRC_DOM8_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT3_MASK)
121098 
121099 #define TRDC_MRC_DOM8_RGD_NSE_BIT4_MASK          (0x10U)
121100 #define TRDC_MRC_DOM8_RGD_NSE_BIT4_SHIFT         (4U)
121101 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
121102  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121103  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121104  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121105  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121106  */
121107 #define TRDC_MRC_DOM8_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT4_MASK)
121108 
121109 #define TRDC_MRC_DOM8_RGD_NSE_BIT5_MASK          (0x20U)
121110 #define TRDC_MRC_DOM8_RGD_NSE_BIT5_SHIFT         (5U)
121111 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
121112  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121113  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121114  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121115  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121116  */
121117 #define TRDC_MRC_DOM8_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT5_MASK)
121118 
121119 #define TRDC_MRC_DOM8_RGD_NSE_BIT6_MASK          (0x40U)
121120 #define TRDC_MRC_DOM8_RGD_NSE_BIT6_SHIFT         (6U)
121121 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
121122  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121123  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121124  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121125  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121126  */
121127 #define TRDC_MRC_DOM8_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT6_MASK)
121128 
121129 #define TRDC_MRC_DOM8_RGD_NSE_BIT7_MASK          (0x80U)
121130 #define TRDC_MRC_DOM8_RGD_NSE_BIT7_SHIFT         (7U)
121131 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
121132  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121133  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121134  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121135  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121136  */
121137 #define TRDC_MRC_DOM8_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT7_MASK)
121138 
121139 #define TRDC_MRC_DOM8_RGD_NSE_BIT8_MASK          (0x100U)
121140 #define TRDC_MRC_DOM8_RGD_NSE_BIT8_SHIFT         (8U)
121141 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
121142  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121143  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121144  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121145  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121146  */
121147 #define TRDC_MRC_DOM8_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT8_MASK)
121148 
121149 #define TRDC_MRC_DOM8_RGD_NSE_BIT9_MASK          (0x200U)
121150 #define TRDC_MRC_DOM8_RGD_NSE_BIT9_SHIFT         (9U)
121151 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
121152  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121153  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121154  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121155  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121156  */
121157 #define TRDC_MRC_DOM8_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT9_MASK)
121158 
121159 #define TRDC_MRC_DOM8_RGD_NSE_BIT10_MASK         (0x400U)
121160 #define TRDC_MRC_DOM8_RGD_NSE_BIT10_SHIFT        (10U)
121161 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
121162  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121163  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121164  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121165  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121166  */
121167 #define TRDC_MRC_DOM8_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT10_MASK)
121168 
121169 #define TRDC_MRC_DOM8_RGD_NSE_BIT11_MASK         (0x800U)
121170 #define TRDC_MRC_DOM8_RGD_NSE_BIT11_SHIFT        (11U)
121171 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
121172  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121173  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121174  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121175  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121176  */
121177 #define TRDC_MRC_DOM8_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT11_MASK)
121178 
121179 #define TRDC_MRC_DOM8_RGD_NSE_BIT12_MASK         (0x1000U)
121180 #define TRDC_MRC_DOM8_RGD_NSE_BIT12_SHIFT        (12U)
121181 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
121182  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121183  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121184  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121185  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121186  */
121187 #define TRDC_MRC_DOM8_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT12_MASK)
121188 
121189 #define TRDC_MRC_DOM8_RGD_NSE_BIT13_MASK         (0x2000U)
121190 #define TRDC_MRC_DOM8_RGD_NSE_BIT13_SHIFT        (13U)
121191 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
121192  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121193  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121194  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121195  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121196  */
121197 #define TRDC_MRC_DOM8_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT13_MASK)
121198 
121199 #define TRDC_MRC_DOM8_RGD_NSE_BIT14_MASK         (0x4000U)
121200 #define TRDC_MRC_DOM8_RGD_NSE_BIT14_SHIFT        (14U)
121201 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
121202  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121203  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121204  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121205  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121206  */
121207 #define TRDC_MRC_DOM8_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT14_MASK)
121208 
121209 #define TRDC_MRC_DOM8_RGD_NSE_BIT15_MASK         (0x8000U)
121210 #define TRDC_MRC_DOM8_RGD_NSE_BIT15_SHIFT        (15U)
121211 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
121212  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121213  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121214  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121215  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121216  */
121217 #define TRDC_MRC_DOM8_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM8_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM8_RGD_NSE_BIT15_MASK)
121218 /*! @} */
121219 
121220 /* The count of TRDC_MRC_DOM8_RGD_NSE */
121221 #define TRDC_MRC_DOM8_RGD_NSE_COUNT              (7U)
121222 
121223 /*! @name MRC_DOM9_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
121224 /*! @{ */
121225 
121226 #define TRDC_MRC_DOM9_RGD_W_MRACSEL_MASK         (0x7U)
121227 #define TRDC_MRC_DOM9_RGD_W_MRACSEL_SHIFT        (0U)
121228 /*! MRACSEL - Memory Region Access Control Select
121229  *  0b000..Select MRC_GLBAC0 access control policy
121230  *  0b001..Select MRC_GLBAC1 access control policy
121231  *  0b010..Select MRC_GLBAC2 access control policy
121232  *  0b011..Select MRC_GLBAC3 access control policy
121233  *  0b100..Select MRC_GLBAC4 access control policy
121234  *  0b101..Select MRC_GLBAC5 access control policy
121235  *  0b110..Select MRC_GLBAC6 access control policy
121236  *  0b111..Select MRC_GLBAC7 access control policy
121237  */
121238 #define TRDC_MRC_DOM9_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM9_RGD_W_MRACSEL_MASK)
121239 
121240 #define TRDC_MRC_DOM9_RGD_W_VLD_MASK             (0x1U)
121241 #define TRDC_MRC_DOM9_RGD_W_VLD_SHIFT            (0U)
121242 /*! VLD - Valid */
121243 #define TRDC_MRC_DOM9_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM9_RGD_W_VLD_MASK)
121244 
121245 #define TRDC_MRC_DOM9_RGD_W_NSE_MASK             (0x10U)
121246 #define TRDC_MRC_DOM9_RGD_W_NSE_SHIFT            (4U)
121247 /*! NSE - NonSecure Enable
121248  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121249  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121250  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121251  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121252  */
121253 #define TRDC_MRC_DOM9_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM9_RGD_W_NSE_MASK)
121254 
121255 #define TRDC_MRC_DOM9_RGD_W_END_ADDR_MASK        (0xFFFFC000U)
121256 #define TRDC_MRC_DOM9_RGD_W_END_ADDR_SHIFT       (14U)
121257 /*! END_ADDR - End Address */
121258 #define TRDC_MRC_DOM9_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM9_RGD_W_END_ADDR_MASK)
121259 
121260 #define TRDC_MRC_DOM9_RGD_W_STRT_ADDR_MASK       (0xFFFFC000U)
121261 #define TRDC_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT      (14U)
121262 /*! STRT_ADDR - Start Address */
121263 #define TRDC_MRC_DOM9_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM9_RGD_W_STRT_ADDR_MASK)
121264 /*! @} */
121265 
121266 /* The count of TRDC_MRC_DOM9_RGD_W */
121267 #define TRDC_MRC_DOM9_RGD_W_COUNT                (7U)
121268 
121269 /* The count of TRDC_MRC_DOM9_RGD_W */
121270 #define TRDC_MRC_DOM9_RGD_W_COUNT2               (16U)
121271 
121272 /* The count of TRDC_MRC_DOM9_RGD_W */
121273 #define TRDC_MRC_DOM9_RGD_W_COUNT3               (2U)
121274 
121275 /*! @name MRC_DOM9_RGD_NSE - MRC Region Descriptor NonSecure Enable */
121276 /*! @{ */
121277 
121278 #define TRDC_MRC_DOM9_RGD_NSE_BIT0_MASK          (0x1U)
121279 #define TRDC_MRC_DOM9_RGD_NSE_BIT0_SHIFT         (0U)
121280 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
121281  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121282  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121283  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121284  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121285  */
121286 #define TRDC_MRC_DOM9_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT0_MASK)
121287 
121288 #define TRDC_MRC_DOM9_RGD_NSE_BIT1_MASK          (0x2U)
121289 #define TRDC_MRC_DOM9_RGD_NSE_BIT1_SHIFT         (1U)
121290 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
121291  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121292  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121293  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121294  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121295  */
121296 #define TRDC_MRC_DOM9_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT1_MASK)
121297 
121298 #define TRDC_MRC_DOM9_RGD_NSE_BIT2_MASK          (0x4U)
121299 #define TRDC_MRC_DOM9_RGD_NSE_BIT2_SHIFT         (2U)
121300 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
121301  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121302  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121303  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121304  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121305  */
121306 #define TRDC_MRC_DOM9_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT2_MASK)
121307 
121308 #define TRDC_MRC_DOM9_RGD_NSE_BIT3_MASK          (0x8U)
121309 #define TRDC_MRC_DOM9_RGD_NSE_BIT3_SHIFT         (3U)
121310 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
121311  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121312  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121313  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121314  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121315  */
121316 #define TRDC_MRC_DOM9_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT3_MASK)
121317 
121318 #define TRDC_MRC_DOM9_RGD_NSE_BIT4_MASK          (0x10U)
121319 #define TRDC_MRC_DOM9_RGD_NSE_BIT4_SHIFT         (4U)
121320 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
121321  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121322  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121323  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121324  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121325  */
121326 #define TRDC_MRC_DOM9_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT4_MASK)
121327 
121328 #define TRDC_MRC_DOM9_RGD_NSE_BIT5_MASK          (0x20U)
121329 #define TRDC_MRC_DOM9_RGD_NSE_BIT5_SHIFT         (5U)
121330 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
121331  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121332  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121333  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121334  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121335  */
121336 #define TRDC_MRC_DOM9_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT5_MASK)
121337 
121338 #define TRDC_MRC_DOM9_RGD_NSE_BIT6_MASK          (0x40U)
121339 #define TRDC_MRC_DOM9_RGD_NSE_BIT6_SHIFT         (6U)
121340 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
121341  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121342  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121343  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121344  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121345  */
121346 #define TRDC_MRC_DOM9_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT6_MASK)
121347 
121348 #define TRDC_MRC_DOM9_RGD_NSE_BIT7_MASK          (0x80U)
121349 #define TRDC_MRC_DOM9_RGD_NSE_BIT7_SHIFT         (7U)
121350 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
121351  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121352  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121353  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121354  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121355  */
121356 #define TRDC_MRC_DOM9_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT7_MASK)
121357 
121358 #define TRDC_MRC_DOM9_RGD_NSE_BIT8_MASK          (0x100U)
121359 #define TRDC_MRC_DOM9_RGD_NSE_BIT8_SHIFT         (8U)
121360 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
121361  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121362  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121363  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121364  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121365  */
121366 #define TRDC_MRC_DOM9_RGD_NSE_BIT8(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT8_MASK)
121367 
121368 #define TRDC_MRC_DOM9_RGD_NSE_BIT9_MASK          (0x200U)
121369 #define TRDC_MRC_DOM9_RGD_NSE_BIT9_SHIFT         (9U)
121370 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
121371  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121372  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121373  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121374  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121375  */
121376 #define TRDC_MRC_DOM9_RGD_NSE_BIT9(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT9_MASK)
121377 
121378 #define TRDC_MRC_DOM9_RGD_NSE_BIT10_MASK         (0x400U)
121379 #define TRDC_MRC_DOM9_RGD_NSE_BIT10_SHIFT        (10U)
121380 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
121381  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121382  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121383  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121384  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121385  */
121386 #define TRDC_MRC_DOM9_RGD_NSE_BIT10(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT10_MASK)
121387 
121388 #define TRDC_MRC_DOM9_RGD_NSE_BIT11_MASK         (0x800U)
121389 #define TRDC_MRC_DOM9_RGD_NSE_BIT11_SHIFT        (11U)
121390 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
121391  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121392  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121393  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121394  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121395  */
121396 #define TRDC_MRC_DOM9_RGD_NSE_BIT11(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT11_MASK)
121397 
121398 #define TRDC_MRC_DOM9_RGD_NSE_BIT12_MASK         (0x1000U)
121399 #define TRDC_MRC_DOM9_RGD_NSE_BIT12_SHIFT        (12U)
121400 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
121401  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121402  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121403  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121404  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121405  */
121406 #define TRDC_MRC_DOM9_RGD_NSE_BIT12(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT12_MASK)
121407 
121408 #define TRDC_MRC_DOM9_RGD_NSE_BIT13_MASK         (0x2000U)
121409 #define TRDC_MRC_DOM9_RGD_NSE_BIT13_SHIFT        (13U)
121410 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
121411  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121412  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121413  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121414  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121415  */
121416 #define TRDC_MRC_DOM9_RGD_NSE_BIT13(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT13_MASK)
121417 
121418 #define TRDC_MRC_DOM9_RGD_NSE_BIT14_MASK         (0x4000U)
121419 #define TRDC_MRC_DOM9_RGD_NSE_BIT14_SHIFT        (14U)
121420 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
121421  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121422  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121423  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121424  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121425  */
121426 #define TRDC_MRC_DOM9_RGD_NSE_BIT14(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT14_MASK)
121427 
121428 #define TRDC_MRC_DOM9_RGD_NSE_BIT15_MASK         (0x8000U)
121429 #define TRDC_MRC_DOM9_RGD_NSE_BIT15_SHIFT        (15U)
121430 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
121431  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121432  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121433  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121434  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121435  */
121436 #define TRDC_MRC_DOM9_RGD_NSE_BIT15(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM9_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM9_RGD_NSE_BIT15_MASK)
121437 /*! @} */
121438 
121439 /* The count of TRDC_MRC_DOM9_RGD_NSE */
121440 #define TRDC_MRC_DOM9_RGD_NSE_COUNT              (7U)
121441 
121442 /*! @name MRC_DOM10_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
121443 /*! @{ */
121444 
121445 #define TRDC_MRC_DOM10_RGD_W_MRACSEL_MASK        (0x7U)
121446 #define TRDC_MRC_DOM10_RGD_W_MRACSEL_SHIFT       (0U)
121447 /*! MRACSEL - Memory Region Access Control Select
121448  *  0b000..Select MRC_GLBAC0 access control policy
121449  *  0b001..Select MRC_GLBAC1 access control policy
121450  *  0b010..Select MRC_GLBAC2 access control policy
121451  *  0b011..Select MRC_GLBAC3 access control policy
121452  *  0b100..Select MRC_GLBAC4 access control policy
121453  *  0b101..Select MRC_GLBAC5 access control policy
121454  *  0b110..Select MRC_GLBAC6 access control policy
121455  *  0b111..Select MRC_GLBAC7 access control policy
121456  */
121457 #define TRDC_MRC_DOM10_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM10_RGD_W_MRACSEL_MASK)
121458 
121459 #define TRDC_MRC_DOM10_RGD_W_VLD_MASK            (0x1U)
121460 #define TRDC_MRC_DOM10_RGD_W_VLD_SHIFT           (0U)
121461 /*! VLD - Valid */
121462 #define TRDC_MRC_DOM10_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM10_RGD_W_VLD_MASK)
121463 
121464 #define TRDC_MRC_DOM10_RGD_W_NSE_MASK            (0x10U)
121465 #define TRDC_MRC_DOM10_RGD_W_NSE_SHIFT           (4U)
121466 /*! NSE - NonSecure Enable
121467  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121468  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121469  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121470  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121471  */
121472 #define TRDC_MRC_DOM10_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM10_RGD_W_NSE_MASK)
121473 
121474 #define TRDC_MRC_DOM10_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
121475 #define TRDC_MRC_DOM10_RGD_W_END_ADDR_SHIFT      (14U)
121476 /*! END_ADDR - End Address */
121477 #define TRDC_MRC_DOM10_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM10_RGD_W_END_ADDR_MASK)
121478 
121479 #define TRDC_MRC_DOM10_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
121480 #define TRDC_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT     (14U)
121481 /*! STRT_ADDR - Start Address */
121482 #define TRDC_MRC_DOM10_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM10_RGD_W_STRT_ADDR_MASK)
121483 /*! @} */
121484 
121485 /* The count of TRDC_MRC_DOM10_RGD_W */
121486 #define TRDC_MRC_DOM10_RGD_W_COUNT               (7U)
121487 
121488 /* The count of TRDC_MRC_DOM10_RGD_W */
121489 #define TRDC_MRC_DOM10_RGD_W_COUNT2              (16U)
121490 
121491 /* The count of TRDC_MRC_DOM10_RGD_W */
121492 #define TRDC_MRC_DOM10_RGD_W_COUNT3              (2U)
121493 
121494 /*! @name MRC_DOM10_RGD_NSE - MRC Region Descriptor NonSecure Enable */
121495 /*! @{ */
121496 
121497 #define TRDC_MRC_DOM10_RGD_NSE_BIT0_MASK         (0x1U)
121498 #define TRDC_MRC_DOM10_RGD_NSE_BIT0_SHIFT        (0U)
121499 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
121500  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121501  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121502  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121503  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121504  */
121505 #define TRDC_MRC_DOM10_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT0_MASK)
121506 
121507 #define TRDC_MRC_DOM10_RGD_NSE_BIT1_MASK         (0x2U)
121508 #define TRDC_MRC_DOM10_RGD_NSE_BIT1_SHIFT        (1U)
121509 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
121510  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121511  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121512  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121513  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121514  */
121515 #define TRDC_MRC_DOM10_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT1_MASK)
121516 
121517 #define TRDC_MRC_DOM10_RGD_NSE_BIT2_MASK         (0x4U)
121518 #define TRDC_MRC_DOM10_RGD_NSE_BIT2_SHIFT        (2U)
121519 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
121520  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121521  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121522  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121523  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121524  */
121525 #define TRDC_MRC_DOM10_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT2_MASK)
121526 
121527 #define TRDC_MRC_DOM10_RGD_NSE_BIT3_MASK         (0x8U)
121528 #define TRDC_MRC_DOM10_RGD_NSE_BIT3_SHIFT        (3U)
121529 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
121530  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121531  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121532  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121533  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121534  */
121535 #define TRDC_MRC_DOM10_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT3_MASK)
121536 
121537 #define TRDC_MRC_DOM10_RGD_NSE_BIT4_MASK         (0x10U)
121538 #define TRDC_MRC_DOM10_RGD_NSE_BIT4_SHIFT        (4U)
121539 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
121540  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121541  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121542  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121543  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121544  */
121545 #define TRDC_MRC_DOM10_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT4_MASK)
121546 
121547 #define TRDC_MRC_DOM10_RGD_NSE_BIT5_MASK         (0x20U)
121548 #define TRDC_MRC_DOM10_RGD_NSE_BIT5_SHIFT        (5U)
121549 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
121550  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121551  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121552  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121553  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121554  */
121555 #define TRDC_MRC_DOM10_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT5_MASK)
121556 
121557 #define TRDC_MRC_DOM10_RGD_NSE_BIT6_MASK         (0x40U)
121558 #define TRDC_MRC_DOM10_RGD_NSE_BIT6_SHIFT        (6U)
121559 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
121560  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121561  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121562  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121563  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121564  */
121565 #define TRDC_MRC_DOM10_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT6_MASK)
121566 
121567 #define TRDC_MRC_DOM10_RGD_NSE_BIT7_MASK         (0x80U)
121568 #define TRDC_MRC_DOM10_RGD_NSE_BIT7_SHIFT        (7U)
121569 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
121570  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121571  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121572  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121573  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121574  */
121575 #define TRDC_MRC_DOM10_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT7_MASK)
121576 
121577 #define TRDC_MRC_DOM10_RGD_NSE_BIT8_MASK         (0x100U)
121578 #define TRDC_MRC_DOM10_RGD_NSE_BIT8_SHIFT        (8U)
121579 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
121580  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121581  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121582  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121583  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121584  */
121585 #define TRDC_MRC_DOM10_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT8_MASK)
121586 
121587 #define TRDC_MRC_DOM10_RGD_NSE_BIT9_MASK         (0x200U)
121588 #define TRDC_MRC_DOM10_RGD_NSE_BIT9_SHIFT        (9U)
121589 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
121590  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121591  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121592  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121593  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121594  */
121595 #define TRDC_MRC_DOM10_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT9_MASK)
121596 
121597 #define TRDC_MRC_DOM10_RGD_NSE_BIT10_MASK        (0x400U)
121598 #define TRDC_MRC_DOM10_RGD_NSE_BIT10_SHIFT       (10U)
121599 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
121600  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121601  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121602  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121603  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121604  */
121605 #define TRDC_MRC_DOM10_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT10_MASK)
121606 
121607 #define TRDC_MRC_DOM10_RGD_NSE_BIT11_MASK        (0x800U)
121608 #define TRDC_MRC_DOM10_RGD_NSE_BIT11_SHIFT       (11U)
121609 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
121610  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121611  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121612  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121613  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121614  */
121615 #define TRDC_MRC_DOM10_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT11_MASK)
121616 
121617 #define TRDC_MRC_DOM10_RGD_NSE_BIT12_MASK        (0x1000U)
121618 #define TRDC_MRC_DOM10_RGD_NSE_BIT12_SHIFT       (12U)
121619 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
121620  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121621  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121622  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121623  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121624  */
121625 #define TRDC_MRC_DOM10_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT12_MASK)
121626 
121627 #define TRDC_MRC_DOM10_RGD_NSE_BIT13_MASK        (0x2000U)
121628 #define TRDC_MRC_DOM10_RGD_NSE_BIT13_SHIFT       (13U)
121629 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
121630  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121631  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121632  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121633  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121634  */
121635 #define TRDC_MRC_DOM10_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT13_MASK)
121636 
121637 #define TRDC_MRC_DOM10_RGD_NSE_BIT14_MASK        (0x4000U)
121638 #define TRDC_MRC_DOM10_RGD_NSE_BIT14_SHIFT       (14U)
121639 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
121640  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121641  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121642  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121643  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121644  */
121645 #define TRDC_MRC_DOM10_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT14_MASK)
121646 
121647 #define TRDC_MRC_DOM10_RGD_NSE_BIT15_MASK        (0x8000U)
121648 #define TRDC_MRC_DOM10_RGD_NSE_BIT15_SHIFT       (15U)
121649 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
121650  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121651  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121652  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121653  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121654  */
121655 #define TRDC_MRC_DOM10_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM10_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM10_RGD_NSE_BIT15_MASK)
121656 /*! @} */
121657 
121658 /* The count of TRDC_MRC_DOM10_RGD_NSE */
121659 #define TRDC_MRC_DOM10_RGD_NSE_COUNT             (7U)
121660 
121661 /*! @name MRC_DOM11_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
121662 /*! @{ */
121663 
121664 #define TRDC_MRC_DOM11_RGD_W_MRACSEL_MASK        (0x7U)
121665 #define TRDC_MRC_DOM11_RGD_W_MRACSEL_SHIFT       (0U)
121666 /*! MRACSEL - Memory Region Access Control Select
121667  *  0b000..Select MRC_GLBAC0 access control policy
121668  *  0b001..Select MRC_GLBAC1 access control policy
121669  *  0b010..Select MRC_GLBAC2 access control policy
121670  *  0b011..Select MRC_GLBAC3 access control policy
121671  *  0b100..Select MRC_GLBAC4 access control policy
121672  *  0b101..Select MRC_GLBAC5 access control policy
121673  *  0b110..Select MRC_GLBAC6 access control policy
121674  *  0b111..Select MRC_GLBAC7 access control policy
121675  */
121676 #define TRDC_MRC_DOM11_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM11_RGD_W_MRACSEL_MASK)
121677 
121678 #define TRDC_MRC_DOM11_RGD_W_VLD_MASK            (0x1U)
121679 #define TRDC_MRC_DOM11_RGD_W_VLD_SHIFT           (0U)
121680 /*! VLD - Valid */
121681 #define TRDC_MRC_DOM11_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM11_RGD_W_VLD_MASK)
121682 
121683 #define TRDC_MRC_DOM11_RGD_W_NSE_MASK            (0x10U)
121684 #define TRDC_MRC_DOM11_RGD_W_NSE_SHIFT           (4U)
121685 /*! NSE - NonSecure Enable
121686  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121687  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121688  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121689  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121690  */
121691 #define TRDC_MRC_DOM11_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM11_RGD_W_NSE_MASK)
121692 
121693 #define TRDC_MRC_DOM11_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
121694 #define TRDC_MRC_DOM11_RGD_W_END_ADDR_SHIFT      (14U)
121695 /*! END_ADDR - End Address */
121696 #define TRDC_MRC_DOM11_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM11_RGD_W_END_ADDR_MASK)
121697 
121698 #define TRDC_MRC_DOM11_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
121699 #define TRDC_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT     (14U)
121700 /*! STRT_ADDR - Start Address */
121701 #define TRDC_MRC_DOM11_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM11_RGD_W_STRT_ADDR_MASK)
121702 /*! @} */
121703 
121704 /* The count of TRDC_MRC_DOM11_RGD_W */
121705 #define TRDC_MRC_DOM11_RGD_W_COUNT               (7U)
121706 
121707 /* The count of TRDC_MRC_DOM11_RGD_W */
121708 #define TRDC_MRC_DOM11_RGD_W_COUNT2              (16U)
121709 
121710 /* The count of TRDC_MRC_DOM11_RGD_W */
121711 #define TRDC_MRC_DOM11_RGD_W_COUNT3              (2U)
121712 
121713 /*! @name MRC_DOM11_RGD_NSE - MRC Region Descriptor NonSecure Enable */
121714 /*! @{ */
121715 
121716 #define TRDC_MRC_DOM11_RGD_NSE_BIT0_MASK         (0x1U)
121717 #define TRDC_MRC_DOM11_RGD_NSE_BIT0_SHIFT        (0U)
121718 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
121719  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121720  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121721  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121722  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121723  */
121724 #define TRDC_MRC_DOM11_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT0_MASK)
121725 
121726 #define TRDC_MRC_DOM11_RGD_NSE_BIT1_MASK         (0x2U)
121727 #define TRDC_MRC_DOM11_RGD_NSE_BIT1_SHIFT        (1U)
121728 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
121729  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121730  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121731  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121732  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121733  */
121734 #define TRDC_MRC_DOM11_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT1_MASK)
121735 
121736 #define TRDC_MRC_DOM11_RGD_NSE_BIT2_MASK         (0x4U)
121737 #define TRDC_MRC_DOM11_RGD_NSE_BIT2_SHIFT        (2U)
121738 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
121739  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121740  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121741  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121742  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121743  */
121744 #define TRDC_MRC_DOM11_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT2_MASK)
121745 
121746 #define TRDC_MRC_DOM11_RGD_NSE_BIT3_MASK         (0x8U)
121747 #define TRDC_MRC_DOM11_RGD_NSE_BIT3_SHIFT        (3U)
121748 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
121749  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121750  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121751  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121752  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121753  */
121754 #define TRDC_MRC_DOM11_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT3_MASK)
121755 
121756 #define TRDC_MRC_DOM11_RGD_NSE_BIT4_MASK         (0x10U)
121757 #define TRDC_MRC_DOM11_RGD_NSE_BIT4_SHIFT        (4U)
121758 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
121759  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121760  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121761  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121762  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121763  */
121764 #define TRDC_MRC_DOM11_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT4_MASK)
121765 
121766 #define TRDC_MRC_DOM11_RGD_NSE_BIT5_MASK         (0x20U)
121767 #define TRDC_MRC_DOM11_RGD_NSE_BIT5_SHIFT        (5U)
121768 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
121769  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121770  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121771  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121772  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121773  */
121774 #define TRDC_MRC_DOM11_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT5_MASK)
121775 
121776 #define TRDC_MRC_DOM11_RGD_NSE_BIT6_MASK         (0x40U)
121777 #define TRDC_MRC_DOM11_RGD_NSE_BIT6_SHIFT        (6U)
121778 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
121779  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121780  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121781  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121782  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121783  */
121784 #define TRDC_MRC_DOM11_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT6_MASK)
121785 
121786 #define TRDC_MRC_DOM11_RGD_NSE_BIT7_MASK         (0x80U)
121787 #define TRDC_MRC_DOM11_RGD_NSE_BIT7_SHIFT        (7U)
121788 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
121789  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121790  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121791  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121792  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121793  */
121794 #define TRDC_MRC_DOM11_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT7_MASK)
121795 
121796 #define TRDC_MRC_DOM11_RGD_NSE_BIT8_MASK         (0x100U)
121797 #define TRDC_MRC_DOM11_RGD_NSE_BIT8_SHIFT        (8U)
121798 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
121799  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121800  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121801  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121802  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121803  */
121804 #define TRDC_MRC_DOM11_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT8_MASK)
121805 
121806 #define TRDC_MRC_DOM11_RGD_NSE_BIT9_MASK         (0x200U)
121807 #define TRDC_MRC_DOM11_RGD_NSE_BIT9_SHIFT        (9U)
121808 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
121809  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121810  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121811  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121812  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121813  */
121814 #define TRDC_MRC_DOM11_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT9_MASK)
121815 
121816 #define TRDC_MRC_DOM11_RGD_NSE_BIT10_MASK        (0x400U)
121817 #define TRDC_MRC_DOM11_RGD_NSE_BIT10_SHIFT       (10U)
121818 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
121819  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121820  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121821  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121822  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121823  */
121824 #define TRDC_MRC_DOM11_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT10_MASK)
121825 
121826 #define TRDC_MRC_DOM11_RGD_NSE_BIT11_MASK        (0x800U)
121827 #define TRDC_MRC_DOM11_RGD_NSE_BIT11_SHIFT       (11U)
121828 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
121829  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121830  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121831  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121832  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121833  */
121834 #define TRDC_MRC_DOM11_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT11_MASK)
121835 
121836 #define TRDC_MRC_DOM11_RGD_NSE_BIT12_MASK        (0x1000U)
121837 #define TRDC_MRC_DOM11_RGD_NSE_BIT12_SHIFT       (12U)
121838 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
121839  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121840  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121841  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121842  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121843  */
121844 #define TRDC_MRC_DOM11_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT12_MASK)
121845 
121846 #define TRDC_MRC_DOM11_RGD_NSE_BIT13_MASK        (0x2000U)
121847 #define TRDC_MRC_DOM11_RGD_NSE_BIT13_SHIFT       (13U)
121848 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
121849  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121850  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121851  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121852  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121853  */
121854 #define TRDC_MRC_DOM11_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT13_MASK)
121855 
121856 #define TRDC_MRC_DOM11_RGD_NSE_BIT14_MASK        (0x4000U)
121857 #define TRDC_MRC_DOM11_RGD_NSE_BIT14_SHIFT       (14U)
121858 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
121859  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121860  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121861  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121862  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121863  */
121864 #define TRDC_MRC_DOM11_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT14_MASK)
121865 
121866 #define TRDC_MRC_DOM11_RGD_NSE_BIT15_MASK        (0x8000U)
121867 #define TRDC_MRC_DOM11_RGD_NSE_BIT15_SHIFT       (15U)
121868 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
121869  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121870  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121871  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121872  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121873  */
121874 #define TRDC_MRC_DOM11_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM11_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM11_RGD_NSE_BIT15_MASK)
121875 /*! @} */
121876 
121877 /* The count of TRDC_MRC_DOM11_RGD_NSE */
121878 #define TRDC_MRC_DOM11_RGD_NSE_COUNT             (7U)
121879 
121880 /*! @name MRC_DOM12_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
121881 /*! @{ */
121882 
121883 #define TRDC_MRC_DOM12_RGD_W_MRACSEL_MASK        (0x7U)
121884 #define TRDC_MRC_DOM12_RGD_W_MRACSEL_SHIFT       (0U)
121885 /*! MRACSEL - Memory Region Access Control Select
121886  *  0b000..Select MRC_GLBAC0 access control policy
121887  *  0b001..Select MRC_GLBAC1 access control policy
121888  *  0b010..Select MRC_GLBAC2 access control policy
121889  *  0b011..Select MRC_GLBAC3 access control policy
121890  *  0b100..Select MRC_GLBAC4 access control policy
121891  *  0b101..Select MRC_GLBAC5 access control policy
121892  *  0b110..Select MRC_GLBAC6 access control policy
121893  *  0b111..Select MRC_GLBAC7 access control policy
121894  */
121895 #define TRDC_MRC_DOM12_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM12_RGD_W_MRACSEL_MASK)
121896 
121897 #define TRDC_MRC_DOM12_RGD_W_VLD_MASK            (0x1U)
121898 #define TRDC_MRC_DOM12_RGD_W_VLD_SHIFT           (0U)
121899 /*! VLD - Valid */
121900 #define TRDC_MRC_DOM12_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM12_RGD_W_VLD_MASK)
121901 
121902 #define TRDC_MRC_DOM12_RGD_W_NSE_MASK            (0x10U)
121903 #define TRDC_MRC_DOM12_RGD_W_NSE_SHIFT           (4U)
121904 /*! NSE - NonSecure Enable
121905  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121906  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121907  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121908  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121909  */
121910 #define TRDC_MRC_DOM12_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM12_RGD_W_NSE_MASK)
121911 
121912 #define TRDC_MRC_DOM12_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
121913 #define TRDC_MRC_DOM12_RGD_W_END_ADDR_SHIFT      (14U)
121914 /*! END_ADDR - End Address */
121915 #define TRDC_MRC_DOM12_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM12_RGD_W_END_ADDR_MASK)
121916 
121917 #define TRDC_MRC_DOM12_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
121918 #define TRDC_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT     (14U)
121919 /*! STRT_ADDR - Start Address */
121920 #define TRDC_MRC_DOM12_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM12_RGD_W_STRT_ADDR_MASK)
121921 /*! @} */
121922 
121923 /* The count of TRDC_MRC_DOM12_RGD_W */
121924 #define TRDC_MRC_DOM12_RGD_W_COUNT               (7U)
121925 
121926 /* The count of TRDC_MRC_DOM12_RGD_W */
121927 #define TRDC_MRC_DOM12_RGD_W_COUNT2              (16U)
121928 
121929 /* The count of TRDC_MRC_DOM12_RGD_W */
121930 #define TRDC_MRC_DOM12_RGD_W_COUNT3              (2U)
121931 
121932 /*! @name MRC_DOM12_RGD_NSE - MRC Region Descriptor NonSecure Enable */
121933 /*! @{ */
121934 
121935 #define TRDC_MRC_DOM12_RGD_NSE_BIT0_MASK         (0x1U)
121936 #define TRDC_MRC_DOM12_RGD_NSE_BIT0_SHIFT        (0U)
121937 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
121938  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121939  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121940  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121941  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121942  */
121943 #define TRDC_MRC_DOM12_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT0_MASK)
121944 
121945 #define TRDC_MRC_DOM12_RGD_NSE_BIT1_MASK         (0x2U)
121946 #define TRDC_MRC_DOM12_RGD_NSE_BIT1_SHIFT        (1U)
121947 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
121948  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121949  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121950  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121951  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121952  */
121953 #define TRDC_MRC_DOM12_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT1_MASK)
121954 
121955 #define TRDC_MRC_DOM12_RGD_NSE_BIT2_MASK         (0x4U)
121956 #define TRDC_MRC_DOM12_RGD_NSE_BIT2_SHIFT        (2U)
121957 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
121958  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121959  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121960  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121961  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121962  */
121963 #define TRDC_MRC_DOM12_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT2_MASK)
121964 
121965 #define TRDC_MRC_DOM12_RGD_NSE_BIT3_MASK         (0x8U)
121966 #define TRDC_MRC_DOM12_RGD_NSE_BIT3_SHIFT        (3U)
121967 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
121968  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121969  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121970  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121971  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121972  */
121973 #define TRDC_MRC_DOM12_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT3_MASK)
121974 
121975 #define TRDC_MRC_DOM12_RGD_NSE_BIT4_MASK         (0x10U)
121976 #define TRDC_MRC_DOM12_RGD_NSE_BIT4_SHIFT        (4U)
121977 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
121978  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121979  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121980  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121981  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121982  */
121983 #define TRDC_MRC_DOM12_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT4_MASK)
121984 
121985 #define TRDC_MRC_DOM12_RGD_NSE_BIT5_MASK         (0x20U)
121986 #define TRDC_MRC_DOM12_RGD_NSE_BIT5_SHIFT        (5U)
121987 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
121988  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121989  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
121990  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
121991  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
121992  */
121993 #define TRDC_MRC_DOM12_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT5_MASK)
121994 
121995 #define TRDC_MRC_DOM12_RGD_NSE_BIT6_MASK         (0x40U)
121996 #define TRDC_MRC_DOM12_RGD_NSE_BIT6_SHIFT        (6U)
121997 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
121998  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
121999  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122000  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122001  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122002  */
122003 #define TRDC_MRC_DOM12_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT6_MASK)
122004 
122005 #define TRDC_MRC_DOM12_RGD_NSE_BIT7_MASK         (0x80U)
122006 #define TRDC_MRC_DOM12_RGD_NSE_BIT7_SHIFT        (7U)
122007 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
122008  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122009  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122010  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122011  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122012  */
122013 #define TRDC_MRC_DOM12_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT7_MASK)
122014 
122015 #define TRDC_MRC_DOM12_RGD_NSE_BIT8_MASK         (0x100U)
122016 #define TRDC_MRC_DOM12_RGD_NSE_BIT8_SHIFT        (8U)
122017 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
122018  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122019  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122020  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122021  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122022  */
122023 #define TRDC_MRC_DOM12_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT8_MASK)
122024 
122025 #define TRDC_MRC_DOM12_RGD_NSE_BIT9_MASK         (0x200U)
122026 #define TRDC_MRC_DOM12_RGD_NSE_BIT9_SHIFT        (9U)
122027 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
122028  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122029  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122030  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122031  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122032  */
122033 #define TRDC_MRC_DOM12_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT9_MASK)
122034 
122035 #define TRDC_MRC_DOM12_RGD_NSE_BIT10_MASK        (0x400U)
122036 #define TRDC_MRC_DOM12_RGD_NSE_BIT10_SHIFT       (10U)
122037 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
122038  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122039  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122040  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122041  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122042  */
122043 #define TRDC_MRC_DOM12_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT10_MASK)
122044 
122045 #define TRDC_MRC_DOM12_RGD_NSE_BIT11_MASK        (0x800U)
122046 #define TRDC_MRC_DOM12_RGD_NSE_BIT11_SHIFT       (11U)
122047 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
122048  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122049  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122050  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122051  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122052  */
122053 #define TRDC_MRC_DOM12_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT11_MASK)
122054 
122055 #define TRDC_MRC_DOM12_RGD_NSE_BIT12_MASK        (0x1000U)
122056 #define TRDC_MRC_DOM12_RGD_NSE_BIT12_SHIFT       (12U)
122057 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
122058  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122059  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122060  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122061  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122062  */
122063 #define TRDC_MRC_DOM12_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT12_MASK)
122064 
122065 #define TRDC_MRC_DOM12_RGD_NSE_BIT13_MASK        (0x2000U)
122066 #define TRDC_MRC_DOM12_RGD_NSE_BIT13_SHIFT       (13U)
122067 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
122068  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122069  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122070  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122071  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122072  */
122073 #define TRDC_MRC_DOM12_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT13_MASK)
122074 
122075 #define TRDC_MRC_DOM12_RGD_NSE_BIT14_MASK        (0x4000U)
122076 #define TRDC_MRC_DOM12_RGD_NSE_BIT14_SHIFT       (14U)
122077 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
122078  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122079  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122080  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122081  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122082  */
122083 #define TRDC_MRC_DOM12_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT14_MASK)
122084 
122085 #define TRDC_MRC_DOM12_RGD_NSE_BIT15_MASK        (0x8000U)
122086 #define TRDC_MRC_DOM12_RGD_NSE_BIT15_SHIFT       (15U)
122087 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
122088  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122089  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122090  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122091  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122092  */
122093 #define TRDC_MRC_DOM12_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM12_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM12_RGD_NSE_BIT15_MASK)
122094 /*! @} */
122095 
122096 /* The count of TRDC_MRC_DOM12_RGD_NSE */
122097 #define TRDC_MRC_DOM12_RGD_NSE_COUNT             (7U)
122098 
122099 /*! @name MRC_DOM13_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
122100 /*! @{ */
122101 
122102 #define TRDC_MRC_DOM13_RGD_W_MRACSEL_MASK        (0x7U)
122103 #define TRDC_MRC_DOM13_RGD_W_MRACSEL_SHIFT       (0U)
122104 /*! MRACSEL - Memory Region Access Control Select
122105  *  0b000..Select MRC_GLBAC0 access control policy
122106  *  0b001..Select MRC_GLBAC1 access control policy
122107  *  0b010..Select MRC_GLBAC2 access control policy
122108  *  0b011..Select MRC_GLBAC3 access control policy
122109  *  0b100..Select MRC_GLBAC4 access control policy
122110  *  0b101..Select MRC_GLBAC5 access control policy
122111  *  0b110..Select MRC_GLBAC6 access control policy
122112  *  0b111..Select MRC_GLBAC7 access control policy
122113  */
122114 #define TRDC_MRC_DOM13_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM13_RGD_W_MRACSEL_MASK)
122115 
122116 #define TRDC_MRC_DOM13_RGD_W_VLD_MASK            (0x1U)
122117 #define TRDC_MRC_DOM13_RGD_W_VLD_SHIFT           (0U)
122118 /*! VLD - Valid */
122119 #define TRDC_MRC_DOM13_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM13_RGD_W_VLD_MASK)
122120 
122121 #define TRDC_MRC_DOM13_RGD_W_NSE_MASK            (0x10U)
122122 #define TRDC_MRC_DOM13_RGD_W_NSE_SHIFT           (4U)
122123 /*! NSE - NonSecure Enable
122124  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122125  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122126  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122127  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122128  */
122129 #define TRDC_MRC_DOM13_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM13_RGD_W_NSE_MASK)
122130 
122131 #define TRDC_MRC_DOM13_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
122132 #define TRDC_MRC_DOM13_RGD_W_END_ADDR_SHIFT      (14U)
122133 /*! END_ADDR - End Address */
122134 #define TRDC_MRC_DOM13_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM13_RGD_W_END_ADDR_MASK)
122135 
122136 #define TRDC_MRC_DOM13_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
122137 #define TRDC_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT     (14U)
122138 /*! STRT_ADDR - Start Address */
122139 #define TRDC_MRC_DOM13_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM13_RGD_W_STRT_ADDR_MASK)
122140 /*! @} */
122141 
122142 /* The count of TRDC_MRC_DOM13_RGD_W */
122143 #define TRDC_MRC_DOM13_RGD_W_COUNT               (7U)
122144 
122145 /* The count of TRDC_MRC_DOM13_RGD_W */
122146 #define TRDC_MRC_DOM13_RGD_W_COUNT2              (16U)
122147 
122148 /* The count of TRDC_MRC_DOM13_RGD_W */
122149 #define TRDC_MRC_DOM13_RGD_W_COUNT3              (2U)
122150 
122151 /*! @name MRC_DOM13_RGD_NSE - MRC Region Descriptor NonSecure Enable */
122152 /*! @{ */
122153 
122154 #define TRDC_MRC_DOM13_RGD_NSE_BIT0_MASK         (0x1U)
122155 #define TRDC_MRC_DOM13_RGD_NSE_BIT0_SHIFT        (0U)
122156 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
122157  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122158  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122159  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122160  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122161  */
122162 #define TRDC_MRC_DOM13_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT0_MASK)
122163 
122164 #define TRDC_MRC_DOM13_RGD_NSE_BIT1_MASK         (0x2U)
122165 #define TRDC_MRC_DOM13_RGD_NSE_BIT1_SHIFT        (1U)
122166 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
122167  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122168  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122169  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122170  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122171  */
122172 #define TRDC_MRC_DOM13_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT1_MASK)
122173 
122174 #define TRDC_MRC_DOM13_RGD_NSE_BIT2_MASK         (0x4U)
122175 #define TRDC_MRC_DOM13_RGD_NSE_BIT2_SHIFT        (2U)
122176 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
122177  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122178  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122179  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122180  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122181  */
122182 #define TRDC_MRC_DOM13_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT2_MASK)
122183 
122184 #define TRDC_MRC_DOM13_RGD_NSE_BIT3_MASK         (0x8U)
122185 #define TRDC_MRC_DOM13_RGD_NSE_BIT3_SHIFT        (3U)
122186 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
122187  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122188  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122189  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122190  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122191  */
122192 #define TRDC_MRC_DOM13_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT3_MASK)
122193 
122194 #define TRDC_MRC_DOM13_RGD_NSE_BIT4_MASK         (0x10U)
122195 #define TRDC_MRC_DOM13_RGD_NSE_BIT4_SHIFT        (4U)
122196 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
122197  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122198  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122199  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122200  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122201  */
122202 #define TRDC_MRC_DOM13_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT4_MASK)
122203 
122204 #define TRDC_MRC_DOM13_RGD_NSE_BIT5_MASK         (0x20U)
122205 #define TRDC_MRC_DOM13_RGD_NSE_BIT5_SHIFT        (5U)
122206 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
122207  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122208  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122209  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122210  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122211  */
122212 #define TRDC_MRC_DOM13_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT5_MASK)
122213 
122214 #define TRDC_MRC_DOM13_RGD_NSE_BIT6_MASK         (0x40U)
122215 #define TRDC_MRC_DOM13_RGD_NSE_BIT6_SHIFT        (6U)
122216 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
122217  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122218  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122219  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122220  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122221  */
122222 #define TRDC_MRC_DOM13_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT6_MASK)
122223 
122224 #define TRDC_MRC_DOM13_RGD_NSE_BIT7_MASK         (0x80U)
122225 #define TRDC_MRC_DOM13_RGD_NSE_BIT7_SHIFT        (7U)
122226 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
122227  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122228  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122229  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122230  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122231  */
122232 #define TRDC_MRC_DOM13_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT7_MASK)
122233 
122234 #define TRDC_MRC_DOM13_RGD_NSE_BIT8_MASK         (0x100U)
122235 #define TRDC_MRC_DOM13_RGD_NSE_BIT8_SHIFT        (8U)
122236 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
122237  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122238  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122239  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122240  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122241  */
122242 #define TRDC_MRC_DOM13_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT8_MASK)
122243 
122244 #define TRDC_MRC_DOM13_RGD_NSE_BIT9_MASK         (0x200U)
122245 #define TRDC_MRC_DOM13_RGD_NSE_BIT9_SHIFT        (9U)
122246 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
122247  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122248  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122249  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122250  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122251  */
122252 #define TRDC_MRC_DOM13_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT9_MASK)
122253 
122254 #define TRDC_MRC_DOM13_RGD_NSE_BIT10_MASK        (0x400U)
122255 #define TRDC_MRC_DOM13_RGD_NSE_BIT10_SHIFT       (10U)
122256 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
122257  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122258  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122259  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122260  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122261  */
122262 #define TRDC_MRC_DOM13_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT10_MASK)
122263 
122264 #define TRDC_MRC_DOM13_RGD_NSE_BIT11_MASK        (0x800U)
122265 #define TRDC_MRC_DOM13_RGD_NSE_BIT11_SHIFT       (11U)
122266 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
122267  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122268  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122269  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122270  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122271  */
122272 #define TRDC_MRC_DOM13_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT11_MASK)
122273 
122274 #define TRDC_MRC_DOM13_RGD_NSE_BIT12_MASK        (0x1000U)
122275 #define TRDC_MRC_DOM13_RGD_NSE_BIT12_SHIFT       (12U)
122276 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
122277  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122278  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122279  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122280  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122281  */
122282 #define TRDC_MRC_DOM13_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT12_MASK)
122283 
122284 #define TRDC_MRC_DOM13_RGD_NSE_BIT13_MASK        (0x2000U)
122285 #define TRDC_MRC_DOM13_RGD_NSE_BIT13_SHIFT       (13U)
122286 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
122287  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122288  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122289  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122290  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122291  */
122292 #define TRDC_MRC_DOM13_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT13_MASK)
122293 
122294 #define TRDC_MRC_DOM13_RGD_NSE_BIT14_MASK        (0x4000U)
122295 #define TRDC_MRC_DOM13_RGD_NSE_BIT14_SHIFT       (14U)
122296 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
122297  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122298  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122299  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122300  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122301  */
122302 #define TRDC_MRC_DOM13_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT14_MASK)
122303 
122304 #define TRDC_MRC_DOM13_RGD_NSE_BIT15_MASK        (0x8000U)
122305 #define TRDC_MRC_DOM13_RGD_NSE_BIT15_SHIFT       (15U)
122306 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
122307  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122308  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122309  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122310  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122311  */
122312 #define TRDC_MRC_DOM13_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM13_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM13_RGD_NSE_BIT15_MASK)
122313 /*! @} */
122314 
122315 /* The count of TRDC_MRC_DOM13_RGD_NSE */
122316 #define TRDC_MRC_DOM13_RGD_NSE_COUNT             (7U)
122317 
122318 /*! @name MRC_DOM14_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
122319 /*! @{ */
122320 
122321 #define TRDC_MRC_DOM14_RGD_W_MRACSEL_MASK        (0x7U)
122322 #define TRDC_MRC_DOM14_RGD_W_MRACSEL_SHIFT       (0U)
122323 /*! MRACSEL - Memory Region Access Control Select
122324  *  0b000..Select MRC_GLBAC0 access control policy
122325  *  0b001..Select MRC_GLBAC1 access control policy
122326  *  0b010..Select MRC_GLBAC2 access control policy
122327  *  0b011..Select MRC_GLBAC3 access control policy
122328  *  0b100..Select MRC_GLBAC4 access control policy
122329  *  0b101..Select MRC_GLBAC5 access control policy
122330  *  0b110..Select MRC_GLBAC6 access control policy
122331  *  0b111..Select MRC_GLBAC7 access control policy
122332  */
122333 #define TRDC_MRC_DOM14_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM14_RGD_W_MRACSEL_MASK)
122334 
122335 #define TRDC_MRC_DOM14_RGD_W_VLD_MASK            (0x1U)
122336 #define TRDC_MRC_DOM14_RGD_W_VLD_SHIFT           (0U)
122337 /*! VLD - Valid */
122338 #define TRDC_MRC_DOM14_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM14_RGD_W_VLD_MASK)
122339 
122340 #define TRDC_MRC_DOM14_RGD_W_NSE_MASK            (0x10U)
122341 #define TRDC_MRC_DOM14_RGD_W_NSE_SHIFT           (4U)
122342 /*! NSE - NonSecure Enable
122343  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122344  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122345  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122346  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122347  */
122348 #define TRDC_MRC_DOM14_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM14_RGD_W_NSE_MASK)
122349 
122350 #define TRDC_MRC_DOM14_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
122351 #define TRDC_MRC_DOM14_RGD_W_END_ADDR_SHIFT      (14U)
122352 /*! END_ADDR - End Address */
122353 #define TRDC_MRC_DOM14_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM14_RGD_W_END_ADDR_MASK)
122354 
122355 #define TRDC_MRC_DOM14_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
122356 #define TRDC_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT     (14U)
122357 /*! STRT_ADDR - Start Address */
122358 #define TRDC_MRC_DOM14_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM14_RGD_W_STRT_ADDR_MASK)
122359 /*! @} */
122360 
122361 /* The count of TRDC_MRC_DOM14_RGD_W */
122362 #define TRDC_MRC_DOM14_RGD_W_COUNT               (7U)
122363 
122364 /* The count of TRDC_MRC_DOM14_RGD_W */
122365 #define TRDC_MRC_DOM14_RGD_W_COUNT2              (16U)
122366 
122367 /* The count of TRDC_MRC_DOM14_RGD_W */
122368 #define TRDC_MRC_DOM14_RGD_W_COUNT3              (2U)
122369 
122370 /*! @name MRC_DOM14_RGD_NSE - MRC Region Descriptor NonSecure Enable */
122371 /*! @{ */
122372 
122373 #define TRDC_MRC_DOM14_RGD_NSE_BIT0_MASK         (0x1U)
122374 #define TRDC_MRC_DOM14_RGD_NSE_BIT0_SHIFT        (0U)
122375 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
122376  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122377  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122378  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122379  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122380  */
122381 #define TRDC_MRC_DOM14_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT0_MASK)
122382 
122383 #define TRDC_MRC_DOM14_RGD_NSE_BIT1_MASK         (0x2U)
122384 #define TRDC_MRC_DOM14_RGD_NSE_BIT1_SHIFT        (1U)
122385 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
122386  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122387  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122388  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122389  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122390  */
122391 #define TRDC_MRC_DOM14_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT1_MASK)
122392 
122393 #define TRDC_MRC_DOM14_RGD_NSE_BIT2_MASK         (0x4U)
122394 #define TRDC_MRC_DOM14_RGD_NSE_BIT2_SHIFT        (2U)
122395 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
122396  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122397  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122398  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122399  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122400  */
122401 #define TRDC_MRC_DOM14_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT2_MASK)
122402 
122403 #define TRDC_MRC_DOM14_RGD_NSE_BIT3_MASK         (0x8U)
122404 #define TRDC_MRC_DOM14_RGD_NSE_BIT3_SHIFT        (3U)
122405 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
122406  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122407  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122408  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122409  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122410  */
122411 #define TRDC_MRC_DOM14_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT3_MASK)
122412 
122413 #define TRDC_MRC_DOM14_RGD_NSE_BIT4_MASK         (0x10U)
122414 #define TRDC_MRC_DOM14_RGD_NSE_BIT4_SHIFT        (4U)
122415 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
122416  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122417  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122418  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122419  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122420  */
122421 #define TRDC_MRC_DOM14_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT4_MASK)
122422 
122423 #define TRDC_MRC_DOM14_RGD_NSE_BIT5_MASK         (0x20U)
122424 #define TRDC_MRC_DOM14_RGD_NSE_BIT5_SHIFT        (5U)
122425 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
122426  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122427  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122428  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122429  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122430  */
122431 #define TRDC_MRC_DOM14_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT5_MASK)
122432 
122433 #define TRDC_MRC_DOM14_RGD_NSE_BIT6_MASK         (0x40U)
122434 #define TRDC_MRC_DOM14_RGD_NSE_BIT6_SHIFT        (6U)
122435 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
122436  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122437  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122438  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122439  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122440  */
122441 #define TRDC_MRC_DOM14_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT6_MASK)
122442 
122443 #define TRDC_MRC_DOM14_RGD_NSE_BIT7_MASK         (0x80U)
122444 #define TRDC_MRC_DOM14_RGD_NSE_BIT7_SHIFT        (7U)
122445 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
122446  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122447  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122448  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122449  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122450  */
122451 #define TRDC_MRC_DOM14_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT7_MASK)
122452 
122453 #define TRDC_MRC_DOM14_RGD_NSE_BIT8_MASK         (0x100U)
122454 #define TRDC_MRC_DOM14_RGD_NSE_BIT8_SHIFT        (8U)
122455 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
122456  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122457  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122458  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122459  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122460  */
122461 #define TRDC_MRC_DOM14_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT8_MASK)
122462 
122463 #define TRDC_MRC_DOM14_RGD_NSE_BIT9_MASK         (0x200U)
122464 #define TRDC_MRC_DOM14_RGD_NSE_BIT9_SHIFT        (9U)
122465 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
122466  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122467  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122468  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122469  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122470  */
122471 #define TRDC_MRC_DOM14_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT9_MASK)
122472 
122473 #define TRDC_MRC_DOM14_RGD_NSE_BIT10_MASK        (0x400U)
122474 #define TRDC_MRC_DOM14_RGD_NSE_BIT10_SHIFT       (10U)
122475 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
122476  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122477  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122478  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122479  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122480  */
122481 #define TRDC_MRC_DOM14_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT10_MASK)
122482 
122483 #define TRDC_MRC_DOM14_RGD_NSE_BIT11_MASK        (0x800U)
122484 #define TRDC_MRC_DOM14_RGD_NSE_BIT11_SHIFT       (11U)
122485 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
122486  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122487  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122488  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122489  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122490  */
122491 #define TRDC_MRC_DOM14_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT11_MASK)
122492 
122493 #define TRDC_MRC_DOM14_RGD_NSE_BIT12_MASK        (0x1000U)
122494 #define TRDC_MRC_DOM14_RGD_NSE_BIT12_SHIFT       (12U)
122495 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
122496  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122497  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122498  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122499  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122500  */
122501 #define TRDC_MRC_DOM14_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT12_MASK)
122502 
122503 #define TRDC_MRC_DOM14_RGD_NSE_BIT13_MASK        (0x2000U)
122504 #define TRDC_MRC_DOM14_RGD_NSE_BIT13_SHIFT       (13U)
122505 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
122506  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122507  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122508  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122509  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122510  */
122511 #define TRDC_MRC_DOM14_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT13_MASK)
122512 
122513 #define TRDC_MRC_DOM14_RGD_NSE_BIT14_MASK        (0x4000U)
122514 #define TRDC_MRC_DOM14_RGD_NSE_BIT14_SHIFT       (14U)
122515 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
122516  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122517  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122518  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122519  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122520  */
122521 #define TRDC_MRC_DOM14_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT14_MASK)
122522 
122523 #define TRDC_MRC_DOM14_RGD_NSE_BIT15_MASK        (0x8000U)
122524 #define TRDC_MRC_DOM14_RGD_NSE_BIT15_SHIFT       (15U)
122525 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
122526  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122527  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122528  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122529  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122530  */
122531 #define TRDC_MRC_DOM14_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM14_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM14_RGD_NSE_BIT15_MASK)
122532 /*! @} */
122533 
122534 /* The count of TRDC_MRC_DOM14_RGD_NSE */
122535 #define TRDC_MRC_DOM14_RGD_NSE_COUNT             (7U)
122536 
122537 /*! @name MRC_DOM15_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
122538 /*! @{ */
122539 
122540 #define TRDC_MRC_DOM15_RGD_W_MRACSEL_MASK        (0x7U)
122541 #define TRDC_MRC_DOM15_RGD_W_MRACSEL_SHIFT       (0U)
122542 /*! MRACSEL - Memory Region Access Control Select
122543  *  0b000..Select MRC_GLBAC0 access control policy
122544  *  0b001..Select MRC_GLBAC1 access control policy
122545  *  0b010..Select MRC_GLBAC2 access control policy
122546  *  0b011..Select MRC_GLBAC3 access control policy
122547  *  0b100..Select MRC_GLBAC4 access control policy
122548  *  0b101..Select MRC_GLBAC5 access control policy
122549  *  0b110..Select MRC_GLBAC6 access control policy
122550  *  0b111..Select MRC_GLBAC7 access control policy
122551  */
122552 #define TRDC_MRC_DOM15_RGD_W_MRACSEL(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM15_RGD_W_MRACSEL_MASK)
122553 
122554 #define TRDC_MRC_DOM15_RGD_W_VLD_MASK            (0x1U)
122555 #define TRDC_MRC_DOM15_RGD_W_VLD_SHIFT           (0U)
122556 /*! VLD - Valid */
122557 #define TRDC_MRC_DOM15_RGD_W_VLD(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM15_RGD_W_VLD_MASK)
122558 
122559 #define TRDC_MRC_DOM15_RGD_W_NSE_MASK            (0x10U)
122560 #define TRDC_MRC_DOM15_RGD_W_NSE_SHIFT           (4U)
122561 /*! NSE - NonSecure Enable
122562  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122563  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122564  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122565  *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122566  */
122567 #define TRDC_MRC_DOM15_RGD_W_NSE(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM15_RGD_W_NSE_MASK)
122568 
122569 #define TRDC_MRC_DOM15_RGD_W_END_ADDR_MASK       (0xFFFFC000U)
122570 #define TRDC_MRC_DOM15_RGD_W_END_ADDR_SHIFT      (14U)
122571 /*! END_ADDR - End Address */
122572 #define TRDC_MRC_DOM15_RGD_W_END_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM15_RGD_W_END_ADDR_MASK)
122573 
122574 #define TRDC_MRC_DOM15_RGD_W_STRT_ADDR_MASK      (0xFFFFC000U)
122575 #define TRDC_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT     (14U)
122576 /*! STRT_ADDR - Start Address */
122577 #define TRDC_MRC_DOM15_RGD_W_STRT_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM15_RGD_W_STRT_ADDR_MASK)
122578 /*! @} */
122579 
122580 /* The count of TRDC_MRC_DOM15_RGD_W */
122581 #define TRDC_MRC_DOM15_RGD_W_COUNT               (7U)
122582 
122583 /* The count of TRDC_MRC_DOM15_RGD_W */
122584 #define TRDC_MRC_DOM15_RGD_W_COUNT2              (16U)
122585 
122586 /* The count of TRDC_MRC_DOM15_RGD_W */
122587 #define TRDC_MRC_DOM15_RGD_W_COUNT3              (2U)
122588 
122589 /*! @name MRC_DOM15_RGD_NSE - MRC Region Descriptor NonSecure Enable */
122590 /*! @{ */
122591 
122592 #define TRDC_MRC_DOM15_RGD_NSE_BIT0_MASK         (0x1U)
122593 #define TRDC_MRC_DOM15_RGD_NSE_BIT0_SHIFT        (0U)
122594 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
122595  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122596  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122597  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122598  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122599  */
122600 #define TRDC_MRC_DOM15_RGD_NSE_BIT0(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT0_MASK)
122601 
122602 #define TRDC_MRC_DOM15_RGD_NSE_BIT1_MASK         (0x2U)
122603 #define TRDC_MRC_DOM15_RGD_NSE_BIT1_SHIFT        (1U)
122604 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
122605  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122606  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122607  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122608  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122609  */
122610 #define TRDC_MRC_DOM15_RGD_NSE_BIT1(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT1_MASK)
122611 
122612 #define TRDC_MRC_DOM15_RGD_NSE_BIT2_MASK         (0x4U)
122613 #define TRDC_MRC_DOM15_RGD_NSE_BIT2_SHIFT        (2U)
122614 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
122615  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122616  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122617  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122618  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122619  */
122620 #define TRDC_MRC_DOM15_RGD_NSE_BIT2(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT2_MASK)
122621 
122622 #define TRDC_MRC_DOM15_RGD_NSE_BIT3_MASK         (0x8U)
122623 #define TRDC_MRC_DOM15_RGD_NSE_BIT3_SHIFT        (3U)
122624 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
122625  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122626  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122627  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122628  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122629  */
122630 #define TRDC_MRC_DOM15_RGD_NSE_BIT3(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT3_MASK)
122631 
122632 #define TRDC_MRC_DOM15_RGD_NSE_BIT4_MASK         (0x10U)
122633 #define TRDC_MRC_DOM15_RGD_NSE_BIT4_SHIFT        (4U)
122634 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
122635  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122636  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122637  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122638  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122639  */
122640 #define TRDC_MRC_DOM15_RGD_NSE_BIT4(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT4_MASK)
122641 
122642 #define TRDC_MRC_DOM15_RGD_NSE_BIT5_MASK         (0x20U)
122643 #define TRDC_MRC_DOM15_RGD_NSE_BIT5_SHIFT        (5U)
122644 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
122645  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122646  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122647  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122648  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122649  */
122650 #define TRDC_MRC_DOM15_RGD_NSE_BIT5(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT5_MASK)
122651 
122652 #define TRDC_MRC_DOM15_RGD_NSE_BIT6_MASK         (0x40U)
122653 #define TRDC_MRC_DOM15_RGD_NSE_BIT6_SHIFT        (6U)
122654 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
122655  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122656  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122657  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122658  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122659  */
122660 #define TRDC_MRC_DOM15_RGD_NSE_BIT6(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT6_MASK)
122661 
122662 #define TRDC_MRC_DOM15_RGD_NSE_BIT7_MASK         (0x80U)
122663 #define TRDC_MRC_DOM15_RGD_NSE_BIT7_SHIFT        (7U)
122664 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
122665  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122666  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122667  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122668  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122669  */
122670 #define TRDC_MRC_DOM15_RGD_NSE_BIT7(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT7_MASK)
122671 
122672 #define TRDC_MRC_DOM15_RGD_NSE_BIT8_MASK         (0x100U)
122673 #define TRDC_MRC_DOM15_RGD_NSE_BIT8_SHIFT        (8U)
122674 /*! BIT8 - Bit n NonSecure Enable [n = 0 - 15]
122675  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122676  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122677  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122678  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122679  */
122680 #define TRDC_MRC_DOM15_RGD_NSE_BIT8(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT8_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT8_MASK)
122681 
122682 #define TRDC_MRC_DOM15_RGD_NSE_BIT9_MASK         (0x200U)
122683 #define TRDC_MRC_DOM15_RGD_NSE_BIT9_SHIFT        (9U)
122684 /*! BIT9 - Bit n NonSecure Enable [n = 0 - 15]
122685  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122686  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122687  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122688  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122689  */
122690 #define TRDC_MRC_DOM15_RGD_NSE_BIT9(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT9_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT9_MASK)
122691 
122692 #define TRDC_MRC_DOM15_RGD_NSE_BIT10_MASK        (0x400U)
122693 #define TRDC_MRC_DOM15_RGD_NSE_BIT10_SHIFT       (10U)
122694 /*! BIT10 - Bit n NonSecure Enable [n = 0 - 15]
122695  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122696  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122697  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122698  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122699  */
122700 #define TRDC_MRC_DOM15_RGD_NSE_BIT10(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT10_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT10_MASK)
122701 
122702 #define TRDC_MRC_DOM15_RGD_NSE_BIT11_MASK        (0x800U)
122703 #define TRDC_MRC_DOM15_RGD_NSE_BIT11_SHIFT       (11U)
122704 /*! BIT11 - Bit n NonSecure Enable [n = 0 - 15]
122705  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122706  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122707  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122708  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122709  */
122710 #define TRDC_MRC_DOM15_RGD_NSE_BIT11(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT11_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT11_MASK)
122711 
122712 #define TRDC_MRC_DOM15_RGD_NSE_BIT12_MASK        (0x1000U)
122713 #define TRDC_MRC_DOM15_RGD_NSE_BIT12_SHIFT       (12U)
122714 /*! BIT12 - Bit n NonSecure Enable [n = 0 - 15]
122715  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122716  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122717  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122718  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122719  */
122720 #define TRDC_MRC_DOM15_RGD_NSE_BIT12(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT12_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT12_MASK)
122721 
122722 #define TRDC_MRC_DOM15_RGD_NSE_BIT13_MASK        (0x2000U)
122723 #define TRDC_MRC_DOM15_RGD_NSE_BIT13_SHIFT       (13U)
122724 /*! BIT13 - Bit n NonSecure Enable [n = 0 - 15]
122725  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122726  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122727  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122728  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122729  */
122730 #define TRDC_MRC_DOM15_RGD_NSE_BIT13(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT13_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT13_MASK)
122731 
122732 #define TRDC_MRC_DOM15_RGD_NSE_BIT14_MASK        (0x4000U)
122733 #define TRDC_MRC_DOM15_RGD_NSE_BIT14_SHIFT       (14U)
122734 /*! BIT14 - Bit n NonSecure Enable [n = 0 - 15]
122735  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122736  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122737  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122738  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122739  */
122740 #define TRDC_MRC_DOM15_RGD_NSE_BIT14(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT14_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT14_MASK)
122741 
122742 #define TRDC_MRC_DOM15_RGD_NSE_BIT15_MASK        (0x8000U)
122743 #define TRDC_MRC_DOM15_RGD_NSE_BIT15_SHIFT       (15U)
122744 /*! BIT15 - Bit n NonSecure Enable [n = 0 - 15]
122745  *  0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register
122746  *       (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed.
122747  *  0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
122748  *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
122749  */
122750 #define TRDC_MRC_DOM15_RGD_NSE_BIT15(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM15_RGD_NSE_BIT15_SHIFT)) & TRDC_MRC_DOM15_RGD_NSE_BIT15_MASK)
122751 /*! @} */
122752 
122753 /* The count of TRDC_MRC_DOM15_RGD_NSE */
122754 #define TRDC_MRC_DOM15_RGD_NSE_COUNT             (7U)
122755 
122756 
122757 /*!
122758  * @}
122759  */ /* end of group TRDC_Register_Masks */
122760 
122761 
122762 /* TRDC - Peripheral instance base addresses */
122763 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
122764   /** Peripheral TRDC1 base address */
122765   #define TRDC1_BASE                               (0x54270000u)
122766   /** Peripheral TRDC1 base address */
122767   #define TRDC1_BASE_NS                            (0x44270000u)
122768   /** Peripheral TRDC1 base pointer */
122769   #define TRDC1                                    ((TRDC_Type *)TRDC1_BASE)
122770   /** Peripheral TRDC1 base pointer */
122771   #define TRDC1_NS                                 ((TRDC_Type *)TRDC1_BASE_NS)
122772   /** Peripheral TRDC2 base address */
122773   #define TRDC2_BASE                               (0x52460000u)
122774   /** Peripheral TRDC2 base address */
122775   #define TRDC2_BASE_NS                            (0x42460000u)
122776   /** Peripheral TRDC2 base pointer */
122777   #define TRDC2                                    ((TRDC_Type *)TRDC2_BASE)
122778   /** Peripheral TRDC2 base pointer */
122779   #define TRDC2_NS                                 ((TRDC_Type *)TRDC2_BASE_NS)
122780   /** Peripheral TRDC3 base address */
122781   #define TRDC3_BASE                               (0x52810000u)
122782   /** Peripheral TRDC3 base address */
122783   #define TRDC3_BASE_NS                            (0x42810000u)
122784   /** Peripheral TRDC3 base pointer */
122785   #define TRDC3                                    ((TRDC_Type *)TRDC3_BASE)
122786   /** Peripheral TRDC3 base pointer */
122787   #define TRDC3_NS                                 ((TRDC_Type *)TRDC3_BASE_NS)
122788   /** Array initializer of TRDC peripheral base addresses */
122789   #define TRDC_BASE_ADDRS                          { 0u, TRDC1_BASE, TRDC2_BASE, TRDC3_BASE }
122790   /** Array initializer of TRDC peripheral base pointers */
122791   #define TRDC_BASE_PTRS                           { (TRDC_Type *)0u, TRDC1, TRDC2, TRDC3 }
122792   /** Array initializer of TRDC peripheral base addresses */
122793   #define TRDC_BASE_ADDRS_NS                       { 0u, TRDC1_BASE_NS, TRDC2_BASE_NS, TRDC3_BASE_NS }
122794   /** Array initializer of TRDC peripheral base pointers */
122795   #define TRDC_BASE_PTRS_NS                        { (TRDC_Type *)0u, TRDC1_NS, TRDC2_NS, TRDC3_NS }
122796 #else
122797   /** Peripheral TRDC1 base address */
122798   #define TRDC1_BASE                               (0x44270000u)
122799   /** Peripheral TRDC1 base pointer */
122800   #define TRDC1                                    ((TRDC_Type *)TRDC1_BASE)
122801   /** Peripheral TRDC2 base address */
122802   #define TRDC2_BASE                               (0x42460000u)
122803   /** Peripheral TRDC2 base pointer */
122804   #define TRDC2                                    ((TRDC_Type *)TRDC2_BASE)
122805   /** Peripheral TRDC3 base address */
122806   #define TRDC3_BASE                               (0x42810000u)
122807   /** Peripheral TRDC3 base pointer */
122808   #define TRDC3                                    ((TRDC_Type *)TRDC3_BASE)
122809   /** Array initializer of TRDC peripheral base addresses */
122810   #define TRDC_BASE_ADDRS                          { 0u, TRDC1_BASE, TRDC2_BASE, TRDC3_BASE }
122811   /** Array initializer of TRDC peripheral base pointers */
122812   #define TRDC_BASE_PTRS                           { (TRDC_Type *)0u, TRDC1, TRDC2, TRDC3 }
122813 #endif
122814 /** Interrupt vectors for the TRDC peripheral type */
122815 #define TRDC_IRQS                                { NotAvail_IRQn, TRDC_MGR_AON_IRQn, TRDC_MGR_WKUP_IRQn, TRDC_MGR_MEGA_IRQn }
122816 #define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1}
122817 #define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1}
122818 #define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1}
122819 #define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0}
122820 #define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT}
122821 #define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1}
122822 #define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1}
122823 #define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1}
122824 #define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0}
122825 #define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT}
122826 
122827 
122828 /*!
122829  * @}
122830  */ /* end of group TRDC_Peripheral_Access_Layer */
122831 
122832 
122833 /* ----------------------------------------------------------------------------
122834    -- TSTMR Peripheral Access Layer
122835    ---------------------------------------------------------------------------- */
122836 
122837 /*!
122838  * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
122839  * @{
122840  */
122841 
122842 /** TSTMR - Register Layout Typedef */
122843 typedef struct {
122844   __I  uint32_t L;                                 /**< Timestamp Timer Low, offset: 0x0 */
122845   __I  uint32_t H;                                 /**< Timestamp Timer High, offset: 0x4 */
122846 } TSTMR_Type;
122847 
122848 /* ----------------------------------------------------------------------------
122849    -- TSTMR Register Masks
122850    ---------------------------------------------------------------------------- */
122851 
122852 /*!
122853  * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
122854  * @{
122855  */
122856 
122857 /*! @name L - Timestamp Timer Low */
122858 /*! @{ */
122859 
122860 #define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
122861 #define TSTMR_L_VALUE_SHIFT                      (0U)
122862 /*! VALUE - Timestamp Timer Low */
122863 #define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
122864 /*! @} */
122865 
122866 /*! @name H - Timestamp Timer High */
122867 /*! @{ */
122868 
122869 #define TSTMR_H_VALUE_MASK                       (0xFFFFFFU)
122870 #define TSTMR_H_VALUE_SHIFT                      (0U)
122871 /*! VALUE - Timestamp Timer High */
122872 #define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
122873 /*! @} */
122874 
122875 
122876 /*!
122877  * @}
122878  */ /* end of group TSTMR_Register_Masks */
122879 
122880 
122881 /* TSTMR - Peripheral instance base addresses */
122882 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
122883   /** Peripheral TSTMR1_TSTMRA base address */
122884   #define TSTMR1_TSTMRA_BASE                       (0x542C0000u)
122885   /** Peripheral TSTMR1_TSTMRA base address */
122886   #define TSTMR1_TSTMRA_BASE_NS                    (0x442C0000u)
122887   /** Peripheral TSTMR1_TSTMRA base pointer */
122888   #define TSTMR1_TSTMRA                            ((TSTMR_Type *)TSTMR1_TSTMRA_BASE)
122889   /** Peripheral TSTMR1_TSTMRA base pointer */
122890   #define TSTMR1_TSTMRA_NS                         ((TSTMR_Type *)TSTMR1_TSTMRA_BASE_NS)
122891   /** Peripheral TSTMR2_TSTMRA base address */
122892   #define TSTMR2_TSTMRA_BASE                       (0x52480000u)
122893   /** Peripheral TSTMR2_TSTMRA base address */
122894   #define TSTMR2_TSTMRA_BASE_NS                    (0x42480000u)
122895   /** Peripheral TSTMR2_TSTMRA base pointer */
122896   #define TSTMR2_TSTMRA                            ((TSTMR_Type *)TSTMR2_TSTMRA_BASE)
122897   /** Peripheral TSTMR2_TSTMRA base pointer */
122898   #define TSTMR2_TSTMRA_NS                         ((TSTMR_Type *)TSTMR2_TSTMRA_BASE_NS)
122899   /** Array initializer of TSTMR peripheral base addresses */
122900   #define TSTMR_BASE_ADDRS                         { TSTMR1_TSTMRA_BASE, TSTMR2_TSTMRA_BASE }
122901   /** Array initializer of TSTMR peripheral base pointers */
122902   #define TSTMR_BASE_PTRS                          { TSTMR1_TSTMRA, TSTMR2_TSTMRA }
122903   /** Array initializer of TSTMR peripheral base addresses */
122904   #define TSTMR_BASE_ADDRS_NS                      { TSTMR1_TSTMRA_BASE_NS, TSTMR2_TSTMRA_BASE_NS }
122905   /** Array initializer of TSTMR peripheral base pointers */
122906   #define TSTMR_BASE_PTRS_NS                       { TSTMR1_TSTMRA_NS, TSTMR2_TSTMRA_NS }
122907 #else
122908   /** Peripheral TSTMR1_TSTMRA base address */
122909   #define TSTMR1_TSTMRA_BASE                       (0x442C0000u)
122910   /** Peripheral TSTMR1_TSTMRA base pointer */
122911   #define TSTMR1_TSTMRA                            ((TSTMR_Type *)TSTMR1_TSTMRA_BASE)
122912   /** Peripheral TSTMR2_TSTMRA base address */
122913   #define TSTMR2_TSTMRA_BASE                       (0x42480000u)
122914   /** Peripheral TSTMR2_TSTMRA base pointer */
122915   #define TSTMR2_TSTMRA                            ((TSTMR_Type *)TSTMR2_TSTMRA_BASE)
122916   /** Array initializer of TSTMR peripheral base addresses */
122917   #define TSTMR_BASE_ADDRS                         { TSTMR1_TSTMRA_BASE, TSTMR2_TSTMRA_BASE }
122918   /** Array initializer of TSTMR peripheral base pointers */
122919   #define TSTMR_BASE_PTRS                          { TSTMR1_TSTMRA, TSTMR2_TSTMRA }
122920 #endif
122921 /* Extra definition */
122922 #define TSTMR_CLOCK_FREQUENCY_MHZ                (24U)
122923 
122924 
122925 /*!
122926  * @}
122927  */ /* end of group TSTMR_Peripheral_Access_Layer */
122928 
122929 
122930 /* ----------------------------------------------------------------------------
122931    -- USBHSDCD Peripheral Access Layer
122932    ---------------------------------------------------------------------------- */
122933 
122934 /*!
122935  * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
122936  * @{
122937  */
122938 
122939 /** USBHSDCD - Register Layout Typedef */
122940 typedef struct {
122941   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
122942   __IO uint32_t CLOCK;                             /**< Clock, offset: 0x4 */
122943   __I  uint32_t STATUS;                            /**< Status, offset: 0x8 */
122944   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override, offset: 0xC */
122945   __IO uint32_t TIMER0;                            /**< TIMER0, offset: 0x10 */
122946   __IO uint32_t TIMER1;                            /**< TIMER1, offset: 0x14 */
122947   union {                                          /* offset: 0x18 */
122948     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11, offset: 0x18 */
122949     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12, offset: 0x18 */
122950   };
122951 } USBHSDCD_Type;
122952 
122953 /* ----------------------------------------------------------------------------
122954    -- USBHSDCD Register Masks
122955    ---------------------------------------------------------------------------- */
122956 
122957 /*!
122958  * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
122959  * @{
122960  */
122961 
122962 /*! @name CONTROL - Control */
122963 /*! @{ */
122964 
122965 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
122966 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
122967 /*! IACK - Interrupt Acknowledge
122968  *  0b0..Do not clear the interrupt.
122969  *  0b1..Clear the IF field (interrupt flag).
122970  */
122971 #define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
122972 
122973 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
122974 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
122975 /*! IF - Interrupt Flag
122976  *  0b0..No interrupt is pending.
122977  *  0b1..An interrupt is pending.
122978  */
122979 #define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
122980 
122981 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
122982 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
122983 /*! IE - Interrupt Enable
122984  *  0b0..Disable interrupts to the system.
122985  *  0b1..Enable interrupts to the system.
122986  */
122987 #define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
122988 
122989 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
122990 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
122991 /*! BC12 - Battery Charging Revision 1.2 Compatibility
122992  *  0b0..Compatible with BC1.1 (default)
122993  *  0b1..Compatible with BC1.2
122994  */
122995 #define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
122996 
122997 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
122998 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
122999 /*! START - Start Change Detection Sequence
123000  *  0b0..Do not start the sequence. Writes of this value have no effect.
123001  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
123002  */
123003 #define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
123004 
123005 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
123006 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
123007 /*! SR - Software Reset
123008  *  0b0..Do not perform a software reset.
123009  *  0b1..Perform a software reset.
123010  */
123011 #define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
123012 /*! @} */
123013 
123014 /*! @name CLOCK - Clock */
123015 /*! @{ */
123016 
123017 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
123018 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
123019 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
123020  *  0b0..kHz Speed (between 4 kHz and 1023 kHz)
123021  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
123022  */
123023 #define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
123024 
123025 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
123026 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
123027 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
123028 #define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
123029 /*! @} */
123030 
123031 /*! @name STATUS - Status */
123032 /*! @{ */
123033 
123034 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
123035 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
123036 /*! SEQ_RES - Charger Detection Sequence Results
123037  *  0b00..No results to report.
123038  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
123039  *  0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached
123040  *        to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The
123041  *        charger type detection has completed.)
123042  *  0b11..Attached to a DCP.
123043  */
123044 #define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
123045 
123046 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
123047 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
123048 /*! SEQ_STAT - Charger Detection Sequence Status
123049  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
123050  *  0b01..Data pin contact detection is complete.
123051  *  0b10..Charging port detection is complete.
123052  *  0b11..Charger type detection is complete.
123053  */
123054 #define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
123055 
123056 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
123057 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
123058 /*! ERR - Error Flag
123059  *  0b0..No sequence errors.
123060  *  0b1..Error in the detection sequence.
123061  */
123062 #define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
123063 
123064 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
123065 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
123066 /*! TO - Timeout Flag
123067  *  0b0..The detection sequence is not running for over 1 s.
123068  *  0b1..It is over 1 s since the data pin contact was detected and debounced.
123069  */
123070 #define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
123071 
123072 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
123073 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
123074 /*! ACTIVE - Active Status Indicator
123075  *  0b0..The sequence is not running.
123076  *  0b1..The sequence is running.
123077  */
123078 #define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
123079 /*! @} */
123080 
123081 /*! @name SIGNAL_OVERRIDE - Signal Override */
123082 /*! @{ */
123083 
123084 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
123085 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
123086 /*! PS - Phase Selection
123087  *  0b00..No overrides. Field must remain at this value during normal USB data communication to prevent unexpected
123088  *        conditions on USB_DP and USB_DM pins. (Default)
123089  *  0b01..Reserved, not for customer use.
123090  *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
123091  *  0b11..Reserved, not for customer use.
123092  */
123093 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
123094 /*! @} */
123095 
123096 /*! @name TIMER0 - TIMER0 */
123097 /*! @{ */
123098 
123099 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
123100 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
123101 /*! TUNITCON - Unit Connection Timer Elapse (in ms) */
123102 #define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
123103 
123104 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
123105 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
123106 /*! TSEQ_INIT - Sequence Initiation Time
123107  *  0b0000000000-0b1111111111..0 ms - 1023 ms
123108  */
123109 #define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
123110 /*! @} */
123111 
123112 /*! @name TIMER1 - TIMER1 */
123113 /*! @{ */
123114 
123115 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
123116 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
123117 /*! TVDPSRC_ON - Time Period Comparator Enabled
123118  *  0b0000000001-0b1111111111..1 ms - 1023 ms
123119  */
123120 #define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
123121 
123122 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
123123 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
123124 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
123125  *  0b0000000001-0b1111111111..1 ms - 1023 ms
123126  */
123127 #define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
123128 /*! @} */
123129 
123130 /*! @name TIMER2_BC11 - TIMER2_BC11 */
123131 /*! @{ */
123132 
123133 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
123134 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
123135 /*! CHECK_DM - Time Before Check of D- Line
123136  *  0b0001-0b1111..1 ms - 15 ms
123137  */
123138 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
123139 
123140 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
123141 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
123142 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
123143  *  0b0000000001-0b1111111111..1 ms - 1023 ms
123144  */
123145 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
123146 /*! @} */
123147 
123148 /*! @name TIMER2_BC12 - TIMER2_BC12 */
123149 /*! @{ */
123150 
123151 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
123152 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
123153 /*! TVDMSRC_ON - TVDMSRC_ON
123154  *  0b0000000000-0b0000101000..0 ms - 40 ms
123155  */
123156 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
123157 
123158 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
123159 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
123160 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
123161  *  0b0000000001-0b1111111111..1 ms - 1023 ms
123162  */
123163 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
123164 /*! @} */
123165 
123166 
123167 /*!
123168  * @}
123169  */ /* end of group USBHSDCD_Register_Masks */
123170 
123171 
123172 /* USBHSDCD - Peripheral instance base addresses */
123173 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
123174   /** Peripheral USBHSDCD1 base address */
123175   #define USBHSDCD1_BASE                           (0x52CA0800u)
123176   /** Peripheral USBHSDCD1 base address */
123177   #define USBHSDCD1_BASE_NS                        (0x42CA0800u)
123178   /** Peripheral USBHSDCD1 base pointer */
123179   #define USBHSDCD1                                ((USBHSDCD_Type *)USBHSDCD1_BASE)
123180   /** Peripheral USBHSDCD1 base pointer */
123181   #define USBHSDCD1_NS                             ((USBHSDCD_Type *)USBHSDCD1_BASE_NS)
123182   /** Peripheral USBHSDCD2 base address */
123183   #define USBHSDCD2_BASE                           (0x52CB0800u)
123184   /** Peripheral USBHSDCD2 base address */
123185   #define USBHSDCD2_BASE_NS                        (0x42CB0800u)
123186   /** Peripheral USBHSDCD2 base pointer */
123187   #define USBHSDCD2                                ((USBHSDCD_Type *)USBHSDCD2_BASE)
123188   /** Peripheral USBHSDCD2 base pointer */
123189   #define USBHSDCD2_NS                             ((USBHSDCD_Type *)USBHSDCD2_BASE_NS)
123190   /** Array initializer of USBHSDCD peripheral base addresses */
123191   #define USBHSDCD_BASE_ADDRS                      { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
123192   /** Array initializer of USBHSDCD peripheral base pointers */
123193   #define USBHSDCD_BASE_PTRS                       { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
123194   /** Array initializer of USBHSDCD peripheral base addresses */
123195   #define USBHSDCD_BASE_ADDRS_NS                   { 0u, USBHSDCD1_BASE_NS, USBHSDCD2_BASE_NS }
123196   /** Array initializer of USBHSDCD peripheral base pointers */
123197   #define USBHSDCD_BASE_PTRS_NS                    { (USBHSDCD_Type *)0u, USBHSDCD1_NS, USBHSDCD2_NS }
123198 #else
123199   /** Peripheral USBHSDCD1 base address */
123200   #define USBHSDCD1_BASE                           (0x42CA0800u)
123201   /** Peripheral USBHSDCD1 base pointer */
123202   #define USBHSDCD1                                ((USBHSDCD_Type *)USBHSDCD1_BASE)
123203   /** Peripheral USBHSDCD2 base address */
123204   #define USBHSDCD2_BASE                           (0x42CB0800u)
123205   /** Peripheral USBHSDCD2 base pointer */
123206   #define USBHSDCD2                                ((USBHSDCD_Type *)USBHSDCD2_BASE)
123207   /** Array initializer of USBHSDCD peripheral base addresses */
123208   #define USBHSDCD_BASE_ADDRS                      { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
123209   /** Array initializer of USBHSDCD peripheral base pointers */
123210   #define USBHSDCD_BASE_PTRS                       { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
123211 #endif
123212 /* Backward compatibility */
123213 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
123214 #define USBHSDCD_STACK_BASE_ADDRS               { USBHSDCD1_BASE, USBHSDCD2_BASE }
123215 #define USBHSDCD_STACK_BASE_ADDRS_NS            { USBHSDCD1_BASE_NS, USBHSDCD2_BASE_NS }
123216 #else
123217 #define USBHSDCD_STACK_BASE_ADDRS                { USBHSDCD1_BASE, USBHSDCD2_BASE }
123218 #endif
123219 
123220 
123221 /*!
123222  * @}
123223  */ /* end of group USBHSDCD_Peripheral_Access_Layer */
123224 
123225 
123226 /* ----------------------------------------------------------------------------
123227    -- USDHC Peripheral Access Layer
123228    ---------------------------------------------------------------------------- */
123229 
123230 /*!
123231  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
123232  * @{
123233  */
123234 
123235 /** USDHC - Register Layout Typedef */
123236 typedef struct {
123237   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
123238   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
123239   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
123240   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
123241   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
123242   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
123243   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
123244   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
123245   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
123246   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
123247   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
123248   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
123249   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
123250   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
123251   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
123252   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
123253   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
123254   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
123255   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
123256        uint8_t RESERVED_0[4];
123257   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
123258   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
123259   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
123260        uint8_t RESERVED_1[4];
123261   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
123262   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
123263   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
123264        uint8_t RESERVED_2[4];
123265   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
123266   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
123267        uint8_t RESERVED_3[72];
123268   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
123269   __IO uint32_t MMC_BOOT;                          /**< eMMC Boot, offset: 0xC4 */
123270   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
123271   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
123272        uint8_t RESERVED_4[48];
123273   __I  uint32_t CQVER;                             /**< Command Queuing Version, offset: 0x100 */
123274   __IO uint32_t CQCAP;                             /**< Command Queuing Capabilities, offset: 0x104 */
123275   __IO uint32_t CQCFG;                             /**< Command Queuing Configuration, offset: 0x108 */
123276   __IO uint32_t CQCTL;                             /**< Command Queuing Control, offset: 0x10C */
123277   __IO uint32_t CQIS;                              /**< Command Queuing Interrupt Status, offset: 0x110 */
123278   __IO uint32_t CQISTE;                            /**< Command Queuing Interrupt Status Enable, offset: 0x114 */
123279   __IO uint32_t CQISGE;                            /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */
123280   __IO uint32_t CQIC;                              /**< Command Queuing Interrupt Coalescing, offset: 0x11C */
123281   __IO uint32_t CQTDLBA;                           /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */
123282   __IO uint32_t CQTDLBAU;                          /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */
123283   __IO uint32_t CQTDBR;                            /**< Command Queuing Task Doorbell, offset: 0x128 */
123284   __IO uint32_t CQTCN;                             /**< Command Queuing Task Completion Notification, offset: 0x12C */
123285   __I  uint32_t CQDQS;                             /**< Command Queuing Device Queue Status, offset: 0x130 */
123286   __I  uint32_t CQDPT;                             /**< Command Queuing Device Pending Tasks, offset: 0x134 */
123287   __IO uint32_t CQTCLR;                            /**< Command Queuing Task Clear, offset: 0x138 */
123288        uint8_t RESERVED_5[4];
123289   __IO uint32_t CQSSC1;                            /**< Command Queuing Send Status Configuration 1, offset: 0x140 */
123290   __IO uint32_t CQSSC2;                            /**< Command Queuing Send Status Configuration 2, offset: 0x144 */
123291   __I  uint32_t CQCRDCT;                           /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */
123292        uint8_t RESERVED_6[4];
123293   __IO uint32_t CQRMEM;                            /**< Command Queuing Response Mode Error Mask, offset: 0x150 */
123294   __I  uint32_t CQTERRI;                           /**< Command Queuing Task Error Information, offset: 0x154 */
123295   __I  uint32_t CQCRI;                             /**< Command Queuing Command Response Index, offset: 0x158 */
123296   __I  uint32_t CQCRA;                             /**< Command Queuing Command Response Argument, offset: 0x15C */
123297 } USDHC_Type;
123298 
123299 /* ----------------------------------------------------------------------------
123300    -- USDHC Register Masks
123301    ---------------------------------------------------------------------------- */
123302 
123303 /*!
123304  * @addtogroup USDHC_Register_Masks USDHC Register Masks
123305  * @{
123306  */
123307 
123308 /*! @name DS_ADDR - DMA System Address */
123309 /*! @{ */
123310 
123311 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
123312 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
123313 /*! DS_ADDR - System address */
123314 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
123315 /*! @} */
123316 
123317 /*! @name BLK_ATT - Block Attributes */
123318 /*! @{ */
123319 
123320 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
123321 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
123322 /*! BLKSIZE - Transfer block size
123323  *  0b1000000000000..4096 bytes
123324  *  0b0100000000000..2048 bytes
123325  *  0b0001000000000..512 bytes
123326  *  0b0000111111111..511 bytes
123327  *  0b0000000000100..4 bytes
123328  *  0b0000000000011..3 bytes
123329  *  0b0000000000010..2 bytes
123330  *  0b0000000000001..1 byte
123331  *  0b0000000000000..No data transfer
123332  */
123333 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
123334 
123335 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
123336 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
123337 /*! BLKCNT - Blocks count for current transfer
123338  *  0b1111111111111111..65535 blocks
123339  *  0b0000000000000010..2 blocks
123340  *  0b0000000000000001..1 block
123341  *  0b0000000000000000..Stop count
123342  */
123343 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
123344 /*! @} */
123345 
123346 /*! @name CMD_ARG - Command Argument */
123347 /*! @{ */
123348 
123349 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
123350 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
123351 /*! CMDARG - Command argument */
123352 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
123353 /*! @} */
123354 
123355 /*! @name CMD_XFR_TYP - Command Transfer Type */
123356 /*! @{ */
123357 
123358 #define USDHC_CMD_XFR_TYP_DMAEN_MASK             (0x1U)
123359 #define USDHC_CMD_XFR_TYP_DMAEN_SHIFT            (0U)
123360 /*! DMAEN - DMAEN
123361  *  0b0..Disable
123362  *  0b1..Enable
123363  */
123364 #define USDHC_CMD_XFR_TYP_DMAEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK)
123365 
123366 #define USDHC_CMD_XFR_TYP_BCEN_MASK              (0x2U)
123367 #define USDHC_CMD_XFR_TYP_BCEN_SHIFT             (1U)
123368 /*! BCEN - BCEN
123369  *  0b0..Disable
123370  *  0b1..Enable
123371  */
123372 #define USDHC_CMD_XFR_TYP_BCEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK)
123373 
123374 #define USDHC_CMD_XFR_TYP_AC12EN_MASK            (0x4U)
123375 #define USDHC_CMD_XFR_TYP_AC12EN_SHIFT           (2U)
123376 /*! AC12EN - AC12EN
123377  *  0b0..Disable
123378  *  0b1..Enable
123379  */
123380 #define USDHC_CMD_XFR_TYP_AC12EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK)
123381 
123382 #define USDHC_CMD_XFR_TYP_DDR_EN_MASK            (0x8U)
123383 #define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT           (3U)
123384 /*! DDR_EN - DDR_EN
123385  *  0b0..Disable
123386  *  0b1..Enable
123387  */
123388 #define USDHC_CMD_XFR_TYP_DDR_EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK)
123389 
123390 #define USDHC_CMD_XFR_TYP_DTDSEL_MASK            (0x10U)
123391 #define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT           (4U)
123392 /*! DTDSEL - DTDSEL
123393  *  0b0..Disable
123394  *  0b1..Enable
123395  */
123396 #define USDHC_CMD_XFR_TYP_DTDSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK)
123397 
123398 #define USDHC_CMD_XFR_TYP_MSBSEL_MASK            (0x20U)
123399 #define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT           (5U)
123400 /*! MSBSEL - MSBSEL
123401  *  0b0..Disable
123402  *  0b1..Enable
123403  */
123404 #define USDHC_CMD_XFR_TYP_MSBSEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK)
123405 
123406 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK        (0x40U)
123407 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT       (6U)
123408 /*! NIBBLE_POS - NIBBLE_POS
123409  *  0b0..Disable
123410  *  0b1..Enable
123411  */
123412 #define USDHC_CMD_XFR_TYP_NIBBLE_POS(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK)
123413 
123414 #define USDHC_CMD_XFR_TYP_AC23EN_MASK            (0x80U)
123415 #define USDHC_CMD_XFR_TYP_AC23EN_SHIFT           (7U)
123416 /*! AC23EN - AC23EN
123417  *  0b0..Disable
123418  *  0b1..Enable
123419  */
123420 #define USDHC_CMD_XFR_TYP_AC23EN(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK)
123421 
123422 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
123423 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
123424 /*! RSPTYP - Response type select
123425  *  0b00..No response
123426  *  0b01..Response length 136
123427  *  0b10..Response length 48
123428  *  0b11..Response length 48, check busy after response
123429  */
123430 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
123431 
123432 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
123433 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
123434 /*! CCCEN - Command CRC check enable
123435  *  0b1..Enables command CRC check
123436  *  0b0..Disables command CRC check
123437  */
123438 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
123439 
123440 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
123441 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
123442 /*! CICEN - Command index check enable
123443  *  0b1..Enables command index check
123444  *  0b0..Disable command index check
123445  */
123446 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
123447 
123448 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
123449 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
123450 /*! DPSEL - Data present select
123451  *  0b1..Data present
123452  *  0b0..No data present
123453  */
123454 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
123455 
123456 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
123457 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
123458 /*! CMDTYP - Command type
123459  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
123460  *  0b10..Resume CMD52 for writing function select in CCCR
123461  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
123462  *  0b00..Normal other commands
123463  */
123464 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
123465 
123466 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
123467 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
123468 /*! CMDINX - Command index */
123469 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
123470 /*! @} */
123471 
123472 /*! @name CMD_RSP0 - Command Response0 */
123473 /*! @{ */
123474 
123475 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
123476 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
123477 /*! CMDRSP0 - Command response 0 */
123478 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
123479 /*! @} */
123480 
123481 /*! @name CMD_RSP1 - Command Response1 */
123482 /*! @{ */
123483 
123484 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
123485 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
123486 /*! CMDRSP1 - Command response 1 */
123487 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
123488 /*! @} */
123489 
123490 /*! @name CMD_RSP2 - Command Response2 */
123491 /*! @{ */
123492 
123493 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
123494 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
123495 /*! CMDRSP2 - Command response 2 */
123496 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
123497 /*! @} */
123498 
123499 /*! @name CMD_RSP3 - Command Response3 */
123500 /*! @{ */
123501 
123502 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
123503 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
123504 /*! CMDRSP3 - Command response 3 */
123505 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
123506 /*! @} */
123507 
123508 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
123509 /*! @{ */
123510 
123511 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
123512 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
123513 /*! DATCONT - Data content */
123514 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
123515 /*! @} */
123516 
123517 /*! @name PRES_STATE - Present State */
123518 /*! @{ */
123519 
123520 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
123521 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
123522 /*! CIHB - Command inhibit (CMD)
123523  *  0b1..Cannot issue command
123524  *  0b0..Can issue command using only CMD line
123525  */
123526 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
123527 
123528 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
123529 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
123530 /*! CDIHB - Command Inhibit Data (DATA)
123531  *  0b1..Cannot issue command that uses the DATA line
123532  *  0b0..Can issue command that uses the DATA line
123533  */
123534 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
123535 
123536 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
123537 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
123538 /*! DLA - Data line active
123539  *  0b1..DATA line active
123540  *  0b0..DATA line inactive
123541  */
123542 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
123543 
123544 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
123545 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
123546 /*! SDSTB - SD clock stable
123547  *  0b1..Clock is stable.
123548  *  0b0..Clock is changing frequency and not stable.
123549  */
123550 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
123551 
123552 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
123553 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
123554 /*! WTA - Write transfer active
123555  *  0b1..Transferring data
123556  *  0b0..No valid data
123557  */
123558 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
123559 
123560 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
123561 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
123562 /*! RTA - Read transfer active
123563  *  0b1..Transferring data
123564  *  0b0..No valid data
123565  */
123566 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
123567 
123568 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
123569 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
123570 /*! BWEN - Buffer write enable
123571  *  0b1..Write enable
123572  *  0b0..Write disable
123573  */
123574 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
123575 
123576 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
123577 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
123578 /*! BREN - Buffer read enable
123579  *  0b1..Read enable
123580  *  0b0..Read disable
123581  */
123582 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
123583 
123584 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
123585 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
123586 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode)
123587  *  0b1..Sampling clock needs re-tuning
123588  *  0b0..Fixed or well tuned sampling clock
123589  */
123590 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
123591 
123592 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
123593 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
123594 /*! TSCD - Tap select change done
123595  *  0b1..Delay cell select change is finished.
123596  *  0b0..Delay cell select change is not finished.
123597  */
123598 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
123599 
123600 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
123601 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
123602 /*! CINST - Card inserted
123603  *  0b1..Card inserted
123604  *  0b0..Power on reset or no card
123605  */
123606 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
123607 
123608 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
123609 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
123610 /*! CDPL - Card detect pin level
123611  *  0b1..Card present (CD_B = 0)
123612  *  0b0..No card present (CD_B = 1)
123613  */
123614 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
123615 
123616 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
123617 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
123618 /*! WPSPL - Write protect switch pin level
123619  *  0b1..Write enabled (WP = 0)
123620  *  0b0..Write protected (WP = 1)
123621  */
123622 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
123623 
123624 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
123625 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
123626 /*! CLSL - CMD line signal level */
123627 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
123628 
123629 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
123630 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
123631 /*! DLSL - DATA[7:0] line signal level
123632  *  0b00000111..Data 7 line signal level
123633  *  0b00000110..Data 6 line signal level
123634  *  0b00000101..Data 5 line signal level
123635  *  0b00000100..Data 4 line signal level
123636  *  0b00000011..Data 3 line signal level
123637  *  0b00000010..Data 2 line signal level
123638  *  0b00000001..Data 1 line signal level
123639  *  0b00000000..Data 0 line signal level
123640  */
123641 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
123642 /*! @} */
123643 
123644 /*! @name PROT_CTRL - Protocol Control */
123645 /*! @{ */
123646 
123647 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
123648 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
123649 /*! DTW - Data transfer width
123650  *  0b10..8-bit mode
123651  *  0b01..4-bit mode
123652  *  0b00..1-bit mode
123653  *  0b11..Reserved
123654  */
123655 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
123656 
123657 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
123658 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
123659 /*! D3CD - DATA3 as card detection pin
123660  *  0b1..DATA3 as card detection pin
123661  *  0b0..DATA3 does not monitor card insertion
123662  */
123663 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
123664 
123665 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
123666 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
123667 /*! EMODE - Endian mode
123668  *  0b00..Big endian mode
123669  *  0b01..Half word big endian mode
123670  *  0b10..Little endian mode
123671  *  0b11..Reserved
123672  */
123673 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
123674 
123675 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
123676 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
123677 /*! DMASEL - DMA select
123678  *  0b00..No DMA or simple DMA is selected.
123679  *  0b01..ADMA1 is selected.
123680  *  0b10..ADMA2 is selected.
123681  *  0b11..Reserved
123682  */
123683 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
123684 
123685 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
123686 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
123687 /*! SABGREQ - Stop at block gap request
123688  *  0b1..Stop
123689  *  0b0..Transfer
123690  */
123691 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
123692 
123693 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
123694 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
123695 /*! CREQ - Continue request
123696  *  0b1..Restart
123697  *  0b0..No effect
123698  */
123699 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
123700 
123701 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
123702 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
123703 /*! RWCTL - Read wait control
123704  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
123705  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
123706  */
123707 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
123708 
123709 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
123710 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
123711 /*! IABG - Interrupt at block gap
123712  *  0b1..Enables interrupt at block gap
123713  *  0b0..Disables interrupt at block gap
123714  */
123715 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
123716 
123717 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
123718 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
123719 /*! RD_DONE_NO_8CLK - Read performed number 8 clock */
123720 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
123721 
123722 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
123723 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
123724 /*! WECINT - Wakeup event enable on card interrupt
123725  *  0b1..Enables wakeup event enable on card interrupt
123726  *  0b0..Disables wakeup event enable on card interrupt
123727  */
123728 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
123729 
123730 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
123731 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
123732 /*! WECINS - Wakeup event enable on SD card insertion
123733  *  0b1..Enable wakeup event enable on SD card insertion
123734  *  0b0..Disable wakeup event enable on SD card insertion
123735  */
123736 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
123737 
123738 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
123739 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
123740 /*! WECRM - Wakeup event enable on SD card removal
123741  *  0b1..Enables wakeup event enable on SD card removal
123742  *  0b0..Disables wakeup event enable on SD card removal
123743  */
123744 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
123745 
123746 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
123747 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
123748 /*! NON_EXACT_BLK_RD - Non-exact block read
123749  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
123750  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
123751  */
123752 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
123753 /*! @} */
123754 
123755 /*! @name SYS_CTRL - System Control */
123756 /*! @{ */
123757 
123758 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
123759 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
123760 /*! DVS - Divisor
123761  *  0b0000..Divide-by-1
123762  *  0b0001..Divide-by-2
123763  *  0b1110..Divide-by-15
123764  *  0b1111..Divide-by-16
123765  */
123766 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
123767 
123768 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
123769 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
123770 /*! SDCLKFS - SDCLK frequency select */
123771 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
123772 
123773 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
123774 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
123775 /*! DTOCV - Data timeout counter value
123776  *  0b1111..SDCLK x 2 31, recommend to use for HS400 mode
123777  *  0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode
123778  *  0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode
123779  *  0b0011..SDCLK x 2 19
123780  *  0b0010..SDCLK x 2 18
123781  *  0b0001..SDCLK x 2 33
123782  *  0b0000..SDCLK x 2 32
123783  */
123784 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
123785 
123786 #define USDHC_SYS_CTRL_RST_FIFO_MASK             (0x400000U)
123787 #define USDHC_SYS_CTRL_RST_FIFO_SHIFT            (22U)
123788 /*! RST_FIFO - Reset the async FIFO */
123789 #define USDHC_SYS_CTRL_RST_FIFO(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK)
123790 
123791 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
123792 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
123793 /*! IPP_RST_N - Hardware reset */
123794 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
123795 
123796 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
123797 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
123798 /*! RSTA - Software reset for all
123799  *  0b1..Reset
123800  *  0b0..No reset
123801  */
123802 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
123803 
123804 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
123805 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
123806 /*! RSTC - Software reset for CMD line
123807  *  0b1..Reset
123808  *  0b0..No reset
123809  */
123810 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
123811 
123812 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
123813 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
123814 /*! RSTD - Software reset for data line
123815  *  0b1..Reset
123816  *  0b0..No reset
123817  */
123818 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
123819 
123820 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
123821 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
123822 /*! INITA - Initialization active */
123823 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
123824 
123825 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
123826 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
123827 /*! RSTT - Reset tuning */
123828 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
123829 /*! @} */
123830 
123831 /*! @name INT_STATUS - Interrupt Status */
123832 /*! @{ */
123833 
123834 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
123835 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
123836 /*! CC - Command complete
123837  *  0b1..Command complete
123838  *  0b0..Command not complete
123839  */
123840 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
123841 
123842 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
123843 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
123844 /*! TC - Transfer complete
123845  *  0b1..Transfer complete
123846  *  0b0..Transfer does not complete
123847  */
123848 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
123849 
123850 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
123851 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
123852 /*! BGE - Block gap event
123853  *  0b1..Transaction stopped at block gap
123854  *  0b0..No block gap event
123855  */
123856 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
123857 
123858 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
123859 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
123860 /*! DINT - DMA interrupt
123861  *  0b1..DMA interrupt is generated.
123862  *  0b0..No DMA interrupt
123863  */
123864 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
123865 
123866 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
123867 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
123868 /*! BWR - Buffer write ready
123869  *  0b1..Ready to write buffer
123870  *  0b0..Not ready to write buffer
123871  */
123872 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
123873 
123874 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
123875 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
123876 /*! BRR - Buffer read ready
123877  *  0b1..Ready to read buffer
123878  *  0b0..Not ready to read buffer
123879  */
123880 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
123881 
123882 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
123883 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
123884 /*! CINS - Card insertion
123885  *  0b1..Card inserted
123886  *  0b0..Card state unstable or removed
123887  */
123888 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
123889 
123890 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
123891 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
123892 /*! CRM - Card removal
123893  *  0b1..Card removed
123894  *  0b0..Card state unstable or inserted
123895  */
123896 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
123897 
123898 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
123899 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
123900 /*! CINT - Card interrupt
123901  *  0b1..Generate card interrupt
123902  *  0b0..No card interrupt
123903  */
123904 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
123905 
123906 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
123907 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
123908 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode)
123909  *  0b1..Re-tuning should be performed.
123910  *  0b0..Re-tuning is not required.
123911  */
123912 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
123913 
123914 #define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
123915 #define USDHC_INT_STATUS_TP_SHIFT                (13U)
123916 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */
123917 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
123918 
123919 #define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
123920 #define USDHC_INT_STATUS_CQI_SHIFT               (14U)
123921 /*! CQI - Command queuing interrupt */
123922 #define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)
123923 
123924 #define USDHC_INT_STATUS_ERR_INT_STATUS_MASK     (0x8000U)
123925 #define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT    (15U)
123926 /*! ERR_INT_STATUS - Error Interrupt Status */
123927 #define USDHC_INT_STATUS_ERR_INT_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK)
123928 
123929 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
123930 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
123931 /*! CTOE - Command timeout error
123932  *  0b1..Time out
123933  *  0b0..No error
123934  */
123935 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
123936 
123937 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
123938 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
123939 /*! CCE - Command CRC error
123940  *  0b1..CRC error generated
123941  *  0b0..No error
123942  */
123943 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
123944 
123945 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
123946 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
123947 /*! CEBE - Command end bit error
123948  *  0b1..End bit error generated
123949  *  0b0..No error
123950  */
123951 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
123952 
123953 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
123954 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
123955 /*! CIE - Command index error
123956  *  0b1..Error
123957  *  0b0..No error
123958  */
123959 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
123960 
123961 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
123962 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
123963 /*! DTOE - Data timeout error
123964  *  0b1..Time out
123965  *  0b0..No error
123966  */
123967 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
123968 
123969 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
123970 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
123971 /*! DCE - Data CRC error
123972  *  0b1..Error
123973  *  0b0..No error
123974  */
123975 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
123976 
123977 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
123978 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
123979 /*! DEBE - Data end bit error
123980  *  0b1..Error
123981  *  0b0..No error
123982  */
123983 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
123984 
123985 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
123986 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
123987 /*! AC12E - Auto CMD12 error
123988  *  0b1..Error
123989  *  0b0..No error
123990  */
123991 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
123992 
123993 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
123994 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
123995 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */
123996 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
123997 
123998 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
123999 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
124000 /*! DMAE - DMA error
124001  *  0b1..Error
124002  *  0b0..No error
124003  */
124004 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
124005 /*! @} */
124006 
124007 /*! @name INT_STATUS_EN - Interrupt Status Enable */
124008 /*! @{ */
124009 
124010 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
124011 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
124012 /*! CCSEN - Command complete status enable
124013  *  0b1..Enabled
124014  *  0b0..Masked
124015  */
124016 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
124017 
124018 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
124019 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
124020 /*! TCSEN - Transfer complete status enable
124021  *  0b1..Enabled
124022  *  0b0..Masked
124023  */
124024 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
124025 
124026 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
124027 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
124028 /*! BGESEN - Block gap event status enable
124029  *  0b1..Enabled
124030  *  0b0..Masked
124031  */
124032 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
124033 
124034 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
124035 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
124036 /*! DINTSEN - DMA interrupt status enable
124037  *  0b1..Enabled
124038  *  0b0..Masked
124039  */
124040 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
124041 
124042 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
124043 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
124044 /*! BWRSEN - Buffer write ready status enable
124045  *  0b1..Enabled
124046  *  0b0..Masked
124047  */
124048 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
124049 
124050 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
124051 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
124052 /*! BRRSEN - Buffer read ready status enable
124053  *  0b1..Enabled
124054  *  0b0..Masked
124055  */
124056 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
124057 
124058 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
124059 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
124060 /*! CINSSEN - Card insertion status enable
124061  *  0b1..Enabled
124062  *  0b0..Masked
124063  */
124064 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
124065 
124066 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
124067 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
124068 /*! CRMSEN - Card removal status enable
124069  *  0b1..Enabled
124070  *  0b0..Masked
124071  */
124072 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
124073 
124074 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
124075 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
124076 /*! CINTSEN - Card interrupt status enable
124077  *  0b1..Enabled
124078  *  0b0..Masked
124079  */
124080 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
124081 
124082 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
124083 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
124084 /*! RTESEN - Re-tuning event status enable
124085  *  0b1..Enabled
124086  *  0b0..Masked
124087  */
124088 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
124089 
124090 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
124091 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
124092 /*! TPSEN - Tuning pass status enable
124093  *  0b1..Enabled
124094  *  0b0..Masked
124095  */
124096 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
124097 
124098 #define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
124099 #define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
124100 /*! CQISEN - Command queuing status enable
124101  *  0b1..Enabled
124102  *  0b0..Masked
124103  */
124104 #define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)
124105 
124106 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
124107 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
124108 /*! CTOESEN - Command timeout error status enable
124109  *  0b1..Enabled
124110  *  0b0..Masked
124111  */
124112 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
124113 
124114 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
124115 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
124116 /*! CCESEN - Command CRC error status enable
124117  *  0b1..Enabled
124118  *  0b0..Masked
124119  */
124120 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
124121 
124122 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
124123 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
124124 /*! CEBESEN - Command end bit error status enable
124125  *  0b1..Enabled
124126  *  0b0..Masked
124127  */
124128 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
124129 
124130 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
124131 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
124132 /*! CIESEN - Command index error status enable
124133  *  0b1..Enabled
124134  *  0b0..Masked
124135  */
124136 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
124137 
124138 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
124139 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
124140 /*! DTOESEN - Data timeout error status enable
124141  *  0b1..Enabled
124142  *  0b0..Masked
124143  */
124144 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
124145 
124146 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
124147 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
124148 /*! DCESEN - Data CRC error status enable
124149  *  0b1..Enabled
124150  *  0b0..Masked
124151  */
124152 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
124153 
124154 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
124155 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
124156 /*! DEBESEN - Data end bit error status enable
124157  *  0b1..Enabled
124158  *  0b0..Masked
124159  */
124160 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
124161 
124162 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
124163 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
124164 /*! AC12ESEN - Auto CMD12 error status enable
124165  *  0b1..Enabled
124166  *  0b0..Masked
124167  */
124168 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
124169 
124170 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
124171 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
124172 /*! TNESEN - Tuning error status enable
124173  *  0b1..Enabled
124174  *  0b0..Masked
124175  */
124176 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
124177 
124178 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
124179 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
124180 /*! DMAESEN - DMA error status enable
124181  *  0b1..Enabled
124182  *  0b0..Masked
124183  */
124184 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
124185 /*! @} */
124186 
124187 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
124188 /*! @{ */
124189 
124190 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
124191 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
124192 /*! CCIEN - Command complete interrupt enable
124193  *  0b1..Enabled
124194  *  0b0..Masked
124195  */
124196 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
124197 
124198 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
124199 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
124200 /*! TCIEN - Transfer complete interrupt enable
124201  *  0b1..Enabled
124202  *  0b0..Masked
124203  */
124204 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
124205 
124206 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
124207 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
124208 /*! BGEIEN - Block gap event interrupt enable
124209  *  0b1..Enabled
124210  *  0b0..Masked
124211  */
124212 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
124213 
124214 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
124215 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
124216 /*! DINTIEN - DMA interrupt enable
124217  *  0b1..Enabled
124218  *  0b0..Masked
124219  */
124220 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
124221 
124222 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
124223 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
124224 /*! BWRIEN - Buffer write ready interrupt enable
124225  *  0b1..Enabled
124226  *  0b0..Masked
124227  */
124228 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
124229 
124230 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
124231 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
124232 /*! BRRIEN - Buffer read ready interrupt enable
124233  *  0b1..Enabled
124234  *  0b0..Masked
124235  */
124236 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
124237 
124238 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
124239 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
124240 /*! CINSIEN - Card insertion interrupt enable
124241  *  0b1..Enabled
124242  *  0b0..Masked
124243  */
124244 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
124245 
124246 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
124247 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
124248 /*! CRMIEN - Card removal interrupt enable
124249  *  0b1..Enabled
124250  *  0b0..Masked
124251  */
124252 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
124253 
124254 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
124255 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
124256 /*! CINTIEN - Card interrupt enable
124257  *  0b1..Enabled
124258  *  0b0..Masked
124259  */
124260 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
124261 
124262 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
124263 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
124264 /*! RTEIEN - Re-tuning event interrupt enable
124265  *  0b1..Enabled
124266  *  0b0..Masked
124267  */
124268 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
124269 
124270 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
124271 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
124272 /*! TPIEN - Tuning pass interrupt enable
124273  *  0b1..Enabled
124274  *  0b0..Masked
124275  */
124276 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
124277 
124278 #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
124279 #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
124280 /*! CQIIEN - Command queuing signal enable
124281  *  0b1..Enabled
124282  *  0b0..Masked
124283  */
124284 #define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)
124285 
124286 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
124287 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
124288 /*! CTOEIEN - Command timeout error interrupt enable
124289  *  0b1..Enabled
124290  *  0b0..Masked
124291  */
124292 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
124293 
124294 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
124295 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
124296 /*! CCEIEN - Command CRC error interrupt enable
124297  *  0b1..Enabled
124298  *  0b0..Masked
124299  */
124300 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
124301 
124302 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
124303 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
124304 /*! CEBEIEN - Command end bit error interrupt enable
124305  *  0b1..Enabled
124306  *  0b0..Masked
124307  */
124308 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
124309 
124310 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
124311 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
124312 /*! CIEIEN - Command index error interrupt enable
124313  *  0b1..Enabled
124314  *  0b0..Masked
124315  */
124316 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
124317 
124318 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
124319 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
124320 /*! DTOEIEN - Data timeout error interrupt enable
124321  *  0b1..Enabled
124322  *  0b0..Masked
124323  */
124324 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
124325 
124326 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
124327 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
124328 /*! DCEIEN - Data CRC error interrupt enable
124329  *  0b1..Enabled
124330  *  0b0..Masked
124331  */
124332 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
124333 
124334 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
124335 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
124336 /*! DEBEIEN - Data end bit error interrupt enable
124337  *  0b1..Enabled
124338  *  0b0..Masked
124339  */
124340 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
124341 
124342 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
124343 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
124344 /*! AC12EIEN - Auto CMD12 error interrupt enable
124345  *  0b1..Enabled
124346  *  0b0..Masked
124347  */
124348 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
124349 
124350 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
124351 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
124352 /*! TNEIEN - Tuning error interrupt enable
124353  *  0b1..Enabled
124354  *  0b0..Masked
124355  */
124356 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
124357 
124358 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
124359 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
124360 /*! DMAEIEN - DMA error interrupt enable
124361  *  0b1..Enable
124362  *  0b0..Masked
124363  */
124364 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
124365 /*! @} */
124366 
124367 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
124368 /*! @{ */
124369 
124370 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
124371 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
124372 /*! AC12NE - Auto CMD12 not executed
124373  *  0b1..Not executed
124374  *  0b0..Executed
124375  */
124376 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
124377 
124378 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
124379 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
124380 /*! AC12TOE - Auto CMD12 / 23 timeout error
124381  *  0b1..Time out
124382  *  0b0..No error
124383  */
124384 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
124385 
124386 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x4U)
124387 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (2U)
124388 /*! AC12CE - Auto CMD12 / 23 CRC error
124389  *  0b1..CRC error met in Auto CMD12/23 response
124390  *  0b0..No CRC error
124391  */
124392 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
124393 
124394 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x8U)
124395 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U)
124396 /*! AC12EBE - Auto CMD12 / 23 end bit error
124397  *  0b1..End bit error generated
124398  *  0b0..No error
124399  */
124400 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
124401 
124402 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
124403 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
124404 /*! AC12IE - Auto CMD12 / 23 index error
124405  *  0b1..Error, the CMD index in response is not CMD12/23
124406  *  0b0..No error
124407  */
124408 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
124409 
124410 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
124411 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
124412 /*! CNIBAC12E - Command not issued by Auto CMD12 error
124413  *  0b1..Not issued
124414  *  0b0..No error
124415  */
124416 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
124417 
124418 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
124419 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
124420 /*! EXECUTE_TUNING - Execute tuning
124421  *  0b1..Start tuning procedure
124422  *  0b0..Tuning procedure is aborted
124423  */
124424 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
124425 
124426 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
124427 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
124428 /*! SMP_CLK_SEL - Sample clock select
124429  *  0b1..Tuned clock is used to sample data
124430  *  0b0..Fixed clock is used to sample data
124431  */
124432 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
124433 /*! @} */
124434 
124435 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
124436 /*! @{ */
124437 
124438 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
124439 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
124440 /*! SDR50_SUPPORT - SDR50 support */
124441 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
124442 
124443 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
124444 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
124445 /*! SDR104_SUPPORT - SDR104 support */
124446 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
124447 
124448 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
124449 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
124450 /*! DDR50_SUPPORT - DDR50 support */
124451 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
124452 
124453 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
124454 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
124455 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
124456  *  0b1..SDR50 supports tuning
124457  *  0b0..SDR50 does not support tuning
124458  */
124459 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
124460 
124461 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
124462 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
124463 /*! MBL - Max block length
124464  *  0b000..512 bytes
124465  *  0b001..1024 bytes
124466  *  0b010..2048 bytes
124467  *  0b011..4096 bytes
124468  */
124469 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
124470 
124471 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
124472 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
124473 /*! ADMAS - ADMA support
124474  *  0b1..Advanced DMA supported
124475  *  0b0..Advanced DMA not supported
124476  */
124477 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
124478 
124479 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
124480 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
124481 /*! HSS - High speed support
124482  *  0b1..High speed supported
124483  *  0b0..High speed not supported
124484  */
124485 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
124486 
124487 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
124488 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
124489 /*! DMAS - DMA support
124490  *  0b1..DMA supported
124491  *  0b0..DMA not supported
124492  */
124493 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
124494 
124495 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
124496 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
124497 /*! SRS - Suspend / resume support
124498  *  0b1..Supported
124499  *  0b0..Not supported
124500  */
124501 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
124502 
124503 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
124504 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
124505 /*! VS33 - Voltage support 3.3 V
124506  *  0b1..3.3 V supported
124507  *  0b0..3.3 V not supported
124508  */
124509 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
124510 
124511 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
124512 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
124513 /*! VS30 - Voltage support 3.0 V
124514  *  0b1..3.0 V supported
124515  *  0b0..3.0 V not supported
124516  */
124517 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
124518 
124519 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
124520 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
124521 /*! VS18 - Voltage support 1.8 V
124522  *  0b1..1.8 V supported
124523  *  0b0..1.8 V not supported
124524  */
124525 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
124526 /*! @} */
124527 
124528 /*! @name WTMK_LVL - Watermark Level */
124529 /*! @{ */
124530 
124531 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
124532 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
124533 /*! RD_WML - Read watermark level */
124534 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
124535 
124536 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
124537 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
124538 /*! WR_WML - Write watermark level */
124539 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
124540 /*! @} */
124541 
124542 /*! @name MIX_CTRL - Mixer Control */
124543 /*! @{ */
124544 
124545 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
124546 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
124547 /*! DMAEN - DMA enable
124548  *  0b1..Enable
124549  *  0b0..Disable
124550  */
124551 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
124552 
124553 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
124554 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
124555 /*! BCEN - Block count enable
124556  *  0b1..Enable
124557  *  0b0..Disable
124558  */
124559 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
124560 
124561 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
124562 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
124563 /*! AC12EN - Auto CMD12 enable
124564  *  0b1..Enable
124565  *  0b0..Disable
124566  */
124567 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
124568 
124569 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
124570 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
124571 /*! DDR_EN - Dual data rate mode selection */
124572 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
124573 
124574 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
124575 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
124576 /*! DTDSEL - Data transfer direction select
124577  *  0b1..Read (Card to host)
124578  *  0b0..Write (Host to card)
124579  */
124580 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
124581 
124582 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
124583 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
124584 /*! MSBSEL - Multi / Single block select
124585  *  0b1..Multiple blocks
124586  *  0b0..Single block
124587  */
124588 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
124589 
124590 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
124591 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
124592 /*! NIBBLE_POS - Nibble position indication */
124593 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
124594 
124595 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
124596 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
124597 /*! AC23EN - Auto CMD23 enable */
124598 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
124599 
124600 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
124601 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
124602 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
124603  *  0b1..Execute tuning
124604  *  0b0..Not tuned or tuning completed
124605  */
124606 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
124607 
124608 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
124609 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
124610 /*! SMP_CLK_SEL - Clock selection
124611  *  0b1..Tuned clock is used to sample data / cmd
124612  *  0b0..Fixed clock is used to sample data / cmd
124613  */
124614 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
124615 
124616 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
124617 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
124618 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
124619  *  0b1..Enable auto tuning
124620  *  0b0..Disable auto tuning
124621  */
124622 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
124623 
124624 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
124625 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
124626 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode)
124627  *  0b1..Feedback clock comes from the ipp_card_clk_out
124628  *  0b0..Feedback clock comes from the loopback CLK
124629  */
124630 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
124631 
124632 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
124633 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
124634 /*! HS400_MODE - Enable HS400 mode */
124635 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
124636 
124637 #define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
124638 #define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
124639 /*! EN_HS400_MODE - Enable enhance HS400 mode */
124640 #define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
124641 /*! @} */
124642 
124643 /*! @name FORCE_EVENT - Force Event */
124644 /*! @{ */
124645 
124646 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
124647 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
124648 /*! FEVTAC12NE - Force event auto command 12 not executed */
124649 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
124650 
124651 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
124652 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
124653 /*! FEVTAC12TOE - Force event auto command 12 time out error */
124654 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
124655 
124656 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
124657 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
124658 /*! FEVTAC12CE - Force event auto command 12 CRC error */
124659 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
124660 
124661 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
124662 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
124663 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
124664 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
124665 
124666 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
124667 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
124668 /*! FEVTAC12IE - Force event Auto Command 12 index error */
124669 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
124670 
124671 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
124672 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
124673 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
124674 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
124675 
124676 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
124677 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
124678 /*! FEVTCTOE - Force event command time out error */
124679 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
124680 
124681 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
124682 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
124683 /*! FEVTCCE - Force event command CRC error */
124684 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
124685 
124686 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
124687 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
124688 /*! FEVTCEBE - Force event command end bit error */
124689 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
124690 
124691 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
124692 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
124693 /*! FEVTCIE - Force event command index error */
124694 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
124695 
124696 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
124697 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
124698 /*! FEVTDTOE - Force event data time out error */
124699 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
124700 
124701 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
124702 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
124703 /*! FEVTDCE - Force event data CRC error */
124704 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
124705 
124706 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
124707 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
124708 /*! FEVTDEBE - Force event data end bit error */
124709 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
124710 
124711 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
124712 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
124713 /*! FEVTAC12E - Force event Auto Command 12 error */
124714 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
124715 
124716 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
124717 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
124718 /*! FEVTTNE - Force tuning error */
124719 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
124720 
124721 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
124722 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
124723 /*! FEVTDMAE - Force event DMA error */
124724 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
124725 
124726 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
124727 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
124728 /*! FEVTCINT - Force event card interrupt */
124729 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
124730 /*! @} */
124731 
124732 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
124733 /*! @{ */
124734 
124735 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
124736 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
124737 /*! ADMAES - ADMA error state (when ADMA error is occurred) */
124738 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
124739 
124740 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
124741 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
124742 /*! ADMALME - ADMA length mismatch error
124743  *  0b1..Error
124744  *  0b0..No error
124745  */
124746 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
124747 
124748 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
124749 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
124750 /*! ADMADCE - ADMA descriptor error
124751  *  0b1..Error
124752  *  0b0..No error
124753  */
124754 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
124755 /*! @} */
124756 
124757 /*! @name ADMA_SYS_ADDR - ADMA System Address */
124758 /*! @{ */
124759 
124760 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
124761 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
124762 /*! ADS_ADDR - ADMA system address */
124763 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
124764 /*! @} */
124765 
124766 /*! @name DLL_CTRL - DLL (Delay Line) Control */
124767 /*! @{ */
124768 
124769 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
124770 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
124771 /*! DLL_CTRL_ENABLE - DLL and delay chain */
124772 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
124773 
124774 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
124775 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
124776 /*! DLL_CTRL_RESET - DLL reset */
124777 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
124778 
124779 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
124780 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
124781 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
124782 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
124783 
124784 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
124785 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
124786 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
124787 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
124788 
124789 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
124790 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
124791 /*! DLL_CTRL_GATE_UPDATE - DLL gate update */
124792 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
124793 
124794 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
124795 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
124796 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
124797 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
124798 
124799 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
124800 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
124801 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
124802 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
124803 
124804 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
124805 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
124806 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
124807 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
124808 
124809 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
124810 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
124811 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
124812 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
124813 
124814 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
124815 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
124816 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
124817 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
124818 /*! @} */
124819 
124820 /*! @name DLL_STATUS - DLL Status */
124821 /*! @{ */
124822 
124823 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
124824 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
124825 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
124826 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
124827 
124828 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
124829 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
124830 /*! DLL_STS_REF_LOCK - Reference DLL lock status */
124831 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
124832 
124833 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
124834 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
124835 /*! DLL_STS_SLV_SEL - Slave delay line select status */
124836 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
124837 
124838 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
124839 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
124840 /*! DLL_STS_REF_SEL - Reference delay line select taps */
124841 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
124842 /*! @} */
124843 
124844 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
124845 /*! @{ */
124846 
124847 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
124848 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
124849 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
124850 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
124851 
124852 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
124853 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
124854 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
124855 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
124856 
124857 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
124858 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
124859 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
124860 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
124861 
124862 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
124863 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
124864 /*! NXT_ERR - NXT error */
124865 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
124866 
124867 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
124868 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
124869 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
124870 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
124871 
124872 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
124873 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
124874 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
124875 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
124876 
124877 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
124878 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
124879 /*! TAP_SEL_PRE - TAP_SEL_PRE */
124880 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
124881 
124882 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
124883 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
124884 /*! PRE_ERR - PRE error */
124885 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
124886 /*! @} */
124887 
124888 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
124889 /*! @{ */
124890 
124891 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
124892 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
124893 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */
124894 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
124895 
124896 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
124897 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
124898 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */
124899 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
124900 
124901 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
124902 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
124903 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */
124904 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
124905 
124906 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
124907 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
124908 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */
124909 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
124910 
124911 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
124912 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
124913 /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */
124914 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
124915 
124916 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
124917 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
124918 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */
124919 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
124920 
124921 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
124922 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
124923 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */
124924 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
124925 
124926 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
124927 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
124928 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */
124929 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
124930 
124931 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
124932 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
124933 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */
124934 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
124935 /*! @} */
124936 
124937 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
124938 /*! @{ */
124939 
124940 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
124941 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
124942 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */
124943 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
124944 
124945 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
124946 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
124947 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */
124948 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
124949 
124950 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
124951 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
124952 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */
124953 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
124954 
124955 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
124956 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
124957 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */
124958 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
124959 /*! @} */
124960 
124961 /*! @name VEND_SPEC - Vendor Specific Register */
124962 /*! @{ */
124963 
124964 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
124965 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
124966 /*! VSELECT - Voltage selection
124967  *  0b1..Change the voltage to low voltage range , around 1.8 V
124968  *  0b0..Change the voltage to high voltage range, around 3.0 V
124969  */
124970 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
124971 
124972 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
124973 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
124974 /*! AC12_WR_CHKBUSY_EN - Check busy enable
124975  *  0b0..Do not check busy after auto CMD12 for write data packet
124976  *  0b1..Check busy after auto CMD12 for write data packet
124977  */
124978 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
124979 
124980 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
124981 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
124982 /*! FRC_SDCLK_ON - Force CLK
124983  *  0b0..CLK active or inactive is fully controlled by the hardware.
124984  *  0b1..Force CLK active
124985  */
124986 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
124987 
124988 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
124989 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
124990 /*! CRC_CHK_DIS - CRC Check Disable
124991  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
124992  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
124993  */
124994 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
124995 
124996 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
124997 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
124998 /*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP
124999  *  0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only.
125000  *  0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write.
125001  */
125002 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
125003 /*! @} */
125004 
125005 /*! @name MMC_BOOT - eMMC Boot */
125006 /*! @{ */
125007 
125008 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
125009 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
125010 /*! DTOCV_ACK - DTOCV_ACK
125011  *  0b0000..SDCLK x 2^32
125012  *  0b0001..SDCLK x 2^33
125013  *  0b0010..SDCLK x 2^18
125014  *  0b0011..SDCLK x 2^19
125015  *  0b0100..SDCLK x 2^20
125016  *  0b0101..SDCLK x 2^21
125017  *  0b0110..SDCLK x 2^22
125018  *  0b0111..SDCLK x 2^23
125019  *  0b1110..SDCLK x 2^30
125020  *  0b1111..SDCLK x 2^31
125021  */
125022 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
125023 
125024 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
125025 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
125026 /*! BOOT_ACK - BOOT ACK
125027  *  0b0..No ack
125028  *  0b1..Ack
125029  */
125030 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
125031 
125032 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
125033 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
125034 /*! BOOT_MODE - Boot mode
125035  *  0b0..Normal boot
125036  *  0b1..Alternative boot
125037  */
125038 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
125039 
125040 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
125041 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
125042 /*! BOOT_EN - Boot enable
125043  *  0b0..Fast boot disable
125044  *  0b1..Fast boot enable
125045  */
125046 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
125047 
125048 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
125049 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
125050 /*! AUTO_SABG_EN - Auto stop at block gap */
125051 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
125052 
125053 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
125054 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
125055 /*! DISABLE_TIME_OUT - Time out
125056  *  0b0..Enable time out
125057  *  0b1..Disable time out
125058  */
125059 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
125060 
125061 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
125062 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
125063 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
125064 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
125065 /*! @} */
125066 
125067 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
125068 /*! @{ */
125069 
125070 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
125071 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
125072 /*! CARD_INT_D3_TEST - Card interrupt detection test
125073  *  0b0..Check the card interrupt only when DATA3 is high.
125074  *  0b1..Check the card interrupt by ignoring the status of DATA3.
125075  */
125076 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
125077 
125078 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK      (0x30U)
125079 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT     (4U)
125080 /*! TUNING_BIT_EN - Tuning bit enable
125081  *  0b00..Enable Tuning circuit for DATA[3:0]
125082  *  0b01..Enable Tuning circuit for DATA[7:0]
125083  *  0b10..Enable Tuning circuit for DATA[0]
125084  *  0b11..Invalid
125085  */
125086 #define USDHC_VEND_SPEC2_TUNING_BIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK)
125087 
125088 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
125089 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
125090 /*! TUNING_CMD_EN - Tuning command enable
125091  *  0b0..Auto tuning circuit does not check the CMD line.
125092  *  0b1..Auto tuning circuit checks the CMD line.
125093  */
125094 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
125095 
125096 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
125097 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
125098 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */
125099 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
125100 
125101 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
125102 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
125103 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */
125104 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
125105 
125106 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
125107 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
125108 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
125109  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
125110  *  0b0..Disable
125111  */
125112 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
125113 
125114 #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
125115 #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
125116 /*! EN_32K_CLK - Select the clock source for host card detection.
125117  *  0b0..Use the peripheral clock (ipg_clk) for card detection.
125118  *  0b1..Use the low power clock (ipg_clk_lp) for card detection.
125119  */
125120 #define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
125121 
125122 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
125123 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
125124 /*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */
125125 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
125126 /*! @} */
125127 
125128 /*! @name TUNING_CTRL - Tuning Control */
125129 /*! @{ */
125130 
125131 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
125132 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
125133 /*! TUNING_START_TAP - Tuning start */
125134 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
125135 
125136 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
125137 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
125138 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
125139 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
125140 
125141 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
125142 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
125143 /*! TUNING_COUNTER - Tuning counter */
125144 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
125145 
125146 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
125147 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
125148 /*! TUNING_STEP - TUNING_STEP */
125149 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
125150 
125151 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
125152 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
125153 /*! TUNING_WINDOW - Data window */
125154 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
125155 
125156 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
125157 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
125158 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
125159 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
125160 /*! @} */
125161 
125162 /*! @name CQVER - Command Queuing Version */
125163 /*! @{ */
125164 
125165 #define USDHC_CQVER_VERSION_SUFFIX_MASK          (0xFU)
125166 #define USDHC_CQVER_VERSION_SUFFIX_SHIFT         (0U)
125167 /*! VERSION_SUFFIX - eMMC version suffix */
125168 #define USDHC_CQVER_VERSION_SUFFIX(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK)
125169 
125170 #define USDHC_CQVER_MINOR_VN_MASK                (0xF0U)
125171 #define USDHC_CQVER_MINOR_VN_SHIFT               (4U)
125172 /*! MINOR_VN - eMMC minor version number */
125173 #define USDHC_CQVER_MINOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK)
125174 
125175 #define USDHC_CQVER_MAJOR_VN_MASK                (0xF00U)
125176 #define USDHC_CQVER_MAJOR_VN_SHIFT               (8U)
125177 /*! MAJOR_VN - eMMC major version number */
125178 #define USDHC_CQVER_MAJOR_VN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK)
125179 /*! @} */
125180 
125181 /*! @name CQCAP - Command Queuing Capabilities */
125182 /*! @{ */
125183 
125184 #define USDHC_CQCAP_ITCFVAL_MASK                 (0x3FFU)
125185 #define USDHC_CQCAP_ITCFVAL_SHIFT                (0U)
125186 /*! ITCFVAL - Internal timer clock frequency value */
125187 #define USDHC_CQCAP_ITCFVAL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK)
125188 
125189 #define USDHC_CQCAP_ITCFMUL_MASK                 (0xF000U)
125190 #define USDHC_CQCAP_ITCFMUL_SHIFT                (12U)
125191 /*! ITCFMUL - Internal timer clock frequency multiplier
125192  *  0b0001..0.001 MHz
125193  *  0b0010..0.01 MHz
125194  *  0b0011..0.1 MHz
125195  *  0b0100..1 MHz
125196  *  0b0101..10 MHz
125197  *  0b0110-0b1001..Reserved
125198  */
125199 #define USDHC_CQCAP_ITCFMUL(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK)
125200 /*! @} */
125201 
125202 /*! @name CQCFG - Command Queuing Configuration */
125203 /*! @{ */
125204 
125205 #define USDHC_CQCFG_CQUE_MASK                    (0x1U)
125206 #define USDHC_CQCFG_CQUE_SHIFT                   (0U)
125207 /*! CQUE - Command queuing enable */
125208 #define USDHC_CQCFG_CQUE(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK)
125209 
125210 #define USDHC_CQCFG_TDS_MASK                     (0x100U)
125211 #define USDHC_CQCFG_TDS_SHIFT                    (8U)
125212 /*! TDS - Task descriptor size
125213  *  0b0..Task descriptor size is 64 bits
125214  *  0b1..Task descriptor size is 128 bits
125215  */
125216 #define USDHC_CQCFG_TDS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK)
125217 
125218 #define USDHC_CQCFG_DCMDE_MASK                   (0x1000U)
125219 #define USDHC_CQCFG_DCMDE_SHIFT                  (12U)
125220 /*! DCMDE - Direct command (DCMD) enable
125221  *  0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor
125222  *  0b1..Task descriptor in slot #31 is a DCMD Task Descriptor
125223  */
125224 #define USDHC_CQCFG_DCMDE(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK)
125225 /*! @} */
125226 
125227 /*! @name CQCTL - Command Queuing Control */
125228 /*! @{ */
125229 
125230 #define USDHC_CQCTL_HALT_MASK                    (0x1U)
125231 #define USDHC_CQCTL_HALT_SHIFT                   (0U)
125232 /*! HALT - Halt */
125233 #define USDHC_CQCTL_HALT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK)
125234 
125235 #define USDHC_CQCTL_CLEAR_MASK                   (0x100U)
125236 #define USDHC_CQCTL_CLEAR_SHIFT                  (8U)
125237 /*! CLEAR - Clear all tasks */
125238 #define USDHC_CQCTL_CLEAR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK)
125239 /*! @} */
125240 
125241 /*! @name CQIS - Command Queuing Interrupt Status */
125242 /*! @{ */
125243 
125244 #define USDHC_CQIS_HAC_MASK                      (0x1U)
125245 #define USDHC_CQIS_HAC_SHIFT                     (0U)
125246 /*! HAC - Halt complete interrupt */
125247 #define USDHC_CQIS_HAC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK)
125248 
125249 #define USDHC_CQIS_TCC_MASK                      (0x2U)
125250 #define USDHC_CQIS_TCC_SHIFT                     (1U)
125251 /*! TCC - Task complete interrupt */
125252 #define USDHC_CQIS_TCC(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK)
125253 
125254 #define USDHC_CQIS_RED_MASK                      (0x4U)
125255 #define USDHC_CQIS_RED_SHIFT                     (2U)
125256 /*! RED - Response error detected interrupt */
125257 #define USDHC_CQIS_RED(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK)
125258 
125259 #define USDHC_CQIS_TCL_MASK                      (0x8U)
125260 #define USDHC_CQIS_TCL_SHIFT                     (3U)
125261 /*! TCL - Task cleared */
125262 #define USDHC_CQIS_TCL(x)                        (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK)
125263 /*! @} */
125264 
125265 /*! @name CQISTE - Command Queuing Interrupt Status Enable */
125266 /*! @{ */
125267 
125268 #define USDHC_CQISTE_HAC_STE_MASK                (0x1U)
125269 #define USDHC_CQISTE_HAC_STE_SHIFT               (0U)
125270 /*! HAC_STE - Halt complete status enable
125271  *  0b0..CQIS[HAC] is disabled
125272  *  0b1..CQIS[HAC] is set when its interrupt condition is active
125273  */
125274 #define USDHC_CQISTE_HAC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK)
125275 
125276 #define USDHC_CQISTE_TCC_STE_MASK                (0x2U)
125277 #define USDHC_CQISTE_TCC_STE_SHIFT               (1U)
125278 /*! TCC_STE - Task complete status enable
125279  *  0b0..CQIS[TCC] is disabled
125280  *  0b1..CQIS[TCC] is set when its interrupt condition is active
125281  */
125282 #define USDHC_CQISTE_TCC_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK)
125283 
125284 #define USDHC_CQISTE_RED_STE_MASK                (0x4U)
125285 #define USDHC_CQISTE_RED_STE_SHIFT               (2U)
125286 /*! RED_STE - Response error detected status enable
125287  *  0b0..CQIS[RED]is disabled
125288  *  0b1..CQIS[RED] is set when its interrupt condition is active
125289  */
125290 #define USDHC_CQISTE_RED_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK)
125291 
125292 #define USDHC_CQISTE_TCL_STE_MASK                (0x8U)
125293 #define USDHC_CQISTE_TCL_STE_SHIFT               (3U)
125294 /*! TCL_STE - Task cleared status enable
125295  *  0b0..CQIS[TCL] is disabled
125296  *  0b1..CQIS[TCL] is set when its interrupt condition is active
125297  */
125298 #define USDHC_CQISTE_TCL_STE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK)
125299 /*! @} */
125300 
125301 /*! @name CQISGE - Command Queuing Interrupt Signal Enable */
125302 /*! @{ */
125303 
125304 #define USDHC_CQISGE_HAC_SGE_MASK                (0x1U)
125305 #define USDHC_CQISGE_HAC_SGE_SHIFT               (0U)
125306 /*! HAC_SGE - Halt complete signal enable */
125307 #define USDHC_CQISGE_HAC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK)
125308 
125309 #define USDHC_CQISGE_TCC_SGE_MASK                (0x2U)
125310 #define USDHC_CQISGE_TCC_SGE_SHIFT               (1U)
125311 /*! TCC_SGE - Task complete signal enable */
125312 #define USDHC_CQISGE_TCC_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK)
125313 
125314 #define USDHC_CQISGE_RED_SGE_MASK                (0x4U)
125315 #define USDHC_CQISGE_RED_SGE_SHIFT               (2U)
125316 /*! RED_SGE - Response error detected signal enable */
125317 #define USDHC_CQISGE_RED_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK)
125318 
125319 #define USDHC_CQISGE_TCL_SGE_MASK                (0x8U)
125320 #define USDHC_CQISGE_TCL_SGE_SHIFT               (3U)
125321 /*! TCL_SGE - Task cleared signal enable */
125322 #define USDHC_CQISGE_TCL_SGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK)
125323 /*! @} */
125324 
125325 /*! @name CQIC - Command Queuing Interrupt Coalescing */
125326 /*! @{ */
125327 
125328 #define USDHC_CQIC_ICTOVAL_MASK                  (0x7FU)
125329 #define USDHC_CQIC_ICTOVAL_SHIFT                 (0U)
125330 /*! ICTOVAL - Interrupt coalescing timeout value */
125331 #define USDHC_CQIC_ICTOVAL(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK)
125332 
125333 #define USDHC_CQIC_ICTOVALWEN_MASK               (0x80U)
125334 #define USDHC_CQIC_ICTOVALWEN_SHIFT              (7U)
125335 /*! ICTOVALWEN - Interrupt coalescing timeout value write enable */
125336 #define USDHC_CQIC_ICTOVALWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK)
125337 
125338 #define USDHC_CQIC_ICCTH_MASK                    (0x1F00U)
125339 #define USDHC_CQIC_ICCTH_SHIFT                   (8U)
125340 /*! ICCTH - Interrupt coalescing counter threshold */
125341 #define USDHC_CQIC_ICCTH(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK)
125342 
125343 #define USDHC_CQIC_ICCTHWEN_MASK                 (0x8000U)
125344 #define USDHC_CQIC_ICCTHWEN_SHIFT                (15U)
125345 /*! ICCTHWEN - Interrupt coalescing counter threshold write enable */
125346 #define USDHC_CQIC_ICCTHWEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK)
125347 
125348 #define USDHC_CQIC_ICCTR_MASK                    (0x10000U)
125349 #define USDHC_CQIC_ICCTR_SHIFT                   (16U)
125350 /*! ICCTR - Counter and timer reset */
125351 #define USDHC_CQIC_ICCTR(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK)
125352 
125353 #define USDHC_CQIC_ICSB_MASK                     (0x100000U)
125354 #define USDHC_CQIC_ICSB_SHIFT                    (20U)
125355 /*! ICSB - Interrupt coalescing status
125356  *  0b0..No task completions have occurred since last counter reset (IC counter =0)
125357  *  0b1..At least one task completion has been counted (IC counter >0)
125358  */
125359 #define USDHC_CQIC_ICSB(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK)
125360 
125361 #define USDHC_CQIC_ICENDIS_MASK                  (0x80000000U)
125362 #define USDHC_CQIC_ICENDIS_SHIFT                 (31U)
125363 /*! ICENDIS - Interrupt coalescing enable/disable */
125364 #define USDHC_CQIC_ICENDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK)
125365 /*! @} */
125366 
125367 /*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */
125368 /*! @{ */
125369 
125370 #define USDHC_CQTDLBA_TDLBA_MASK                 (0xFFFFFFFFU)
125371 #define USDHC_CQTDLBA_TDLBA_SHIFT                (0U)
125372 /*! TDLBA - Task descriptor list base address */
125373 #define USDHC_CQTDLBA_TDLBA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK)
125374 /*! @} */
125375 
125376 /*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */
125377 /*! @{ */
125378 
125379 #define USDHC_CQTDLBAU_TDLBAU_MASK               (0xFFFFFFFFU)
125380 #define USDHC_CQTDLBAU_TDLBAU_SHIFT              (0U)
125381 /*! TDLBAU - Task descriptor list base address */
125382 #define USDHC_CQTDLBAU_TDLBAU(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK)
125383 /*! @} */
125384 
125385 /*! @name CQTDBR - Command Queuing Task Doorbell */
125386 /*! @{ */
125387 
125388 #define USDHC_CQTDBR_TDBR_MASK                   (0xFFFFFFFFU)
125389 #define USDHC_CQTDBR_TDBR_SHIFT                  (0U)
125390 /*! TDBR - Task doorbell */
125391 #define USDHC_CQTDBR_TDBR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK)
125392 /*! @} */
125393 
125394 /*! @name CQTCN - Command Queuing Task Completion Notification */
125395 /*! @{ */
125396 
125397 #define USDHC_CQTCN_TCN_MASK                     (0xFFFFFFFFU)
125398 #define USDHC_CQTCN_TCN_SHIFT                    (0U)
125399 /*! TCN - Task complete notification */
125400 #define USDHC_CQTCN_TCN(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK)
125401 /*! @} */
125402 
125403 /*! @name CQDQS - Command Queuing Device Queue Status */
125404 /*! @{ */
125405 
125406 #define USDHC_CQDQS_DQS_MASK                     (0xFFFFFFFFU)
125407 #define USDHC_CQDQS_DQS_SHIFT                    (0U)
125408 /*! DQS - Device queue status */
125409 #define USDHC_CQDQS_DQS(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK)
125410 /*! @} */
125411 
125412 /*! @name CQDPT - Command Queuing Device Pending Tasks */
125413 /*! @{ */
125414 
125415 #define USDHC_CQDPT_DPT_MASK                     (0xFFFFFFFFU)
125416 #define USDHC_CQDPT_DPT_SHIFT                    (0U)
125417 /*! DPT - Device pending tasks */
125418 #define USDHC_CQDPT_DPT(x)                       (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK)
125419 /*! @} */
125420 
125421 /*! @name CQTCLR - Command Queuing Task Clear */
125422 /*! @{ */
125423 
125424 #define USDHC_CQTCLR_TCLR_MASK                   (0xFFFFFFFFU)
125425 #define USDHC_CQTCLR_TCLR_SHIFT                  (0U)
125426 /*! TCLR - Task clear */
125427 #define USDHC_CQTCLR_TCLR(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK)
125428 /*! @} */
125429 
125430 /*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */
125431 /*! @{ */
125432 
125433 #define USDHC_CQSSC1_CIT_MASK                    (0xFFFFU)
125434 #define USDHC_CQSSC1_CIT_SHIFT                   (0U)
125435 /*! CIT - Send status command idle timer */
125436 #define USDHC_CQSSC1_CIT(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK)
125437 
125438 #define USDHC_CQSSC1_CBC_MASK                    (0xF0000U)
125439 #define USDHC_CQSSC1_CBC_SHIFT                   (16U)
125440 /*! CBC - Send status command block counter */
125441 #define USDHC_CQSSC1_CBC(x)                      (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK)
125442 /*! @} */
125443 
125444 /*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */
125445 /*! @{ */
125446 
125447 #define USDHC_CQSSC2_SSC2_MASK                   (0xFFFFU)
125448 #define USDHC_CQSSC2_SSC2_SHIFT                  (0U)
125449 /*! SSC2 - Send queue status RCA */
125450 #define USDHC_CQSSC2_SSC2(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK)
125451 /*! @} */
125452 
125453 /*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */
125454 /*! @{ */
125455 
125456 #define USDHC_CQCRDCT_CRDCT_MASK                 (0xFFFFFFFFU)
125457 #define USDHC_CQCRDCT_CRDCT_SHIFT                (0U)
125458 /*! CRDCT - Direct command last response */
125459 #define USDHC_CQCRDCT_CRDCT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK)
125460 /*! @} */
125461 
125462 /*! @name CQRMEM - Command Queuing Response Mode Error Mask */
125463 /*! @{ */
125464 
125465 #define USDHC_CQRMEM_RMEM_MASK                   (0xFFFFFFFFU)
125466 #define USDHC_CQRMEM_RMEM_SHIFT                  (0U)
125467 /*! RMEM - Response mode error mask
125468  *  0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored
125469  *  0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated
125470  */
125471 #define USDHC_CQRMEM_RMEM(x)                     (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK)
125472 /*! @} */
125473 
125474 /*! @name CQTERRI - Command Queuing Task Error Information */
125475 /*! @{ */
125476 
125477 #define USDHC_CQTERRI_RMECI_MASK                 (0x3FU)
125478 #define USDHC_CQTERRI_RMECI_SHIFT                (0U)
125479 /*! RMECI - Response mode error command index */
125480 #define USDHC_CQTERRI_RMECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK)
125481 
125482 #define USDHC_CQTERRI_RMETID_MASK                (0x1F00U)
125483 #define USDHC_CQTERRI_RMETID_SHIFT               (8U)
125484 /*! RMETID - Response mode error task ID */
125485 #define USDHC_CQTERRI_RMETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK)
125486 
125487 #define USDHC_CQTERRI_RMEFV_MASK                 (0x8000U)
125488 #define USDHC_CQTERRI_RMEFV_SHIFT                (15U)
125489 /*! RMEFV - Response mode error fields valid */
125490 #define USDHC_CQTERRI_RMEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK)
125491 
125492 #define USDHC_CQTERRI_DTECI_MASK                 (0x3F0000U)
125493 #define USDHC_CQTERRI_DTECI_SHIFT                (16U)
125494 /*! DTECI - Data transfer error command index */
125495 #define USDHC_CQTERRI_DTECI(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK)
125496 
125497 #define USDHC_CQTERRI_DTETID_MASK                (0x1F000000U)
125498 #define USDHC_CQTERRI_DTETID_SHIFT               (24U)
125499 /*! DTETID - Data transfer error task ID */
125500 #define USDHC_CQTERRI_DTETID(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK)
125501 
125502 #define USDHC_CQTERRI_DTEFV_MASK                 (0x80000000U)
125503 #define USDHC_CQTERRI_DTEFV_SHIFT                (31U)
125504 /*! DTEFV - Data transfer error fields valid */
125505 #define USDHC_CQTERRI_DTEFV(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK)
125506 /*! @} */
125507 
125508 /*! @name CQCRI - Command Queuing Command Response Index */
125509 /*! @{ */
125510 
125511 #define USDHC_CQCRI_LCMDRI_MASK                  (0x3FU)
125512 #define USDHC_CQCRI_LCMDRI_SHIFT                 (0U)
125513 /*! LCMDRI - Last command response index */
125514 #define USDHC_CQCRI_LCMDRI(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK)
125515 /*! @} */
125516 
125517 /*! @name CQCRA - Command Queuing Command Response Argument */
125518 /*! @{ */
125519 
125520 #define USDHC_CQCRA_LCMDRA_MASK                  (0xFFFFFFFFU)
125521 #define USDHC_CQCRA_LCMDRA_SHIFT                 (0U)
125522 /*! LCMDRA - Last command response argument */
125523 #define USDHC_CQCRA_LCMDRA(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK)
125524 /*! @} */
125525 
125526 
125527 /*!
125528  * @}
125529  */ /* end of group USDHC_Register_Masks */
125530 
125531 
125532 /* USDHC - Peripheral instance base addresses */
125533 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
125534   /** Peripheral USDHC1 base address */
125535   #define USDHC1_BASE                              (0x52850000u)
125536   /** Peripheral USDHC1 base address */
125537   #define USDHC1_BASE_NS                           (0x42850000u)
125538   /** Peripheral USDHC1 base pointer */
125539   #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
125540   /** Peripheral USDHC1 base pointer */
125541   #define USDHC1_NS                                ((USDHC_Type *)USDHC1_BASE_NS)
125542   /** Array initializer of USDHC peripheral base addresses */
125543   #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE }
125544   /** Array initializer of USDHC peripheral base pointers */
125545   #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1 }
125546   /** Array initializer of USDHC peripheral base addresses */
125547   #define USDHC_BASE_ADDRS_NS                      { 0u, USDHC1_BASE_NS }
125548   /** Array initializer of USDHC peripheral base pointers */
125549   #define USDHC_BASE_PTRS_NS                       { (USDHC_Type *)0u, USDHC1_NS }
125550 #else
125551   /** Peripheral USDHC1 base address */
125552   #define USDHC1_BASE                              (0x42850000u)
125553   /** Peripheral USDHC1 base pointer */
125554   #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
125555   /** Array initializer of USDHC peripheral base addresses */
125556   #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE }
125557   /** Array initializer of USDHC peripheral base pointers */
125558   #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1 }
125559 #endif
125560 /** Interrupt vectors for the USDHC peripheral type */
125561 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn }
125562 
125563 /*!
125564  * @}
125565  */ /* end of group USDHC_Peripheral_Access_Layer */
125566 
125567 
125568 /* ----------------------------------------------------------------------------
125569    -- VMBANDGAP Peripheral Access Layer
125570    ---------------------------------------------------------------------------- */
125571 
125572 /*!
125573  * @addtogroup VMBANDGAP_Peripheral_Access_Layer VMBANDGAP Peripheral Access Layer
125574  * @{
125575  */
125576 
125577 /** VMBANDGAP - Register Layout Typedef */
125578 typedef struct {
125579   struct {                                         /* offset: 0x0 */
125580     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
125581     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
125582     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
125583     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
125584   } CTRL0;
125585        uint8_t RESERVED_0[64];
125586   struct {                                         /* offset: 0x50 */
125587     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
125588     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
125589     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
125590     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
125591   } STAT0;
125592 } VMBANDGAP_Type;
125593 
125594 /* ----------------------------------------------------------------------------
125595    -- VMBANDGAP Register Masks
125596    ---------------------------------------------------------------------------- */
125597 
125598 /*!
125599  * @addtogroup VMBANDGAP_Register_Masks VMBANDGAP Register Masks
125600  * @{
125601  */
125602 
125603 /*! @name CTRL0 - Analog Control Register CTRL0 */
125604 /*! @{ */
125605 
125606 #define VMBANDGAP_CTRL0_REFTOP_PWD_MASK          (0x1U)
125607 #define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT         (0U)
125608 /*! REFTOP_PWD - Master power-down for bandgap module */
125609 #define VMBANDGAP_CTRL0_REFTOP_PWD(x)            (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
125610 
125611 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
125612 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
125613 /*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer */
125614 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)  (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
125615 
125616 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK     (0x4U)
125617 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT    (2U)
125618 /*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap */
125619 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
125620 
125621 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK     (0x8U)
125622 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT    (3U)
125623 /*! REFTOP_LOWPOWER - Low-power control bit */
125624 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
125625 
125626 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK  (0x10U)
125627 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
125628 /*! REFTOP_SELFBIASOFF - bandgap self-bias control bit */
125629 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)    (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
125630 /*! @} */
125631 
125632 /*! @name STAT0 - Analog Status Register STAT0 */
125633 /*! @{ */
125634 
125635 #define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK        (0x1U)
125636 #define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT       (0U)
125637 /*! REFTOP_VBGUP - Brief description here */
125638 #define VMBANDGAP_STAT0_REFTOP_VBGUP(x)          (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
125639 
125640 #define VMBANDGAP_STAT0_VDD1_PORB_MASK           (0x2U)
125641 #define VMBANDGAP_STAT0_VDD1_PORB_SHIFT          (1U)
125642 /*! VDD1_PORB - Brief description here */
125643 #define VMBANDGAP_STAT0_VDD1_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
125644 
125645 #define VMBANDGAP_STAT0_VDD2_PORB_MASK           (0x4U)
125646 #define VMBANDGAP_STAT0_VDD2_PORB_SHIFT          (2U)
125647 /*! VDD2_PORB - Brief description here */
125648 #define VMBANDGAP_STAT0_VDD2_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
125649 
125650 #define VMBANDGAP_STAT0_VDD3_PORB_MASK           (0x8U)
125651 #define VMBANDGAP_STAT0_VDD3_PORB_SHIFT          (3U)
125652 /*! VDD3_PORB - Brief description here */
125653 #define VMBANDGAP_STAT0_VDD3_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK)
125654 /*! @} */
125655 
125656 
125657 /*!
125658  * @}
125659  */ /* end of group VMBANDGAP_Register_Masks */
125660 
125661 
125662 /* VMBANDGAP - Peripheral instance base addresses */
125663 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
125664   /** Peripheral VMBANDGAP base address */
125665   #define VMBANDGAP_BASE                           (0x54484780u)
125666   /** Peripheral VMBANDGAP base address */
125667   #define VMBANDGAP_BASE_NS                        (0x44484780u)
125668   /** Peripheral VMBANDGAP base pointer */
125669   #define VMBANDGAP                                ((VMBANDGAP_Type *)VMBANDGAP_BASE)
125670   /** Peripheral VMBANDGAP base pointer */
125671   #define VMBANDGAP_NS                             ((VMBANDGAP_Type *)VMBANDGAP_BASE_NS)
125672   /** Array initializer of VMBANDGAP peripheral base addresses */
125673   #define VMBANDGAP_BASE_ADDRS                     { VMBANDGAP_BASE }
125674   /** Array initializer of VMBANDGAP peripheral base pointers */
125675   #define VMBANDGAP_BASE_PTRS                      { VMBANDGAP }
125676   /** Array initializer of VMBANDGAP peripheral base addresses */
125677   #define VMBANDGAP_BASE_ADDRS_NS                  { VMBANDGAP_BASE_NS }
125678   /** Array initializer of VMBANDGAP peripheral base pointers */
125679   #define VMBANDGAP_BASE_PTRS_NS                   { VMBANDGAP_NS }
125680 #else
125681   /** Peripheral VMBANDGAP base address */
125682   #define VMBANDGAP_BASE                           (0x44484780u)
125683   /** Peripheral VMBANDGAP base pointer */
125684   #define VMBANDGAP                                ((VMBANDGAP_Type *)VMBANDGAP_BASE)
125685   /** Array initializer of VMBANDGAP peripheral base addresses */
125686   #define VMBANDGAP_BASE_ADDRS                     { VMBANDGAP_BASE }
125687   /** Array initializer of VMBANDGAP peripheral base pointers */
125688   #define VMBANDGAP_BASE_PTRS                      { VMBANDGAP }
125689 #endif
125690 
125691 /*!
125692  * @}
125693  */ /* end of group VMBANDGAP_Peripheral_Access_Layer */
125694 
125695 
125696 /* ----------------------------------------------------------------------------
125697    -- VREF Peripheral Access Layer
125698    ---------------------------------------------------------------------------- */
125699 
125700 /*!
125701  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
125702  * @{
125703  */
125704 
125705 /** VREF - Register Layout Typedef */
125706 typedef struct {
125707   __I  uint32_t VERID;                             /**< VREF Version ID, offset: 0x0 */
125708        uint8_t RESERVED_0[4];
125709   __IO uint32_t CSR;                               /**< VREF Control and Status Register, offset: 0x8 */
125710        uint8_t RESERVED_1[4];
125711   __IO uint32_t UTRIM;                             /**< VREF User Trim, offset: 0x10 */
125712 } VREF_Type;
125713 
125714 /* ----------------------------------------------------------------------------
125715    -- VREF Register Masks
125716    ---------------------------------------------------------------------------- */
125717 
125718 /*!
125719  * @addtogroup VREF_Register_Masks VREF Register Masks
125720  * @{
125721  */
125722 
125723 /*! @name VERID - VREF Version ID */
125724 /*! @{ */
125725 
125726 #define VREF_VERID_FEATURE_MASK                  (0xFFFFU)
125727 #define VREF_VERID_FEATURE_SHIFT                 (0U)
125728 /*! FEATURE - FEATURE */
125729 #define VREF_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK)
125730 
125731 #define VREF_VERID_MINOR_MASK                    (0xFF0000U)
125732 #define VREF_VERID_MINOR_SHIFT                   (16U)
125733 /*! MINOR - MINOR */
125734 #define VREF_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK)
125735 
125736 #define VREF_VERID_MAJOR_MASK                    (0xFF000000U)
125737 #define VREF_VERID_MAJOR_SHIFT                   (24U)
125738 /*! MAJOR - MAJOR */
125739 #define VREF_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK)
125740 /*! @} */
125741 
125742 /*! @name CSR - VREF Control and Status Register */
125743 /*! @{ */
125744 
125745 #define VREF_CSR_HCBGEN_MASK                     (0x1U)
125746 #define VREF_CSR_HCBGEN_SHIFT                    (0U)
125747 /*! HCBGEN - High Accuracy Bandgap enabled
125748  *  0b0..HC Bandgap is disabled
125749  *  0b1..HC Bandgap is enabled
125750  */
125751 #define VREF_CSR_HCBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK)
125752 
125753 #define VREF_CSR_LPBGEN_MASK                     (0x2U)
125754 #define VREF_CSR_LPBGEN_SHIFT                    (1U)
125755 /*! LPBGEN - Low Power Bandgap enable
125756  *  0b0..LP Bandgap is disabled
125757  *  0b1..LP Bandgap is enabled
125758  */
125759 #define VREF_CSR_LPBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK)
125760 
125761 #define VREF_CSR_CHOPEN_MASK                     (0x8U)
125762 #define VREF_CSR_CHOPEN_SHIFT                    (3U)
125763 /*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the
125764  *    internal analog offset will be minimized.
125765  *  0b0..Chop oscillator is disabled.
125766  *  0b1..Chop oscillator is enabled.
125767  */
125768 #define VREF_CSR_CHOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK)
125769 
125770 #define VREF_CSR_ICOMPEN_MASK                    (0x10U)
125771 #define VREF_CSR_ICOMPEN_SHIFT                   (4U)
125772 /*! ICOMPEN - Second order curvature compensation enable
125773  *  0b0..Disabled
125774  *  0b1..Enabled
125775  */
125776 #define VREF_CSR_ICOMPEN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK)
125777 
125778 #define VREF_CSR_REGEN_MASK                      (0x20U)
125779 #define VREF_CSR_REGEN_SHIFT                     (5U)
125780 /*! REGEN - Regulator enable
125781  *  0b0..Internal 1.75 V regulator is disabled.
125782  *  0b1..Internal 1.75 V regulator is enabled.
125783  */
125784 #define VREF_CSR_REGEN(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK)
125785 
125786 #define VREF_CSR_HI_PWR_LV_MASK                  (0x800U)
125787 #define VREF_CSR_HI_PWR_LV_SHIFT                 (11U)
125788 /*! HI_PWR_LV
125789  *  0b0..buffer is in low power mode
125790  *  0b1..buffer is in high power mode
125791  */
125792 #define VREF_CSR_HI_PWR_LV(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK)
125793 
125794 #define VREF_CSR_Buf21EN_MASK                    (0x10000U)
125795 #define VREF_CSR_Buf21EN_SHIFT                   (16U)
125796 /*! Buf21EN - Internal buffer enable
125797  *  0b0..buffer is disabled
125798  *  0b1..buffer is enabled
125799  */
125800 #define VREF_CSR_Buf21EN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_Buf21EN_SHIFT)) & VREF_CSR_Buf21EN_MASK)
125801 
125802 #define VREF_CSR_VREFST_MASK                     (0x80000000U)
125803 #define VREF_CSR_VREFST_SHIFT                    (31U)
125804 /*! VREFST - Internal High Accuracy Voltage Reference stable
125805  *  0b0..The module is disabled or not stable.
125806  *  0b1..The module is stable.
125807  */
125808 #define VREF_CSR_VREFST(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK)
125809 /*! @} */
125810 
125811 /*! @name UTRIM - VREF User Trim */
125812 /*! @{ */
125813 
125814 #define VREF_UTRIM_VREFTRIM_MASK                 (0x3F00U)
125815 #define VREF_UTRIM_VREFTRIM_SHIFT                (8U)
125816 /*! VREFTRIM - VREF Trim bits
125817  *  0b000000..Min
125818  *  0b000001..Max-31*(4/3) mV
125819  *  0b111111..Max
125820  */
125821 #define VREF_UTRIM_VREFTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK)
125822 /*! @} */
125823 
125824 
125825 /*!
125826  * @}
125827  */ /* end of group VREF_Register_Masks */
125828 
125829 
125830 /* VREF - Peripheral instance base addresses */
125831 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
125832   /** Peripheral VREF base address */
125833   #define VREF_BASE                                (0x52E30000u)
125834   /** Peripheral VREF base address */
125835   #define VREF_BASE_NS                             (0x42E30000u)
125836   /** Peripheral VREF base pointer */
125837   #define VREF                                     ((VREF_Type *)VREF_BASE)
125838   /** Peripheral VREF base pointer */
125839   #define VREF_NS                                  ((VREF_Type *)VREF_BASE_NS)
125840   /** Array initializer of VREF peripheral base addresses */
125841   #define VREF_BASE_ADDRS                          { VREF_BASE }
125842   /** Array initializer of VREF peripheral base pointers */
125843   #define VREF_BASE_PTRS                           { VREF }
125844   /** Array initializer of VREF peripheral base addresses */
125845   #define VREF_BASE_ADDRS_NS                       { VREF_BASE_NS }
125846   /** Array initializer of VREF peripheral base pointers */
125847   #define VREF_BASE_PTRS_NS                        { VREF_NS }
125848 #else
125849   /** Peripheral VREF base address */
125850   #define VREF_BASE                                (0x42E30000u)
125851   /** Peripheral VREF base pointer */
125852   #define VREF                                     ((VREF_Type *)VREF_BASE)
125853   /** Array initializer of VREF peripheral base addresses */
125854   #define VREF_BASE_ADDRS                          { VREF_BASE }
125855   /** Array initializer of VREF peripheral base pointers */
125856   #define VREF_BASE_PTRS                           { VREF }
125857 #endif
125858 
125859 /*!
125860  * @}
125861  */ /* end of group VREF_Peripheral_Access_Layer */
125862 
125863 
125864 /* ----------------------------------------------------------------------------
125865    -- XBAR_NUM_OUT221 Peripheral Access Layer
125866    ---------------------------------------------------------------------------- */
125867 
125868 /*!
125869  * @addtogroup XBAR_NUM_OUT221_Peripheral_Access_Layer XBAR_NUM_OUT221 Peripheral Access Layer
125870  * @{
125871  */
125872 
125873 /** XBAR_NUM_OUT221 - Register Layout Typedef */
125874 typedef struct {
125875   __IO uint16_t SEL[111];                          /**< Crossbar Select Register, array offset: 0x0, array step: 0x2 */
125876   __IO uint16_t CTRL[2];                           /**< Crossbar Control Register, array offset: 0xDE, array step: 0x2 */
125877 } XBAR_NUM_OUT221_Type;
125878 
125879 /* ----------------------------------------------------------------------------
125880    -- XBAR_NUM_OUT221 Register Masks
125881    ---------------------------------------------------------------------------- */
125882 
125883 /*!
125884  * @addtogroup XBAR_NUM_OUT221_Register_Masks XBAR_NUM_OUT221 Register Masks
125885  * @{
125886  */
125887 
125888 /*! @name SEL - Crossbar Select Register */
125889 /*! @{ */
125890 
125891 #define XBAR_NUM_OUT221_SEL_SEL0_MASK            (0xFFU)
125892 #define XBAR_NUM_OUT221_SEL_SEL0_SHIFT           (0U)
125893 /*! SEL0 - SEL0 */
125894 #define XBAR_NUM_OUT221_SEL_SEL0(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL0_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL0_MASK)
125895 
125896 #define XBAR_NUM_OUT221_SEL_SEL2_MASK            (0xFFU)
125897 #define XBAR_NUM_OUT221_SEL_SEL2_SHIFT           (0U)
125898 /*! SEL2 - SEL2 */
125899 #define XBAR_NUM_OUT221_SEL_SEL2(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL2_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL2_MASK)
125900 
125901 #define XBAR_NUM_OUT221_SEL_SEL4_MASK            (0xFFU)
125902 #define XBAR_NUM_OUT221_SEL_SEL4_SHIFT           (0U)
125903 /*! SEL4 - SEL4 */
125904 #define XBAR_NUM_OUT221_SEL_SEL4(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL4_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL4_MASK)
125905 
125906 #define XBAR_NUM_OUT221_SEL_SEL6_MASK            (0xFFU)
125907 #define XBAR_NUM_OUT221_SEL_SEL6_SHIFT           (0U)
125908 /*! SEL6 - SEL6 */
125909 #define XBAR_NUM_OUT221_SEL_SEL6(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL6_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL6_MASK)
125910 
125911 #define XBAR_NUM_OUT221_SEL_SEL8_MASK            (0xFFU)
125912 #define XBAR_NUM_OUT221_SEL_SEL8_SHIFT           (0U)
125913 /*! SEL8 - SEL8 */
125914 #define XBAR_NUM_OUT221_SEL_SEL8(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL8_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL8_MASK)
125915 
125916 #define XBAR_NUM_OUT221_SEL_SEL10_MASK           (0xFFU)
125917 #define XBAR_NUM_OUT221_SEL_SEL10_SHIFT          (0U)
125918 /*! SEL10 - SEL10 */
125919 #define XBAR_NUM_OUT221_SEL_SEL10(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL10_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL10_MASK)
125920 
125921 #define XBAR_NUM_OUT221_SEL_SEL12_MASK           (0xFFU)
125922 #define XBAR_NUM_OUT221_SEL_SEL12_SHIFT          (0U)
125923 /*! SEL12 - SEL12 */
125924 #define XBAR_NUM_OUT221_SEL_SEL12(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL12_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL12_MASK)
125925 
125926 #define XBAR_NUM_OUT221_SEL_SEL14_MASK           (0xFFU)
125927 #define XBAR_NUM_OUT221_SEL_SEL14_SHIFT          (0U)
125928 /*! SEL14 - SEL14 */
125929 #define XBAR_NUM_OUT221_SEL_SEL14(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL14_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL14_MASK)
125930 
125931 #define XBAR_NUM_OUT221_SEL_SEL16_MASK           (0xFFU)
125932 #define XBAR_NUM_OUT221_SEL_SEL16_SHIFT          (0U)
125933 /*! SEL16 - SEL16 */
125934 #define XBAR_NUM_OUT221_SEL_SEL16(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL16_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL16_MASK)
125935 
125936 #define XBAR_NUM_OUT221_SEL_SEL18_MASK           (0xFFU)
125937 #define XBAR_NUM_OUT221_SEL_SEL18_SHIFT          (0U)
125938 /*! SEL18 - SEL18 */
125939 #define XBAR_NUM_OUT221_SEL_SEL18(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL18_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL18_MASK)
125940 
125941 #define XBAR_NUM_OUT221_SEL_SEL20_MASK           (0xFFU)
125942 #define XBAR_NUM_OUT221_SEL_SEL20_SHIFT          (0U)
125943 /*! SEL20 - SEL20 */
125944 #define XBAR_NUM_OUT221_SEL_SEL20(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL20_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL20_MASK)
125945 
125946 #define XBAR_NUM_OUT221_SEL_SEL22_MASK           (0xFFU)
125947 #define XBAR_NUM_OUT221_SEL_SEL22_SHIFT          (0U)
125948 /*! SEL22 - SEL22 */
125949 #define XBAR_NUM_OUT221_SEL_SEL22(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL22_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL22_MASK)
125950 
125951 #define XBAR_NUM_OUT221_SEL_SEL24_MASK           (0xFFU)
125952 #define XBAR_NUM_OUT221_SEL_SEL24_SHIFT          (0U)
125953 /*! SEL24 - SEL24 */
125954 #define XBAR_NUM_OUT221_SEL_SEL24(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL24_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL24_MASK)
125955 
125956 #define XBAR_NUM_OUT221_SEL_SEL26_MASK           (0xFFU)
125957 #define XBAR_NUM_OUT221_SEL_SEL26_SHIFT          (0U)
125958 /*! SEL26 - SEL26 */
125959 #define XBAR_NUM_OUT221_SEL_SEL26(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL26_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL26_MASK)
125960 
125961 #define XBAR_NUM_OUT221_SEL_SEL28_MASK           (0xFFU)
125962 #define XBAR_NUM_OUT221_SEL_SEL28_SHIFT          (0U)
125963 /*! SEL28 - SEL28 */
125964 #define XBAR_NUM_OUT221_SEL_SEL28(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL28_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL28_MASK)
125965 
125966 #define XBAR_NUM_OUT221_SEL_SEL30_MASK           (0xFFU)
125967 #define XBAR_NUM_OUT221_SEL_SEL30_SHIFT          (0U)
125968 /*! SEL30 - SEL30 */
125969 #define XBAR_NUM_OUT221_SEL_SEL30(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL30_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL30_MASK)
125970 
125971 #define XBAR_NUM_OUT221_SEL_SEL32_MASK           (0xFFU)
125972 #define XBAR_NUM_OUT221_SEL_SEL32_SHIFT          (0U)
125973 /*! SEL32 - SEL32 */
125974 #define XBAR_NUM_OUT221_SEL_SEL32(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL32_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL32_MASK)
125975 
125976 #define XBAR_NUM_OUT221_SEL_SEL34_MASK           (0xFFU)
125977 #define XBAR_NUM_OUT221_SEL_SEL34_SHIFT          (0U)
125978 /*! SEL34 - SEL34 */
125979 #define XBAR_NUM_OUT221_SEL_SEL34(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL34_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL34_MASK)
125980 
125981 #define XBAR_NUM_OUT221_SEL_SEL36_MASK           (0xFFU)
125982 #define XBAR_NUM_OUT221_SEL_SEL36_SHIFT          (0U)
125983 /*! SEL36 - SEL36 */
125984 #define XBAR_NUM_OUT221_SEL_SEL36(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL36_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL36_MASK)
125985 
125986 #define XBAR_NUM_OUT221_SEL_SEL38_MASK           (0xFFU)
125987 #define XBAR_NUM_OUT221_SEL_SEL38_SHIFT          (0U)
125988 /*! SEL38 - SEL38 */
125989 #define XBAR_NUM_OUT221_SEL_SEL38(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL38_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL38_MASK)
125990 
125991 #define XBAR_NUM_OUT221_SEL_SEL40_MASK           (0xFFU)
125992 #define XBAR_NUM_OUT221_SEL_SEL40_SHIFT          (0U)
125993 /*! SEL40 - SEL40 */
125994 #define XBAR_NUM_OUT221_SEL_SEL40(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL40_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL40_MASK)
125995 
125996 #define XBAR_NUM_OUT221_SEL_SEL42_MASK           (0xFFU)
125997 #define XBAR_NUM_OUT221_SEL_SEL42_SHIFT          (0U)
125998 /*! SEL42 - SEL42 */
125999 #define XBAR_NUM_OUT221_SEL_SEL42(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL42_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL42_MASK)
126000 
126001 #define XBAR_NUM_OUT221_SEL_SEL44_MASK           (0xFFU)
126002 #define XBAR_NUM_OUT221_SEL_SEL44_SHIFT          (0U)
126003 /*! SEL44 - SEL44 */
126004 #define XBAR_NUM_OUT221_SEL_SEL44(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL44_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL44_MASK)
126005 
126006 #define XBAR_NUM_OUT221_SEL_SEL46_MASK           (0xFFU)
126007 #define XBAR_NUM_OUT221_SEL_SEL46_SHIFT          (0U)
126008 /*! SEL46 - SEL46 */
126009 #define XBAR_NUM_OUT221_SEL_SEL46(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL46_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL46_MASK)
126010 
126011 #define XBAR_NUM_OUT221_SEL_SEL48_MASK           (0xFFU)
126012 #define XBAR_NUM_OUT221_SEL_SEL48_SHIFT          (0U)
126013 /*! SEL48 - SEL48 */
126014 #define XBAR_NUM_OUT221_SEL_SEL48(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL48_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL48_MASK)
126015 
126016 #define XBAR_NUM_OUT221_SEL_SEL50_MASK           (0xFFU)
126017 #define XBAR_NUM_OUT221_SEL_SEL50_SHIFT          (0U)
126018 /*! SEL50 - SEL50 */
126019 #define XBAR_NUM_OUT221_SEL_SEL50(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL50_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL50_MASK)
126020 
126021 #define XBAR_NUM_OUT221_SEL_SEL52_MASK           (0xFFU)
126022 #define XBAR_NUM_OUT221_SEL_SEL52_SHIFT          (0U)
126023 /*! SEL52 - SEL52 */
126024 #define XBAR_NUM_OUT221_SEL_SEL52(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL52_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL52_MASK)
126025 
126026 #define XBAR_NUM_OUT221_SEL_SEL54_MASK           (0xFFU)
126027 #define XBAR_NUM_OUT221_SEL_SEL54_SHIFT          (0U)
126028 /*! SEL54 - SEL54 */
126029 #define XBAR_NUM_OUT221_SEL_SEL54(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL54_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL54_MASK)
126030 
126031 #define XBAR_NUM_OUT221_SEL_SEL56_MASK           (0xFFU)
126032 #define XBAR_NUM_OUT221_SEL_SEL56_SHIFT          (0U)
126033 /*! SEL56 - SEL56 */
126034 #define XBAR_NUM_OUT221_SEL_SEL56(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL56_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL56_MASK)
126035 
126036 #define XBAR_NUM_OUT221_SEL_SEL58_MASK           (0xFFU)
126037 #define XBAR_NUM_OUT221_SEL_SEL58_SHIFT          (0U)
126038 /*! SEL58 - SEL58 */
126039 #define XBAR_NUM_OUT221_SEL_SEL58(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL58_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL58_MASK)
126040 
126041 #define XBAR_NUM_OUT221_SEL_SEL60_MASK           (0xFFU)
126042 #define XBAR_NUM_OUT221_SEL_SEL60_SHIFT          (0U)
126043 /*! SEL60 - SEL60 */
126044 #define XBAR_NUM_OUT221_SEL_SEL60(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL60_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL60_MASK)
126045 
126046 #define XBAR_NUM_OUT221_SEL_SEL62_MASK           (0xFFU)
126047 #define XBAR_NUM_OUT221_SEL_SEL62_SHIFT          (0U)
126048 /*! SEL62 - SEL62 */
126049 #define XBAR_NUM_OUT221_SEL_SEL62(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL62_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL62_MASK)
126050 
126051 #define XBAR_NUM_OUT221_SEL_SEL64_MASK           (0xFFU)
126052 #define XBAR_NUM_OUT221_SEL_SEL64_SHIFT          (0U)
126053 /*! SEL64 - SEL64 */
126054 #define XBAR_NUM_OUT221_SEL_SEL64(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL64_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL64_MASK)
126055 
126056 #define XBAR_NUM_OUT221_SEL_SEL66_MASK           (0xFFU)
126057 #define XBAR_NUM_OUT221_SEL_SEL66_SHIFT          (0U)
126058 /*! SEL66 - SEL66 */
126059 #define XBAR_NUM_OUT221_SEL_SEL66(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL66_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL66_MASK)
126060 
126061 #define XBAR_NUM_OUT221_SEL_SEL68_MASK           (0xFFU)
126062 #define XBAR_NUM_OUT221_SEL_SEL68_SHIFT          (0U)
126063 /*! SEL68 - SEL68 */
126064 #define XBAR_NUM_OUT221_SEL_SEL68(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL68_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL68_MASK)
126065 
126066 #define XBAR_NUM_OUT221_SEL_SEL70_MASK           (0xFFU)
126067 #define XBAR_NUM_OUT221_SEL_SEL70_SHIFT          (0U)
126068 /*! SEL70 - SEL70 */
126069 #define XBAR_NUM_OUT221_SEL_SEL70(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL70_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL70_MASK)
126070 
126071 #define XBAR_NUM_OUT221_SEL_SEL72_MASK           (0xFFU)
126072 #define XBAR_NUM_OUT221_SEL_SEL72_SHIFT          (0U)
126073 /*! SEL72 - SEL72 */
126074 #define XBAR_NUM_OUT221_SEL_SEL72(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL72_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL72_MASK)
126075 
126076 #define XBAR_NUM_OUT221_SEL_SEL74_MASK           (0xFFU)
126077 #define XBAR_NUM_OUT221_SEL_SEL74_SHIFT          (0U)
126078 /*! SEL74 - SEL74 */
126079 #define XBAR_NUM_OUT221_SEL_SEL74(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL74_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL74_MASK)
126080 
126081 #define XBAR_NUM_OUT221_SEL_SEL76_MASK           (0xFFU)
126082 #define XBAR_NUM_OUT221_SEL_SEL76_SHIFT          (0U)
126083 /*! SEL76 - SEL76 */
126084 #define XBAR_NUM_OUT221_SEL_SEL76(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL76_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL76_MASK)
126085 
126086 #define XBAR_NUM_OUT221_SEL_SEL78_MASK           (0xFFU)
126087 #define XBAR_NUM_OUT221_SEL_SEL78_SHIFT          (0U)
126088 /*! SEL78 - SEL78 */
126089 #define XBAR_NUM_OUT221_SEL_SEL78(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL78_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL78_MASK)
126090 
126091 #define XBAR_NUM_OUT221_SEL_SEL80_MASK           (0xFFU)
126092 #define XBAR_NUM_OUT221_SEL_SEL80_SHIFT          (0U)
126093 /*! SEL80 - SEL80 */
126094 #define XBAR_NUM_OUT221_SEL_SEL80(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL80_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL80_MASK)
126095 
126096 #define XBAR_NUM_OUT221_SEL_SEL82_MASK           (0xFFU)
126097 #define XBAR_NUM_OUT221_SEL_SEL82_SHIFT          (0U)
126098 /*! SEL82 - SEL82 */
126099 #define XBAR_NUM_OUT221_SEL_SEL82(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL82_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL82_MASK)
126100 
126101 #define XBAR_NUM_OUT221_SEL_SEL84_MASK           (0xFFU)
126102 #define XBAR_NUM_OUT221_SEL_SEL84_SHIFT          (0U)
126103 /*! SEL84 - SEL84 */
126104 #define XBAR_NUM_OUT221_SEL_SEL84(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL84_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL84_MASK)
126105 
126106 #define XBAR_NUM_OUT221_SEL_SEL86_MASK           (0xFFU)
126107 #define XBAR_NUM_OUT221_SEL_SEL86_SHIFT          (0U)
126108 /*! SEL86 - SEL86 */
126109 #define XBAR_NUM_OUT221_SEL_SEL86(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL86_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL86_MASK)
126110 
126111 #define XBAR_NUM_OUT221_SEL_SEL88_MASK           (0xFFU)
126112 #define XBAR_NUM_OUT221_SEL_SEL88_SHIFT          (0U)
126113 /*! SEL88 - SEL88 */
126114 #define XBAR_NUM_OUT221_SEL_SEL88(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL88_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL88_MASK)
126115 
126116 #define XBAR_NUM_OUT221_SEL_SEL90_MASK           (0xFFU)
126117 #define XBAR_NUM_OUT221_SEL_SEL90_SHIFT          (0U)
126118 /*! SEL90 - SEL90 */
126119 #define XBAR_NUM_OUT221_SEL_SEL90(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL90_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL90_MASK)
126120 
126121 #define XBAR_NUM_OUT221_SEL_SEL92_MASK           (0xFFU)
126122 #define XBAR_NUM_OUT221_SEL_SEL92_SHIFT          (0U)
126123 /*! SEL92 - SEL92 */
126124 #define XBAR_NUM_OUT221_SEL_SEL92(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL92_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL92_MASK)
126125 
126126 #define XBAR_NUM_OUT221_SEL_SEL94_MASK           (0xFFU)
126127 #define XBAR_NUM_OUT221_SEL_SEL94_SHIFT          (0U)
126128 /*! SEL94 - SEL94 */
126129 #define XBAR_NUM_OUT221_SEL_SEL94(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL94_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL94_MASK)
126130 
126131 #define XBAR_NUM_OUT221_SEL_SEL96_MASK           (0xFFU)
126132 #define XBAR_NUM_OUT221_SEL_SEL96_SHIFT          (0U)
126133 /*! SEL96 - SEL96 */
126134 #define XBAR_NUM_OUT221_SEL_SEL96(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL96_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL96_MASK)
126135 
126136 #define XBAR_NUM_OUT221_SEL_SEL98_MASK           (0xFFU)
126137 #define XBAR_NUM_OUT221_SEL_SEL98_SHIFT          (0U)
126138 /*! SEL98 - SEL98 */
126139 #define XBAR_NUM_OUT221_SEL_SEL98(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL98_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL98_MASK)
126140 
126141 #define XBAR_NUM_OUT221_SEL_SEL100_MASK          (0xFFU)
126142 #define XBAR_NUM_OUT221_SEL_SEL100_SHIFT         (0U)
126143 /*! SEL100 - SEL100 */
126144 #define XBAR_NUM_OUT221_SEL_SEL100(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL100_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL100_MASK)
126145 
126146 #define XBAR_NUM_OUT221_SEL_SEL102_MASK          (0xFFU)
126147 #define XBAR_NUM_OUT221_SEL_SEL102_SHIFT         (0U)
126148 /*! SEL102 - SEL102 */
126149 #define XBAR_NUM_OUT221_SEL_SEL102(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL102_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL102_MASK)
126150 
126151 #define XBAR_NUM_OUT221_SEL_SEL104_MASK          (0xFFU)
126152 #define XBAR_NUM_OUT221_SEL_SEL104_SHIFT         (0U)
126153 /*! SEL104 - SEL104 */
126154 #define XBAR_NUM_OUT221_SEL_SEL104(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL104_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL104_MASK)
126155 
126156 #define XBAR_NUM_OUT221_SEL_SEL106_MASK          (0xFFU)
126157 #define XBAR_NUM_OUT221_SEL_SEL106_SHIFT         (0U)
126158 /*! SEL106 - SEL106 */
126159 #define XBAR_NUM_OUT221_SEL_SEL106(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL106_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL106_MASK)
126160 
126161 #define XBAR_NUM_OUT221_SEL_SEL108_MASK          (0xFFU)
126162 #define XBAR_NUM_OUT221_SEL_SEL108_SHIFT         (0U)
126163 /*! SEL108 - SEL108 */
126164 #define XBAR_NUM_OUT221_SEL_SEL108(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL108_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL108_MASK)
126165 
126166 #define XBAR_NUM_OUT221_SEL_SEL110_MASK          (0xFFU)
126167 #define XBAR_NUM_OUT221_SEL_SEL110_SHIFT         (0U)
126168 /*! SEL110 - SEL110 */
126169 #define XBAR_NUM_OUT221_SEL_SEL110(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL110_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL110_MASK)
126170 
126171 #define XBAR_NUM_OUT221_SEL_SEL112_MASK          (0xFFU)
126172 #define XBAR_NUM_OUT221_SEL_SEL112_SHIFT         (0U)
126173 /*! SEL112 - SEL112 */
126174 #define XBAR_NUM_OUT221_SEL_SEL112(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL112_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL112_MASK)
126175 
126176 #define XBAR_NUM_OUT221_SEL_SEL114_MASK          (0xFFU)
126177 #define XBAR_NUM_OUT221_SEL_SEL114_SHIFT         (0U)
126178 /*! SEL114 - SEL114 */
126179 #define XBAR_NUM_OUT221_SEL_SEL114(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL114_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL114_MASK)
126180 
126181 #define XBAR_NUM_OUT221_SEL_SEL116_MASK          (0xFFU)
126182 #define XBAR_NUM_OUT221_SEL_SEL116_SHIFT         (0U)
126183 /*! SEL116 - SEL116 */
126184 #define XBAR_NUM_OUT221_SEL_SEL116(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL116_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL116_MASK)
126185 
126186 #define XBAR_NUM_OUT221_SEL_SEL118_MASK          (0xFFU)
126187 #define XBAR_NUM_OUT221_SEL_SEL118_SHIFT         (0U)
126188 /*! SEL118 - SEL118 */
126189 #define XBAR_NUM_OUT221_SEL_SEL118(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL118_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL118_MASK)
126190 
126191 #define XBAR_NUM_OUT221_SEL_SEL120_MASK          (0xFFU)
126192 #define XBAR_NUM_OUT221_SEL_SEL120_SHIFT         (0U)
126193 /*! SEL120 - SEL120 */
126194 #define XBAR_NUM_OUT221_SEL_SEL120(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL120_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL120_MASK)
126195 
126196 #define XBAR_NUM_OUT221_SEL_SEL122_MASK          (0xFFU)
126197 #define XBAR_NUM_OUT221_SEL_SEL122_SHIFT         (0U)
126198 /*! SEL122 - SEL122 */
126199 #define XBAR_NUM_OUT221_SEL_SEL122(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL122_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL122_MASK)
126200 
126201 #define XBAR_NUM_OUT221_SEL_SEL124_MASK          (0xFFU)
126202 #define XBAR_NUM_OUT221_SEL_SEL124_SHIFT         (0U)
126203 /*! SEL124 - SEL124 */
126204 #define XBAR_NUM_OUT221_SEL_SEL124(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL124_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL124_MASK)
126205 
126206 #define XBAR_NUM_OUT221_SEL_SEL126_MASK          (0xFFU)
126207 #define XBAR_NUM_OUT221_SEL_SEL126_SHIFT         (0U)
126208 /*! SEL126 - SEL126 */
126209 #define XBAR_NUM_OUT221_SEL_SEL126(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL126_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL126_MASK)
126210 
126211 #define XBAR_NUM_OUT221_SEL_SEL128_MASK          (0xFFU)
126212 #define XBAR_NUM_OUT221_SEL_SEL128_SHIFT         (0U)
126213 /*! SEL128 - SEL128 */
126214 #define XBAR_NUM_OUT221_SEL_SEL128(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL128_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL128_MASK)
126215 
126216 #define XBAR_NUM_OUT221_SEL_SEL130_MASK          (0xFFU)
126217 #define XBAR_NUM_OUT221_SEL_SEL130_SHIFT         (0U)
126218 /*! SEL130 - SEL130 */
126219 #define XBAR_NUM_OUT221_SEL_SEL130(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL130_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL130_MASK)
126220 
126221 #define XBAR_NUM_OUT221_SEL_SEL132_MASK          (0xFFU)
126222 #define XBAR_NUM_OUT221_SEL_SEL132_SHIFT         (0U)
126223 /*! SEL132 - SEL132 */
126224 #define XBAR_NUM_OUT221_SEL_SEL132(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL132_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL132_MASK)
126225 
126226 #define XBAR_NUM_OUT221_SEL_SEL134_MASK          (0xFFU)
126227 #define XBAR_NUM_OUT221_SEL_SEL134_SHIFT         (0U)
126228 /*! SEL134 - SEL134 */
126229 #define XBAR_NUM_OUT221_SEL_SEL134(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL134_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL134_MASK)
126230 
126231 #define XBAR_NUM_OUT221_SEL_SEL136_MASK          (0xFFU)
126232 #define XBAR_NUM_OUT221_SEL_SEL136_SHIFT         (0U)
126233 /*! SEL136 - SEL136 */
126234 #define XBAR_NUM_OUT221_SEL_SEL136(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL136_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL136_MASK)
126235 
126236 #define XBAR_NUM_OUT221_SEL_SEL138_MASK          (0xFFU)
126237 #define XBAR_NUM_OUT221_SEL_SEL138_SHIFT         (0U)
126238 /*! SEL138 - SEL138 */
126239 #define XBAR_NUM_OUT221_SEL_SEL138(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL138_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL138_MASK)
126240 
126241 #define XBAR_NUM_OUT221_SEL_SEL140_MASK          (0xFFU)
126242 #define XBAR_NUM_OUT221_SEL_SEL140_SHIFT         (0U)
126243 /*! SEL140 - SEL140 */
126244 #define XBAR_NUM_OUT221_SEL_SEL140(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL140_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL140_MASK)
126245 
126246 #define XBAR_NUM_OUT221_SEL_SEL142_MASK          (0xFFU)
126247 #define XBAR_NUM_OUT221_SEL_SEL142_SHIFT         (0U)
126248 /*! SEL142 - SEL142 */
126249 #define XBAR_NUM_OUT221_SEL_SEL142(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL142_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL142_MASK)
126250 
126251 #define XBAR_NUM_OUT221_SEL_SEL144_MASK          (0xFFU)
126252 #define XBAR_NUM_OUT221_SEL_SEL144_SHIFT         (0U)
126253 /*! SEL144 - SEL144 */
126254 #define XBAR_NUM_OUT221_SEL_SEL144(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL144_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL144_MASK)
126255 
126256 #define XBAR_NUM_OUT221_SEL_SEL146_MASK          (0xFFU)
126257 #define XBAR_NUM_OUT221_SEL_SEL146_SHIFT         (0U)
126258 /*! SEL146 - SEL146 */
126259 #define XBAR_NUM_OUT221_SEL_SEL146(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL146_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL146_MASK)
126260 
126261 #define XBAR_NUM_OUT221_SEL_SEL148_MASK          (0xFFU)
126262 #define XBAR_NUM_OUT221_SEL_SEL148_SHIFT         (0U)
126263 /*! SEL148 - SEL148 */
126264 #define XBAR_NUM_OUT221_SEL_SEL148(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL148_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL148_MASK)
126265 
126266 #define XBAR_NUM_OUT221_SEL_SEL150_MASK          (0xFFU)
126267 #define XBAR_NUM_OUT221_SEL_SEL150_SHIFT         (0U)
126268 /*! SEL150 - SEL150 */
126269 #define XBAR_NUM_OUT221_SEL_SEL150(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL150_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL150_MASK)
126270 
126271 #define XBAR_NUM_OUT221_SEL_SEL152_MASK          (0xFFU)
126272 #define XBAR_NUM_OUT221_SEL_SEL152_SHIFT         (0U)
126273 /*! SEL152 - SEL152 */
126274 #define XBAR_NUM_OUT221_SEL_SEL152(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL152_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL152_MASK)
126275 
126276 #define XBAR_NUM_OUT221_SEL_SEL154_MASK          (0xFFU)
126277 #define XBAR_NUM_OUT221_SEL_SEL154_SHIFT         (0U)
126278 /*! SEL154 - SEL154 */
126279 #define XBAR_NUM_OUT221_SEL_SEL154(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL154_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL154_MASK)
126280 
126281 #define XBAR_NUM_OUT221_SEL_SEL156_MASK          (0xFFU)
126282 #define XBAR_NUM_OUT221_SEL_SEL156_SHIFT         (0U)
126283 /*! SEL156 - SEL156 */
126284 #define XBAR_NUM_OUT221_SEL_SEL156(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL156_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL156_MASK)
126285 
126286 #define XBAR_NUM_OUT221_SEL_SEL158_MASK          (0xFFU)
126287 #define XBAR_NUM_OUT221_SEL_SEL158_SHIFT         (0U)
126288 /*! SEL158 - SEL158 */
126289 #define XBAR_NUM_OUT221_SEL_SEL158(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL158_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL158_MASK)
126290 
126291 #define XBAR_NUM_OUT221_SEL_SEL160_MASK          (0xFFU)
126292 #define XBAR_NUM_OUT221_SEL_SEL160_SHIFT         (0U)
126293 /*! SEL160 - SEL160 */
126294 #define XBAR_NUM_OUT221_SEL_SEL160(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL160_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL160_MASK)
126295 
126296 #define XBAR_NUM_OUT221_SEL_SEL162_MASK          (0xFFU)
126297 #define XBAR_NUM_OUT221_SEL_SEL162_SHIFT         (0U)
126298 /*! SEL162 - SEL162 */
126299 #define XBAR_NUM_OUT221_SEL_SEL162(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL162_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL162_MASK)
126300 
126301 #define XBAR_NUM_OUT221_SEL_SEL164_MASK          (0xFFU)
126302 #define XBAR_NUM_OUT221_SEL_SEL164_SHIFT         (0U)
126303 /*! SEL164 - SEL164 */
126304 #define XBAR_NUM_OUT221_SEL_SEL164(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL164_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL164_MASK)
126305 
126306 #define XBAR_NUM_OUT221_SEL_SEL166_MASK          (0xFFU)
126307 #define XBAR_NUM_OUT221_SEL_SEL166_SHIFT         (0U)
126308 /*! SEL166 - SEL166 */
126309 #define XBAR_NUM_OUT221_SEL_SEL166(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL166_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL166_MASK)
126310 
126311 #define XBAR_NUM_OUT221_SEL_SEL168_MASK          (0xFFU)
126312 #define XBAR_NUM_OUT221_SEL_SEL168_SHIFT         (0U)
126313 /*! SEL168 - SEL168 */
126314 #define XBAR_NUM_OUT221_SEL_SEL168(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL168_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL168_MASK)
126315 
126316 #define XBAR_NUM_OUT221_SEL_SEL170_MASK          (0xFFU)
126317 #define XBAR_NUM_OUT221_SEL_SEL170_SHIFT         (0U)
126318 /*! SEL170 - SEL170 */
126319 #define XBAR_NUM_OUT221_SEL_SEL170(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL170_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL170_MASK)
126320 
126321 #define XBAR_NUM_OUT221_SEL_SEL172_MASK          (0xFFU)
126322 #define XBAR_NUM_OUT221_SEL_SEL172_SHIFT         (0U)
126323 /*! SEL172 - SEL172 */
126324 #define XBAR_NUM_OUT221_SEL_SEL172(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL172_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL172_MASK)
126325 
126326 #define XBAR_NUM_OUT221_SEL_SEL174_MASK          (0xFFU)
126327 #define XBAR_NUM_OUT221_SEL_SEL174_SHIFT         (0U)
126328 /*! SEL174 - SEL174 */
126329 #define XBAR_NUM_OUT221_SEL_SEL174(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL174_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL174_MASK)
126330 
126331 #define XBAR_NUM_OUT221_SEL_SEL176_MASK          (0xFFU)
126332 #define XBAR_NUM_OUT221_SEL_SEL176_SHIFT         (0U)
126333 /*! SEL176 - SEL176 */
126334 #define XBAR_NUM_OUT221_SEL_SEL176(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL176_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL176_MASK)
126335 
126336 #define XBAR_NUM_OUT221_SEL_SEL178_MASK          (0xFFU)
126337 #define XBAR_NUM_OUT221_SEL_SEL178_SHIFT         (0U)
126338 /*! SEL178 - SEL178 */
126339 #define XBAR_NUM_OUT221_SEL_SEL178(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL178_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL178_MASK)
126340 
126341 #define XBAR_NUM_OUT221_SEL_SEL180_MASK          (0xFFU)
126342 #define XBAR_NUM_OUT221_SEL_SEL180_SHIFT         (0U)
126343 /*! SEL180 - SEL180 */
126344 #define XBAR_NUM_OUT221_SEL_SEL180(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL180_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL180_MASK)
126345 
126346 #define XBAR_NUM_OUT221_SEL_SEL182_MASK          (0xFFU)
126347 #define XBAR_NUM_OUT221_SEL_SEL182_SHIFT         (0U)
126348 /*! SEL182 - SEL182 */
126349 #define XBAR_NUM_OUT221_SEL_SEL182(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL182_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL182_MASK)
126350 
126351 #define XBAR_NUM_OUT221_SEL_SEL184_MASK          (0xFFU)
126352 #define XBAR_NUM_OUT221_SEL_SEL184_SHIFT         (0U)
126353 /*! SEL184 - SEL184 */
126354 #define XBAR_NUM_OUT221_SEL_SEL184(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL184_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL184_MASK)
126355 
126356 #define XBAR_NUM_OUT221_SEL_SEL186_MASK          (0xFFU)
126357 #define XBAR_NUM_OUT221_SEL_SEL186_SHIFT         (0U)
126358 /*! SEL186 - SEL186 */
126359 #define XBAR_NUM_OUT221_SEL_SEL186(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL186_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL186_MASK)
126360 
126361 #define XBAR_NUM_OUT221_SEL_SEL188_MASK          (0xFFU)
126362 #define XBAR_NUM_OUT221_SEL_SEL188_SHIFT         (0U)
126363 /*! SEL188 - SEL188 */
126364 #define XBAR_NUM_OUT221_SEL_SEL188(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL188_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL188_MASK)
126365 
126366 #define XBAR_NUM_OUT221_SEL_SEL190_MASK          (0xFFU)
126367 #define XBAR_NUM_OUT221_SEL_SEL190_SHIFT         (0U)
126368 /*! SEL190 - SEL190 */
126369 #define XBAR_NUM_OUT221_SEL_SEL190(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL190_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL190_MASK)
126370 
126371 #define XBAR_NUM_OUT221_SEL_SEL192_MASK          (0xFFU)
126372 #define XBAR_NUM_OUT221_SEL_SEL192_SHIFT         (0U)
126373 /*! SEL192 - SEL192 */
126374 #define XBAR_NUM_OUT221_SEL_SEL192(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL192_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL192_MASK)
126375 
126376 #define XBAR_NUM_OUT221_SEL_SEL194_MASK          (0xFFU)
126377 #define XBAR_NUM_OUT221_SEL_SEL194_SHIFT         (0U)
126378 /*! SEL194 - SEL194 */
126379 #define XBAR_NUM_OUT221_SEL_SEL194(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL194_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL194_MASK)
126380 
126381 #define XBAR_NUM_OUT221_SEL_SEL196_MASK          (0xFFU)
126382 #define XBAR_NUM_OUT221_SEL_SEL196_SHIFT         (0U)
126383 /*! SEL196 - SEL196 */
126384 #define XBAR_NUM_OUT221_SEL_SEL196(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL196_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL196_MASK)
126385 
126386 #define XBAR_NUM_OUT221_SEL_SEL198_MASK          (0xFFU)
126387 #define XBAR_NUM_OUT221_SEL_SEL198_SHIFT         (0U)
126388 /*! SEL198 - SEL198 */
126389 #define XBAR_NUM_OUT221_SEL_SEL198(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL198_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL198_MASK)
126390 
126391 #define XBAR_NUM_OUT221_SEL_SEL200_MASK          (0xFFU)
126392 #define XBAR_NUM_OUT221_SEL_SEL200_SHIFT         (0U)
126393 /*! SEL200 - SEL200 */
126394 #define XBAR_NUM_OUT221_SEL_SEL200(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL200_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL200_MASK)
126395 
126396 #define XBAR_NUM_OUT221_SEL_SEL202_MASK          (0xFFU)
126397 #define XBAR_NUM_OUT221_SEL_SEL202_SHIFT         (0U)
126398 /*! SEL202 - SEL202 */
126399 #define XBAR_NUM_OUT221_SEL_SEL202(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL202_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL202_MASK)
126400 
126401 #define XBAR_NUM_OUT221_SEL_SEL204_MASK          (0xFFU)
126402 #define XBAR_NUM_OUT221_SEL_SEL204_SHIFT         (0U)
126403 /*! SEL204 - SEL204 */
126404 #define XBAR_NUM_OUT221_SEL_SEL204(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL204_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL204_MASK)
126405 
126406 #define XBAR_NUM_OUT221_SEL_SEL206_MASK          (0xFFU)
126407 #define XBAR_NUM_OUT221_SEL_SEL206_SHIFT         (0U)
126408 /*! SEL206 - SEL206 */
126409 #define XBAR_NUM_OUT221_SEL_SEL206(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL206_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL206_MASK)
126410 
126411 #define XBAR_NUM_OUT221_SEL_SEL208_MASK          (0xFFU)
126412 #define XBAR_NUM_OUT221_SEL_SEL208_SHIFT         (0U)
126413 /*! SEL208 - SEL208 */
126414 #define XBAR_NUM_OUT221_SEL_SEL208(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL208_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL208_MASK)
126415 
126416 #define XBAR_NUM_OUT221_SEL_SEL210_MASK          (0xFFU)
126417 #define XBAR_NUM_OUT221_SEL_SEL210_SHIFT         (0U)
126418 /*! SEL210 - SEL210 */
126419 #define XBAR_NUM_OUT221_SEL_SEL210(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL210_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL210_MASK)
126420 
126421 #define XBAR_NUM_OUT221_SEL_SEL212_MASK          (0xFFU)
126422 #define XBAR_NUM_OUT221_SEL_SEL212_SHIFT         (0U)
126423 /*! SEL212 - SEL212 */
126424 #define XBAR_NUM_OUT221_SEL_SEL212(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL212_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL212_MASK)
126425 
126426 #define XBAR_NUM_OUT221_SEL_SEL214_MASK          (0xFFU)
126427 #define XBAR_NUM_OUT221_SEL_SEL214_SHIFT         (0U)
126428 /*! SEL214 - SEL214 */
126429 #define XBAR_NUM_OUT221_SEL_SEL214(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL214_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL214_MASK)
126430 
126431 #define XBAR_NUM_OUT221_SEL_SEL216_MASK          (0xFFU)
126432 #define XBAR_NUM_OUT221_SEL_SEL216_SHIFT         (0U)
126433 /*! SEL216 - SEL216 */
126434 #define XBAR_NUM_OUT221_SEL_SEL216(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL216_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL216_MASK)
126435 
126436 #define XBAR_NUM_OUT221_SEL_SEL218_MASK          (0xFFU)
126437 #define XBAR_NUM_OUT221_SEL_SEL218_SHIFT         (0U)
126438 /*! SEL218 - SEL218 */
126439 #define XBAR_NUM_OUT221_SEL_SEL218(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL218_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL218_MASK)
126440 
126441 #define XBAR_NUM_OUT221_SEL_SEL220_MASK          (0xFFU)
126442 #define XBAR_NUM_OUT221_SEL_SEL220_SHIFT         (0U)
126443 /*! SEL220 - SEL220 */
126444 #define XBAR_NUM_OUT221_SEL_SEL220(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL220_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL220_MASK)
126445 
126446 #define XBAR_NUM_OUT221_SEL_SEL1_MASK            (0xFF00U)
126447 #define XBAR_NUM_OUT221_SEL_SEL1_SHIFT           (8U)
126448 /*! SEL1 - SEL1 */
126449 #define XBAR_NUM_OUT221_SEL_SEL1(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL1_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL1_MASK)
126450 
126451 #define XBAR_NUM_OUT221_SEL_SEL3_MASK            (0xFF00U)
126452 #define XBAR_NUM_OUT221_SEL_SEL3_SHIFT           (8U)
126453 /*! SEL3 - SEL3 */
126454 #define XBAR_NUM_OUT221_SEL_SEL3(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL3_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL3_MASK)
126455 
126456 #define XBAR_NUM_OUT221_SEL_SEL5_MASK            (0xFF00U)
126457 #define XBAR_NUM_OUT221_SEL_SEL5_SHIFT           (8U)
126458 /*! SEL5 - SEL5 */
126459 #define XBAR_NUM_OUT221_SEL_SEL5(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL5_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL5_MASK)
126460 
126461 #define XBAR_NUM_OUT221_SEL_SEL7_MASK            (0xFF00U)
126462 #define XBAR_NUM_OUT221_SEL_SEL7_SHIFT           (8U)
126463 /*! SEL7 - SEL7 */
126464 #define XBAR_NUM_OUT221_SEL_SEL7(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL7_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL7_MASK)
126465 
126466 #define XBAR_NUM_OUT221_SEL_SEL9_MASK            (0xFF00U)
126467 #define XBAR_NUM_OUT221_SEL_SEL9_SHIFT           (8U)
126468 /*! SEL9 - SEL9 */
126469 #define XBAR_NUM_OUT221_SEL_SEL9(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL9_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL9_MASK)
126470 
126471 #define XBAR_NUM_OUT221_SEL_SEL11_MASK           (0xFF00U)
126472 #define XBAR_NUM_OUT221_SEL_SEL11_SHIFT          (8U)
126473 /*! SEL11 - SEL11 */
126474 #define XBAR_NUM_OUT221_SEL_SEL11(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL11_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL11_MASK)
126475 
126476 #define XBAR_NUM_OUT221_SEL_SEL13_MASK           (0xFF00U)
126477 #define XBAR_NUM_OUT221_SEL_SEL13_SHIFT          (8U)
126478 /*! SEL13 - SEL13 */
126479 #define XBAR_NUM_OUT221_SEL_SEL13(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL13_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL13_MASK)
126480 
126481 #define XBAR_NUM_OUT221_SEL_SEL15_MASK           (0xFF00U)
126482 #define XBAR_NUM_OUT221_SEL_SEL15_SHIFT          (8U)
126483 /*! SEL15 - SEL15 */
126484 #define XBAR_NUM_OUT221_SEL_SEL15(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL15_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL15_MASK)
126485 
126486 #define XBAR_NUM_OUT221_SEL_SEL17_MASK           (0xFF00U)
126487 #define XBAR_NUM_OUT221_SEL_SEL17_SHIFT          (8U)
126488 /*! SEL17 - SEL17 */
126489 #define XBAR_NUM_OUT221_SEL_SEL17(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL17_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL17_MASK)
126490 
126491 #define XBAR_NUM_OUT221_SEL_SEL19_MASK           (0xFF00U)
126492 #define XBAR_NUM_OUT221_SEL_SEL19_SHIFT          (8U)
126493 /*! SEL19 - SEL19 */
126494 #define XBAR_NUM_OUT221_SEL_SEL19(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL19_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL19_MASK)
126495 
126496 #define XBAR_NUM_OUT221_SEL_SEL21_MASK           (0xFF00U)
126497 #define XBAR_NUM_OUT221_SEL_SEL21_SHIFT          (8U)
126498 /*! SEL21 - SEL21 */
126499 #define XBAR_NUM_OUT221_SEL_SEL21(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL21_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL21_MASK)
126500 
126501 #define XBAR_NUM_OUT221_SEL_SEL23_MASK           (0xFF00U)
126502 #define XBAR_NUM_OUT221_SEL_SEL23_SHIFT          (8U)
126503 /*! SEL23 - SEL23 */
126504 #define XBAR_NUM_OUT221_SEL_SEL23(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL23_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL23_MASK)
126505 
126506 #define XBAR_NUM_OUT221_SEL_SEL25_MASK           (0xFF00U)
126507 #define XBAR_NUM_OUT221_SEL_SEL25_SHIFT          (8U)
126508 /*! SEL25 - SEL25 */
126509 #define XBAR_NUM_OUT221_SEL_SEL25(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL25_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL25_MASK)
126510 
126511 #define XBAR_NUM_OUT221_SEL_SEL27_MASK           (0xFF00U)
126512 #define XBAR_NUM_OUT221_SEL_SEL27_SHIFT          (8U)
126513 /*! SEL27 - SEL27 */
126514 #define XBAR_NUM_OUT221_SEL_SEL27(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL27_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL27_MASK)
126515 
126516 #define XBAR_NUM_OUT221_SEL_SEL29_MASK           (0xFF00U)
126517 #define XBAR_NUM_OUT221_SEL_SEL29_SHIFT          (8U)
126518 /*! SEL29 - SEL29 */
126519 #define XBAR_NUM_OUT221_SEL_SEL29(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL29_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL29_MASK)
126520 
126521 #define XBAR_NUM_OUT221_SEL_SEL31_MASK           (0xFF00U)
126522 #define XBAR_NUM_OUT221_SEL_SEL31_SHIFT          (8U)
126523 /*! SEL31 - SEL31 */
126524 #define XBAR_NUM_OUT221_SEL_SEL31(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL31_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL31_MASK)
126525 
126526 #define XBAR_NUM_OUT221_SEL_SEL33_MASK           (0xFF00U)
126527 #define XBAR_NUM_OUT221_SEL_SEL33_SHIFT          (8U)
126528 /*! SEL33 - SEL33 */
126529 #define XBAR_NUM_OUT221_SEL_SEL33(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL33_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL33_MASK)
126530 
126531 #define XBAR_NUM_OUT221_SEL_SEL35_MASK           (0xFF00U)
126532 #define XBAR_NUM_OUT221_SEL_SEL35_SHIFT          (8U)
126533 /*! SEL35 - SEL35 */
126534 #define XBAR_NUM_OUT221_SEL_SEL35(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL35_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL35_MASK)
126535 
126536 #define XBAR_NUM_OUT221_SEL_SEL37_MASK           (0xFF00U)
126537 #define XBAR_NUM_OUT221_SEL_SEL37_SHIFT          (8U)
126538 /*! SEL37 - SEL37 */
126539 #define XBAR_NUM_OUT221_SEL_SEL37(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL37_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL37_MASK)
126540 
126541 #define XBAR_NUM_OUT221_SEL_SEL39_MASK           (0xFF00U)
126542 #define XBAR_NUM_OUT221_SEL_SEL39_SHIFT          (8U)
126543 /*! SEL39 - SEL39 */
126544 #define XBAR_NUM_OUT221_SEL_SEL39(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL39_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL39_MASK)
126545 
126546 #define XBAR_NUM_OUT221_SEL_SEL41_MASK           (0xFF00U)
126547 #define XBAR_NUM_OUT221_SEL_SEL41_SHIFT          (8U)
126548 /*! SEL41 - SEL41 */
126549 #define XBAR_NUM_OUT221_SEL_SEL41(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL41_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL41_MASK)
126550 
126551 #define XBAR_NUM_OUT221_SEL_SEL43_MASK           (0xFF00U)
126552 #define XBAR_NUM_OUT221_SEL_SEL43_SHIFT          (8U)
126553 /*! SEL43 - SEL43 */
126554 #define XBAR_NUM_OUT221_SEL_SEL43(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL43_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL43_MASK)
126555 
126556 #define XBAR_NUM_OUT221_SEL_SEL45_MASK           (0xFF00U)
126557 #define XBAR_NUM_OUT221_SEL_SEL45_SHIFT          (8U)
126558 /*! SEL45 - SEL45 */
126559 #define XBAR_NUM_OUT221_SEL_SEL45(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL45_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL45_MASK)
126560 
126561 #define XBAR_NUM_OUT221_SEL_SEL47_MASK           (0xFF00U)
126562 #define XBAR_NUM_OUT221_SEL_SEL47_SHIFT          (8U)
126563 /*! SEL47 - SEL47 */
126564 #define XBAR_NUM_OUT221_SEL_SEL47(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL47_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL47_MASK)
126565 
126566 #define XBAR_NUM_OUT221_SEL_SEL49_MASK           (0xFF00U)
126567 #define XBAR_NUM_OUT221_SEL_SEL49_SHIFT          (8U)
126568 /*! SEL49 - SEL49 */
126569 #define XBAR_NUM_OUT221_SEL_SEL49(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL49_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL49_MASK)
126570 
126571 #define XBAR_NUM_OUT221_SEL_SEL51_MASK           (0xFF00U)
126572 #define XBAR_NUM_OUT221_SEL_SEL51_SHIFT          (8U)
126573 /*! SEL51 - SEL51 */
126574 #define XBAR_NUM_OUT221_SEL_SEL51(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL51_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL51_MASK)
126575 
126576 #define XBAR_NUM_OUT221_SEL_SEL53_MASK           (0xFF00U)
126577 #define XBAR_NUM_OUT221_SEL_SEL53_SHIFT          (8U)
126578 /*! SEL53 - SEL53 */
126579 #define XBAR_NUM_OUT221_SEL_SEL53(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL53_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL53_MASK)
126580 
126581 #define XBAR_NUM_OUT221_SEL_SEL55_MASK           (0xFF00U)
126582 #define XBAR_NUM_OUT221_SEL_SEL55_SHIFT          (8U)
126583 /*! SEL55 - SEL55 */
126584 #define XBAR_NUM_OUT221_SEL_SEL55(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL55_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL55_MASK)
126585 
126586 #define XBAR_NUM_OUT221_SEL_SEL57_MASK           (0xFF00U)
126587 #define XBAR_NUM_OUT221_SEL_SEL57_SHIFT          (8U)
126588 /*! SEL57 - SEL57 */
126589 #define XBAR_NUM_OUT221_SEL_SEL57(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL57_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL57_MASK)
126590 
126591 #define XBAR_NUM_OUT221_SEL_SEL59_MASK           (0xFF00U)
126592 #define XBAR_NUM_OUT221_SEL_SEL59_SHIFT          (8U)
126593 /*! SEL59 - SEL59 */
126594 #define XBAR_NUM_OUT221_SEL_SEL59(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL59_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL59_MASK)
126595 
126596 #define XBAR_NUM_OUT221_SEL_SEL61_MASK           (0xFF00U)
126597 #define XBAR_NUM_OUT221_SEL_SEL61_SHIFT          (8U)
126598 /*! SEL61 - SEL61 */
126599 #define XBAR_NUM_OUT221_SEL_SEL61(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL61_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL61_MASK)
126600 
126601 #define XBAR_NUM_OUT221_SEL_SEL63_MASK           (0xFF00U)
126602 #define XBAR_NUM_OUT221_SEL_SEL63_SHIFT          (8U)
126603 /*! SEL63 - SEL63 */
126604 #define XBAR_NUM_OUT221_SEL_SEL63(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL63_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL63_MASK)
126605 
126606 #define XBAR_NUM_OUT221_SEL_SEL65_MASK           (0xFF00U)
126607 #define XBAR_NUM_OUT221_SEL_SEL65_SHIFT          (8U)
126608 /*! SEL65 - SEL65 */
126609 #define XBAR_NUM_OUT221_SEL_SEL65(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL65_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL65_MASK)
126610 
126611 #define XBAR_NUM_OUT221_SEL_SEL67_MASK           (0xFF00U)
126612 #define XBAR_NUM_OUT221_SEL_SEL67_SHIFT          (8U)
126613 /*! SEL67 - SEL67 */
126614 #define XBAR_NUM_OUT221_SEL_SEL67(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL67_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL67_MASK)
126615 
126616 #define XBAR_NUM_OUT221_SEL_SEL69_MASK           (0xFF00U)
126617 #define XBAR_NUM_OUT221_SEL_SEL69_SHIFT          (8U)
126618 /*! SEL69 - SEL69 */
126619 #define XBAR_NUM_OUT221_SEL_SEL69(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL69_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL69_MASK)
126620 
126621 #define XBAR_NUM_OUT221_SEL_SEL71_MASK           (0xFF00U)
126622 #define XBAR_NUM_OUT221_SEL_SEL71_SHIFT          (8U)
126623 /*! SEL71 - SEL71 */
126624 #define XBAR_NUM_OUT221_SEL_SEL71(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL71_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL71_MASK)
126625 
126626 #define XBAR_NUM_OUT221_SEL_SEL73_MASK           (0xFF00U)
126627 #define XBAR_NUM_OUT221_SEL_SEL73_SHIFT          (8U)
126628 /*! SEL73 - SEL73 */
126629 #define XBAR_NUM_OUT221_SEL_SEL73(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL73_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL73_MASK)
126630 
126631 #define XBAR_NUM_OUT221_SEL_SEL75_MASK           (0xFF00U)
126632 #define XBAR_NUM_OUT221_SEL_SEL75_SHIFT          (8U)
126633 /*! SEL75 - SEL75 */
126634 #define XBAR_NUM_OUT221_SEL_SEL75(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL75_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL75_MASK)
126635 
126636 #define XBAR_NUM_OUT221_SEL_SEL77_MASK           (0xFF00U)
126637 #define XBAR_NUM_OUT221_SEL_SEL77_SHIFT          (8U)
126638 /*! SEL77 - SEL77 */
126639 #define XBAR_NUM_OUT221_SEL_SEL77(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL77_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL77_MASK)
126640 
126641 #define XBAR_NUM_OUT221_SEL_SEL79_MASK           (0xFF00U)
126642 #define XBAR_NUM_OUT221_SEL_SEL79_SHIFT          (8U)
126643 /*! SEL79 - SEL79 */
126644 #define XBAR_NUM_OUT221_SEL_SEL79(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL79_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL79_MASK)
126645 
126646 #define XBAR_NUM_OUT221_SEL_SEL81_MASK           (0xFF00U)
126647 #define XBAR_NUM_OUT221_SEL_SEL81_SHIFT          (8U)
126648 /*! SEL81 - SEL81 */
126649 #define XBAR_NUM_OUT221_SEL_SEL81(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL81_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL81_MASK)
126650 
126651 #define XBAR_NUM_OUT221_SEL_SEL83_MASK           (0xFF00U)
126652 #define XBAR_NUM_OUT221_SEL_SEL83_SHIFT          (8U)
126653 /*! SEL83 - SEL83 */
126654 #define XBAR_NUM_OUT221_SEL_SEL83(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL83_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL83_MASK)
126655 
126656 #define XBAR_NUM_OUT221_SEL_SEL85_MASK           (0xFF00U)
126657 #define XBAR_NUM_OUT221_SEL_SEL85_SHIFT          (8U)
126658 /*! SEL85 - SEL85 */
126659 #define XBAR_NUM_OUT221_SEL_SEL85(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL85_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL85_MASK)
126660 
126661 #define XBAR_NUM_OUT221_SEL_SEL87_MASK           (0xFF00U)
126662 #define XBAR_NUM_OUT221_SEL_SEL87_SHIFT          (8U)
126663 /*! SEL87 - SEL87 */
126664 #define XBAR_NUM_OUT221_SEL_SEL87(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL87_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL87_MASK)
126665 
126666 #define XBAR_NUM_OUT221_SEL_SEL89_MASK           (0xFF00U)
126667 #define XBAR_NUM_OUT221_SEL_SEL89_SHIFT          (8U)
126668 /*! SEL89 - SEL89 */
126669 #define XBAR_NUM_OUT221_SEL_SEL89(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL89_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL89_MASK)
126670 
126671 #define XBAR_NUM_OUT221_SEL_SEL91_MASK           (0xFF00U)
126672 #define XBAR_NUM_OUT221_SEL_SEL91_SHIFT          (8U)
126673 /*! SEL91 - SEL91 */
126674 #define XBAR_NUM_OUT221_SEL_SEL91(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL91_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL91_MASK)
126675 
126676 #define XBAR_NUM_OUT221_SEL_SEL93_MASK           (0xFF00U)
126677 #define XBAR_NUM_OUT221_SEL_SEL93_SHIFT          (8U)
126678 /*! SEL93 - SEL93 */
126679 #define XBAR_NUM_OUT221_SEL_SEL93(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL93_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL93_MASK)
126680 
126681 #define XBAR_NUM_OUT221_SEL_SEL95_MASK           (0xFF00U)
126682 #define XBAR_NUM_OUT221_SEL_SEL95_SHIFT          (8U)
126683 /*! SEL95 - SEL95 */
126684 #define XBAR_NUM_OUT221_SEL_SEL95(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL95_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL95_MASK)
126685 
126686 #define XBAR_NUM_OUT221_SEL_SEL97_MASK           (0xFF00U)
126687 #define XBAR_NUM_OUT221_SEL_SEL97_SHIFT          (8U)
126688 /*! SEL97 - SEL97 */
126689 #define XBAR_NUM_OUT221_SEL_SEL97(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL97_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL97_MASK)
126690 
126691 #define XBAR_NUM_OUT221_SEL_SEL99_MASK           (0xFF00U)
126692 #define XBAR_NUM_OUT221_SEL_SEL99_SHIFT          (8U)
126693 /*! SEL99 - SEL99 */
126694 #define XBAR_NUM_OUT221_SEL_SEL99(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL99_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL99_MASK)
126695 
126696 #define XBAR_NUM_OUT221_SEL_SEL101_MASK          (0xFF00U)
126697 #define XBAR_NUM_OUT221_SEL_SEL101_SHIFT         (8U)
126698 /*! SEL101 - SEL101 */
126699 #define XBAR_NUM_OUT221_SEL_SEL101(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL101_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL101_MASK)
126700 
126701 #define XBAR_NUM_OUT221_SEL_SEL103_MASK          (0xFF00U)
126702 #define XBAR_NUM_OUT221_SEL_SEL103_SHIFT         (8U)
126703 /*! SEL103 - SEL103 */
126704 #define XBAR_NUM_OUT221_SEL_SEL103(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL103_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL103_MASK)
126705 
126706 #define XBAR_NUM_OUT221_SEL_SEL105_MASK          (0xFF00U)
126707 #define XBAR_NUM_OUT221_SEL_SEL105_SHIFT         (8U)
126708 /*! SEL105 - SEL105 */
126709 #define XBAR_NUM_OUT221_SEL_SEL105(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL105_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL105_MASK)
126710 
126711 #define XBAR_NUM_OUT221_SEL_SEL107_MASK          (0xFF00U)
126712 #define XBAR_NUM_OUT221_SEL_SEL107_SHIFT         (8U)
126713 /*! SEL107 - SEL107 */
126714 #define XBAR_NUM_OUT221_SEL_SEL107(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL107_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL107_MASK)
126715 
126716 #define XBAR_NUM_OUT221_SEL_SEL109_MASK          (0xFF00U)
126717 #define XBAR_NUM_OUT221_SEL_SEL109_SHIFT         (8U)
126718 /*! SEL109 - SEL109 */
126719 #define XBAR_NUM_OUT221_SEL_SEL109(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL109_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL109_MASK)
126720 
126721 #define XBAR_NUM_OUT221_SEL_SEL111_MASK          (0xFF00U)
126722 #define XBAR_NUM_OUT221_SEL_SEL111_SHIFT         (8U)
126723 /*! SEL111 - SEL111 */
126724 #define XBAR_NUM_OUT221_SEL_SEL111(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL111_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL111_MASK)
126725 
126726 #define XBAR_NUM_OUT221_SEL_SEL113_MASK          (0xFF00U)
126727 #define XBAR_NUM_OUT221_SEL_SEL113_SHIFT         (8U)
126728 /*! SEL113 - SEL113 */
126729 #define XBAR_NUM_OUT221_SEL_SEL113(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL113_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL113_MASK)
126730 
126731 #define XBAR_NUM_OUT221_SEL_SEL115_MASK          (0xFF00U)
126732 #define XBAR_NUM_OUT221_SEL_SEL115_SHIFT         (8U)
126733 /*! SEL115 - SEL115 */
126734 #define XBAR_NUM_OUT221_SEL_SEL115(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL115_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL115_MASK)
126735 
126736 #define XBAR_NUM_OUT221_SEL_SEL117_MASK          (0xFF00U)
126737 #define XBAR_NUM_OUT221_SEL_SEL117_SHIFT         (8U)
126738 /*! SEL117 - SEL117 */
126739 #define XBAR_NUM_OUT221_SEL_SEL117(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL117_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL117_MASK)
126740 
126741 #define XBAR_NUM_OUT221_SEL_SEL119_MASK          (0xFF00U)
126742 #define XBAR_NUM_OUT221_SEL_SEL119_SHIFT         (8U)
126743 /*! SEL119 - SEL119 */
126744 #define XBAR_NUM_OUT221_SEL_SEL119(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL119_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL119_MASK)
126745 
126746 #define XBAR_NUM_OUT221_SEL_SEL121_MASK          (0xFF00U)
126747 #define XBAR_NUM_OUT221_SEL_SEL121_SHIFT         (8U)
126748 /*! SEL121 - SEL121 */
126749 #define XBAR_NUM_OUT221_SEL_SEL121(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL121_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL121_MASK)
126750 
126751 #define XBAR_NUM_OUT221_SEL_SEL123_MASK          (0xFF00U)
126752 #define XBAR_NUM_OUT221_SEL_SEL123_SHIFT         (8U)
126753 /*! SEL123 - SEL123 */
126754 #define XBAR_NUM_OUT221_SEL_SEL123(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL123_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL123_MASK)
126755 
126756 #define XBAR_NUM_OUT221_SEL_SEL125_MASK          (0xFF00U)
126757 #define XBAR_NUM_OUT221_SEL_SEL125_SHIFT         (8U)
126758 /*! SEL125 - SEL125 */
126759 #define XBAR_NUM_OUT221_SEL_SEL125(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL125_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL125_MASK)
126760 
126761 #define XBAR_NUM_OUT221_SEL_SEL127_MASK          (0xFF00U)
126762 #define XBAR_NUM_OUT221_SEL_SEL127_SHIFT         (8U)
126763 /*! SEL127 - SEL127 */
126764 #define XBAR_NUM_OUT221_SEL_SEL127(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL127_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL127_MASK)
126765 
126766 #define XBAR_NUM_OUT221_SEL_SEL129_MASK          (0xFF00U)
126767 #define XBAR_NUM_OUT221_SEL_SEL129_SHIFT         (8U)
126768 /*! SEL129 - SEL129 */
126769 #define XBAR_NUM_OUT221_SEL_SEL129(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL129_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL129_MASK)
126770 
126771 #define XBAR_NUM_OUT221_SEL_SEL131_MASK          (0xFF00U)
126772 #define XBAR_NUM_OUT221_SEL_SEL131_SHIFT         (8U)
126773 /*! SEL131 - SEL131 */
126774 #define XBAR_NUM_OUT221_SEL_SEL131(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL131_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL131_MASK)
126775 
126776 #define XBAR_NUM_OUT221_SEL_SEL133_MASK          (0xFF00U)
126777 #define XBAR_NUM_OUT221_SEL_SEL133_SHIFT         (8U)
126778 /*! SEL133 - SEL133 */
126779 #define XBAR_NUM_OUT221_SEL_SEL133(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL133_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL133_MASK)
126780 
126781 #define XBAR_NUM_OUT221_SEL_SEL135_MASK          (0xFF00U)
126782 #define XBAR_NUM_OUT221_SEL_SEL135_SHIFT         (8U)
126783 /*! SEL135 - SEL135 */
126784 #define XBAR_NUM_OUT221_SEL_SEL135(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL135_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL135_MASK)
126785 
126786 #define XBAR_NUM_OUT221_SEL_SEL137_MASK          (0xFF00U)
126787 #define XBAR_NUM_OUT221_SEL_SEL137_SHIFT         (8U)
126788 /*! SEL137 - SEL137 */
126789 #define XBAR_NUM_OUT221_SEL_SEL137(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL137_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL137_MASK)
126790 
126791 #define XBAR_NUM_OUT221_SEL_SEL139_MASK          (0xFF00U)
126792 #define XBAR_NUM_OUT221_SEL_SEL139_SHIFT         (8U)
126793 /*! SEL139 - SEL139 */
126794 #define XBAR_NUM_OUT221_SEL_SEL139(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL139_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL139_MASK)
126795 
126796 #define XBAR_NUM_OUT221_SEL_SEL141_MASK          (0xFF00U)
126797 #define XBAR_NUM_OUT221_SEL_SEL141_SHIFT         (8U)
126798 /*! SEL141 - SEL141 */
126799 #define XBAR_NUM_OUT221_SEL_SEL141(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL141_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL141_MASK)
126800 
126801 #define XBAR_NUM_OUT221_SEL_SEL143_MASK          (0xFF00U)
126802 #define XBAR_NUM_OUT221_SEL_SEL143_SHIFT         (8U)
126803 /*! SEL143 - SEL143 */
126804 #define XBAR_NUM_OUT221_SEL_SEL143(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL143_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL143_MASK)
126805 
126806 #define XBAR_NUM_OUT221_SEL_SEL145_MASK          (0xFF00U)
126807 #define XBAR_NUM_OUT221_SEL_SEL145_SHIFT         (8U)
126808 /*! SEL145 - SEL145 */
126809 #define XBAR_NUM_OUT221_SEL_SEL145(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL145_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL145_MASK)
126810 
126811 #define XBAR_NUM_OUT221_SEL_SEL147_MASK          (0xFF00U)
126812 #define XBAR_NUM_OUT221_SEL_SEL147_SHIFT         (8U)
126813 /*! SEL147 - SEL147 */
126814 #define XBAR_NUM_OUT221_SEL_SEL147(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL147_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL147_MASK)
126815 
126816 #define XBAR_NUM_OUT221_SEL_SEL149_MASK          (0xFF00U)
126817 #define XBAR_NUM_OUT221_SEL_SEL149_SHIFT         (8U)
126818 /*! SEL149 - SEL149 */
126819 #define XBAR_NUM_OUT221_SEL_SEL149(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL149_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL149_MASK)
126820 
126821 #define XBAR_NUM_OUT221_SEL_SEL151_MASK          (0xFF00U)
126822 #define XBAR_NUM_OUT221_SEL_SEL151_SHIFT         (8U)
126823 /*! SEL151 - SEL151 */
126824 #define XBAR_NUM_OUT221_SEL_SEL151(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL151_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL151_MASK)
126825 
126826 #define XBAR_NUM_OUT221_SEL_SEL153_MASK          (0xFF00U)
126827 #define XBAR_NUM_OUT221_SEL_SEL153_SHIFT         (8U)
126828 /*! SEL153 - SEL153 */
126829 #define XBAR_NUM_OUT221_SEL_SEL153(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL153_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL153_MASK)
126830 
126831 #define XBAR_NUM_OUT221_SEL_SEL155_MASK          (0xFF00U)
126832 #define XBAR_NUM_OUT221_SEL_SEL155_SHIFT         (8U)
126833 /*! SEL155 - SEL155 */
126834 #define XBAR_NUM_OUT221_SEL_SEL155(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL155_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL155_MASK)
126835 
126836 #define XBAR_NUM_OUT221_SEL_SEL157_MASK          (0xFF00U)
126837 #define XBAR_NUM_OUT221_SEL_SEL157_SHIFT         (8U)
126838 /*! SEL157 - SEL157 */
126839 #define XBAR_NUM_OUT221_SEL_SEL157(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL157_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL157_MASK)
126840 
126841 #define XBAR_NUM_OUT221_SEL_SEL159_MASK          (0xFF00U)
126842 #define XBAR_NUM_OUT221_SEL_SEL159_SHIFT         (8U)
126843 /*! SEL159 - SEL159 */
126844 #define XBAR_NUM_OUT221_SEL_SEL159(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL159_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL159_MASK)
126845 
126846 #define XBAR_NUM_OUT221_SEL_SEL161_MASK          (0xFF00U)
126847 #define XBAR_NUM_OUT221_SEL_SEL161_SHIFT         (8U)
126848 /*! SEL161 - SEL161 */
126849 #define XBAR_NUM_OUT221_SEL_SEL161(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL161_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL161_MASK)
126850 
126851 #define XBAR_NUM_OUT221_SEL_SEL163_MASK          (0xFF00U)
126852 #define XBAR_NUM_OUT221_SEL_SEL163_SHIFT         (8U)
126853 /*! SEL163 - SEL163 */
126854 #define XBAR_NUM_OUT221_SEL_SEL163(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL163_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL163_MASK)
126855 
126856 #define XBAR_NUM_OUT221_SEL_SEL165_MASK          (0xFF00U)
126857 #define XBAR_NUM_OUT221_SEL_SEL165_SHIFT         (8U)
126858 /*! SEL165 - SEL165 */
126859 #define XBAR_NUM_OUT221_SEL_SEL165(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL165_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL165_MASK)
126860 
126861 #define XBAR_NUM_OUT221_SEL_SEL167_MASK          (0xFF00U)
126862 #define XBAR_NUM_OUT221_SEL_SEL167_SHIFT         (8U)
126863 /*! SEL167 - SEL167 */
126864 #define XBAR_NUM_OUT221_SEL_SEL167(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL167_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL167_MASK)
126865 
126866 #define XBAR_NUM_OUT221_SEL_SEL169_MASK          (0xFF00U)
126867 #define XBAR_NUM_OUT221_SEL_SEL169_SHIFT         (8U)
126868 /*! SEL169 - SEL169 */
126869 #define XBAR_NUM_OUT221_SEL_SEL169(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL169_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL169_MASK)
126870 
126871 #define XBAR_NUM_OUT221_SEL_SEL171_MASK          (0xFF00U)
126872 #define XBAR_NUM_OUT221_SEL_SEL171_SHIFT         (8U)
126873 /*! SEL171 - SEL171 */
126874 #define XBAR_NUM_OUT221_SEL_SEL171(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL171_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL171_MASK)
126875 
126876 #define XBAR_NUM_OUT221_SEL_SEL173_MASK          (0xFF00U)
126877 #define XBAR_NUM_OUT221_SEL_SEL173_SHIFT         (8U)
126878 /*! SEL173 - SEL173 */
126879 #define XBAR_NUM_OUT221_SEL_SEL173(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL173_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL173_MASK)
126880 
126881 #define XBAR_NUM_OUT221_SEL_SEL175_MASK          (0xFF00U)
126882 #define XBAR_NUM_OUT221_SEL_SEL175_SHIFT         (8U)
126883 /*! SEL175 - SEL175 */
126884 #define XBAR_NUM_OUT221_SEL_SEL175(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL175_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL175_MASK)
126885 
126886 #define XBAR_NUM_OUT221_SEL_SEL177_MASK          (0xFF00U)
126887 #define XBAR_NUM_OUT221_SEL_SEL177_SHIFT         (8U)
126888 /*! SEL177 - SEL177 */
126889 #define XBAR_NUM_OUT221_SEL_SEL177(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL177_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL177_MASK)
126890 
126891 #define XBAR_NUM_OUT221_SEL_SEL179_MASK          (0xFF00U)
126892 #define XBAR_NUM_OUT221_SEL_SEL179_SHIFT         (8U)
126893 /*! SEL179 - SEL179 */
126894 #define XBAR_NUM_OUT221_SEL_SEL179(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL179_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL179_MASK)
126895 
126896 #define XBAR_NUM_OUT221_SEL_SEL181_MASK          (0xFF00U)
126897 #define XBAR_NUM_OUT221_SEL_SEL181_SHIFT         (8U)
126898 /*! SEL181 - SEL181 */
126899 #define XBAR_NUM_OUT221_SEL_SEL181(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL181_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL181_MASK)
126900 
126901 #define XBAR_NUM_OUT221_SEL_SEL183_MASK          (0xFF00U)
126902 #define XBAR_NUM_OUT221_SEL_SEL183_SHIFT         (8U)
126903 /*! SEL183 - SEL183 */
126904 #define XBAR_NUM_OUT221_SEL_SEL183(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL183_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL183_MASK)
126905 
126906 #define XBAR_NUM_OUT221_SEL_SEL185_MASK          (0xFF00U)
126907 #define XBAR_NUM_OUT221_SEL_SEL185_SHIFT         (8U)
126908 /*! SEL185 - SEL185 */
126909 #define XBAR_NUM_OUT221_SEL_SEL185(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL185_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL185_MASK)
126910 
126911 #define XBAR_NUM_OUT221_SEL_SEL187_MASK          (0xFF00U)
126912 #define XBAR_NUM_OUT221_SEL_SEL187_SHIFT         (8U)
126913 /*! SEL187 - SEL187 */
126914 #define XBAR_NUM_OUT221_SEL_SEL187(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL187_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL187_MASK)
126915 
126916 #define XBAR_NUM_OUT221_SEL_SEL189_MASK          (0xFF00U)
126917 #define XBAR_NUM_OUT221_SEL_SEL189_SHIFT         (8U)
126918 /*! SEL189 - SEL189 */
126919 #define XBAR_NUM_OUT221_SEL_SEL189(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL189_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL189_MASK)
126920 
126921 #define XBAR_NUM_OUT221_SEL_SEL191_MASK          (0xFF00U)
126922 #define XBAR_NUM_OUT221_SEL_SEL191_SHIFT         (8U)
126923 /*! SEL191 - SEL191 */
126924 #define XBAR_NUM_OUT221_SEL_SEL191(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL191_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL191_MASK)
126925 
126926 #define XBAR_NUM_OUT221_SEL_SEL193_MASK          (0xFF00U)
126927 #define XBAR_NUM_OUT221_SEL_SEL193_SHIFT         (8U)
126928 /*! SEL193 - SEL193 */
126929 #define XBAR_NUM_OUT221_SEL_SEL193(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL193_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL193_MASK)
126930 
126931 #define XBAR_NUM_OUT221_SEL_SEL195_MASK          (0xFF00U)
126932 #define XBAR_NUM_OUT221_SEL_SEL195_SHIFT         (8U)
126933 /*! SEL195 - SEL195 */
126934 #define XBAR_NUM_OUT221_SEL_SEL195(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL195_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL195_MASK)
126935 
126936 #define XBAR_NUM_OUT221_SEL_SEL197_MASK          (0xFF00U)
126937 #define XBAR_NUM_OUT221_SEL_SEL197_SHIFT         (8U)
126938 /*! SEL197 - SEL197 */
126939 #define XBAR_NUM_OUT221_SEL_SEL197(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL197_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL197_MASK)
126940 
126941 #define XBAR_NUM_OUT221_SEL_SEL199_MASK          (0xFF00U)
126942 #define XBAR_NUM_OUT221_SEL_SEL199_SHIFT         (8U)
126943 /*! SEL199 - SEL199 */
126944 #define XBAR_NUM_OUT221_SEL_SEL199(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL199_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL199_MASK)
126945 
126946 #define XBAR_NUM_OUT221_SEL_SEL201_MASK          (0xFF00U)
126947 #define XBAR_NUM_OUT221_SEL_SEL201_SHIFT         (8U)
126948 /*! SEL201 - SEL201 */
126949 #define XBAR_NUM_OUT221_SEL_SEL201(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL201_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL201_MASK)
126950 
126951 #define XBAR_NUM_OUT221_SEL_SEL203_MASK          (0xFF00U)
126952 #define XBAR_NUM_OUT221_SEL_SEL203_SHIFT         (8U)
126953 /*! SEL203 - SEL203 */
126954 #define XBAR_NUM_OUT221_SEL_SEL203(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL203_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL203_MASK)
126955 
126956 #define XBAR_NUM_OUT221_SEL_SEL205_MASK          (0xFF00U)
126957 #define XBAR_NUM_OUT221_SEL_SEL205_SHIFT         (8U)
126958 /*! SEL205 - SEL205 */
126959 #define XBAR_NUM_OUT221_SEL_SEL205(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL205_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL205_MASK)
126960 
126961 #define XBAR_NUM_OUT221_SEL_SEL207_MASK          (0xFF00U)
126962 #define XBAR_NUM_OUT221_SEL_SEL207_SHIFT         (8U)
126963 /*! SEL207 - SEL207 */
126964 #define XBAR_NUM_OUT221_SEL_SEL207(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL207_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL207_MASK)
126965 
126966 #define XBAR_NUM_OUT221_SEL_SEL209_MASK          (0xFF00U)
126967 #define XBAR_NUM_OUT221_SEL_SEL209_SHIFT         (8U)
126968 /*! SEL209 - SEL209 */
126969 #define XBAR_NUM_OUT221_SEL_SEL209(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL209_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL209_MASK)
126970 
126971 #define XBAR_NUM_OUT221_SEL_SEL211_MASK          (0xFF00U)
126972 #define XBAR_NUM_OUT221_SEL_SEL211_SHIFT         (8U)
126973 /*! SEL211 - SEL211 */
126974 #define XBAR_NUM_OUT221_SEL_SEL211(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL211_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL211_MASK)
126975 
126976 #define XBAR_NUM_OUT221_SEL_SEL213_MASK          (0xFF00U)
126977 #define XBAR_NUM_OUT221_SEL_SEL213_SHIFT         (8U)
126978 /*! SEL213 - SEL213 */
126979 #define XBAR_NUM_OUT221_SEL_SEL213(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL213_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL213_MASK)
126980 
126981 #define XBAR_NUM_OUT221_SEL_SEL215_MASK          (0xFF00U)
126982 #define XBAR_NUM_OUT221_SEL_SEL215_SHIFT         (8U)
126983 /*! SEL215 - SEL215 */
126984 #define XBAR_NUM_OUT221_SEL_SEL215(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL215_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL215_MASK)
126985 
126986 #define XBAR_NUM_OUT221_SEL_SEL217_MASK          (0xFF00U)
126987 #define XBAR_NUM_OUT221_SEL_SEL217_SHIFT         (8U)
126988 /*! SEL217 - SEL217 */
126989 #define XBAR_NUM_OUT221_SEL_SEL217(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL217_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL217_MASK)
126990 
126991 #define XBAR_NUM_OUT221_SEL_SEL219_MASK          (0xFF00U)
126992 #define XBAR_NUM_OUT221_SEL_SEL219_SHIFT         (8U)
126993 /*! SEL219 - SEL219 */
126994 #define XBAR_NUM_OUT221_SEL_SEL219(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_SEL_SEL219_SHIFT)) & XBAR_NUM_OUT221_SEL_SEL219_MASK)
126995 /*! @} */
126996 
126997 /* The count of XBAR_NUM_OUT221_SEL */
126998 #define XBAR_NUM_OUT221_SEL_COUNT                (111U)
126999 
127000 /*! @name CTRL - Crossbar Control Register */
127001 /*! @{ */
127002 
127003 #define XBAR_NUM_OUT221_CTRL_DEN0_MASK           (0x1U)
127004 #define XBAR_NUM_OUT221_CTRL_DEN0_SHIFT          (0U)
127005 /*! DEN0 - DMA Enable for XBAR_OUT0
127006  *  0b0..DMA disabled
127007  *  0b1..DMA enabled
127008  */
127009 #define XBAR_NUM_OUT221_CTRL_DEN0(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_DEN0_SHIFT)) & XBAR_NUM_OUT221_CTRL_DEN0_MASK)
127010 
127011 #define XBAR_NUM_OUT221_CTRL_DEN2_MASK           (0x1U)
127012 #define XBAR_NUM_OUT221_CTRL_DEN2_SHIFT          (0U)
127013 /*! DEN2 - DMA Enable for XBAR_OUT2
127014  *  0b0..DMA disabled
127015  *  0b1..DMA enabled
127016  */
127017 #define XBAR_NUM_OUT221_CTRL_DEN2(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_DEN2_SHIFT)) & XBAR_NUM_OUT221_CTRL_DEN2_MASK)
127018 
127019 #define XBAR_NUM_OUT221_CTRL_IEN0_MASK           (0x2U)
127020 #define XBAR_NUM_OUT221_CTRL_IEN0_SHIFT          (1U)
127021 /*! IEN0 - Interrupt Enable for XBAR_OUT0
127022  *  0b0..Interrupt disabled
127023  *  0b1..Interrupt enabled
127024  */
127025 #define XBAR_NUM_OUT221_CTRL_IEN0(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_IEN0_SHIFT)) & XBAR_NUM_OUT221_CTRL_IEN0_MASK)
127026 
127027 #define XBAR_NUM_OUT221_CTRL_IEN2_MASK           (0x2U)
127028 #define XBAR_NUM_OUT221_CTRL_IEN2_SHIFT          (1U)
127029 /*! IEN2 - Interrupt Enable for XBAR_OUT2
127030  *  0b0..Interrupt disabled
127031  *  0b1..Interrupt enabled
127032  */
127033 #define XBAR_NUM_OUT221_CTRL_IEN2(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_IEN2_SHIFT)) & XBAR_NUM_OUT221_CTRL_IEN2_MASK)
127034 
127035 #define XBAR_NUM_OUT221_CTRL_EDGE0_MASK          (0xCU)
127036 #define XBAR_NUM_OUT221_CTRL_EDGE0_SHIFT         (2U)
127037 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0
127038  *  0b00..STS0 never asserts
127039  *  0b01..STS0 asserts on rising edges of XBAR_OUT0
127040  *  0b10..STS0 asserts on falling edges of XBAR_OUT0
127041  *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
127042  */
127043 #define XBAR_NUM_OUT221_CTRL_EDGE0(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_EDGE0_SHIFT)) & XBAR_NUM_OUT221_CTRL_EDGE0_MASK)
127044 
127045 #define XBAR_NUM_OUT221_CTRL_EDGE2_MASK          (0xCU)
127046 #define XBAR_NUM_OUT221_CTRL_EDGE2_SHIFT         (2U)
127047 /*! EDGE2 - Active edge for edge detection on XBAR_OUT2
127048  *  0b00..STS2 never asserts
127049  *  0b01..STS2 asserts on rising edges of XBAR_OUT2
127050  *  0b10..STS2 asserts on falling edges of XBAR_OUT2
127051  *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
127052  */
127053 #define XBAR_NUM_OUT221_CTRL_EDGE2(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_EDGE2_SHIFT)) & XBAR_NUM_OUT221_CTRL_EDGE2_MASK)
127054 
127055 #define XBAR_NUM_OUT221_CTRL_STS0_MASK           (0x10U)
127056 #define XBAR_NUM_OUT221_CTRL_STS0_SHIFT          (4U)
127057 /*! STS0 - Edge detection status for XBAR_OUT0
127058  *  0b0..Active edge not yet detected on XBAR_OUT0
127059  *  0b1..Active edge detected on XBAR_OUT0
127060  */
127061 #define XBAR_NUM_OUT221_CTRL_STS0(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_STS0_SHIFT)) & XBAR_NUM_OUT221_CTRL_STS0_MASK)
127062 
127063 #define XBAR_NUM_OUT221_CTRL_STS2_MASK           (0x10U)
127064 #define XBAR_NUM_OUT221_CTRL_STS2_SHIFT          (4U)
127065 /*! STS2 - Edge detection status for XBAR_OUT2
127066  *  0b0..Active edge not yet detected on XBAR_OUT2
127067  *  0b1..Active edge detected on XBAR_OUT2
127068  */
127069 #define XBAR_NUM_OUT221_CTRL_STS2(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_STS2_SHIFT)) & XBAR_NUM_OUT221_CTRL_STS2_MASK)
127070 
127071 #define XBAR_NUM_OUT221_CTRL_DEN1_MASK           (0x100U)
127072 #define XBAR_NUM_OUT221_CTRL_DEN1_SHIFT          (8U)
127073 /*! DEN1 - DMA Enable for XBAR_OUT1
127074  *  0b0..DMA disabled
127075  *  0b1..DMA enabled
127076  */
127077 #define XBAR_NUM_OUT221_CTRL_DEN1(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_DEN1_SHIFT)) & XBAR_NUM_OUT221_CTRL_DEN1_MASK)
127078 
127079 #define XBAR_NUM_OUT221_CTRL_DEN3_MASK           (0x100U)
127080 #define XBAR_NUM_OUT221_CTRL_DEN3_SHIFT          (8U)
127081 /*! DEN3 - DMA Enable for XBAR_OUT3
127082  *  0b0..DMA disabled
127083  *  0b1..DMA enabled
127084  */
127085 #define XBAR_NUM_OUT221_CTRL_DEN3(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_DEN3_SHIFT)) & XBAR_NUM_OUT221_CTRL_DEN3_MASK)
127086 
127087 #define XBAR_NUM_OUT221_CTRL_IEN1_MASK           (0x200U)
127088 #define XBAR_NUM_OUT221_CTRL_IEN1_SHIFT          (9U)
127089 /*! IEN1 - Interrupt Enable for XBAR_OUT1
127090  *  0b0..Interrupt disabled
127091  *  0b1..Interrupt enabled
127092  */
127093 #define XBAR_NUM_OUT221_CTRL_IEN1(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_IEN1_SHIFT)) & XBAR_NUM_OUT221_CTRL_IEN1_MASK)
127094 
127095 #define XBAR_NUM_OUT221_CTRL_IEN3_MASK           (0x200U)
127096 #define XBAR_NUM_OUT221_CTRL_IEN3_SHIFT          (9U)
127097 /*! IEN3 - Interrupt Enable for XBAR_OUT3
127098  *  0b0..Interrupt disabled
127099  *  0b1..Interrupt enabled
127100  */
127101 #define XBAR_NUM_OUT221_CTRL_IEN3(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_IEN3_SHIFT)) & XBAR_NUM_OUT221_CTRL_IEN3_MASK)
127102 
127103 #define XBAR_NUM_OUT221_CTRL_EDGE1_MASK          (0xC00U)
127104 #define XBAR_NUM_OUT221_CTRL_EDGE1_SHIFT         (10U)
127105 /*! EDGE1 - Active edge for edge detection on XBAR_OUT1
127106  *  0b00..STS1 never asserts
127107  *  0b01..STS1 asserts on rising edges of XBAR_OUT1
127108  *  0b10..STS1 asserts on falling edges of XBAR_OUT1
127109  *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
127110  */
127111 #define XBAR_NUM_OUT221_CTRL_EDGE1(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_EDGE1_SHIFT)) & XBAR_NUM_OUT221_CTRL_EDGE1_MASK)
127112 
127113 #define XBAR_NUM_OUT221_CTRL_EDGE3_MASK          (0xC00U)
127114 #define XBAR_NUM_OUT221_CTRL_EDGE3_SHIFT         (10U)
127115 /*! EDGE3 - Active edge for edge detection on XBAR_OUT3
127116  *  0b00..STS3 never asserts
127117  *  0b01..STS3 asserts on rising edges of XBAR_OUT3
127118  *  0b10..STS3 asserts on falling edges of XBAR_OUT3
127119  *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
127120  */
127121 #define XBAR_NUM_OUT221_CTRL_EDGE3(x)            (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_EDGE3_SHIFT)) & XBAR_NUM_OUT221_CTRL_EDGE3_MASK)
127122 
127123 #define XBAR_NUM_OUT221_CTRL_STS1_MASK           (0x1000U)
127124 #define XBAR_NUM_OUT221_CTRL_STS1_SHIFT          (12U)
127125 /*! STS1 - Edge detection status for XBAR_OUT1
127126  *  0b0..Active edge not yet detected on XBAR_OUT1
127127  *  0b1..Active edge detected on XBAR_OUT1
127128  */
127129 #define XBAR_NUM_OUT221_CTRL_STS1(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_STS1_SHIFT)) & XBAR_NUM_OUT221_CTRL_STS1_MASK)
127130 
127131 #define XBAR_NUM_OUT221_CTRL_STS3_MASK           (0x1000U)
127132 #define XBAR_NUM_OUT221_CTRL_STS3_SHIFT          (12U)
127133 /*! STS3 - Edge detection status for XBAR_OUT3
127134  *  0b0..Active edge not yet detected on XBAR_OUT3
127135  *  0b1..Active edge detected on XBAR_OUT3
127136  */
127137 #define XBAR_NUM_OUT221_CTRL_STS3(x)             (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT221_CTRL_STS3_SHIFT)) & XBAR_NUM_OUT221_CTRL_STS3_MASK)
127138 /*! @} */
127139 
127140 /* The count of XBAR_NUM_OUT221_CTRL */
127141 #define XBAR_NUM_OUT221_CTRL_COUNT               (2U)
127142 
127143 
127144 /*!
127145  * @}
127146  */ /* end of group XBAR_NUM_OUT221_Register_Masks */
127147 
127148 
127149 /* XBAR_NUM_OUT221 - Peripheral instance base addresses */
127150 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
127151   /** Peripheral XBAR1 base address */
127152   #define XBAR1_BASE                               (0x52750000u)
127153   /** Peripheral XBAR1 base address */
127154   #define XBAR1_BASE_NS                            (0x42750000u)
127155   /** Peripheral XBAR1 base pointer */
127156   #define XBAR1                                    ((XBAR_NUM_OUT221_Type *)XBAR1_BASE)
127157   /** Peripheral XBAR1 base pointer */
127158   #define XBAR1_NS                                 ((XBAR_NUM_OUT221_Type *)XBAR1_BASE_NS)
127159   /** Array initializer of XBAR_NUM_OUT221 peripheral base addresses */
127160   #define XBAR_NUM_OUT221_BASE_ADDRS               { XBAR1_BASE }
127161   /** Array initializer of XBAR_NUM_OUT221 peripheral base pointers */
127162   #define XBAR_NUM_OUT221_BASE_PTRS                { XBAR1 }
127163   /** Array initializer of XBAR_NUM_OUT221 peripheral base addresses */
127164   #define XBAR_NUM_OUT221_BASE_ADDRS_NS            { XBAR1_BASE_NS }
127165   /** Array initializer of XBAR_NUM_OUT221 peripheral base pointers */
127166   #define XBAR_NUM_OUT221_BASE_PTRS_NS             { XBAR1_NS }
127167 #else
127168   /** Peripheral XBAR1 base address */
127169   #define XBAR1_BASE                               (0x42750000u)
127170   /** Peripheral XBAR1 base pointer */
127171   #define XBAR1                                    ((XBAR_NUM_OUT221_Type *)XBAR1_BASE)
127172   /** Array initializer of XBAR_NUM_OUT221 peripheral base addresses */
127173   #define XBAR_NUM_OUT221_BASE_ADDRS               { XBAR1_BASE }
127174   /** Array initializer of XBAR_NUM_OUT221 peripheral base pointers */
127175   #define XBAR_NUM_OUT221_BASE_PTRS                { XBAR1 }
127176 #endif
127177 
127178 /*!
127179  * @}
127180  */ /* end of group XBAR_NUM_OUT221_Peripheral_Access_Layer */
127181 
127182 
127183 /* ----------------------------------------------------------------------------
127184    -- XBAR_NUM_OUT32 Peripheral Access Layer
127185    ---------------------------------------------------------------------------- */
127186 
127187 /*!
127188  * @addtogroup XBAR_NUM_OUT32_Peripheral_Access_Layer XBAR_NUM_OUT32 Peripheral Access Layer
127189  * @{
127190  */
127191 
127192 /** XBAR_NUM_OUT32 - Register Layout Typedef */
127193 typedef struct {
127194   __IO uint16_t SEL[16];                           /**< Crossbar Select Register, array offset: 0x0, array step: 0x2 */
127195 } XBAR_NUM_OUT32_Type;
127196 
127197 /* ----------------------------------------------------------------------------
127198    -- XBAR_NUM_OUT32 Register Masks
127199    ---------------------------------------------------------------------------- */
127200 
127201 /*!
127202  * @addtogroup XBAR_NUM_OUT32_Register_Masks XBAR_NUM_OUT32 Register Masks
127203  * @{
127204  */
127205 
127206 /*! @name SEL - Crossbar Select Register */
127207 /*! @{ */
127208 
127209 #define XBAR_NUM_OUT32_SEL_SEL0_MASK             (0xFFU)
127210 #define XBAR_NUM_OUT32_SEL_SEL0_SHIFT            (0U)
127211 /*! SEL0 - SEL0 */
127212 #define XBAR_NUM_OUT32_SEL_SEL0(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL0_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL0_MASK)
127213 
127214 #define XBAR_NUM_OUT32_SEL_SEL2_MASK             (0xFFU)
127215 #define XBAR_NUM_OUT32_SEL_SEL2_SHIFT            (0U)
127216 /*! SEL2 - SEL2 */
127217 #define XBAR_NUM_OUT32_SEL_SEL2(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL2_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL2_MASK)
127218 
127219 #define XBAR_NUM_OUT32_SEL_SEL4_MASK             (0xFFU)
127220 #define XBAR_NUM_OUT32_SEL_SEL4_SHIFT            (0U)
127221 /*! SEL4 - SEL4 */
127222 #define XBAR_NUM_OUT32_SEL_SEL4(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL4_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL4_MASK)
127223 
127224 #define XBAR_NUM_OUT32_SEL_SEL6_MASK             (0xFFU)
127225 #define XBAR_NUM_OUT32_SEL_SEL6_SHIFT            (0U)
127226 /*! SEL6 - SEL6 */
127227 #define XBAR_NUM_OUT32_SEL_SEL6(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL6_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL6_MASK)
127228 
127229 #define XBAR_NUM_OUT32_SEL_SEL8_MASK             (0xFFU)
127230 #define XBAR_NUM_OUT32_SEL_SEL8_SHIFT            (0U)
127231 /*! SEL8 - SEL8 */
127232 #define XBAR_NUM_OUT32_SEL_SEL8(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL8_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL8_MASK)
127233 
127234 #define XBAR_NUM_OUT32_SEL_SEL10_MASK            (0xFFU)
127235 #define XBAR_NUM_OUT32_SEL_SEL10_SHIFT           (0U)
127236 /*! SEL10 - SEL10 */
127237 #define XBAR_NUM_OUT32_SEL_SEL10(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL10_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL10_MASK)
127238 
127239 #define XBAR_NUM_OUT32_SEL_SEL12_MASK            (0xFFU)
127240 #define XBAR_NUM_OUT32_SEL_SEL12_SHIFT           (0U)
127241 /*! SEL12 - SEL12 */
127242 #define XBAR_NUM_OUT32_SEL_SEL12(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL12_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL12_MASK)
127243 
127244 #define XBAR_NUM_OUT32_SEL_SEL14_MASK            (0xFFU)
127245 #define XBAR_NUM_OUT32_SEL_SEL14_SHIFT           (0U)
127246 /*! SEL14 - SEL14 */
127247 #define XBAR_NUM_OUT32_SEL_SEL14(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL14_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL14_MASK)
127248 
127249 #define XBAR_NUM_OUT32_SEL_SEL16_MASK            (0xFFU)
127250 #define XBAR_NUM_OUT32_SEL_SEL16_SHIFT           (0U)
127251 /*! SEL16 - SEL16 */
127252 #define XBAR_NUM_OUT32_SEL_SEL16(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL16_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL16_MASK)
127253 
127254 #define XBAR_NUM_OUT32_SEL_SEL18_MASK            (0xFFU)
127255 #define XBAR_NUM_OUT32_SEL_SEL18_SHIFT           (0U)
127256 /*! SEL18 - SEL18 */
127257 #define XBAR_NUM_OUT32_SEL_SEL18(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL18_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL18_MASK)
127258 
127259 #define XBAR_NUM_OUT32_SEL_SEL20_MASK            (0xFFU)
127260 #define XBAR_NUM_OUT32_SEL_SEL20_SHIFT           (0U)
127261 /*! SEL20 - SEL20 */
127262 #define XBAR_NUM_OUT32_SEL_SEL20(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL20_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL20_MASK)
127263 
127264 #define XBAR_NUM_OUT32_SEL_SEL22_MASK            (0xFFU)
127265 #define XBAR_NUM_OUT32_SEL_SEL22_SHIFT           (0U)
127266 /*! SEL22 - SEL22 */
127267 #define XBAR_NUM_OUT32_SEL_SEL22(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL22_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL22_MASK)
127268 
127269 #define XBAR_NUM_OUT32_SEL_SEL24_MASK            (0xFFU)
127270 #define XBAR_NUM_OUT32_SEL_SEL24_SHIFT           (0U)
127271 /*! SEL24 - SEL24 */
127272 #define XBAR_NUM_OUT32_SEL_SEL24(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL24_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL24_MASK)
127273 
127274 #define XBAR_NUM_OUT32_SEL_SEL26_MASK            (0xFFU)
127275 #define XBAR_NUM_OUT32_SEL_SEL26_SHIFT           (0U)
127276 /*! SEL26 - SEL26 */
127277 #define XBAR_NUM_OUT32_SEL_SEL26(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL26_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL26_MASK)
127278 
127279 #define XBAR_NUM_OUT32_SEL_SEL28_MASK            (0xFFU)
127280 #define XBAR_NUM_OUT32_SEL_SEL28_SHIFT           (0U)
127281 /*! SEL28 - SEL28 */
127282 #define XBAR_NUM_OUT32_SEL_SEL28(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL28_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL28_MASK)
127283 
127284 #define XBAR_NUM_OUT32_SEL_SEL30_MASK            (0xFFU)
127285 #define XBAR_NUM_OUT32_SEL_SEL30_SHIFT           (0U)
127286 /*! SEL30 - SEL30 */
127287 #define XBAR_NUM_OUT32_SEL_SEL30(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL30_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL30_MASK)
127288 
127289 #define XBAR_NUM_OUT32_SEL_SEL1_MASK             (0xFF00U)
127290 #define XBAR_NUM_OUT32_SEL_SEL1_SHIFT            (8U)
127291 /*! SEL1 - SEL1 */
127292 #define XBAR_NUM_OUT32_SEL_SEL1(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL1_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL1_MASK)
127293 
127294 #define XBAR_NUM_OUT32_SEL_SEL3_MASK             (0xFF00U)
127295 #define XBAR_NUM_OUT32_SEL_SEL3_SHIFT            (8U)
127296 /*! SEL3 - SEL3 */
127297 #define XBAR_NUM_OUT32_SEL_SEL3(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL3_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL3_MASK)
127298 
127299 #define XBAR_NUM_OUT32_SEL_SEL5_MASK             (0xFF00U)
127300 #define XBAR_NUM_OUT32_SEL_SEL5_SHIFT            (8U)
127301 /*! SEL5 - SEL5 */
127302 #define XBAR_NUM_OUT32_SEL_SEL5(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL5_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL5_MASK)
127303 
127304 #define XBAR_NUM_OUT32_SEL_SEL7_MASK             (0xFF00U)
127305 #define XBAR_NUM_OUT32_SEL_SEL7_SHIFT            (8U)
127306 /*! SEL7 - SEL7 */
127307 #define XBAR_NUM_OUT32_SEL_SEL7(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL7_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL7_MASK)
127308 
127309 #define XBAR_NUM_OUT32_SEL_SEL9_MASK             (0xFF00U)
127310 #define XBAR_NUM_OUT32_SEL_SEL9_SHIFT            (8U)
127311 /*! SEL9 - SEL9 */
127312 #define XBAR_NUM_OUT32_SEL_SEL9(x)               (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL9_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL9_MASK)
127313 
127314 #define XBAR_NUM_OUT32_SEL_SEL11_MASK            (0xFF00U)
127315 #define XBAR_NUM_OUT32_SEL_SEL11_SHIFT           (8U)
127316 /*! SEL11 - SEL11 */
127317 #define XBAR_NUM_OUT32_SEL_SEL11(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL11_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL11_MASK)
127318 
127319 #define XBAR_NUM_OUT32_SEL_SEL13_MASK            (0xFF00U)
127320 #define XBAR_NUM_OUT32_SEL_SEL13_SHIFT           (8U)
127321 /*! SEL13 - SEL13 */
127322 #define XBAR_NUM_OUT32_SEL_SEL13(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL13_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL13_MASK)
127323 
127324 #define XBAR_NUM_OUT32_SEL_SEL15_MASK            (0xFF00U)
127325 #define XBAR_NUM_OUT32_SEL_SEL15_SHIFT           (8U)
127326 /*! SEL15 - SEL15 */
127327 #define XBAR_NUM_OUT32_SEL_SEL15(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL15_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL15_MASK)
127328 
127329 #define XBAR_NUM_OUT32_SEL_SEL17_MASK            (0xFF00U)
127330 #define XBAR_NUM_OUT32_SEL_SEL17_SHIFT           (8U)
127331 /*! SEL17 - SEL17 */
127332 #define XBAR_NUM_OUT32_SEL_SEL17(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL17_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL17_MASK)
127333 
127334 #define XBAR_NUM_OUT32_SEL_SEL19_MASK            (0xFF00U)
127335 #define XBAR_NUM_OUT32_SEL_SEL19_SHIFT           (8U)
127336 /*! SEL19 - SEL19 */
127337 #define XBAR_NUM_OUT32_SEL_SEL19(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL19_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL19_MASK)
127338 
127339 #define XBAR_NUM_OUT32_SEL_SEL21_MASK            (0xFF00U)
127340 #define XBAR_NUM_OUT32_SEL_SEL21_SHIFT           (8U)
127341 /*! SEL21 - SEL21 */
127342 #define XBAR_NUM_OUT32_SEL_SEL21(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL21_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL21_MASK)
127343 
127344 #define XBAR_NUM_OUT32_SEL_SEL23_MASK            (0xFF00U)
127345 #define XBAR_NUM_OUT32_SEL_SEL23_SHIFT           (8U)
127346 /*! SEL23 - SEL23 */
127347 #define XBAR_NUM_OUT32_SEL_SEL23(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL23_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL23_MASK)
127348 
127349 #define XBAR_NUM_OUT32_SEL_SEL25_MASK            (0xFF00U)
127350 #define XBAR_NUM_OUT32_SEL_SEL25_SHIFT           (8U)
127351 /*! SEL25 - SEL25 */
127352 #define XBAR_NUM_OUT32_SEL_SEL25(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL25_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL25_MASK)
127353 
127354 #define XBAR_NUM_OUT32_SEL_SEL27_MASK            (0xFF00U)
127355 #define XBAR_NUM_OUT32_SEL_SEL27_SHIFT           (8U)
127356 /*! SEL27 - SEL27 */
127357 #define XBAR_NUM_OUT32_SEL_SEL27(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL27_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL27_MASK)
127358 
127359 #define XBAR_NUM_OUT32_SEL_SEL29_MASK            (0xFF00U)
127360 #define XBAR_NUM_OUT32_SEL_SEL29_SHIFT           (8U)
127361 /*! SEL29 - SEL29 */
127362 #define XBAR_NUM_OUT32_SEL_SEL29(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL29_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL29_MASK)
127363 
127364 #define XBAR_NUM_OUT32_SEL_SEL31_MASK            (0xFF00U)
127365 #define XBAR_NUM_OUT32_SEL_SEL31_SHIFT           (8U)
127366 /*! SEL31 - SEL31 */
127367 #define XBAR_NUM_OUT32_SEL_SEL31(x)              (((uint16_t)(((uint16_t)(x)) << XBAR_NUM_OUT32_SEL_SEL31_SHIFT)) & XBAR_NUM_OUT32_SEL_SEL31_MASK)
127368 /*! @} */
127369 
127370 /* The count of XBAR_NUM_OUT32_SEL */
127371 #define XBAR_NUM_OUT32_SEL_COUNT                 (16U)
127372 
127373 
127374 /*!
127375  * @}
127376  */ /* end of group XBAR_NUM_OUT32_Register_Masks */
127377 
127378 
127379 /* XBAR_NUM_OUT32 - Peripheral instance base addresses */
127380 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
127381   /** Peripheral XBAR2 base address */
127382   #define XBAR2_BASE                               (0x52760000u)
127383   /** Peripheral XBAR2 base address */
127384   #define XBAR2_BASE_NS                            (0x42760000u)
127385   /** Peripheral XBAR2 base pointer */
127386   #define XBAR2                                    ((XBAR_NUM_OUT32_Type *)XBAR2_BASE)
127387   /** Peripheral XBAR2 base pointer */
127388   #define XBAR2_NS                                 ((XBAR_NUM_OUT32_Type *)XBAR2_BASE_NS)
127389   /** Peripheral XBAR3 base address */
127390   #define XBAR3_BASE                               (0x52770000u)
127391   /** Peripheral XBAR3 base address */
127392   #define XBAR3_BASE_NS                            (0x42770000u)
127393   /** Peripheral XBAR3 base pointer */
127394   #define XBAR3                                    ((XBAR_NUM_OUT32_Type *)XBAR3_BASE)
127395   /** Peripheral XBAR3 base pointer */
127396   #define XBAR3_NS                                 ((XBAR_NUM_OUT32_Type *)XBAR3_BASE_NS)
127397   /** Array initializer of XBAR_NUM_OUT32 peripheral base addresses */
127398   #define XBAR_NUM_OUT32_BASE_ADDRS                { XBAR2_BASE, XBAR3_BASE }
127399   /** Array initializer of XBAR_NUM_OUT32 peripheral base pointers */
127400   #define XBAR_NUM_OUT32_BASE_PTRS                 { XBAR2, XBAR3 }
127401   /** Array initializer of XBAR_NUM_OUT32 peripheral base addresses */
127402   #define XBAR_NUM_OUT32_BASE_ADDRS_NS             { XBAR2_BASE_NS, XBAR3_BASE_NS }
127403   /** Array initializer of XBAR_NUM_OUT32 peripheral base pointers */
127404   #define XBAR_NUM_OUT32_BASE_PTRS_NS              { XBAR2_NS, XBAR3_NS }
127405 #else
127406   /** Peripheral XBAR2 base address */
127407   #define XBAR2_BASE                               (0x42760000u)
127408   /** Peripheral XBAR2 base pointer */
127409   #define XBAR2                                    ((XBAR_NUM_OUT32_Type *)XBAR2_BASE)
127410   /** Peripheral XBAR3 base address */
127411   #define XBAR3_BASE                               (0x42770000u)
127412   /** Peripheral XBAR3 base pointer */
127413   #define XBAR3                                    ((XBAR_NUM_OUT32_Type *)XBAR3_BASE)
127414   /** Array initializer of XBAR_NUM_OUT32 peripheral base addresses */
127415   #define XBAR_NUM_OUT32_BASE_ADDRS                { XBAR2_BASE, XBAR3_BASE }
127416   /** Array initializer of XBAR_NUM_OUT32 peripheral base pointers */
127417   #define XBAR_NUM_OUT32_BASE_PTRS                 { XBAR2, XBAR3 }
127418 #endif
127419 
127420 /*!
127421  * @}
127422  */ /* end of group XBAR_NUM_OUT32_Peripheral_Access_Layer */
127423 
127424 
127425 /* ----------------------------------------------------------------------------
127426    -- XCACHE Peripheral Access Layer
127427    ---------------------------------------------------------------------------- */
127428 
127429 /*!
127430  * @addtogroup XCACHE_Peripheral_Access_Layer XCACHE Peripheral Access Layer
127431  * @{
127432  */
127433 
127434 /** XCACHE - Register Layout Typedef */
127435 typedef struct {
127436   __IO uint32_t CCR;                               /**< Cache Control, offset: 0x0 */
127437   __IO uint32_t CLCR;                              /**< Cache Line Control, offset: 0x4 */
127438   __IO uint32_t CSAR;                              /**< Cache Search Address, offset: 0x8 */
127439   __IO uint32_t CCVR;                              /**< Cache Read/Write Value, offset: 0xC */
127440 } XCACHE_Type;
127441 
127442 /* ----------------------------------------------------------------------------
127443    -- XCACHE Register Masks
127444    ---------------------------------------------------------------------------- */
127445 
127446 /*!
127447  * @addtogroup XCACHE_Register_Masks XCACHE Register Masks
127448  * @{
127449  */
127450 
127451 /*! @name CCR - Cache Control */
127452 /*! @{ */
127453 
127454 #define XCACHE_CCR_ENCACHE_MASK                  (0x1U)
127455 #define XCACHE_CCR_ENCACHE_SHIFT                 (0U)
127456 /*! ENCACHE - Cache Enable
127457  *  0b0..Disable
127458  *  0b1..Enable
127459  */
127460 #define XCACHE_CCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_ENCACHE_SHIFT)) & XCACHE_CCR_ENCACHE_MASK)
127461 
127462 #define XCACHE_CCR_FRCWT_MASK                    (0x4U)
127463 #define XCACHE_CCR_FRCWT_SHIFT                   (2U)
127464 /*! FRCWT - Force Write Through Mode
127465  *  0b0..Does not force
127466  *  0b1..Force
127467  */
127468 #define XCACHE_CCR_FRCWT(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCWT_SHIFT)) & XCACHE_CCR_FRCWT_MASK)
127469 
127470 #define XCACHE_CCR_FRCNOALLC_MASK                (0x8U)
127471 #define XCACHE_CCR_FRCNOALLC_SHIFT               (3U)
127472 /*! FRCNOALLC - Forces No Allocation on Cache Misses
127473  *  0b0..Allocation on cache misses
127474  *  0b1..Forces no allocation on cache misses (must also have FRCWT asserted)
127475  */
127476 #define XCACHE_CCR_FRCNOALLC(x)                  (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCNOALLC_SHIFT)) & XCACHE_CCR_FRCNOALLC_MASK)
127477 
127478 #define XCACHE_CCR_INVW0_MASK                    (0x1000000U)
127479 #define XCACHE_CCR_INVW0_SHIFT                   (24U)
127480 /*! INVW0 - Invalidate Way 0
127481  *  0b0..No operation
127482  *  0b1..When you write 1 to GO, invalidates all lines in way 0.
127483  */
127484 #define XCACHE_CCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW0_SHIFT)) & XCACHE_CCR_INVW0_MASK)
127485 
127486 #define XCACHE_CCR_PUSHW0_MASK                   (0x2000000U)
127487 #define XCACHE_CCR_PUSHW0_SHIFT                  (25U)
127488 /*! PUSHW0 - Push Way 0
127489  *  0b0..No operation
127490  *  0b1..When you write 1 to GO, push all modified lines in way 0
127491  */
127492 #define XCACHE_CCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW0_SHIFT)) & XCACHE_CCR_PUSHW0_MASK)
127493 
127494 #define XCACHE_CCR_INVW1_MASK                    (0x4000000U)
127495 #define XCACHE_CCR_INVW1_SHIFT                   (26U)
127496 /*! INVW1 - Invalidate Way 1
127497  *  0b0..No operation
127498  *  0b1..When you write 1 to GO, invalidates all lines in way 1
127499  */
127500 #define XCACHE_CCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW1_SHIFT)) & XCACHE_CCR_INVW1_MASK)
127501 
127502 #define XCACHE_CCR_PUSHW1_MASK                   (0x8000000U)
127503 #define XCACHE_CCR_PUSHW1_SHIFT                  (27U)
127504 /*! PUSHW1 - Push Way 1
127505  *  0b0..No operation
127506  *  0b1..When you write 1 to GO, push all modified lines in way 1
127507  */
127508 #define XCACHE_CCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW1_SHIFT)) & XCACHE_CCR_PUSHW1_MASK)
127509 
127510 #define XCACHE_CCR_GO_MASK                       (0x80000000U)
127511 #define XCACHE_CCR_GO_SHIFT                      (31U)
127512 /*! GO - Initiate Cache Command
127513  *  0b0..Write: no effect. Read: no cache command active
127514  *  0b1..Write: initiates command; Read: cache command active
127515  */
127516 #define XCACHE_CCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_GO_SHIFT)) & XCACHE_CCR_GO_MASK)
127517 /*! @} */
127518 
127519 /*! @name CLCR - Cache Line Control */
127520 /*! @{ */
127521 
127522 #define XCACHE_CLCR_LGO_MASK                     (0x1U)
127523 #define XCACHE_CLCR_LGO_SHIFT                    (0U)
127524 /*! LGO - Initiate Cache Line Command
127525  *  0b0..Write: no effect. Read: no line command active.
127526  *  0b1..Write: initiate line command. Read: line command active.
127527  */
127528 #define XCACHE_CLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LGO_SHIFT)) & XCACHE_CLCR_LGO_MASK)
127529 
127530 #define XCACHE_CLCR_CACHEADDR_MASK               (0x3FFCU)
127531 #define XCACHE_CLCR_CACHEADDR_SHIFT              (2U)
127532 /*! CACHEADDR - Cache Address */
127533 #define XCACHE_CLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_CACHEADDR_SHIFT)) & XCACHE_CLCR_CACHEADDR_MASK)
127534 
127535 #define XCACHE_CLCR_WSEL_MASK                    (0x4000U)
127536 #define XCACHE_CLCR_WSEL_SHIFT                   (14U)
127537 /*! WSEL - Way Select
127538  *  0b0..Way 0
127539  *  0b1..Way 1
127540  */
127541 #define XCACHE_CLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_WSEL_SHIFT)) & XCACHE_CLCR_WSEL_MASK)
127542 
127543 #define XCACHE_CLCR_TDSEL_MASK                   (0x10000U)
127544 #define XCACHE_CLCR_TDSEL_SHIFT                  (16U)
127545 /*! TDSEL - Tag or Data Select
127546  *  0b0..Data
127547  *  0b1..Tag
127548  */
127549 #define XCACHE_CLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_TDSEL_SHIFT)) & XCACHE_CLCR_TDSEL_MASK)
127550 
127551 #define XCACHE_CLCR_LCIVB_MASK                   (0x100000U)
127552 #define XCACHE_CLCR_LCIVB_SHIFT                  (20U)
127553 /*! LCIVB - Line Command Initial Valid */
127554 #define XCACHE_CLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIVB_SHIFT)) & XCACHE_CLCR_LCIVB_MASK)
127555 
127556 #define XCACHE_CLCR_LCIMB_MASK                   (0x200000U)
127557 #define XCACHE_CLCR_LCIMB_SHIFT                  (21U)
127558 /*! LCIMB - Line Command Initial Modified */
127559 #define XCACHE_CLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIMB_SHIFT)) & XCACHE_CLCR_LCIMB_MASK)
127560 
127561 #define XCACHE_CLCR_LCWAY_MASK                   (0x400000U)
127562 #define XCACHE_CLCR_LCWAY_SHIFT                  (22U)
127563 /*! LCWAY - Line Command Way */
127564 #define XCACHE_CLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCWAY_SHIFT)) & XCACHE_CLCR_LCWAY_MASK)
127565 
127566 #define XCACHE_CLCR_LCMD_MASK                    (0x3000000U)
127567 #define XCACHE_CLCR_LCMD_SHIFT                   (24U)
127568 /*! LCMD - Line Command
127569  *  0b00..Search and read or write
127570  *  0b01..Invalidate
127571  *  0b10..Push
127572  *  0b11..Clear
127573  */
127574 #define XCACHE_CLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCMD_SHIFT)) & XCACHE_CLCR_LCMD_MASK)
127575 
127576 #define XCACHE_CLCR_LADSEL_MASK                  (0x4000000U)
127577 #define XCACHE_CLCR_LADSEL_SHIFT                 (26U)
127578 /*! LADSEL - Line Address Select
127579  *  0b0..Cache address
127580  *  0b1..Physical address
127581  */
127582 #define XCACHE_CLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LADSEL_SHIFT)) & XCACHE_CLCR_LADSEL_MASK)
127583 
127584 #define XCACHE_CLCR_LACC_MASK                    (0x8000000U)
127585 #define XCACHE_CLCR_LACC_SHIFT                   (27U)
127586 /*! LACC - Line Access Type
127587  *  0b0..Read
127588  *  0b1..Write
127589  */
127590 #define XCACHE_CLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LACC_SHIFT)) & XCACHE_CLCR_LACC_MASK)
127591 /*! @} */
127592 
127593 /*! @name CSAR - Cache Search Address */
127594 /*! @{ */
127595 
127596 #define XCACHE_CSAR_LGO_MASK                     (0x1U)
127597 #define XCACHE_CSAR_LGO_SHIFT                    (0U)
127598 /*! LGO - Initiate Cache Line Command
127599  *  0b0..Write: no effect. Read: no line command active.
127600  *  0b1..Write: initiate line command. Read: line command active.
127601  */
127602 #define XCACHE_CSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_LGO_SHIFT)) & XCACHE_CSAR_LGO_MASK)
127603 
127604 #define XCACHE_CSAR_PHYADDR_MASK                 (0xFFFFFFFCU)
127605 #define XCACHE_CSAR_PHYADDR_SHIFT                (2U)
127606 /*! PHYADDR - Physical Address */
127607 #define XCACHE_CSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_PHYADDR_SHIFT)) & XCACHE_CSAR_PHYADDR_MASK)
127608 /*! @} */
127609 
127610 /*! @name CCVR - Cache Read/Write Value */
127611 /*! @{ */
127612 
127613 #define XCACHE_CCVR_DATA_MASK                    (0xFFFFFFFFU)
127614 #define XCACHE_CCVR_DATA_SHIFT                   (0U)
127615 /*! DATA - Cache Read/Write Data */
127616 #define XCACHE_CCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << XCACHE_CCVR_DATA_SHIFT)) & XCACHE_CCVR_DATA_MASK)
127617 /*! @} */
127618 
127619 
127620 /*!
127621  * @}
127622  */ /* end of group XCACHE_Register_Masks */
127623 
127624 
127625 /* XCACHE - Peripheral instance base addresses */
127626 #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
127627   /** Peripheral XCACHE_PC base address */
127628   #define XCACHE_PC_BASE                           (0x54400000u)
127629   /** Peripheral XCACHE_PC base address */
127630   #define XCACHE_PC_BASE_NS                        (0x44400000u)
127631   /** Peripheral XCACHE_PC base pointer */
127632   #define XCACHE_PC                                ((XCACHE_Type *)XCACHE_PC_BASE)
127633   /** Peripheral XCACHE_PC base pointer */
127634   #define XCACHE_PC_NS                             ((XCACHE_Type *)XCACHE_PC_BASE_NS)
127635   /** Peripheral XCACHE_PS base address */
127636   #define XCACHE_PS_BASE                           (0x54400800u)
127637   /** Peripheral XCACHE_PS base address */
127638   #define XCACHE_PS_BASE_NS                        (0x44400800u)
127639   /** Peripheral XCACHE_PS base pointer */
127640   #define XCACHE_PS                                ((XCACHE_Type *)XCACHE_PS_BASE)
127641   /** Peripheral XCACHE_PS base pointer */
127642   #define XCACHE_PS_NS                             ((XCACHE_Type *)XCACHE_PS_BASE_NS)
127643   /** Array initializer of XCACHE peripheral base addresses */
127644   #define XCACHE_BASE_ADDRS                        { XCACHE_PC_BASE, XCACHE_PS_BASE }
127645   /** Array initializer of XCACHE peripheral base pointers */
127646   #define XCACHE_BASE_PTRS                         { XCACHE_PC, XCACHE_PS }
127647   /** Array initializer of XCACHE peripheral base addresses */
127648   #define XCACHE_BASE_ADDRS_NS                     { XCACHE_PC_BASE_NS, XCACHE_PS_BASE_NS }
127649   /** Array initializer of XCACHE peripheral base pointers */
127650   #define XCACHE_BASE_PTRS_NS                      { XCACHE_PC_NS, XCACHE_PS_NS }
127651 #else
127652   /** Peripheral XCACHE_PC base address */
127653   #define XCACHE_PC_BASE                           (0x44400000u)
127654   /** Peripheral XCACHE_PC base pointer */
127655   #define XCACHE_PC                                ((XCACHE_Type *)XCACHE_PC_BASE)
127656   /** Peripheral XCACHE_PS base address */
127657   #define XCACHE_PS_BASE                           (0x44400800u)
127658   /** Peripheral XCACHE_PS base pointer */
127659   #define XCACHE_PS                                ((XCACHE_Type *)XCACHE_PS_BASE)
127660   /** Array initializer of XCACHE peripheral base addresses */
127661   #define XCACHE_BASE_ADDRS                        { XCACHE_PC_BASE, XCACHE_PS_BASE }
127662   /** Array initializer of XCACHE peripheral base pointers */
127663   #define XCACHE_BASE_PTRS                         { XCACHE_PC, XCACHE_PS }
127664 #endif
127665 /** XCACHE physical memory base address */
127666 #define XCACHE_PHYMEM_BASES                        { 0x00000000u, 0x20000000u }
127667 /** XCACHE physical memory size */
127668 #define XCACHE_PHYMEM_SIZES                        { 0x20000000u, 0xE0000000u }
127669 
127670 
127671 /*!
127672  * @}
127673  */ /* end of group XCACHE_Peripheral_Access_Layer */
127674 
127675 
127676 /*
127677 ** End of section using anonymous unions
127678 */
127679 
127680 #if defined(__ARMCC_VERSION)
127681   #if (__ARMCC_VERSION >= 6010050)
127682     #pragma clang diagnostic pop
127683   #else
127684     #pragma pop
127685   #endif
127686 #elif defined(__GNUC__)
127687   /* leave anonymous unions enabled */
127688 #elif defined(__IAR_SYSTEMS_ICC__)
127689   #pragma language=default
127690 #else
127691   #error Not supported compiler type
127692 #endif
127693 
127694 /*!
127695  * @}
127696  */ /* end of group Peripheral_access_layer */
127697 
127698 
127699 /* ----------------------------------------------------------------------------
127700    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
127701    ---------------------------------------------------------------------------- */
127702 
127703 /*!
127704  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
127705  * @{
127706  */
127707 
127708 #if defined(__ARMCC_VERSION)
127709   #if (__ARMCC_VERSION >= 6010050)
127710     #pragma clang system_header
127711   #endif
127712 #elif defined(__IAR_SYSTEMS_ICC__)
127713   #pragma system_include
127714 #endif
127715 
127716 /**
127717  * @brief Mask and left-shift a bit field value for use in a register bit range.
127718  * @param field Name of the register bit field.
127719  * @param value Value of the bit field.
127720  * @return Masked and shifted value.
127721  */
127722 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
127723 /**
127724  * @brief Mask and right-shift a register value to extract a bit field value.
127725  * @param field Name of the register bit field.
127726  * @param value Value of the register.
127727  * @return Masked and shifted bit field value.
127728  */
127729 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
127730 
127731 /*!
127732  * @}
127733  */ /* end of group Bit_Field_Generic_Macros */
127734 
127735 
127736 /* ----------------------------------------------------------------------------
127737    -- SDK Compatibility
127738    ---------------------------------------------------------------------------- */
127739 
127740 /*!
127741  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
127742  * @{
127743  */
127744 
127745 /* No SDK compatibility issues. */
127746 
127747 /*!
127748  * @}
127749  */ /* end of group SDK_Compatibility_Symbols */
127750 
127751 
127752 #endif  /* MIMXRT1182_H_ */
127753 
127754