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Searched refs:TMR2_BASE (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h12140 #define TMR2_BASE (0x40059000u) macro
12142 #define TMR2 ((TMR_Type *)TMR2_BASE)
12148 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h16845 #define TMR2_BASE (0x40059000u) macro
16847 #define TMR2 ((TMR_Type *)TMR2_BASE)
16853 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h16841 #define TMR2_BASE (0x40059000u) macro
16843 #define TMR2 ((TMR_Type *)TMR2_BASE)
16849 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h18257 #define TMR2_BASE (0x40059000u) macro
18259 #define TMR2 ((TMR_Type *)TMR2_BASE)
18265 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h18389 #define TMR2_BASE (0x40059000u) macro
18391 #define TMR2 ((TMR_Type *)TMR2_BASE)
18399 TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE \
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h37346 #define TMR2_BASE (0x401E0000u) macro
37348 #define TMR2 ((TMR_Type *)TMR2_BASE)
37350 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h37325 #define TMR2_BASE (0x401E0000u) macro
37327 #define TMR2 ((TMR_Type *)TMR2_BASE)
37329 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h40401 #define TMR2_BASE (0x401E0000u) macro
40403 #define TMR2 ((TMR_Type *)TMR2_BASE)
40413 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h38884 #define TMR2_BASE (0x401E0000u) macro
38886 #define TMR2 ((TMR_Type *)TMR2_BASE)
38896 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h43811 #define TMR2_BASE (0x401E0000u) macro
43813 #define TMR2 ((TMR_Type *)TMR2_BASE)
43823 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h43150 #define TMR2_BASE (0x401E0000u) macro
43152 #define TMR2 ((TMR_Type *)TMR2_BASE)
43162 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h41285 #define TMR2_BASE (0x401E0000u) macro
41287 #define TMR2 ((TMR_Type *)TMR2_BASE)
41297 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h82904 #define TMR2_BASE (0x526A0000u) macro
82908 #define TMR2 ((TMR_Type *)TMR2_BASE)
82928 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
82941 #define TMR2_BASE (0x426A0000u) macro
82943 #define TMR2 ((TMR_Type *)TMR2_BASE)
82953 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h79055 #define TMR2_BASE (0x526A0000u) macro
79059 #define TMR2 ((TMR_Type *)TMR2_BASE)
79079 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
79092 #define TMR2_BASE (0x426A0000u) macro
79094 #define TMR2 ((TMR_Type *)TMR2_BASE)
79104 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h45479 #define TMR2_BASE (0x401E0000u) macro
45481 #define TMR2 ((TMR_Type *)TMR2_BASE)
45491 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h45415 #define TMR2_BASE (0x401E0000u) macro
45417 #define TMR2 ((TMR_Type *)TMR2_BASE)
45427 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h83114 #define TMR2_BASE (0x526A0000u) macro
83118 #define TMR2 ((TMR_Type *)TMR2_BASE)
83170 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
83183 #define TMR2_BASE (0x426A0000u) macro
83185 #define TMR2 ((TMR_Type *)TMR2_BASE)
83211 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h86962 #define TMR2_BASE (0x526A0000u) macro
86966 #define TMR2 ((TMR_Type *)TMR2_BASE)
87018 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
87031 #define TMR2_BASE (0x426A0000u) macro
87033 #define TMR2 ((TMR_Type *)TMR2_BASE)
87059 …#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE,…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h73638 #define TMR2_BASE (0x40160000u) macro
73640 #define TMR2 ((TMR_Type *)TMR2_BASE)
73650 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1165_cm7.h72736 #define TMR2_BASE (0x40160000u) macro
72738 #define TMR2 ((TMR_Type *)TMR2_BASE)
72748 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h73238 #define TMR2_BASE (0x40160000u) macro
73240 #define TMR2 ((TMR_Type *)TMR2_BASE)
73250 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h74140 #define TMR2_BASE (0x40160000u) macro
74142 #define TMR2 ((TMR_Type *)TMR2_BASE)
74152 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1175_cm7.h73238 #define TMR2_BASE (0x40160000u) macro
73240 #define TMR2 ((TMR_Type *)TMR2_BASE)
73250 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h78698 #define TMR2_BASE (0x40160000u) macro
78700 #define TMR2 ((TMR_Type *)TMR2_BASE)
78710 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
DMIMXRT1173_cm4.h79600 #define TMR2_BASE (0x40160000u) macro
79602 #define TMR2 ((TMR_Type *)TMR2_BASE)
79612 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }

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