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Searched refs:SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.c951 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
967 SLEEPCON1->RUNCFG_CLR = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_clock.h2297 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.c951 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
967 SLEEPCON1->RUNCFG_CLR = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_clock.h2297 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.c951 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
967 SLEEPCON1->RUNCFG_CLR = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_clock.h2297 SLEEPCON1->RUNCFG_SET = SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK | SLEEPCON1_RUNCFG_AUDPLLANA_PD_MASK; in CLOCK_DeinitAudioPll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h48603 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
48609 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT735S_cm33_core1.h48663 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
48669 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT735S_ezhv.h72416 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
72422 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h51886 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
51892 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT758S_hifi1.h51824 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
51830 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT758S_ezhv.h75561 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
75567 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h51824 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
51830 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT798S_cm33_core1.h51886 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
51892 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)
DMIMXRT798S_ezhv.h75585 #define SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK (0x8000U) macro
75591 …2_t)(((uint32_t)(x)) << SLEEPCON1_RUNCFG_AUDPLLLDO_PD_SHIFT)) & SLEEPCON1_RUNCFG_AUDPLLLDO_PD_MASK)