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/hal_nxp-latest/mcux/mcux-sdk/tools/cmake_toolchain_files/
Dxcc.cmake5 SET(TOOLCHAIN_EXT ".exe")
7 SET(TOOLCHAIN_EXT "")
11 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
14 SET(TOOLCHAIN_DIR $ENV{XCC_DIR})
23 SET(XTENSA_SYSTEM $ENV{XTENSA_SYSTEM})
25 SET(XTENSA_SYSTEM "/opt/xtensa/builds/RI-2019.1-linux/nxp_rt600_RI2019_newlib/config")
27 SET(XTENSA_CORE $ENV{XTENSA_CORE})
29 SET(XTENSA_CORE "nxp_rt600_RI2019_newlib")
33 SET(TARGET_TRIPLET "xt")
35 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
[all …]
Dxclang.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{XCC_DIR})
21 SET(XTENSA_SYSTEM $ENV{XTENSA_SYSTEM})
23 SET(XTENSA_SYSTEM "/opt/xtensa/builds/RI-2019.1-linux/nxp_rt600_RI2019_newlib/config")
25 SET(XTENSA_CORE $ENV{XTENSA_CORE})
27 SET(XTENSA_CORE "nxp_rt600_RI2019_newlib")
31 SET(TARGET_TRIPLET "xt")
33 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
[all …]
Darmgcc_aarch64.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "aarch64-none-elf")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
[all …]
Darmgcc_force_cpp.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "arm-none-eabi")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
[all …]
Darmgcc.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "arm-none-eabi")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/drivers/
Dfsl_clock.h71 pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK; in CLOCK_PllInit()
83 pll->CTRL.SET = PLL_CTRL_POWERUP_MASK; in CLOCK_PllInit()
89 pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK; in CLOCK_PllInit()
105 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
111 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; in CLOCK_PllPfdInit()
115 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; in CLOCK_PllPfdInit()
118 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
1188 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK; in CLOCK_PowerOffRootClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h71 pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK; in CLOCK_PllInit()
83 pll->CTRL.SET = PLL_CTRL_POWERUP_MASK; in CLOCK_PllInit()
89 pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK; in CLOCK_PllInit()
105 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
111 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; in CLOCK_PllPfdInit()
115 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; in CLOCK_PllPfdInit()
118 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
1188 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK; in CLOCK_PowerOffRootClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
676 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
699 base->CTRL0.SET = PLL_CTRL0_DIV_SELECT(div); in ANATOP_PllConfigure()
703 base->CTRL0.SET = PLL_CTRL0_POST_DIV_SEL(post_div); in ANATOP_PllConfigure()
1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
676 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
699 base->CTRL0.SET = PLL_CTRL0_DIV_SELECT(div); in ANATOP_PllConfigure()
703 base->CTRL0.SET = PLL_CTRL0_POST_DIV_SEL(post_div); in ANATOP_PllConfigure()
1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
676 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
699 base->CTRL0.SET = PLL_CTRL0_DIV_SELECT(div); in ANATOP_PllConfigure()
703 base->CTRL0.SET = PLL_CTRL0_POST_DIV_SEL(post_div); in ANATOP_PllConfigure()
1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
676 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
699 base->CTRL0.SET = PLL_CTRL0_DIV_SELECT(div); in ANATOP_PllConfigure()
703 base->CTRL0.SET = PLL_CTRL0_POST_DIV_SEL(post_div); in ANATOP_PllConfigure()
1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/ci_pi/
Dfsl_ci_pi.c84 …base->IF_CTRL_REG.SET = CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK | CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK; in CI_PI_Init()
174 base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK; in CI_PI_Start()
189 …base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK | CI_PI_CSR_CSI_CTRL_REG_VSYNC… in CI_PI_Stop()
Dfsl_ci_pi.h153 base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK; in CI_PI_Reset()
/hal_nxp-latest/mcux/mcux-sdk/drivers/epdc/
Dfsl_epdc.h508 base->IRQ_MASK.SET = ((uint32_t)interrupts << 16U); in EPDC_EnableInterrupts()
571 base->IRQ_MASK1.SET = (uint32_t)interrupts; in EPDC_EnableLutCompleteInterrupts()
572 base->IRQ_MASK2.SET = (uint32_t)(interrupts >> 32U); in EPDC_EnableLutCompleteInterrupts()
697 base->FIFOCTRL.SET = EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK; in EPDC_EnableFifoPanic()
/hal_nxp-latest/mcux/mcux-sdk/drivers/prg/
Dfsl_prg.h85 base->PRG_CTRL.SET = PRG_PRG_CTRL_BYPASS_MASK; in PRG_Enable()
103 base->PRG_CTRL.SET = PRG_PRG_CTRL_SHADOW_EN_MASK; in PRG_EnableShadowLoad()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93qsb/
Dboard.c518 DRAMPLL->CTRL.SET |= PLL_CTRL_POWERUP_MASK; in BOARD_DRAM_PLL_Init()
527 DRAMPLL->CTRL.SET |= PLL_CTRL_CLKMUX_EN_MASK; in BOARD_DRAM_PLL_Init()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93evk/
Dboard.c560 DRAMPLL->CTRL.SET |= PLL_CTRL_POWERUP_MASK; in BOARD_DRAM_PLL_Init()
569 DRAMPLL->CTRL.SET |= PLL_CTRL_CLKMUX_EN_MASK; in BOARD_DRAM_PLL_Init()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93autoevk/
Dboard.c531 DRAMPLL->CTRL.SET |= PLL_CTRL_POWERUP_MASK; in BOARD_DRAM_PLL_Init()
540 DRAMPLL->CTRL.SET |= PLL_CTRL_CLKMUX_EN_MASK; in BOARD_DRAM_PLL_Init()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()

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