609         base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK;  in ANATOP_PllSetPower()
621         base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK;  in ANATOP_PllBypass()
633         base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK;  in ANATOP_PllEnablePllReg()
645         base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK;  in ANATOP_PllHoldRingOff()
664         base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK;  in ANATOP_PllEnableSs()
676         base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK;  in ANATOP_PllEnableClk()
699     base->CTRL0.SET      = PLL_CTRL0_DIV_SELECT(div);  in ANATOP_PllConfigure()
703         base->CTRL0.SET = PLL_CTRL0_POST_DIV_SEL(post_div);  in ANATOP_PllConfigure()
1136         OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK;  in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155         OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK;  in CLOCK_OSC_EnableOscRc400MTuneLogic()
1174         OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_EN_MASK;  in CLOCK_OSC_FreezeOscRc400MTuneValue()
1265     OSC_RC_400M->CTRL3.SET = OSC_RC_400M_CTRL3_CLR_ERR_MASK;  in CLOCK_OSC_ClearLocked1MHzErrorFlag()
1664 …OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_OSC_TUNE_VAL(trim) | OSC_RC_400M_CTRL2_TUNE_BYP(bypass);  in CLOCK_OSC_TrimOscRc400M()