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Searched refs:SC_IRQ_TEMP_GPU1_HIGH (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/svc/irq/
Dirq_api.h74 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/svc/irq/
Dirq_api.h76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_sc_event.h64 … SC_EVENT_TYPE_TUPLE(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_GPU1_HIGH), /*!< GPU1 temp alarm interrupt */