1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2017-2019 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Redistribution and use in source and binary forms, with or without modification, 8 * are permitted provided that the following conditions are met: 9 * 10 * o Redistributions of source code must retain the above copyright notice, this list 11 * of conditions and the following disclaimer. 12 * 13 * o Redistributions in binary form must reproduce the above copyright notice, this 14 * list of conditions and the following disclaimer in the documentation and/or 15 * other materials provided with the distribution. 16 * 17 * o Neither the name of the copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived from this 19 * software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*! 34 * Header file containing the public API for the System Controller (SC) 35 * Interrupt (IRQ) function. 36 * 37 * @addtogroup IRQ_SVC IRQ: Interrupt Service 38 * 39 * Module for the Interrupt (IRQ) service. 40 * 41 * @{ 42 */ 43 44 #ifndef SC_IRQ_API_H 45 #define SC_IRQ_API_H 46 47 /* Includes */ 48 49 #include "main/types.h" 50 51 /* Defines */ 52 53 #define SC_IRQ_NUM_GROUP 7U /*!< Number of groups */ 54 55 /*! 56 * @name Defines for sc_irq_group_t 57 */ 58 /*@{*/ 59 #define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ 60 #define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ 61 #define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ 62 #define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ 63 #define SC_IRQ_GROUP_SYSCTR 4U /*!< System counter interrupts */ 64 #define SC_IRQ_GROUP_REBOOTED 5U /*!< Partition reboot complete */ 65 #define SC_IRQ_GROUP_REBOOT 6U /*!< Partition reboot starting */ 66 /*@}*/ 67 68 /*! 69 * @name Defines for sc_irq_temp_t 70 */ 71 /*@{*/ 72 #define SC_IRQ_TEMP_HIGH (1UL << 0U) /*!< Temp alarm interrupt */ 73 #define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /*!< CPU0 temp alarm interrupt */ 74 #define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /*!< CPU1 temp alarm interrupt */ 75 #define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /*!< GPU0 temp alarm interrupt */ 76 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ 77 #define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /*!< DRC0 temp alarm interrupt */ 78 #define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /*!< DRC1 temp alarm interrupt */ 79 #define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /*!< DRC1 temp alarm interrupt */ 80 #define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /*!< PMIC0 temp alarm interrupt */ 81 #define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /*!< PMIC1 temp alarm interrupt */ 82 #define SC_IRQ_TEMP_LOW (1UL << 10U) /*!< Temp alarm interrupt */ 83 #define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /*!< CPU0 temp alarm interrupt */ 84 #define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /*!< CPU1 temp alarm interrupt */ 85 #define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /*!< GPU0 temp alarm interrupt */ 86 #define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /*!< GPU1 temp alarm interrupt */ 87 #define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /*!< DRC0 temp alarm interrupt */ 88 #define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /*!< DRC1 temp alarm interrupt */ 89 #define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /*!< DRC1 temp alarm interrupt */ 90 #define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /*!< PMIC0 temp alarm interrupt */ 91 #define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /*!< PMIC1 temp alarm interrupt */ 92 #define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /*!< PMIC2 temp alarm interrupt */ 93 #define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /*!< PMIC2 temp alarm interrupt */ 94 /*@}*/ 95 96 /*! 97 * @name Defines for sc_irq_wdog_t 98 */ 99 /*@{*/ 100 #define SC_IRQ_WDOG (1U << 0U) /*!< Watchdog interrupt */ 101 /*@}*/ 102 103 /*! 104 * @name Defines for sc_irq_rtc_t 105 */ 106 /*@{*/ 107 #define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ 108 /*@}*/ 109 110 /*! 111 * @name Defines for sc_irq_wake_t 112 */ 113 /*@{*/ 114 #define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt */ 115 #define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ 116 #define SC_IRQ_USR1 (1U << 2U) /*!< User defined 1 */ 117 #define SC_IRQ_USR2 (1U << 3U) /*!< User defined 2 */ 118 #define SC_IRQ_BC_PAD (1U << 4U) /*!< Pad wakeup (broadcast to all partitions) */ 119 #define SC_IRQ_SW_WAKE (1U << 5U) /*!< Software requested wake */ 120 #define SC_IRQ_SECVIO (1U << 6U) /*!< Security violation */ 121 /*@}*/ 122 123 /*! 124 * @name Defines for sc_irq_sysctr_t 125 */ 126 /*@{*/ 127 #define SC_IRQ_SYSCTR (1U << 0U) /*!< SYSCTR interrupt */ 128 /*@}*/ 129 130 /* Types */ 131 132 /*! 133 * This type is used to declare an interrupt group. 134 */ 135 typedef uint8_t sc_irq_group_t; 136 137 /*! 138 * This type is used to declare a bit mask of temp interrupts. 139 */ 140 typedef uint8_t sc_irq_temp_t; 141 142 /*! 143 * This type is used to declare a bit mask of watchdog interrupts. 144 */ 145 typedef uint8_t sc_irq_wdog_t; 146 147 /*! 148 * This type is used to declare a bit mask of RTC interrupts. 149 */ 150 typedef uint8_t sc_irq_rtc_t; 151 152 /*! 153 * This type is used to declare a bit mask of wakeup interrupts. 154 */ 155 typedef uint8_t sc_irq_wake_t; 156 157 /* Functions */ 158 159 /*! 160 * This function enables/disables interrupts. If pending interrupts 161 * are unmasked, an interrupt will be triggered. 162 * 163 * @param[in] ipc IPC handle 164 * @param[in] resource MU channel 165 * @param[in] group group the interrupts are in 166 * @param[in] mask mask of interrupts to affect 167 * @param[in] enable state to change interrupts to 168 * 169 * @return Returns an error code (SC_ERR_NONE = success). 170 * 171 * Return errors: 172 * - SC_PARM if group invalid 173 */ 174 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, 175 sc_irq_group_t group, uint32_t mask, sc_bool_t enable); 176 177 /*! 178 * This function returns the current interrupt status (regardless if 179 * masked). Automatically clears pending interrupts. 180 * 181 * @param[in] ipc IPC handle 182 * @param[in] resource MU channel 183 * @param[in] group groups the interrupts are in 184 * @param[in] status status of interrupts 185 * 186 * @return Returns an error code (SC_ERR_NONE = success). 187 * 188 * Return errors: 189 * - SC_PARM if group invalid 190 * 191 * The returned \a status may show interrupts pending that are 192 * currently masked. 193 */ 194 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, 195 sc_irq_group_t group, uint32_t *status); 196 197 #endif /* SC_IRQ_API_H */ 198 199 /**@}*/ 200 201
