1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2017-2020 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /*! 32 * Header file containing the public API for the System Controller (SC) 33 * Interrupt (IRQ) function. 34 * 35 * @addtogroup IRQ_SVC IRQ: Interrupt Service 36 * 37 * Module for the Interrupt (IRQ) service. 38 * 39 * @{ 40 */ 41 42 #ifndef SC_IRQ_API_H 43 #define SC_IRQ_API_H 44 45 /* Includes */ 46 47 #include "main/types.h" 48 49 /* Defines */ 50 51 #define SC_IRQ_NUM_GROUP 7U /*!< Number of groups */ 52 53 /*! 54 * @name Defines for sc_irq_group_t 55 */ 56 /*@{*/ 57 #define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ 58 #define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ 59 #define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ 60 #define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ 61 #define SC_IRQ_GROUP_SYSCTR 4U /*!< System counter interrupts */ 62 #define SC_IRQ_GROUP_REBOOTED 5U /*!< Partition reboot complete */ 63 #define SC_IRQ_GROUP_REBOOT 6U /*!< Partition reboot starting */ 64 /*@}*/ 65 66 /*! 67 * @name Defines for sc_irq_temp_t 68 */ 69 /*@{*/ 70 #define SC_IRQ_TEMP_HIGH (1UL << 0U) /*!< Temp alarm interrupt */ 71 #define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /*!< CPU0 temp alarm interrupt */ 72 #define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /*!< CPU1 temp alarm interrupt */ 73 #define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /*!< GPU0 temp alarm interrupt */ 74 #define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ 75 #define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /*!< DRC0 temp alarm interrupt */ 76 #define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /*!< DRC1 temp alarm interrupt */ 77 #define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /*!< DRC1 temp alarm interrupt */ 78 #define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /*!< PMIC0 temp alarm interrupt */ 79 #define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /*!< PMIC1 temp alarm interrupt */ 80 #define SC_IRQ_TEMP_LOW (1UL << 10U) /*!< Temp alarm interrupt */ 81 #define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /*!< CPU0 temp alarm interrupt */ 82 #define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /*!< CPU1 temp alarm interrupt */ 83 #define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /*!< GPU0 temp alarm interrupt */ 84 #define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /*!< GPU1 temp alarm interrupt */ 85 #define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /*!< DRC0 temp alarm interrupt */ 86 #define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /*!< DRC1 temp alarm interrupt */ 87 #define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /*!< DRC1 temp alarm interrupt */ 88 #define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /*!< PMIC0 temp alarm interrupt */ 89 #define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /*!< PMIC1 temp alarm interrupt */ 90 #define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /*!< PMIC2 temp alarm interrupt */ 91 #define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /*!< PMIC2 temp alarm interrupt */ 92 /*@}*/ 93 94 /*! 95 * @name Defines for sc_irq_wdog_t 96 */ 97 /*@{*/ 98 #define SC_IRQ_WDOG (1U << 0U) /*!< Watchdog interrupt */ 99 /*@}*/ 100 101 /*! 102 * @name Defines for sc_irq_rtc_t 103 */ 104 /*@{*/ 105 #define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ 106 /*@}*/ 107 108 /*! 109 * @name Defines for sc_irq_wake_t 110 */ 111 /*@{*/ 112 #define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt */ 113 #define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ 114 #define SC_IRQ_USR1 (1U << 2U) /*!< User defined 1 */ 115 #define SC_IRQ_USR2 (1U << 3U) /*!< User defined 2 */ 116 #define SC_IRQ_BC_PAD (1U << 4U) /*!< Pad wakeup (broadcast to all partitions) */ 117 #define SC_IRQ_SW_WAKE (1U << 5U) /*!< Software requested wake */ 118 #define SC_IRQ_SECVIO (1U << 6U) /*!< Security violation */ 119 /*@}*/ 120 121 /*! 122 * @name Defines for sc_irq_sysctr_t 123 */ 124 /*@{*/ 125 #define SC_IRQ_SYSCTR (1U << 0U) /*!< SYSCTR interrupt */ 126 /*@}*/ 127 128 /* Types */ 129 130 /*! 131 * This type is used to declare an interrupt group. 132 */ 133 typedef uint8_t sc_irq_group_t; 134 135 /*! 136 * This type is used to declare a bit mask of temp interrupts. 137 */ 138 typedef uint8_t sc_irq_temp_t; 139 140 /*! 141 * This type is used to declare a bit mask of watchdog interrupts. 142 */ 143 typedef uint8_t sc_irq_wdog_t; 144 145 /*! 146 * This type is used to declare a bit mask of RTC interrupts. 147 */ 148 typedef uint8_t sc_irq_rtc_t; 149 150 /*! 151 * This type is used to declare a bit mask of wakeup interrupts. 152 */ 153 typedef uint8_t sc_irq_wake_t; 154 155 /* Functions */ 156 157 /*! 158 * This function enables/disables interrupts. If pending interrupts 159 * are unmasked, an interrupt will be triggered. 160 * 161 * @param[in] ipc IPC handle 162 * @param[in] resource MU channel 163 * @param[in] group group the interrupts are in 164 * @param[in] mask mask of interrupts to affect 165 * @param[in] enable state to change interrupts to 166 * 167 * @return Returns an error code (SC_ERR_NONE = success). 168 * 169 * Return errors: 170 * - SC_PARM if group invalid 171 */ 172 sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, 173 sc_irq_group_t group, uint32_t mask, sc_bool_t enable); 174 175 /*! 176 * This function returns the current interrupt status (regardless if 177 * masked). Automatically clears pending interrupts. 178 * 179 * @param[in] ipc IPC handle 180 * @param[in] resource MU channel 181 * @param[in] group groups the interrupts are in 182 * @param[in] status status of interrupts 183 * 184 * @return Returns an error code (SC_ERR_NONE = success). 185 * 186 * Return errors: 187 * - SC_PARM if group invalid 188 * 189 * The returned \a status may show interrupts pending that are 190 * currently masked. 191 */ 192 sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, 193 sc_irq_group_t group, uint32_t *status); 194 195 #endif /* SC_IRQ_API_H */ 196 197 /**@}*/ 198 199
