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Searched refs:SCTFCLKDIV_OFFSET (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h469 #define SCTFCLKDIV_OFFSET 0x644 macro
779 … kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h469 #define SCTFCLKDIV_OFFSET 0x644 macro
779 … kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h591 #define SCTFCLKDIV_OFFSET 0x644 macro
978 … kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h591 #define SCTFCLKDIV_OFFSET 0x644 macro
978 … kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h591 #define SCTFCLKDIV_OFFSET 0x644 macro
978 … kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h810 #define SCTFCLKDIV_OFFSET 0x644 macro
1703 …kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< SCT functional Clk Di…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h810 #define SCTFCLKDIV_OFFSET 0x644 macro
1703 …kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< SCT functional Clk Di…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h810 #define SCTFCLKDIV_OFFSET 0x644 macro
1703 …kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< SCT functional Clk Di…