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Searched refs:SCG_APLLCSR_APLL_LOCK_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.h1513 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.h1513 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.h1840 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.h1840 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.h1840 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.h1840 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); in CLOCK_IsPLL0Locked()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53152 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
53158 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53110 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
53116 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64711 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
64717 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
DMCXN546_cm33_core1.h64711 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
64717 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64711 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
64717 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
DMCXN547_cm33_core1.h64711 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
64717 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65458 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
65464 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
DMCXN947_cm33_core0.h65458 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
65464 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65458 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
65464 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)
DMCXN946_cm33_core1.h65458 #define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) macro
65464 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK)