1 /*
2 * Copyright 2022-2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.0.0. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40 #endif
41
42 /*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51 #endif
52
53 /* Definition for delay API in clock driver, users can redefine it to the real application. */
54 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)
56 #endif
57
58 /*! @brief Clock ip name array for ROM. */
59 #define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63 /*! @brief Clock ip name array for SRAM. */
64 #define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4, kCLOCK_Sram5, kCLOCK_Sram6, kCLOCK_Sram7 \
67 }
68 /*! @brief Clock ip name array for FMC. */
69 #define FMC_CLOCKS \
70 { \
71 kCLOCK_Fmc \
72 }
73 /*! @brief Clock ip name array for INPUTMUX. */
74 #define INPUTMUX_CLOCKS \
75 { \
76 kCLOCK_InputMux0 \
77 }
78 /*! @brief Clock ip name array for GPIO. */
79 #define GPIO_CLOCKS \
80 { \
81 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4 \
82 }
83 /*! @brief Clock ip name array for PINT. */
84 #define PINT_CLOCKS \
85 { \
86 kCLOCK_Pint \
87 }
88 /*! @brief Clock ip name array for DMA. */
89 #define DMA_CLOCKS \
90 { \
91 kCLOCK_Dma0, kCLOCK_Dma1 \
92 }
93 /*! @brief Clock gate name array for EDMA. */
94 #define EDMA_CLOCKS \
95 { \
96 kCLOCK_Dma0, kCLOCK_Dma1 \
97 }
98 /*! @brief Clock ip name array for CRC. */
99 #define CRC_CLOCKS \
100 { \
101 kCLOCK_Crc0 \
102 }
103 /*! @brief Clock ip name array for WWDT. */
104 #define WWDT_CLOCKS \
105 { \
106 kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
107 }
108 /*! @brief Clock ip name array for LPADC. */
109 #define LPADC_CLOCKS \
110 { \
111 kCLOCK_Adc0, kCLOCK_Adc1 \
112 }
113 /*! @brief Clock ip name array for MRT. */
114 #define MRT_CLOCKS \
115 { \
116 kCLOCK_Mrt \
117 }
118 /*! @brief Clock ip name array for OSTIMER. */
119 #define OSTIMER_CLOCKS \
120 { \
121 kCLOCK_OsTimer \
122 }
123 /*! @brief Clock ip name array for UTICK. */
124 #define UTICK_CLOCKS \
125 { \
126 kCLOCK_Utick \
127 }
128 /*! @brief Clock ip name array for LP_FLEXCOMM. */
129 #define LP_FLEXCOMM_CLOCKS \
130 { \
131 kCLOCK_LPFlexComm0, kCLOCK_LPFlexComm1, kCLOCK_LPFlexComm2, kCLOCK_LPFlexComm3, kCLOCK_LPFlexComm4, \
132 kCLOCK_LPFlexComm5, kCLOCK_LPFlexComm6, kCLOCK_LPFlexComm7 \
133 }
134 /*! @brief Clock ip name array for LPUART. */
135 #define LPUART_CLOCKS \
136 { \
137 kCLOCK_LPUart0, kCLOCK_LPUart1, kCLOCK_LPUart2, kCLOCK_LPUart3, kCLOCK_LPUart4, kCLOCK_LPUart5, \
138 kCLOCK_LPUart6, kCLOCK_LPUart7 \
139 }
140 /*! @brief Clock ip name array for LPI2C. */
141 #define LPI2C_CLOCKS \
142 { \
143 kCLOCK_LPI2c0, kCLOCK_LPI2c1, kCLOCK_LPI2c2, kCLOCK_LPI2c3, kCLOCK_LPI2c4, kCLOCK_LPI2c5, kCLOCK_LPI2c6, \
144 kCLOCK_LPI2c7 \
145 }
146 /*! @brief Clock ip name array for LSPI. */
147 #define LPSPI_CLOCKS \
148 { \
149 kCLOCK_LPSpi0, kCLOCK_LPSpi1, kCLOCK_LPSpi2, kCLOCK_LPSpi3, kCLOCK_LPSpi4, kCLOCK_LPSpi5, kCLOCK_LPSpi6, \
150 kCLOCK_LPSpi7 \
151 }
152 /*! @brief Clock ip name array for CTIMER. */
153 #define CTIMER_CLOCKS \
154 { \
155 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
156 }
157 /*! @brief Clock ip name array for FREQME. */
158 #define FREQME_CLOCKS \
159 { \
160 kCLOCK_Freqme \
161 }
162 /*! @brief Clock ip name array for PUF. */
163 #define PUF_CLOCKS \
164 { \
165 kCLOCK_Puf \
166 }
167 /*! @brief Clock ip name array for VREF. */
168 #define VREF_CLOCKS \
169 { \
170 kCLOCK_Vref \
171 }
172 /*! @brief Clock ip name array for PWM. */
173 #define PWM_CLOCKS \
174 { \
175 {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \
176 { \
177 kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \
178 } \
179 }
180 /*! @brief Clock ip name array for QDC. */
181 #define QDC_CLOCKS \
182 { \
183 kCLOCK_Qdc0, kCLOCK_Qdc1 \
184 }
185 /*! @brief Clock ip name array for FLEXIO. */
186 #define FLEXIO_CLOCKS \
187 { \
188 kCLOCK_Flexio \
189 }
190 /*! @brief Clock ip name array for FLEXCAN. */
191 #define FLEXCAN_CLOCKS \
192 { \
193 kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
194 }
195 /*! @brief Clock ip name array for I3C */
196 #define I3C_CLOCKS \
197 { \
198 kCLOCK_I3c0, kCLOCK_I3c1 \
199 }
200 /*! @brief Clock ip name array for USDHC. */
201 #define USDHC_CLOCKS \
202 { \
203 kCLOCK_uSdhc \
204 }
205 /*! @brief Clock ip name array for SAI. */
206 #define SAI_CLOCKS \
207 { \
208 kCLOCK_Sai0, kCLOCK_Sai1 \
209 }
210 /*! @brief Clock ip name array for RTC. */
211 #define RTC_CLOCKS \
212 { \
213 kCLOCK_Rtc0 \
214 }
215 /*! @brief Clock ip name array for PDM. */
216 #define PDM_CLOCKS \
217 { \
218 kCLOCK_Micfil \
219 }
220 /*! @brief Clock ip name array for ERM. */
221 #define ERM_CLOCKS \
222 { \
223 kCLOCK_Erm \
224 }
225 /*! @brief Clock ip name array for EIM. */
226 #define EIM_CLOCKS \
227 { \
228 kCLOCK_Eim \
229 }
230 /*! @brief Clock ip name array for TRNG. */
231 #define TRNG_CLOCKS \
232 { \
233 kCLOCK_Trng \
234 }
235 /*! @brief Clock ip name array for LPCMP. */
236 #define LPCMP_CLOCKS \
237 { \
238 kCLOCK_None, kCLOCK_None, kCLOCK_Cmp2 \
239 }
240 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
241 /*------------------------------------------------------------------------------
242 clock_ip_name_t definition:
243 ------------------------------------------------------------------------------*/
244
245 #define CLK_GATE_REG_OFFSET_SHIFT 8U
246 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
247 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
248 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
249
250 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
251 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
252 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
253
254 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
255 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
256
257 #define AHB_CLK_CTRL0 0
258 #define AHB_CLK_CTRL1 1
259 #define AHB_CLK_CTRL2 2
260 #define AHB_CLK_CTRL3 3
261 #define REG_PWM0SUBCTL 250
262 #define REG_PWM1SUBCTL 251
263
264 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
265 typedef enum _clock_ip_name
266 {
267 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
268 kCLOCK_None = 0U, /*!< None clock gate. */
269
270 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
271 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */
272 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */
273 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */
274 kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */
275 kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */
276 kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */
277 kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */
278 kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */
279 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */
280 kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */
281 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */
282 kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */
283 kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */
284 kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */
285 kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */
286 kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */
287 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */
288 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */
289 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */
290 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */
291 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */
292 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */
293 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */
294 kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */
295 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */
296 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */
297
298 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
299 kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */
300 kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */
301 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */
302 kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */
303 kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */
304 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */
305 kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPFlexComm0. */
306 kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPFlexComm1. */
307 kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPFlexComm2. */
308 kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPFlexComm3. */
309 kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPFlexComm4. */
310 kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPFlexComm5. */
311 kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPFlexComm6. */
312 kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPFlexComm7. */
313 kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */
314 kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */
315 kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */
316 kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */
317 kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */
318 kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */
319 kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */
320 kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */
321 kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */
322 kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */
323 kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */
324 kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */
325 kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */
326 kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */
327 kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */
328 kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */
329 kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */
330 kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */
331 kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */
332 kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */
333 kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */
334 kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */
335 kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */
336 kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */
337 kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */
338 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */
339 kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */
340 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */
341 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */
342 kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */
343 kCLOCK_Smartdma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */
344
345 kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */
346 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */
347 kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */
348 kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */
349 kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */
350 kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */
351 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */
352 kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */
353 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */
354 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */
355 kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */
356 kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */
357 kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */
358 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */
359 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */
360 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */
361 kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */
362 kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */
363 kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */
364 kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */
365
366 kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */
367 kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */
368 kCLOCK_Qdc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Qdc0. */
369 kCLOCK_Qdc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Qdc1. */
370 kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */
371 kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */
372 kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */
373 kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */
374 kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */
375 kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */
376 kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */
377 kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */
378 kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */
379 kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */
380
381 kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */
382 kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */
383 kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */
384 kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */
385
386 kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */
387 kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */
388 kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */
389 kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */
390
391 } clock_ip_name_t;
392
393 /*! @brief Peripherals clock source definition. */
394 #define BUS_CLK kCLOCK_BusClk
395
396 #define I2C0_CLK_SRC BUS_CLK
397
398 /*! @brief Clock name used to get clock frequency. */
399 typedef enum _clock_name
400 {
401 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
402 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
403 kCLOCK_SystickClk0, /*!< Systick clock0 */
404 kCLOCK_ClockOut, /*!< CLOCKOUT */
405 kCLOCK_Fro12M, /*!< FRO12M */
406 kCLOCK_Clk1M, /*!< CLK1M */
407 kCLOCK_FroHf, /*!< FRO48/144 */
408 kCLOCK_Clk48M, /*!< CLK48M */
409 kCLOCK_Clk144M, /*!< CLK144M */
410 kCLOCK_Clk16K0, /*!< CLK16K[0] */
411 kCLOCK_Clk16K1, /*!< CLK16K[1] */
412 kCLOCK_Clk16K2, /*!< CLK16K[2] */
413 kCLOCK_Clk16K3, /*!< CLK16K[3] */
414 kCLOCK_ExtClk, /*!< External Clock */
415 kCLOCK_Osc32K0, /*!< OSC32K[0] */
416 kCLOCK_Osc32K1, /*!< OSC32K[1] */
417 kCLOCK_Osc32K2, /*!< OSC32K[2] */
418 kCLOCK_Osc32K3, /*!< OSC32K[3] */
419 kCLOCK_Pll0Out, /*!< PLL0 Output */
420 kCLOCK_Pll1Out, /*!< PLL1 Output */
421 kCLOCK_UsbPllOut, /*!< USB PLL Output */
422 kCLOCK_LpOsc, /*!< lp_osc */
423 } clock_name_t;
424
425 /*! @brief Clock Mux Switches
426 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
427 * starting from LSB upwards
428 *
429 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
430 *
431 */
432
433 #define CLK_ATTACH_ID(mux, sel, pos) \
434 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U))
435 #define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
436 #define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
437
438 #define GET_ID_ITEM(connection) ((connection)&0xFFFFU)
439 #define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U)
440 #define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU)
441 #define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U))
442 #define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
443
444 #define CM_SYSTICKCLKSEL0 0U
445 #define CM_TRACECLKSEL ((0x268 - 0x260) / 4)
446 #define CM_CTIMERCLKSEL0 ((0x26C - 0x260) / 4)
447 #define CM_CTIMERCLKSEL1 ((0x270 - 0x260) / 4)
448 #define CM_CTIMERCLKSEL2 ((0x274 - 0x260) / 4)
449 #define CM_CTIMERCLKSEL3 ((0x278 - 0x260) / 4)
450 #define CM_CTIMERCLKSEL4 ((0x27C - 0x260) / 4)
451 #define CM_CLKOUTCLKSEL ((0x288 - 0x260) / 4)
452 #define CM_ADC0CLKSEL ((0x2A4 - 0x260) / 4)
453 #define CM_FCCLKSEL0 ((0x2B0 - 0x260) / 4)
454 #define CM_FCCLKSEL1 ((0x2B4 - 0x260) / 4)
455 #define CM_FCCLKSEL2 ((0x2B8 - 0x260) / 4)
456 #define CM_FCCLKSEL3 ((0x2BC - 0x260) / 4)
457 #define CM_FCCLKSEL4 ((0x2C0 - 0x260) / 4)
458 #define CM_FCCLKSEL5 ((0x2C4 - 0x260) / 4)
459 #define CM_FCCLKSEL6 ((0x2C8 - 0x260) / 4)
460 #define CM_FCCLKSEL7 ((0x2CC - 0x260) / 4)
461 #define CM_ADC1CLKSEL ((0x464 - 0x260) / 4)
462 #define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4)
463 #define CM_I3C0FCLKSEL ((0x530 - 0x260) / 4)
464 #define CM_MICFILFCLKSEL ((0x548 - 0x260) / 4)
465 #define CM_FLEXIOCLKSEL ((0x560 - 0x260) / 4)
466 #define CM_FLEXCAN0CLKSEL ((0x5A0 - 0x260) / 4)
467 #define CM_FLEXCAN1CLKSEL ((0x5A8 - 0x260) / 4)
468 #define CM_EWM0CLKSEL ((0x5D4 - 0x260) / 4)
469 #define CM_WDT1CLKSEL ((0x5D8 - 0x260) / 4)
470 #define CM_OSTIMERCLKSEL ((0x5E0 - 0x260) / 4)
471 #define CM_CMP0FCLKSEL ((0x5F0 - 0x260) / 4)
472 #define CM_CMP0RRCLKSEL ((0x5F8 - 0x260) / 4)
473 #define CM_CMP1FCLKSEL ((0x600 - 0x260) / 4)
474 #define CM_CMP1RRCLKSEL ((0x608 - 0x260) / 4)
475 #define CM_UTICKCLKSEL ((0x878 - 0x260) / 4)
476 #define CM_SAI0CLKSEL ((0x880 - 0x260) / 4)
477 #define CM_SAI1CLKSEL ((0x884 - 0x260) / 4)
478 #define CM_I3C1FCLKSEL ((0xB30 - 0x260) / 4)
479
480 #define CM_SCGRCCRSCSCLKSEL 0x3FEU
481
482 /*!
483 * @brief The enumerator of clock attach Id.
484 */
485 typedef enum _clock_attach_id
486 {
487 kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */
488 kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */
489 kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */
490 kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */
491 kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */
492 kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */
493 kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */
494 kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */
495
496 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */
497 kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */
498 kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */
499 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
500
501 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
502 kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */
503 kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */
504 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
505
506 kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */
507 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
508 kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */
509 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
510 kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */
511 kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */
512 kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */
513 kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */
514 kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */
515 kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */
516 kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */
517 kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */
518 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */
519
520 kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */
521 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
522 kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */
523 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
524 kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */
525 kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */
526 kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */
527 kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */
528 kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */
529 kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */
530 kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */
531 kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */
532 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */
533
534 kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */
535 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
536 kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */
537 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
538 kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */
539 kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */
540 kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */
541 kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */
542 kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */
543 kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */
544 kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */
545 kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */
546 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */
547
548 kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */
549 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
550 kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */
551 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
552 kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */
553 kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */
554 kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */
555 kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */
556 kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */
557 kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */
558 kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */
559 kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */
560 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */
561
562 kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */
563 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
564 kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */
565 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
566 kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */
567 kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */
568 kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */
569 kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */
570 kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */
571 kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */
572 kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */
573 kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */
574 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */
575
576 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
577 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
578 kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */
579 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
580 kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */
581 kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */
582 kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */
583 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */
584 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */
585
586 kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */
587 kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */
588 kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */
589 kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */
590 kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */
591 kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */
592 kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */
593
594 kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */
595 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
596 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
597 kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */
598 kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */
599 kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */
600 kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
601
602 kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */
603 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
604 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
605 kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */
606 kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */
607 kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */
608 kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
609
610 kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */
611 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
612 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
613 kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */
614 kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */
615 kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */
616 kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
617
618 kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */
619 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
620 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
621 kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */
622 kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */
623 kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */
624 kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
625
626 kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */
627 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
628 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
629 kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */
630 kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */
631 kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */
632 kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
633
634 kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */
635 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
636 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
637 kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */
638 kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */
639 kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */
640 kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
641
642 kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */
643 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
644 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
645 kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */
646 kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */
647 kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */
648 kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
649
650 kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */
651 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */
652 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */
653 kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */
654 kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */
655 kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */
656 kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
657
658 kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */
659 kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */
660 kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */
661 kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */
662 kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */
663 kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */
664 kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */
665
666 kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */
667 kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */
668 kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */
669
670 kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */
671 kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */
672 kCLK_1M_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLK. */
673 kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */
674 kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */
675 kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */
676
677 kPLL0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKSTC. */
678 kFRO_HF_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKSTC. */
679 kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKSTC. */
680 kPLL1_CLK0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKSTC. */
681 kUSB_PLL_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKSTC. */
682 kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */
683
684 kPLL0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKS. */
685 kFRO_HF_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKS. */
686 kCLK_1M_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKS. */
687 kPLL1_CLK0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKS. */
688 kUSB_PLL_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKS. */
689 kNONE_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKS. */
690
691 kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */
692 kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */
693 kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */
694 kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */
695 kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */
696 kSAI0_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */
697 kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */
698 kSAI1_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */
699 kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */
700
701 kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */
702 kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */
703 kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */
704 kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */
705 kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */
706 kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */
707 kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */
708
709 kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */
710 kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */
711 kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */
712 kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */
713 kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */
714 kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */
715
716 kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */
717 kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */
718 kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */
719 kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */
720 kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */
721 kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */
722
723 kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */
724 kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */
725
726 kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */
727 kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */
728 kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */
729 kCLK_1M_2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach clk_1m to WDT1. */
730
731 kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */
732 kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */
733 kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */
734 kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */
735
736 kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */
737 kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */
738 kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */
739 kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */
740 kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */
741 kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */
742 kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */
743
744 kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */
745 kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */
746 kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */
747 kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */
748 kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */
749 kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */
750 kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */
751
752 kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */
753 kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */
754 kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */
755 kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */
756 kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */
757 kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */
758 kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */
759
760 kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */
761 kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */
762 kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */
763 kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */
764 kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */
765 kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */
766 kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */
767
768 kCLK_IN_to_UTICK = MUX_A(CM_UTICKCLKSEL, 0), /*!< Attach Clk_in to UTICK. */
769 kXTAL32K2_to_UTICK = MUX_A(CM_UTICKCLKSEL, 1), /*!< Attach xtal32k[2] to UTICK. */
770 kCLK_1M_to_UTICK = MUX_A(CM_UTICKCLKSEL, 2), /*!< Attach clk_1m to UTICK. */
771 kNONE_to_UTICK = MUX_A(CM_UTICKCLKSEL, 3), /*!< Attach NONE to UTICK. */
772
773 kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */
774 kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */
775 kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */
776 kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */
777 kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */
778 kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */
779
780 kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */
781 kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */
782 kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */
783 kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */
784 kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */
785 kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */
786
787 kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */
788 kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */
789 kCLK_1M_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLK. */
790 kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */
791 kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */
792 kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */
793
794 kPLL0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKSTC. */
795 kFRO_HF_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKSTC. */
796 kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKSTC. */
797 kPLL1_CLK0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKSTC. */
798 kUSB_PLL_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKSTC. */
799 kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */
800
801 kPLL0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKS. */
802 kFRO_HF_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKS. */
803 kCLK_1M_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKS. */
804 kPLL1_CLK0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKS. */
805 kUSB_PLL_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKS. */
806 kNONE_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKS. */
807
808 kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
809
810 } clock_attach_id_t;
811
812 /*! @brief Clock dividers */
813 typedef enum _clock_div_name
814 {
815 kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */
816 kCLOCK_DivTraceClk = ((0x308 - 0x300) / 4), /*!< Trace Clk Divider. */
817 kCLOCK_DivSlowClk = ((0x378 - 0x300) / 4), /*!< SLOW CLK Divider. */
818 kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clk Divider. */
819 kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< ClkOut Clk Divider. */
820 kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Clk Divider. */
821 kCLOCK_DivWdt0Clk = ((0x38C - 0x300) / 4), /*!< Wdt0 Clk Divider. */
822 kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clk Divider. */
823 kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll Clk Divider. */
824 kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clk Divider. */
825 kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clk Divider. */
826 kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clk Divider. */
827 kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clk Divider. */
828 kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clk Divider. */
829 kCLOCK_DivPLL1Clk0 = ((0x3E4 - 0x300) / 4), /*!< PLL1 Clk0 Divider. */
830 kCLOCK_DivPLL1Clk1 = ((0x3E8 - 0x300) / 4), /*!< Pll1 Clk1 Divider. */
831 kCLOCK_DivUtickClk = ((0x3F0 - 0x300) / 4), /*!< Utick Clk Divider. */
832 kCLOCK_DivFrg = ((0x3F4 - 0x300) / 4), /*!< CLKOUT FRG Clk Divider. */
833 kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clk Divider. */
834 kCLOCK_DivI3c0FClk = ((0x540 - 0x300) / 4), /*!< I3C0 FClk Divider. */
835 kCLOCK_DivMicfilFClk = ((0x54C - 0x300) / 4), /*!< MICFILFCLK Divider. */
836 kCLOCK_DivFlexioClk = ((0x564 - 0x300) / 4), /*!< Flexio Clk Divider. */
837 kCLOCK_DivFlexcan0Clk = ((0x5A4 - 0x300) / 4), /*!< Flexcan0 Clk Divider. */
838 kCLOCK_DivFlexcan1Clk = ((0x5AC - 0x300) / 4), /*!< Flexcan1 Clk Divider. */
839 kCLOCK_DivWdt1Clk = ((0x5DC - 0x300) / 4), /*!< Wdt1 Clk Divider. */
840 kCLOCK_DivCmp0FClk = ((0x5F4 - 0x300) / 4), /*!< Cmp0 FClk Divider. */
841 kCLOCK_DivCmp0rrClk = ((0x5FC - 0x300) / 4), /*!< Cmp0rr Clk Divider. */
842 kCLOCK_DivCmp1FClk = ((0x604 - 0x300) / 4), /*!< Cmp1 FClk Divider. */
843 kCLOCK_DivCmp1rrClk = ((0x60C - 0x300) / 4), /*!< Cmp1rr Clk Divider. */
844 kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clk Divider. */
845 kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clk Divider. */
846 kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clk Divider. */
847 kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clk Divider. */
848 kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clk Divider. */
849 kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clk Divider. */
850 kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clk Divider. */
851 kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clk Divider. */
852 kCLOCK_DivSai0Clk = ((0x888 - 0x300) / 4), /*!< Sai0 Clk Divider. */
853 kCLOCK_DivSai1Clk = ((0x88C - 0x300) / 4), /*!< Sai1 Clk Divider. */
854 kCLOCK_DivI3c1FClk = ((0xB40 - 0x300) / 4), /*!< I3C1 FClk Divider. */
855 } clock_div_name_t;
856
857 /*! @brief OSC32K clock gate */
858 typedef enum _osc32k_clk_gate_id
859 {
860 kCLOCK_Osc32kToVbat = 0x1, /*!< OSC32K[0] to VBAT domain. */
861 kCLOCK_Osc32kToVsys = 0x2, /*!< OSC32K[1] to VSYS domain. */
862 kCLOCK_Osc32kToWake = 0x4, /*!< OSC32K[2] to WAKE domain. */
863 kCLOCK_Osc32kToMain = 0x8, /*!< OSC32K[3] to MAIN domain. */
864 kCLOCK_Osc32kToAll = 0xF, /*!< OSC32K to VBAT,VSYS,WAKE,MAIN domain. */
865 } osc32k_clk_gate_id_t;
866
867 /*! @brief CLK16K clock gate */
868 typedef enum _clk16k_clk_gate_id
869 {
870 kCLOCK_Clk16KToVbat = 0x1, /*!< Clk16k[0] to VBAT domain. */
871 kCLOCK_Clk16KToVsys = 0x2, /*!< Clk16k[1] to VSYS domain. */
872 kCLOCK_Clk16KToWake = 0x4, /*!< Clk16k[2] to WAKE domain. */
873 kCLOCK_Clk16KToMain = 0x8, /*!< Clk16k[3] to MAIN domain. */
874 kCLOCK_Clk16KToAll = 0xF, /*!< Clk16k to VBAT,VSYS,WAKE,MAIN domain. */
875 } clk16k_clk_gate_id_t;
876
877 /*! @brief system clocks enable controls */
878 typedef enum _clock_ctrl_enable
879 {
880 kCLOCK_FRO1MHZ_CLK_ENA =
881 SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */
882 kCLOCK_CLKIN_ENA = SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1,
883 SAI0/1, clkout */
884 kCLOCK_FRO_HF_ENA =
885 SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK, /*!< Enables FRO HF clock for the Frequency Measure module. */
886 kCLOCK_FRO12MHZ_ENA = SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK, /*!< Enables the FRO_12MHz clock for the Flash,
887 LPTIMER0/1, and Frequency Measurement modules. */
888 kCLOCK_FRO1MHZ_ENA =
889 SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */
890 kCLOCK_CLKIN_ENA_FM_USBH_LPT =
891 SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK, /*!< Enables the clk_in clock for the Frequency Measurement, USB
892 HS and LPTIMER0/1 modules. */
893 } clock_ctrl_enable_t;
894
895 /*! @brief Source of the USB HS PHY. */
896 typedef enum _clock_usb_phy_src
897 {
898 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
899 } clock_usb_phy_src_t;
900
901 /*!
902 * @brief SCG status return codes.
903 */
904 enum _scg_status
905 {
906 kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */
907 kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */
908 };
909
910 /*!
911 * @brief firc trim mode.
912 */
913 typedef enum _firc_trim_mode
914 {
915 kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK,
916 /*!< Trim enable but not enable trim value update. In this mode, the
917 trim value is fixed to the initialized value which is defined by
918 trimCoar and trimFine in configure structure \ref trim_config_t.*/
919
920 kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK
921 /*!< Trim enable and trim value update enable. In this mode, the trim
922 value is auto update. */
923
924 } firc_trim_mode_t;
925
926 /*!
927 * @brief firc trim source.
928 */
929 typedef enum _firc_trim_src
930 {
931 kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */
932 kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */
933 kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */
934 } firc_trim_src_t;
935
936 /*!
937 * @brief firc trim configuration.
938 */
939 typedef struct _firc_trim_config
940 {
941 firc_trim_mode_t trimMode; /*!< Trim mode. */
942 firc_trim_src_t trimSrc; /*!< Trim source. */
943 uint16_t trimDiv; /*!< Divider of SOSC. */
944
945 uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
946 uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
947 } firc_trim_config_t;
948
949 /*!
950 * @brief sirc trim mode.
951 */
952 typedef enum _sirc_trim_mode
953 {
954 kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK,
955 /*!< Trim enable but not enable trim value update. In this mode, the
956 trim value is fixed to the initialized value which is defined by
957 trimCoar and trimFine in configure structure \ref trim_config_t.*/
958
959 kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK
960 /*!< Trim enable and trim value update enable. In this mode, the trim
961 value is auto update. */
962
963 } sirc_trim_mode_t;
964
965 /*!
966 * @brief sirc trim source.
967 */
968 typedef enum _sirc_trim_src
969 {
970 kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */
971 kSCG_SircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */
972 } sirc_trim_src_t;
973
974 /*!
975 * @brief sirc trim configuration.
976 */
977 typedef struct _sirc_trim_config
978 {
979 sirc_trim_mode_t trimMode; /*!< Trim mode. */
980 sirc_trim_src_t trimSrc; /*!< Trim source. */
981 uint16_t trimDiv; /*!< Divider of SOSC. */
982
983 uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
984 uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
985 } sirc_trim_config_t;
986
987 /*!
988 * @brief SCG system OSC monitor mode.
989 */
990 typedef enum _scg_sosc_monitor_mode
991 {
992 kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */
993 kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */
994 kSCG_SysOscMonitorReset =
995 SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */
996 } scg_sosc_monitor_mode_t;
997
998 /*!
999 * @brief SCG ROSC monitor mode.
1000 */
1001 typedef enum _scg_rosc_monitor_mode
1002 {
1003 kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */
1004 kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */
1005 kSCG_RoscMonitorReset =
1006 SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */
1007 } scg_rosc_monitor_mode_t;
1008
1009 /*!
1010 * @brief SCG UPLL monitor mode.
1011 */
1012 typedef enum _scg_upll_monitor_mode
1013 {
1014 kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */
1015 kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */
1016 kSCG_UpllMonitorReset =
1017 SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK /*!< Reset when the UPLL error is detected. */
1018 } scg_upll_monitor_mode_t;
1019
1020 /*!
1021 * @brief SCG PLL0 monitor mode.
1022 */
1023 typedef enum _scg_pll0_monitor_mode
1024 {
1025 kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */
1026 kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */
1027 kSCG_Pll0MonitorReset =
1028 SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detected. */
1029 } scg_pll0_monitor_mode_t;
1030
1031 /*!
1032 * @brief SCG PLL1 monitor mode.
1033 */
1034 typedef enum _scg_pll1_monitor_mode
1035 {
1036 kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */
1037 kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */
1038 kSCG_Pll1MonitorReset =
1039 SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */
1040 } scg_pll1_monitor_mode_t;
1041
1042 /*!
1043 * @brief The enumerator of internal capacitance of OSC's XTAL pin.
1044 */
1045 typedef enum _vbat_osc_xtal_cap
1046 {
1047 kVBAT_OscXtal0pFCap = 0x0U, /*!< The internal capacitance for XTAL pin is 0pF. */
1048 kVBAT_OscXtal2pFCap = 0x1U, /*!< The internal capacitance for XTAL pin is 2pF. */
1049 kVBAT_OscXtal4pFCap = 0x2U, /*!< The internal capacitance for XTAL pin is 4pF. */
1050 kVBAT_OscXtal6pFCap = 0x3U, /*!< The internal capacitance for XTAL pin is 6pF. */
1051 kVBAT_OscXtal8pFCap = 0x4U, /*!< The internal capacitance for XTAL pin is 8pF. */
1052 kVBAT_OscXtal10pFCap = 0x5U, /*!< The internal capacitance for XTAL pin is 10pF. */
1053 kVBAT_OscXtal12pFCap = 0x6U, /*!< The internal capacitance for XTAL pin is 12pF. */
1054 kVBAT_OscXtal14pFCap = 0x7U, /*!< The internal capacitance for XTAL pin is 14pF. */
1055 kVBAT_OscXtal16pFCap = 0x8U, /*!< The internal capacitance for XTAL pin is 16pF. */
1056 kVBAT_OscXtal18pFCap = 0x9U, /*!< The internal capacitance for XTAL pin is 18pF. */
1057 kVBAT_OscXtal20pFCap = 0xAU, /*!< The internal capacitance for XTAL pin is 20pF. */
1058 kVBAT_OscXtal22pFCap = 0xBU, /*!< The internal capacitance for XTAL pin is 22pF. */
1059 kVBAT_OscXtal24pFCap = 0xCU, /*!< The internal capacitance for XTAL pin is 24pF. */
1060 kVBAT_OscXtal26pFCap = 0xDU, /*!< The internal capacitance for XTAL pin is 26pF. */
1061 kVBAT_OscXtal28pFCap = 0xEU, /*!< The internal capacitance for XTAL pin is 28pF. */
1062 kVBAT_OscXtal30pFCap = 0xFU, /*!< The internal capacitance for XTAL pin is 30pF. */
1063 } vbat_osc_xtal_cap_t;
1064
1065 /*!
1066 * @brief The enumerator of internal capacitance of OSC's EXTAL pin.
1067 */
1068 typedef enum _vbat_osc_extal_cap
1069 {
1070 kVBAT_OscExtal0pFCap = 0x0U, /*!< The internal capacitance for EXTAL pin is 0pF. */
1071 kVBAT_OscExtal2pFCap = 0x1U, /*!< The internal capacitance for EXTAL pin is 2pF. */
1072 kVBAT_OscExtal4pFCap = 0x2U, /*!< The internal capacitance for EXTAL pin is 4pF. */
1073 kVBAT_OscExtal6pFCap = 0x3U, /*!< The internal capacitance for EXTAL pin is 6pF. */
1074 kVBAT_OscExtal8pFCap = 0x4U, /*!< The internal capacitance for EXTAL pin is 8pF. */
1075 kVBAT_OscExtal10pFCap = 0x5U, /*!< The internal capacitance for EXTAL pin is 10pF. */
1076 kVBAT_OscExtal12pFCap = 0x6U, /*!< The internal capacitance for EXTAL pin is 12pF. */
1077 kVBAT_OscExtal14pFCap = 0x7U, /*!< The internal capacitance for EXTAL pin is 14pF. */
1078 kVBAT_OscExtal16pFCap = 0x8U, /*!< The internal capacitance for EXTAL pin is 16pF. */
1079 kVBAT_OscExtal18pFCap = 0x9U, /*!< The internal capacitance for EXTAL pin is 18pF. */
1080 kVBAT_OscExtal20pFCap = 0xAU, /*!< The internal capacitance for EXTAL pin is 20pF. */
1081 kVBAT_OscExtal22pFCap = 0xBU, /*!< The internal capacitance for EXTAL pin is 22pF. */
1082 kVBAT_OscExtal24pFCap = 0xCU, /*!< The internal capacitance for EXTAL pin is 24pF. */
1083 kVBAT_OscExtal26pFCap = 0xDU, /*!< The internal capacitance for EXTAL pin is 26pF. */
1084 kVBAT_OscExtal28pFCap = 0xEU, /*!< The internal capacitance for EXTAL pin is 28pF. */
1085 kVBAT_OscExtal30pFCap = 0xFU, /*!< The internal capacitance for EXTAL pin is 30pF. */
1086 } vbat_osc_extal_cap_t;
1087
1088 /*!
1089 * @brief The enumerator of osc amplifier gain fine adjustment.
1090 * Changes the oscillator amplitude by modifying the automatic gain control (AGC).
1091 */
1092 typedef enum _vbat_osc_fine_adjustment_value
1093 {
1094 kVBAT_OscCoarseAdjustment05 = 0U,
1095 kVBAT_OscCoarseAdjustment10 = 1U,
1096 kVBAT_OscCoarseAdjustment18 = 2U,
1097 kVBAT_OscCoarseAdjustment33 = 3U,
1098 } vbat_osc_coarse_adjustment_value_t;
1099
1100 /*!
1101 * @brief The structure of oscillator configuration.
1102 */
1103 typedef struct _vbat_osc_config
1104 {
1105 bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */
1106
1107 bool enableCrystalOscillatorBypass; /*!< enable/disable the crystal oscillator bypass. */
1108
1109 vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank,
1110 only useful when the internal capacitance bank is enabled. */
1111 vbat_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank, only
1112 useful when the internal capacitance bank is enabled. */
1113 vbat_osc_coarse_adjustment_value_t
1114 coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */
1115 } vbat_osc_config_t;
1116
1117 /*!
1118 * @brief The active run mode (voltage level).
1119 */
1120 typedef enum _run_mode
1121 {
1122 kMD_Mode, /*!< Midvoltage (1.0 V). */
1123 kSD_Mode, /*!< Normal voltage (1.1 V). */
1124 kOD_Mode, /*!< Overdrive voltage (1.2 V). */
1125 } run_mode_t;
1126
1127 /*******************************************************************************
1128 * API
1129 ******************************************************************************/
1130
1131 #if defined(__cplusplus)
1132 extern "C" {
1133 #endif /* __cplusplus */
1134
1135 /**
1136 * @brief Enable the clock for specific IP.
1137 * @param clk : Clock to be enabled.
1138 * @return Nothing
1139 */
CLOCK_EnableClock(clock_ip_name_t clk)1140 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
1141 {
1142 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
1143 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk);
1144
1145 if (index == (uint32_t)REG_PWM0SUBCTL)
1146 {
1147 SYSCON->PWM0SUBCTL |= (1UL << bit);
1148 SYSCON->AHBCLKCTRLSET[3] = 0x40U;
1149 }
1150 else if (index == (uint32_t)REG_PWM1SUBCTL)
1151 {
1152 SYSCON->PWM1SUBCTL |= (1UL << bit);
1153 SYSCON->AHBCLKCTRLSET[3] = 0x80U;
1154 }
1155 else
1156 {
1157 SYSCON->AHBCLKCTRLSET[index] = (1UL << bit);
1158 }
1159 }
1160
1161 /**
1162 * @brief Disable the clock for specific IP.
1163 * @param clk : Clock to be Disabled.
1164 * @return Nothing
1165 */
CLOCK_DisableClock(clock_ip_name_t clk)1166 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
1167 {
1168 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
1169 uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk);
1170
1171 if (index == (uint32_t)REG_PWM0SUBCTL)
1172 {
1173 SYSCON->PWM0SUBCTL &= ~(1UL << bit);
1174 if (0U == (SYSCON->PWM0SUBCTL & 0xFU))
1175 {
1176 SYSCON->AHBCLKCTRLCLR[3] = 0x20U;
1177 }
1178 }
1179 else if (index == (uint32_t)REG_PWM1SUBCTL)
1180 {
1181 SYSCON->PWM1SUBCTL &= ~(1UL << bit);
1182 if (0U == (SYSCON->PWM1SUBCTL & 0xFU))
1183 {
1184 SYSCON->AHBCLKCTRLCLR[3] = 0x40U;
1185 }
1186 }
1187 else
1188 {
1189 SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit);
1190 }
1191 }
1192
1193 /**
1194 * @brief Initialize the Core clock to given frequency (48 or 144 MHz).
1195 * This function turns on FIRC and select the given frequency as the source of fro_hf
1196 * @param iFreq : Desired frequency (must be one of CLK_FRO_44MHZ or CLK_FRO_144MHZ)
1197 * @return returns success or fail status.
1198 */
1199 status_t CLOCK_SetupFROHFClocking(uint32_t iFreq);
1200
1201 /**
1202 * @brief Initialize the external osc clock to given frequency.
1203 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1204 * @return returns success or fail status.
1205 */
1206 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
1207
1208 /**
1209 * @brief Initialize the external reference clock to given frequency.
1210 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
1211 * @return returns success or fail status.
1212 */
1213 status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
1214
1215 /**
1216 * @brief Initialize the XTAL32/EXTAL32 input clock to given frequency.
1217 * @param id : OSC 32 kHz output clock to specified modules, it should use osc32k_clk_gate_id_t value
1218 * @return returns success or fail status.
1219 */
1220 status_t CLOCK_SetupOsc32KClocking(uint32_t id);
1221
1222 /**
1223 * @brief Initialize the FRO16K input clock to given frequency.
1224 * @param id : FRO 16 kHz output clock to specified modules, it should use clk16k_clk_gate_id_t value
1225 * @return returns success or fail status.
1226 */
1227 status_t CLOCK_SetupClk16KClocking(uint32_t id);
1228
1229 /**
1230 * @brief Setup FROHF trim.
1231 * @param config : FROHF trim value
1232 * @return returns success or fail status.
1233 */
1234 status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config);
1235
1236 /**
1237 * @brief Setup FRO 12M trim.
1238 * @param config : FRO 12M trim value
1239 * @return returns success or fail status.
1240 */
1241 status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config);
1242
1243 /*!
1244 * @brief Sets the system OSC monitor mode.
1245 *
1246 * This function sets the system OSC monitor mode. The mode can be disabled,
1247 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1248 *
1249 * @param mode Monitor mode to set.
1250 */
1251 void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode);
1252
1253 /*!
1254 * @brief Sets the ROSC monitor mode.
1255 *
1256 * This function sets the ROSC monitor mode. The mode can be disabled,
1257 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1258 *
1259 * @param mode Monitor mode to set.
1260 */
1261 void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode);
1262
1263 /*!
1264 * @brief Sets the UPLL monitor mode.
1265 *
1266 * This function sets the UPLL monitor mode. The mode can be disabled,
1267 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1268 *
1269 * @param mode Monitor mode to set.
1270 */
1271 void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode);
1272
1273 /*!
1274 * @brief Sets the PLL0 monitor mode.
1275 *
1276 * This function sets the PLL0 monitor mode. The mode can be disabled,
1277 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1278 *
1279 * @param mode Monitor mode to set.
1280 */
1281 void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode);
1282
1283 /*!
1284 * @brief Sets the PLL1 monitor mode.
1285 *
1286 * This function sets the PLL1 monitor mode. The mode can be disabled,
1287 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1288 *
1289 * @param mode Monitor mode to set.
1290 */
1291 void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode);
1292
1293 /*!
1294 * @brief Config 32k Crystal Oscillator.
1295 *
1296 * @param base VBAT peripheral base address.
1297 * @param config The pointer to the structure \ref vbat_osc_config_t.
1298 */
1299 void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config);
1300
1301 /*!
1302 * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access
1303 * time during full speed power mode.
1304 * @param system_freq_hz : Input frequency
1305 * @param mode : Active run mode (voltage level).
1306 * @return success or fail status
1307 */
1308 status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode);
1309
1310 /**
1311 * @brief Configure the clock selection muxes.
1312 * @param connection : Clock to be configured.
1313 * @return Nothing
1314 */
1315 void CLOCK_AttachClk(clock_attach_id_t connection);
1316
1317 /**
1318 * @brief Get the actual clock attach id.
1319 * This fuction uses the offset in input attach id, then it reads the actual source value in
1320 * the register and combine the offset to obtain an actual attach id.
1321 * @param attachId : Clock attach id to get.
1322 * @return Clock source value.
1323 */
1324 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
1325
1326 /**
1327 * @brief Setup peripheral clock dividers.
1328 * @param div_name : Clock divider name
1329 * @param divided_by_value: Value to be divided
1330 * @return Nothing
1331 */
1332 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value);
1333
1334 /**
1335 * @brief Get peripheral clock dividers.
1336 * @param div_name : Clock divider name
1337 * @return peripheral clock dividers
1338 */
1339 uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name);
1340
1341 /**
1342 * @brief Halt peripheral clock dividers.
1343 * @param div_name : Clock divider name
1344 * @return Nothing
1345 */
1346 void CLOCK_HaltClkDiv(clock_div_name_t div_name);
1347
1348 /**
1349 * @brief system clocks enable controls.
1350 * @param mask : system clocks enable value, it should use clock_ctrl_enable_t value
1351 * @return Nothing
1352 */
1353 void CLOCK_SetupClockCtrl(uint32_t mask);
1354
1355 /*! @brief Return Frequency of selected clock
1356 * @return Frequency of selected clock
1357 */
1358 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1359
1360 /*! @brief Return Frequency of core
1361 * @return Frequency of the core
1362 */
1363 uint32_t CLOCK_GetCoreSysClkFreq(void);
1364
1365 /*! @brief Return Frequency of CTimer functional Clock
1366 * @return Frequency of CTimer functional Clock
1367 */
1368 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
1369
1370 /*! @brief Return Frequency of Adc Clock
1371 * @return Frequency of Adc.
1372 */
1373 uint32_t CLOCK_GetAdcClkFreq(uint32_t id);
1374
1375 /*! @brief Return Frequency of LPFlexComm Clock
1376 * @return Frequency of LPFlexComm Clock
1377 */
1378 uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id);
1379
1380 /*! @brief Return Frequency of PLL
1381 * @return Frequency of PLL
1382 */
1383 uint32_t CLOCK_GetPll0OutFreq(void);
1384 /*! @brief Return Frequency of USB PLL
1385 * @return Frequency of PLL
1386 */
1387 uint32_t CLOCK_GetPll1OutFreq(void);
1388
1389 /*! @brief Return Frequency of PLLCLKDIV
1390 * @return Frequency of PLLCLKDIV Clock
1391 */
1392 uint32_t CLOCK_GetPllClkDivFreq(void);
1393
1394 /*! @brief Return Frequency of I3C function Clock
1395 * @return Frequency of I3C function Clock
1396 */
1397 uint32_t CLOCK_GetI3cClkFreq(uint32_t id);
1398
1399 /*! @brief Return Frequency of MICFIL Clock
1400 * @return Frequency of MICFIL.
1401 */
1402 uint32_t CLOCK_GetMicfilClkFreq(void);
1403
1404 /*! @brief Return Frequency of FLEXIO
1405 * @return Frequency of FLEXIO Clock
1406 */
1407 uint32_t CLOCK_GetFlexioClkFreq(void);
1408
1409 /*! @brief Return Frequency of FLEXCAN
1410 * @return Frequency of FLEXCAN Clock
1411 */
1412 uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id);
1413
1414 /*! @brief Return Frequency of EWM0 Clock
1415 * @return Frequency of EWM0.
1416 */
1417 uint32_t CLOCK_GetEwm0ClkFreq(void);
1418
1419 /*! @brief Return Frequency of Watchdog
1420 * @return Frequency of Watchdog
1421 */
1422 uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
1423
1424 /*! @brief Return Frequency of OSTIMER
1425 * @return Frequency of OSTIMER Clock
1426 */
1427 uint32_t CLOCK_GetOstimerClkFreq(void);
1428
1429 /*! @brief Return Frequency of CMP Function Clock
1430 * @return Frequency of CMP Function.
1431 */
1432 uint32_t CLOCK_GetCmpFClkFreq(uint32_t id);
1433
1434 /*! @brief Return Frequency of CMP Round Robin Clock
1435 * @return Frequency of CMP Round Robin.
1436 */
1437 uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id);
1438
1439 /*! @brief Return Frequency of UTICK Clock
1440 * @return Frequency of UTICK Clock.
1441 */
1442 uint32_t CLOCK_GetUtickClkFreq(void);
1443
1444 /*! @brief Return Frequency of SAI Clock
1445 * @return Frequency of SAI Clock.
1446 */
1447 uint32_t CLOCK_GetSaiClkFreq(uint32_t id);
1448
1449 /**
1450 * @brief Initialize the SAI MCLK to given frequency.
1451 * @param iFreq : Desired frequency
1452 * @return Nothing
1453 */
1454 void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq);
1455
1456 /**
1457 * @brief Initialize the SAI TX BCLK to given frequency.
1458 * @param iFreq : Desired frequency
1459 * @return Nothing
1460 */
1461 void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq);
1462
1463 /**
1464 * @brief Initialize the SAI RX BCLK to given frequency.
1465 * @param iFreq : Desired frequency
1466 * @return Nothing
1467 */
1468 void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq);
1469
1470 /**
1471 * @brief Return Frequency of SAI MCLK
1472 * @return Frequency of SAI MCLK
1473 */
1474 uint32_t CLOCK_GetSaiMclkFreq(uint32_t id);
1475
1476 /**
1477 * @brief Return Frequency of SAI TX BCLK
1478 * @return Frequency of SAI TX BCLK
1479 */
1480 uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id);
1481
1482 /**
1483 * @brief Return Frequency of SAI RX BCLK
1484 * @return Frequency of SAI RX BCLK
1485 */
1486 uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id);
1487
1488 /*! @brief Return PLL0 input clock rate
1489 * @return PLL0 input clock rate
1490 */
1491 uint32_t CLOCK_GetPLL0InClockRate(void);
1492
1493 /*! @brief Return PLL1 input clock rate
1494 * @return PLL1 input clock rate
1495 */
1496 uint32_t CLOCK_GetPLL1InClockRate(void);
1497
1498 /*! @brief Gets the external UPLL frequency.
1499 * @return The frequency of the external UPLL.
1500 */
1501 uint32_t CLOCK_GetExtUpllFreq(void);
1502
1503 /*! @brief Sets the external UPLL frequency.
1504 * @param The frequency of external UPLL.
1505 */
1506 void CLOCK_SetExtUpllFreq(uint32_t freq);
1507
1508 /*! @brief Check if PLL is locked or not
1509 * @return true if the PLL is locked, false if not locked
1510 */
CLOCK_IsPLL0Locked(void)1511 __STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
1512 {
1513 return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL);
1514 }
1515
1516 /*! @brief Check if PLL1 is locked or not
1517 * @return true if the PLL1 is locked, false if not locked
1518 */
CLOCK_IsPLL1Locked(void)1519 __STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
1520 {
1521 return (bool)((SCG0->SPLLCSR & SCG_SPLLCSR_SPLL_LOCK_MASK) != 0UL);
1522 }
1523
1524 /*! @brief PLL configuration structure flags for 'flags' field
1525 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1526 *
1527 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1528 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1529 * are not used.<br>
1530 */
1531 #define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1532 /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1533
1534 /*!
1535 * @brief PLL clock source.
1536 */
1537 typedef enum _pll_clk_src
1538 {
1539 kPll_ClkSrcSysOsc = (0 << 25), /*!< System OSC. */
1540 kPll_ClkSrcFirc = (1 << 25), /*!< Fast IRC. */
1541 kPll_ClkSrcRosc = (2 << 25), /*!< RTC OSC. */
1542 } pll_clk_src_t;
1543
1544 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1545 * See (MF) field in the PLL0SSCG1 register in the UM.
1546 */
1547 typedef enum _ss_progmodfm
1548 {
1549 kSS_MF_512 = (0 << 2), /*!< Nss = 512 (fm ~= 3.9 - 7.8 kHz) */
1550 kSS_MF_384 = (1 << 2), /*!< Nss ~= 384 (fm ~= 5.2 - 10.4 kHz) */
1551 kSS_MF_256 = (2 << 2), /*!< Nss = 256 (fm ~= 7.8 - 15.6 kHz) */
1552 kSS_MF_128 = (3 << 2), /*!< Nss = 128 (fm ~= 15.6 - 31.3 kHz) */
1553 kSS_MF_64 = (4 << 2), /*!< Nss = 64 (fm ~= 32.3 - 64.5 kHz) */
1554 kSS_MF_32 = (5 << 2), /*!< Nss = 32 (fm ~= 62.5 - 125 kHz) */
1555 kSS_MF_24 = (6 << 2), /*!< Nss ~= 24 (fm ~= 83.3 - 166.6 kHz) */
1556 kSS_MF_16 = (7 << 2) /*!< Nss = 16 (fm ~= 125 - 250 kHz) */
1557 } ss_progmodfm_t;
1558
1559 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1560 * See (MR) field in the PLL0SSCG1 register in the UM.
1561 */
1562 typedef enum _ss_progmoddp
1563 {
1564 kSS_MR_K0 = (0 << 5), /*!< k = 0 (no spread spectrum) */
1565 kSS_MR_K1 = (1 << 5), /*!< k ~= 1 */
1566 kSS_MR_K1_5 = (2 << 5), /*!< k ~= 1.5 */
1567 kSS_MR_K2 = (3 << 5), /*!< k ~= 2 */
1568 kSS_MR_K3 = (4 << 5), /*!< k ~= 3 */
1569 kSS_MR_K4 = (5 << 5), /*!< k ~= 4 */
1570 kSS_MR_K6 = (6 << 5), /*!< k ~= 6 */
1571 kSS_MR_K8 = (7 << 5) /*!< k ~= 8 */
1572 } ss_progmoddp_t;
1573
1574 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1575 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1576 * Compensation for low pass filtering of the PLL to get a triangular
1577 * modulation at the output of the PLL, giving a flat frequency spectrum.
1578 */
1579 typedef enum _ss_modwvctrl
1580 {
1581 kSS_MC_NOC = (0 << 8), /*!< no compensation */
1582 kSS_MC_RECC = (2 << 8), /*!< recommended setting */
1583 kSS_MC_MAXC = (3 << 8), /*!< max. compensation */
1584 } ss_modwvctrl_t;
1585
1586 /*! @brief PLL configuration structure
1587 *
1588 * This structure can be used to configure the settings for a PLL
1589 * setup structure. Fill in the desired configuration for the PLL
1590 * and call the PLL setup function to fill in a PLL setup structure.
1591 */
1592 typedef struct _pll_config
1593 {
1594 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1595 uint32_t inputSource; /*!< PLL input source */
1596 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1597 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1598 PLL_CONFIGFLAG_FORCENOFRACT flag */
1599 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1600 PLL_CONFIGFLAG_FORCENOFRACT flag */
1601 ss_modwvctrl_t
1602 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag
1603 */
1604 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1605 PLL_CONFIGFLAG_FORCENOFRACT flag */
1606
1607 } pll_config_t;
1608
1609 /*! @brief PLL0 setup structure
1610 * This structure can be used to pre-build a PLL setup configuration
1611 * at run-time and quickly set the PLL to the configuration. It can be
1612 * populated with the PLL setup function. If powering up or waiting
1613 * for PLL lock, the PLL input clock source should be configured prior
1614 * to PLL setup.
1615 */
1616 typedef struct _pll_setup
1617 {
1618 uint32_t pllctrl; /*!< PLL Control register APLLCTRL */
1619 uint32_t pllndiv; /*!< PLL N Divider register APLLNDIV */
1620 uint32_t pllpdiv; /*!< PLL P Divider register APLLPDIV */
1621 uint32_t pllmdiv; /*!< PLL M Divider register APLLMDIV */
1622 uint32_t pllsscg[2]; /*!< PLL Spread Spectrum Control registers APLLSSCG*/
1623 uint32_t pllRate; /*!< Acutal PLL rate */
1624 } pll_setup_t;
1625
1626 /*! @brief PLL status definitions
1627 */
1628 typedef enum _pll_error
1629 {
1630 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1631 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1632 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1633 kStatus_PLL_OutputError = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL output rate error */
1634 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too low */
1635 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< PLL input rate is too high */
1636 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested output rate isn't possible */
1637 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Requested CCO rate isn't possible */
1638 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 8) /*!< Requested CCO rate isn't possible */
1639 } pll_error_t;
1640
1641 /*! @brief Return PLL0 output clock rate from setup structure
1642 * @param pSetup : Pointer to a PLL setup structure
1643 * @return System PLL output clock rate the setup structure will generate
1644 */
1645 uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup);
1646
1647 /*! @brief Set PLL output based on the passed PLL setup data
1648 * @param pControl : Pointer to populated PLL control structure to generate setup with
1649 * @param pSetup : Pointer to PLL setup structure to be filled
1650 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1651 * @note Actual frequency for setup may vary from the desired frequency based on the
1652 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1653 */
1654 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1655
1656 /**
1657 * @brief Set PLL output from PLL setup structure (precise frequency)
1658 * @param pSetup : Pointer to populated PLL setup structure
1659 * @return kStatus_PLL_Success on success, or PLL setup error code
1660 * @note This function will power off the PLL, setup the PLL with the
1661 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1662 * and adjust system voltages to the new PLL rate. The function will not
1663 * alter any source clocks (ie, main systen clock) that may use the PLL,
1664 * so these should be setup prior to and after exiting the function.
1665 */
1666 pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1667
1668 /**
1669 * @brief Set PLL output from PLL setup structure (precise frequency)
1670 * @param pSetup : Pointer to populated PLL setup structure
1671 * @return kStatus_PLL_Success on success, or PLL setup error code
1672 * @note This function will power off the PLL, setup the PLL with the
1673 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1674 * and adjust system voltages to the new PLL rate. The function will not
1675 * alter any source clocks (ie, main systen clock) that may use the PLL,
1676 * so these should be setup prior to and after exiting the function.
1677 */
1678 pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1679
1680 /*! @brief Enable the OSTIMER 32k clock.
1681 * @return Nothing
1682 */
1683 void CLOCK_EnableOstimer32kClock(void);
1684
1685 /*! brief Enable USB HS PHY PLL clock.
1686 *
1687 * This function enables the internal 480MHz USB PHY PLL clock.
1688 *
1689 * param src USB HS PHY PLL clock source.
1690 * param freq The frequency specified by src.
1691 * retval true The clock is set successfully.
1692 * retval false The clock source is invalid to get proper USB HS clock.
1693 */
1694 bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1695
1696 /*! brief Disable USB HS PHY PLL clock.
1697 *
1698 * This function disables USB HS PHY PLL clock.
1699 */
1700 void CLOCK_DisableUsbhsPhyPllClock(void);
1701
1702 /*! brief Enable USB HS clock.
1703 * retval true The clock is set successfully.
1704 * retval false The clock source is invalid to get proper USB HS clock.
1705 */
1706 bool CLOCK_EnableUsbhsClock(void);
1707
1708 /**
1709 * @brief FIRC Auto Trim With SOF.
1710 * @return returns success or fail status.
1711 */
1712 status_t CLOCK_FIRCAutoTrimWithSOF(void);
1713
1714 #if defined(__cplusplus)
1715 }
1716 #endif /* __cplusplus */
1717
1718 /*! @} */
1719
1720 #endif /* _FSL_CLOCK_H_ */
1721
