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Searched refs:SCG_APLLCSR_APLLCMRE_MASK (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.h1028 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c489 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.h1028 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c489 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.h1282 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c505 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.h1282 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c505 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.h1282 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c505 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.h1282 …SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detect…
Dfsl_clock.c505 reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); in CLOCK_SetPll0MonitorMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h53136 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
53142 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h53094 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
53100 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h64695 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
64701 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
DMCXN546_cm33_core1.h64695 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
64701 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h64695 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
64701 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
DMCXN547_cm33_core1.h64695 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
64701 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h65442 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
65448 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
DMCXN947_cm33_core0.h65442 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
65448 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h65442 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
65448 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)
DMCXN946_cm33_core1.h65442 #define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) macro
65448 … (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK)