Home
last modified time | relevance | path

Searched refs:RW (Results 1 – 25 of 723) sorted by relevance

12345678910>>...29

/hal_nxp-latest/mcux/mcux-sdk/drivers/epdc/
Dfsl_epdc.c87 while ((base->CTRL.RW & EPDC_CTRL_CLKGATE_MASK) == 0U) in EPDC_ResetToInit()
93 while ((base->CTRL.RW & (EPDC_CTRL_CLKGATE_MASK | EPDC_CTRL_SFTRST_MASK)) != 0U) in EPDC_ResetToInit()
155 base->FORMAT.RW = EPDC_FORMAT_DEFAULT_TFT_PIXEL((uint32_t)config->defaltTftPixelValue) | in EPDC_InitDisplay()
158 …base->CTRL.RW = (base->CTRL.RW & ~(EPDC_CTRL_UPD_DATA_SWIZZLE_MASK | EPDC_CTRL_LUT_DATA_SWIZZLE_MA… in EPDC_InitDisplay()
184 base->FIFOCTRL.RW = pid._u32; in EPDC_ConfigFifo()
221 base->TCE_CTRL.RW = EPDC_TCE_CTRL_VSCAN_HOLDOFF((uint32_t)config->vscanHoldoff) | in EPDC_ConfigTCE()
227 base->TCE_SDCFG.RW = ((uint32_t)pid._u64 & ~EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK) | in EPDC_ConfigTCE()
229 base->TCE_GDCFG.RW = EPDC_TCE_GDCFG_GDSP_MODE((uint32_t)config->gdConfig.gdspMode) | in EPDC_ConfigTCE()
232 …base->TCE_HSCAN1.RW = ((uint32_t)config->scanConfig.lineSync << 16U) | (uint32_t)config->scanConfi… in EPDC_ConfigTCE()
233 …base->TCE_HSCAN2.RW = ((uint32_t)config->scanConfig.lineEnd << 16U) | (uint32_t)config->scanConfig… in EPDC_ConfigTCE()
[all …]
Dfsl_epdc.h532 return (uint8_t)(base->IRQ_MASK.RW >> 16U); in EPDC_GetEnabledInterrupts()
543 return (uint16_t)((base->IRQ.RW >> 12U) | (base->STATUS.RW & 0xFU)); in EPDC_GetStatusFlags()
597 return (((uint64_t)(base->IRQ_MASK2.RW) << 32U) | (uint64_t)base->IRQ_MASK1.RW); in EPDC_GetEnabledLutCompleteInterrupts()
609 return (uint64_t)base->IRQ1.RW | ((uint64_t)base->IRQ2.RW << 32U); in EPDC_GetLutCompleteStatusFlags()
773 …base->UPD_CTRL.RW = (base->UPD_CTRL.RW & ~EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) | EPDC_UPD_CTRL_WAVEFO… in EPDC_ConfigureWaveform()
/hal_nxp-latest/mcux/mcux-sdk/drivers/prg/
Dfsl_prg.c59 base->PRG_HEIGHT.RW = (uint32_t)config->height - 1U; in PRG_SetBufferConfig()
60 base->PRG_WIDTH.RW = (uint32_t)config->width - 1U; in PRG_SetBufferConfig()
61 base->PRG_STRIDE.RW = (uint32_t)config->strideBytes - 1U; in PRG_SetBufferConfig()
62 base->PRG_OFFSET.RW = 0U; in PRG_SetBufferConfig()
63 base->PRG_CTRL.RW = (base->PRG_CTRL.RW & ~PRG_PRG_CTRL_DES_DATA_TYPE_MASK) | in PRG_SetBufferConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dpr/
Dfsl_dpr.c83 base->MODE_CTRL0.RW = modeCtrl | DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK; in DPR_SetBufferConfig()
86 base->FRAME_CTRL0.RW = in DPR_SetBufferConfig()
87 … (base->FRAME_CTRL0.RW & ~DPR_FRAME_CTRL0_PITCH_MASK) | DPR_FRAME_CTRL0_PITCH(config->strideBytes); in DPR_SetBufferConfig()
90 base->FRAME_1P_PIX_X_CTRL.RW = DPR_ALIGN_UP(config->width, numPixelIn64Byte); in DPR_SetBufferConfig()
95 base->FRAME_1P_PIX_Y_CTRL.RW = DPR_ALIGN_UP(config->height, 4U); in DPR_SetBufferConfig()
97 base->RTRAM_CTRL0.RW = DPR_RTRAM_CTRL0_THRES_LOW(3) | DPR_RTRAM_CTRL0_THRES_HIGH(7); in DPR_SetBufferConfig()
Dfsl_dpr.h99 …base->SYSTEM_CTRL0.RW = DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK | DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN… in DPR_Start()
101 base->SYSTEM_CTRL0.RW = in DPR_Start()
115 base->SYSTEM_CTRL0.RW = in DPR_StartRepeat()
126 …base->SYSTEM_CTRL0.RW = DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK | DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN… in DPR_Stop()
137 base->FRAME_1P_BASE_ADDR_CTRL0.RW = addr; in DPR_SetBufferAddr()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/drivers/
Dfsl_clock.h75 …pll->DIV.RW = PLL_DIV_RDIV(pll_cfg->rdiv) | PLL_DIV_MFI(pll_cfg->mfi) | PLL_DIV_ODIV(pll_cfg->odiv… in CLOCK_PllInit()
79 pll->NUMERATOR.RW = PLL_NUMERATOR_MFN(pll_cfg->mfn); in CLOCK_PllInit()
80 pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(pll_cfg->mfd); in CLOCK_PllInit()
109 pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); in CLOCK_PllPfdInit()
1122 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = in CLOCK_SetRootClockMux()
1123 …(CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~(CCM_CLOCK_ROOT_MUX_MASK)) | CCM_CLOCK_ROOT_M… in CLOCK_SetRootClockMux()
1136 …return (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_MUX_MASK) >> CCM_CLOCK_R… in CLOCK_GetRootClockMux()
1160 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = in CLOCK_SetRootClockDiv()
1161 (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~CCM_CLOCK_ROOT_DIV_MASK) | in CLOCK_SetRootClockDiv()
1175 …return ((CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_DIV_MASK) >> CCM_CLOCK_… in CLOCK_GetRootClockDiv()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h75 …pll->DIV.RW = PLL_DIV_RDIV(pll_cfg->rdiv) | PLL_DIV_MFI(pll_cfg->mfi) | PLL_DIV_ODIV(pll_cfg->odiv… in CLOCK_PllInit()
79 pll->NUMERATOR.RW = PLL_NUMERATOR_MFN(pll_cfg->mfn); in CLOCK_PllInit()
80 pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(pll_cfg->mfd); in CLOCK_PllInit()
109 pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); in CLOCK_PllPfdInit()
1122 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = in CLOCK_SetRootClockMux()
1123 …(CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~(CCM_CLOCK_ROOT_MUX_MASK)) | CCM_CLOCK_ROOT_M… in CLOCK_SetRootClockMux()
1136 …return (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_MUX_MASK) >> CCM_CLOCK_R… in CLOCK_GetRootClockMux()
1160 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = in CLOCK_SetRootClockDiv()
1161 (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~CCM_CLOCK_ROOT_DIV_MASK) | in CLOCK_SetRootClockDiv()
1175 …return ((CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_DIV_MASK) >> CCM_CLOCK_… in CLOCK_GetRootClockDiv()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c693 base->SPREAD_SPECTRUM.RW = in ANATOP_PllConfigure()
696 base->NUMERATOR.RW = numer; in ANATOP_PllConfigure()
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1091 OSC_RC_400M->CTRL0.RW = in CLOCK_OSC_SetOscRc400MRefClkDiv()
1092 …(OSC_RC_400M->CTRL0.RW & ~OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) | OSC_RC_400M_CTRL0_REF_CLK_DIV(divV… in CLOCK_OSC_SetOscRc400MRefClkDiv()
1103 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MFastClkCount()
1104 …(OSC_RC_400M->CTRL1.RW & ~OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) | OSC_RC_400M_CTRL1_TARGET_COUNT(ta… in CLOCK_OSC_SetOscRc400MFastClkCount()
1119 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MHysteresisValue()
1120 …(OSC_RC_400M->CTRL1.RW & ~(OSC_RC_400M_CTRL1_HYST_PLUS_MASK | OSC_RC_400M_CTRL1_HYST_MINUS_MASK)) | in CLOCK_OSC_SetOscRc400MHysteresisValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c693 base->SPREAD_SPECTRUM.RW = in ANATOP_PllConfigure()
696 base->NUMERATOR.RW = numer; in ANATOP_PllConfigure()
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1091 OSC_RC_400M->CTRL0.RW = in CLOCK_OSC_SetOscRc400MRefClkDiv()
1092 …(OSC_RC_400M->CTRL0.RW & ~OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) | OSC_RC_400M_CTRL0_REF_CLK_DIV(divV… in CLOCK_OSC_SetOscRc400MRefClkDiv()
1103 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MFastClkCount()
1104 …(OSC_RC_400M->CTRL1.RW & ~OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) | OSC_RC_400M_CTRL1_TARGET_COUNT(ta… in CLOCK_OSC_SetOscRc400MFastClkCount()
1119 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MHysteresisValue()
1120 …(OSC_RC_400M->CTRL1.RW & ~(OSC_RC_400M_CTRL1_HYST_PLUS_MASK | OSC_RC_400M_CTRL1_HYST_MINUS_MASK)) | in CLOCK_OSC_SetOscRc400MHysteresisValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c693 base->SPREAD_SPECTRUM.RW = in ANATOP_PllConfigure()
696 base->NUMERATOR.RW = numer; in ANATOP_PllConfigure()
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1091 OSC_RC_400M->CTRL0.RW = in CLOCK_OSC_SetOscRc400MRefClkDiv()
1092 …(OSC_RC_400M->CTRL0.RW & ~OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) | OSC_RC_400M_CTRL0_REF_CLK_DIV(divV… in CLOCK_OSC_SetOscRc400MRefClkDiv()
1103 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MFastClkCount()
1104 …(OSC_RC_400M->CTRL1.RW & ~OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) | OSC_RC_400M_CTRL1_TARGET_COUNT(ta… in CLOCK_OSC_SetOscRc400MFastClkCount()
1119 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MHysteresisValue()
1120 …(OSC_RC_400M->CTRL1.RW & ~(OSC_RC_400M_CTRL1_HYST_PLUS_MASK | OSC_RC_400M_CTRL1_HYST_MINUS_MASK)) | in CLOCK_OSC_SetOscRc400MHysteresisValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
321 regValue = VMBANDGAP->STAT0.RW; in PMU_DisableBandgapSelfBiasAfterPowerUp()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c693 base->SPREAD_SPECTRUM.RW = in ANATOP_PllConfigure()
696 base->NUMERATOR.RW = numer; in ANATOP_PllConfigure()
697 base->DENOMINATOR.RW = denom; in ANATOP_PllConfigure()
1091 OSC_RC_400M->CTRL0.RW = in CLOCK_OSC_SetOscRc400MRefClkDiv()
1092 …(OSC_RC_400M->CTRL0.RW & ~OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) | OSC_RC_400M_CTRL0_REF_CLK_DIV(divV… in CLOCK_OSC_SetOscRc400MRefClkDiv()
1103 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MFastClkCount()
1104 …(OSC_RC_400M->CTRL1.RW & ~OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) | OSC_RC_400M_CTRL1_TARGET_COUNT(ta… in CLOCK_OSC_SetOscRc400MFastClkCount()
1119 OSC_RC_400M->CTRL1.RW = in CLOCK_OSC_SetOscRc400MHysteresisValue()
1120 …(OSC_RC_400M->CTRL1.RW & ~(OSC_RC_400M_CTRL1_HYST_PLUS_MASK | OSC_RC_400M_CTRL1_HYST_MINUS_MASK)) | in CLOCK_OSC_SetOscRc400MHysteresisValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_hifi4.h66 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
69 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
70 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
71 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT798S_cm33_core1.h70 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
73 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
74 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
75 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT798S_hifi1.h66 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
69 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
70 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
71 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT798S_cm33_core0.h71 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
74 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
75 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
76 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_cm33_core1.h70 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
73 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
74 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
75 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT735S_hifi1.h66 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
69 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
70 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
71 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT735S_cm33_core0.h71 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
74 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
75 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
76 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_hifi1.h66 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
69 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
70 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
71 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT758S_cm33_core1.h70 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
73 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
74 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
75 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))
Dsystem_MIMXRT758S_cm33_core0.h71 #define FRO_TUNER_USED(base) ((base->TEXPCNT.RW & FRO_TEXPCNT_TEXPCNT_MASK) != 0u)
74 ((uint32_t)((uint64_t)(base->TRIMCNT.RW) * \
75 (uint64_t)(CLK_OSC_CLK / ((base->CNFG1.RW & FRO_CNFG1_REFDIV_MASK) + 1U)) / \
76 ((base->CNFG1.RW & FRO_CNFG1_RFCLKCNT_MASK) >> FRO_CNFG1_RFCLKCNT_SHIFT)))

12345678910>>...29