87     while ((base->CTRL.RW & EPDC_CTRL_CLKGATE_MASK) == 0U)  in EPDC_ResetToInit()
93     while ((base->CTRL.RW & (EPDC_CTRL_CLKGATE_MASK | EPDC_CTRL_SFTRST_MASK)) != 0U)  in EPDC_ResetToInit()
155     base->FORMAT.RW = EPDC_FORMAT_DEFAULT_TFT_PIXEL((uint32_t)config->defaltTftPixelValue) |  in EPDC_InitDisplay()
158 …base->CTRL.RW = (base->CTRL.RW & ~(EPDC_CTRL_UPD_DATA_SWIZZLE_MASK | EPDC_CTRL_LUT_DATA_SWIZZLE_MA…  in EPDC_InitDisplay()
184     base->FIFOCTRL.RW = pid._u32;  in EPDC_ConfigFifo()
221     base->TCE_CTRL.RW = EPDC_TCE_CTRL_VSCAN_HOLDOFF((uint32_t)config->vscanHoldoff) |  in EPDC_ConfigTCE()
227     base->TCE_SDCFG.RW = ((uint32_t)pid._u64 & ~EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK) |  in EPDC_ConfigTCE()
229     base->TCE_GDCFG.RW = EPDC_TCE_GDCFG_GDSP_MODE((uint32_t)config->gdConfig.gdspMode) |  in EPDC_ConfigTCE()
232 …base->TCE_HSCAN1.RW = ((uint32_t)config->scanConfig.lineSync << 16U) | (uint32_t)config->scanConfi…  in EPDC_ConfigTCE()
233 …base->TCE_HSCAN2.RW = ((uint32_t)config->scanConfig.lineEnd << 16U) | (uint32_t)config->scanConfig…  in EPDC_ConfigTCE()
234     base->TCE_VSCAN.RW  = ((uint32_t)config->scanConfig.frameEnd << 16U) |  in EPDC_ConfigTCE()
236     base->TCE_OE.RW       = (uint32_t)(pid._u64 >> 32U);  in EPDC_ConfigTCE()
237     base->TCE_POLARITY.RW = ((uint32_t)pid._u64 & 0x7UL) |  in EPDC_ConfigTCE()
240     base->TCE_TIMING1.RW = ((uint32_t)pid._u64 >> 3U) & 0x3FUL;  in EPDC_ConfigTCE()
241 …base->TCE_TIMING2.RW = ((uint32_t)config->gdConfig.gdClkHigh << 16U) | (uint32_t)config->gdConfig.…  in EPDC_ConfigTCE()
242 …base->TCE_TIMING3.RW = ((uint32_t)config->gdConfig.gdoeOffset << 16U) | (uint32_t)config->gdConfig…  in EPDC_ConfigTCE()
245     if ((base->TCE_CTRL.RW & EPDC_TCE_CTRL_DDR_MODE_MASK) != 0U)  in EPDC_ConfigTCE()
249     if ((base->TCE_CTRL.RW & EPDC_TCE_CTRL_SDDO_WIDTH_MASK) != 0U)  in EPDC_ConfigTCE()
253     if ((base->TCE_CTRL.RW & EPDC_TCE_CTRL_LVDS_MODE_MASK) != 0U)  in EPDC_ConfigTCE()
257     if ((base->TCE_CTRL.RW & EPDC_TCE_CTRL_DUAL_SCAN_MASK) != 0U)  in EPDC_ConfigTCE()
261 …if (((base->FORMAT.RW & EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK) >> EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT) …  in EPDC_ConfigTCE()
273     base->TCE_CTRL.RW =  in EPDC_ConfigTCE()
274 …(base->TCE_CTRL.RW & ~EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK) | EPDC_TCE_CTRL_PIXELS_PER_SDCLK(piexel…  in EPDC_ConfigTCE()
322     base->PIGEON_CTRL0.RW = (uint32_t)pid._u64;  in EPDC_ConfigPigeonCycle()
323     base->PIGEON_CTRL1.RW = (uint32_t)(pid._u64 >> 32U);  in EPDC_ConfigPigeonCycle()
363 …(((base->FORMAT.RW & EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK) >> (EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT + 1…  in EPDC_UpdateDisplay()
383     base->UPD_FIXED.RW = *(uint32_t *)dataAddr;  in EPDC_UpdateDisplay()
387     if ((base->STATUS.RW & (EPDC_STATUS_WB_BUSY_MASK | EPDC_STATUS_LUTS_BUSY_MASK)) != 0U)  in EPDC_UpdateDisplay()
391     base->UPD_CTRL.RW = *(uint32_t *)dataAddr;  in EPDC_UpdateDisplay()
427     base->GPIO.RW = pid._u32;  in EPDC_SetGpioOutput()
446     status->lutlist = (uint64_t)(base->STATUS_COL1.RW) | ((uint64_t)(base->STATUS_COL2.RW) << 32U);  in EPDC_GetCollisionStatus()