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Searched refs:RCCR (Results 1 – 25 of 129) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/esai/
Dfsl_esai.c185 base->RCCR &= ~ESAI_RCCR_RDC_MASK; in ESAI_SetCustomerProtocol()
186 base->RCCR |= ESAI_RCCR_RDC(protocol->slotNum - 1UL); in ESAI_SetCustomerProtocol()
386 base->RCCR |= (ESAI_RCCR_RFSD_MASK | ESAI_RCCR_RCKD_MASK); in ESAI_Init()
394 base->RCCR &= ~(ESAI_RCCR_RFSD_MASK | ESAI_RCCR_RCKD_MASK); in ESAI_Init()
402 base->RCCR |= ESAI_RCCR_RHCKD(config->rxHckDirection); in ESAI_Init()
428 base->RCCR &= ~(ESAI_RCCR_RHCKP_MASK | ESAI_RCCR_RFSP_MASK | ESAI_RCCR_RCKP_MASK); in ESAI_Init()
429 base->RCCR |= (ESAI_RCCR_RHCKP(config->rxHckPolarity) | ESAI_RCCR_RFSP(config->rxFsPolarity) | in ESAI_Init()
685 uint8_t slotNum = (uint8_t)((base->RCCR & ESAI_RCCR_RDC_MASK) >> ESAI_RCCR_RDC_SHIFT) + 1U; in ESAI_RxSetFormat()
706 base->RCCR &= ~(ESAI_RCCR_RFSP_MASK | ESAI_RCCR_RPM_MASK); in ESAI_RxSetFormat()
707 base->RCCR |= ESAI_RCCR_RFP(hckClockHz / sck - 1U); in ESAI_RxSetFormat()
[all …]
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Divider.c497 RegValue = IP_SCG->RCCR; in Clock_Ip_SetScgRunDivcore_TrustedCall()
500 IP_SCG->RCCR = RegValue; in Clock_Ip_SetScgRunDivcore_TrustedCall()
510 RegValue = IP_SCG->RCCR; in Clock_Ip_SetScgRunDivbus_TrustedCall()
513 IP_SCG->RCCR = RegValue; in Clock_Ip_SetScgRunDivbus_TrustedCall()
523 RegValue = IP_SCG->RCCR; in Clock_Ip_SetScgRunDivslow_TrustedCall()
526 IP_SCG->RCCR = RegValue; in Clock_Ip_SetScgRunDivslow_TrustedCall()
DClock_Ip_Selector.c512 RegValue = IP_SCG->RCCR; in Clock_Ip_ResetScgRunSel_TrustedCall()
515 IP_SCG->RCCR = RegValue; in Clock_Ip_ResetScgRunSel_TrustedCall()
523 RegValue = IP_SCG->RCCR; in Clock_Ip_SetScgRunSel_TrustedCall()
526 IP_SCG->RCCR = RegValue; in Clock_Ip_SetScgRunSel_TrustedCall()
DClock_Ip_Specific.c722 …SelectorConfigurations[SelectorConfigIndex].Value = ClockSource[(IP_SCG->RCCR & SCG_RCCR_SCS_MASK)… in getSelectorConfig()
786 …CoreDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->RCCR & SCG_RCCR_DIVCORE_MASK) >> S… in getCoreDividerConfig()
852 …BusDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->RCCR & SCG_RCCR_DIVBUS_MASK) >> SCG… in getBusDividerConfig()
917 …SlowDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->RCCR & SCG_RCCR_DIVSLOW_MASK) >> S… in getSlowDividerConfig()
DClock_Ip_IntOsc.c387 RegValue = IP_SCG->RCCR; in SetInputSouceSytemClock()
390 IP_SCG->RCCR = RegValue; in SetInputSouceSytemClock()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c211 scg->RCCR = scgRunConfig; in AT_QUICKACCESS_SECTION_CODE()
234 scg->RCCR = scgRunConfig; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/drivers/
Dfsl_clock.c112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); in CLOCK_SetClockSelect()
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockSelect()
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_CMU_FM.h74 …__IO uint32_t RCCR; /**< Reference Count Configuration Register, offs… member
DS32K344_CMU_FC.h74 …__IO uint32_t RCCR; /**< Reference Count Configuration Register, offs… member
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K118_CMU.h74 …__IO uint32_t RCCR; /**< Reference Count Configuration Register, offs… member
DS32K116_CMU.h74 …__IO uint32_t RCCR; /**< Reference Count Configuration Register, offs… member
/hal_nxp-latest/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h250 …uint32 RCCR; /**< Reference Count Configuration Register, offset: 0x4… member
/hal_nxp-latest/s32/drivers/s32k1/Mcu/include/
DClock_Ip_Specific.h391 …uint32 RCCR; /**< Reference Count Configuration Register, offset: 0x4… member
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CMU_FC.h74 …__IO uint32_t RCCR; /**< Reference Count Configuration Register, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c675 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); in CLOCK_AttachClk()
722 actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c675 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); in CLOCK_AttachClk()
722 actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockAttachId()

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