1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_CMU_FM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_CMU_FM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_CMU_FM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_CMU_FM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CMU_FM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CMU_FM_Peripheral_Access_Layer CMU_FM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CMU_FM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ 74 __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 75 __IO uint32_t SR; /**< Status Register, offset: 0x8 */ 76 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0xC */ 77 } CMU_FM_Type, *CMU_FM_MemMapPtr; 78 79 /** Number of instances of the CMU_FM module. */ 80 #define CMU_FM_INSTANCE_COUNT (2u) 81 82 /* CMU_FM - Peripheral instance base addresses */ 83 /** Peripheral CMU_1 base address */ 84 #define IP_CMU_1_BASE (0x402BC020u) 85 /** Peripheral CMU_1 base pointer */ 86 #define IP_CMU_1 ((CMU_FM_Type *)IP_CMU_1_BASE) 87 /** Peripheral CMU_2 base address */ 88 #define IP_CMU_2_BASE (0x402BC040u) 89 /** Peripheral CMU_2 base pointer */ 90 #define IP_CMU_2 ((CMU_FM_Type *)IP_CMU_2_BASE) 91 /** Array initializer of CMU_FM peripheral base addresses */ 92 #define IP_CMU_FM_BASE_ADDRS { IP_CMU_1_BASE, IP_CMU_2_BASE } 93 /** Array initializer of CMU_FM peripheral base pointers */ 94 #define IP_CMU_FM_BASE_PTRS { IP_CMU_1, IP_CMU_2 } 95 96 /* ---------------------------------------------------------------------------- 97 -- CMU_FM Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup CMU_FM_Register_Masks CMU_FM Register Masks 102 * @{ 103 */ 104 105 /*! @name GCR - Global Configuration Register */ 106 /*! @{ */ 107 108 #define CMU_FM_GCR_FME_MASK (0x1U) 109 #define CMU_FM_GCR_FME_SHIFT (0U) 110 #define CMU_FM_GCR_FME_WIDTH (1U) 111 #define CMU_FM_GCR_FME(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_GCR_FME_SHIFT)) & CMU_FM_GCR_FME_MASK) 112 /*! @} */ 113 114 /*! @name RCCR - Reference Count Configuration Register */ 115 /*! @{ */ 116 117 #define CMU_FM_RCCR_REF_CNT_MASK (0xFFFFU) 118 #define CMU_FM_RCCR_REF_CNT_SHIFT (0U) 119 #define CMU_FM_RCCR_REF_CNT_WIDTH (16U) 120 #define CMU_FM_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_RCCR_REF_CNT_SHIFT)) & CMU_FM_RCCR_REF_CNT_MASK) 121 /*! @} */ 122 123 /*! @name SR - Status Register */ 124 /*! @{ */ 125 126 #define CMU_FM_SR_FMC_MASK (0x1U) 127 #define CMU_FM_SR_FMC_SHIFT (0U) 128 #define CMU_FM_SR_FMC_WIDTH (1U) 129 #define CMU_FM_SR_FMC(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_SR_FMC_SHIFT)) & CMU_FM_SR_FMC_MASK) 130 131 #define CMU_FM_SR_FMTO_MASK (0x2U) 132 #define CMU_FM_SR_FMTO_SHIFT (1U) 133 #define CMU_FM_SR_FMTO_WIDTH (1U) 134 #define CMU_FM_SR_FMTO(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_SR_FMTO_SHIFT)) & CMU_FM_SR_FMTO_MASK) 135 136 #define CMU_FM_SR_RS_MASK (0x10U) 137 #define CMU_FM_SR_RS_SHIFT (4U) 138 #define CMU_FM_SR_RS_WIDTH (1U) 139 #define CMU_FM_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_SR_RS_SHIFT)) & CMU_FM_SR_RS_MASK) 140 141 #define CMU_FM_SR_MET_CNT_MASK (0xFFFFFF00U) 142 #define CMU_FM_SR_MET_CNT_SHIFT (8U) 143 #define CMU_FM_SR_MET_CNT_WIDTH (24U) 144 #define CMU_FM_SR_MET_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_SR_MET_CNT_SHIFT)) & CMU_FM_SR_MET_CNT_MASK) 145 /*! @} */ 146 147 /*! @name IER - Interrupt Enable Register */ 148 /*! @{ */ 149 150 #define CMU_FM_IER_FMCIE_MASK (0x1U) 151 #define CMU_FM_IER_FMCIE_SHIFT (0U) 152 #define CMU_FM_IER_FMCIE_WIDTH (1U) 153 #define CMU_FM_IER_FMCIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FM_IER_FMCIE_SHIFT)) & CMU_FM_IER_FMCIE_MASK) 154 /*! @} */ 155 156 /*! 157 * @} 158 */ /* end of group CMU_FM_Register_Masks */ 159 160 /*! 161 * @} 162 */ /* end of group CMU_FM_Peripheral_Access_Layer */ 163 164 #endif /* #if !defined(S32K344_CMU_FM_H_) */ 165
