| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | system_K32L3A60_cm0plus.c | 87 if (LPTMR0->PSR != 0U) in SystemInit()
89 LPTMR0->PSR = 0; in SystemInit()
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| D | system_K32L3A60_cm4.c | 90 if (LPTMR0->PSR != 0U) in SystemInit()
92 LPTMR0->PSR = 0; in SystemInit()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/puf_v3/ |
| D | fsl_puf_v3.c | 278 *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); in PUF_Enroll()
364 *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); in PUF_Start()
953 *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); in PUF_Test()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lptmr/ |
| D | fsl_lptmr.c | 103 base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | in LPTMR_Init()
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K116_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K118_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K144_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K142W_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K146_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K148_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K142_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| D | S32K144W_LPTMR.h | 74 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/src/ |
| D | Adc_Sar_Ip.c | 1115 PSR(AdcAEBasePtr, Index) = PsrMask[Index]; in Adc_Sar_ConfigChannels()
1126 PSR(AdcBasePtr, Index) = PsrMask[Index]; in Adc_Sar_ConfigChannels()
2490 PSR(AdcAEBasePtr, Index) = 0u; in Adc_Sar_Ip_Deinit()
2508 PSR(AdcBasePtr, Index) = 0u; in Adc_Sar_Ip_Deinit()
4449 PSR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit; in Adc_Sar_Ip_EnableChannelPresampling()
4457 PSR(AdcBasePtr, VectAdr) |= 1UL << VectBit; in Adc_Sar_Ip_EnableChannelPresampling()
4501 PSR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit); in Adc_Sar_Ip_DisableChannelPresampling()
4509 PSR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit); in Adc_Sar_Ip_DisableChannelPresampling()
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/src/ |
| D | Adc_Sar_Ip.c | 1077 PSR(AdcAEBasePtr, Index) = PsrMask[Index]; in Adc_Sar_ConfigChannels()
1088 PSR(AdcBasePtr, Index) = PsrMask[Index]; in Adc_Sar_ConfigChannels()
2298 PSR(AdcAEBasePtr, Index) = 0u; in Adc_Sar_Ip_Deinit()
2316 PSR(AdcBasePtr, Index) = 0u; in Adc_Sar_Ip_Deinit()
4239 PSR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit; in Adc_Sar_Ip_EnableChannelPresampling()
4247 PSR(AdcBasePtr, VectAdr) |= 1UL << VectBit; in Adc_Sar_Ip_EnableChannelPresampling()
4291 PSR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit); in Adc_Sar_Ip_DisableChannelPresampling()
4299 PSR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit); in Adc_Sar_Ip_DisableChannelPresampling()
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32XX.h | 142 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex)) macro
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| D | Adc_Sar_Ip_HeaderWrapper_S32XX_AE.h | 137 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex)) macro
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/igpio/ |
| D | fsl_gpio.h | 209 return (uint8_t)(((base->PSR) >> pin) & 0x1U); in GPIO_PinReadPadStatus()
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32K3.h | 172 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex)) macro
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_ENETC_PORT.h | 94 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ member
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| D | S32Z2_SW_PORT2.h | 96 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ member
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| D | S32Z2_SW_PORT0.h | 96 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ member
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| D | S32Z2_SW_PORT1.h | 96 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/netc/netc_hw/ |
| D | fsl_netc_hw_port.c | 640 while (0U != (base->PSR & NETC_PORT_PSR_RX_BUSY_MASK)) in NETC_PortEthMacGracefulStop()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/ |
| D | MCXC041.h | 2248 …__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0… member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/netc/ |
| D | fsl_netc_switch.c | 525 while (0U != (base->PSR & NETC_PORT_PSR_RX_BUSY_MASK)) in SWT_PortStop()
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