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Searched refs:POLSEL (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_cm33.c115 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL->POLSEL == 0U)) /* Enable cache to accelerate boot.… in SystemInit()
130 CACHE64_POLSEL->POLSEL = 0x1U; in SystemInit()
DMIMXRT685S_dsp.h1131 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
DMIMXRT685S_cm33.h6473 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
Dsystem_MIMXRT633S.c114 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL->POLSEL == 0U)) /* Enable cache to accelerate boot.… in SystemInit()
129 CACHE64_POLSEL->POLSEL = 0x1U; in SystemInit()
DMIMXRT633S.h6473 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_cm33.c126 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured … in SystemInit()
141 CACHE64_POLSEL0->POLSEL = 0x1U; in SystemInit()
DMIMXRT595S_dsp.h1500 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
DMIMXRT595S_cm33.h7690 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.c125 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured … in SystemInit()
140 CACHE64_POLSEL0->POLSEL = 0x1U; in SystemInit()
DMIMXRT555S.h7689 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.c125 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured … in SystemInit()
140 CACHE64_POLSEL0->POLSEL = 0x1U; in SystemInit()
DMIMXRT533S.h7686 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
Dsystem_RW610.c84 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* Enable cache to accelerate boot… in SystemInit()
99 CACHE64_POLSEL0->POLSEL = 0x1U; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
Dsystem_RW612.c84 …if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* Enable cache to accelerate boot… in SystemInit()
99 CACHE64_POLSEL0->POLSEL = 0x1U; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_cm33_core0.c103 CACHE64_POLSEL0->POLSEL = STARTUP_XSPI0_CACHE_POLICY; in SystemInit()
122 CACHE64_POLSEL1->POLSEL = STARTUP_XSPI1_CACHE_POLICY; in SystemInit()
DMIMXRT735S_ezhv.h16433 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_cm33_core0.c103 CACHE64_POLSEL0->POLSEL = STARTUP_XSPI0_CACHE_POLICY; in SystemInit()
122 CACHE64_POLSEL1->POLSEL = STARTUP_XSPI1_CACHE_POLICY; in SystemInit()
DMIMXRT798S_hifi4.h16873 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_cm33_core0.c103 CACHE64_POLSEL0->POLSEL = STARTUP_XSPI0_CACHE_POLICY; in SystemInit()
122 CACHE64_POLSEL1->POLSEL = STARTUP_XSPI1_CACHE_POLICY; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c152 base->POLSEL = polsel; in CACHE64_Init()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2984 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2984 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2983 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8249 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8249 __IO uint32_t POLSEL; /**< Policy Select, offset: 0x1C */ member

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