Home
last modified time | relevance | path

Searched refs:NIC_USDHC1_BASE (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_nic301.h46 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_nic301.h46 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_nic301.h46 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_nic301.h46 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
86 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
86 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_nic301.h51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) macro
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_nic301.h54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) macro
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,