1 /*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_NIC301_H_
9 #define _FSL_NIC301_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup nic301
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.nic301"
25 #endif
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief NIC301 driver version 2.0.1. */
30 #define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
31 /*@}*/
32
33 #define GPV0_BASE (0x41000000UL)
34 #define GPV1_BASE (0x41100000UL)
35 #define GPV4_BASE (0x41400000UL)
36
37 #define NIC_FN_MOD_AHB_OFFSET (0x028UL)
38 #define NIC_WR_TIDEMARK_OFFSET (0x040UL)
39 #define NIC_READ_QOS_OFFSET (0x100UL)
40 #define NIC_WRITE_QOS_OFFSET (0x104UL)
41 #define NIC_FN_MOD_OFFSET (0x108UL)
42
43 #define NIC_GC355_BASE (GPV0_BASE + 0x42000)
44 #define NIC_PXP_BASE (GPV0_BASE + 0x43000)
45 #define NIC_LCDIF_BASE (GPV0_BASE + 0x44000)
46 #define NIC_LCDIFV2_BASE (GPV0_BASE + 0x45000)
47 #define NIC_CSI_BASE (GPV0_BASE + 0x46000)
48
49 #define NIC_CAAM_BASE (GPV1_BASE + 0x42000)
50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000)
51 #define NIC_ENET1G_TX_BASE (GPV1_BASE + 0x44000)
52 #define NIC_ENET_BASE (GPV1_BASE + 0x45000)
53 #define NIC_USBO2_BASE (GPV1_BASE + 0x46000)
54 #define NIC_USDHC1_BASE (GPV1_BASE + 0x47000)
55 #define NIC_USDHC2_BASE (GPV1_BASE + 0x48000)
56 #define NIC_ENET_QOS_BASE (GPV1_BASE + 0x4A000)
57
58 #define NIC_CM7_BASE (GPV4_BASE + 0x42000)
59 #define NIC_LPSRMIX_M_BASE (GPV4_BASE + 0x46000)
60 #define NIC_DMA_BASE (GPV4_BASE + 0x47000)
61 #define NIC_IEE_BASE (GPV4_BASE + 0x48000)
62
63 #define NIC_QOS_MASK (0xF)
64 #define NIC_WR_TIDEMARK_MASK (0xF)
65 #define NIC_FN_MOD_AHB_MASK (0x7)
66 #define NIC_FN_MOD_MASK (0x1)
67
68 typedef enum _nic_reg
69 {
70 /* read_qos */
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
80 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
81 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
82 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
83 kNIC_REG_READ_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_READ_QOS_OFFSET,
84 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
86 kNIC_REG_READ_QOS_IEE = NIC_IEE_BASE + NIC_READ_QOS_OFFSET,
87
88 /* write_qos */
89 kNIC_REG_WRITE_QOS_GC355 = NIC_GC355_BASE + NIC_WRITE_QOS_OFFSET,
90 kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET,
91 kNIC_REG_WRITE_QOS_LCDIF = NIC_LCDIF_BASE + NIC_WRITE_QOS_OFFSET,
92 kNIC_REG_WRITE_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_WRITE_QOS_OFFSET,
93 kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET,
94 kNIC_REG_WRITE_QOS_CAAM = NIC_CAAM_BASE + NIC_WRITE_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
96 kNIC_REG_WRITE_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_WRITE_QOS_OFFSET,
97 kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET,
98 kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
100 kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET,
101 kNIC_REG_WRITE_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_WRITE_QOS_OFFSET,
102 kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET,
103 kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET,
104 kNIC_REG_WRITE_QOS_IEE = NIC_IEE_BASE + NIC_WRITE_QOS_OFFSET,
105
106 /* fn_mod */
107 kNIC_REG_FN_MOD_GC355 = NIC_GC355_BASE + NIC_FN_MOD_OFFSET,
108 kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET,
109 kNIC_REG_FN_MOD_LCDIF = NIC_LCDIF_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_FN_MOD_OFFSET,
111 kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET,
112 kNIC_REG_FN_MOD_CAAM = NIC_CAAM_BASE + NIC_FN_MOD_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
114 kNIC_REG_FN_MOD_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_FN_MOD_OFFSET,
115 kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET,
116 kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET,
117 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
118 kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET,
119 kNIC_REG_FN_MOD_ENET_QOS = NIC_ENET_QOS_BASE + NIC_FN_MOD_OFFSET,
120 kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET,
121 kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET,
122 kNIC_REG_FN_MOD_IEE = NIC_IEE_BASE + NIC_FN_MOD_OFFSET,
123
124 /* fn_mod_ahb */
125 kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET,
126 kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET,
127
128 /* wr_tidemark */
129 kNIC_REG_WR_TIDEMARK_LPSRMIX_M = NIC_LPSRMIX_M_BASE + NIC_WR_TIDEMARK_OFFSET,
130 } nic_reg_t;
131
132 /* fn_mod_ahb */
133 typedef enum _nic_fn_mod_ahb
134 {
135 kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0,
136 kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE,
137 kNIC_FN_MOD_AHB_LOCK_OVERRIDE,
138 } nic_fn_mod_ahb_t;
139
140 /* fn_mod */
141 typedef enum _nic_fn_mod
142 {
143 kNIC_FN_MOD_ReadIssue = 0,
144 kNIC_FN_MOD_WriteIssue,
145 } nic_fn_mod_t;
146
147 /* read_qos/write_qos */
148 typedef enum _nic_qos
149 {
150 kNIC_QOS_0 = 0,
151 kNIC_QOS_1,
152 kNIC_QOS_2,
153 kNIC_QOS_3,
154 kNIC_QOS_4,
155 kNIC_QOS_5,
156 kNIC_QOS_6,
157 kNIC_QOS_7,
158 kNIC_QOS_8,
159 kNIC_QOS_9,
160 kNIC_QOS_10,
161 kNIC_QOS_11,
162 kNIC_QOS_12,
163 kNIC_QOS_13,
164 kNIC_QOS_14,
165 kNIC_QOS_15,
166 } nic_qos_t;
167
168 /*******************************************************************************
169 * API
170 ******************************************************************************/
171 #if defined(__cplusplus)
172 extern "C" {
173 #endif /* __cplusplus */
174
175 /*!
176 * @brief Set read_qos Value
177 *
178 * @param base Base address of GPV address
179 * @param value Target value (0 - 15)
180 */
NIC_SetReadQos(nic_reg_t base,nic_qos_t value)181 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
182 {
183 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
184 __DSB();
185 }
186
187 /*!
188 * @brief Get read_qos Value
189 *
190 * @param base Base address of GPV address
191 * @return Current value configured
192 */
NIC_GetReadQos(nic_reg_t base)193 static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
194 {
195 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
196 }
197
198 /*!
199 * @brief Set write_qos Value
200 *
201 * @param base Base address of GPV address
202 * @param value Target value (0 - 15)
203 */
NIC_SetWriteQos(nic_reg_t base,nic_qos_t value)204 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
205 {
206 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
207 __DSB();
208 }
209
210 /*!
211 * @brief Get write_qos Value
212 *
213 * @param base Base address of GPV address
214 * @return Current value configured
215 */
NIC_GetWriteQos(nic_reg_t base)216 static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
217 {
218 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
219 }
220
221 /*!
222 * @brief Set fn_mod_ahb Value
223 *
224 * @param base Base address of GPV address
225 * @param value Target value
226 */
NIC_SetFnModAhb(nic_reg_t base,nic_fn_mod_ahb_t value)227 static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t value)
228 {
229 *(volatile uint32_t *)(base) = value;
230 __DSB();
231 }
232
233 /*!
234 * @brief Get fn_mod_ahb Value
235 *
236 * @param base Base address of GPV address
237 * @return Current value configured
238 */
NIC_GetFnModAhb(nic_reg_t base)239 static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
240 {
241 return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
242 }
243
244 /*!
245 * @brief Set wr_tidemark Value
246 *
247 * @param base Base address of GPV address
248 * @param value Target value (0 - 15)
249 */
NIC_SetWrTideMark(nic_reg_t base,uint8_t value)250 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
251 {
252 *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
253 __DSB();
254 }
255
256 /*!
257 * @brief Get wr_tidemark Value
258 *
259 * @param base Base address of GPV address
260 * @return Current value configured
261 */
NIC_GetWrTideMark(nic_reg_t base)262 static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
263 {
264 return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
265 }
266
267 /*!
268 * @brief Set fn_mod Value
269 *
270 * @param base Base address of GPV address
271 * @param value Target value
272 */
NIC_SetFnMod(nic_reg_t base,nic_fn_mod_t value)273 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
274 {
275 *(volatile uint32_t *)(base) = value;
276 __DSB();
277 }
278
279 /*!
280 * @brief Get fn_mod Value
281 *
282 * @param base Base address of GPV address
283 * @return Current value configured
284 */
NIC_GetFnMod(nic_reg_t base)285 static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
286 {
287 return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
288 }
289
290 #if defined(__cplusplus)
291 }
292 #endif /* __cplusplus */
293 /*!
294 * @}
295 */
296 #endif /* _FSL_NIC301_H_ */
297
