1 /*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_NIC301_H_
9 #define _FSL_NIC301_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup nic301
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.nic301"
25 #endif
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief NIC301 driver version 2.0.1. */
30 #define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
31 /*@}*/
32
33 #define GPV0_BASE (0x41000000UL)
34 #define GPV1_BASE (0x41100000UL)
35 #define GPV4_BASE (0x41400000UL)
36
37 #define NIC_FN_MOD2_OFFSET (0x024UL)
38 #define NIC_FN_MOD_AHB_OFFSET (0x028UL)
39 #define NIC_WR_TIDEMARK_OFFSET (0x040UL)
40 #define NIC_READ_QOS_OFFSET (0x100UL)
41 #define NIC_WRITE_QOS_OFFSET (0x104UL)
42 #define NIC_FN_MOD_OFFSET (0x108UL)
43
44 #define NIC_LCD_BASE (GPV0_BASE + 0x44000)
45 #define NIC_CSI_BASE (GPV0_BASE + 0x45000)
46 #define NIC_PXP_BASE (GPV0_BASE + 0x46000)
47
48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000)
49 #define NIC_ENET_BASE (GPV1_BASE + 0x43000)
50 #define NIC_USBO2_BASE (GPV1_BASE + 0x44000)
51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000)
52 #define NIC_USDHC2_BASE (GPV1_BASE + 0x46000)
53 #define NIC_TestPort_BASE (GPV1_BASE + 0x47000)
54
55 #define NIC_CM7_BASE (GPV4_BASE + 0x42000)
56 #define NIC_DMA_BASE (GPV4_BASE + 0x43000)
57
58 #define NIC_QOS_MASK (0xF)
59 #define NIC_WR_TIDEMARK_MASK (0x7)
60 #define NIC_FN_MOD_AHB_MASK (0x7)
61 #define NIC_FN_MOD_MASK (0x1)
62 #define NIC_FN_MOD2_MASK (0x1)
63
64 typedef enum _nic_reg
65 {
66 /* read_qos */
67 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
78
79 /* write_qos */
80 kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET,
81 kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET,
83 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
84 kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET,
86 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
87 kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET,
89 kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET,
90 kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET,
91
92 /* fn_mod */
93 kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET,
94 kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET,
95 kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET,
96 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
97 kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET,
98 kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET,
99 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
100 kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET,
101 kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET,
102 kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET,
103 kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET,
104
105 /* fn_mod2 */
106 kNIC_REG_FN_MOD2_DCP = NIC_ENET_BASE + NIC_FN_MOD2_OFFSET,
107
108 /* fn_mod_ahb */
109 kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET,
110 kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET,
111 kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET,
112
113 /* wr_tidemark */
114 kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET,
115 } nic_reg_t;
116
117 /* fn_mod2 */
118 typedef enum _nic_fn_mod2
119 {
120 kNIC_FN_MOD2_ENABLE = 0,
121 kNIC_FN_MOD2_BYPASS,
122 } nic_fn_mod2_t;
123
124 /* fn_mod_ahb */
125 typedef enum _nic_fn_mod_ahb
126 {
127 kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0,
128 kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE,
129 kNIC_FN_MOD_AHB_LOCK_OVERRIDE,
130 } nic_fn_mod_ahb_t;
131
132 /* fn_mod */
133 typedef enum _nic_fn_mod
134 {
135 kNIC_FN_MOD_ReadIssue = 0,
136 kNIC_FN_MOD_WriteIssue,
137 } nic_fn_mod_t;
138
139 /* read_qos/write_qos */
140 typedef enum _nic_qos
141 {
142 kNIC_QOS_0 = 0,
143 kNIC_QOS_1,
144 kNIC_QOS_2,
145 kNIC_QOS_3,
146 kNIC_QOS_4,
147 kNIC_QOS_5,
148 kNIC_QOS_6,
149 kNIC_QOS_7,
150 kNIC_QOS_8,
151 kNIC_QOS_9,
152 kNIC_QOS_10,
153 kNIC_QOS_11,
154 kNIC_QOS_12,
155 kNIC_QOS_13,
156 kNIC_QOS_14,
157 kNIC_QOS_15,
158 } nic_qos_t;
159
160 /*******************************************************************************
161 * API
162 ******************************************************************************/
163 #if defined(__cplusplus)
164 extern "C" {
165 #endif /* __cplusplus */
166
167 /*!
168 * @brief Set read_qos Value
169 *
170 * @param base Base address of GPV address
171 * @param value Target value (0 - 15)
172 */
NIC_SetReadQos(nic_reg_t base,nic_qos_t value)173 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
174 {
175 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
176 __DSB();
177 }
178
179 /*!
180 * @brief Get read_qos Value
181 *
182 * @param base Base address of GPV address
183 * @return Current value configured
184 */
NIC_GetReadQos(nic_reg_t base)185 static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
186 {
187 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
188 }
189
190 /*!
191 * @brief Set write_qos Value
192 *
193 * @param base Base address of GPV address
194 * @param value Target value (0 - 15)
195 */
NIC_SetWriteQos(nic_reg_t base,nic_qos_t value)196 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
197 {
198 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
199 __DSB();
200 }
201
202 /*!
203 * @brief Get write_qos Value
204 *
205 * @param base Base address of GPV address
206 * @return Current value configured
207 */
NIC_GetWriteQos(nic_reg_t base)208 static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
209 {
210 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
211 }
212
213 /*!
214 * @brief Set fn_mod_ahb Value
215 *
216 * @param base Base address of GPV address
217 * @param value Target value
218 */
NIC_SetFnModAhb(nic_reg_t base,nic_fn_mod_ahb_t value)219 static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t value)
220 {
221 *(volatile uint32_t *)(base) = value;
222 __DSB();
223 }
224
225 /*!
226 * @brief Get fn_mod_ahb Value
227 *
228 * @param base Base address of GPV address
229 * @return Current value configured
230 */
NIC_GetFnModAhb(nic_reg_t base)231 static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
232 {
233 return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
234 }
235
236 /*!
237 * @brief Set wr_tidemark Value
238 *
239 * @param base Base address of GPV address
240 * @param value Target value (0 - 7)
241 */
NIC_SetWrTideMark(nic_reg_t base,uint8_t value)242 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
243 {
244 *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
245 __DSB();
246 }
247
248 /*!
249 * @brief Get wr_tidemark Value
250 *
251 * @param base Base address of GPV address
252 * @return Current value configured
253 */
NIC_GetWrTideMark(nic_reg_t base)254 static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
255 {
256 return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
257 }
258
259 /*!
260 * @brief Set fn_mod Value
261 *
262 * @param base Base address of GPV address
263 * @param value Target value
264 */
NIC_SetFnMod(nic_reg_t base,nic_fn_mod_t value)265 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
266 {
267 *(volatile uint32_t *)(base) = value;
268 __DSB();
269 }
270
271 /*!
272 * @brief Get fn_mod Value
273 *
274 * @param base Base address of GPV address
275 * @return Current value configured
276 */
NIC_GetFnMod(nic_reg_t base)277 static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
278 {
279 return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
280 }
281
282 /*!
283 * @brief Set fn_mod2 Value
284 *
285 * @param base Base address of GPV address
286 * @param value Target value
287 */
NIC_SetFnMod2(nic_reg_t base,nic_fn_mod_t value)288 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
289 {
290 *(volatile uint32_t *)(base) = value;
291 __DSB();
292 }
293
294 /*!
295 * @brief Get fn_mod2 Value
296 *
297 * @param base Base address of GPV address
298 * @return Current value configured
299 */
NIC_GetFnMod2(nic_reg_t base)300 static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base)
301 {
302 return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK);
303 }
304
305 #if defined(__cplusplus)
306 }
307 #endif /* __cplusplus */
308 /*!
309 * @}
310 */
311 #endif /* _FSL_NIC301_H_ */
312
