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Searched refs:NIC_READ_QOS_OFFSET (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_nic301.h39 #define NIC_READ_QOS_OFFSET (0x100UL) macro
71 kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
67 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_nic301.h40 #define NIC_READ_QOS_OFFSET (0x100UL) macro
67 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_nic301.h38 #define NIC_READ_QOS_OFFSET (0x100UL) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
63 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
64 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
66 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
67 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_nic301.h38 #define NIC_READ_QOS_OFFSET (0x100UL) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
63 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
64 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
66 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
67 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_nic301.h38 #define NIC_READ_QOS_OFFSET (0x100UL) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
63 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
64 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
66 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
67 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_nic301.h38 #define NIC_READ_QOS_OFFSET (0x100UL) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
63 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
64 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
65 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
66 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
67 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
68 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,