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Searched refs:ICER (Results 1 – 25 of 28) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_cm0.h318 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
665 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm1.h318 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
692 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_sc000.h324 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
791 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm0plus.h332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_armv8mbl.h355 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1294 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
1645 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_cm23.h355 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1369 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
1720 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_armv8mml.h465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
2094 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2469 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_cm35p.h465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
2169 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2544 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_cm33.h465 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
2169 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2544 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_armv81mml.h466 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
2227 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2602 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_sc300.h344 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1528 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm3.h344 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1545 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm4.h410 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1721 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm7.h425 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1944 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm0plus.h332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm33.h472 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
2420 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2795 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in TZ_NVIC_DisableIRQ_NS()
Dcore_cm4.h415 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1726 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
Dcore_cm7.h430 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ member
1953 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_NVIC.h83 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register, array offse… member
DS32K118_NVIC.h83 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register, array offse… member
DS32K142W_NVIC.h84 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array off… member
DS32K148_NVIC.h84 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array off… member
DS32K146_NVIC.h84 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array off… member
DS32K142_NVIC.h84 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array off… member
DS32K144W_NVIC.h84 …__IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array off… member

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