1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_NVIC.h 10 * @version 1.0 11 * @date 2021-02-18 12 * @brief Peripheral Access Layer for S32K116_NVIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_NVIC_H_) /* Check if memory map has not been already included */ 58 #define S32K116_NVIC_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_NVIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_NVIC_Peripheral_Access_Layer S32_NVIC Peripheral Access Layer 68 * @{ 69 */ 70 71 72 /** S32_NVIC - Size of Registers Arrays */ 73 #define S32_NVIC_ISER_COUNT 1u 74 #define S32_NVIC_ICER_COUNT 1u 75 #define S32_NVIC_ISPR_COUNT 1u 76 #define S32_NVIC_ICPR_COUNT 1u 77 #define S32_NVIC_IPR_COUNT 8u 78 79 /** S32_NVIC - Register Layout Typedef */ 80 typedef struct { 81 __IO uint32_t ISER[S32_NVIC_ISER_COUNT]; /**< Interrupt Set Enable Register, array offset: 0x0, array step: 0x4 */ 82 uint8_t RESERVED_0[124]; 83 __IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register, array offset: 0x80, array step: 0x4 */ 84 uint8_t RESERVED_1[124]; 85 __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT]; /**< Interrupt Set Pending Register, array offset: 0x100, array step: 0x4 */ 86 uint8_t RESERVED_2[124]; 87 __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT]; /**< Interrupt Clear Pending Register, array offset: 0x180, array step: 0x4 */ 88 uint8_t RESERVED_3[380]; 89 __IO uint32_t IP[S32_NVIC_IPR_COUNT]; /**< Interrupt Priority Register n, array offset: 0x300, array step: 0x4 */ 90 } S32_NVIC_Type, *S32_NVIC_MemMapPtr; 91 92 /** Number of instances of the S32_NVIC module. */ 93 #define S32_NVIC_INSTANCE_COUNT (1u) 94 95 96 /* S32_NVIC - Peripheral instance base addresses */ 97 /** Peripheral S32_NVIC base address */ 98 #define S32_NVIC_BASE (0xE000E100u) 99 /** Peripheral S32_NVIC base pointer */ 100 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE) 101 /** Array initializer of S32_NVIC peripheral base addresses */ 102 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE } 103 /** Array initializer of S32_NVIC peripheral base pointers */ 104 #define S32_NVIC_BASE_PTRS { S32_NVIC } 105 106 /* ---------------------------------------------------------------------------- 107 -- S32_NVIC Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup S32_NVIC_Register_Masks S32_NVIC Register Masks 112 * @{ 113 */ 114 115 /* ISER Bit Fields */ 116 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu 117 #define S32_NVIC_ISER_SETENA_SHIFT 0u 118 #define S32_NVIC_ISER_SETENA_WIDTH 32u 119 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK) 120 /* ICER Bit Fields */ 121 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu 122 #define S32_NVIC_ICER_CLRENA_SHIFT 0u 123 #define S32_NVIC_ICER_CLRENA_WIDTH 32u 124 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK) 125 /* ISPR Bit Fields */ 126 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu 127 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u 128 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u 129 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK) 130 /* ICPR Bit Fields */ 131 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu 132 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u 133 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u 134 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK) 135 /* IPR Bit Fields */ 136 #define S32_NVIC_IPR_PRI_0_MASK 0xFFu 137 #define S32_NVIC_IPR_PRI_0_SHIFT 0u 138 #define S32_NVIC_IPR_PRI_0_WIDTH 8u 139 #define S32_NVIC_IPR_PRI_0(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_0_SHIFT))&S32_NVIC_IPR_PRI_0_MASK) 140 #define S32_NVIC_IPR_PRI_1_MASK 0xFF00u 141 #define S32_NVIC_IPR_PRI_1_SHIFT 8u 142 #define S32_NVIC_IPR_PRI_1_WIDTH 8u 143 #define S32_NVIC_IPR_PRI_1(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_1_SHIFT))&S32_NVIC_IPR_PRI_1_MASK) 144 #define S32_NVIC_IPR_PRI_2_MASK 0xFF0000u 145 #define S32_NVIC_IPR_PRI_2_SHIFT 16u 146 #define S32_NVIC_IPR_PRI_2_WIDTH 8u 147 #define S32_NVIC_IPR_PRI_2(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_2_SHIFT))&S32_NVIC_IPR_PRI_2_MASK) 148 #define S32_NVIC_IPR_PRI_3_MASK 0xFF000000u 149 #define S32_NVIC_IPR_PRI_3_SHIFT 24u 150 #define S32_NVIC_IPR_PRI_3_WIDTH 8u 151 #define S32_NVIC_IPR_PRI_3(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_3_SHIFT))&S32_NVIC_IPR_PRI_3_MASK) 152 153 /*! 154 * @} 155 */ /* end of group S32_NVIC_Register_Masks */ 156 157 158 /*! 159 * @} 160 */ /* end of group S32_NVIC_Peripheral_Access_Layer */ 161 162 #endif /* #if !defined(S32K116_NVIC_H_) */ 163
