| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/s32/drivers/s32k1/Mcu/src/ |
| D | Clock_Ip_IntOsc.c | 624 IP_SCG->FIRCCSR &= (uint32)(~(SCG_FIRCCSR_LK_MASK)); in Clock_Ip_SetFirc_TrustedCall()
627 if ((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCSEL_MASK) != 0U) in Clock_Ip_SetFirc_TrustedCall()
631 …(Config->Regulator != ((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCREGOFF_MASK) >> SCG_FIRCCSR_FIRCREGOFF_S… in Clock_Ip_SetFirc_TrustedCall()
644 IP_SCG->FIRCCSR &= (~((uint32)SCG_FIRCCSR_FIRCEN_MASK)); in Clock_Ip_SetFirc_TrustedCall()
653 … IP_SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN(1U) | SCG_FIRCCSR_FIRCREGOFF(Config->Regulator)); in Clock_Ip_SetFirc_TrustedCall()
659 … IrcoscStatus = (((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) >> SCG_FIRCCSR_FIRCVLD_SHIFT)); in Clock_Ip_SetFirc_TrustedCall()
685 IP_SCG->FIRCCSR &= (~((uint32)SCG_FIRCCSR_FIRCEN_MASK)); in Clock_Ip_SetFirc_TrustedCall()
693 IP_SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN(1U) | SCG_FIRCCSR_FIRCREGOFF(Config->Regulator)); in Clock_Ip_SetFirc_TrustedCall()
699 … IrcoscStatus = (((IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) >> SCG_FIRCCSR_FIRCVLD_SHIFT)); in Clock_Ip_SetFirc_TrustedCall()
723 IP_SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN(1U); in Clock_Ip_EnableFirc_TrustedCall()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/drivers/ |
| D | fsl_clock.c | 236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || in CLOCK_GetFroHfFreq()
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) in CLOCK_GetFroHfFreq()
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || in CLOCK_GetClk48MFreq()
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? in CLOCK_GetClk48MFreq()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/ |
| D | fsl_clock.c | 540 CLOCK_REG(&SCG0->FIRCCSR) = (uint32_t)config->trimConfig->trimMode; in CLOCK_InitFirc()
548 if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) in CLOCK_InitFirc()
554 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
557 while ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) != SCG_FIRCCSR_FIRCVLD_MASK) in CLOCK_InitFirc()
577 uint32_t reg = CLOCK_REG(&SCG0->FIRCCSR); in CLOCK_DeinitFirc()
591 CLOCK_REG(&SCG0->FIRCCSR) = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
605 …if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) == SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is… in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/ |
| D | fsl_clock.c | 539 CLOCK_REG(&SCG0->FIRCCSR) = (uint32_t)config->trimConfig->trimMode; in CLOCK_InitFirc()
547 if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) in CLOCK_InitFirc()
553 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
556 while ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) != SCG_FIRCCSR_FIRCVLD_MASK) in CLOCK_InitFirc()
576 uint32_t reg = CLOCK_REG(&SCG0->FIRCCSR); in CLOCK_DeinitFirc()
590 CLOCK_REG(&SCG0->FIRCCSR) = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
604 …if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) == SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is… in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/ |
| D | fsl_clock.c | 539 CLOCK_REG(&SCG0->FIRCCSR) = (uint32_t)config->trimConfig->trimMode; in CLOCK_InitFirc()
547 if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) in CLOCK_InitFirc()
553 CLOCK_REG(&SCG0->FIRCCSR) |= (SCG_FIRCCSR_FIRCEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitFirc()
556 while ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) != SCG_FIRCCSR_FIRCVLD_MASK) in CLOCK_InitFirc()
576 uint32_t reg = CLOCK_REG(&SCG0->FIRCCSR); in CLOCK_DeinitFirc()
590 CLOCK_REG(&SCG0->FIRCCSR) = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
604 …if ((CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_FIRCVLD_MASK) == SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is… in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/ |
| D | fsl_clock.c | 638 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
640 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
647 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
650 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
685 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
704 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/ |
| D | fsl_clock.c | 555 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
557 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0U) in CLOCK_InitFirc()
564 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode); in CLOCK_InitFirc()
567 while (0U == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
587 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
601 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
620 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/ |
| D | fsl_clock.c | 618 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
620 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
627 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
630 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
650 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
665 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
684 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/ |
| D | fsl_clock.c | 638 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
640 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
647 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
650 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
685 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
704 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/ |
| D | fsl_clock.c | 638 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
640 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
647 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
650 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
685 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
704 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/ |
| D | fsl_clock.c | 618 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
620 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
627 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
630 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
650 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
665 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
684 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/ |
| D | fsl_clock.c | 618 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
620 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
627 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
630 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
650 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
665 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
684 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/ |
| D | fsl_clock.c | 683 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
685 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
692 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
695 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
715 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
730 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
752 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/ |
| D | fsl_clock.c | 683 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
685 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
692 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
695 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
715 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
730 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
752 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/ |
| D | fsl_clock.c | 749 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
751 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
758 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
761 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
781 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
796 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
818 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/ |
| D | fsl_clock.c | 749 SCG->FIRCCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitFirc()
751 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) != 0UL) in CLOCK_InitFirc()
758 SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode); in CLOCK_InitFirc()
761 while (0UL == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) in CLOCK_InitFirc()
781 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc()
796 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
818 if ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) != 0UL) /* FIRC is valid. */ in CLOCK_GetFircFreq()
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