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Searched refs:DevAssert (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/Pwm/src/
DEmios_Pwm_Ip.c411 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_GetCounterBusPeriod()
412 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > Channel); in Emios_Pwm_Ip_GetCounterBusPeriod()
420 DevAssert(0xFFU != MasterBusCh); in Emios_Pwm_Ip_GetCounterBusPeriod()
482 DevAssert(NULL_PTR != UserChCfg); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
483 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
484 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > UserChCfg->ChannelId); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
486 DevAssert((UserChCfg->Mode == EMIOS_PWM_IP_MODE_OPWFMB_FLAG) || in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
489 …DevAssert(TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_O… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
491 DevAssert(EMIOS_PWM_IP_MIN_CNT_VAL < UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
492 DevAssert(UserChCfg->DutyCycle <= UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c268 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_GetCounterBusPeriod()
269 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > Channel); in Emios_Pwm_Ip_GetCounterBusPeriod()
277 DevAssert(0xFFU != MasterBusCh); in Emios_Pwm_Ip_GetCounterBusPeriod()
330 DevAssert(NULL_PTR != UserChCfg); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
331 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
332 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > UserChCfg->ChannelId); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
334 DevAssert((UserChCfg->Mode == EMIOS_PWM_IP_MODE_OPWFMB_FLAG) || in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
337 …DevAssert(TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_O… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
339 DevAssert(EMIOS_PWM_IP_MIN_CNT_VAL < UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
340 DevAssert(UserChCfg->DutyCycle <= UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Icu/src/
DEmios_Icu_Ip.c566 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Init()
567 DevAssert(userConfig != NULL_PTR); in Emios_Icu_Ip_Init()
769 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Deinit()
885 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetSleepMode()
886 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetSleepMode()
887 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SetSleepMode()
896 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetNormalMode()
897 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetNormalMode()
913 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetActivation()
914 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetActivation()
[all …]
DEmios_Icu_Ip_Irq.c355 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_GetCaptureRegA()
356 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_GetCaptureRegA()
998 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SignalMeasurementHandler()
999 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SignalMeasurementHandler()
1000 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SignalMeasurementHandler()
1040 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_IrqHandler()
1041 DevAssert(channel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_IrqHandler()
/hal_nxp-latest/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c519 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Init()
520 DevAssert(userConfig != NULL_PTR); in Emios_Icu_Ip_Init()
671 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_Deinit()
759 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetSleepMode()
760 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetSleepMode()
761 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SetSleepMode()
772 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetNormalMode()
773 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetNormalMode()
793 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SetActivation()
794 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SetActivation()
[all …]
DEmios_Icu_Ip_Irq.c401 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_GetCaptureRegA()
402 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_GetCaptureRegA()
996 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_SignalMeasurementHandler()
997 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_SignalMeasurementHandler()
998 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED); in Emios_Icu_Ip_SignalMeasurementHandler()
1038 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT); in Emios_Icu_Ip_IrqHandler()
1039 DevAssert(channel < EMIOS_ICU_IP_NUM_OF_CHANNELS); in Emios_Icu_Ip_IrqHandler()
/hal_nxp-latest/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c164 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_Init()
165 DevAssert(ConfigPtr != NULL_PTR); in Emios_Mcl_Ip_Init()
266 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_EnableChannel()
267 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_EnableChannel()
278 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_DisableChannel()
279 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_DisableChannel()
290 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferEnable()
291 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferEnable()
303 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferDisable()
304 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferDisable()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Mcl/src/
DEmios_Mcl_Ip.c164 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_Init()
165 DevAssert(ConfigPtr != NULL_PTR); in Emios_Mcl_Ip_Init()
259 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferEnable()
260 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferEnable()
272 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_ComparatorTransferDisable()
273 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL); in Emios_Mcl_Ip_ComparatorTransferDisable()
285 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_Deinit()
337 DevAssert((uint8)31 > Interval); in Emios_Mcl_Ip_SetReloadInterval()
338 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_SetReloadInterval()
339 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_SetReloadInterval()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c182 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_GetControllerMRU()
183 DevAssert(pValue != NULL_PTR); in Canexcel_GetControllerMRU()
391 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_GetStartMode()
409 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_ConfigTimeStamp()
434 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_SetStopMode()
504 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_Init()
505 DevAssert(Config != NULL_PTR); in Canexcel_Ip_Init()
506 DevAssert(pState != NULL_PTR); in Canexcel_Ip_Init()
579 DevAssert(instance < CANXL_SIC_INSTANCE_COUNT); in Canexcel_Ip_SetRxIndividualMask()
580 DevAssert(descNo < CANXL_DSC_CONTROL_DSCMBCTRLAR_COUNT); in Canexcel_Ip_SetRxIndividualMask()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c1230 DevAssert((ResultsRaw != NULL_PTR) || (ResultsStruct != NULL_PTR)); in Adc_Sar_GetConvResults()
1783 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_IRQHandler()
1976 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Init()
1977 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
1981 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2190 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Deinit()
2359 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_ChainConfig()
2360 DevAssert(pChansIdxMask != NULL_PTR); in Adc_Sar_Ip_ChainConfig()
2366 …DevAssert((pChansIdxMask->ChanMaskArr[i] & (~Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][i])) == 0u); in Adc_Sar_Ip_ChainConfig()
2382 DevAssert(FALSE); in Adc_Sar_Ip_ChainConfig()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c1436 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1514 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1676 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1677 DevAssert(SwitchPortIdx < NETC_ETHSWT_IP_NUMBER_OF_PORTS);
1738 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1739 DevAssert(SwitchPortIdx < NETC_ETHSWT_IP_NUMBER_OF_PORTS);
1795 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1796 DevAssert(SwitchPortIdx < NETC_ETHSWT_IP_NUMBER_OF_PORTS);
1885 DevAssert(SwitchIdx < FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS);
1886 DevAssert(SwitchPortIdx < NETC_ETHSWT_IP_NUMBER_OF_PORTS);
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Adc/src/
DAdc_Sar_Ip.c1268 DevAssert((ResultsRaw != NULL_PTR) || (ResultsStruct != NULL_PTR)); in Adc_Sar_GetConvResults()
1895 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_IRQHandler()
2162 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Init()
2163 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
2167 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2383 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_Deinit()
2551 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT); in Adc_Sar_Ip_ChainConfig()
2552 DevAssert(pChansIdxMask != NULL_PTR); in Adc_Sar_Ip_ChainConfig()
2559 …DevAssert((pChansIdxMask->ChanMaskArr[i] & (~Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][i])) == 0u); in Adc_Sar_Ip_ChainConfig()
2575 DevAssert(FALSE); in Adc_Sar_Ip_ChainConfig()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c1627 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_AddMACFilterEntry()
1628 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_AddMACFilterEntry()
1663 DevAssert(CtrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_DeleteMACFilterEntry()
1664 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_DeleteMACFilterEntry()
2140 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_AddVLANFilterTableEntry()
2141 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]); in Netc_Eth_Ip_AddVLANFilterTableEntry()
2171 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_QueryVLANFilterTableEntry()
2172 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]); in Netc_Eth_Ip_QueryVLANFilterTableEntry()
2218 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_ConfigVLANFilterTable()
2247 DevAssert(ctrlIndex < FEATURE_NETC_ETH_NUMBER_OF_CTRLS); in Netc_Eth_Ip_ConfigRatePolicerTable()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c281 DevAssert(State->NbCmdsIndex < 3u); in Spi_Ip_WriteCmdFifo()
434 DevAssert(State->NbCmds > 0u); in Spi_Ip_UpdateCtarAndPushr()
1108 DevAssert(NumberOfWrites <= SPI_IP_FIFO_SIZE_U16); in Spi_Ip_WriteTxFifo()
1350 DevAssert(ExternalDevice != NULL_PTR); in Spi_Ip_CheckValidParameters()
1351 DevAssert(0u != Length); in Spi_Ip_CheckValidParameters()
1352 DevAssert(0u != TimeOut); in Spi_Ip_CheckValidParameters()
1355 DevAssert((Length % 4u) == 0u); in Spi_Ip_CheckValidParameters()
1359 DevAssert((Length % 2u) == 0u); in Spi_Ip_CheckValidParameters()
1365 DevAssert(Spi_Ip_apxStateStructureArray[ExternalDevice->Instance] != NULL_PTR); in Spi_Ip_CheckValidParameters()
1371 DevAssert((TxBuffer >> 32) == 0); in Spi_Ip_CheckValidParameters()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Platform/src/
DMru_Ip.c226 DevAssert(NULL_PTR != HWUnitConfigPtr); in Mru_Ip_Init_Privileged()
254 DevAssert(NULL_PTR != TransmitChCfgPtr); in Mru_Ip_Transmit_Privileged()
255 DevAssert(NULL_PTR != TxBufferPtr); in Mru_Ip_Transmit_Privileged()
283 DevAssert(NULL_PTR != TransmitChCfgPtr); in Mru_Ip_ResetTransmitChannel_Privileged()
301 DevAssert(NULL_PTR != ReceiveChCfgPtr); in Mru_Ip_ResetReceiveChannel_Privileged()
326 DevAssert(NULL_PTR != ResetInsCfgPtr); in Mru_Ip_ResetInstance_Privileged()
350 DevAssert(NULL_PTR != ReceiveChCfgPtr); in Mru_Ip_ReadMailbox_Privileged()
351 DevAssert(NULL_PTR != RxBufferPtr); in Mru_Ip_ReadMailbox_Privileged()
363 DevAssert((sint8)LastRxMailboxIdx >= (sint8)0); in Mru_Ip_ReadMailbox_Privileged()
411 DevAssert(NULL_PTR != ReceiveChCfgPtr); in Mru_Ip_GetMailboxStatus_Privileged()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h498 DevAssert(timeSeg != NULL_PTR); in CanXL_SetFDBaudRate()
517 DevAssert(timeSeg != NULL_PTR); in CanXL_SetXLBaudRate()
536 DevAssert(timeSeg != NULL_PTR); in CanXL_SetBaudRate()
601 DevAssert(timeSeg != NULL_PTR); in CanXL_GetFDBaudRate()
620 DevAssert(timeSeg != NULL_PTR); in CanXL_GetXLBaudRate()
638 DevAssert(timeSeg != NULL_PTR); in CanXL_GetBaudRate()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/include/
DDevassert.h53 #define DevAssert(x) macro
68 static inline void DevAssert(volatile boolean x) in DevAssert() function
DOsIf_Cfg_TypesDef.h37 #define OSIF_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/include/
DDevassert.h53 #define DevAssert(x) macro
67 static inline void DevAssert(volatile boolean x) in DevAssert() function
DOsIf_Cfg_TypesDef.h37 #define OSIF_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/include/
DDevassert.h53 #define DevAssert(x) macro
68 static inline void DevAssert(volatile boolean x) in DevAssert() function
DOsIf_Cfg_TypesDef.h37 #define OSIF_DEV_ASSERT(x) DevAssert(x)
/hal_nxp-latest/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h283 DevAssert(RegisterNumber < ADC_SAR_IP_THRHLR_COUNT); in Adc_Sar_WriteThresholds()
469 DevAssert(FALSE); in Adc_Sar_GetChannelWatchdogAddress()
/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip_HwAccess.h288 DevAssert(RegisterNumber < ADC_SAR_IP_THRHLR_COUNT); in Adc_Sar_WriteThresholds()
474 DevAssert(FALSE); in Adc_Sar_GetChannelWatchdogAddress()
/hal_nxp-latest/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Private.h227 #define CLOCK_IP_DEV_ASSERT(x) DevAssert(x)

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