Searched refs:DSPCPUCLKDIV_OFFSET (Results 1 – 8 of 8) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_clock.h | 479 #define DSPCPUCLKDIV_OFFSET 0x400 macro
788 …kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider.…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_clock.h | 479 #define DSPCPUCLKDIV_OFFSET 0x400 macro
788 …kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider.…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_clock.h | 605 #define DSPCPUCLKDIV_OFFSET 0x400 macro
986 …kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider.…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_clock.h | 605 #define DSPCPUCLKDIV_OFFSET 0x400 macro
986 …kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider.…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_clock.h | 605 #define DSPCPUCLKDIV_OFFSET 0x400 macro
986 …kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider.…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/ |
| D | fsl_clock.h | 799 #define DSPCPUCLKDIV_OFFSET 0x440 macro
1698 …kCLOCK_DivDspClk = CLKCTL0_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< DSP CPU Clk Divider. …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/ |
| D | fsl_clock.h | 799 #define DSPCPUCLKDIV_OFFSET 0x440 macro
1698 …kCLOCK_DivDspClk = CLKCTL0_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< DSP CPU Clk Divider. …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/ |
| D | fsl_clock.h | 799 #define DSPCPUCLKDIV_OFFSET 0x440 macro
1698 …kCLOCK_DivDspClk = CLKCTL0_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< DSP CPU Clk Divider. …
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