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Searched refs:DMA_CHX_STAT (Results 1 – 25 of 36) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/enet_qos/
Dfsl_enet_qos.c3931 uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT; in ENET_QOS_CommonIRQHandler()
3934 … base->DMA_CH[0].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_RI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3942 … base->DMA_CH[0].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_TI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3950 uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT; in ENET_QOS_CommonIRQHandler()
3953 … base->DMA_CH[1].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_RI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3961 … base->DMA_CH[1].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_TI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3969 uint32_t flag = base->DMA_CH[2].DMA_CHX_STAT; in ENET_QOS_CommonIRQHandler()
3972 … base->DMA_CH[2].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_RI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3980 … base->DMA_CH[2].DMA_CHX_STAT = ENET_QOS_DMA_CHX_STAT_TI_MASK | ENET_QOS_DMA_CHX_STAT_NIS_MASK; in ENET_QOS_CommonIRQHandler()
3988 uint32_t flag = base->DMA_CH[3].DMA_CHX_STAT; in ENET_QOS_CommonIRQHandler()
[all …]
Dfsl_enet_qos.h1236 return base->DMA_CH[channel].DMA_CHX_STAT; in ENET_QOS_GetDmaInterruptStatus()
1250 base->DMA_CH[channel].DMA_CHX_STAT = mask; in ENET_QOS_ClearDmaInterruptStatus()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_enet/
Dfsl_enet.c1265 if ((base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) != 0U) in ENET_ReadFrame()
2381 uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT; in ENET_IRQHandler()
2384 …base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2392 …base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2400 uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT; in ENET_IRQHandler()
2403 …base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2411 …base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
Dfsl_enet.h938 return base->DMA_CH[channel].DMA_CHX_STAT; in ENET_GetDmaInterruptStatus()
952 base->DMA_CH[channel].DMA_CHX_STAT = mask; in ENET_ClearDmaInterruptStatus()
/hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_enet/
Dfsl_enet.c1387 if ((base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) != 0U) in ENET_ReadFrame()
2503 uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT; in ENET_IRQHandler()
2506 …base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2514 …base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2522 uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT; in ENET_IRQHandler()
2525 …base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
2533 …base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MAS… in ENET_IRQHandler()
Dfsl_enet.h1023 return base->DMA_CH[channel].DMA_CHX_STAT; in ENET_GetDmaInterruptStatus()
1037 base->DMA_CH[channel].DMA_CHX_STAT = mask; in ENET_ClearDmaInterruptStatus()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h5276 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h4787 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h5351 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h5143 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h5347 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h5349 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h5551 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h5143 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h5152 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h5272 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h5551 …__IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h16771 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
DMCXN546_cm33_core1.h16771 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h16771 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
DMCXN547_cm33_core1.h16771 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16817 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
DMCXN947_cm33_core0.h16817 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16817 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member
DMCXN946_cm33_core1.h16817 …__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 1 Status, … member

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