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Searched refs:CnSC (Results 1 – 25 of 131) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/ftm/
Dfsl_ftm.c497 reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; in FTM_SetupPwm()
507 base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; in FTM_SetupPwm()
543 reg = base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC; in FTM_SetupPwm()
550 base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC = reg; in FTM_SetupPwm()
553 reg = base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC; in FTM_SetupPwm()
560 base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC = reg; in FTM_SetupPwm()
671 uint32_t reg = base->CONTROLS[chnlNumber].CnSC; in FTM_UpdateChnlEdgeLevelSelect()
677 base->CONTROLS[chnlNumber].CnSC = reg; in FTM_UpdateChnlEdgeLevelSelect()
734 reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; in FTM_SetupPwmMode()
744 base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; in FTM_SetupPwmMode()
[all …]
Dfsl_ftm.h1090 base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_DMA_MASK; in FTM_EnableDmaTransfer()
1095 base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_DMA_MASK; in FTM_EnableDmaTransfer()
/hal_nxp-latest/mcux/mcux-sdk/drivers/tpm/
Dfsl_tpm.h510 return (uint8_t)(base->CONTROLS[chnlNumber].CnSC & in TPM_GetChannelContorlBits()
527 base->CONTROLS[chnlNumber].CnSC &= in TPM_DisableChannel()
537 } while (0U != (base->CONTROLS[chnlNumber].CnSC & in TPM_DisableChannel()
560 base->CONTROLS[chnlNumber].CnSC = in TPM_EnableChannel()
561 (base->CONTROLS[chnlNumber].CnSC & in TPM_EnableChannel()
573 (uint8_t)(base->CONTROLS[chnlNumber].CnSC & in TPM_EnableChannel()
781 if (0U != (base->CONTROLS[chanlNumber].CnSC & TPM_CnSC_CHF_MASK)) in TPM_GetStatusFlags()
816 base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHF_MASK; in TPM_ClearStatusFlags()
Dfsl_tpm.c1027 base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK; in TPM_EnableInterrupts()
1057 base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK; in TPM_DisableInterrupts()
1091 if (0U != (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK)) in TPM_GetEnabledInterrupts()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K148_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K118_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K116_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K146_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: … member
DS32K142W_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K144W_FTM.h81 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
DS32K144_FTM.h80 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h6498 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/
DMKE04Z4.h1009 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/
DMKE02Z4.h997 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/
DMKE04Z1284.h1022 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/
DMKE06Z4.h1022 …__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h7989 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/
DMCXC141.h8986 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/
DMCXC142.h8984 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h4175 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/
DMCXC242.h8994 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h8005 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h9636 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h9636 …__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset… member

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