1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_FTM.h 10 * @version 1.1 11 * @date 2022-02-01 12 * @brief Peripheral Access Layer for S32K142_FTM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_FTM_H_) /* Check if memory map has not been already included */ 58 #define S32K142_FTM_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FTM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FTM - Size of Registers Arrays */ 72 #define FTM_CnSC_COUNT 8u 73 #define FTM_CV_MIRROR_COUNT 8u 74 75 /** FTM - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 78 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 79 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 80 struct { /* offset: 0xC, array step: 0x8 */ 81 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 82 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 83 } CONTROLS[FTM_CnSC_COUNT]; 84 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 85 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 86 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 87 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 88 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 89 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 90 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 91 __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */ 92 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 93 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 94 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 95 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 96 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 97 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ 98 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 99 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 100 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 101 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 102 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 103 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 104 __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */ 105 __IO uint32_t PAIR0DEADTIME; /**< Pair 0 Deadtime Configuration, offset: 0xA0 */ 106 uint8_t RESERVED_0[4]; 107 __IO uint32_t PAIR1DEADTIME; /**< Pair 1 Deadtime Configuration, offset: 0xA8 */ 108 uint8_t RESERVED_1[4]; 109 __IO uint32_t PAIR2DEADTIME; /**< Pair 2 Deadtime Configuration, offset: 0xB0 */ 110 uint8_t RESERVED_2[4]; 111 __IO uint32_t PAIR3DEADTIME; /**< Pair 3 Deadtime Configuration, offset: 0xB8 */ 112 uint8_t RESERVED_3[324]; 113 __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */ 114 __IO uint32_t CV_MIRROR[FTM_CV_MIRROR_COUNT]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */ 115 } FTM_Type, *FTM_MemMapPtr; 116 117 /** Number of instances of the FTM module. */ 118 #define FTM_INSTANCE_COUNT (4u) 119 120 /* FTM - Peripheral instance base addresses */ 121 /** Peripheral FTM0 base address */ 122 #define IP_FTM0_BASE (0x40038000u) 123 /** Peripheral FTM0 base pointer */ 124 #define IP_FTM0 ((FTM_Type *)IP_FTM0_BASE) 125 /** Peripheral FTM1 base address */ 126 #define IP_FTM1_BASE (0x40039000u) 127 /** Peripheral FTM1 base pointer */ 128 #define IP_FTM1 ((FTM_Type *)IP_FTM1_BASE) 129 /** Peripheral FTM2 base address */ 130 #define IP_FTM2_BASE (0x4003A000u) 131 /** Peripheral FTM2 base pointer */ 132 #define IP_FTM2 ((FTM_Type *)IP_FTM2_BASE) 133 /** Peripheral FTM3 base address */ 134 #define IP_FTM3_BASE (0x40026000u) 135 /** Peripheral FTM3 base pointer */ 136 #define IP_FTM3 ((FTM_Type *)IP_FTM3_BASE) 137 /** Array initializer of FTM peripheral base addresses */ 138 #define IP_FTM_BASE_ADDRS { IP_FTM0_BASE, IP_FTM1_BASE, IP_FTM2_BASE, IP_FTM3_BASE } 139 /** Array initializer of FTM peripheral base pointers */ 140 #define IP_FTM_BASE_PTRS { IP_FTM0, IP_FTM1, IP_FTM2, IP_FTM3 } 141 142 /* ---------------------------------------------------------------------------- 143 -- FTM Register Masks 144 ---------------------------------------------------------------------------- */ 145 146 /*! 147 * @addtogroup FTM_Register_Masks FTM Register Masks 148 * @{ 149 */ 150 151 /*! @name SC - Status And Control */ 152 /*! @{ */ 153 154 #define FTM_SC_PS_MASK (0x7U) 155 #define FTM_SC_PS_SHIFT (0U) 156 #define FTM_SC_PS_WIDTH (3U) 157 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 158 159 #define FTM_SC_CLKS_MASK (0x18U) 160 #define FTM_SC_CLKS_SHIFT (3U) 161 #define FTM_SC_CLKS_WIDTH (2U) 162 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 163 164 #define FTM_SC_CPWMS_MASK (0x20U) 165 #define FTM_SC_CPWMS_SHIFT (5U) 166 #define FTM_SC_CPWMS_WIDTH (1U) 167 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 168 169 #define FTM_SC_RIE_MASK (0x40U) 170 #define FTM_SC_RIE_SHIFT (6U) 171 #define FTM_SC_RIE_WIDTH (1U) 172 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK) 173 174 #define FTM_SC_RF_MASK (0x80U) 175 #define FTM_SC_RF_SHIFT (7U) 176 #define FTM_SC_RF_WIDTH (1U) 177 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK) 178 179 #define FTM_SC_TOIE_MASK (0x100U) 180 #define FTM_SC_TOIE_SHIFT (8U) 181 #define FTM_SC_TOIE_WIDTH (1U) 182 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 183 184 #define FTM_SC_TOF_MASK (0x200U) 185 #define FTM_SC_TOF_SHIFT (9U) 186 #define FTM_SC_TOF_WIDTH (1U) 187 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 188 189 #define FTM_SC_PWMEN0_MASK (0x10000U) 190 #define FTM_SC_PWMEN0_SHIFT (16U) 191 #define FTM_SC_PWMEN0_WIDTH (1U) 192 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK) 193 194 #define FTM_SC_PWMEN1_MASK (0x20000U) 195 #define FTM_SC_PWMEN1_SHIFT (17U) 196 #define FTM_SC_PWMEN1_WIDTH (1U) 197 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK) 198 199 #define FTM_SC_PWMEN2_MASK (0x40000U) 200 #define FTM_SC_PWMEN2_SHIFT (18U) 201 #define FTM_SC_PWMEN2_WIDTH (1U) 202 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK) 203 204 #define FTM_SC_PWMEN3_MASK (0x80000U) 205 #define FTM_SC_PWMEN3_SHIFT (19U) 206 #define FTM_SC_PWMEN3_WIDTH (1U) 207 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK) 208 209 #define FTM_SC_PWMEN4_MASK (0x100000U) 210 #define FTM_SC_PWMEN4_SHIFT (20U) 211 #define FTM_SC_PWMEN4_WIDTH (1U) 212 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK) 213 214 #define FTM_SC_PWMEN5_MASK (0x200000U) 215 #define FTM_SC_PWMEN5_SHIFT (21U) 216 #define FTM_SC_PWMEN5_WIDTH (1U) 217 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK) 218 219 #define FTM_SC_PWMEN6_MASK (0x400000U) 220 #define FTM_SC_PWMEN6_SHIFT (22U) 221 #define FTM_SC_PWMEN6_WIDTH (1U) 222 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK) 223 224 #define FTM_SC_PWMEN7_MASK (0x800000U) 225 #define FTM_SC_PWMEN7_SHIFT (23U) 226 #define FTM_SC_PWMEN7_WIDTH (1U) 227 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK) 228 229 #define FTM_SC_FLTPS_MASK (0xF000000U) 230 #define FTM_SC_FLTPS_SHIFT (24U) 231 #define FTM_SC_FLTPS_WIDTH (4U) 232 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK) 233 /*! @} */ 234 235 /*! @name CNT - Counter */ 236 /*! @{ */ 237 238 #define FTM_CNT_COUNT_MASK (0xFFFFU) 239 #define FTM_CNT_COUNT_SHIFT (0U) 240 #define FTM_CNT_COUNT_WIDTH (16U) 241 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 242 /*! @} */ 243 244 /*! @name MOD - Modulo */ 245 /*! @{ */ 246 247 #define FTM_MOD_MOD_MASK (0xFFFFU) 248 #define FTM_MOD_MOD_SHIFT (0U) 249 #define FTM_MOD_MOD_WIDTH (16U) 250 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 251 /*! @} */ 252 253 /*! @name CnSC - Channel (n) Status And Control */ 254 /*! @{ */ 255 256 #define FTM_CnSC_DMA_MASK (0x1U) 257 #define FTM_CnSC_DMA_SHIFT (0U) 258 #define FTM_CnSC_DMA_WIDTH (1U) 259 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) 260 261 #define FTM_CnSC_ICRST_MASK (0x2U) 262 #define FTM_CnSC_ICRST_SHIFT (1U) 263 #define FTM_CnSC_ICRST_WIDTH (1U) 264 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) 265 266 #define FTM_CnSC_ELSA_MASK (0x4U) 267 #define FTM_CnSC_ELSA_SHIFT (2U) 268 #define FTM_CnSC_ELSA_WIDTH (1U) 269 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 270 271 #define FTM_CnSC_ELSB_MASK (0x8U) 272 #define FTM_CnSC_ELSB_SHIFT (3U) 273 #define FTM_CnSC_ELSB_WIDTH (1U) 274 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 275 276 #define FTM_CnSC_MSA_MASK (0x10U) 277 #define FTM_CnSC_MSA_SHIFT (4U) 278 #define FTM_CnSC_MSA_WIDTH (1U) 279 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 280 281 #define FTM_CnSC_MSB_MASK (0x20U) 282 #define FTM_CnSC_MSB_SHIFT (5U) 283 #define FTM_CnSC_MSB_WIDTH (1U) 284 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 285 286 #define FTM_CnSC_CHIE_MASK (0x40U) 287 #define FTM_CnSC_CHIE_SHIFT (6U) 288 #define FTM_CnSC_CHIE_WIDTH (1U) 289 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 290 291 #define FTM_CnSC_CHF_MASK (0x80U) 292 #define FTM_CnSC_CHF_SHIFT (7U) 293 #define FTM_CnSC_CHF_WIDTH (1U) 294 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 295 296 #define FTM_CnSC_TRIGMODE_MASK (0x100U) 297 #define FTM_CnSC_TRIGMODE_SHIFT (8U) 298 #define FTM_CnSC_TRIGMODE_WIDTH (1U) 299 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK) 300 301 #define FTM_CnSC_CHIS_MASK (0x200U) 302 #define FTM_CnSC_CHIS_SHIFT (9U) 303 #define FTM_CnSC_CHIS_WIDTH (1U) 304 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK) 305 306 #define FTM_CnSC_CHOV_MASK (0x400U) 307 #define FTM_CnSC_CHOV_SHIFT (10U) 308 #define FTM_CnSC_CHOV_WIDTH (1U) 309 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK) 310 /*! @} */ 311 312 /*! @name CnV - Channel (n) Value */ 313 /*! @{ */ 314 315 #define FTM_CnV_VAL_MASK (0xFFFFU) 316 #define FTM_CnV_VAL_SHIFT (0U) 317 #define FTM_CnV_VAL_WIDTH (16U) 318 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 319 /*! @} */ 320 321 /*! @name CNTIN - Counter Initial Value */ 322 /*! @{ */ 323 324 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 325 #define FTM_CNTIN_INIT_SHIFT (0U) 326 #define FTM_CNTIN_INIT_WIDTH (16U) 327 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 328 /*! @} */ 329 330 /*! @name STATUS - Capture And Compare Status */ 331 /*! @{ */ 332 333 #define FTM_STATUS_CH0F_MASK (0x1U) 334 #define FTM_STATUS_CH0F_SHIFT (0U) 335 #define FTM_STATUS_CH0F_WIDTH (1U) 336 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 337 338 #define FTM_STATUS_CH1F_MASK (0x2U) 339 #define FTM_STATUS_CH1F_SHIFT (1U) 340 #define FTM_STATUS_CH1F_WIDTH (1U) 341 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 342 343 #define FTM_STATUS_CH2F_MASK (0x4U) 344 #define FTM_STATUS_CH2F_SHIFT (2U) 345 #define FTM_STATUS_CH2F_WIDTH (1U) 346 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 347 348 #define FTM_STATUS_CH3F_MASK (0x8U) 349 #define FTM_STATUS_CH3F_SHIFT (3U) 350 #define FTM_STATUS_CH3F_WIDTH (1U) 351 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 352 353 #define FTM_STATUS_CH4F_MASK (0x10U) 354 #define FTM_STATUS_CH4F_SHIFT (4U) 355 #define FTM_STATUS_CH4F_WIDTH (1U) 356 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 357 358 #define FTM_STATUS_CH5F_MASK (0x20U) 359 #define FTM_STATUS_CH5F_SHIFT (5U) 360 #define FTM_STATUS_CH5F_WIDTH (1U) 361 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 362 363 #define FTM_STATUS_CH6F_MASK (0x40U) 364 #define FTM_STATUS_CH6F_SHIFT (6U) 365 #define FTM_STATUS_CH6F_WIDTH (1U) 366 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 367 368 #define FTM_STATUS_CH7F_MASK (0x80U) 369 #define FTM_STATUS_CH7F_SHIFT (7U) 370 #define FTM_STATUS_CH7F_WIDTH (1U) 371 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 372 /*! @} */ 373 374 /*! @name MODE - Features Mode Selection */ 375 /*! @{ */ 376 377 #define FTM_MODE_FTMEN_MASK (0x1U) 378 #define FTM_MODE_FTMEN_SHIFT (0U) 379 #define FTM_MODE_FTMEN_WIDTH (1U) 380 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 381 382 #define FTM_MODE_INIT_MASK (0x2U) 383 #define FTM_MODE_INIT_SHIFT (1U) 384 #define FTM_MODE_INIT_WIDTH (1U) 385 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 386 387 #define FTM_MODE_WPDIS_MASK (0x4U) 388 #define FTM_MODE_WPDIS_SHIFT (2U) 389 #define FTM_MODE_WPDIS_WIDTH (1U) 390 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 391 392 #define FTM_MODE_PWMSYNC_MASK (0x8U) 393 #define FTM_MODE_PWMSYNC_SHIFT (3U) 394 #define FTM_MODE_PWMSYNC_WIDTH (1U) 395 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 396 397 #define FTM_MODE_CAPTEST_MASK (0x10U) 398 #define FTM_MODE_CAPTEST_SHIFT (4U) 399 #define FTM_MODE_CAPTEST_WIDTH (1U) 400 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 401 402 #define FTM_MODE_FAULTM_MASK (0x60U) 403 #define FTM_MODE_FAULTM_SHIFT (5U) 404 #define FTM_MODE_FAULTM_WIDTH (2U) 405 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 406 407 #define FTM_MODE_FAULTIE_MASK (0x80U) 408 #define FTM_MODE_FAULTIE_SHIFT (7U) 409 #define FTM_MODE_FAULTIE_WIDTH (1U) 410 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 411 /*! @} */ 412 413 /*! @name SYNC - Synchronization */ 414 /*! @{ */ 415 416 #define FTM_SYNC_CNTMIN_MASK (0x1U) 417 #define FTM_SYNC_CNTMIN_SHIFT (0U) 418 #define FTM_SYNC_CNTMIN_WIDTH (1U) 419 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 420 421 #define FTM_SYNC_CNTMAX_MASK (0x2U) 422 #define FTM_SYNC_CNTMAX_SHIFT (1U) 423 #define FTM_SYNC_CNTMAX_WIDTH (1U) 424 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 425 426 #define FTM_SYNC_REINIT_MASK (0x4U) 427 #define FTM_SYNC_REINIT_SHIFT (2U) 428 #define FTM_SYNC_REINIT_WIDTH (1U) 429 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 430 431 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 432 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 433 #define FTM_SYNC_SYNCHOM_WIDTH (1U) 434 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 435 436 #define FTM_SYNC_TRIG0_MASK (0x10U) 437 #define FTM_SYNC_TRIG0_SHIFT (4U) 438 #define FTM_SYNC_TRIG0_WIDTH (1U) 439 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 440 441 #define FTM_SYNC_TRIG1_MASK (0x20U) 442 #define FTM_SYNC_TRIG1_SHIFT (5U) 443 #define FTM_SYNC_TRIG1_WIDTH (1U) 444 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 445 446 #define FTM_SYNC_TRIG2_MASK (0x40U) 447 #define FTM_SYNC_TRIG2_SHIFT (6U) 448 #define FTM_SYNC_TRIG2_WIDTH (1U) 449 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 450 451 #define FTM_SYNC_SWSYNC_MASK (0x80U) 452 #define FTM_SYNC_SWSYNC_SHIFT (7U) 453 #define FTM_SYNC_SWSYNC_WIDTH (1U) 454 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 455 /*! @} */ 456 457 /*! @name OUTINIT - Initial State For Channels Output */ 458 /*! @{ */ 459 460 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 461 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 462 #define FTM_OUTINIT_CH0OI_WIDTH (1U) 463 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 464 465 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 466 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 467 #define FTM_OUTINIT_CH1OI_WIDTH (1U) 468 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 469 470 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 471 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 472 #define FTM_OUTINIT_CH2OI_WIDTH (1U) 473 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 474 475 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 476 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 477 #define FTM_OUTINIT_CH3OI_WIDTH (1U) 478 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 479 480 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 481 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 482 #define FTM_OUTINIT_CH4OI_WIDTH (1U) 483 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 484 485 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 486 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 487 #define FTM_OUTINIT_CH5OI_WIDTH (1U) 488 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 489 490 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 491 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 492 #define FTM_OUTINIT_CH6OI_WIDTH (1U) 493 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 494 495 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 496 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 497 #define FTM_OUTINIT_CH7OI_WIDTH (1U) 498 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 499 /*! @} */ 500 501 /*! @name OUTMASK - Output Mask */ 502 /*! @{ */ 503 504 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 505 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 506 #define FTM_OUTMASK_CH0OM_WIDTH (1U) 507 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 508 509 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 510 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 511 #define FTM_OUTMASK_CH1OM_WIDTH (1U) 512 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 513 514 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 515 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 516 #define FTM_OUTMASK_CH2OM_WIDTH (1U) 517 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 518 519 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 520 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 521 #define FTM_OUTMASK_CH3OM_WIDTH (1U) 522 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 523 524 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 525 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 526 #define FTM_OUTMASK_CH4OM_WIDTH (1U) 527 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 528 529 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 530 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 531 #define FTM_OUTMASK_CH5OM_WIDTH (1U) 532 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 533 534 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 535 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 536 #define FTM_OUTMASK_CH6OM_WIDTH (1U) 537 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 538 539 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 540 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 541 #define FTM_OUTMASK_CH7OM_WIDTH (1U) 542 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 543 /*! @} */ 544 545 /*! @name COMBINE - Function For Linked Channels */ 546 /*! @{ */ 547 548 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 549 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 550 #define FTM_COMBINE_COMBINE0_WIDTH (1U) 551 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 552 553 #define FTM_COMBINE_COMP0_MASK (0x2U) 554 #define FTM_COMBINE_COMP0_SHIFT (1U) 555 #define FTM_COMBINE_COMP0_WIDTH (1U) 556 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 557 558 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 559 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 560 #define FTM_COMBINE_DECAPEN0_WIDTH (1U) 561 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 562 563 #define FTM_COMBINE_DECAP0_MASK (0x8U) 564 #define FTM_COMBINE_DECAP0_SHIFT (3U) 565 #define FTM_COMBINE_DECAP0_WIDTH (1U) 566 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 567 568 #define FTM_COMBINE_DTEN0_MASK (0x10U) 569 #define FTM_COMBINE_DTEN0_SHIFT (4U) 570 #define FTM_COMBINE_DTEN0_WIDTH (1U) 571 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 572 573 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 574 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 575 #define FTM_COMBINE_SYNCEN0_WIDTH (1U) 576 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 577 578 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 579 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 580 #define FTM_COMBINE_FAULTEN0_WIDTH (1U) 581 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 582 583 #define FTM_COMBINE_MCOMBINE0_MASK (0x80U) 584 #define FTM_COMBINE_MCOMBINE0_SHIFT (7U) 585 #define FTM_COMBINE_MCOMBINE0_WIDTH (1U) 586 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK) 587 588 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 589 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 590 #define FTM_COMBINE_COMBINE1_WIDTH (1U) 591 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 592 593 #define FTM_COMBINE_COMP1_MASK (0x200U) 594 #define FTM_COMBINE_COMP1_SHIFT (9U) 595 #define FTM_COMBINE_COMP1_WIDTH (1U) 596 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 597 598 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 599 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 600 #define FTM_COMBINE_DECAPEN1_WIDTH (1U) 601 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 602 603 #define FTM_COMBINE_DECAP1_MASK (0x800U) 604 #define FTM_COMBINE_DECAP1_SHIFT (11U) 605 #define FTM_COMBINE_DECAP1_WIDTH (1U) 606 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 607 608 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 609 #define FTM_COMBINE_DTEN1_SHIFT (12U) 610 #define FTM_COMBINE_DTEN1_WIDTH (1U) 611 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 612 613 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 614 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 615 #define FTM_COMBINE_SYNCEN1_WIDTH (1U) 616 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 617 618 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 619 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 620 #define FTM_COMBINE_FAULTEN1_WIDTH (1U) 621 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 622 623 #define FTM_COMBINE_MCOMBINE1_MASK (0x8000U) 624 #define FTM_COMBINE_MCOMBINE1_SHIFT (15U) 625 #define FTM_COMBINE_MCOMBINE1_WIDTH (1U) 626 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK) 627 628 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 629 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 630 #define FTM_COMBINE_COMBINE2_WIDTH (1U) 631 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 632 633 #define FTM_COMBINE_COMP2_MASK (0x20000U) 634 #define FTM_COMBINE_COMP2_SHIFT (17U) 635 #define FTM_COMBINE_COMP2_WIDTH (1U) 636 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 637 638 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 639 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 640 #define FTM_COMBINE_DECAPEN2_WIDTH (1U) 641 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 642 643 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 644 #define FTM_COMBINE_DECAP2_SHIFT (19U) 645 #define FTM_COMBINE_DECAP2_WIDTH (1U) 646 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 647 648 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 649 #define FTM_COMBINE_DTEN2_SHIFT (20U) 650 #define FTM_COMBINE_DTEN2_WIDTH (1U) 651 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 652 653 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 654 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 655 #define FTM_COMBINE_SYNCEN2_WIDTH (1U) 656 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 657 658 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 659 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 660 #define FTM_COMBINE_FAULTEN2_WIDTH (1U) 661 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 662 663 #define FTM_COMBINE_MCOMBINE2_MASK (0x800000U) 664 #define FTM_COMBINE_MCOMBINE2_SHIFT (23U) 665 #define FTM_COMBINE_MCOMBINE2_WIDTH (1U) 666 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK) 667 668 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 669 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 670 #define FTM_COMBINE_COMBINE3_WIDTH (1U) 671 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 672 673 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 674 #define FTM_COMBINE_COMP3_SHIFT (25U) 675 #define FTM_COMBINE_COMP3_WIDTH (1U) 676 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 677 678 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 679 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 680 #define FTM_COMBINE_DECAPEN3_WIDTH (1U) 681 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 682 683 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 684 #define FTM_COMBINE_DECAP3_SHIFT (27U) 685 #define FTM_COMBINE_DECAP3_WIDTH (1U) 686 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 687 688 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 689 #define FTM_COMBINE_DTEN3_SHIFT (28U) 690 #define FTM_COMBINE_DTEN3_WIDTH (1U) 691 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 692 693 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 694 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 695 #define FTM_COMBINE_SYNCEN3_WIDTH (1U) 696 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 697 698 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 699 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 700 #define FTM_COMBINE_FAULTEN3_WIDTH (1U) 701 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 702 703 #define FTM_COMBINE_MCOMBINE3_MASK (0x80000000U) 704 #define FTM_COMBINE_MCOMBINE3_SHIFT (31U) 705 #define FTM_COMBINE_MCOMBINE3_WIDTH (1U) 706 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK) 707 /*! @} */ 708 709 /*! @name DEADTIME - Deadtime Configuration */ 710 /*! @{ */ 711 712 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 713 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 714 #define FTM_DEADTIME_DTVAL_WIDTH (6U) 715 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 716 717 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 718 #define FTM_DEADTIME_DTPS_SHIFT (6U) 719 #define FTM_DEADTIME_DTPS_WIDTH (2U) 720 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 721 722 #define FTM_DEADTIME_DTVALEX_MASK (0xF0000U) 723 #define FTM_DEADTIME_DTVALEX_SHIFT (16U) 724 #define FTM_DEADTIME_DTVALEX_WIDTH (4U) 725 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK) 726 /*! @} */ 727 728 /*! @name EXTTRIG - FTM External Trigger */ 729 /*! @{ */ 730 731 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 732 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 733 #define FTM_EXTTRIG_CH2TRIG_WIDTH (1U) 734 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 735 736 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 737 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 738 #define FTM_EXTTRIG_CH3TRIG_WIDTH (1U) 739 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 740 741 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 742 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 743 #define FTM_EXTTRIG_CH4TRIG_WIDTH (1U) 744 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 745 746 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 747 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 748 #define FTM_EXTTRIG_CH5TRIG_WIDTH (1U) 749 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 750 751 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 752 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 753 #define FTM_EXTTRIG_CH0TRIG_WIDTH (1U) 754 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 755 756 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 757 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 758 #define FTM_EXTTRIG_CH1TRIG_WIDTH (1U) 759 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 760 761 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 762 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 763 #define FTM_EXTTRIG_INITTRIGEN_WIDTH (1U) 764 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 765 766 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 767 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 768 #define FTM_EXTTRIG_TRIGF_WIDTH (1U) 769 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 770 771 #define FTM_EXTTRIG_CH6TRIG_MASK (0x100U) 772 #define FTM_EXTTRIG_CH6TRIG_SHIFT (8U) 773 #define FTM_EXTTRIG_CH6TRIG_WIDTH (1U) 774 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK) 775 776 #define FTM_EXTTRIG_CH7TRIG_MASK (0x200U) 777 #define FTM_EXTTRIG_CH7TRIG_SHIFT (9U) 778 #define FTM_EXTTRIG_CH7TRIG_WIDTH (1U) 779 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK) 780 /*! @} */ 781 782 /*! @name POL - Channels Polarity */ 783 /*! @{ */ 784 785 #define FTM_POL_POL0_MASK (0x1U) 786 #define FTM_POL_POL0_SHIFT (0U) 787 #define FTM_POL_POL0_WIDTH (1U) 788 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 789 790 #define FTM_POL_POL1_MASK (0x2U) 791 #define FTM_POL_POL1_SHIFT (1U) 792 #define FTM_POL_POL1_WIDTH (1U) 793 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 794 795 #define FTM_POL_POL2_MASK (0x4U) 796 #define FTM_POL_POL2_SHIFT (2U) 797 #define FTM_POL_POL2_WIDTH (1U) 798 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 799 800 #define FTM_POL_POL3_MASK (0x8U) 801 #define FTM_POL_POL3_SHIFT (3U) 802 #define FTM_POL_POL3_WIDTH (1U) 803 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 804 805 #define FTM_POL_POL4_MASK (0x10U) 806 #define FTM_POL_POL4_SHIFT (4U) 807 #define FTM_POL_POL4_WIDTH (1U) 808 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 809 810 #define FTM_POL_POL5_MASK (0x20U) 811 #define FTM_POL_POL5_SHIFT (5U) 812 #define FTM_POL_POL5_WIDTH (1U) 813 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 814 815 #define FTM_POL_POL6_MASK (0x40U) 816 #define FTM_POL_POL6_SHIFT (6U) 817 #define FTM_POL_POL6_WIDTH (1U) 818 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 819 820 #define FTM_POL_POL7_MASK (0x80U) 821 #define FTM_POL_POL7_SHIFT (7U) 822 #define FTM_POL_POL7_WIDTH (1U) 823 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 824 /*! @} */ 825 826 /*! @name FMS - Fault Mode Status */ 827 /*! @{ */ 828 829 #define FTM_FMS_FAULTF0_MASK (0x1U) 830 #define FTM_FMS_FAULTF0_SHIFT (0U) 831 #define FTM_FMS_FAULTF0_WIDTH (1U) 832 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 833 834 #define FTM_FMS_FAULTF1_MASK (0x2U) 835 #define FTM_FMS_FAULTF1_SHIFT (1U) 836 #define FTM_FMS_FAULTF1_WIDTH (1U) 837 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 838 839 #define FTM_FMS_FAULTF2_MASK (0x4U) 840 #define FTM_FMS_FAULTF2_SHIFT (2U) 841 #define FTM_FMS_FAULTF2_WIDTH (1U) 842 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 843 844 #define FTM_FMS_FAULTF3_MASK (0x8U) 845 #define FTM_FMS_FAULTF3_SHIFT (3U) 846 #define FTM_FMS_FAULTF3_WIDTH (1U) 847 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 848 849 #define FTM_FMS_FAULTIN_MASK (0x20U) 850 #define FTM_FMS_FAULTIN_SHIFT (5U) 851 #define FTM_FMS_FAULTIN_WIDTH (1U) 852 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 853 854 #define FTM_FMS_WPEN_MASK (0x40U) 855 #define FTM_FMS_WPEN_SHIFT (6U) 856 #define FTM_FMS_WPEN_WIDTH (1U) 857 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 858 859 #define FTM_FMS_FAULTF_MASK (0x80U) 860 #define FTM_FMS_FAULTF_SHIFT (7U) 861 #define FTM_FMS_FAULTF_WIDTH (1U) 862 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 863 /*! @} */ 864 865 /*! @name FILTER - Input Capture Filter Control */ 866 /*! @{ */ 867 868 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 869 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 870 #define FTM_FILTER_CH0FVAL_WIDTH (4U) 871 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 872 873 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 874 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 875 #define FTM_FILTER_CH1FVAL_WIDTH (4U) 876 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 877 878 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 879 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 880 #define FTM_FILTER_CH2FVAL_WIDTH (4U) 881 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 882 883 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 884 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 885 #define FTM_FILTER_CH3FVAL_WIDTH (4U) 886 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 887 /*! @} */ 888 889 /*! @name FLTCTRL - Fault Control */ 890 /*! @{ */ 891 892 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 893 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 894 #define FTM_FLTCTRL_FAULT0EN_WIDTH (1U) 895 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 896 897 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 898 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 899 #define FTM_FLTCTRL_FAULT1EN_WIDTH (1U) 900 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 901 902 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 903 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 904 #define FTM_FLTCTRL_FAULT2EN_WIDTH (1U) 905 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 906 907 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 908 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 909 #define FTM_FLTCTRL_FAULT3EN_WIDTH (1U) 910 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 911 912 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 913 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 914 #define FTM_FLTCTRL_FFLTR0EN_WIDTH (1U) 915 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 916 917 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 918 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 919 #define FTM_FLTCTRL_FFLTR1EN_WIDTH (1U) 920 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 921 922 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 923 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 924 #define FTM_FLTCTRL_FFLTR2EN_WIDTH (1U) 925 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 926 927 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 928 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 929 #define FTM_FLTCTRL_FFLTR3EN_WIDTH (1U) 930 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 931 932 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 933 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 934 #define FTM_FLTCTRL_FFVAL_WIDTH (4U) 935 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 936 937 #define FTM_FLTCTRL_FSTATE_MASK (0x8000U) 938 #define FTM_FLTCTRL_FSTATE_SHIFT (15U) 939 #define FTM_FLTCTRL_FSTATE_WIDTH (1U) 940 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK) 941 /*! @} */ 942 943 /*! @name QDCTRL - Quadrature Decoder Control And Status */ 944 /*! @{ */ 945 946 #define FTM_QDCTRL_QUADEN_MASK (0x1U) 947 #define FTM_QDCTRL_QUADEN_SHIFT (0U) 948 #define FTM_QDCTRL_QUADEN_WIDTH (1U) 949 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) 950 951 #define FTM_QDCTRL_TOFDIR_MASK (0x2U) 952 #define FTM_QDCTRL_TOFDIR_SHIFT (1U) 953 #define FTM_QDCTRL_TOFDIR_WIDTH (1U) 954 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) 955 956 #define FTM_QDCTRL_QUADIR_MASK (0x4U) 957 #define FTM_QDCTRL_QUADIR_SHIFT (2U) 958 #define FTM_QDCTRL_QUADIR_WIDTH (1U) 959 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) 960 961 #define FTM_QDCTRL_QUADMODE_MASK (0x8U) 962 #define FTM_QDCTRL_QUADMODE_SHIFT (3U) 963 #define FTM_QDCTRL_QUADMODE_WIDTH (1U) 964 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) 965 966 #define FTM_QDCTRL_PHBPOL_MASK (0x10U) 967 #define FTM_QDCTRL_PHBPOL_SHIFT (4U) 968 #define FTM_QDCTRL_PHBPOL_WIDTH (1U) 969 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) 970 971 #define FTM_QDCTRL_PHAPOL_MASK (0x20U) 972 #define FTM_QDCTRL_PHAPOL_SHIFT (5U) 973 #define FTM_QDCTRL_PHAPOL_WIDTH (1U) 974 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) 975 976 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) 977 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) 978 #define FTM_QDCTRL_PHBFLTREN_WIDTH (1U) 979 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) 980 981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) 982 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) 983 #define FTM_QDCTRL_PHAFLTREN_WIDTH (1U) 984 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) 985 /*! @} */ 986 987 /*! @name CONF - Configuration */ 988 /*! @{ */ 989 990 #define FTM_CONF_LDFQ_MASK (0x1FU) 991 #define FTM_CONF_LDFQ_SHIFT (0U) 992 #define FTM_CONF_LDFQ_WIDTH (5U) 993 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK) 994 995 #define FTM_CONF_BDMMODE_MASK (0xC0U) 996 #define FTM_CONF_BDMMODE_SHIFT (6U) 997 #define FTM_CONF_BDMMODE_WIDTH (2U) 998 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 999 1000 #define FTM_CONF_GTBEEN_MASK (0x200U) 1001 #define FTM_CONF_GTBEEN_SHIFT (9U) 1002 #define FTM_CONF_GTBEEN_WIDTH (1U) 1003 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 1004 1005 #define FTM_CONF_GTBEOUT_MASK (0x400U) 1006 #define FTM_CONF_GTBEOUT_SHIFT (10U) 1007 #define FTM_CONF_GTBEOUT_WIDTH (1U) 1008 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 1009 1010 #define FTM_CONF_ITRIGR_MASK (0x800U) 1011 #define FTM_CONF_ITRIGR_SHIFT (11U) 1012 #define FTM_CONF_ITRIGR_WIDTH (1U) 1013 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK) 1014 /*! @} */ 1015 1016 /*! @name FLTPOL - FTM Fault Input Polarity */ 1017 /*! @{ */ 1018 1019 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 1020 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 1021 #define FTM_FLTPOL_FLT0POL_WIDTH (1U) 1022 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 1023 1024 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 1025 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 1026 #define FTM_FLTPOL_FLT1POL_WIDTH (1U) 1027 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 1028 1029 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 1030 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 1031 #define FTM_FLTPOL_FLT2POL_WIDTH (1U) 1032 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 1033 1034 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 1035 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 1036 #define FTM_FLTPOL_FLT3POL_WIDTH (1U) 1037 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 1038 /*! @} */ 1039 1040 /*! @name SYNCONF - Synchronization Configuration */ 1041 /*! @{ */ 1042 1043 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 1044 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 1045 #define FTM_SYNCONF_HWTRIGMODE_WIDTH (1U) 1046 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 1047 1048 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 1049 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 1050 #define FTM_SYNCONF_CNTINC_WIDTH (1U) 1051 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 1052 1053 #define FTM_SYNCONF_INVC_MASK (0x10U) 1054 #define FTM_SYNCONF_INVC_SHIFT (4U) 1055 #define FTM_SYNCONF_INVC_WIDTH (1U) 1056 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 1057 1058 #define FTM_SYNCONF_SWOC_MASK (0x20U) 1059 #define FTM_SYNCONF_SWOC_SHIFT (5U) 1060 #define FTM_SYNCONF_SWOC_WIDTH (1U) 1061 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 1062 1063 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 1064 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 1065 #define FTM_SYNCONF_SYNCMODE_WIDTH (1U) 1066 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 1067 1068 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 1069 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 1070 #define FTM_SYNCONF_SWRSTCNT_WIDTH (1U) 1071 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 1072 1073 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 1074 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 1075 #define FTM_SYNCONF_SWWRBUF_WIDTH (1U) 1076 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 1077 1078 #define FTM_SYNCONF_SWOM_MASK (0x400U) 1079 #define FTM_SYNCONF_SWOM_SHIFT (10U) 1080 #define FTM_SYNCONF_SWOM_WIDTH (1U) 1081 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 1082 1083 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 1084 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 1085 #define FTM_SYNCONF_SWINVC_WIDTH (1U) 1086 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 1087 1088 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 1089 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 1090 #define FTM_SYNCONF_SWSOC_WIDTH (1U) 1091 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 1092 1093 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 1094 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 1095 #define FTM_SYNCONF_HWRSTCNT_WIDTH (1U) 1096 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 1097 1098 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 1099 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 1100 #define FTM_SYNCONF_HWWRBUF_WIDTH (1U) 1101 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 1102 1103 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 1104 #define FTM_SYNCONF_HWOM_SHIFT (18U) 1105 #define FTM_SYNCONF_HWOM_WIDTH (1U) 1106 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 1107 1108 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 1109 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 1110 #define FTM_SYNCONF_HWINVC_WIDTH (1U) 1111 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 1112 1113 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 1114 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 1115 #define FTM_SYNCONF_HWSOC_WIDTH (1U) 1116 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 1117 /*! @} */ 1118 1119 /*! @name INVCTRL - FTM Inverting Control */ 1120 /*! @{ */ 1121 1122 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 1123 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 1124 #define FTM_INVCTRL_INV0EN_WIDTH (1U) 1125 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 1126 1127 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 1128 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 1129 #define FTM_INVCTRL_INV1EN_WIDTH (1U) 1130 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 1131 1132 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 1133 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 1134 #define FTM_INVCTRL_INV2EN_WIDTH (1U) 1135 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 1136 1137 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 1138 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 1139 #define FTM_INVCTRL_INV3EN_WIDTH (1U) 1140 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 1141 /*! @} */ 1142 1143 /*! @name SWOCTRL - FTM Software Output Control */ 1144 /*! @{ */ 1145 1146 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 1147 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 1148 #define FTM_SWOCTRL_CH0OC_WIDTH (1U) 1149 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 1150 1151 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 1152 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 1153 #define FTM_SWOCTRL_CH1OC_WIDTH (1U) 1154 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 1155 1156 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 1157 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 1158 #define FTM_SWOCTRL_CH2OC_WIDTH (1U) 1159 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 1160 1161 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 1162 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 1163 #define FTM_SWOCTRL_CH3OC_WIDTH (1U) 1164 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 1165 1166 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 1167 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 1168 #define FTM_SWOCTRL_CH4OC_WIDTH (1U) 1169 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 1170 1171 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 1172 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 1173 #define FTM_SWOCTRL_CH5OC_WIDTH (1U) 1174 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 1175 1176 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 1177 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 1178 #define FTM_SWOCTRL_CH6OC_WIDTH (1U) 1179 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 1180 1181 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 1182 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 1183 #define FTM_SWOCTRL_CH7OC_WIDTH (1U) 1184 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 1185 1186 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 1187 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 1188 #define FTM_SWOCTRL_CH0OCV_WIDTH (1U) 1189 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 1190 1191 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 1192 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 1193 #define FTM_SWOCTRL_CH1OCV_WIDTH (1U) 1194 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 1195 1196 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 1197 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 1198 #define FTM_SWOCTRL_CH2OCV_WIDTH (1U) 1199 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 1200 1201 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 1202 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 1203 #define FTM_SWOCTRL_CH3OCV_WIDTH (1U) 1204 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 1205 1206 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 1207 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 1208 #define FTM_SWOCTRL_CH4OCV_WIDTH (1U) 1209 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 1210 1211 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 1212 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 1213 #define FTM_SWOCTRL_CH5OCV_WIDTH (1U) 1214 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 1215 1216 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 1217 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 1218 #define FTM_SWOCTRL_CH6OCV_WIDTH (1U) 1219 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 1220 1221 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 1222 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 1223 #define FTM_SWOCTRL_CH7OCV_WIDTH (1U) 1224 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 1225 /*! @} */ 1226 1227 /*! @name PWMLOAD - FTM PWM Load */ 1228 /*! @{ */ 1229 1230 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 1231 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 1232 #define FTM_PWMLOAD_CH0SEL_WIDTH (1U) 1233 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 1234 1235 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 1236 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 1237 #define FTM_PWMLOAD_CH1SEL_WIDTH (1U) 1238 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 1239 1240 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 1241 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 1242 #define FTM_PWMLOAD_CH2SEL_WIDTH (1U) 1243 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 1244 1245 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 1246 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 1247 #define FTM_PWMLOAD_CH3SEL_WIDTH (1U) 1248 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 1249 1250 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 1251 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 1252 #define FTM_PWMLOAD_CH4SEL_WIDTH (1U) 1253 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 1254 1255 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 1256 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 1257 #define FTM_PWMLOAD_CH5SEL_WIDTH (1U) 1258 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 1259 1260 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 1261 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 1262 #define FTM_PWMLOAD_CH6SEL_WIDTH (1U) 1263 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 1264 1265 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 1266 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 1267 #define FTM_PWMLOAD_CH7SEL_WIDTH (1U) 1268 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 1269 1270 #define FTM_PWMLOAD_HCSEL_MASK (0x100U) 1271 #define FTM_PWMLOAD_HCSEL_SHIFT (8U) 1272 #define FTM_PWMLOAD_HCSEL_WIDTH (1U) 1273 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK) 1274 1275 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 1276 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 1277 #define FTM_PWMLOAD_LDOK_WIDTH (1U) 1278 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 1279 1280 #define FTM_PWMLOAD_GLEN_MASK (0x400U) 1281 #define FTM_PWMLOAD_GLEN_SHIFT (10U) 1282 #define FTM_PWMLOAD_GLEN_WIDTH (1U) 1283 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK) 1284 1285 #define FTM_PWMLOAD_GLDOK_MASK (0x800U) 1286 #define FTM_PWMLOAD_GLDOK_SHIFT (11U) 1287 #define FTM_PWMLOAD_GLDOK_WIDTH (1U) 1288 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK) 1289 /*! @} */ 1290 1291 /*! @name HCR - Half Cycle Register */ 1292 /*! @{ */ 1293 1294 #define FTM_HCR_HCVAL_MASK (0xFFFFU) 1295 #define FTM_HCR_HCVAL_SHIFT (0U) 1296 #define FTM_HCR_HCVAL_WIDTH (16U) 1297 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK) 1298 /*! @} */ 1299 1300 /*! @name PAIR0DEADTIME - Pair 0 Deadtime Configuration */ 1301 /*! @{ */ 1302 1303 #define FTM_PAIR0DEADTIME_DTVAL_MASK (0x3FU) 1304 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT (0U) 1305 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH (6U) 1306 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTVAL_SHIFT)) & FTM_PAIR0DEADTIME_DTVAL_MASK) 1307 1308 #define FTM_PAIR0DEADTIME_DTPS_MASK (0xC0U) 1309 #define FTM_PAIR0DEADTIME_DTPS_SHIFT (6U) 1310 #define FTM_PAIR0DEADTIME_DTPS_WIDTH (2U) 1311 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTPS_SHIFT)) & FTM_PAIR0DEADTIME_DTPS_MASK) 1312 1313 #define FTM_PAIR0DEADTIME_DTVALEX_MASK (0xF0000U) 1314 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT (16U) 1315 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH (4U) 1316 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR0DEADTIME_DTVALEX_MASK) 1317 /*! @} */ 1318 1319 /*! @name PAIR1DEADTIME - Pair 1 Deadtime Configuration */ 1320 /*! @{ */ 1321 1322 #define FTM_PAIR1DEADTIME_DTVAL_MASK (0x3FU) 1323 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT (0U) 1324 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH (6U) 1325 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTVAL_SHIFT)) & FTM_PAIR1DEADTIME_DTVAL_MASK) 1326 1327 #define FTM_PAIR1DEADTIME_DTPS_MASK (0xC0U) 1328 #define FTM_PAIR1DEADTIME_DTPS_SHIFT (6U) 1329 #define FTM_PAIR1DEADTIME_DTPS_WIDTH (2U) 1330 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTPS_SHIFT)) & FTM_PAIR1DEADTIME_DTPS_MASK) 1331 1332 #define FTM_PAIR1DEADTIME_DTVALEX_MASK (0xF0000U) 1333 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT (16U) 1334 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH (4U) 1335 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR1DEADTIME_DTVALEX_MASK) 1336 /*! @} */ 1337 1338 /*! @name PAIR2DEADTIME - Pair 2 Deadtime Configuration */ 1339 /*! @{ */ 1340 1341 #define FTM_PAIR2DEADTIME_DTVAL_MASK (0x3FU) 1342 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT (0U) 1343 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH (6U) 1344 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTVAL_SHIFT)) & FTM_PAIR2DEADTIME_DTVAL_MASK) 1345 1346 #define FTM_PAIR2DEADTIME_DTPS_MASK (0xC0U) 1347 #define FTM_PAIR2DEADTIME_DTPS_SHIFT (6U) 1348 #define FTM_PAIR2DEADTIME_DTPS_WIDTH (2U) 1349 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTPS_SHIFT)) & FTM_PAIR2DEADTIME_DTPS_MASK) 1350 1351 #define FTM_PAIR2DEADTIME_DTVALEX_MASK (0xF0000U) 1352 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT (16U) 1353 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH (4U) 1354 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR2DEADTIME_DTVALEX_MASK) 1355 /*! @} */ 1356 1357 /*! @name PAIR3DEADTIME - Pair 3 Deadtime Configuration */ 1358 /*! @{ */ 1359 1360 #define FTM_PAIR3DEADTIME_DTVAL_MASK (0x3FU) 1361 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT (0U) 1362 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH (6U) 1363 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTVAL_SHIFT)) & FTM_PAIR3DEADTIME_DTVAL_MASK) 1364 1365 #define FTM_PAIR3DEADTIME_DTPS_MASK (0xC0U) 1366 #define FTM_PAIR3DEADTIME_DTPS_SHIFT (6U) 1367 #define FTM_PAIR3DEADTIME_DTPS_WIDTH (2U) 1368 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTPS_SHIFT)) & FTM_PAIR3DEADTIME_DTPS_MASK) 1369 1370 #define FTM_PAIR3DEADTIME_DTVALEX_MASK (0xF0000U) 1371 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT (16U) 1372 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH (4U) 1373 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR3DEADTIME_DTVALEX_MASK) 1374 /*! @} */ 1375 1376 /*! @name MOD_MIRROR - Mirror of Modulo Value */ 1377 /*! @{ */ 1378 1379 #define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U) 1380 #define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U) 1381 #define FTM_MOD_MIRROR_FRACMOD_WIDTH (5U) 1382 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK) 1383 1384 #define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U) 1385 #define FTM_MOD_MIRROR_MOD_SHIFT (16U) 1386 #define FTM_MOD_MIRROR_MOD_WIDTH (16U) 1387 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK) 1388 /*! @} */ 1389 1390 /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */ 1391 /*! @{ */ 1392 1393 #define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U) 1394 #define FTM_CV_MIRROR_FRACVAL_SHIFT (11U) 1395 #define FTM_CV_MIRROR_FRACVAL_WIDTH (5U) 1396 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK) 1397 1398 #define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U) 1399 #define FTM_CV_MIRROR_VAL_SHIFT (16U) 1400 #define FTM_CV_MIRROR_VAL_WIDTH (16U) 1401 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK) 1402 /*! @} */ 1403 1404 /*! 1405 * @} 1406 */ /* end of group FTM_Register_Masks */ 1407 1408 /*! 1409 * @} 1410 */ /* end of group FTM_Peripheral_Access_Layer */ 1411 1412 #endif /* #if !defined(S32K142_FTM_H_) */ 1413
