Searched refs:CLK_CTL0_PSCCTL3 (Results 1 – 6 of 6) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/ |
| D | fsl_clock.h | 448 #define CLK_CTL0_PSCCTL3 3 macro
593 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 5), /*!< Clock gate name: PINT0*/
594 …kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 10), /*!< Clock gate name: PMUX_CMPT_SPL…
596 kCLOCK_Freqme0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 8), /*!< Clock gate name: FREQME0*/
597 kCLOCK_SafoSgi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 12), /*!< Clock gate name: SAFO_SGI*/
598 kCLOCK_Trace = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 13), /*!< Clock gate name: TRACE*/
599 kCLOCK_Prince0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 15), /*!< Clock gate name: PRINCE0*/
600 kCLOCK_Prince1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 16), /*!< Clock gate name: PRINCE1*/
601 … kCLOCK_PrinceExe = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 17), /*!< Clock gate name: PRINCE_EXE*/
602 …kCLOCK_Syspm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 18), /*!< Clock gate name: CMX_PERFMON0*/
[all …]
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| D | fsl_clock.c | 73 case CLK_CTL0_PSCCTL3: in CLOCK_EnableClock()
211 case CLK_CTL0_PSCCTL3: in CLOCK_DisableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/ |
| D | fsl_clock.h | 448 #define CLK_CTL0_PSCCTL3 3 macro
593 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 5), /*!< Clock gate name: PINT0*/
594 …kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 10), /*!< Clock gate name: PMUX_CMPT_SPL…
596 kCLOCK_Freqme0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 8), /*!< Clock gate name: FREQME0*/
597 kCLOCK_SafoSgi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 12), /*!< Clock gate name: SAFO_SGI*/
598 kCLOCK_Trace = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 13), /*!< Clock gate name: TRACE*/
599 kCLOCK_Prince0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 15), /*!< Clock gate name: PRINCE0*/
600 kCLOCK_Prince1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 16), /*!< Clock gate name: PRINCE1*/
601 … kCLOCK_PrinceExe = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 17), /*!< Clock gate name: PRINCE_EXE*/
602 …kCLOCK_Syspm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 18), /*!< Clock gate name: CMX_PERFMON0*/
[all …]
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| D | fsl_clock.c | 73 case CLK_CTL0_PSCCTL3: in CLOCK_EnableClock()
211 case CLK_CTL0_PSCCTL3: in CLOCK_DisableClock()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/ |
| D | fsl_clock.h | 448 #define CLK_CTL0_PSCCTL3 3 macro
593 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 5), /*!< Clock gate name: PINT0*/
594 …kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 10), /*!< Clock gate name: PMUX_CMPT_SPL…
596 kCLOCK_Freqme0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 8), /*!< Clock gate name: FREQME0*/
597 kCLOCK_SafoSgi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 12), /*!< Clock gate name: SAFO_SGI*/
598 kCLOCK_Trace = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 13), /*!< Clock gate name: TRACE*/
599 kCLOCK_Prince0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 15), /*!< Clock gate name: PRINCE0*/
600 kCLOCK_Prince1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 16), /*!< Clock gate name: PRINCE1*/
601 … kCLOCK_PrinceExe = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 17), /*!< Clock gate name: PRINCE_EXE*/
602 …kCLOCK_Syspm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 18), /*!< Clock gate name: CMX_PERFMON0*/
[all …]
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| D | fsl_clock.c | 73 case CLK_CTL0_PSCCTL3: in CLOCK_EnableClock()
211 case CLK_CTL0_PSCCTL3: in CLOCK_DisableClock()
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