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Searched refs:CH_INT (Results 1 – 25 of 96) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/
Dfsl_edma_core.h126 #define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_…
127 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) …
175 … __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ member
Dfsl_edma.c2520 if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_HandleIRQ()
2522 handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
2641 if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/
Dfsl_edma_core.h126 #define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_…
127 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) …
175 … __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ member
Dfsl_edma.c2527 if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_HandleIRQ()
2529 handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
2648 if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/
Dfsl_ad_edma.c779 retval |= (((base->CH[channel].CH_INT & DMA_CH_INT_INT_MASK) >> DMA_CH_INT_INT_SHIFT) << 2U); in EDMA_AD_GetChannelStatusFlags()
809 base->CH[channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_AD_ClearChannelStatusFlags()
1372 handle->base->CH[handle->channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_AD_HandleIRQ()
Dfsl_edma.c807 retval |= (((base->CH[channel].CH_INT & DMA_CH_INT_INT_MASK) >> DMA_CH_INT_INT_SHIFT) << 2U); in EDMA_GetChannelStatusFlags()
837 base->CH[channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_ClearChannelStatusFlags()
1423 handle->base->CH[handle->channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_EDMA3_TCD.h79 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8,… member
DS32Z2_FEED_DMA_TCD.h79 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8,… member
DS32Z2_RESULT_DMA_TCD.h79 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8,… member
DS32Z2_EDMA4_TCD.h79 …__IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array off… member
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2418 … __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ member
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h1889 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8,… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h3932 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h3932 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h3932 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h3932 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h6143 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h6898 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h27833 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
28709 …__IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array off… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h27833 …__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10… member
28709 …__IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array off… member

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