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Searched refs:CH_CSR (Results 1 – 25 of 104) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/
Dfsl_ad_edma.c238 base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_AD_ResetChannel()
401 …base->CH[channel].CH_CSR = (base->CH[channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_EEI_M… in EDMA_AD_EnableChannelInterrupts()
426 …base->CH[channel].CH_CSR = (base->CH[channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_EEI_… in EDMA_AD_DisableChannelInterrupts()
738 if ((DMA_CH_CSR_DONE_MASK & base->CH[channel].CH_CSR) != 0U) in EDMA_AD_GetRemainingMajorLoopCount()
775 retval |= ((base->CH[channel].CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT); in EDMA_AD_GetChannelStatusFlags()
799 base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_AD_ClearChannelStatusFlags()
1244 handle->base->CH[handle->channel].CH_CSR = in EDMA_AD_SubmitTransfer()
1245 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_AD_SubmitTransfer()
1267 handle->base->CH[handle->channel].CH_CSR = in EDMA_AD_StartTransfer()
1268 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_AD_StartTransfer()
[all …]
Dfsl_edma.c269 base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_ResetChannel()
429 …base->CH[channel].CH_CSR = (base->CH[channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_EEI_M… in EDMA_EnableChannelInterrupts()
454 …base->CH[channel].CH_CSR = (base->CH[channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_EEI_… in EDMA_DisableChannelInterrupts()
766 if ((DMA_CH_CSR_DONE_MASK & base->CH[channel].CH_CSR) != 0U) in EDMA_GetRemainingMajorLoopCount()
803 retval |= ((base->CH[channel].CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT); in EDMA_GetChannelStatusFlags()
827 base->CH[channel].CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_ClearChannelStatusFlags()
1285 handle->base->CH[handle->channel].CH_CSR = in EDMA_SubmitTransfer()
1286 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_SubmitTransfer()
1308 handle->base->CH[handle->channel].CH_CSR = in EDMA_StartTransfer()
1309 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
[all …]
Dfsl_ad_edma.h516 base->CH[channel].CH_CSR = in EDMA_AD_EnableAsyncRequest()
517 …(base->CH[channel].CH_CSR & (~(DMA_CH_CSR_EARQ_MASK | DMA_CH_CSR_DONE_MASK))) | DMA_CH_CSR_EARQ(en… in EDMA_AD_EnableAsyncRequest()
737 base->CH[channel].CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_AD_EnableChannelRequest()
752 base->CH[channel].CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_AD_DisableChannelRequest()
Dfsl_edma.h517 base->CH[channel].CH_CSR = in EDMA_EnableAsyncRequest()
518 …(base->CH[channel].CH_CSR & (~(DMA_CH_CSR_EARQ_MASK | DMA_CH_CSR_DONE_MASK))) | DMA_CH_CSR_EARQ(en… in EDMA_EnableAsyncRequest()
738 base->CH[channel].CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
753 base->CH[channel].CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
Dsystem_MIMXRT1189_cm33.c196 DMA4->TCD[0].CH_CSR = 0x7; in InitCM7DMA()
200 DMA4->TCD[0].CH_CSR = 0x40000006; in InitCM7DMA()
202 while ((DMA4->TCD[0].CH_CSR & DMA4_CH_CSR_DONE_MASK) == 0UL) in InitCM7DMA()
206 DMA4->TCD[0].CH_CSR = (1UL << DMA4_CH_CSR_DONE_SHIFT); in InitCM7DMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
Dsystem_MIMXRT1187_cm33.c207 DMA4->TCD[0].CH_CSR = 0x7; in InitCM7DMA()
211 DMA4->TCD[0].CH_CSR = 0x40000006; in InitCM7DMA()
213 while ((DMA4->TCD[0].CH_CSR & DMA4_CH_CSR_DONE_MASK) == 0UL) in InitCM7DMA()
217 DMA4->TCD[0].CH_CSR = (1UL << DMA4_CH_CSR_DONE_SHIFT); in InitCM7DMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/
Dfsl_edma.h630 EDMA_CHANNEL_BASE(base, channel)->CH_CSR = in EDMA_SetChannelSignExtension()
631 (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | in EDMA_SetChannelSignExtension()
652 EDMA_CHANNEL_BASE(base, channel)->CH_CSR = in EDMA_SetChannelSwapSize()
653 (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | in EDMA_SetChannelSwapSize()
995 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EARQ_MASK; in EDMA_EnableAsyncRequest()
999 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EARQ_MASK; in EDMA_EnableAsyncRequest()
1459 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
1478 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
Dfsl_edma_core.h115 #define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CS…
117 ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT)
119 #define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_C…
120 #define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_…
173 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 … member
Dfsl_edma.c1914 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitTransferTCD()
2102 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitTransfer()
2294 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitLoopTransfer()
2406 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2411 if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) in EDMA_StartTransfer()
2414 if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || in EDMA_StartTransfer()
2421 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2442 …handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_E… in EDMA_StopTransfer()
2511 transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); in EDMA_HandleIRQ()
2594 handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_HandleIRQ()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/
Dfsl_edma.h630 EDMA_CHANNEL_BASE(base, channel)->CH_CSR = in EDMA_SetChannelSignExtension()
631 (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | in EDMA_SetChannelSignExtension()
652 EDMA_CHANNEL_BASE(base, channel)->CH_CSR = in EDMA_SetChannelSwapSize()
653 (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | in EDMA_SetChannelSwapSize()
995 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EARQ_MASK; in EDMA_EnableAsyncRequest()
999 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EARQ_MASK; in EDMA_EnableAsyncRequest()
1459 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
1478 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
Dfsl_edma_core.h115 #define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CS…
117 ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT)
119 #define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_C…
120 #define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_…
173 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 … member
Dfsl_edma.c1921 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitTransferTCD()
2109 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitTransfer()
2301 if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || in EDMA_SubmitLoopTransfer()
2413 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2418 if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) in EDMA_StartTransfer()
2421 if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || in EDMA_StartTransfer()
2428 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2449 …handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_E… in EDMA_StopTransfer()
2518 transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); in EDMA_HandleIRQ()
2601 handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; in EDMA_HandleIRQ()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/jlinkscript/
Devkmimxrt1180_cm33.jlinkscript377 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
384 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
388 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
393 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR
403 _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR
409 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
411 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
Devkmimxrt1180_cm7.jlinkscript377 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
384 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
388 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
393 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR
403 _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR
409 reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR
411 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_EDMA3_TCD.h77 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
DS32Z2_FEED_DMA_TCD.h77 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
DS32Z2_RESULT_DMA_TCD.h77 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
DS32Z2_EDMA4_TCD.h77 …__IO uint32_t CH_CSR; /**< Channel Control and Status Register, array o… member
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2416 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 … member
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h1887 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h3930 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h3930 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h3930 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h3930 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h6141 …__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x… member

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