1__constant U32 _INDEX_AHB_AP_CORTEX_M33       = 3;
2__constant U32 _AHB_ACC_32BIT_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0);
3__constant U32 _AHB_ACC_16BIT_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0);  // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word;
4__constant U32 _ACCESS_AP                     = 1;
5__constant U32 _CM33_CPUID                    = 0xD210;
6__constant U32 _CM7_CPUID                     = 0x0C27;
7
8unsigned int cpuID;
9
10static int _WriteViaCM33AP16(U32 Addr, U16 Data) {
11    int r;
12
13    JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24));
14    JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL,   _AHB_ACC_16BIT_AUTO_INC);
15    Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16);
16    r  = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr);
17    r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data);
18    return r;
19}
20
21static U32 _ReadViaCM33AP16(U32 Addr) {
22    U32 r;
23
24    JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24));
25    JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL,   _AHB_ACC_16BIT_AUTO_INC);
26    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr);
27    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r);
28    return r;
29}
30
31static int _WriteViaCM33AP32(U32 Addr, U32 Data) {
32    int r;
33
34    JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24));
35    JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL,   _AHB_ACC_32BIT_AUTO_INC);
36    r  = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr);
37    r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data);
38    return r;
39}
40
41static U32 _ReadViaCM33AP32(U32 Addr) {
42    int r;
43
44    JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24));
45    JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL,   _AHB_ACC_32BIT_AUTO_INC);
46    r  = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr);
47    r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r);
48    return r;
49}
50
51void _FLEXSPI1_ModuleReset()
52{
53    unsigned int reg;
54
55    reg = MEM_ReadU32(0x425E0000);  // FlexSPI1->MCR0
56    if( (reg & 0x02) == 0)  // Module Enabled
57    {
58        reg = MEM_ReadU32(0x425E0000);
59        MEM_WriteU32(0x425E0000, (reg | 0x1));
60        do
61        {
62            reg = MEM_ReadU32(0x425E0000);
63        } while ((reg & 0x1) != 0);
64    }
65}
66
67void _FLEXSPI1_WaitBusIdle()
68{
69    unsigned int reg;
70    reg = MEM_ReadU32(0x425E0000);  // FlexSPI1->MCR0
71    if( (reg & 0x02) == 0)  // Module Enabled
72    {
73        do
74        {
75            reg = MEM_ReadU32(0x425E00E0);
76        } while ((reg & 0x3) != 0x3);
77    }
78}
79
80void _FLEXSPI1_ClockInit()
81{
82    _WriteViaCM33AP32(0x54484350, 0x0);  // ROSC400M_CTRL1
83
84    // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3
85    MEM_WriteU32(0x54450A80, 0x103);     // CLOCK_ROOT[21].CONTROL, FlexSPI1
86}
87
88void _FLEXSPI1_SetPinForQuadMode(void) {
89    // Set 4 Pin Mode for JLink
90    // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS
91    MEM_WriteU32(0x42A1023C, 0x17);
92    MEM_WriteU32(0x42A10544, 0x1);
93    // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK
94    MEM_WriteU32(0x42A10240, 0x17);
95    // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B
96    MEM_WriteU32(0x42A10244, 0x17);
97    // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00
98    MEM_WriteU32(0x42A10248, 0x17);
99    // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01
100    MEM_WriteU32(0x42A1024C, 0x17);
101    // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02
102    MEM_WriteU32(0x42A10250, 0x17);
103    // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03
104    MEM_WriteU32(0x42A10254, 0x17);
105}
106
107void _FLEXSPI1_ModuleInit(void) {
108
109    unsigned int reg;
110    reg = MEM_ReadU32(0x425E0000);
111    MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD));
112
113    //FLEXSPI1->MCR0 = 0xFFFF8010;
114    MEM_WriteU32(0x425E0000, 0xFFFF8010);
115    //FLEXSPI1->MCR2 = 0x200001F7;
116    MEM_WriteU32(0x425E0008, 0x200001F7);
117    //FLEXSPI1->AHBCR = 0x78;
118    MEM_WriteU32(0x425E000C, 0x78);
119
120    //FLEXSPI1->FLSHCR0[0] = 0x00004000;
121    MEM_WriteU32(0x425E0060, 0x00004000);
122
123
124    //FLEXSPI1->FLSHCR4 = 0xC3;
125    MEM_WriteU32(0x425E0094, 0xC3);
126    //FLEXSPI1->IPRXFCR = 0x1C;
127    MEM_WriteU32(0x425E00B8, 0x1C);
128
129    //FLEXSPI1->LUTKEY = 0x5AF05AF0UL;
130    MEM_WriteU32(0x425E0018, 0x5AF05AF0);
131    //FLEXSPI1->LUTCR  = 0x02;
132    MEM_WriteU32(0x425E001C, 0x02);
133
134    //FLEXSPI1->LUT[0] = 0x0A1804EB;  // AHB Quad Read Change to use Fast Read Quad
135    MEM_WriteU32(0x425E0200, 0x0A1804EB);
136    //FLEXSPI1->LUT[1] = 0x26043206;
137    MEM_WriteU32(0x425E0204, 0x26043206);
138    //FLEXSPI1->LUT[2] = 0x00000000;
139    MEM_WriteU32(0x425E0208, 0x00000000);
140    //FLEXSPI1->LUT[3] = 0x00000000;
141    MEM_WriteU32(0x425E020C, 0x00000000);
142
143    //FLEXSPI1->LUT[4] = 0x00000406;  // Write Enable
144    MEM_WriteU32(0x425E0210, 0x00000406);
145    //FLEXSPI1->LUT[5] = 0x00000000;
146    MEM_WriteU32(0x425E0214, 0x00000000);
147    //FLEXSPI1->LUT[6] = 0x00000000;
148    MEM_WriteU32(0x425E0218, 0x00000000);
149    //FLEXSPI1->LUT[7] = 0x00000000;
150    MEM_WriteU32(0x425E021C, 0x00000000);
151
152    //FLEXSPI1->LUT[8] = 0x20040401;  // Wirte s1
153    MEM_WriteU32(0x425E0220, 0x20040401);
154    //FLEXSPI1->LUT[9] = 0x00000000;
155    MEM_WriteU32(0x425E0224, 0x00000000);
156    //FLEXSPI1->LUT[10] = 0x00000000;
157    MEM_WriteU32(0x425E0228, 0x00000000);
158    //FLEXSPI1->LUT[11] = 0x00000000;
159    MEM_WriteU32(0x425E022C, 0x00000000);
160
161    //FLEXSPI1->LUT[12] = 0x24040405;  // Read s1
162    MEM_WriteU32(0x425E0230, 0x24040405);
163    //FLEXSPI1->LUT[13] = 0x00000000;
164    MEM_WriteU32(0x425E0234, 0x00000000);
165    //FLEXSPI1->LUT[14] = 0x00000000;
166    MEM_WriteU32(0x425E0238, 0x00000000);
167    //FLEXSPI1->LUT[15] = 0x00000000;
168    MEM_WriteU32(0x425E023C, 0x00000000);
169
170    //FLEXSPI1->LUT[16] = 0x00000404;  // Write Disable
171    MEM_WriteU32(0x425E0240, 0x00000404);
172    //FLEXSPI1->LUT[17] = 0x00000000;
173    MEM_WriteU32(0x425E0244, 0x00000000);
174    //FLEXSPI1->LUT[18] = 0x00000000;
175    MEM_WriteU32(0x425E0248, 0x00000000);
176    //FLEXSPI1->LUT[19] = 0x00000000;
177    MEM_WriteU32(0x425E024C, 0x00000000);
178
179    //FLEXSPI1->LUT[20] = 0x20040431;  // Wirte s2
180    MEM_WriteU32(0x425E0250, 0x20040431);
181    //FLEXSPI1->LUT[21] = 0x00000000;
182    MEM_WriteU32(0x425E0254, 0x00000000);
183    //FLEXSPI1->LUT[22] = 0x00000000;
184    MEM_WriteU32(0x425E0258, 0x00000000);
185    //FLEXSPI1->LUT[23] = 0x00000000;
186    MEM_WriteU32(0x425E025C, 0x00000000);
187
188    //FLEXSPI1->LUT[24] = 0x24040435;  // Read s2
189    MEM_WriteU32(0x425E0260, 0x24040435);
190    //FLEXSPI1->LUT[25] = 0x00000000;
191    MEM_WriteU32(0x425E0264, 0x00000000);
192    //FLEXSPI1->LUT[26] = 0x00000000;
193    MEM_WriteU32(0x425E0268, 0x00000000);
194    //FLEXSPI1->LUT[27] = 0x00000000;
195    MEM_WriteU32(0x425E026C, 0x00000000);
196
197    //FLEXSPI1->LUT[28] = 0x00000450;  // Write Enable Volatile
198    MEM_WriteU32(0x425E0270, 0x00000450);
199    //FLEXSPI1->LUT[29] = 0x00000000;
200    MEM_WriteU32(0x425E0274, 0x00000000);
201    //FLEXSPI1->LUT[30] = 0x00000000;
202    MEM_WriteU32(0x425E0278, 0x00000000);
203    //FLEXSPI1->LUT[31] = 0x00000000;
204    MEM_WriteU32(0x425E027C, 0x00000000);
205
206    //FLEXSPI1->LUTKEY = 0x5AF05AF0UL;
207    MEM_WriteU32(0x425E0018, 0x5AF05AF0);
208    //FLEXSPI1->LUTCR  = 0x01;
209    MEM_WriteU32(0x425E001C, 0x01);
210}
211
212void _FLEXSPI2_ModuleReset()
213{
214    unsigned int reg;
215
216    reg = MEM_ReadU32(0x445E0000);  // FlexSPI2->MCR0
217    if( (reg & 0x02) == 0)  // Module Enabled
218    {
219        reg = MEM_ReadU32(0x445E0000);
220        MEM_WriteU32(0x445E0000, (reg | 0x1));
221        do
222        {
223            reg = MEM_ReadU32(0x445E0000);
224        } while ((reg & 0x1) != 0);
225    }
226}
227
228void _FLEXSPI2_WaitBusIdle()
229{
230    unsigned int reg;
231
232    reg = MEM_ReadU32(0x445E0000);  // FlexSPI2->MCR0
233    if( (reg & 0x02) == 0)  // Module Enabled
234    {
235        do
236        {
237            reg = MEM_ReadU32(0x445E00E0);
238        } while ((reg & 0x3) != 0x3);
239    }
240}
241
242void _FlexSPI2_SetPinForOctalMode()
243{
244    // Config IOMUX for FlexSPI2
245    MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03
246    MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02
247    MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01
248    MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00
249    MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00
250    MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01
251    MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02
252    MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03
253    MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B
254    MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS
255    MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK
256
257    //The input daisy!!
258    MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03
259    MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02
260    MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01
261    MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00
262    MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00
263    MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01
264    MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02
265    MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03
266    MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS
267    MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK
268
269    // PAD ctrl
270    MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03
271    MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02
272    MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01
273    MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00
274    MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00
275    MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01
276    MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02
277    MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03
278    MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B
279    MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS
280    MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK
281}
282
283void _FLEXSPI2_ClockInit()
284{
285    _WriteViaCM33AP32(0x54484350, 0x0);  // ROSC400M_CTRL1
286
287    // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1
288    MEM_WriteU32(0x44450B00, 0x101);     // CLOCK_ROOT[22].CONTROL, FlexSPI2
289}
290
291void _FLEXSPI2_ModuleInit()
292{
293    // Config FlexSPI2 Registers
294
295    unsigned int reg;
296    reg = MEM_ReadU32(0x445E0000);
297    MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD));
298
299    _FLEXSPI2_ModuleReset();
300
301    MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0
302    MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1
303    MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2
304    MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable
305    MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0
306    MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0
307    MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0
308    MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0
309    MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0
310    MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0
311    MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0
312    MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0
313    MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR
314    MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR
315
316    MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0
317    MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0
318    MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0
319    MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0
320
321    _FLEXSPI2_WaitBusIdle();
322
323    MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0
324    MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1
325    MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2
326
327    _FLEXSPI2_WaitBusIdle();
328
329    MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA
330    MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0
331
332    do
333    {
334        reg = MEM_ReadU32(0x445E00E8);
335    } while (0x3 != (reg & 0x3));
336    JLINK_SYS_Sleep(1);
337    // __delay(100);//100us
338
339    MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0
340    MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4
341    MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4
342    MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0
343
344    _FLEXSPI2_WaitBusIdle();
345
346    MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY
347    MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR
348    MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0]
349    MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1]
350    MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2]
351    MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3]
352    MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4]
353    MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5]
354    MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6]
355    MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7]
356    MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8]
357    MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9]
358    MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10]
359    MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11]
360    MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12]
361    MEM_WriteU32(0x445E0234, 0xA3048F10); // LUT[13]
362    MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14]
363    MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15]
364    MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16]
365    MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17]
366    MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18]
367    MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19]
368    MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY
369    MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR
370
371    _FLEXSPI2_ModuleReset();
372}
373
374void CM7_InitTCM(U32 targetAddr, U32 size) {
375    U32 reg;
376
377    reg = _ReadViaCM33AP32(0x52010000);           // DMA4->TDC[0].CH_CSR
378
379    if((reg & 0x80000000) != 0)
380    {
381        // DMA channel is active, wait it get finished
382        do
383        {
384            reg = _ReadViaCM33AP32(0x52010000);   // DMA4->TDC[0].CH_CSR
385        } while((reg & 0x40000000) == 0);
386    }
387
388    _WriteViaCM33AP32(0x52010000, 0x40000000);    // DMA4->TDC[0].CH_CSR, clear DONE flag
389
390    _WriteViaCM33AP32(0x5201002C, 0x00000000);    // DMA4->TCD[0].SLAST_SGA
391    _WriteViaCM33AP32(0x52010038, 0x00000000);    // DMA4->TCD[0].DLAST_SGA
392
393    _WriteViaCM33AP32(0x52010000, 0x40000000);    // DMA4->TCD[0].CH_CSR
394
395    _WriteViaCM33AP32(0x52010020, 0x20484000);    // DMA4->TCD[0].SADDR
396    _WriteViaCM33AP32(0x52010030, targetAddr);    // DMA4->TCD[0].DADDR
397    _WriteViaCM33AP32(0x52010028, size);          // DMA4->TCD[0].NBYTES_MLOFFNO
398    _WriteViaCM33AP16(0x52010036, 0x1);           // DMA4->TCD[0].ELINKNO
399    _WriteViaCM33AP16(0x5201003E, 0x1);           // DMA4->TCD[0].BITER_ELINKNO
400    _WriteViaCM33AP16(0x52010026, 0x0303);        // DMA4->TCD[0].ATTR
401    _WriteViaCM33AP16(0x52010024, 0x0);           // DMA4->TCD[0].SOFF
402    _WriteViaCM33AP16(0x52010034, 0x8);           // DMA4->TCD[0].DOFF
403    _WriteViaCM33AP32(0x52010000, 0x7);           // DMA4->TDC[0].CH_CSR
404    _WriteViaCM33AP16(0x5201003C, 0x8);           // DMA4->TCD[0].CSR
405    _WriteViaCM33AP16(0x5201003C, 0x9);           // DMA4->TCD[0].CSR
406
407    do
408    {
409        reg = _ReadViaCM33AP32(0x52010000);       // DMA4->TDC[0].CH_CSR
410    } while((reg & 0x40000000) == 0);
411    _WriteViaCM33AP32(0x52010000, 0x40000000);    // DMA4->TDC[0].CH_CSR, clear DONE flag
412}
413
414void CM7_KickOff(void)
415{
416    U32 reg, resp1, resp2;
417
418    reg = _ReadViaCM33AP32(0x544F0080);  // BLK_CTRL_S_AONMIX->M7_CFG
419    if((reg & 0x10) == 0)
420    {
421        JLINK_SYS_Report("CM7 is running already");
422    }
423    else
424    {
425        JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************");
426
427        // Clock Preparation
428        JLINK_SYS_Report("******** Prepare Clock *********");
429        _WriteViaCM33AP32(0x54484350, 0x0);   // ROSC400M_CTRL1
430        _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7
431
432        // Release CM7
433        _WriteViaCM33AP32(0x54460010, 0x1);  // SRC_GENERAL_REG->SCR
434
435        // DMA initialization
436        JLINK_SYS_Report("******** DMA operation *********");
437        CM7_InitTCM(0x303C0000, 0x40000);
438        CM7_InitTCM(0x30400000, 0x40000);
439
440        // Making Landing Zone
441        JLINK_SYS_Report("******** Creating Landing Zone *********");
442        _WriteViaCM33AP32(0x303C0000, 0x20020000);
443        _WriteViaCM33AP32(0x303C0004, 0x00000009);
444        _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE);
445
446        // VTOR 0x00
447        _WriteViaCM33AP32(0x544F0080, 0x0010);  // BLK_CTRL_S_AONMIX->M7_CFG
448
449        // Trigger ELE
450        JLINK_SYS_Report("******** ELE Trigger *********");
451        _WriteViaCM33AP32(0x57540200, 0x17d20106);  // MU_RT_S3MUA->TR[0]
452        resp1 = _ReadViaCM33AP32(0x57540280);  // MU_RT_S3MUA->RR[0]
453        resp2 = _ReadViaCM33AP32(0x57540284);  // MU_RT_S3MUA->RR[1]
454        JLINK_SYS_Report1("ELE RESP1 : ", resp1);
455        JLINK_SYS_Report1("ELE RESP2 : ", resp2);
456
457        // Deassert CM7 Wait
458        JLINK_SYS_Report("******** Kickoff CM7 *********");
459        _WriteViaCM33AP32(0x544F0080, 0x0);  // BLK_CTRL_S_AONMIX->M7_CFG
460    }
461}
462
463void DAP_Init(void)
464{
465    JLINK_CORESIGHT_Configure("");
466
467    CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
468    CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
469    CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
470    CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);
471    CORESIGHT_AddAP(4, CORESIGHT_APB_AP);
472    CORESIGHT_AddAP(5, CORESIGHT_APB_AP);
473    CORESIGHT_AddAP(6, CORESIGHT_APB_AP);
474
475    JLINK_SYS_Report("***************************************************");
476    if(cpuID == _CM7_CPUID)
477    {
478        CPU = CORTEX_M7;
479        CORESIGHT_IndexAHBAPToUse = 2;
480        JLINK_SYS_Report("Current core is CM7");
481    }
482    else if(cpuID == _CM33_CPUID)
483    {
484        CPU = CORTEX_M33;
485        CORESIGHT_IndexAHBAPToUse = 3;
486        JLINK_SYS_Report("Current core is CM33");
487    }
488    else
489    {
490        JLINK_SYS_Report1("Wrong CPU ID: ", cpuID);
491    }
492    JLINK_SYS_Report("***************************************************");
493}
494
495void CM33_Halt(void)
496{
497    U32 reg;
498
499    reg = (_ReadViaCM33AP32(0x54460044) >> 24) & 0x3F;  //SRC->SBMR2
500
501    if((reg == 8) || (reg == 9))  // Serial Download Mode, or Boot From Fuse
502    {
503        JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted...");
504
505        reg = _ReadViaCM33AP32(0xE000EDF0);  //DHCSR
506
507        if(0 == (reg & 0x02))
508        {
509            JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg);
510
511            _WriteViaCM33AP32(0xE000EDF0, 0xA05F0001);   // DHCSR, Enable CM33 debug control
512            _WriteViaCM33AP32(0xE000EDF0, 0xA05F0003);   // DHCSR, Halt CM33
513            reg = _ReadViaCM33AP32(0xE000EDF0);  //DHCSR
514            if(0 != (reg & 0x02))
515            {
516                JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg);
517            }
518            else
519            {
520                JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg);
521            }
522        }
523        else
524        {
525            JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg);
526        }
527    }
528    else
529    {
530        JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was...");
531    }
532}
533
534void Flash_Init() {
535    JLINK_SYS_Report("***************************************************");
536    JLINK_SYS_Report("Init Flash");
537
538    _FLEXSPI1_WaitBusIdle();
539    _FLEXSPI1_ModuleReset();
540
541    _FLEXSPI1_SetPinForQuadMode();
542    _FLEXSPI1_ClockInit();
543    _FLEXSPI1_ModuleInit();
544
545    JLINK_SYS_Report("***************************************************");
546}
547
548void HyperRAM_Init()
549{
550    JLINK_SYS_Report("***************************************************");
551    JLINK_SYS_Report("Init HyperRAM");
552
553    _FLEXSPI2_WaitBusIdle();
554    _FLEXSPI2_ModuleReset();
555
556    _FlexSPI2_SetPinForOctalMode();
557    _FLEXSPI2_ClockInit();
558    _FLEXSPI2_ModuleInit();
559
560    JLINK_SYS_Report("***************************************************");
561}
562
563void CM33_ClearNVIC(void) {
564    JLINK_SYS_Report("***************************************************");
565    JLINK_SYS_Report("Clear NVIC");
566    JLINK_SYS_Report("***************************************************");
567    JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF);
568    JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF);
569}
570
571int InitTarget(void)
572{
573    cpuID = _CM7_CPUID;
574
575    DAP_Init();
576
577    if(cpuID == _CM7_CPUID)
578    {
579        CM33_Halt();
580        CM7_KickOff();
581
582        /* Avoid to access TPIU to prevent soc hang */
583        JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X");  // Mark region as illegal
584    }
585
586    return 0;
587}
588
589int SetupTarget(void)
590{
591    return 0;
592}
593
594void ResetTarget(void) {
595    JLINK_TARGET_Halt(); // Make sure that the CPU is halted when reset is called
596}
597
598int AfterResetTarget(void)
599{
600    U32 reg;
601
602    if(cpuID == _CM33_CPUID)
603    {
604        CM33_ClearNVIC();
605    }
606
607    Flash_Init();
608    HyperRAM_Init();
609
610    return 0;
611}
612