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Searched refs:CAN_ERFCR_ERFEN_MASK (Results 1 – 25 of 44) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan_edma.c79 if (0U != (flexcanPrivateHandle->base->ERFCR & CAN_ERFCR_ERFEN_MASK)) in FLEXCAN_ReceiveFifoEDMACallback()
Dfsl_flexcan.c2440 assert((base->ERFCR & CAN_ERFCR_ERFEN_MASK) == 0U); in FLEXCAN_SetRxFifoConfig()
2589 base->ERFCR |= CAN_ERFCR_ERFEN_MASK; in FLEXCAN_SetEnhancedRxFifoConfig()
3217 if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) in FLEXCAN_ReadEnhancedRxFifo()
4235 if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) in FLEXCAN_TransferAbortReceiveEnhancedFifo()
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2263 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
2269 … CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h1770 #define CAN_ERFCR_ERFEN_MASK FLEXCAN_ERFCR_ERFEN_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h3884 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
3890 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h5540 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
5546 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h8031 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
8037 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h8013 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
8019 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h5741 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
5747 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h10327 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10333 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
DMCXN546_cm33_core1.h10327 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10333 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h10327 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10333 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
DMCXN547_cm33_core1.h10327 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10333 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h10361 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10367 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
DMCXN947_cm33_core0.h10361 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10367 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h10361 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10367 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
DMCXN946_cm33_core1.h10361 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10367 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h15147 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
15153 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h15147 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
15153 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
DMIMX9131.h10636 #define CAN_ERFCR_ERFEN_MASK (0x80000000U) macro
10642 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)

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