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Searched refs:CLK_CTL1_PSCCTL2 (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.h224 #define CLK_CTL1_PSCCTL2 5 macro
315 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
316 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
317 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
318 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
319 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
320 kCLOCK_Pmu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 6),
321 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
322 kCLOCK_Mrt = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
323 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
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Dfsl_clock.c303 case CLK_CTL1_PSCCTL2: in CLOCK_EnableClock()
362 case CLK_CTL1_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.h224 #define CLK_CTL1_PSCCTL2 5 macro
315 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
316 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
317 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
318 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
319 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
320 kCLOCK_Pmu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 6),
321 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
322 kCLOCK_Mrt = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
323 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
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Dfsl_clock.c303 case CLK_CTL1_PSCCTL2: in CLOCK_EnableClock()
362 case CLK_CTL1_PSCCTL2: in CLOCK_DisableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h263 #define CLK_CTL1_PSCCTL2 5 macro
354 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
355 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
356 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
357 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
358 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
359 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
360 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
361 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
362 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h263 #define CLK_CTL1_PSCCTL2 5 macro
354 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
355 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
356 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
357 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
358 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
359 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
360 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
361 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
362 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h311 #define CLK_CTL1_PSCCTL2 5 macro
444 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
445 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
446 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
447 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
448 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
449 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
450 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
451 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
452 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h311 #define CLK_CTL1_PSCCTL2 5 macro
444 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
445 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
446 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
447 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
448 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
449 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
450 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
451 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
452 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h311 #define CLK_CTL1_PSCCTL2 5 macro
444 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
445 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
446 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
447 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
448 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
449 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
450 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
451 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
452 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
[all …]