1 /*
2 * Copyright 2020-2024, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12 #include "fsl_reset.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configure whether driver controls clock
24 *
25 * When set to 0, peripheral drivers will enable clock in initialize function
26 * and disable clock in de-initialize function. When set to 1, peripheral
27 * driver will not control the clock, application could control the clock out of
28 * the driver.
29 *
30 * @note All drivers share this feature switcher. If it is set to 1, application
31 * should handle clock enable and disable for all drivers.
32 */
33 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
34 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
35 #endif
36
37 /*******************************************************************************
38 * Definitions
39 ******************************************************************************/
40
41 /*! @name Driver version */
42 /*@{*/
43 /*! @brief CLOCK driver version 2.1.4. */
44 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
45 /*@}*/
46
47 /* Definition for delay API in clock driver, users can redefine it to the real application. */
48 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
49 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (260000000UL)
50 #endif
51
52 /*! @brief Clock ip name array for GPIO. */
53 #define GPIO_CLOCKS \
54 { \
55 kCLOCK_HsGpio0, kCLOCK_HsGpio1 \
56 }
57
58 /*! @brief Clock ip name array for CACHE64. */
59 #define CACHE64_CLOCKS \
60 { \
61 kCLOCK_Flexspi, kCLOCK_Flexspi \
62 }
63
64 /*! @brief Clock ip name array for FLEXSPI. */
65 #define FLEXSPI_CLOCKS \
66 { \
67 kCLOCK_Flexspi \
68 }
69
70 /*! @brief Clock ip name array for FLEXCOMM. */
71 #define FLEXCOMM_CLOCKS \
72 { \
73 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
74 }
75
76 /*! @brief Clock ip name array for LPUART. */
77 #define USART_CLOCKS \
78 { \
79 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
80 }
81
82 /*! @brief Clock ip name array for I2C. */
83 #define I2C_CLOCKS \
84 { \
85 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3 \
86 }
87
88 /*! @brief Clock ip name array for SPI. */
89 #define SPI_CLOCKS \
90 { \
91 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm14 \
92 }
93
94 /*! @brief Clock ip name array for ACOMP. */
95 #define ACOMP_CLOCKS \
96 { \
97 kCLOCK_Gau \
98 }
99
100 /*! @brief Clock ip name array for ADC. */
101 #define ADC_CLOCKS \
102 { \
103 kCLOCK_Gau, kCLOCK_Gau \
104 }
105
106 /*! @brief Clock ip name array for DAC. */
107 #define DAC_CLOCKS \
108 { \
109 kCLOCK_Gau \
110 }
111
112 /*! @brief Clock ip name array for LCDIC. */
113 #define LCDIC_CLOCKS \
114 { \
115 kCLOCK_Lcdic \
116 }
117
118 /*! @brief Clock ip name array for DMA. */
119 #define DMA_CLOCKS \
120 { \
121 kCLOCK_Dma0, kCLOCK_Dma1 \
122 }
123
124 /*! @brief Clock ip name array for DMIC. */
125 #define DMIC_CLOCKS \
126 { \
127 kCLOCK_Dmic0 \
128 }
129
130 /*! @brief Clock ip name array for ENET. */
131 #define ENET_CLOCKS \
132 { \
133 kCLOCK_EnetIpg \
134 }
135
136 /*! @brief Extra clock ip name array for ENET. */
137 #define ENET_EXTRA_CLOCKS \
138 { \
139 kCLOCK_EnetIpgS \
140 }
141
142 /*! @brief Clock ip name array for Powerquad */
143 #define POWERQUAD_CLOCKS \
144 { \
145 kCLOCK_PowerQuad \
146 }
147
148 /*! @brief Clock ip name array for OSTimer */
149 #define OSTIMER_CLOCKS \
150 { \
151 kCLOCK_OsEventTimer \
152 }
153
154 /*! @brief Clock ip name array for CT32B. */
155 #define CTIMER_CLOCKS \
156 { \
157 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
158 }
159
160 /*! @brief Clock ip name array for UTICK. */
161 #define UTICK_CLOCKS \
162 { \
163 kCLOCK_Utick \
164 }
165
166 /*! @brief Clock ip name array for MRT. */
167 #define MRT_CLOCKS \
168 { \
169 kCLOCK_Mrt, kCLOCK_FreeMrt \
170 }
171
172 /*! @brief Clock ip name array for SCT. */
173 #define SCT_CLOCKS \
174 { \
175 kCLOCK_Sct \
176 }
177
178 /*! @brief Clock ip name array for RTC. */
179 #define RTC_CLOCKS \
180 { \
181 kCLOCK_Rtc \
182 }
183
184 /*! @brief Clock ip name array for WWDT. */
185 #define WWDT_CLOCKS \
186 { \
187 kCLOCK_Wwdt0 \
188 }
189
190 /*! @brief Clock ip name array for TRNG. */
191 #define TRNG_CLOCKS \
192 { \
193 kCLOCK_Trng \
194 }
195
196 /*! @brief Clock ip name array for USIM. */
197 #define USIM_CLOCKS \
198 { \
199 kCLOCK_Usim \
200 }
201
202 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
203 /*------------------------------------------------------------------------------
204 clock_ip_name_t definition:
205 ------------------------------------------------------------------------------*/
206
207 #define CLK_GATE_REG_OFFSET_SHIFT 8U
208 #define CLK_GATE_REG_OFFSET_MASK 0xFF00U
209 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
210 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
211
212 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
213 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
214 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
215
216 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
217 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
218
219 #define CLK_CTL0_PSCCTL0 0
220 #define CLK_CTL0_PSCCTL1 1
221 #define CLK_CTL0_PSCCTL2 2
222 #define CLK_CTL1_PSCCTL0 3
223 #define CLK_CTL1_PSCCTL1 4
224 #define CLK_CTL1_PSCCTL2 5
225
226 #define SYS_CLK_GATE_FLAG_MASK (0x10000UL)
227 #define SYS_CLK_GATE_DEFINE(bit_shift) (((bit_shift)&CLK_GATE_BIT_SHIFT_MASK) | SYS_CLK_GATE_FLAG_MASK)
228 #define SYS_CLK_GATE_BIT_MASK(x) (1UL << (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT))
229
230 #define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U))
231 #define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) << 16) | ((choice) << 28U))
232 #define CLKCTL1_TUPLE_FLAG_MASK (0x8000U)
233 #define CLKCTL1_TUPLE_MUXA(reg, choice) (((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 12U))
234 #define CLKCTL1_TUPLE_MUXB(reg, choice) ((((reg)&0xFFCU) | CLKCTL1_TUPLE_FLAG_MASK | ((choice) << 28U)) << 16)
235 #define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
236 #define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x7U)
237
238 #define CLKOUT_TUPLE_MUX_AVAIL (0x2U)
239 #define CLKOUT_TUPLE_MUX(ch0, ch1, ch2) (CLKOUT_TUPLE_MUX_AVAIL | ((ch0) << 4U) | ((ch1) << 8) | ((ch2) << 12))
240
241 #define PMU_TUPLE_MUX_AVAIL (0x1U)
242 #define PMU_TUPLE_MUX(reg, choice) (((reg)&0xFFCU) | ((choice) << 12U) | PMU_TUPLE_MUX_AVAIL)
243 #define PMU_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFCU)))
244 #define PMU_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x3U)
245
246 /*!
247 * @brief Peripheral clock name difinition used for
248 * clock gate.
249 */
250 typedef enum _clock_ip_name
251 {
252 kCLOCK_IpInvalid = 0U,
253
254 kCLOCK_TcpuMciClk = SYS_CLK_GATE_DEFINE(0),
255 kCLOCK_TcpuMciFlexspiClk = SYS_CLK_GATE_DEFINE(1),
256 kCLOCK_TddrMciEnetClk = SYS_CLK_GATE_DEFINE(2),
257 kCLOCK_TddrMciFlexspiClk = SYS_CLK_GATE_DEFINE(3),
258 kCLOCK_T3PllMciIrcClk = SYS_CLK_GATE_DEFINE(4),
259 kCLOCK_T3PllMci256mClk = SYS_CLK_GATE_DEFINE(5),
260 kCLOCK_T3PllMci213mClk = SYS_CLK_GATE_DEFINE(6),
261 kCLOCK_T3PllMciFlexspiClk = SYS_CLK_GATE_DEFINE(7),
262 kCLOCK_RefClkSys = SYS_CLK_GATE_DEFINE(9),
263 kCLOCK_RefClkTcpu = SYS_CLK_GATE_DEFINE(28),
264 kCLOCK_RefClkTddr = SYS_CLK_GATE_DEFINE(29),
265 kCLOCK_RefClkAud = SYS_CLK_GATE_DEFINE(30),
266 kCLOCK_RefClkUsb = SYS_CLK_GATE_DEFINE(31),
267 kCLOCK_RefClkCauSlp = SYS_CLK_GATE_DEFINE(32),
268
269 kCLOCK_Cpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 0),
270 kCLOCK_Matrix = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1),
271 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
272 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
273 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
274 kCLOCK_Els = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
275 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
276 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
277 kCLOCK_Hpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
278 kCLOCK_Usb = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
279 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
280 kCLOCK_AonMem = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 25),
281 kCLOCK_Gdma = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28),
282 kCLOCK_Dma0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 29),
283 kCLOCK_Dma1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30),
284 kCLOCK_Sdio = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 31),
285
286 kCLOCK_ElsApb = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 0),
287 kCLOCK_SdioSlv = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
288 kCLOCK_Gau = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
289 kCLOCK_Otp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 17),
290 kCLOCK_SecureGpio = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
291 kCLOCK_EnetIpg = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 25),
292 kCLOCK_EnetIpgS = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 26),
293 kCLOCK_Trng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 27),
294
295 kCLOCK_Utick = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
296 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
297 kCLOCK_Usim = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2),
298 kCLOCK_Itrc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3),
299 kCLOCK_FreeMrt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26),
300 kCLOCK_Lcdic = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27),
301
302 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
303 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
304 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
305 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
306 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
307 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
308 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
309
310 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
311 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
312 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
313 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
314
315 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
316 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
317 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
318 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
319 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
320 kCLOCK_Pmu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 6),
321 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
322 kCLOCK_Mrt = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
323 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
324 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31),
325 } clock_ip_name_t;
326
327 /*!
328 * @brief Peripheral clock source selection definition.
329 */
330 typedef enum _clock_attach_id
331 {
332 kXTAL_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 0),
333 kCLKIN_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 1),
334 kNONE_to_SYSOSC_CLK = CLKCTL0_TUPLE_MUXA(0x168U, 7),
335
336 kSYSOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 0) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
337 kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 1) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
338 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 2) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
339 kFFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x430U, 3) | CLKCTL0_TUPLE_MUXB(0x434U, 0),
340 kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 1),
341 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 2),
342 kCLK32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(0x434U, 3),
343
344 kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 0),
345 kT3PLL_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 1),
346 kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 2),
347 kTCPU_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 3),
348 kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 4),
349 kTDDR_MCI_FLEXSPI_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 5),
350 kT3PLL_MCI_256M_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 6),
351 kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(0x620U, 7),
352
353 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 0),
354 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 1),
355 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 2),
356 kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 3),
357 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 4),
358 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 5),
359 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(0x640U, 7),
360
361 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 0),
362 kMAIN_CLK_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 1),
363 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(0x700U, 3),
364
365 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 0),
366 kMAIN_CLK_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 1),
367 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(0x720U, 3),
368
369 kSYSTICK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 0),
370 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 1),
371 kCLK32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 2),
372 kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 3),
373 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(0x760U, 7),
374
375 kMAIN_CLK_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 0),
376 kAUDIO_PLL_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 1),
377 kFFRO_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 2),
378 kNONE_to_USIM_CLK = CLKCTL0_TUPLE_MUXA(0x774U, 3),
379
380 kMAIN_CLK_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 0),
381 kT3PLL_MCI_256M_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 1),
382 kAVPLL_CH2_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 2),
383 kNONE_to_GAU_CLK = CLKCTL0_TUPLE_MUXA(0x77CU, 3),
384
385 kMAIN_CLK_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 0),
386 kT3PLL_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 1),
387 kTCPU_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 2),
388 kTDDR_MCI_FLEXSPI_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 3),
389 kNONE_to_LCD_CLK = CLKCTL0_TUPLE_MUXA(0x778U, 7),
390
391 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 0),
392 kCLK32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 1),
393 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 2),
394 kMAIN_CLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 3),
395 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(0x480U, 7),
396
397 kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 0),
398 kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 1),
399 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 2),
400 kMCLK_IN_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 3),
401 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 4),
402 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(0x508U, 7),
403
404 kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 0),
405 kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 1),
406 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 2),
407 kMCLK_IN_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 3),
408 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 4),
409 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(0x528U, 7),
410
411 kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 0),
412 kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 1),
413 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 2),
414 kMCLK_IN_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 3),
415 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 4),
416 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(0x548U, 7),
417
418 kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 0),
419 kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 1),
420 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 2),
421 kMCLK_IN_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 3),
422 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 4),
423 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(0x568U, 7),
424
425 kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 0),
426 kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 1),
427 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 2),
428 kMCLK_IN_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 3),
429 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 4),
430 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(0x6C8U, 7),
431
432 kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 0),
433 kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 1),
434 kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 2),
435 kMCLK_IN_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 3),
436 kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 4),
437 kCLK32K_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 5),
438 kMAIN_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 5),
439 kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(0x700U, 7),
440
441 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 0),
442 kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 1),
443 kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 2),
444 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 3),
445 kMCLK_IN_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 4),
446 kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 5),
447 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(0x720U, 7),
448
449 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 0),
450 kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 1),
451 kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 2),
452 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 3),
453 kMCLK_IN_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 4),
454 kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 5),
455 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(0x724U, 7),
456
457 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 0),
458 kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 1),
459 kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 2),
460 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 3),
461 kMCLK_IN_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 4),
462 kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 5),
463 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(0x728U, 7),
464
465 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 0),
466 kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 1),
467 kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 2),
468 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 3),
469 kMCLK_IN_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 4),
470 kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 5),
471 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(0x72CU, 7),
472
473 kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 0),
474 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 1),
475 kMAIN_CLK_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 2),
476 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(0x740U, 3),
477
478 kSFRO_to_CLKOUT = CLKOUT_TUPLE_MUX(0U, 0U, 0U),
479 kSYSOSC_to_CLKOUT = CLKOUT_TUPLE_MUX(1U, 0U, 0U),
480 kLPOSC_to_CLKOUT = CLKOUT_TUPLE_MUX(2U, 0U, 0U),
481 kFFRO_to_CLKOUT = CLKOUT_TUPLE_MUX(3U, 0U, 0U),
482 kMAIN_CLK_to_CLKOUT = CLKOUT_TUPLE_MUX(4U, 0U, 0U),
483 kREFCLK_SYS_to_CLKOUT = CLKOUT_TUPLE_MUX(5U, 0U, 0U),
484 kAVPLL_CH2_to_CLKOUT = CLKOUT_TUPLE_MUX(6U, 0U, 0U),
485 kMAIN_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 1U, 0U),
486 kAUX0_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 2U, 0U),
487 kAUX1_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 4U, 0U),
488 kAUDIO_PLL_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 5U, 0U),
489 kCLK32K_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 6U, 0U),
490 kTCPU_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 1U),
491 kTDDR_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 2U),
492 kT3PLL_MCI_FLEXSPI_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 3U),
493 kT3PLL_MCI_256M_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 4U),
494 kCAU_SLP_REF_CLK_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 5U),
495 kTDDR_MCI_ENET_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 6U),
496 kNONE_to_CLKOUT = CLKOUT_TUPLE_MUX(7U, 7U, 7U),
497
498 kRC32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 0),
499 kXTAL32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 1),
500 kNCO32K_to_CLK32K = PMU_TUPLE_MUX(0x70U, 2),
501 } clock_attach_id_t;
502
503 /*!
504 * @brief Clock divider definition.
505 */
506 typedef enum _clock_div_name
507 {
508 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(0x240U, 0),
509 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(0x248U, 0),
510 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(0x24CU, 0),
511 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(0x400U, 0),
512 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(0x504U, 0),
513 kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(0x624U, 0),
514 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(0x644U, 0),
515 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(0x664U, 0),
516 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(0x764U, 0),
517 kCLOCK_DivLcdClk = CLKCTL0_TUPLE_MUXA(0x768U, 0),
518 kCLOCK_DivGauClk = CLKCTL0_TUPLE_MUXA(0x76CU, 0),
519 kCLOCK_DivUsimClk = CLKCTL0_TUPLE_MUXA(0x770U, 0),
520 kCLOCK_DivPmuFclk = CLKCTL0_TUPLE_MUXA(0x780U, 0),
521
522 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(0x240U, 0),
523 kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(0x6FCU, 0),
524 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(0x704U, 0),
525 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(0x744U, 0),
526 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(0x768U, 0),
527 } clock_div_name_t;
528
529 /*! @brief PLL configuration for FRG */
530 typedef struct _clock_frg_clk_config
531 {
532 uint8_t num; /*!< FRG clock */
533 enum
534 {
535 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
536 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
537 kCLOCK_FrgSFro, /*!< 16MHz FRO */
538 kCLOCK_FrgFFro, /*!< FRO48/60 */
539 } sfg_clock_src;
540 uint8_t divider; /*!< Denominator of the fractional divider. */
541 uint8_t mult; /*!< Numerator of the fractional divider. */
542 } clock_frg_clk_config_t;
543
544 /*! @brief TCPU PLL divider for tcpu_mci_flexspi_clk */
545 typedef enum
546 {
547 kCLOCK_TcpuFlexspiDiv12 = 0, /*!< Divided by 12 */
548 kCLOCK_TcpuFlexspiDiv11, /*!< Divided by 11 */
549 kCLOCK_TcpuFlexspiDiv10, /*!< Divided by 10 */
550 kCLOCK_TcpuFlexspiDiv9, /*!< Divided by 9 */
551 } clock_tcpu_flexspi_div_t;
552
553 /*! @brief TDDR PLL divider for tddr_mci_flexspi_clk */
554 typedef enum
555 {
556 kCLOCK_TddrFlexspiDiv11 = 0, /*!< Divided by 11 */
557 kCLOCK_TddrFlexspiDiv10, /*!< Divided by 10 */
558 kCLOCK_TddrFlexspiDiv9, /*!< Divided by 9 */
559 kCLOCK_TddrFlexspiDiv8, /*!< Divided by 8 */
560 } clock_tddr_flexspi_div_t;
561
562 /*! @brief T3 PLL IRC configuration */
563 typedef enum
564 {
565 kCLOCK_T3MciIrc60m = 0, /*!< T3 MCI IRC 59.53MHz */
566 kCLOCK_T3MciIrc48m, /*!< T3 MCI IRC 48.30MHz */
567 } clock_t3_mci_irc_config_t;
568
569 /*! @brief AVPLL channel1 frequency configuration */
570 typedef enum
571 {
572 kCLOCK_AvPllChUnchanged = 0, /*!< AVPLL channel frequency unchanged. */
573 kCLOCK_AvPllChFreq2p048m, /*!< AVPLL channel frequency 2.048MHz */
574 kCLOCK_AvPllChFreq4p096m, /*!< AVPLL channel frequency 4.096MHz */
575 kCLOCK_AvPllChFreq6p144m, /*!< AVPLL channel frequency 6.144MHz */
576 kCLOCK_AvPllChFreq8p192m, /*!< AVPLL channel frequency 8.192MHz */
577 kCLOCK_AvPllChFreq11p2896m, /*!< AVPLL channel frequency 11.2896MHz */
578 kCLOCK_AvPllChFreq12m, /*!< AVPLL channel frequency 12MHz */
579 kCLOCK_AvPllChFreq12p288m, /*!< AVPLL channel frequency 12.288MHz */
580 kCLOCK_AvPllChFreq24p576m, /*!< AVPLL channel frequency 24.576MHz */
581 kCLOCK_AvPllChFreq64m, /*!< AVPLL channel frequency 64MHz */
582 kCLOCK_AvPllChFreq98p304m, /*!< AVPLL channel frequency 98.304MHz */
583 } clock_avpll_ch_freq_t;
584
585 /*! @brief AVPLL configuration */
586 typedef struct
587 {
588 clock_avpll_ch_freq_t ch1Freq; /*!< AVPLL channel 1 frequency configuration */
589 clock_avpll_ch_freq_t ch2Freq; /*!< AVPLL channel 2 frequency configuration */
590 bool enableCali; /*!< Enable calibration */
591 } clock_avpll_config_t;
592
593 /*******************************************************************************
594 * API
595 ******************************************************************************/
596
597 #if defined(__cplusplus)
598 extern "C" {
599 #endif /* __cplusplus */
600
601 /*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
602 *
603 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
604 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
605 * if CLK_IN is 16MHz,
606 * @code
607 * CLOCK_SetClkinFreq(16000000);
608 * @endcode
609 */
610 extern volatile uint32_t g_clkinFreq;
611 /*! @brief External MCLK IN clock frequency.
612 *
613 * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
614 * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
615 * if mclk_In is 16MHz,
616 * @code
617 * CLOCK_SetMclkInFreq(16000000);
618 * @endcode
619 */
620 extern volatile uint32_t g_mclkinFreq;
621
622 /*! @brief Return Frequency of t3pll_mci_48_60m_irc
623 * @return Frequency of t3pll_mci_48_60m_irc
624 */
625 uint32_t CLOCK_GetT3PllMciIrcClkFreq(void);
626
627 /*! @brief Return Frequency of t3pll_mci_213p3m
628 * @return Frequency of t3pll_mci_213p3m
629 */
630 uint32_t CLOCK_GetT3PllMci213mClkFreq(void);
631
632 /*! @brief Return Frequency of t3pll_mci_256m
633 * @return Frequency of t3pll_mci_256m
634 */
635 uint32_t CLOCK_GetT3PllMci256mClkFreq(void);
636
637 /*! @brief Return Frequency of t3pll_mci_flexspi_clk
638 * @return Frequency of t3pll_mci_flexspi_clk
639 */
640 uint32_t CLOCK_GetT3PllMciFlexspiClkFreq(void);
641
642 /*! @brief Return Frequency of tcpu_mci_clk
643 * @return Frequency of tcpu_mci_clk
644 */
645 uint32_t CLOCK_GetTcpuMciClkFreq(void);
646
647 /*! @brief Return Frequency of tcpu_mci_flexspi_clk
648 * @return Frequency of tcpu_mci_flexspi_clk
649 */
650 uint32_t CLOCK_GetTcpuMciFlexspiClkFreq(void);
651
652 /*! @brief Return Frequency of tddr_mci_flexspi_clk
653 * @return Frequency of tddr_mci_flexspi_clk
654 */
655 uint32_t CLOCK_GetTddrMciFlexspiClkFreq(void);
656
657 /*! @brief Return Frequency of tddr_mci_enet_clk
658 * @return Frequency of tddr_mci_enet_clk
659 */
660 uint32_t CLOCK_GetTddrMciEnetClkFreq(void);
661
662 /*!
663 * @brief Enable the clock for specific IP.
664 *
665 * @param clk Which clock to enable, see @ref clock_ip_name_t.
666 */
667 void CLOCK_EnableClock(clock_ip_name_t clk);
668
669 /*!
670 * @brief Disable the clock for specific IP.
671 *
672 * @param clk Which clock to disable, see @ref clock_ip_name_t.
673 */
674 void CLOCK_DisableClock(clock_ip_name_t clk);
675
676 /**
677 * @brief Configure the clock selection muxes.
678 * @param connection : Clock to be configured.
679 */
680 void CLOCK_AttachClk(clock_attach_id_t connection);
681
682 /**
683 * @brief Setup clock dividers.
684 * @param name : Clock divider name
685 * @param divider : Value to be divided.
686 */
687 void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider);
688
689 /*! @brief Return Input frequency for the Fractional baud rate generator
690 * @return Input Frequency for FRG
691 */
692 uint32_t CLOCK_GetFRGClock(uint32_t id);
693
694 /*! @brief Set output of the Fractional baud rate generator
695 * @param config : Configuration to set to FRGn clock.
696 */
697 void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
698
699 /*! @brief Return Frequency of FFRO
700 * @return Frequency of FFRO
701 */
702 uint32_t CLOCK_GetFFroFreq(void);
703
704 /*! @brief Return Frequency of SFRO
705 * @return Frequency of SFRO
706 */
707 uint32_t CLOCK_GetSFroFreq(void);
708
709 /*! @brief Return Frequency of AUDIO PLL (AVPLL CH1)
710 * @return Frequency of AUDIO PLL
711 */
712 uint32_t CLOCK_GetAvPllCh1Freq(void);
713
714 /*! @brief Return Frequency of AVPLL CH2
715 * @return Frequency of AVPLL CH2
716 */
717 uint32_t CLOCK_GetAvPllCh2Freq(void);
718
719 /*! @brief Return Frequency of main clk
720 * @return Frequency of main clk
721 */
722 uint32_t CLOCK_GetMainClkFreq(void);
723
724 /*! @brief Return Frequency of core/bus clk
725 * @return Frequency of core/bus clk
726 */
727 uint32_t CLOCK_GetCoreSysClkFreq(void);
728
729 /*! @brief Return Frequency of systick clk
730 * @return Frequency of systick clk
731 */
732 uint32_t CLOCK_GetSystickClkFreq(void);
733
734 /*! @brief Return Frequency of sys osc Clock
735 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
736 */
CLOCK_GetSysOscFreq(void)737 static inline uint32_t CLOCK_GetSysOscFreq(void)
738 {
739 return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
740 }
741
742 /*! @brief Return Frequency of MCLK Input Clock
743 * @return Frequency of MCLK input Clock.
744 */
CLOCK_GetMclkInClkFreq(void)745 static inline uint32_t CLOCK_GetMclkInClkFreq(void)
746 {
747 return g_mclkinFreq;
748 }
749
750 /*! @brief Return Frequency of LPOSC
751 * @return Frequency of LPOSC
752 */
CLOCK_GetLpOscFreq(void)753 static inline uint32_t CLOCK_GetLpOscFreq(void)
754 {
755 return CLK_XTAL_OSC_CLK / 40U;
756 }
757
758 /*! @brief Return Frequency of CLK_32K
759 * @return Frequency of 32KHz osc
760 */
CLOCK_GetClk32KFreq(void)761 static inline uint32_t CLOCK_GetClk32KFreq(void)
762 {
763 return CLK_RTC_32K_CLK;
764 }
765
766 /*! @brief Enables and disables 32KHz XTAL
767 * @param enable : true to enable 32k XTAL clock, false to disable clock
768 */
769 void CLOCK_EnableXtal32K(bool enable);
770
771 /*! @brief Enables and disables RTC 32KHz
772 * @param enable : true to enable 32k RTC clock, false to disable clock
773 */
774 void CLOCK_EnableRtc32K(bool enable);
775
776 /*!
777 * @brief Set the CLKIN (CLKIN pin) frequency based on GPIO4 input.
778 *
779 * @param freq : The CLK_IN pin input clock frequency in Hz.
780 */
CLOCK_SetClkinFreq(uint32_t freq)781 static inline void CLOCK_SetClkinFreq(uint32_t freq)
782 {
783 g_clkinFreq = freq;
784 }
785 /*!
786 * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
787 *
788 * @param freq : The MCLK input clock frequency in Hz.
789 */
CLOCK_SetMclkinFreq(uint32_t freq)790 static inline void CLOCK_SetMclkinFreq(uint32_t freq)
791 {
792 g_mclkinFreq = freq;
793 }
794
795 /*! @brief Return Frequency of DMIC clk
796 * @return Frequency of DMIC clk
797 */
798 uint32_t CLOCK_GetDmicClkFreq(void);
799
800 /*! @brief Return Frequency of LCD clk
801 * @return Frequency of LCD clk
802 */
803 uint32_t CLOCK_GetLcdClkFreq(void);
804
805 /*! @brief Return Frequency of WDT clk
806 * @return Frequency of WDT clk
807 */
808 uint32_t CLOCK_GetWdtClkFreq(void);
809
810 /*! @brief Return Frequency of mclk
811 * @return Frequency of mclk clk
812 */
813 uint32_t CLOCK_GetMclkClkFreq(void);
814
815 /*! @brief Return Frequency of sct
816 * @return Frequency of sct clk
817 */
818 uint32_t CLOCK_GetSctClkFreq(void);
819
820 /*! @brief Return Frequency of Flexcomm functional Clock
821 * @param id : flexcomm index to get frequency.
822 * @return Frequency of Flexcomm functional Clock
823 */
824 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
825
826 /*! @brief Return Frequency of CTimer Clock
827 * @param id : ctimer index to get frequency.
828 * @return Frequency of CTimer Clock
829 */
830 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
831
832 /*! @brief Return Frequency of Utick Clock
833 * @return Frequency of Utick Clock
834 */
835 uint32_t CLOCK_GetUtickClkFreq(void);
836
837 /*! @brief Return Frequency of Flexspi Clock
838 * @return Frequency of Flexspi.
839 */
840 uint32_t CLOCK_GetFlexspiClkFreq(void);
841
842 /*! @brief Return Frequency of USIM Clock
843 * @return Frequency of USIM.
844 */
845 uint32_t CLOCK_GetUsimClkFreq(void);
846
847 /*! @brief Return Frequency of GAU Clock
848 * @return Frequency of GAU.
849 */
850 uint32_t CLOCK_GetGauClkFreq(void);
851
852 /*! @brief Return Frequency of OSTimer Clock
853 * @return Frequency of OSTimer.
854 */
855 uint32_t CLOCK_GetOSTimerClkFreq(void);
856
857 /*! @brief Initialize TCPU FVCO to target frequency.
858 * For 40MHz XTAL, FVCO ranges from 3000MHz to 3840MHz.
859 For 38.4MHz XTAL, FVCO ranges from 2995.2MHz to 3840MHz
860 * @param targetHz : Target FVCO frequency in Hz.
861 * @param div : Divider for tcpu_mci_flexspi_clk.
862 * @return Actual FVCO frequency in Hz.
863 */
864 uint32_t CLOCK_InitTcpuRefClk(uint32_t targetHz, clock_tcpu_flexspi_div_t div);
865
866 /*! @brief Deinit the TCPU reference clock.
867 */
868 void CLOCK_DeinitTcpuRefClk(void);
869
870 /*! @brief Initialize the TDDR reference clock.
871 * @param div : Divider for tddr_mci_flexspi_clk.
872 */
873 void CLOCK_InitTddrRefClk(clock_tddr_flexspi_div_t div);
874
875 /*! @brief Deinit the TDDR reference clock.
876 */
877 void CLOCK_DeinitTddrRefClk(void);
878
879 /*! @brief Initialize the T3 reference clock.
880 * @param cnfg : t3pll_mci_48_60m_irc clock configuration
881 */
882 void CLOCK_InitT3RefClk(clock_t3_mci_irc_config_t cnfg);
883
884 /*! @brief Deinit the T3 reference clock. */
885 void CLOCK_DeinitT3RefClk(void);
886
887 /*! @brief Initialize the AVPLL. Both channel 1 and 2 are enabled.
888 * @param cnfg : AVPLL clock configuration
889 */
890 void CLOCK_InitAvPll(const clock_avpll_config_t *cnfg);
891
892 /*! @brief Deinit the AVPLL. All channels are disabled.
893 */
894 void CLOCK_DeinitAvPll(void);
895
896 /*! @brief Update the AVPLL channel configuration. Enable/Disable state keeps unchanged.
897 * @param ch1Freq : Channel 1 frequency to set.
898 * @param ch2Freq : Channel 2 frequency to set.
899 * @param enableCali : Enable AVPLL calibration.
900 */
901 void CLOCK_ConfigAvPllCh(clock_avpll_ch_freq_t ch1Freq, clock_avpll_ch_freq_t ch2Freq, bool enableCali);
902
903 /*! @brief Enable the AVPLL channel.
904 * @param enableCh1 : Enable AVPLL channel1, channel unchanged on false.
905 * @param enableCh2 : Enable AVPLL channel2, channel unchanged on false.
906 * @param enableCali : Enable AVPLL calibration.
907 */
908 void CLOCK_EnableAvPllCh(bool enableCh1, bool enableCh2, bool enableCali);
909
910 /*! @brief Disable the AVPLL.
911 * @param disableCh1 : Disable AVPLL channel1, channel unchanged on false.
912 * @param disableCh2 : Disable AVPLL channel2, channel unchanged on false.
913 */
914 void CLOCK_DisableAvPllCh(bool disableCh1, bool disableCh2);
915
916 /*! @brief Enable USB HS PHY PLL clock.
917 *
918 * This function enables USB HS PHY PLL clock.
919 */
920 void CLOCK_EnableUsbhsPhyClock(void);
921
922 /*! @brief Disable USB HS PHY PLL clock.
923 *
924 * This function disables USB HS PHY PLL clock.
925 */
926 void CLOCK_DisableUsbhsPhyClock(void);
927
928 #if defined(__cplusplus)
929 }
930 #endif /* __cplusplus */
931
932 /*! @} */
933
934 #endif /* _FSL_CLOCK_H_ */
935
