1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_device_registers.h"
13 #include <stdint.h>
14 #include <stdbool.h>
15 #include <assert.h>
16 #include "fsl_reset.h"
17 #include "fsl_common.h"
18
19 /*! @addtogroup clock */
20 /*! @{ */
21
22 /*! @file */
23
24 /*******************************************************************************
25 * Definitions
26 *****************************************************************************/
27
28 /*! @name Driver version */
29 /*@{*/
30 /*! @brief CLOCK driver version 2.7.0 */
31 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))
32 /*@}*/
33
34 /* Definition for delay API in clock driver, users can redefine it to the real application. */
35 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
36 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (198000000UL)
37 #endif
38
39 /* Definition for compatiblity with other platforms. */
40 #define CLOCK_GetFlexCommClkFreq CLOCK_GetFlexcommClkFreq
41 #define CLOCK_GetCTimerClkFreq CLOCK_GetCtimerClkFreq
42
43 /*! @brief External XTAL (SYSOSC) clock frequency.
44 *
45 * The XTAL (YSOSC) clock frequency in Hz, when the clock is setup, use the
46 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
47 * if XTAL is 16MHz,
48 * @code
49 * CLOCK_SetXtalFreq(160000000);
50 * @endcode
51 */
52 extern volatile uint32_t g_xtalFreq;
53
54 /*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
55 *
56 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
57 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
58 * if CLK_IN is 16MHz,
59 * @code
60 * CLOCK_SetClkinFreq(160000000);
61 * @endcode
62 */
63 extern volatile uint32_t g_clkinFreq;
64
65 /*! @brief External MCLK IN clock frequency.
66 *
67 * The MCLK IN clock frequency in Hz, when the clock is setup, use the
68 * function CLOCK_SetMclkFreq to set the value in to clock driver. For example,
69 * if MCLK IN is 16MHz,
70 * @code
71 * CLOCK_SetMclkFreq(160000000);
72 * @endcode
73 */
74 extern volatile uint32_t g_mclkFreq;
75
76 /*! @brief Clock ip name array for MIPI DSI. */
77 #define MIPI_DSI_HOST_CLOCKS \
78 { \
79 kCLOCK_MipiDsiCtrl \
80 }
81
82 /*! @brief Clock ip name array for LCDIF. */
83 #define LCDIF_CLOCKS \
84 { \
85 kCLOCK_DisplayCtrl \
86 }
87
88 /*! @brief Clock ip name array for SCT. */
89 #define SCT_CLOCKS \
90 { \
91 kCLOCK_Sct \
92 }
93
94 /*! @brief Clock ip name array for USBD. */
95 #define USBD_CLOCKS \
96 { \
97 kCLOCK_UsbhsDevice \
98 }
99
100 /*! @brief Clock ip name array for FlexSPI */
101 #define FLEXSPI_CLOCKS \
102 { \
103 kCLOCK_Flexspi0, kCLOCK_Flexspi1 \
104 }
105
106 /*! @brief Clock ip name array for Cache64 */
107 #define CACHE64_CLOCKS \
108 { \
109 kCLOCK_Flexspi0, kCLOCK_Flexspi1 \
110 }
111
112 /*! @brief Clock ip name array for RNG */
113 #define TRNG_CLOCKS \
114 { \
115 kCLOCK_Rng \
116 }
117
118 /*! @brief Clock ip name array for PUF */
119 #define PUF_CLOCKS \
120 { \
121 kCLOCK_Puf \
122 }
123
124 /*! @brief Clock ip name array for HashCrypt */
125 #define HASHCRYPT_CLOCKS \
126 { \
127 kCLOCK_Hashcrypt \
128 }
129
130 /*! @brief Clock ip name array for Casper */
131 #define CASPER_CLOCKS \
132 { \
133 kCLOCK_Casper \
134 }
135
136 /*! @brief Clock ip name array for Powerquad */
137 #define POWERQUAD_CLOCKS \
138 { \
139 kCLOCK_PowerQuad \
140 }
141
142 /*! @brief Clock ip name array for ADC. */
143 #define LPADC_CLOCKS \
144 { \
145 kCLOCK_Adc0 \
146 }
147
148 /*! @brief Clock ip name array for ACMP. */
149 #define CMP_CLOCKS \
150 { \
151 kCLOCK_Acmp0 \
152 }
153
154 /*! @brief Clock ip name array for uSDHC */
155 #define USDHC_CLOCKS \
156 { \
157 kCLOCK_Sdio0, kCLOCK_Sdio1 \
158 }
159
160 /*! @brief Clock ip name array for WWDT. */
161 #define WWDT_CLOCKS \
162 { \
163 kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
164 }
165
166 /*! @brief Clock ip name array for UTICK. */
167 #define UTICK_CLOCKS \
168 { \
169 kCLOCK_Utick0 \
170 }
171
172 /*! @brief Clock ip name array for FlexIO. */
173 #define FLEXIO_CLOCKS \
174 { \
175 kCLOCK_Flexio \
176 }
177
178 /*! @brief Clock ip name array for OSTimer */
179 #define OSTIMER_CLOCKS \
180 { \
181 kCLOCK_OsEventTimer \
182 }
183
184 /*! @brief Clock ip name array for FLEXCOMM. */
185 #define FLEXCOMM_CLOCKS \
186 { \
187 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, \
188 kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm8, kCLOCK_Flexcomm9, kCLOCK_Flexcomm10, \
189 kCLOCK_Flexcomm11, kCLOCK_Flexcomm12, kCLOCK_Flexcomm13, kCLOCK_Flexcomm14, kCLOCK_Flexcomm15, \
190 kCLOCK_Flexcomm16 \
191 }
192
193 /*! @brief Clock ip name array for LPUART. */
194 #define USART_CLOCKS \
195 { \
196 kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, kCLOCK_Usart4, kCLOCK_Usart5, kCLOCK_Usart6, \
197 kCLOCK_Usart7, kCLOCK_Usart8, kCLOCK_Usart9, kCLOCK_Usart10, kCLOCK_Usart11, kCLOCK_Usart12, \
198 kCLOCK_Usart13 \
199 }
200
201 /*! @brief Clock ip name array for I2C. */
202 #define I2C_CLOCKS \
203 { \
204 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, kCLOCK_I2c7, \
205 kCLOCK_I2c8, kCLOCK_I2c9, kCLOCK_I2c10, kCLOCK_I2c11, kCLOCK_I2c12, kCLOCK_I2c13, kCLOCK_I2c15 \
206 }
207
208 /*! @brief Clock ip name array for SPI. */
209 #define SPI_CLOCKS \
210 { \
211 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3, kCLOCK_Spi4, kCLOCK_Spi5, kCLOCK_Spi6, kCLOCK_Spi7, \
212 kCLOCK_Spi8, kCLOCK_Spi9, kCLOCK_Spi10, kCLOCK_Spi11, kCLOCK_Spi12, kCLOCK_Spi13, kCLOCK_Spi14, \
213 kCLOCK_Spi16 \
214 }
215 /*! @brief Clock ip name array for FLEXI2S. */
216 #define I2S_CLOCKS \
217 { \
218 kCLOCK_I2s0, kCLOCK_I2s1, kCLOCK_I2s2, kCLOCK_I2s3, kCLOCK_I2s4, kCLOCK_I2s5, kCLOCK_I2s6, kCLOCK_I2s7, \
219 kCLOCK_I2s8, kCLOCK_I2s9, kCLOCK_I2s10, kCLOCK_I2s11, kCLOCK_I2s12, kCLOCK_I2s13 \
220 }
221
222 /*! @brief Clock ip name array for DMIC. */
223 #define DMIC_CLOCKS \
224 { \
225 kCLOCK_Dmic0 \
226 }
227
228 /*! @brief Clock ip name array for SEMA */
229 #define SEMA42_CLOCKS \
230 { \
231 kCLOCK_Sema \
232 }
233
234 /*! @brief Clock ip name array for MUA */
235 #define MU_CLOCKS \
236 { \
237 kCLOCK_Mu \
238 }
239
240 /*! @brief Clock ip name array for DMA. */
241 #define DMA_CLOCKS \
242 { \
243 kCLOCK_Dmac0, kCLOCK_Dmac1 \
244 }
245
246 /*! @brief Clock ip name array for CRC. */
247 #define CRC_CLOCKS \
248 { \
249 kCLOCK_Crc \
250 }
251
252 /*! @brief Clock ip name array for GPIO. */
253 #define GPIO_CLOCKS \
254 { \
255 kCLOCK_HsGpio0, kCLOCK_HsGpio1, kCLOCK_HsGpio2, kCLOCK_HsGpio3, kCLOCK_HsGpio4, kCLOCK_HsGpio5, \
256 kCLOCK_HsGpio6, kCLOCK_HsGpio7 \
257 }
258
259 /*! @brief Clock ip name array for PINT. */
260 #define PINT_CLOCKS \
261 { \
262 kCLOCK_GpioIntCtl \
263 }
264
265 /*! @brief Clock ip name array for I3C. */
266 #define I3C_CLOCKS \
267 { \
268 kCLOCK_I3c0, kCLOCK_I3c1 \
269 }
270
271 /*! @brief Clock ip name array for MRT. */
272 #define MRT_CLOCKS \
273 { \
274 kCLOCK_Mrt0 \
275 }
276
277 /*! @brief Clock ip name array for RTC. */
278 #define RTC_CLOCKS \
279 { \
280 kCLOCK_Rtc \
281 }
282
283 /*! @brief Clock ip name array for CT32B. */
284 #define CTIMER_CLOCKS \
285 { \
286 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
287 }
288
289 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
290 /*------------------------------------------------------------------------------
291 clock_ip_name_t definition:
292 ------------------------------------------------------------------------------*/
293
294 #define CLK_GATE_REG_OFFSET_SHIFT 8U
295 #define CLK_GATE_REG_OFFSET_MASK 0xFF00U
296 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
297 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
298
299 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
300 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
301 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
302
303 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
304 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
305
306 #define CLK_CTL0_PSCCTL0 0
307 #define CLK_CTL0_PSCCTL1 1
308 #define CLK_CTL0_PSCCTL2 2
309 #define CLK_CTL1_PSCCTL0 3
310 #define CLK_CTL1_PSCCTL1 4
311 #define CLK_CTL1_PSCCTL2 5
312
313 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
314 typedef enum _clock_ip_name
315 {
316 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
326 kCLOCK_Flexspi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi0*/
327 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
328 kCLOCK_Flexspi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 18), /*!< Clock gate name: Flexspi1*/
329 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
330 kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21), /*!< Clock gate name: UsbhsDevice*/
331 kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22), /*!< Clock gate name: UsbhsHost*/
332 kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23), /*!< Clock gate name: UsbhsSram*/
333 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24), /*!< Clock gate name: Sct*/
334 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 26), /*!< Clock gate name: Gpu*/
335 kCLOCK_DisplayCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 27), /*!< Clock gate name: DisplayCtrl*/
336 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28), /*!< Clock gate name: MipiDsiCtrl*/
337 kCLOCK_Smartdma = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30), /*!< Clock gate name: Smartdma*/
338
339 kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: Sdio0*/
340 kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: Sdio1*/
341 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15), /*!< Clock gate name: Acmp0*/
342 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: Adc0*/
343 kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: ShsGpio0*/
344
345 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
346 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
347 kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
348
349 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
350 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
351 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
352 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
353 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
354 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
355 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
356 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
357 kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
358 kCLOCK_Flexcomm9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Flexcomm9*/
359 kCLOCK_Flexcomm10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Flexcomm10*/
360 kCLOCK_Flexcomm11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Flexcomm11*/
361 kCLOCK_Flexcomm12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Flexcomm12*/
362 kCLOCK_Flexcomm13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Flexcomm13*/
363 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
364 kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: Flexcomm15*/
365 kCLOCK_Flexcomm16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Flexcomm16*/
366 kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Usart0*/
367 kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Usart1*/
368 kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Usart2*/
369 kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Usart3*/
370 kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Usart4*/
371 kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Usart5*/
372 kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Usart6*/
373 kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Usart7*/
374 kCLOCK_Usart8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Usart8*/
375 kCLOCK_Usart9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Usart9*/
376 kCLOCK_Usart10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Usart10*/
377 kCLOCK_Usart11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Usart11*/
378 kCLOCK_Usart12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Usart12*/
379 kCLOCK_Usart13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Usart13*/
380 kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2s0*/
381 kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2s1*/
382 kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2s2*/
383 kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2s3*/
384 kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2s4*/
385 kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2s5*/
386 kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2s6*/
387 kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2s7*/
388 kCLOCK_I2s8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2s8*/
389 kCLOCK_I2s9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2s9*/
390 kCLOCK_I2s10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2s10*/
391 kCLOCK_I2s11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2s11*/
392 kCLOCK_I2s12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2s12*/
393 kCLOCK_I2s13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2s13*/
394 kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2c0*/
395 kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2c1*/
396 kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2c2*/
397 kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2c3*/
398 kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2c4*/
399 kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2c5*/
400 kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2c6*/
401 kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2c7*/
402 kCLOCK_I2c8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2c8*/
403 kCLOCK_I2c9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2c9*/
404 kCLOCK_I2c10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2c10*/
405 kCLOCK_I2c11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2c11*/
406 kCLOCK_I2c12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2c12*/
407 kCLOCK_I2c13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2c13*/
408 kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: I2c15*/
409 kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Spi0*/
410 kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Spi1*/
411 kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Spi2*/
412 kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Spi3*/
413 kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Spi4*/
414 kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Spi5*/
415 kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Spi6*/
416 kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Spi7*/
417 kCLOCK_Spi8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Spi8*/
418 kCLOCK_Spi9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Spi9*/
419 kCLOCK_Spi10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Spi10*/
420 kCLOCK_Spi11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Spi11*/
421 kCLOCK_Spi12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Spi12*/
422 kCLOCK_Spi13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Spi13*/
423 kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Spi14*/
424 kCLOCK_Spi16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Spi16*/
425 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24), /*!< Clock gate name: Dmic0*/
426 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27), /*!< Clock gate name: OsEventTimer*/
427 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 29), /*!< Clock gate name: Flexio*/
428
429 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
430 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
431 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
432 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
433 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
434 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
435 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
436 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
437 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
438 kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: Dmac0*/
439 kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: Dmac1*/
440 kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28), /*!< Clock gate name: Mu*/
441 kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29), /*!< Clock gate name: Sema*/
442 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31), /*!< Clock gate name: Freqme*/
443
444 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
445 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
446 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
447 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
448 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
449 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
450 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
451 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
452 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
453 kCLOCK_I3c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 17), /*!< Clock gate name: I3c1*/
454 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30), /*!< Clock gate name: Pint*/
455 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31) /*!< Clock gate name: InputMux. */
456 } clock_ip_name_t;
457
458 /*! @brief Clock name used to get clock frequency. */
459 typedef enum _clock_name
460 {
461 kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
462 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
463 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
464 kCLOCK_ClockOutClk, /*!< CLOCKOUT */
465 kCLOCK_AdcClk, /*!< ADC */
466 kCLOCK_Flexspi0Clk, /*!< FlexSpi0 */
467 kCLOCK_Flexspi1Clk, /*!< FlexSpi1 */
468 kCLOCK_SctClk, /*!< SCT */
469 kCLOCK_Wdt0Clk, /*!< Watchdog0 */
470 kCLOCK_Wdt1Clk, /*!< Watchdog1 */
471 kCLOCK_SystickClk, /*!< Systick */
472 kCLOCK_Sdio0Clk, /*!< SDIO0 */
473 kCLOCK_Sdio1Clk, /*!< SDIO1 */
474 kCLOCK_I3cClk, /*!< I3C0 and I3C1 */
475 kCLOCK_UsbClk, /*!< USB0 */
476 kCLOCK_DmicClk, /*!< Digital Mic clock */
477 kCLOCK_DspCpuClk, /*!< DSP clock */
478 kCLOCK_AcmpClk, /*!< Acmp clock */
479 kCLOCK_Flexcomm0Clk, /*!< Flexcomm0Clock */
480 kCLOCK_Flexcomm1Clk, /*!< Flexcomm1Clock */
481 kCLOCK_Flexcomm2Clk, /*!< Flexcomm2Clock */
482 kCLOCK_Flexcomm3Clk, /*!< Flexcomm3Clock */
483 kCLOCK_Flexcomm4Clk, /*!< Flexcomm4Clock */
484 kCLOCK_Flexcomm5Clk, /*!< Flexcomm5Clock */
485 kCLOCK_Flexcomm6Clk, /*!< Flexcomm6Clock */
486 kCLOCK_Flexcomm7Clk, /*!< Flexcomm7Clock */
487 kCLOCK_Flexcomm8Clk, /*!< Flexcomm8Clock */
488 kCLOCK_Flexcomm9Clk, /*!< Flexcomm9Clock */
489 kCLOCK_Flexcomm10Clk, /*!< Flexcomm10Clock */
490 kCLOCK_Flexcomm11Clk, /*!< Flexcomm11Clock */
491 kCLOCK_Flexcomm12Clk, /*!< Flexcomm12Clock */
492 kCLOCK_Flexcomm13Clk, /*!< Flexcomm13Clock */
493 kCLOCK_Flexcomm14Clk, /*!< Flexcomm14Clock */
494 kCLOCK_Flexcomm15Clk, /*!< Flexcomm15Clock */
495 kCLOCK_Flexcomm16Clk, /*!< Flexcomm16Clock */
496 kCLOCK_FlexioClk, /*!< FlexIO */
497 kCLOCK_GpuClk, /*!< GPU Core */
498 kCLOCK_DcPixelClk, /*!< DCNano Pixel Clock */
499 kCLOCK_MipiDphyClk, /*!< MIPI D-PHY Bit Clock */
500 kCLOCK_MipiDphyEscRxClk, /*!< MIPI D-PHY RX Clock */
501 kCLOCK_MipiDphyEscTxClk, /*!< MIPI D-PHY TX Clock */
502 } clock_name_t;
503
504 /**
505 * @brief PLL PFD clock name
506 */
507 typedef enum _clock_pfd
508 {
509 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
510 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
511 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
512 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
513 } clock_pfd_t;
514
515 /*! @brief Clock Mux Switches
516 * The encoding is as follows each connection identified is 32bits wide
517 * starting from LSB upwards
518 *
519 * [ 31 30 29:28 27:25 24:14 13:11 10:0 ]
520 * [CLKCTL index]:[FRODIVSEL onoff]:[FRODIVSEL]:[MUXB choice]:[MUXB offset]:[MUXA choice]:[MUXA offset]
521 * FRODIVSEL onoff '1' means need to set FRODIVSEL. MUX offset 0 means end of descriptor.
522 */
523 /* CLKCTL0 SEL */
524 #define SYSPLL0CLKSEL_OFFSET 0x200
525 #define MAINCLKSELA_OFFSET 0x430
526 #define MAINCLKSELB_OFFSET 0x434
527 #define FLEXSPI0FCLKSEL_OFFSET 0x620
528 #define FLEXSPI1FCLKSEL_OFFSET 0x630
529 #define SCTFCLKSEL_OFFSET 0x640
530 #define USBHSFCLKSEL_OFFSET 0x660
531 #define SDIO0FCLKSEL_OFFSET 0x680
532 #define SDIO1FCLKSEL_OFFSET 0x690
533 #define ADC0FCLKSEL0_OFFSET 0x6D0
534 #define ADC0FCLKSEL1_OFFSET 0x6D4
535 #define UTICKFCLKSEL_OFFSET 0x700
536 #define WDT0FCLKSEL_OFFSET 0x720
537 #define A32KHZWAKECLKSEL_OFFSET 0x730
538 #define SYSTICKFCLKSEL_OFFSET 0x760
539 #define DPHYCLKSEL_OFFSET 0x770
540 #define DPHYESCCLKSEL_OFFSET 0x778
541 #define GPUCLKSEL_OFFSET 0x790
542 #define DCPIXELCLKSEL_OFFSET 0x7A0
543 /* CLKCTL1 SEL */
544 #define AUDIOPLL0CLKSEL_OFFSET 0x200
545 #define DSPCPUCLKSELA_OFFSET 0x430
546 #define DSPCPUCLKSELB_OFFSET 0x434
547 #define OSEVENTTFCLKSEL_OFFSET 0x480
548 #define FC0FCLKSEL_OFFSET 0x508
549 #define FC1FCLKSEL_OFFSET 0x528
550 #define FC2FCLKSEL_OFFSET 0x548
551 #define FC3FCLKSEL_OFFSET 0x568
552 #define FC4FCLKSEL_OFFSET 0x588
553 #define FC5FCLKSEL_OFFSET 0x5A8
554 #define FC6FCLKSEL_OFFSET 0x5C8
555 #define FC7FCLKSEL_OFFSET 0x5E8
556 #define FC8FCLKSEL_OFFSET 0x608
557 #define FC9FCLKSEL_OFFSET 0x628
558 #define FC10FCLKSEL_OFFSET 0x648
559 #define FC11FCLKSEL_OFFSET 0x668
560 #define FC12FCLKSEL_OFFSET 0x688
561 #define FC13FCLKSEL_OFFSET 0x6A8
562 #define FC14FCLKSEL_OFFSET 0x6C8
563 #define FC15FCLKSEL_OFFSET 0x6E8
564 #define FC16FCLKSEL_OFFSET 0x708
565 #define FLEXIOCLKSEL_OFFSET 0x728
566 #define DMIC0FCLKSEL_OFFSET 0x780
567 #define CT32BIT0FCLKSEL_OFFSET 0x7A0
568 #define CT32BIT1FCLKSEL_OFFSET 0x7A4
569 #define CT32BIT2FCLKSEL_OFFSET 0x7A8
570 #define CT32BIT3FCLKSEL_OFFSET 0x7AC
571 #define CT32BIT4FCLKSEL_OFFSET 0x7B0
572 #define AUDIOMCLKSEL_OFFSET 0x7C0
573 #define CLKOUTSEL0_OFFSET 0x7E0
574 #define CLKOUTSEL1_OFFSET 0x7E4
575 #define I3C01FCLKSEL_OFFSET 0x800
576 #define I3C01FCLKSTCSEL_OFFSET 0x804
577 #define I3C01FCLKSTSTCLKSEL_OFFSET 0x814
578 #define WDT1FCLKSEL_OFFSET 0x820
579 #define ACMP0FCLKSEL_OFFSET 0x830
580 /* CLKCTL0 DIV */
581 #define LOWFREQCLKDIV_OFFSET 0x130
582 #define MAINPLLCLKDIV_OFFSET 0x240
583 #define DSPPLLCLKDIV_OFFSET 0x244
584 #define AUX0PLLCLKDIV_OFFSET 0x248
585 #define AUX1PLLCLKDIV_OFFSET 0x24C
586 #define SYSCPUAHBCLKDIV_OFFSET 0x400
587 #define PFC0CLKDIV_OFFSET 0x500
588 #define PFC1CLKDIV_OFFSET 0x504
589 #define FLEXSPI0FCLKDIV_OFFSET 0x624
590 #define FLEXSPI1FCLKDIV_OFFSET 0x634
591 #define SCTFCLKDIV_OFFSET 0x644
592 #define USBHSFCLKDIV_OFFSET 0x664
593 #define SDIO0FCLKDIV_OFFSET 0x684
594 #define SDIO1FCLKDIV_OFFSET 0x694
595 #define ADC0FCLKDIV_OFFSET 0x6D8
596 #define A32KHZWAKECLKDIV_OFFSET 0x734
597 #define SYSTICKFCLKDIV_OFFSET 0x764
598 #define DPHYCLKDIV_OFFSET 0x774
599 #define DPHYESCRXCLKDIV_OFFSET 0x77C
600 #define DPHYESCTXCLKDIV_OFFSET 0x780
601 #define GPUCLKDIV_OFFSET 0x794
602 #define DCPIXELCLKDIV_OFFSET 0x7A4
603 /* CLKCTL1 DIV */
604 #define AUDIOPLLCLKDIV_OFFSET 0x240
605 #define DSPCPUCLKDIV_OFFSET 0x400
606 #define FLEXIOCLKDIV_OFFSET 0x740
607 #define FRGPLLCLKDIV_OFFSET 0x760
608 #define DMIC0FCLKDIV_OFFSET 0x784
609 #define AUDIOMCLKDIV_OFFSET 0x7C4
610 #define CLKOUTFCLKDIV_OFFSET 0x7E8
611 #define I3C01FCLKSTCDIV_OFFSET 0x808
612 #define I3C01FCLKSDIV_OFFSET 0x80C
613 #define I3C01FCLKDIV_OFFSET 0x810
614 #define ACMP0FCLKDIV_OFFSET 0x834
615
616 #define CLKCTL0_TUPLE_MUXA(reg, choice) ((((reg) >> 2U) & 0x7FFU) | (((choice)&0x7U) << 11U))
617 #define CLKCTL0_TUPLE_MUXB(reg, choice) (((((reg) >> 2U) & 0x7FFU) << 14U) | (((choice)&0x7U) << 25U))
618 #define CLKCTL1_TUPLE_MUXA(reg, choice) (0x80000000U | ((((reg) >> 2U) & 0x7FFU) | (((choice)&0x7U) << 11U)))
619 #define CLKCTL1_TUPLE_MUXB(reg, choice) (0x80000000U | (((((reg) >> 2U) & 0x7FFU) << 14U) | (((choice)&0x7U) << 25U)))
620 #define CLKCTL_TUPLE_FRODIVSEL(choice) (0x40000000U | (((choice)&0x7U) << 28U))
621 #define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)(tuple)&0x7FFU) << 2U)))
622 #define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 11U) & 0x7U)
623
624 /*!
625 * @brief The enumerator of clock attach Id.
626 */
627 typedef enum _clock_attach_id
628 {
629 kFRO_DIV8_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to SYS_PLL. */
630 kOSC_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1), /*!< Attach OSC_CLK to SYS_PLL. */
631 kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to SYS_PLL. */
632
633 kFRO_DIV8_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to AUDIO_PLL. */
634 kOSC_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1), /*!< Attach OSC_CLK to AUDIO_PLL. */
635 kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7), /*!< Attach NONE to AUDIO_PLL. */
636
637 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 0) |
638 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach LPOSC to MAIN_CLK. */
639 kFRO_DIV2_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(0) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
640 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV2 to MAIN_CLK. */
641 kFRO_DIV4_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(1) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
642 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV4 to MAIN_CLK. */
643 kFRO_DIV8_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(2) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
644 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV8 to MAIN_CLK. */
645 kFRO_DIV16_to_MAIN_CLK = CLKCTL_TUPLE_FRODIVSEL(3) | CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) |
646 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV16 to MAIN_CLK. */
647 kOSC_CLK_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 2) |
648 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach OSC_CLK to MAIN_CLK. */
649 kFRO_DIV1_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 3) |
650 CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0), /*!< Attach FRO_DIV1 to MAIN_CLK. */
651 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1), /*!< Attach MAIN_PLL to MAIN_CLK. */
652 kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2), /*!< Attach OSC32K to MAIN_CLK. */
653
654 kFRO_DIV1_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 0) |
655 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach Fro_DIV1 to DSP_MAIN_CLK. */
656 kOSC_CLK_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 1) |
657 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach OSC_CLK to DSP_MAIN_CLK. */
658 kLPOSC_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 2) |
659 CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0), /*!< Attach LPOSC to DSP_MAIN_CLK. */
660 kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1), /*!< Attach MAIN_PLL to DSP_MAIN_CLK. */
661 kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2), /*!< Attach DSP_PLL to DSP_MAIN_CLK. */
662 kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3), /*!< Attach OSC32K to DSP_MAIN_CLK. */
663
664 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to UTICK_CLK. */
665 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to UTICK_CLK. */
666
667 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT0_CLK. */
668 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT0_CLK. */
669
670 kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0), /*!< Attach LPOSC to WDT1_CLK. */
671 kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to WDT1_CLK. */
672
673 kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 0), /*!< Attach OSC32K to 32KHZWAKE_CLK. */
674 kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 1), /*!< Attach LPOSC_DIV32
675 to 32KHZWAKE_CLK. */
676 kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKSEL_OFFSET, 7), /*!< Attach NONE to 32KHZWAKE_CLK. */
677
678 kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK_DIV
679 to SYSTICK_CLK. */
680 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1), /*!< Attach LPOSC to SYSTICK_CLK. */
681 kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2), /*!< Attach OSC32K to SYSTICK_CLK. */
682 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7), /*!< Attach NONE to SYSTICK_CLK. */
683
684 kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO0_CLK. */
685 kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO0_CLK. */
686 kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO0_CLK. */
687 kFRO_DIV2_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV2 to SDIO0_CLK. */
688 kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO0_CLK. */
689 kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO0_CLK. */
690
691 kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SDIO1_CLK. */
692 kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SDIO1_CLK. */
693 kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SDIO1_CLK. */
694 kFRO_DIV2_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV2 to SDIO1_CLK. */
695 kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SDIO1_CLK. */
696 kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7), /*!< Attach NONE to SDIO1_CLK. */
697
698 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER0. */
699 kFRO_DIV1_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER0. */
700 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER0. */
701 kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER0. */
702 k32K_WAKE_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER0. */
703 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER0. */
704
705 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER1. */
706 kFRO_DIV1_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER1. */
707 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER1. */
708 kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER1. */
709 k32K_WAKE_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER1. */
710 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER1. */
711
712 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER2. */
713 kFRO_DIV1_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER2. */
714 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER2. */
715 kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER2. */
716 k32K_WAKE_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER2. */
717 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER2. */
718
719 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER3. */
720 kFRO_DIV1_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER3. */
721 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER3. */
722 kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER3. */
723 k32K_WAKE_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER3. */
724 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER3. */
725
726 kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to CTIMER4. */
727 kFRO_DIV1_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to CTIMER4. */
728 kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2), /*!< Attach AUDIO_PLL to CTIMER4. */
729 kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3), /*!< Attach MASTER_CLK to CTIMER4. */
730 k32K_WAKE_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to CTIMER4. */
731 kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7), /*!< Attach NONE to CTIMER4. */
732
733 kMAIN_CLK_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to FLEXSPI0_CLK. */
734 kMAIN_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to FLEXSPI0_CLK. */
735 kAUX0_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to FLEXSPI0_CLK. */
736 kFRO_DIV1_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to FLEXSPI0_CLK. */
737 kAUX1_PLL_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to FLEXSPI0_CLK. */
738 kFRO_DIV4_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 5), /*!< Attach FRO_DIV4 to FLEXSPI0_CLK. */
739 kFRO_DIV8_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 6), /*!< Attach FRO_DIV8 to FLEXSPI0_CLK. */
740 kNONE_to_FLEXSPI0_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXSPI0_CLK. */
741
742 kMAIN_CLK_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to FLEXSPI1_CLK. */
743 kMAIN_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to FLEXSPI1_CLK. */
744 kAUX0_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to FLEXSPI1_CLK. */
745 kFRO_DIV1_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to FLEXSPI1_CLK. */
746 kAUX1_PLL_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to FLEXSPI1_CLK. */
747 kNONE_to_FLEXSPI1_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXSPI1_CLK. */
748
749 kOSC_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0), /*!< Attach OSC_CLK to USB_CLK. */
750 kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1), /*!< Attach MAIN_CLK to USB_CLK. */
751 kAUX0_PLL_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 3), /*!< Attach AUX0_PLL to USB_CLK. */
752 kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7), /*!< Attach NONE to USB_CLK. */
753
754 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
755 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to SCT_CLK. */
756 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to SCT_CLK. */
757 kFRO_DIV1_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3), /*!< Attach FRO_DIV1 to SCT_CLK. */
758 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to SCT_CLK. */
759 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5), /*!< Attach AUDIO_PLL to SCT_CLK. */
760 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7), /*!< Attach NONE to SCT_CLK. */
761
762 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 0), /*!< Attach LPOSC to OSTIMER_CLK. */
763 kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 1), /*!< Attach OSC32K to OSTIMER_CLK. */
764 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 2), /*!< Attach HCLK to OSTIMER_CLK. */
765 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTTFCLKSEL_OFFSET, 7), /*!< Attach NONE to OSTIMER_CLK. */
766
767 kFRO_DIV8_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV8 to MCLK_CLK. */
768 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to MCLK_CLK. */
769 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7), /*!< Attach NONE to MCLK_CLK. */
770
771 kFRO_DIV4_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to DMIC. */
772 kAUDIO_PLL_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to DMIC. */
773 kMASTER_CLK_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to DMIC. */
774 kLPOSC_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3), /*!< Attach LPOSC to DMIC. */
775 k32K_WAKE_CLK_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4), /*!< Attach 32K_WAKE_CLK to DMIC. */
776 kNONE_to_DMIC = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to DMIC. */
777
778 kFRO_DIV4_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM0. */
779 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM0. */
780 kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM0. */
781 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM0. */
782 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM0. */
783
784 kFRO_DIV4_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM1. */
785 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM1. */
786 kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM1. */
787 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM1. */
788 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM1. */
789
790 kFRO_DIV4_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM2. */
791 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM2. */
792 kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM2. */
793 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM2. */
794 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM2. */
795
796 kFRO_DIV4_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM3. */
797 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM3. */
798 kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM3. */
799 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM3. */
800 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM3. */
801
802 kFRO_DIV4_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM4. */
803 kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM4. */
804 kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM4. */
805 kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM4. */
806 kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM4. */
807
808 kFRO_DIV4_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM5. */
809 kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM5. */
810 kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM5. */
811 kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM5. */
812 kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM5. */
813
814 kFRO_DIV4_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM6. */
815 kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM6. */
816 kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM6. */
817 kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM6. */
818 kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM6. */
819
820 kFRO_DIV4_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM7. */
821 kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM7. */
822 kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM7. */
823 kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM7. */
824 kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM7. */
825
826 kFRO_DIV4_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM8. */
827 kAUDIO_PLL_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM8. */
828 kMASTER_CLK_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM8. */
829 kFRG_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM8. */
830 kNONE_to_FLEXCOMM8 = CLKCTL1_TUPLE_MUXA(FC8FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM8. */
831
832 kFRO_DIV4_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM9. */
833 kAUDIO_PLL_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM9. */
834 kMASTER_CLK_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM9. */
835 kFRG_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM9. */
836 kNONE_to_FLEXCOMM9 = CLKCTL1_TUPLE_MUXA(FC9FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM9. */
837
838 kFRO_DIV4_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM10. */
839 kAUDIO_PLL_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM10. */
840 kMASTER_CLK_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM10. */
841 kFRG_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM10. */
842 kNONE_to_FLEXCOMM10 = CLKCTL1_TUPLE_MUXA(FC10FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM10. */
843
844 kFRO_DIV4_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM11. */
845 kAUDIO_PLL_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM11. */
846 kMASTER_CLK_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM11. */
847 kFRG_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM11. */
848 kNONE_to_FLEXCOMM11 = CLKCTL1_TUPLE_MUXA(FC11FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM11. */
849
850 kFRO_DIV4_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM12. */
851 kAUDIO_PLL_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM12. */
852 kMASTER_CLK_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM12. */
853 kFRG_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM12. */
854 kNONE_to_FLEXCOMM12 = CLKCTL1_TUPLE_MUXA(FC12FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM12. */
855
856 kFRO_DIV4_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM13. */
857 kAUDIO_PLL_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM13. */
858 kMASTER_CLK_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM13. */
859 kFRG_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM13. */
860 kNONE_to_FLEXCOMM13 = CLKCTL1_TUPLE_MUXA(FC13FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM13. */
861
862 kFRO_DIV4_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM14. */
863 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM14. */
864 kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM14. */
865 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM14. */
866 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM14. */
867
868 kFRO_DIV4_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM15. */
869 kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM15. */
870 kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM15. */
871 kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM15. */
872 kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM15. */
873
874 kFRO_DIV4_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV4 to FLEXCOMM16. */
875 kAUDIO_PLL_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXCOMM16. */
876 kMASTER_CLK_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXCOMM16. */
877 kFRG_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXCOMM16. */
878 kNONE_to_FLEXCOMM16 = CLKCTL1_TUPLE_MUXA(FC16FCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXCOMM16. */
879
880 kFRO_DIV2_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV2 to FLEXIO. */
881 kAUDIO_PLL_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 1), /*!< Attach AUDIO_PLL to FLEXIO. */
882 kMASTER_CLK_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 2), /*!< Attach MASTER_CLK to FLEXIO. */
883 kFRG_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 3), /*!< Attach FRG to FLEXIO. */
884 kNONE_to_FLEXIO = CLKCTL1_TUPLE_MUXA(FLEXIOCLKSEL_OFFSET, 7), /*!< Attach NONE to FLEXIO. */
885
886 kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to I3C_CLK. */
887 kFRO_DIV8_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV8 to I3C_CLK. */
888 kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSEL_OFFSET, 7), /*!< Attach NONE to I3C_CLK. */
889
890 kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 0), /*!< Attach I3C_CLK to I3C_TC_CLK. */
891 kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 1), /*!< Attach LPOSC to I3C_TC_CLK. */
892 kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCSEL_OFFSET, 7), /*!< Attach NONE to I3C_TC_CLK. */
893
894 kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to ACMP_CLK. */
895 kFRO_DIV4_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV4 to ACMP_CLK. */
896 kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to ACMP_CLK. */
897 kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL to ACMP_CLK. */
898 kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7), /*!< Attach NONE to ACMP_CLK. */
899
900 kOSC_CLK_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 0) |
901 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach OSC_CLK to ADC_CLK. */
902 kLPOSC_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 1) |
903 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach LPOSC to ADC_CLK. */
904 kFRO_DIV4_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 2) |
905 CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0), /*!< Attach FRO_DIV4 to ADC_CLK. */
906 kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to ADC_CLK. */
907 kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 2), /*!< Attach AUX0_PLL to ADC_CLK. */
908 kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3), /*!< Attach AUX1_PLL to ADC_CLK. */
909
910 kOSC_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 0) |
911 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach OSC_CLK to CLKOUT. */
912 kLPOSC_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 1) |
913 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach LPOSC to CLKOUT. */
914 kFRO_DIV2_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 2) |
915 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach FRO_DIV2 to CLKOUT. */
916 kMAIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 3) |
917 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach MAIN_CLK to CLKOUT. */
918 kDSP_MAIN_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 4) |
919 CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0), /*!< Attach DSP_MAIN to CLKOUT. */
920 kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1), /*!< Attach MAIN_PLL to CLKOUT. */
921 kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2), /*!< Attach AUX0_PLL to CLKOUT. */
922 kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3), /*!< Attach DSP_PLL to CLKOUT. */
923 kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4), /*!< Attach AUX1_PLL to CLKOUT. */
924 kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5), /*!< Attach AUDIO_PLL to CLKOUT. */
925 kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6), /*!< Attach OSC32K to CLKOUT. */
926 kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7), /*!< Attach NONE to CLKOUT. */
927
928 kMAIN_CLK_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 0), /*!< Attach MAIN_CLK to GPU_CLK. */
929 kFRO_DIV1_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV1 to GPU_CLK. */
930 kMAIN_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 2), /*!< Attach MAIN_PLL to GPU_CLK. */
931 kAUX0_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 3), /*!< Attach AUX0_PLL to GPU_CLK. */
932 kAUX1_PLL_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 4), /*!< Attach AUX1_PLL to GPU_CLK. */
933 kNONE_to_GPU_CLK = CLKCTL0_TUPLE_MUXA(GPUCLKSEL_OFFSET, 7), /*!< Attach NONE to GPU_CLK. */
934
935 kFRO_DIV1_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV1 to MIPI_DPHY_CLK. */
936 kMAIN_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 1), /*!< Attach MAIN_PLL to MIPI_DPHY_CLK. */
937 kAUX0_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL to MIPI_DPHY_CLK. */
938 kAUX1_PLL_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL to MIPI_DPHY_CLK. */
939 kNONE_to_MIPI_DPHY_CLK = CLKCTL0_TUPLE_MUXA(DPHYCLKSEL_OFFSET, 7), /*!< Attach NONE to MIPI_DPHY_CLK. */
940
941 kFRO_DIV1_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 0), /*!< Attach FRO_DIV1
942 to MIPI_DPHYESC_CLK. */
943 kFRO_DIV16_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 1), /*!< Attach FRO_DIV16
944 to MIPI_DPHYESC_CLK. */
945 kAUX0_PLL_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 2), /*!< Attach AUX0_PLL
946 to MIPI_DPHYESC_CLK. */
947 kAUX1_PLL_to_MIPI_DPHYESC_CLK = CLKCTL0_TUPLE_MUXA(DPHYESCCLKSEL_OFFSET, 3), /*!< Attach AUX1_PLL
948 to MIPI_DPHYESC_CLK. */
949
950 kMIPI_DPHY_CLK_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 0), /*!< Attach MIPI_DPHY_CLK
951 to DCPIXEL_CLK. */
952 kMAIN_CLK_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 1), /*!< Attach MAIN_CLK to DCPIXEL_CLK. */
953 kFRO_DIV1_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 2), /*!< Attach FRO_DIV1 to DCPIXEL_CLK. */
954 kMAIN_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 3), /*!< Attach MAIN_PLL to DCPIXEL_CLK. */
955 kAUX0_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 4), /*!< Attach AUX0_PLL to DCPIXEL_CLK. */
956 kAUX1_PLL_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 5), /*!< Attach AUX1_PLL to DCPIXEL_CLK. */
957 kNONE_to_DCPIXEL_CLK = CLKCTL0_TUPLE_MUXA(DCPIXELCLKSEL_OFFSET, 7), /*!< Attach NONE to DCPIXEL_CLK. */
958 } clock_attach_id_t;
959
960 /*! @brief Clock dividers */
961 typedef enum _clock_div_name
962 {
963 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0), /*!< Audio Pll Clk Divider. */
964 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0), /*!< Main Pll Clk Divider. */
965 kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0), /*!< Dsp Pll Clk Divider. */
966 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0), /*!< Aux0 Pll Clk Divider. */
967 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0), /*!< Aux1 Pll Clk Divider. */
968 kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0), /*!< Pfc0 Clk Divider. */
969 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0), /*!< Pfc1 Clk Divider. */
970 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0), /*!< Sys Cpu Ahb Clk Divider. */
971 kCLOCK_Div32KhzWakeClk = CLKCTL0_TUPLE_MUXA(A32KHZWAKECLKDIV_OFFSET, 0), /*!< Khz Wake Clk Divider. */
972 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0), /*!< Systick Clk Divider. */
973 kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0), /*!< Sdio0 Clk Divider. */
974 kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0), /*!< Sdio1 Clk Divider. */
975 kCLOCK_DivFlexspi0Clk = CLKCTL0_TUPLE_MUXA(FLEXSPI0FCLKDIV_OFFSET, 0), /*!< Flexspi0 Clk Divider. */
976 kCLOCK_DivFlexspi1Clk = CLKCTL0_TUPLE_MUXA(FLEXSPI1FCLKDIV_OFFSET, 0), /*!< Flexspi1 Clk Divider. */
977 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0), /*!< Usb Hs Fclk Divider. */
978 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0), /*!< Sct Clk Divider. */
979 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0), /*!< Mclk Clk Divider. */
980 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0), /*!< Dmic Clk Divider. */
981 kCLOCK_DivPLLFRGClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0), /*!< P L L F R G Clk Divider. */
982 kCLOCK_DivFlexioClk = CLKCTL1_TUPLE_MUXA(FLEXIOCLKDIV_OFFSET, 0), /*!< Flexio Clk Divider. */
983 kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */
984 kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. */
985 kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSDIV_OFFSET, 0), /*!< I3c Slow Clk Divider. */
986 kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0), /*!< Dsp Cpu Clk Divider. */
987 kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0), /*!< Acmp Clk Divider. */
988 kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0), /*!< Adc Clk Divider. */
989 kCLOCK_DivLowFreqClk = CLKCTL0_TUPLE_MUXA(LOWFREQCLKDIV_OFFSET, 0), /*!< Low Freq Clk Divider. */
990 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTFCLKDIV_OFFSET, 0), /*!< Clock Out Divider. */
991 kCLOCK_DivGpuClk = CLKCTL0_TUPLE_MUXA(GPUCLKDIV_OFFSET, 0), /*!< Gpu Clk Divider. */
992 kCLOCK_DivDcPixelClk = CLKCTL0_TUPLE_MUXA(DCPIXELCLKDIV_OFFSET, 0), /*!< Dc Pixel Clk Divider. */
993 kCLOCK_DivDphyClk = CLKCTL0_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< Dphy Clk Divider. */
994 kCLOCK_DivDphyEscRxClk = CLKCTL0_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< Dphy Esc Rx Clk Divider. */
995 kCLOCK_DivDphyEscTxClk = CLKCTL0_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< Dphy Esc Tx Clk Divider. */
996 } clock_div_name_t;
997
998 /*! @brief SysPLL Reference Input Clock Source */
999 typedef enum _sys_pll_src
1000 {
1001 kCLOCK_SysPllFroDiv8Clk = 0, /*!< FRO_DIV8 clock */
1002 kCLOCK_SysPllXtalIn = 1, /*!< OSC clock */
1003 kCLOCK_SysPllNone = 7 /*!< Gated to reduce power */
1004 } sys_pll_src_t;
1005
1006 /*! @brief SysPLL Multiplication Factor */
1007 typedef enum _sys_pll_mult
1008 {
1009 kCLOCK_SysPllMult16 = 0, /*!< Divide by 16 */
1010 kCLOCK_SysPllMult17, /*!< Divide by 17 */
1011 kCLOCK_SysPllMult18, /*!< Divide by 18 */
1012 kCLOCK_SysPllMult19, /*!< Divide by 19 */
1013 kCLOCK_SysPllMult20, /*!< Divide by 20 */
1014 kCLOCK_SysPllMult21, /*!< Divide by 21 */
1015 kCLOCK_SysPllMult22, /*!< Divide by 22 */
1016 } sys_pll_mult_t;
1017
1018 /*! @brief PLL configuration for SYSPLL */
1019 typedef struct _clock_sys_pll_config
1020 {
1021 sys_pll_src_t sys_pll_src; /*!< Reference Input Clock Source */
1022 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
1023 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
1024 sys_pll_mult_t sys_pll_mult; /*!< Multiplication Factor */
1025 } clock_sys_pll_config_t;
1026
1027 /*! @brief AudioPll Reference Input Clock Source */
1028 typedef enum _audio_pll_src
1029 {
1030 kCLOCK_AudioPllFroDiv8Clk = 0, /*!< FRO_DIV8 clock */
1031 kCLOCK_AudioPllXtalIn = 1, /*!< OSC clock */
1032 kCLOCK_AudioPllNone = 7 /*!< Gated to reduce power */
1033 } audio_pll_src_t;
1034
1035 /*! @brief AudioPll Multiplication Factor */
1036 typedef enum _audio_pll_mult
1037 {
1038 kCLOCK_AudioPllMult16 = 0, /*!< Divide by 16 */
1039 kCLOCK_AudioPllMult17, /*!< Divide by 17 */
1040 kCLOCK_AudioPllMult18, /*!< Divide by 18 */
1041 kCLOCK_AudioPllMult19, /*!< Divide by 19 */
1042 kCLOCK_AudioPllMult20, /*!< Divide by 20 */
1043 kCLOCK_AudioPllMult21, /*!< Divide by 21 */
1044 kCLOCK_AudioPllMult22, /*!< Divide by 22 */
1045 } audio_pll_mult_t;
1046
1047 /*! @brief PLL configuration for SYSPLL */
1048 typedef struct _clock_audio_pll_config
1049 {
1050 audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source */
1051 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
1052 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
1053 audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor */
1054 } clock_audio_pll_config_t;
1055
1056 /*! @brief PLL configuration for FRG */
1057 typedef struct _clock_frg_clk_config
1058 {
1059 uint8_t num; /*!< FRG clock, [0 - 16]: Flexcomm, [17]: Flexio */
1060 enum
1061 {
1062 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
1063 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
1064 kCLOCK_FrgFroDiv4, /*!< FRO_DIV4 */
1065 } sfg_clock_src;
1066 uint8_t divider; /*!< Denominator of the fractional divider. */
1067 uint8_t mult; /*!< Numerator of the fractional divider. */
1068 } clock_frg_clk_config_t;
1069
1070 /*! @brief FRO output enable */
1071 typedef enum _clock_fro_output_en
1072 {
1073 kCLOCK_FroDiv1OutEn = CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK, /*!< Enable Fro Div1 output. */
1074 kCLOCK_FroDiv2OutEn = CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK, /*!< Enable Fro Div2 output. */
1075 kCLOCK_FroDiv4OutEn = CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK, /*!< Enable Fro Div4 output. */
1076 kCLOCK_FroDiv8OutEn = CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK, /*!< Enable Fro Div8 output. */
1077 kCLOCK_FroDiv16OutEn = CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK, /*!< Enable Fro Div16 output. */
1078 kCLOCK_FroAllOutEn = CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK | CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK |
1079 CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK | CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK |
1080 CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK
1081 } clock_fro_output_en_t;
1082
1083 /*! @brief FRO frequence configuration */
1084 typedef enum _clock_fro_freq
1085 {
1086 kCLOCK_Fro192M, /*!< 192MHz FRO clock. */
1087 kCLOCK_Fro96M, /*!< 96MHz FRO clock. */
1088 } clock_fro_freq_t;
1089
1090 /*******************************************************************************
1091 * API
1092 ******************************************************************************/
1093
1094 #if defined(__cplusplus)
1095 extern "C" {
1096 #endif /* __cplusplus */
1097
CLOCK_EnableClock(clock_ip_name_t clk)1098 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
1099 {
1100 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
1101
1102 switch (index)
1103 {
1104 case CLK_CTL0_PSCCTL0:
1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1106 break;
1107 case CLK_CTL0_PSCCTL1:
1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1109 break;
1110 case CLK_CTL0_PSCCTL2:
1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1112 break;
1113 case CLK_CTL1_PSCCTL0:
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1115 break;
1116 case CLK_CTL1_PSCCTL1:
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1118 break;
1119 case CLK_CTL1_PSCCTL2:
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1121 break;
1122 default:
1123 assert(false);
1124 break;
1125 }
1126 }
1127
CLOCK_DisableClock(clock_ip_name_t clk)1128 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
1129 {
1130 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
1131 switch (index)
1132 {
1133 case CLK_CTL0_PSCCTL0:
1134 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1135 break;
1136 case CLK_CTL0_PSCCTL1:
1137 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1138 break;
1139 case CLK_CTL0_PSCCTL2:
1140 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1141 break;
1142 case CLK_CTL1_PSCCTL0:
1143 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1144 break;
1145 case CLK_CTL1_PSCCTL1:
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1147 break;
1148 case CLK_CTL1_PSCCTL2:
1149 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
1150 break;
1151 default:
1152 assert(false);
1153 break;
1154 }
1155 }
1156
1157 /**
1158 * @brief Configure the clock selection muxes.
1159 * @param connection : Clock to be configured.
1160 * @return Nothing
1161 */
1162 void CLOCK_AttachClk(clock_attach_id_t connection);
1163
1164 /**
1165 * @brief Setup peripheral clock dividers.
1166 * @param div_name : Clock divider name
1167 * @param divider : Value to be divided. Divided clock frequency = Undivided clock frequency / divider.
1168 * @return Nothing
1169 */
1170 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
1171
1172 /*! @brief Return Frequency of selected clock
1173 * @return Frequency of selected clock
1174 */
1175 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1176
1177 /*! @brief Return Input frequency for the Fractional baud rate generator
1178 * @return Input Frequency for FRG
1179 */
1180 uint32_t CLOCK_GetFRGClock(uint32_t id);
1181
1182 /*! @brief Set output of the Fractional baud rate generator
1183 * @param config : Configuration to set to FRGn clock.
1184 */
1185 void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
1186
1187 /*! @brief Return Frequency of SYSPLL
1188 * @return Frequency of SYSPLL
1189 */
1190 uint32_t CLOCK_GetSysPllFreq(void);
1191
1192 /*! @brief Get current output frequency of specific System PLL PFD.
1193 * @param pfd : pfd name to get frequency.
1194 * @return Frequency of SYSPLL PFD.
1195 */
1196 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1197
1198 /*! @brief Return Frequency of AUDIO PLL
1199 * @return Frequency of AUDIO PLL
1200 */
1201 uint32_t CLOCK_GetAudioPllFreq(void);
1202
1203 /*! @brief Get current output frequency of specific Audio PLL PFD.
1204 * @param pfd : pfd name to get frequency.
1205 * @return Frequency of AUDIO PLL PFD.
1206 */
1207 uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
1208
1209 /*! @brief Return Frequency of main clk
1210 * @return Frequency of main clk
1211 */
1212 uint32_t CLOCK_GetMainClkFreq(void);
1213
1214 /*! @brief Return Frequency of DSP main clk
1215 * @return Frequency of DSP main clk
1216 */
1217 uint32_t CLOCK_GetDspMainClkFreq(void);
1218
1219 /*! @brief Return Frequency of ACMP clk
1220 * @return Frequency of ACMP clk
1221 */
1222 uint32_t CLOCK_GetAcmpClkFreq(void);
1223
1224 /*! @brief Return Frequency of DMIC clk
1225 * @return Frequency of DMIC clk
1226 */
1227 uint32_t CLOCK_GetDmicClkFreq(void);
1228
1229 /*! @brief Return Frequency of USB clk
1230 * @return Frequency of USB clk
1231 */
1232 uint32_t CLOCK_GetUsbClkFreq(void);
1233
1234 /*! @brief Return Frequency of SDIO clk
1235 * @param id : SDIO index to get frequency.
1236 * @return Frequency of SDIO clk
1237 */
1238 uint32_t CLOCK_GetSdioClkFreq(uint32_t id);
1239
1240 /*! @brief Return Frequency of I3C clk
1241 * @return Frequency of I3C clk
1242 */
1243 uint32_t CLOCK_GetI3cClkFreq(void);
1244
1245 /*! @brief Return Frequency of systick clk
1246 * @return Frequency of systick clk
1247 */
1248 uint32_t CLOCK_GetSystickClkFreq(void);
1249
1250 /*! @brief Return Frequency of WDT clk
1251 * @param id : WDT index to get frequency.
1252 * @return Frequency of WDT clk
1253 */
1254 uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
1255
1256 /*! @brief Return output Frequency of mclk
1257 * @return Frequency of mclk output clk
1258 */
1259 uint32_t CLOCK_GetMclkClkFreq(void);
1260
1261 /*! @brief Return Frequency of sct
1262 * @return Frequency of sct clk
1263 */
1264 uint32_t CLOCK_GetSctClkFreq(void);
1265
1266 /*! @brief Enable/Disable sys osc clock from external crystal clock.
1267 * @param enable : true to enable system osc clock, false to bypass system osc.
1268 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1269 * @param delay_us : Delay time after OSC power up.
1270 */
1271 void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
1272
1273 /*! @brief Enable/Disable FRO clock output.
1274 * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
1275 */
1276 void CLOCK_EnableFroClk(uint32_t divOutEnable);
1277
1278 /*! @brief Enable/Disable FRO clock output with specified frequency using the FRO Tuner.
1279 * @param targetFreq target fro frequency.
1280 * @param divOutEnable Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
1281 */
1282 void CLOCK_EnableFroClkFreq(uint32_t targetFreq, uint32_t divOutEnable);
1283
1284 #ifndef __XTENSA__
1285 /*! @brief Enable/Disable FRO192M or FRO96M clock output.
1286 * @param froFreq : target fro frequency.
1287 * @param divOutEnable : Or'ed value of clock_fro_output_en_t to enable certain clock freq output.
1288 */
1289 void CLOCK_EnableFroClkRange(clock_fro_freq_t froFreq, uint32_t divOutEnable);
1290 #endif /* __XTENSA__ */
1291
1292 /*! @brief Enable LPOSC 1MHz clock.
1293 */
1294 void CLOCK_EnableLpOscClk(void);
1295
1296 /*! @brief Return Frequency of sys osc Clock
1297 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
1298 */
CLOCK_GetXtalInClkFreq(void)1299 static inline uint32_t CLOCK_GetXtalInClkFreq(void)
1300 {
1301 return (CLKCTL0->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
1302 }
1303
1304 /*! @brief Return Frequency of MCLK Input Clock
1305 * @return Frequency of MCLK input Clock.
1306 */
CLOCK_GetMclkInClkFreq(void)1307 static inline uint32_t CLOCK_GetMclkInClkFreq(void)
1308 {
1309 return g_mclkFreq;
1310 }
1311
1312 /*! @brief Return Frequency of Lower power osc
1313 * @return Frequency of LPOSC
1314 */
CLOCK_GetLpOscFreq(void)1315 static inline uint32_t CLOCK_GetLpOscFreq(void)
1316 {
1317 return CLK_LPOSC_1MHZ;
1318 }
1319
1320 /*! @brief Return Frequency of 32kHz osc
1321 * @return Frequency of 32kHz osc
1322 */
CLOCK_GetOsc32KFreq(void)1323 static inline uint32_t CLOCK_GetOsc32KFreq(void)
1324 {
1325 return ((CLKCTL0->OSC32KHZCTL0 & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK) != 0UL) ? CLK_RTC_32K_CLK : 0U;
1326 }
1327
1328 /*! @brief Enables and disables 32kHz osc
1329 * @param enable : true to enable 32k osc clock, false to disable clock
1330 */
CLOCK_EnableOsc32K(bool enable)1331 static inline void CLOCK_EnableOsc32K(bool enable)
1332 {
1333 if (enable)
1334 {
1335 CLKCTL0->OSC32KHZCTL0 |= CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1336 }
1337 else
1338 {
1339 CLKCTL0->OSC32KHZCTL0 &= ~CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1340 }
1341 }
1342
1343 /*! @brief Return Frequency of 32khz wake clk
1344 * @return Frequency of 32kHz wake clk
1345 */
CLOCK_GetWakeClk32KFreq(void)1346 static inline uint32_t CLOCK_GetWakeClk32KFreq(void)
1347 {
1348 return ((CLKCTL0->A32KHZWAKECLKSEL & CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK) != 0U) ?
1349 CLOCK_GetLpOscFreq() / ((CLKCTL0->A32KHZWAKECLKDIV & CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK) + 1U) :
1350 CLOCK_GetOsc32KFreq();
1351 }
1352
1353 /*!
1354 * @brief Set the XTALIN (system OSC) frequency based on board setting.
1355 *
1356 * @param freq : The XTAL input clock frequency in Hz.
1357 */
CLOCK_SetXtalFreq(uint32_t freq)1358 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1359 {
1360 g_xtalFreq = freq;
1361 }
1362
1363 /*!
1364 * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
1365 *
1366 * @param freq : The CLK_IN pin input clock frequency in Hz.
1367 */
CLOCK_SetClkinFreq(uint32_t freq)1368 static inline void CLOCK_SetClkinFreq(uint32_t freq)
1369 {
1370 g_clkinFreq = freq;
1371 }
1372
1373 /*!
1374 * @brief Set the MCLK IN frequency based on board setting.
1375 *
1376 * @param freq : The MCLK input clock frequency in Hz.
1377 */
CLOCK_SetMclkFreq(uint32_t freq)1378 static inline void CLOCK_SetMclkFreq(uint32_t freq)
1379 {
1380 g_mclkFreq = freq;
1381 }
1382
1383 /*! @brief Return Frequency of Flexcomm functional Clock
1384 * @param id : flexcomm index to get frequency.
1385 * @return Frequency of Flexcomm functional Clock
1386 */
1387 uint32_t CLOCK_GetFlexcommClkFreq(uint32_t id);
1388
1389 /*! @brief Return Frequency of Flexio functional Clock
1390 * @return Frequency of Flexcomm functional Clock
1391 */
1392 uint32_t CLOCK_GetFlexioClkFreq(void);
1393
1394 /*! @brief Return Frequency of Ctimer Clock
1395 * @param id : ctimer index to get frequency.
1396 * @return Frequency of Ctimer Clock
1397 */
1398 uint32_t CLOCK_GetCtimerClkFreq(uint32_t id);
1399 /*! @brief Return Frequency of ClockOut
1400 * @return Frequency of ClockOut
1401 */
1402 uint32_t CLOCK_GetClockOutClkFreq(void);
1403 /*! @brief Return Frequency of Adc Clock
1404 * @return Frequency of Adc Clock.
1405 */
1406 uint32_t CLOCK_GetAdcClkFreq(void);
1407 /*! @brief Return Frequency of FLEXSPI Clock
1408 * @param id : flexspi index to get frequency.
1409 * @return Frequency of Flexspi.
1410 */
1411 uint32_t CLOCK_GetFlexspiClkFreq(uint32_t id);
1412
1413 /*! @brief Return Frequency of GPU functional Clock
1414 * @return Frequency of GPU functional Clock
1415 */
1416 uint32_t CLOCK_GetGpuClkFreq(void);
1417
1418 /*! @brief Return Frequency of DCNano Pixel functional Clock
1419 * @return Frequency of DCNano pixel functional Clock
1420 */
1421 uint32_t CLOCK_GetDcPixelClkFreq(void);
1422
1423 /*! @brief Return Frequency of MIPI DPHY functional Clock
1424 * @return Frequency of MIPI DPHY functional Clock
1425 */
1426 uint32_t CLOCK_GetMipiDphyClkFreq(void);
1427
1428 /*! @brief Return Frequency of MIPI DPHY Esc RX functional Clock
1429 * @return Frequency of MIPI DPHY Esc RX functional Clock
1430 */
1431 uint32_t CLOCK_GetMipiDphyEscRxClkFreq(void);
1432
1433 /*! @brief Return Frequency of MIPI DPHY Esc Tx functional Clock
1434 * @return Frequency of MIPI DPHY Esc Tx functional Clock
1435 */
1436 uint32_t CLOCK_GetMipiDphyEscTxClkFreq(void);
1437
1438 /*! @brief Initialize the System PLL.
1439 * @param config : Configuration to set to PLL.
1440 */
1441 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1442
1443 /*! brief Deinit the System PLL.
1444 * param none.
1445 */
CLOCK_DeinitSysPll(void)1446 static inline void CLOCK_DeinitSysPll(void)
1447 {
1448 /* Set System PLL Reset & HOLDRINGOFF_ENA */
1449 CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL0_SYSPLL0CTL0_RESET_MASK;
1450 /* Power down System PLL*/
1451 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1452 }
1453
1454 /*! @brief Initialize the System PLL PFD.
1455 * @param pfd : Which PFD clock to enable.
1456 * @param divider : The PFD divider value.
1457 * @note It is recommended that PFD settings are kept between 12-35.
1458 */
1459 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider);
1460
1461 /*! brief Disable the audio PLL PFD.
1462 * param pfd : Which PFD clock to disable.
1463 */
CLOCK_DeinitSysPfd(clock_pfd_t pfd)1464 static inline void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
1465 {
1466 CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK << (8U * (uint32_t)pfd));
1467 }
1468
1469 /*! @brief Initialize the audio PLL.
1470 * @param config : Configuration to set to PLL.
1471 */
1472 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1473
1474 /*! brief Deinit the Audio PLL.
1475 * param none.
1476 */
CLOCK_DeinitAudioPll(void)1477 static inline void CLOCK_DeinitAudioPll(void)
1478 {
1479 /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
1480 CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
1481 /* Power down Audio PLL */
1482 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1483 }
1484
1485 /*! @brief Initialize the audio PLL PFD.
1486 * @param pfd : Which PFD clock to enable.
1487 * @param divider : The PFD divider value.
1488 * @note It is recommended that PFD settings are kept between 12-35.
1489 */
1490 void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
1491
1492 /*! brief Disable the audio PLL PFD.
1493 * param pfd : Which PFD clock to disable.
1494 */
CLOCK_DeinitAudioPfd(uint32_t pfd)1495 static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
1496 {
1497 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8U * pfd));
1498 }
1499
1500 /*! @brief Tune the FRO to the specified frequency.
1501 * @param targetFreq The target frequency.
1502 * @retval true The FRO is tuned successfully.
1503 * @retval false The FRO is not tuned to the target frequency.
1504 * @note This API can be used to tune the FRO to an accurate frequency periodicly using the reference clock(crystal
1505 * oscillator). Make sure the reference clock is enabled before calling this API and the reference clock can be disabled
1506 * after this API call.
1507 */
1508 status_t CLOCK_FroTuneToFreq(uint32_t targetFreq);
1509
1510 /*! @brief Enable/Disable FRO tuning.
1511 * On enable, the function will wait until FRO is close to the target frequency.
1512 */
1513 void CLOCK_EnableFroTuning(bool enable);
1514
1515 /*! @brief Enable USB HS device clock.
1516 *
1517 * This function enables USB HS device clock.
1518 */
1519 void CLOCK_EnableUsbHs0DeviceClock(clock_attach_id_t src, uint8_t divider);
1520
1521 /*! @brief Disable USB HS device clock.
1522 *
1523 * This function disables USB HS device clock.
1524 */
1525 void CLOCK_DisableUsbHs0DeviceClock(void);
1526
1527 /*! @brief Enable USB HS host clock.
1528 *
1529 * This function enables USB HS host clock.
1530 */
1531 void CLOCK_EnableUsbHs0HostClock(clock_attach_id_t src, uint8_t divider);
1532
1533 /*! @brief Disable USB HS host clock.
1534 *
1535 * This function disables USB HS host clock.
1536 */
1537 void CLOCK_DisableUsbHs0HostClock(void);
1538
1539 /*! brief Enable USB hs0PhyPll clock.
1540 *
1541 * param src USB HS clock source.
1542 * param freq The frequency specified by src.
1543 * retval true The clock is set successfully.
1544 * retval false The clock source is invalid to get proper USB HS clock.
1545 */
1546 bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq);
1547
1548 /*! @brief Disable USB hs0PhyPll clock.
1549 *
1550 * This function disables USB hs0PhyPll clock.
1551 */
1552 void CLOCK_DisableUsbHs0PhyPllClock(void);
1553
1554 #if defined(__cplusplus)
1555 }
1556 #endif /* __cplusplus */
1557
1558 /*! @} */
1559
1560 #endif /* _FSL_CLOCK_H_ */
1561
