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/hal_nxp-3.7.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip_Irq.c549 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[0].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
580 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[1].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
611 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[2].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
642 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[3].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
702 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[4].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
733 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[5].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
764 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[6].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
795 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[7].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
855 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[8].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
886 … if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[9].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) ) in ISR()
[all …]
DEmios_Mcl_Ip.c194 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK; in Emios_Mcl_Ip_Init()
227 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_MODE((*ConfigPtr… in Emios_Mcl_Ip_Init()
229 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_UCPREN(1U); in Emios_Mcl_Ip_Init()
342 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].C = 0U; in Emios_Mcl_Ip_Deinit()
/hal_nxp-3.7.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h283 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FREN_MASK)) | eMIOS_C_FREN(ValueConve… in Emios_Pwm_Ip_SetFreezeEnable()
297 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODIS_MASK)) | eMIOS_C_ODIS(ValueConve… in Emios_Pwm_Ip_SetOutDisable()
310 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODISSL_MASK)) | eMIOS_C_ODISSL(Value); in Emios_Pwm_Ip_SetOutDisableSource()
326 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_UCPREN_MASK)) | eMIOS_C_UCPREN(ValueC… in Emios_Pwm_Ip_SetPrescalerEnable()
344 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_DMA_MASK)) | eMIOS_C_DMA(ValueConvert… in Emios_Pwm_Ip_SetDMARequest()
358 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDMARequest()
374 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FEN_MASK)) | eMIOS_C_FEN(ValueConvert… in Emios_Pwm_Ip_SetInterruptRequest()
388 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetInterruptRequest()
404 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMA_MASK)) | eMIOS_C_FORCMA(ValueC… in Emios_Pwm_Ip_SetForceMatchA()
420 …Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMB_MASK)) | eMIOS_C_FORCMB(ValueC… in Emios_Pwm_Ip_SetForceMatchB()
[all …]
/hal_nxp-3.7.0/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c349 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_MODE_MASK; in Emios_Icu_Ip_UCSetMode()
351 s_emiosBase[instance]->CH.UC[hwChannel].C |= (u32Mode & eMIOS_C_MODE_MASK); in Emios_Icu_Ip_UCSetMode()
408 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_UCPREN_MASK; in Emios_Icu_Ip_SetPrescaler()
414 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_UCPREN_MASK; in Emios_Icu_Ip_SetPrescaler()
495 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_FEN_MASK; in Emios_Icu_Ip_EnableInterrupt()
504 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_FEN_MASK; in Emios_Icu_Ip_DisableInterrupt()
589 s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32; in Emios_Icu_Ip_Init()
599 s_emiosBase[instance]->CH.UC[hwChannel].C |= u32RegCCR; in Emios_Icu_Ip_Init()
689 s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32; in Emios_Icu_Ip_Deinit()
776 u32Value_CCR_FEN = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_FEN_MASK); in Emios_Icu_Ip_SetNormalMode()
[all …]
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa/gdbio/
Dmemmap.xmm38 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
56 …dsp_core : C : 0x00200000 - 0x0047ffff : STACK : HEAP : .rodata .literal .text .data __llvm_prf_…
61 dsp_uncached : C : 0x20060000 - 0x2006ffff : NonCacheable.init NonCacheable ;
66 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa/min-rt/
Dmemmap.xmm36 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
54 …dsp_core : C : 0x00200000 - 0x0047ffff : STACK : HEAP : .rodata .literal .text .data __llvm_prf_…
59 dsp_uncached : C : 0x20060000 - 0x2006ffff : NonCacheable.init NonCacheable ;
64 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa/sim/
Dmemmap.xmm36 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
54 …dsp_core : C : 0x00200000 - 0x0047ffff : STACK : HEAP : .rodata .literal .text .data __llvm_prf_…
59 dsp_uncached : C : 0x20060000 - 0x2006ffff : NonCacheable.init NonCacheable ;
64 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…
/hal_nxp-3.7.0/mcux/mcux-sdk/components/conn_fwloader/
Dreadme_rc.txt25 loadbin C:\xxx\rw610w_raw_cpu1_xx.bin,0x08400000
28 loadbin C:\xxx\rw610n_raw_cpu2_ble_xx.bin,0x08540000
31 loadbin C:\xxx\rw610n_combo_raw_cpu2_ble_15_4_combo_xx.bin,0x085e0000
Dreadme.txt25 loadbin C:\xxx\rw61x_sb_wifi_xx.bin,0x08400000
28 loadbin C:\xxx\rw61x_sb_ble_xx.bin,0x08540000
31 loadbin C:\xxx\rw61x_sb_ble_15d4_combo_xx.bin,0x085e0000
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/
Dmemmap.xmm36 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
55 …dsp_core : C : 0x300000 - 0x47ffff : STACK : HEAP : .sram.rodata .clib.rodata .rtos.rodata .roda…
60 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…
77 dsp_uncached : C : 0x20040000 - 0x2007ffff : NonCacheable.init NonCacheable;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x820000 - 0x87ffff : .shmem;
85 dram1_0 : C : 0x880000 - 0x97ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x820000 - 0x87ffff : .shmem;
85 dram1_0 : C : 0x880000 - 0x97ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/xtensa/sim/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x820000 - 0x87ffff : .shmem;
85 dram1_0 : C : 0x880000 - 0x97ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD5/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD5/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US3/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US3/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US5/xtensa/gdbio/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8US5/xtensa/min-rt/
Dmemmap.xmm34 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
80 dram0_0 : C : 0x880000 - 0x88ffff : .shmem;
85 dram1_0 : C : 0x820000 - 0x82ffff : STACK : HEAP : .rodata .data .bss;
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/min-rt/
Dmemmap.xmm36 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
54 …sram0 : C : 0x4 - 0x23ffffff : STACK : HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sr…
59 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/gdbio/
Dmemmap.xmm41 // <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
59 …sram0 : C : 0x4 - 0x23ffffff : STACK : HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sr…
64 …dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.…

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