1 /*
2  * Copyright 2020-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /**
8  *     @file       File with source code used to implement ICU driver functionality on EMIOS module.
9  *     @details    This file contains the source code for all functions which are using EMIOS module.
10  *     @addtogroup emios_icu_ip EMIOS IPL
11  *     @{
12  */
13 #ifdef __cplusplus
14 extern "C"{
15 #endif
16 
17 /*==================================================================================================
18 *                                         INCLUDE FILES
19 * 1) system and project includes
20 * 2) needed interfaces from external units
21 * 3) internal and external interfaces from this unit
22 ==================================================================================================*/
23 #include "Emios_Icu_Ip.h"
24 #include "SchM_Icu.h"
25 
26 #if (STD_ON == EMIOS_ICU_IP_USED)
27     #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
28         #include "Devassert.h"
29     #endif
30 
31     #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
32         #define USER_MODE_REG_PROT_ENABLED  (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
33         #include "RegLockMacros.h"
34     #endif
35 
36     #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
37         #include "Dma_Ip.h"
38     #endif
39 
40 #endif  /* EMIOS_ICU_IP_USED */
41 /*==================================================================================================
42 *                                        LOCAL MACROS
43 ==================================================================================================*/
44 #define EMIOS_ICU_IP_VENDOR_ID_C                       43
45 #define EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C        4
46 #define EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C        7
47 #define EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION_C     0
48 #define EMIOS_ICU_IP_SW_MAJOR_VERSION_C                3
49 #define EMIOS_ICU_IP_SW_MINOR_VERSION_C                0
50 #define EMIOS_ICU_IP_SW_PATCH_VERSION_C                0
51 
52 /*==================================================================================================
53 *                                      FILE VERSION CHECKS
54 ==================================================================================================*/
55 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
56     #if (STD_ON == EMIOS_ICU_IP_USED)
57         #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
58             /* Check if the files Emios_Icu_Ip.c and RegLockMacros.h are of the same version */
59             #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
60                 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
61                 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and RegLockMacros.h are different"
62             #endif
63         #endif
64 
65         #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
66             /* Check if header file and Dma_Ip.h file are of the same Autosar version */
67             #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != DMA_IP_AR_RELEASE_MAJOR_VERSION) || \
68                  (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != DMA_IP_AR_RELEASE_MINOR_VERSION))
69                 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Dma_Ip.h are different"
70             #endif
71         #endif
72     #endif  /* EMIOS_ICU_IP_USED */
73 
74     /* Check if this header file and SchM_Icu.h file are of the same Autosar version */
75     #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION != SCHM_ICU_AR_RELEASE_MAJOR_VERSION) || \
76         (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION != SCHM_ICU_AR_RELEASE_MINOR_VERSION))
77         #error "AutoSar Version Numbers of Emios_Icu_Ip.c and SchM_Icu.h are different"
78     #endif
79 #endif
80 
81 /* Check if source file and ICU header file are of the same vendor */
82 #if (EMIOS_ICU_IP_VENDOR_ID_C != EMIOS_ICU_IP_VENDOR_ID)
83     #error "Emios_Icu_Ip.c and Emios_Icu_Ip.h have different vendor IDs"
84 #endif
85 /* Check if source file and Emios_Icu_Ip header file are of the same Autosar version */
86 #if (  (EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION) || \
87        (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION) || \
88        (EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION))
89     #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Emios_Icu_Ip.h are different"
90 #endif
91 /* Check if source file and Icu_eMIOS header file are of the same Software version */
92 #if ((EMIOS_ICU_IP_SW_MAJOR_VERSION_C != EMIOS_ICU_IP_SW_MAJOR_VERSION) || \
93         (EMIOS_ICU_IP_SW_MINOR_VERSION_C != EMIOS_ICU_IP_SW_MINOR_VERSION) || \
94         (EMIOS_ICU_IP_SW_PATCH_VERSION_C != EMIOS_ICU_IP_SW_PATCH_VERSION))
95     #error "Software Version Numbers of Emios_Icu_Ip.c and Emios_Icu_Ip.h are different"
96 #endif
97 
98 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
99     #if (STD_ON == EMIOS_ICU_IP_USED)
100         #if(EMIOS_ICU_IP_DEV_ERROR_DETECT == STD_ON)
101             /* Check if this header file and Devassert.h file are of the same Autosar version */
102             #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
103                 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION))
104                 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Devassert.h are different"
105             #endif
106         #endif
107     #endif  /* EMIOS_ICU_IP_USED */
108 #endif
109 /*==================================================================================================
110 *                                           LOCAL MACROS
111 ==================================================================================================*/
112 #if (STD_ON == EMIOS_ICU_IP_USED)
113     #if (defined (MCAL_EMIOS_REG_PROT_AVAILABLE))
114         #if ((STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
115             #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr) OsIf_Trusted_Call1param(Emios_Icu_Ip_SetUserAccessAllowed,(BaseAddr))
116         #else
117             #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
118         #endif
119     #else
120         #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
121     #endif
122 #endif  /* EMIOS_ICU_IP_USED */
123 /*==================================================================================================
124 *                                       LOCAL CONSTANTS
125 ==================================================================================================*/
126 
127 
128 /*==================================================================================================
129 *                                       LOCAL VARIABLES
130 ==================================================================================================*/
131 #if (STD_ON == EMIOS_ICU_IP_USED)
132 
133 #define ICU_START_SEC_VAR_CLEARED_BOOLEAN
134 #include "Icu_MemMap.h"
135 
136 /* State of initialized EMIOS modules. */
137 static boolean eMios_Icu_Ip_bInstanceState[EMIOS_ICU_IP_INSTANCE_COUNT];
138 
139 #define ICU_STOP_SEC_VAR_CLEARED_BOOLEAN
140 #include "Icu_MemMap.h"
141 
142 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED
143 #include "Icu_MemMap.h"
144 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
145 static uint32 eMios_Icu_Ip_u32aEdgeCurrent_Value[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
146 #endif /* EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON */
147 
148 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
149 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
150 /**
151 * @brief      eMios_Icu_Ip_u8NumOvflByCounterBus
152 * @details    The number of active channels has the overflow notification function using masterbus.
153 */
154 static uint8 eMios_Icu_Ip_u8NumOvflByCounterBus[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS];
155 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
156 #endif /* ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)) */
157 
158 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
159 #include "Icu_MemMap.h"
160 
161 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
162 #include "Icu_MemMap.h"
163 
164 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
165 /** @brief Array for saving value of DMA **/
166 volatile uint32 Emios_Icu_Ip_aDmaBuffer[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED][EMIOS_ICU_IP_DMA_MAJORLOOP_COUNT];
167 
168 /** @brief Array for saving the period */
169 volatile uint32 Emios_Icu_Ip_aIsSecondInterrupt[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
170 
171 /** @brief Array for saving the period */
172 volatile uint32 Emios_Icu_Ip_aFirstEdgeTimeStamp[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
173 
174 #endif /* EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL */
175 
176 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
177 
178 #include "Icu_MemMap.h"
179 /*==================================================================================================
180                                        GLOBAL CONSTANTS
181 ==================================================================================================*/
182 #define ICU_START_SEC_CONST_UNSPECIFIED
183 #include "Icu_MemMap.h"
184 /* Table of base addresses for EMIOS instances. */
185 eMIOS_Type * const s_emiosBase[] = IP_eMIOS_BASE_PTRS;
186 #define ICU_STOP_SEC_CONST_UNSPECIFIED
187 #include "Icu_MemMap.h"
188 /*==================================================================================================
189 *                                       GLOBAL VARIABLES
190 ==================================================================================================*/
191 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED
192 #include "Icu_MemMap.h"
193 
194 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
195 eMios_Icu_Ip_MeasStatusType eMios_Icu_Ip_aeInt_Counter[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
196 eMios_Icu_ValueType eMios_Icu_Ip_CapturedActivePulseWidth[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
197 eMios_Icu_ValueType eMios_Icu_Ip_TimeStart[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
198 #endif /* EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON */
199 
200 #if (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)
201 eMios_Icu_ValueType eMios_Icu_Ip_BufferPtr[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
202 #endif /* EMIOS_ICU_IP_TIMESTAMP_API == STD_ON */
203 
204 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
205 #include "Icu_MemMap.h"
206 
207 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED
208 #include "Icu_MemMap.h"
209 eMios_Icu_Ip_ChStateType eMios_Icu_Ip_ChState[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
210 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
211 #include "Icu_MemMap.h"
212 
213 #define ICU_START_SEC_VAR_INIT_8
214 #include "Icu_MemMap.h"
215 /* This array stores the positions in the eMios_Icu_Ip_ChState array of the configured eMios channels. */
216 uint8 eMios_Icu_Ip_IndexInChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS] = EMIOS_ICU_IP_INITIAL_INDEX_OF_CHANNELS;
217 #define ICU_STOP_SEC_VAR_INIT_8
218 #include "Icu_MemMap.h"
219 
220 /*==================================================================================================
221 *                                   LOCAL FUNCTION PROTOTYPES
222 ==================================================================================================*/
223 #define ICU_START_SEC_CODE
224 #include "Icu_MemMap.h"
225 
226 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
227 extern void Emios_Icu_Ip_SignalMeasurementHandler(const uint8 instance, const uint8 hwChannel, boolean bOverflow);
228 #endif
229 
230 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
231 /**
232  * @brief      Icu driver function that sets the channel prescaler.
233  * @details    This function:
234  *             - Writes prescaling rate at UCPRE[0:1] bits in EMIOSC[n] register
235  *             - Enables channel prescaler by setting UCPREN bit in EMIOSC[n] register
236  *
237  * @param[in]  instance                - eMIOS module index
238  * @param[in]  hwChannel               - eMIOS encoded hardware channel
239  * @param[in]  u32ChannelPrescaler     - prescaler for the hardware channel
240  */
241 static inline void Emios_Icu_Ip_SetPrescaler
242 (
243     const uint8 instance,
244     const uint8 hwChannel,
245     const uint32 u32ChannelPrescaler
246 );
247 #endif  /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
248 
249 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
250 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
251 /**
252 * @brief      Icu driver function that enable the master buses Interrupt.
253 * @details    This function:
254 *             - Only using for the following functions:
255 *                   - Emios_Icu_Ip_StartSignalMeasurement: Used for enable master buses interrupt that hwChannel uses as an overflow notification.
256 *                   - Emios_Icu_Ip_StartTimestamp: Used for enable master buses interrupt that hwChannel uses as an overflow notification.
257 *
258 * @param[in]  instance        - eMIOS module index
259 * @param[in]  hwChannel       - eMIOS encoded hardware channel using master bus
260 * @api
261 */
262 static inline void Emios_Icu_Ip_EnableMasterBusInterrupt
263 (
264     const uint8 instance,
265     const uint8 hwChannel
266 );
267 
268 /**
269 * @brief      Icu driver function that disable the master buses Interrupt.
270 * @details    This function:
271 *             - Only using for the following functions:
272 *                   - Emios_Icu_Ip_StartSignalMeasurement: Used for disable master buses interrupt that hwChannel uses as an overflow notification.
273 *                   - Emios_Icu_Ip_StartTimestamp: Used for disable master buses interrupt that hwChannel uses as an overflow notification.
274 *
275 * @param[in]  instance        - eMIOS module index
276 * @param[in]  hwChannel       - eMIOS encoded hardware channel using master bus
277 * @api
278 */
279 static inline void Emios_Icu_Ip_DisableMasterBusInterrupt
280 (
281     const uint8 instance,
282     const uint8 hwChannel
283 );
284 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
285 #endif
286 
287 /**
288 * @brief      Emios_Icu_Ip_UCSetMode
289 * @details    This function sets CCR_MODE bitfield, the mode of operation of the Unified Channel
290 *
291 * @param[in]  instance  - eMIOS module index
292 * @param[in]  hwChannel - eMIOS Channel index
293 * @param[in]  u32Mode   - CCR_MODE bitfield value to be set
294 * @api
295 */
296 static inline void Emios_Icu_Ip_UCSetMode
297 (
298     const uint8 instance,
299     const uint8 hwChannel,
300     const uint32 u32Mode
301 );
302 
303 /**
304 * @brief   Function to return the channel id of master bus of current channel
305 * @details Function to return the channel id of master bus of current channel
306 * @param[in]  hwChannel - eMIOS Channel index
307 * @param[in]  u32Bus    - the used bus for current channels
308 * @param[out] - The id of master bus
309 */
310 static inline uint8 Emios_Icu_Ip_GetMasterBus
311 (
312     uint8 hwChannel,
313     eMios_Icu_Ip_BusType u32Bus
314 );
315 
316 #if (defined(EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
317 #if (defined(MCAL_EMIOS_REG_PROT_AVAILABLE))
318 #if (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE)
319 /**
320 * @brief        Enables EMIOS registers writing in User Mode by configuring REG_PROT
321 * @details      Sets the UAA (User Access Allowed) bit of the EMIOS IP allowing EMIOS registers writing in User Mode
322 *
323 * @param[in]    EmiosBaseAddr
324 *
325 * @return       none
326 *
327 * @pre          Should be executed in supervisor mode
328 * @post         none
329 *
330 */
331 void Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr);
332 #endif /* (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) */
333 #endif /* (defined(MCAL_EMIOS_REG_PROT_AVAILABLE)) */
334 #endif /* (defined(EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)) */
335 
336 
337 /*==================================================================================================
338 *                                       LOCAL FUNCTIONS
339 ==================================================================================================*/
Emios_Icu_Ip_UCSetMode(const uint8 instance,const uint8 hwChannel,const uint32 u32Mode)340 static inline void Emios_Icu_Ip_UCSetMode
341 (
342     const uint8 instance,
343     const uint8 hwChannel,
344     const uint32 u32Mode
345 )
346 {
347     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48();
348     /* Clear MODE bitfield - GPIO mode */
349     s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_MODE_MASK;
350     /* Set desired mode */
351     s_emiosBase[instance]->CH.UC[hwChannel].C |= (u32Mode & eMIOS_C_MODE_MASK);
352     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48();
353 }
354 
Emios_Icu_Ip_GetMasterBus(uint8 hwChannel,eMios_Icu_Ip_BusType u32Bus)355 static inline uint8 Emios_Icu_Ip_GetMasterBus
356 (
357     uint8 hwChannel,
358     eMios_Icu_Ip_BusType u32Bus
359 )
360 {
361     uint8 u8MasterBusChannelIdx = (uint8)0U;
362 
363     if (EMIOS_ICU_BUS_DIVERSE == u32Bus)
364     {
365         if (EMIOS_ICU_IP_CHANNEL_7 >= hwChannel) /* bus B */
366         {
367             u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_0;
368         }
369         else if (EMIOS_ICU_IP_CHANNEL_15 >= hwChannel) /* Bus C */
370         {
371             u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_8;
372         }
373         else if (EMIOS_ICU_IP_CHANNEL_23 >= hwChannel) /* bus D */
374         {
375             u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_16;
376         }
377         else /* Bus E remaining */
378         {
379             u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_24;
380         }
381     }
382     else if (EMIOS_ICU_BUS_A == u32Bus) /* bus A */
383     {
384         u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_23;
385     }
386     else if (EMIOS_ICU_BUS_F == u32Bus) /* bus F remaining */
387     {
388         u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_22;
389     }
390     else
391     {
392         /*Empty else to fix misra*/
393     }
394     return u8MasterBusChannelIdx;
395 }
396 
397 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
Emios_Icu_Ip_SetPrescaler(const uint8 instance,const uint8 hwChannel,const uint32 u32ChannelPrescaler)398 static inline void Emios_Icu_Ip_SetPrescaler
399 (
400     const uint8 instance,
401     const uint8 hwChannel,
402     const uint32 u32ChannelPrescaler
403 )
404 {
405     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53();
406 
407     /* Clear UCPREN bit */
408     s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_UCPREN_MASK;
409     /* Write prescaling rate at UCEXTPRE[0:3] bits in EMIOSC2[n] */
410     s_emiosBase[instance]->CH.UC[hwChannel].C2 &= ~eMIOS_C2_UCEXTPRE_MASK;
411 
412     s_emiosBase[instance]->CH.UC[hwChannel].C2 |= eMIOS_C2_UCEXTPRE(u32ChannelPrescaler);
413     /* Enable channel prescaler */
414     s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_UCPREN_MASK;
415 
416     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53();
417 }
418 #endif  /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
419 
420 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
421 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
Emios_Icu_Ip_EnableMasterBusInterrupt(const uint8 instance,const uint8 hwChannel)422 static inline void Emios_Icu_Ip_EnableMasterBusInterrupt
423 (
424     const uint8 instance,
425     const uint8 hwChannel
426 )
427 {
428     uint8      nMasterBusHwChannel;
429 
430     if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
431     {
432         nMasterBusHwChannel = Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
433         if (nMasterBusHwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS)
434         {
435             if((uint8)0U == eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel])
436             {
437                 /* Clear pending interrupts */
438                 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
439                 /* Enable Interrupt for master bus*/
440                 Emios_Icu_Ip_EnableInterrupt(instance, nMasterBusHwChannel);
441             }
442             eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel]++;
443         }
444     }
445 }
446 
Emios_Icu_Ip_DisableMasterBusInterrupt(const uint8 instance,const uint8 hwChannel)447 static inline void Emios_Icu_Ip_DisableMasterBusInterrupt
448 (
449     const uint8 instance,
450     const uint8 hwChannel
451 )
452 {
453     uint8      nMasterBusHwChannel;
454 
455     if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
456     {
457         nMasterBusHwChannel = Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
458         if (nMasterBusHwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS)
459         {
460             eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel]--;
461             if((uint8)0U == eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel])
462             {
463                 /* Disable Interrupt for master bus*/
464                 Emios_Icu_Ip_DisableInterrupt(instance, nMasterBusHwChannel);
465             }
466         }
467     }
468 }
469 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
470 #endif /* (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON) */
471 
472 /*==================================================================================================
473 *                                       GLOBAL FUNCTIONS
474 ==================================================================================================*/
475 #if (defined(EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
476 #if (defined(MCAL_EMIOS_REG_PROT_AVAILABLE))
477 #if (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE)
Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr)478 void Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr)
479 {
480     SET_USER_ACCESS_ALLOWED(EmiosBaseAddr, EMIOS_PROT_MEM_U32);
481 }
482 #endif /* (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) */
483 #endif /* (defined(MCAL_EMIOS_REG_PROT_AVAILABLE)) */
484 #endif /* (defined(EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)) */
485 
486 
487 /** @implements Emios_Icu_Ip_EnableInterrupt_Activity */
Emios_Icu_Ip_EnableInterrupt(uint8 instance,uint8 hwChannel)488 void Emios_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel)
489 {
490     /* Clear pending flag */
491     s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_FLAG_MASK;
492 
493     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46();
494     /* Enable interrupt */
495     s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_FEN_MASK;
496     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46();
497 }
498 
499 /** @implements Emios_Icu_Ip_DisableInterrupt_Activity */
Emios_Icu_Ip_DisableInterrupt(uint8 instance,uint8 hwChannel)500 void Emios_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel)
501 {
502     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47();
503     /* Disable interrupt */
504     s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_FEN_MASK;
505     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47();
506 }
507 
508 /* @implements Emios_Icu_Ip_Init_Activity */
Emios_Icu_Ip_Init(uint8 instance,const eMios_Icu_Ip_ConfigType * userConfig)509 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Init(uint8 instance, const eMios_Icu_Ip_ConfigType *userConfig)
510 {
511     uint8                       hwChannel;
512     uint32                      u32RegCCR;
513     uint8                       u8MasterBusMode[EMIOS_ICU_IP_NUM_OF_CHANNELS];
514     uint8                       index;
515     uint8                       u8MasterBusChannelIdx;
516     eMios_Icu_Ip_StatusType     retStatus   = EMIOS_IP_STATUS_SUCCESS;
517 
518 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
519     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
520     DevAssert(userConfig != NULL_PTR);
521 #endif
522     if (FALSE == eMios_Icu_Ip_bInstanceState[instance])
523     {
524         eMios_Icu_Ip_bInstanceState[instance] = TRUE;
525         for (index=0U; index < EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
526         {
527             if (eMios_Icu_Ip_IndexInChState[instance][index] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED)
528             {
529                 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][index]].channelsInitState = FALSE;
530             }
531             u8MasterBusMode[index] = EMIOS_ICU_IP_CB_NONE;
532         }
533         /* Register Protection - Set UAA bit in GCR - allow USER MODE access */
534         Call_Emios_Icu_Ip_SetUserAccessAllowed((uint32)s_emiosBase[instance]);
535 
536         for (index=0U; index < userConfig->nNumChannels; index++)
537         {
538             hwChannel   = (*userConfig->pChannelsConfig)[index].hwChannel;
539             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState = TRUE;
540 
541             /* Initialize the state for calling user notification - can be HLD or IPL direct user notification */
542             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMiosChannelNotification = (*userConfig->pChannelsConfig)[index].eMiosChannelNotification;
543 
544             /* Take HLD callback pointer and logic channel and store them in state configuration. */
545             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMiosOverflowNotification = (*userConfig->pChannelsConfig)[index].eMiosOverflowNotification;
546             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].callback      = (*userConfig->pChannelsConfig)[index].callback;
547             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].logicChStateCallback = (*userConfig->pChannelsConfig)[index].logicChStateCallback;
548             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].callbackParam = (*userConfig->pChannelsConfig)[index].callbackParams;
549 
550             /* Set the event which will generate the interrupt */
551             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger   = (*userConfig->pChannelsConfig)[index].edgeAlignement;
552 
553             /* Clear channel config for hwChannel */
554             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
555 #if (defined(EMIOS_ICU_IP_EDGE_COUNT_API) && (STD_ON == EMIOS_ICU_IP_EDGE_COUNT_API))
556 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
557             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32;
558 #endif  /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
559 #endif /* (defined(EMIOS_ICU_IP_EDGE_COUNT_API) && (STD_ON == EMIOS_ICU_IP_EDGE_COUNT_API)) */
560 
561 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
562             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement = EMIOS_ICU_NO_MEASUREMENT;
563             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (uint16)0U;
564             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (uint16)0U;
565 #endif
566 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API)
567     #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
568             /* Reset aBufferPtr */
569             eMios_Icu_Ip_BufferPtr[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
570     #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
571             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer = NULL_PTR;
572             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferSize = (uint16)0U;
573             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferNotify = (uint16)0U;
574             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aNotifyCount = (uint16)0U;
575             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex = (uint16)0U;
576             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType = (*userConfig->pChannelsConfig)[index].timestampBufferType;
577 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API) */
578 #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
579             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel =  (*userConfig->pChannelsConfig)[index].dmaChannel;
580 #endif
581 
582 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
583             /* Enable EMIOS Channel. */
584             Emios_Mcl_Ip_EnableChannel(instance, hwChannel);
585 #endif
586 
587             /* Enter GPIO Mode to Configure Channel */
588             /* Reset mode for selected channel */
589             s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32;
590 
591             /* Initialize channel filter, freeze enable, and bus select and disable the
592             * Set Default Edge (included)
593             */
594             u32RegCCR = eMIOS_C_UCPREN_MASK | eMIOS_C_FCK_MASK;
595             u32RegCCR |= eMIOS_C_FREN(((*userConfig->pChannelsConfig)[index].FreezeEn)?1U:0U);
596             u32RegCCR |= eMIOS_C_IF((*userConfig->pChannelsConfig)[index].Filter);
597             u32RegCCR |= eMIOS_C_BSL((*userConfig->pChannelsConfig)[index].CntBus);
598 
599             s_emiosBase[instance]->CH.UC[hwChannel].C |= u32RegCCR;
600 
601             /* Initialize prescaler value */
602             s_emiosBase[instance]->CH.UC[hwChannel].C2 &= ~eMIOS_C2_UCEXTPRE_MASK;
603             s_emiosBase[instance]->CH.UC[hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*userConfig->pChannelsConfig)[index].Prescaler);
604 
605             /* Disable interrupt */
606             Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
607 
608             /* Clear pending interrupt flag (and other flags) for the channel */
609             s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
610 
611             Emios_Icu_Ip_SetActivation( instance, hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger);
612 
613             /* Set Configuration for hwChannel */
614             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode = (*userConfig->pChannelsConfig)[index].chSubMode;
615             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode = (*userConfig->pChannelsConfig)[index].ucMode;
616             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt = (*userConfig->pChannelsConfig)[index].bWithoutInterrupt;
617         #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
618             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement = (*userConfig->pChannelsConfig)[index].measurementMode;
619         #endif
620             /* Store bus select of hwChannel */
621             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected = (*userConfig->pChannelsConfig)[index].CntBus;
622 
623             if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
624             {
625                 u8MasterBusChannelIdx = (uint8)Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
626                 if(EMIOS_ICU_IP_CB_NONE == u8MasterBusMode[u8MasterBusChannelIdx]) /* This master bus have not been configured*/
627                 {
628                     /* store master bus mode and master bus pre-scaler*/
629                     u8MasterBusMode[u8MasterBusChannelIdx] = (uint8)EMIOS_ICU_IP_MCB_INT_CLOCK_U32;
630                     eMios_Icu_Ip_IndexInChState[instance][u8MasterBusChannelIdx] = EMIOS_ICU_IP_MASTERBUS_CHANNEL_USED;
631 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
632                     /* Enable EMIOS Channel to make registers write-able. */
633                     Emios_Mcl_Ip_EnableChannel(instance, hwChannel);
634 #endif
635                 }
636             }
637         }
638 
639         /* configuration for master bus */
640         for (index=0U; index < EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
641         {
642             if(EMIOS_ICU_IP_CB_NONE != u8MasterBusMode[index]) /* Master bus is used */
643             {
644 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
645 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
646                 /* Reset the number of active channels has the overflow notification function using masterbus. */
647                 eMios_Icu_Ip_u8NumOvflByCounterBus[instance][index] = 0;
648 #endif
649 #endif
650             }
651         }
652     }
653     else
654     {
655         /* Module already initialized - use de-initialize first */
656         retStatus = EMIOS_IP_STATUS_ERROR;
657     }
658     return retStatus;
659 }
660 
661 #if (EMIOS_ICU_IP_DEINIT_API == STD_ON)
662 /* @implements Emios_Icu_Ip_DeinitChannel_Activity */
Emios_Icu_Ip_Deinit(uint8 instance)663 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Deinit(uint8 instance)
664 {
665     eMios_Icu_Ip_ModeType       nMeasMode;
666     uint8                       hwChannel;
667 
668     eMios_Icu_Ip_StatusType     retStatus   = EMIOS_IP_STATUS_SUCCESS;
669 
670 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
671     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
672 #endif
673 
674     if (TRUE == eMios_Icu_Ip_bInstanceState[instance])
675     {
676         eMios_Icu_Ip_bInstanceState[instance] = FALSE;
677 
678         for (hwChannel=0U; hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS; hwChannel++)
679         {
680             if (eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED)
681             {
682                 if (TRUE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState)
683                 {
684                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState = FALSE;
685 
686                     nMeasMode = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode;
687 
688                     /* Set all channel registers as after reset */
689                     s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32;
690                     s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;
691 
692                     switch (nMeasMode)
693                     {
694                         case EMIOS_ICU_MODE_SIGNAL_MEASUREMENT:
695                         {
696                             s_emiosBase[instance]->CH.UC[hwChannel].B = EMIOS_ICU_IP_CCR_CLEAR_U32;
697                         }
698                         break;
699 
700                         case EMIOS_ICU_MODE_EDGE_COUNTER:
701                         {
702                             s_emiosBase[instance]->CH.UC[hwChannel].CNT = EMIOS_ICU_IP_CCR_CLEAR_U32;
703                         }
704                         break;
705 
706                         default:
707                         {
708                             /*For Misra Compliance*/
709                         }
710                         break;
711                     }
712                     /* Clear CSR register */
713                     s_emiosBase[instance]->CH.UC[hwChannel].S = EMIOS_ICU_IP_CSR_CLEAR_U32;
714 
715 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
716                     /* Clear all aEdgeCurrent_Value */
717                     eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = (uint32)(0x0U);
718 #endif /* EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON */
719 
720                     /* if channel using master bus, so de-init for master bus */
721                     if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
722                     {
723 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
724                         /* Disable eMIOS Channel */
725                         Emios_Mcl_Ip_DisableChannel(instance, hwChannel);
726 #endif
727                     }
728                     /* Clear config for hardware channel */
729                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode = EMIOS_ICU_UNINIT;
730                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected   = EMIOS_ICU_BUS_INTERNAL_COUNTER;
731                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode   = EMIOS_ICU_MODE_NO_MEASUREMENT;
732 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
733                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement   = EMIOS_ICU_NO_MEASUREMENT;
734 #endif
735 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API)
736                     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType = EMIOS_ICU_NO_TIMESTAMP;
737 #endif
738                 }
739             }
740             if (EMIOS_ICU_IP_MASTERBUS_CHANNEL_USED == eMios_Icu_Ip_IndexInChState[instance][hwChannel])
741             {
742                 eMios_Icu_Ip_IndexInChState[instance][hwChannel] = EMIOS_ICU_IP_CHANNEL_NOT_USED;
743             }
744         }
745     }
746     else
747     {
748         /* Module already de-init - use init first */
749         retStatus = EMIOS_IP_STATUS_ERROR;
750     }
751     return retStatus;
752 }
753 #endif
754 
755 #if (EMIOS_ICU_IP_SET_MODE_API == STD_ON)
Emios_Icu_Ip_SetSleepMode(uint8 instance,uint8 hwChannel)756 void Emios_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel)
757 {
758 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
759     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
760     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
761     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
762 #endif
763     /* Stop eMIOS channel */
764     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
765 }
766 
Emios_Icu_Ip_SetNormalMode(uint8 instance,uint8 hwChannel)767 void Emios_Icu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel)
768 {
769     uint32 u32Value_CCR_FEN;
770 
771 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
772     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
773     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
774 #endif
775     /* u32Value_CCR_FEN will indicate whether the interrupt is enabled or not*/
776     u32Value_CCR_FEN  = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_FEN_MASK);
777     /* if interrupt is not enabled*/
778     if(0U == u32Value_CCR_FEN)
779     {
780         Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
781     }
782 }
783 #endif  /* EMIOS_ICU_IP_SET_MODE_API */
784 
785 /* @implements Emios_Icu_Ip_SetActivation_Activity */
Emios_Icu_Ip_SetActivation(uint8 instance,uint8 hwChannel,eMios_Icu_Ip_EdgeType edge)786 void Emios_Icu_Ip_SetActivation(uint8 instance, uint8 hwChannel, eMios_Icu_Ip_EdgeType edge)
787 {
788 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE)
789     uint32 u32RegEmiosCCR;
790 #endif  /* STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE */
791 
792 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
793     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
794     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
795 #endif
796     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50();
797     switch (edge)
798     {
799 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE)
800         case EMIOS_OPPOSITE_EDGES:
801         {
802             u32RegEmiosCCR = s_emiosBase[instance]->CH.UC[hwChannel].C;
803             s_emiosBase[instance]->CH.UC[hwChannel].C = (u32RegEmiosCCR ^ eMIOS_C_EDPOL_MASK);
804         }
805         break;
806 #endif  /* STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE */
807 
808         case EMIOS_ICU_BOTH_EDGES:
809         {
810             s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDSEL_MASK;
811         }
812         break;
813 
814         case EMIOS_ICU_RISING_EDGE:
815         {
816             s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_EDSEL_MASK;
817             s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDPOL_MASK;
818         }
819         break;
820 
821         default:
822         {
823             /* EMIOS_ICU_FALLING_EDGE */
824             s_emiosBase[instance]->CH.UC[hwChannel].C &= ~(eMIOS_C_EDSEL_MASK|eMIOS_C_EDPOL_MASK);
825         }
826         break;
827     }
828     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50();
829 }
830 
831 #if (EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON)
832 /* @implements Emios_Icu_Ip_EnableEdgeDetection_Activity */
Emios_Icu_Ip_EnableEdgeDetection(uint8 instance,uint8 hwChannel)833 void Emios_Icu_Ip_EnableEdgeDetection(uint8 instance, uint8 hwChannel)
834 {
835 
836 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
837     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
838     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
839     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
840 #endif
841     /* Enter GPIO Mode */
842     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
843 
844     /* Enable SAIC mode */
845     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
846 
847     /* Enable Interrupt */
848     Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
849 
850     /* Set Channel Config */
851     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_SIGNAL_EDGE_DETECT;
852 
853 }
854 
855 /* @implements Emios_Icu_Ip_DisableEdgeDetection_Activity */
Emios_Icu_Ip_DisableEdgeDetection(uint8 instance,uint8 hwChannel)856 void Emios_Icu_Ip_DisableEdgeDetection(uint8 instance, uint8 hwChannel)
857 {
858 
859 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
860     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
861     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
862     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
863 #endif
864     /* Disable interrupt */
865     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
866 
867     /* Enter GPIO Mode */
868     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
869 
870     /* Clear Channel Config */
871     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
872 
873 }
874 #endif /* EMIOS_ICU_IP_EDGE_DETECT_API */
875 
876 /* @implements Emios_Icu_Ip_EnableNotification_Activity */
Emios_Icu_Ip_EnableNotification(uint8 instance,uint8 hwChannel)877 void Emios_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel)
878 {
879 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
880     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
881     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
882     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
883 #endif
884 
885     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificationEnable =  TRUE;
886 }
887 
888 /* @implements Emios_Icu_Ip_DisableNotification_Activity */
Emios_Icu_Ip_DisableNotification(uint8 instance,uint8 hwChannel)889 void Emios_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel)
890 {
891 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
892     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
893     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
894     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
895 #endif
896 
897     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificationEnable =  FALSE;
898 }
899 
900 #if (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)
901 /* @implements Emios_Icu_Ip_StartTimestamp_Activity */
Emios_Icu_Ip_StartTimestamp(uint8 instance,uint8 hwChannel,eMios_Icu_ValueType * bufferPtr,uint16 bufferSize,uint16 notifyInterval)902 void Emios_Icu_Ip_StartTimestamp
903 (
904     uint8 instance,
905     uint8 hwChannel,
906     eMios_Icu_ValueType * bufferPtr,
907     uint16 bufferSize,
908     uint16 notifyInterval
909 )
910 {
911 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
912         Dma_Ip_LogicChannelTransferListType global_DmaChannelTransferList[11U];
913 #endif /* (EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL == STD_ON) */
914 
915 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
916     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
917     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
918     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
919 #endif
920     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51();
921     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer = bufferPtr;
922     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferSize = bufferSize;
923     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferNotify = notifyInterval;
924     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aNotifyCount = (uint16)0U;
925     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex = (uint16)0U;
926     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51();
927 
928     /* Reset aBufferPtr */
929     eMios_Icu_Ip_BufferPtr[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
930 
931 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
932     /* Setup DMA in Dma_Ip*/
933     if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
934     {
935         /* Create the desired configuration list. */
936         global_DmaChannelTransferList[0U].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
937         global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel);
938         /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe.
939          * The application should ensure that only addresses that fit in uint32 are used for configuring DMA. */
940         global_DmaChannelTransferList[1U].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
941         global_DmaChannelTransferList[1U].Value = (uint32)bufferPtr;
942         global_DmaChannelTransferList[2U].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
943         global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
944         global_DmaChannelTransferList[3U].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
945         global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
946         global_DmaChannelTransferList[4U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
947         global_DmaChannelTransferList[4U].Value = (uint32)0U;
948         global_DmaChannelTransferList[5U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
949         global_DmaChannelTransferList[5U].Value = (uint32)4U;
950         global_DmaChannelTransferList[6U].Param = DMA_IP_CH_SET_SOURCE_MODULO;
951         global_DmaChannelTransferList[6U].Value = (uint32)0U;
952         global_DmaChannelTransferList[7U].Param = DMA_IP_CH_SET_DESTINATION_MODULO;
953         global_DmaChannelTransferList[7U].Value = (uint32)0U;
954 
955         if ((notifyInterval >= bufferSize) || (notifyInterval == (uint16)0))
956         {
957             global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
958             global_DmaChannelTransferList[8U].Value = 4U;
959             global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
960             global_DmaChannelTransferList[9U].Value = bufferSize;
961             if ((uint8) EMIOS_ICU_CIRCULAR_BUFFER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType)
962             {
963                 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
964                 global_DmaChannelTransferList[10U].Value = (uint32) (~(bufferSize * 4U)) + 1U;
965             }
966             else
967             {
968                 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
969                 global_DmaChannelTransferList[10U].Value = (uint32)1U;
970             }
971         }
972         else if (notifyInterval < bufferSize)
973         {
974             global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
975             global_DmaChannelTransferList[8U].Value = 4U;
976             global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
977             global_DmaChannelTransferList[9U].Value = notifyInterval;
978             if ((uint8) EMIOS_ICU_CIRCULAR_BUFFER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType)
979             {
980 
981                 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
982                 global_DmaChannelTransferList[10U].Value = (uint32)0U;
983             }
984             else
985             {
986                 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
987                 global_DmaChannelTransferList[10U].Value = (uint32)0U;
988             }
989         }
990         else
991         {
992             /* Nothing to be done */
993         }
994 
995         Dma_Ip_SetLogicChannelTransferList(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, global_DmaChannelTransferList, (uint32)11U);
996         Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
997     }
998 #endif  /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
999 
1000     /* Make sure channel is in GPIO mode before switching modes */
1001     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1002 
1003     /* Clear pending interrupts */
1004     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1005 
1006     /* Enable SAIC mode */
1007     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
1008 
1009     if(EMIOS_ICU_MODE_WITH_DMA == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode)
1010     {
1011         SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51();
1012         s_emiosBase[instance]->CH.UC[hwChannel].C |= (eMIOS_C_DMA_MASK);
1013         SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51();
1014     }
1015 
1016     if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1017     {
1018         /* Set Max. A value */
1019         s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1020     }
1021 
1022     /* Set channel Config*/
1023     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_TIMESTAMP;
1024     /* Enable Interrupt */
1025     Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1026 
1027 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1028     /* Enable Interrupt for masterbus*/
1029     Emios_Icu_Ip_EnableMasterBusInterrupt(instance ,hwChannel);
1030 #endif
1031 }
1032 
1033 /* @implements Emios_Icu_Ip_GetTimestampIndex_Activity */
Emios_Icu_Ip_GetTimestampIndex(uint8 instance,uint8 hwChannel)1034 uint16 Emios_Icu_Ip_GetTimestampIndex
1035 (
1036     uint8 instance,
1037     uint8 hwChannel
1038 )
1039 {
1040     uint16 timestampIndex = 0U;
1041 
1042 #if (EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL == STD_ON)
1043     uint32          startIter;
1044     uint32          crtIter;
1045     uint32* const   pStartIter = &startIter;
1046     uint32* const   pCrtIter = &crtIter;
1047 #endif
1048 
1049 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1050     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1051     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1052 #endif
1053 
1054 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1055     if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1056     {
1057         if (NULL_PTR == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer)
1058         {
1059             timestampIndex = 0U;
1060         }
1061         else
1062         {
1063             Dma_Ip_GetLogicChannelParam(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_GET_BEGIN_ITER_COUNT, pStartIter);
1064             Dma_Ip_GetLogicChannelParam(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_GET_CURRENT_ITER_COUNT, pCrtIter);
1065             crtIter = startIter - crtIter;
1066             timestampIndex =  eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex + (uint16)crtIter;
1067         }
1068     }
1069     else
1070     {
1071 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1072         if (NULL_PTR == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer)
1073         {
1074             timestampIndex = 0U;
1075         }
1076         else
1077         {
1078             timestampIndex = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex;
1079         }
1080 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1081     }
1082 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1083 
1084     return timestampIndex;
1085 }
1086 
1087 /* @implements Emios_Icu_Ip_StopTimestamp_Activity */
Emios_Icu_Ip_StopTimestamp(uint8 instance,uint8 hwChannel)1088 void Emios_Icu_Ip_StopTimestamp(uint8 instance, uint8 hwChannel)
1089 {
1090 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1091     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1092     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1093     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1094 #endif
1095 
1096 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1097     /* Disable Dma for Timestamp */
1098     if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1099     {
1100         Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
1101     }
1102 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1103 
1104     /* Disable interrupt */
1105     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1106 
1107     /* Enter GPIO Mode */
1108     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1109 
1110     /* Clear channel Config */
1111     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1112 
1113     if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1114     {
1115         /* Set Max. A value */
1116         s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;;
1117     }
1118 
1119 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1120     /* Disable Interrupt for masterbus*/
1121     Emios_Icu_Ip_DisableMasterBusInterrupt(instance, hwChannel);
1122 #endif
1123 }
1124 #endif  /* EMIOS_ICU_IP_TIMESTAMP_API */
1125 
1126 #if ((EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_USES_DMA == STD_ON))
Emios_Icu_Ip_GetStartAddress(uint8 instance,uint8 hwChannel)1127 uint32 Emios_Icu_Ip_GetStartAddress
1128 (
1129     uint8 instance,
1130     uint8 hwChannel
1131 )
1132 {
1133 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1134     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1135     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1136 #endif
1137     /*return the value of A register*/
1138     return (uint32)(&s_emiosBase[instance]->CH.UC[hwChannel].A);
1139 }
1140 #endif
1141 
1142 
1143 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
1144 
1145 /* @implements Emios_Icu_Ip_ResetEdgeCount_Activity */
Emios_Icu_Ip_ResetEdgeCount(uint8 instance,uint8 hwChannel)1146 void Emios_Icu_Ip_ResetEdgeCount
1147 (
1148     uint8 instance,
1149     uint8 hwChannel
1150 )
1151 {
1152     uint32  u32PrevMode;
1153 
1154 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1155     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1156     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1157 #endif
1158     u32PrevMode = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_MODE_MASK);
1159 
1160     /* Disable timer interrupts */
1161     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1162 
1163     /* Enter GPIO Mode */
1164     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1165 
1166     /* Reset counter */
1167     s_emiosBase[instance]->CH.UC[hwChannel].CNT = EMIOS_ICU_IP_INIT_CCNTR_U32;
1168 
1169     /* Max. value for register A. If reached, overflow interrupt */
1170     s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1171 
1172     /* Clear pending interrupts */
1173     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1174 
1175     /* Restore previous mode */
1176     Emios_Icu_Ip_UCSetMode(instance, hwChannel, u32PrevMode);
1177 
1178     /* Cleare Current Value*/
1179     eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = (uint32)0U;
1180     /* Enable timer interrupts */
1181     Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1182 }
1183 
1184 /* @implements Emios_Icu_Ip_EnableEdgeCount_Activity */
Emios_Icu_Ip_EnableEdgeCount(uint8 instance,uint8 hwChannel)1185 void Emios_Icu_Ip_EnableEdgeCount(uint8 instance, uint8 hwChannel)
1186 {
1187 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1188     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1189     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1190     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1191 #endif
1192     /* Disable interrupt */
1193     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1194     /* Make sure channel is in GPIO mode before switching modes */
1195     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1196 
1197     /* Set Max. A value */
1198 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1199     s_emiosBase[instance]->CH.UC[hwChannel].A = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue;
1200 #else
1201     s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1202 #endif  /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1203 
1204 
1205     /* Sync. eMIOS counter value. (Needed in case of stopping and re-enabling counting)
1206      * Note: Setting GPIO mode, the internal counter was cleared and must be restored
1207      */
1208 
1209     /* When call again affter call Emios_Icu_Ip_DisableEdgeCount*/
1210     s_emiosBase[instance]->CH.UC[hwChannel].CNT = eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]];
1211 
1212     /* Modulus counter mode */
1213     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_MCB_EXT_CLOCK_U32);
1214 
1215     /* Clear pending interrupts */
1216     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1217 
1218     /* Enable interrupt */
1219     Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1220 
1221     /* Set Channel config */
1222     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_EDGE_COUNTER;
1223 
1224 
1225 }
1226 
1227 /* @implements Emios_Icu_Ip_DisableEdgeCount_Activity */
Emios_Icu_Ip_DisableEdgeCount(uint8 instance,uint8 hwChannel)1228 void Emios_Icu_Ip_DisableEdgeCount
1229 (
1230     uint8 instance,
1231     uint8 hwChannel
1232 )
1233 {
1234 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1235     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1236     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1237     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1238 #endif
1239     /* Disable interrupt */
1240     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1241 
1242     /* Clear pending interrupts */
1243     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1244 
1245     /* Save count, before going to GPIO mode (because counter is reset to 0x0000) */
1246     eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = s_emiosBase[instance]->CH.UC[hwChannel].CNT;
1247 
1248     /* Disable MCB mode */
1249     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1250 
1251     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1252 
1253 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1254     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32;
1255 #endif  /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1256 }
1257 
1258 
1259 /* @implements Emios_Icu_Ip_GetEdgeNumbers_Activity */
Emios_Icu_Ip_GetEdgeNumbers(uint8 instance,uint8 hwChannel)1260 eMios_Icu_ValueType Emios_Icu_Ip_GetEdgeNumbers
1261 (
1262     uint8 instance,
1263     uint8 hwChannel
1264 )
1265 {
1266     uint32 u32Mode;
1267     eMios_Icu_ValueType u16Result = (eMios_Icu_ValueType)0U;
1268     u32Mode = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_MODE_MASK);
1269 
1270 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1271     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1272     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1273 #endif
1274     /* Check mode after call Emios_Icu_Ip_DisableEdgeCount */
1275     if(EMIOS_ICU_IP_CCR_MODE_GPI_U32 == u32Mode)
1276     {
1277         u16Result = (eMios_Icu_ValueType)eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]];
1278     }
1279     else
1280     {
1281         u16Result = (eMios_Icu_ValueType)s_emiosBase[instance]->CH.UC[hwChannel].CNT;
1282     }
1283     return u16Result;
1284 
1285 }
1286 
1287 #if (STD_ON == EMIOS_ICU_IP_SET_INITIAL_COUNTER)
1288 /* @implements Emios_Icu_Ip_SetInitialCounterValue_Activity */
Emios_Icu_Ip_SetInitialCounterValue(uint8 instance,uint8 hwChannel,uint32 initialCounter)1289 void Emios_Icu_Ip_SetInitialCounterValue
1290 (
1291     uint8 instance,
1292     uint8 hwChannel,
1293     uint32 initialCounter
1294 )
1295 {
1296 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1297     DevAssert(instance   < EMIOS_ICU_IP_INSTANCE_COUNT);
1298     DevAssert(hwChannel  < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1299 #endif
1300 
1301     /* Save initial counter for channel */
1302     eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]]= initialCounter;
1303 }
1304 #endif  /* STD_ON == EMIOS_ICU_IP_SET_INITIAL_COUNTER */
1305 
1306 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1307 /* @implements Emios_Icu_Ip_SetMaxCounterValue_Activity */
Emios_Icu_Ip_SetMaxCounterValue(uint8 instance,uint8 hwChannel,uint32 maxCounter)1308 void Emios_Icu_Ip_SetMaxCounterValue
1309 (
1310     uint8 instance,
1311     uint8 hwChannel,
1312     uint32 maxCounter
1313 )
1314 {
1315 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1316     DevAssert(instance   < EMIOS_ICU_IP_INSTANCE_COUNT);
1317     DevAssert(hwChannel  < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1318     DevAssert(maxCounter < EMIOS_ICU_IP_COUNTER_MASK);
1319 #endif
1320 
1321     /* Save max counter for channel */
1322     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = maxCounter;
1323 }
1324 #endif  /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1325 #endif  /* EMIOS_ICU_IP_EDGE_COUNT_API */
1326 
1327 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
1328 /* @implements Emios_Icu_Ip_StartSignalMeasurement_Activity */
Emios_Icu_Ip_StartSignalMeasurement(uint8 instance,uint8 hwChannel)1329 void Emios_Icu_Ip_StartSignalMeasurement
1330 (
1331     uint8 instance,
1332     uint8 hwChannel
1333 )
1334 {
1335     eMios_Icu_Ip_UCModeType eMiosOperationMode;
1336 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
1337     /* Setup DMA for this channel */
1338     uint8 u8index = 0U;
1339     Dma_Ip_LogicChannelTransferListType global_DmaChannelTransferList[10U];
1340 #endif
1341 
1342 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1343     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1344     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1345     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1346 #endif
1347 
1348 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
1349     /* Setup DMA for this channel */
1350     if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1351     {
1352         Emios_Icu_Ip_aIsSecondInterrupt[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1353         /* initialize the members of the structure */
1354         global_DmaChannelTransferList[0U].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
1355         global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel);
1356         global_DmaChannelTransferList[1U].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
1357         global_DmaChannelTransferList[1U].Value = (uint32)&Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState[instance][hwChannel]][0];
1358         global_DmaChannelTransferList[2U].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
1359         global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1360         global_DmaChannelTransferList[3U].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
1361         global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1362         global_DmaChannelTransferList[4U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
1363         global_DmaChannelTransferList[4U].Value = (uint32)0U;
1364         global_DmaChannelTransferList[5U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
1365         global_DmaChannelTransferList[5U].Value = (uint32)4U;
1366         global_DmaChannelTransferList[6U].Param = DMA_IP_CH_SET_SOURCE_MODULO;
1367         global_DmaChannelTransferList[6U].Value = (uint32)0U;
1368         global_DmaChannelTransferList[7U].Param = DMA_IP_CH_SET_DESTINATION_MODULO;
1369         global_DmaChannelTransferList[7U].Value = (uint32)0U;
1370         global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
1371         global_DmaChannelTransferList[8U].Value = (uint32)4U;
1372         global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
1373         global_DmaChannelTransferList[9U].Value = (uint32)1U;
1374 
1375         Dma_Ip_SetLogicChannelTransferList(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, global_DmaChannelTransferList, (uint32)10U);
1376         Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
1377 
1378         /*Clear the DMA result buffer for configured DMA channel*/
1379         for(u8index = 0U; u8index < EMIOS_ICU_IP_DMA_MAJORLOOP_COUNT; u8index++)
1380         {
1381              Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState[instance][hwChannel]][u8index] = (uint16)0;
1382         }
1383     }
1384 #endif
1385 
1386     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (eMios_Icu_ValueType)0U;
1387     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1388 
1389     /* Reset capture and timestart of hwChannel */
1390     eMios_Icu_Ip_CapturedActivePulseWidth[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1391     eMios_Icu_Ip_TimeStart[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1392 
1393     /* Disable interrupt */
1394     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1395 
1396     /* Enter GPIO Mode */
1397     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1398 
1399     /* Set activation condition */
1400     Emios_Icu_Ip_SetActivation(instance, hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger);
1401 
1402     /* Get operation mode of hardware channel */
1403     if(EMIOS_ICU_MODE_WITH_DMA == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode)\
1404     {
1405         SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52();
1406         s_emiosBase[instance]->CH.UC[hwChannel].C |= (eMIOS_C_DMA_MASK);
1407         SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52();
1408     }
1409     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_SIGNAL_MEASUREMENT;
1410 
1411     eMiosOperationMode = (eMios_Icu_Ip_UCModeType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode;
1412 
1413     switch (eMiosOperationMode)
1414     {
1415         case EMIOS_ICU_IPWM:
1416             {
1417                 /* Enable IPWM mode */
1418                 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_IPWM_U32);
1419             }
1420         break;
1421 
1422         case EMIOS_ICU_IPM:
1423             {
1424                 /* Enable IPM mode */
1425                 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_IPM_U32);
1426             }
1427         break;
1428 
1429         default:
1430             {
1431                 /* Enable SAIC mode */
1432                 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
1433             }
1434         break;
1435     }
1436 
1437     if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1438     {
1439         /* Set Max. A value */
1440         s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1441     }
1442     /* Clear pending interrupt flag (and other flags) for the channel */
1443     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1444     /* Clear the counter for signal measurement */
1445     eMios_Icu_Ip_aeInt_Counter[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = EMIOS_ICU_MEASUREMENT_PENDING;
1446     if (TRUE != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt)
1447     {
1448         /* Enable Interrupt */
1449         Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1450     }
1451 
1452 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1453     /* Enable Interrupt for masterbus*/
1454     Emios_Icu_Ip_EnableMasterBusInterrupt(instance, hwChannel);
1455 #endif
1456 }
1457 
1458 /* @implements Emios_Icu_Ip_StopSignalMeasurement_Activity */
Emios_Icu_Ip_StopSignalMeasurement(uint8 instance,uint8 hwChannel)1459 void Emios_Icu_Ip_StopSignalMeasurement
1460 (
1461     uint8 instance,
1462     uint8 hwChannel
1463 )
1464 {
1465 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1466     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1467     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1468     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1469 #endif
1470     /* Disable interrupt */
1471     Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1472 
1473     /* Enter GPIO Mode */
1474     Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1475 
1476     SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49();
1477     /* EDSEL is set to 1 to discard the input in GPIO mode (not to repond the input signal
1478        in GPIO mode)*/
1479     /* Disables the flag generation as defined by EDPOL Bit */
1480     s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDSEL_MASK;
1481     SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49();
1482 
1483     if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1484     {
1485         /* Set Max. A value */
1486         s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;
1487     }
1488     /* Clear pending interrupt flag (and other flags) for the channel */
1489     s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1490     /* Clear channel config */
1491     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1492 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1493     /* Disable Interrupt for masterbus*/
1494     Emios_Icu_Ip_DisableMasterBusInterrupt(instance, hwChannel);
1495 #endif
1496 }
1497 
1498 /* @implements Emios_Icu_Ip_GetTimeElapsed_Activity */
Emios_Icu_Ip_GetTimeElapsed(uint8 instance,uint8 hwChannel)1499 eMios_Icu_ValueType Emios_Icu_Ip_GetTimeElapsed
1500 (
1501     uint8 instance,
1502     uint8 hwChannel
1503 )
1504 {
1505     eMios_Icu_ValueType timeElapsed = (eMios_Icu_ValueType)0U;
1506 
1507 
1508 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1509     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1510     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1511     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1512 #endif
1513     if((EMIOS_ICU_DUTY_CYCLE != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement) && \
1514         (EMIOS_ICU_NO_MEASUREMENT != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement))
1515     {
1516         if ((eMios_Icu_Ip_MeasType)EMIOS_ICU_PERIOD_TIME == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement)
1517         {
1518             timeElapsed = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod;
1519             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (eMios_Icu_ValueType)0U;
1520         }
1521         else
1522         {
1523             timeElapsed = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth;
1524             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1525         }
1526     }
1527     #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1528     else
1529     {
1530         DevAssert(TRUE);
1531     }
1532     #endif
1533     return timeElapsed;
1534 }
1535 
1536 /* @implements Emios_Icu_Ip_GetDutyCycleValues_Activity */
Emios_Icu_Ip_GetDutyCycleValues(uint8 instance,uint8 hwChannel,eMios_Icu_Ip_DutyCycleType * dutyCycleValues)1537 void Emios_Icu_Ip_GetDutyCycleValues
1538 (
1539     uint8 instance,
1540     uint8 hwChannel,
1541     eMios_Icu_Ip_DutyCycleType*  dutyCycleValues
1542 )
1543 {
1544 
1545 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1546     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1547     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1548     DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1549 #endif
1550     if(EMIOS_ICU_DUTY_CYCLE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement)
1551     {
1552         if ((eMios_Icu_ValueType)0U != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod)
1553         {
1554             dutyCycleValues->ActiveTime = (eMios_Icu_ValueType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth;
1555             dutyCycleValues->PeriodTime = (eMios_Icu_ValueType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod;
1556             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1557             eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod           = (eMios_Icu_ValueType)0U;
1558         }
1559         else
1560         {
1561             dutyCycleValues->ActiveTime = (eMios_Icu_ValueType)0U;
1562             dutyCycleValues->PeriodTime = (eMios_Icu_ValueType)0U;
1563         }
1564     }
1565     #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1566     else
1567     {
1568         DevAssert(TRUE);
1569     }
1570     #endif
1571 }
1572 
1573 /**
1574  * @brief Emios_Icu_Ip_SetPWandPeriod
1575  */
Emios_Icu_Ip_SetPWandPeriod(uint8 instance,uint8 hwChannel,eMios_Icu_ValueType activePulseWidth,eMios_Icu_ValueType period)1576 void Emios_Icu_Ip_SetPWandPeriod(uint8 instance, \
1577                                uint8 hwChannel, \
1578                                eMios_Icu_ValueType activePulseWidth, \
1579                                eMios_Icu_ValueType period)
1580 {
1581     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = activePulseWidth;
1582     eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod           = period;
1583 }
1584 #endif  /* EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API */
1585 
1586 #if (EMIOS_ICU_IP_GET_INPUT_STATE_API == STD_ON)
Emios_Icu_Ip_GetInputState(uint8 instance,uint8 hwChannel)1587 boolean Emios_Icu_Ip_GetInputState
1588 (
1589     uint8 instance,
1590     uint8 hwChannel
1591 )
1592 {
1593     boolean bResult = FALSE;
1594     uint32 u32ValueCCRFEN;
1595     uint32 u32ValueCSRFLAG;
1596 
1597 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1598     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1599     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1600 #endif
1601     u32ValueCCRFEN  = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_FEN_MASK);
1602     u32ValueCSRFLAG = (s_emiosBase[instance]->CH.UC[hwChannel].S & eMIOS_S_FLAG_MASK);
1603 
1604     /* Interrupt not enabled, flag bit was set */
1605     if ( (eMIOS_C_FEN_MASK != u32ValueCCRFEN) && (eMIOS_S_FLAG_MASK == u32ValueCSRFLAG))
1606     {
1607 
1608         /* Clear pending interrupt */
1609         s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_FLAG_MASK;
1610         bResult = TRUE;
1611     }
1612 
1613     return bResult;
1614 }
1615 #endif  /* EMIOS_ICU_IP_GET_INPUT_STATE_API */
1616 
1617 #if (EMIOS_ICU_IP_GET_INPUT_LEVEL_API == STD_ON)
1618 /* @implements  Emios_Icu_Ip_GetInputLevel_Activity */
Emios_Icu_Ip_GetInputLevel(uint8 instance,uint8 hwChannel)1619 eMios_Icu_Ip_LevelType Emios_Icu_Ip_GetInputLevel
1620 (
1621     uint8 instance,
1622     uint8 hwChannel
1623 )
1624 {
1625 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1626     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1627     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1628 #endif
1629     return ((0U != ((s_emiosBase[instance]->CH.UC[hwChannel].S & eMIOS_S_UCIN_MASK)>> eMIOS_S_UCIN_SHIFT))? \
1630             EMIOS_ICU_LEVEL_HIGH : EMIOS_ICU_LEVEL_LOW);
1631 }
1632 #endif /* EMIOS_ICU_IP_GET_INPUT_LEVEL_API == STD_ON */
1633 
Emios_Icu_Ip_GetOverflow(uint8 instance,uint8 hwChannel)1634 boolean Emios_Icu_Ip_GetOverflow
1635 (
1636     uint8 instance,
1637     uint8 hwChannel
1638 )
1639 {
1640     uint32 u32RegCSR = (uint32) 0U;
1641 
1642 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1643     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1644     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1645 #endif
1646     u32RegCSR = s_emiosBase[instance]->CH.UC[hwChannel].S;
1647 
1648     /* Clear pending interrupt serviced */
1649     s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_OVFL_MASK;
1650 
1651     return ((eMIOS_S_OVFL_MASK == (u32RegCSR & eMIOS_S_OVFL_MASK)) ? TRUE : FALSE);
1652 }
1653 
1654 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
Emios_Icu_Ip_SetClockMode(uint8 instance,const eMios_Icu_Ip_ConfigType * peMiosIpConfig,const eMios_Icu_Ip_ClockModeType Prescaler)1655 void Emios_Icu_Ip_SetClockMode
1656 (
1657     uint8 instance,
1658     const eMios_Icu_Ip_ConfigType                   *peMiosIpConfig,
1659     const eMios_Icu_Ip_ClockModeType                Prescaler
1660 )
1661 {
1662     /* logical channel */
1663     uint8   index;
1664     uint8   hwChannel;
1665     eMios_Icu_Ip_BusType  nCtrlBus;
1666     uint8   u8MasterBusChannelIdx;
1667     uint8   u8MasterBusUse[EMIOS_ICU_IP_NUM_OF_CHANNELS];
1668 
1669 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1670     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1671 #endif
1672     for (index=0U; index < (uint8)EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
1673     {
1674         u8MasterBusUse[index] = (uint8)EMIOS_ICU_IP_CB_NONE;
1675     }
1676 
1677     for (index=0U; index < peMiosIpConfig->nNumChannels; index++)
1678     {
1679         hwChannel   = (*peMiosIpConfig->pChannelsConfig)[index].hwChannel;
1680         nCtrlBus = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected;
1681 
1682         if (EMIOS_ICU_BUS_INTERNAL_COUNTER == nCtrlBus)
1683         {
1684             if (EMIOS_ICU_NORMAL_CLK == Prescaler)
1685             {
1686                 Emios_Icu_Ip_SetPrescaler(  instance,
1687                                             hwChannel,
1688                                             (uint32)(*peMiosIpConfig->pChannelsConfig)[index].Prescaler
1689                                           );
1690             }
1691             else
1692             {
1693                 Emios_Icu_Ip_SetPrescaler(  instance,
1694                                             hwChannel,
1695                                             (uint32)(*peMiosIpConfig->pChannelsConfig)[index].AltPrescaler
1696                                           );
1697             }
1698         }
1699         else
1700         {
1701             u8MasterBusChannelIdx = (uint8)Emios_Icu_Ip_GetMasterBus(hwChannel, nCtrlBus);
1702 
1703             if(u8MasterBusChannelIdx < EMIOS_ICU_IP_NUM_OF_CHANNELS)
1704             {
1705                 if(u8MasterBusUse[u8MasterBusChannelIdx] == EMIOS_ICU_IP_CB_NONE)
1706                 {
1707                     if (EMIOS_ICU_NORMAL_CLK == Prescaler)
1708                     {
1709                         Emios_Icu_Ip_SetPrescaler(  instance,
1710                                                 u8MasterBusChannelIdx,
1711                                                 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].Prescaler
1712                                               );
1713                     }
1714                     else
1715                     {
1716                         Emios_Icu_Ip_SetPrescaler(  instance,
1717                                                 u8MasterBusChannelIdx,
1718                                                 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].AltPrescaler
1719                                               );
1720                     }
1721                     u8MasterBusUse[u8MasterBusChannelIdx] = (uint8)1U;
1722                 }
1723             }
1724         }
1725     }
1726 }
1727 #endif  /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
1728 
1729 #if ((EMIOS_ICU_IP_CAPTURERGISTER_API == STD_ON) && ((EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)))
1730 /** @implements Emios_Icu_Ip_GetCaptureRegValue_Activity */
Emios_Icu_Ip_GetCaptureRegValue(uint8 instance,uint8 hwChannel)1731 uint32 Emios_Icu_Ip_GetCaptureRegValue
1732 (
1733     uint8 instance,
1734     uint8 hwChannel
1735 )
1736 {
1737 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1738     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1739     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1740 #endif
1741     return s_emiosBase[instance]->CH.UC[hwChannel].A;
1742 }
1743 #endif  /* (EMIOS_ICU_IP_CAPTURERGISTER_API == STD_ON) && ((EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)) */
1744 
1745 #if ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
1746 /* @implements Emios_Icu_Ip_GetPulseWidth_Activity */
Emios_Icu_Ip_GetPulseWidth(uint8 instance,uint8 hwChannel)1747 void Emios_Icu_Ip_GetPulseWidth
1748 (
1749     uint8 instance,
1750     uint8 hwChannel
1751 )
1752 {
1753 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1754     DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1755     DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1756 #endif
1757     Emios_Icu_Ip_SignalMeasurementHandler(instance, hwChannel, FALSE);
1758 }
1759 #endif /* ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))*/
1760 
1761 #if ((EMIOS_ICU_IP_VALIDATE_GLOBAL_CALL == STD_ON) && ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)))
Emios_Icu_Ip_ValidateSignalMeasureWithoutInterrupt(uint8 instance,uint8 hwChannel)1762 Std_ReturnType Emios_Icu_Ip_ValidateSignalMeasureWithoutInterrupt
1763 (
1764     uint8 instance,
1765     uint8 hwChannel
1766 )
1767 {
1768     /*return ICU signal property without using interrupt*/
1769     return (eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt)?(Std_ReturnType)E_OK:(Std_ReturnType)E_NOT_OK;
1770 }
1771 #endif /* ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))*/
1772 
1773 #define ICU_STOP_SEC_CODE
1774 #include "Icu_MemMap.h"
1775 
1776 #endif  /* EMIOS_ICU_IP_USED */
1777 
1778 #ifdef __cplusplus
1779 }
1780 #endif
1781 
1782 /** @} */
1783