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Searched refs:RST_CTL1_PSCCTL1 (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_reset.h40 #define RST_CTL1_PSCCTL1 4 macro
84 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
85 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
86 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
87 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
88 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
89 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
90 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
91 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
92 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
[all …]
Dfsl_reset.c74 case RST_CTL1_PSCCTL1: in RESET_SetPeripheralReset()
134 case RST_CTL1_PSCCTL1: in RESET_ClearPeripheralReset()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_reset.h40 #define RST_CTL1_PSCCTL1 4 macro
84 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
85 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
86 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
87 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
88 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
89 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
90 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
91 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
92 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
[all …]
Dfsl_reset.c74 case RST_CTL1_PSCCTL1: in RESET_SetPeripheralReset()
134 case RST_CTL1_PSCCTL1: in RESET_ClearPeripheralReset()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_reset.h40 #define RST_CTL1_PSCCTL1 4 macro
99 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
100 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
101 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
102 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
103 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
104 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
105 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
106 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
107 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
[all …]
Dfsl_reset.c74 case RST_CTL1_PSCCTL1: in RESET_SetPeripheralReset()
134 case RST_CTL1_PSCCTL1: in RESET_ClearPeripheralReset()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_reset.h40 #define RST_CTL1_PSCCTL1 4 macro
99 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
100 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
101 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
102 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
103 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
104 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
105 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
106 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
107 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
[all …]
Dfsl_reset.c74 case RST_CTL1_PSCCTL1: in RESET_SetPeripheralReset()
134 case RST_CTL1_PSCCTL1: in RESET_ClearPeripheralReset()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_reset.h40 #define RST_CTL1_PSCCTL1 4 macro
99 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
100 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
101 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
102 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
103 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
104 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
105 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
106 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
107 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
[all …]
Dfsl_reset.c74 case RST_CTL1_PSCCTL1: in RESET_SetPeripheralReset()
134 case RST_CTL1_PSCCTL1: in RESET_ClearPeripheralReset()