1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020, NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_RESET_H_ 10 #define _FSL_RESET_H_ 11 12 #include <assert.h> 13 #include <stdbool.h> 14 #include <stdint.h> 15 #include <string.h> 16 #include "fsl_device_registers.h" 17 18 /*! 19 * @addtogroup reset 20 * @{ 21 */ 22 23 /******************************************************************************* 24 * Definitions 25 ******************************************************************************/ 26 27 /*! @name Driver version */ 28 /*@{*/ 29 /*! @brief reset driver version 2.0.1. */ 30 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 31 /*@}*/ 32 33 /*! 34 * @brief Reset control registers index 35 */ 36 #define RST_CTL0_PSCCTL0 0 37 #define RST_CTL0_PSCCTL1 1 38 #define RST_CTL0_PSCCTL2 2 39 #define RST_CTL1_PSCCTL0 3 40 #define RST_CTL1_PSCCTL1 4 41 #define RST_CTL1_PSCCTL2 5 42 /*! 43 * @brief Enumeration for peripheral reset control bits 44 * 45 * Defines the enumeration for peripheral reset control bits in RSTCLTx registers 46 */ 47 typedef enum _RSTCTL_RSTn 48 { 49 kDSP_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 1U, /**< DSP reset control */ 50 kAXI_SWITCH_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 3U, /**< AXI Switch reset control */ 51 kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U, /**< POWERQUAD reset control */ 52 kCASPER_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 9U, /**< CASPER reset control */ 53 kHASHCRYPT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 10U, /**< HASHCRYPT reset control */ 54 kPUF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 11U, /**< Physical unclonable function reset control */ 55 kRNG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 12U, /**< Random number generator (RNG) reset control */ 56 kFLEXSPI0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 16U, /**< FLEXSPI0/OTFAD reset control */ 57 kFLEXSPI1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 18U, /**< FLEXSPI1 reset control */ 58 kUSBHS_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 20U, /**< High speed USB PHY reset control */ 59 kUSBHS_DEVICE_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 21U, /**< High speed USB Device reset control */ 60 kUSBHS_HOST_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 22U, /**< High speed USB Host reset control */ 61 kUSBHS_SRAM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 23U, /**< High speed USB SRAM reset control */ 62 kSCT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 24U, /**< Standard ctimers reset control */ 63 kGPU_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 26U, /**< GPU reset control */ 64 kDISP_CTRL_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 27U, /**< Display controller reset control */ 65 kMIPI_DSI_CTRL_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 28U, /**< MIPI DSI controller reset control */ 66 kMIPI_DSI_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 29U, /**< MIPI DSI PHY reset control */ 67 kSMART_DMA_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 30U, /**< Smart DMA reset control */ 68 69 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */ 70 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */ 71 kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset control. */ 72 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */ 73 kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */ 74 75 kUTICK0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 0U, /**< Micro-tick timer reset control */ 76 kWWDT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 1U, /**< Windowed Watchdog timer 0 reset control */ 77 78 kFC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U, /**< Flexcomm Interface 0 reset control */ 79 kFC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U, /**< Flexcomm Interface 1 reset control */ 80 kFC2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U, /**< Flexcomm Interface 2 reset control */ 81 kFC3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U, /**< Flexcomm Interface 3 reset control */ 82 kFC4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 12U, /**< Flexcomm Interface 4 reset control */ 83 kFC5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 13U, /**< Flexcomm Interface 5 reset control */ 84 kFC6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 14U, /**< Flexcomm Interface 6 reset control */ 85 kFC7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 15U, /**< Flexcomm Interface 7 reset control */ 86 kFC8_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 16U, /**< Flexcomm Interface 8 reset control */ 87 kFC9_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 17U, /**< Flexcomm Interface 9 reset control */ 88 kFC10_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 18U, /**< Flexcomm Interface 10 reset control */ 89 kFC11_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 19U, /**< Flexcomm Interface 11 reset control */ 90 kFC12_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 20U, /**< Flexcomm Interface 12 reset control */ 91 kFC13_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 21U, /**< Flexcomm Interface 13 reset control */ 92 kFC14_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 22U, /**< Flexcomm Interface 14 reset control */ 93 kFC15_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 23U, /**< Flexcomm Interface 15 reset control */ 94 kDMIC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U, /**< Digital microphone interface reset control */ 95 kFC16_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 25U, /**< Flexcomm Interface 16 reset control */ 96 kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U, /**< Osevent Timer reset control */ 97 kFLEXIO_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 29U, /**< FlexIO reset control */ 98 99 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */ 100 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */ 101 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */ 102 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */ 103 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */ 104 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */ 105 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */ 106 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */ 107 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */ 108 kDMAC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 23U, /**< DMA Controller 0 reset control */ 109 kDMAC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 24U, /**< DMA Controller 1 reset control */ 110 kMU_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 28U, /**< Message Unit reset control */ 111 kSEMA_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 29U, /**< Semaphore reset control */ 112 kFREQME_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 31U, /**< Frequency Measure reset control */ 113 114 kCT32B0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 0U, /**< CT32B0 reset control */ 115 kCT32B1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 1U, /**< CT32B1 reset control */ 116 kCT32B2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 2U, /**< CT32B3 reset control */ 117 kCT32B3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 3U, /**< CT32B4 reset control */ 118 kCT32B4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 4U, /**< CT32B4 reset control */ 119 kMRT0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 8U, /**< Multi-rate timer (MRT) reset control */ 120 kWWDT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 10U, /**< Windowed Watchdog timer 1 reset control */ 121 kI3C0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 16U, /**< I3C0 reset control */ 122 kI3C1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 17U, /**< I3C1 reset control */ 123 kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 30U, /**< GPIO Pin interrupt reset control */ 124 kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U, /**< Peripheral input muxes reset control */ 125 } RSTCTL_RSTn_t; 126 127 /** Array initializers with peripheral reset bits **/ 128 #define ADC_RSTS \ 129 { \ 130 kADC0_RST_SHIFT_RSTn \ 131 } /* Reset bits for ADC peripheral */ 132 #define CASPER_RSTS \ 133 { \ 134 kCASPER_RST_SHIFT_RSTn \ 135 } /* Reset bits for Casper peripheral */ 136 #define CRC_RSTS \ 137 { \ 138 kCRC_RST_SHIFT_RSTn \ 139 } /* Reset bits for CRC peripheral */ 140 #define CTIMER_RSTS \ 141 { \ 142 kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ 143 kCT32B4_RST_SHIFT_RSTn \ 144 } /* Reset bits for TIMER peripheral */ 145 #define DCNANO_RSTS \ 146 { \ 147 kDISP_CTRL_RST_SHIFT_RSTn \ 148 } /* Reset bits for CRC peripheral */ 149 #define MIPI_DSI_RSTS \ 150 { \ 151 kMIPI_DSI_CTRL_RST_SHIFT_RSTn \ 152 } /* Reset bits for CRC peripheral */ 153 #define DMA_RSTS_N \ 154 { \ 155 kDMAC0_RST_SHIFT_RSTn, kDMAC1_RST_SHIFT_RSTn \ 156 } /* Reset bits for DMA peripheral */ 157 #define DMIC_RSTS \ 158 { \ 159 kDMIC_RST_SHIFT_RSTn \ 160 } /* Reset bits for ADC peripheral */ 161 #define FLEXCOMM_RSTS \ 162 { \ 163 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ 164 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, \ 165 kFC10_RST_SHIFT_RSTn, kFC11_RST_SHIFT_RSTn, kFC12_RST_SHIFT_RSTn, kFC13_RST_SHIFT_RSTn, \ 166 kFC14_RST_SHIFT_RSTn, kFC15_RST_SHIFT_RSTn, kFC16_RST_SHIFT_RSTn \ 167 } /* Reset bits for FLEXCOMM peripheral */ 168 #define FLEXIO_RSTS \ 169 { \ 170 kFLEXIO_RST_SHIFT_RSTn \ 171 } /* Resets bits for FLEXIO peripheral */ 172 #define FLEXSPI_RSTS \ 173 { \ 174 kFLEXSPI0_RST_SHIFT_RSTn, kFLEXSPI1_RST_SHIFT_RSTn \ 175 } /* Resets bits for FLEXSPI peripheral */ 176 #define GPIO_RSTS_N \ 177 { \ 178 kHSGPIO0_RST_SHIFT_RSTn, kHSGPIO1_RST_SHIFT_RSTn, kHSGPIO2_RST_SHIFT_RSTn, kHSGPIO3_RST_SHIFT_RSTn, \ 179 kHSGPIO4_RST_SHIFT_RSTn, kHSGPIO5_RST_SHIFT_RSTn, kHSGPIO6_RST_SHIFT_RSTn, kHSGPIO7_RST_SHIFT_RSTn \ 180 } /* Reset bits for GPIO peripheral */ 181 #define HASHCRYPT_RSTS \ 182 { \ 183 kHASHCRYPT_RST_SHIFT_RSTn \ 184 } /* Reset bits for Hashcrypt peripheral */ 185 #define I3C_RSTS \ 186 { \ 187 kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \ 188 } /* Reset bits for I3C peripheral */ 189 #define INPUTMUX_RSTS \ 190 { \ 191 kINPUTMUX_RST_SHIFT_RSTn \ 192 } /* Reset bits for INPUTMUX peripheral */ 193 #define MRT_RSTS \ 194 { \ 195 kMRT0_RST_SHIFT_RSTn \ 196 } /* Reset bits for MRT peripheral */ 197 #define MU_RSTS \ 198 { \ 199 kMU_RST_SHIFT_RSTn \ 200 } /* Reset bits for MU peripheral */ 201 #define OSTIMER_RSTS \ 202 { \ 203 kOSEVENT_TIMER_RST_SHIFT_RSTn \ 204 } /* Reset bits for OSTIMER peripheral */ 205 #define PINT_RSTS \ 206 { \ 207 kPINT_RST_SHIFT_RSTn \ 208 } /* Reset bits for PINT peripheral */ 209 #define POWERQUAD_RSTS \ 210 { \ 211 kPOWERQUAD_RST_SHIFT_RSTn \ 212 } /* Reset bits for Powerquad peripheral */ 213 #define PUF_RSTS \ 214 { \ 215 kPUF_RST_SHIFT_RSTn \ 216 } /* Reset bits for PUF peripheral */ 217 #define SCT_RSTS \ 218 { \ 219 kSCT_RST_SHIFT_RSTn \ 220 } /* Reset bits for SCT peripheral */ 221 #define SEMA42_RSTS \ 222 { \ 223 kSEMA_RST_SHIFT_RSTn \ 224 } /* Reset bits for SEMA42 peripheral */ 225 #define TRNG_RSTS \ 226 { \ 227 kRNG_RST_SHIFT_RSTn \ 228 } /* Reset bits for TRNG peripheral */ 229 #define USDHC_RSTS \ 230 { \ 231 kSDIO0_RST_SHIFT_RSTn, kSDIO1_RST_SHIFT_RSTn \ 232 } /* Reset bits for USDHC peripheral */ 233 #define UTICK_RSTS \ 234 { \ 235 kUTICK0_RST_SHIFT_RSTn \ 236 } /* Reset bits for UTICK peripheral */ 237 #define WWDT_RSTS \ 238 { \ 239 kWWDT0_RST_SHIFT_RSTn, kWWDT1_RST_SHIFT_RSTn \ 240 } /* Reset bits for WWDT peripheral */ 241 242 /*! 243 * @brief IP reset handle 244 */ 245 typedef RSTCTL_RSTn_t reset_ip_name_t; 246 247 /******************************************************************************* 248 * API 249 ******************************************************************************/ 250 #if defined(__cplusplus) 251 extern "C" { 252 #endif 253 254 /*! 255 * @brief Assert reset to peripheral. 256 * 257 * Asserts reset signal to specified peripheral module. 258 * 259 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register 260 * and reset bit position in the reset register. 261 */ 262 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 263 264 /*! 265 * @brief Clear reset to peripheral. 266 * 267 * Clears reset signal to specified peripheral module, allows it to operate. 268 * 269 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register 270 * and reset bit position in the reset register. 271 */ 272 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 273 274 /*! 275 * @brief Reset peripheral module. 276 * 277 * Reset peripheral module. 278 * 279 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 280 * and reset bit position in the reset register. 281 */ 282 void RESET_PeripheralReset(reset_ip_name_t peripheral); 283 284 #if defined(__cplusplus) 285 } 286 #endif 287 288 /*! @} */ 289 290 #endif /* _FSL_RESET_H_ */ 291
