Searched refs:RST_CTL0_PSCCTL1 (Results 1 – 10 of 10) sorted by relevance
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/ |
| D | fsl_reset.h | 37 #define RST_CTL0_PSCCTL1 1 macro
62 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
63 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
64 …kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset cont…
65 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
66 … kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
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| D | fsl_reset.c | 56 case RST_CTL0_PSCCTL1: in RESET_SetPeripheralReset()
116 case RST_CTL0_PSCCTL1: in RESET_ClearPeripheralReset()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/ |
| D | fsl_reset.h | 37 #define RST_CTL0_PSCCTL1 1 macro
62 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
63 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
64 …kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset cont…
65 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
66 … kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
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| D | fsl_reset.c | 56 case RST_CTL0_PSCCTL1: in RESET_SetPeripheralReset()
116 case RST_CTL0_PSCCTL1: in RESET_ClearPeripheralReset()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/ |
| D | fsl_reset.h | 37 #define RST_CTL0_PSCCTL1 1 macro
69 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
70 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
71 …kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset cont…
72 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
73 … kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
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| D | fsl_reset.c | 56 case RST_CTL0_PSCCTL1: in RESET_SetPeripheralReset()
116 case RST_CTL0_PSCCTL1: in RESET_ClearPeripheralReset()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/ |
| D | fsl_reset.h | 37 #define RST_CTL0_PSCCTL1 1 macro
69 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
70 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
71 …kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset cont…
72 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
73 … kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
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| D | fsl_reset.c | 56 case RST_CTL0_PSCCTL1: in RESET_SetPeripheralReset()
116 case RST_CTL0_PSCCTL1: in RESET_ClearPeripheralReset()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/ |
| D | fsl_reset.h | 37 #define RST_CTL0_PSCCTL1 1 macro
69 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
70 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
71 …kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset cont…
72 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
73 … kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
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| D | fsl_reset.c | 56 case RST_CTL0_PSCCTL1: in RESET_SetPeripheralReset()
116 case RST_CTL0_PSCCTL1: in RESET_ClearPeripheralReset()
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